diff --git a/coupledL2 b/coupledL2
index cbd1d461fd7d5e002c10e7cc298bb2b82f4dbf90..e175f13c8ab7f37aef3a6bd5ab0256b93b57405a 160000
--- a/coupledL2
+++ b/coupledL2
@@ -1 +1 @@
-Subproject commit cbd1d461fd7d5e002c10e7cc298bb2b82f4dbf90
+Subproject commit e175f13c8ab7f37aef3a6bd5ab0256b93b57405a
diff --git a/src/main/scala/xiangshan/XSTile.scala b/src/main/scala/xiangshan/XSTile.scala
index ee03ec468c2221f03bd0167f598db5f6c05d5833..7986c8e929e1fa536536d653a355c24ca7242023 100644
--- a/src/main/scala/xiangshan/XSTile.scala
+++ b/src/main/scala/xiangshan/XSTile.scala
@@ -96,7 +96,10 @@ class XSTile()(implicit p: Parameters) extends LazyModule
   private val misc = LazyModule(new XSTileMisc())
   private val l2cache = coreParams.L2CacheParamsOpt.map(l2param =>
     LazyModule(new CoupledL2()(new Config((_, _, _) => {
-      case L2ParamKey => l2param.copy(hartIds = Seq(p(XSCoreParamsKey).HartId))
+      case L2ParamKey => l2param.copy(
+        hartIds = Seq(p(XSCoreParamsKey).HartId),
+        FPGAPlatform = debugOpts.FPGAPlatform
+      )
     })))
   )