From 77fd5074eb5cf3758de5e4343dcbfab0bfa9224f Mon Sep 17 00:00:00 2001
From: Haojin Tang <tanghaojin@outlook.com>
Date: Tue, 30 May 2023 11:18:09 +0800
Subject: [PATCH] top-down: fix sq full condition

---
 src/main/scala/xiangshan/backend/dispatch/Dispatch.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala b/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
index 394088935..d3da75799 100644
--- a/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
+++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
@@ -318,7 +318,7 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasPerfEvents {
     val headIsSt  = io.robHead.ctrl.fuType === stu && io.robHeadNotReady || !io.sqCanAccept
     val headIsAmo = io.robHead.ctrl.fuType === mou && io.robHeadNotReady
     val headIsLs  = headIsLd || headIsSt
-    val robSqFull = io.robFull || io.sqCanAccept
+    val robSqFull = io.robFull || !io.sqCanAccept
 
     import TopDownCounters._
     update := MuxCase(OtherCoreStall.id.U, Seq(
-- 
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