diff --git a/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala b/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
index 394088935ca0ab9639889d9948f049d606b1c9c1..d3da75799af03fec2fed3e9fe711a4bce0417208 100644
--- a/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
+++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
@@ -318,7 +318,7 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasPerfEvents {
     val headIsSt  = io.robHead.ctrl.fuType === stu && io.robHeadNotReady || !io.sqCanAccept
     val headIsAmo = io.robHead.ctrl.fuType === mou && io.robHeadNotReady
     val headIsLs  = headIsLd || headIsSt
-    val robSqFull = io.robFull || io.sqCanAccept
+    val robSqFull = io.robFull || !io.sqCanAccept
 
     import TopDownCounters._
     update := MuxCase(OtherCoreStall.id.U, Seq(