diff --git a/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala b/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala
index fbe27ed88b13ea822da6ea0647fe6221e00d19da..654f8b3264f58c3a309743127e1d4f3608e33ab5 100644
--- a/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala
+++ b/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala
@@ -41,7 +41,7 @@ class Radix2Divider(len: Int) extends AbstractDivider(len) {
   val uopReg = RegEnable(uop, newReq)
 
   val cnt = Counter(len)
-  when (newReq) {
+  when (newReq && !io.in.bits.uop.roqIdx.needFlush(io.redirectIn)) {
     state := s_log2
   } .elsewhen (state === s_log2) {
     // `canSkipShift` is calculated as following:
diff --git a/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala b/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala
index c981982d5225811defbf5c95779275f9b14db5ec..ea8fd75724cc3525e1bd41378cd4459b4533f363 100644
--- a/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala
+++ b/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala
@@ -37,7 +37,9 @@ class SRT4Divider(len: Int) extends AbstractDivider(len) {
 
   switch(state){
     is(s_idle){
-      when(io.in.fire()){ state := Mux(divZero, s_finish, s_lzd) }
+      when (io.in.fire() && !io.in.bits.uop.roqIdx.needFlush(io.redirectIn)) {
+        state := Mux(divZero, s_finish, s_lzd)
+      }
     }
     is(s_lzd){ // leading zero detection
       state := s_normlize