From 70083794d00d215233179d6e163dece2d6e043e3 Mon Sep 17 00:00:00 2001
From: Lemover <1773908404@qq.com>
Date: Wed, 30 Mar 2022 14:45:02 +0800
Subject: [PATCH] sram-tlb: change SRAMTemplate & when tlb refill, just resp a
 miss/fast_miss (#1504)

* bump huancun

* sram: fix sram, keep rdata when w.valid

* tlb: when refill, just return miss at next cycle, rm unused assert
---
 src/main/scala/utils/SRAMTemplate.scala      | 2 +-
 src/main/scala/xiangshan/cache/mmu/TLB.scala | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/utils/SRAMTemplate.scala b/src/main/scala/utils/SRAMTemplate.scala
index 77ffc51d8..4882e78c3 100644
--- a/src/main/scala/utils/SRAMTemplate.scala
+++ b/src/main/scala/utils/SRAMTemplate.scala
@@ -134,7 +134,7 @@ class SRAMTemplate[T <: Data](gen: T, set: Int, way: Int = 1,
     else VecInit((0 until way).map(_ => LFSR64().asTypeOf(wordType)))
   val bypass_mask = need_bypass(io.w.req.valid, io.w.req.bits.setIdx, io.w.req.bits.waymask.getOrElse("b1".U), io.r.req.valid, io.r.req.bits.setIdx)
   val mem_rdata = {
-    if (singlePort) raw_rdata
+    if (singlePort) Mux(RegNext(io.w.req.valid, false.B), RegNext(raw_rdata), raw_rdata)
     else VecInit(bypass_mask.asBools.zip(raw_rdata).zip(bypass_wdata).map {
       case ((m, r), w) => Mux(m, w, r)
     })
diff --git a/src/main/scala/xiangshan/cache/mmu/TLB.scala b/src/main/scala/xiangshan/cache/mmu/TLB.scala
index 3bbc1eb45..46b146e4c 100644
--- a/src/main/scala/xiangshan/cache/mmu/TLB.scala
+++ b/src/main/scala/xiangshan/cache/mmu/TLB.scala
@@ -113,7 +113,7 @@ class TLB(Width: Int, q: TLBParameters)(implicit p: Parameters) extends TlbModul
   def TLBNormalRead(i: Int) = {
     val (n_hit_sameCycle, normal_hit, normal_ppn, normal_perm) = normalPage.r_resp_apply(i)
     val (s_hit_sameCycle, super_hit, super_ppn, super_perm) = superPage.r_resp_apply(i)
-    assert(!(normal_hit && super_hit && vmEnable && RegNext(req(i).valid, init = false.B)))
+    // assert(!(normal_hit && super_hit && vmEnable && RegNext(req(i).valid, init = false.B)))
 
     val hit = normal_hit || super_hit
     val hit_sameCycle = n_hit_sameCycle || s_hit_sameCycle
@@ -138,12 +138,12 @@ class TLB(Width: Int, q: TLBParameters)(implicit p: Parameters) extends TlbModul
 
     val paddr = Cat(ppn, offReg)
     val vaddr = SignExt(req(i).bits.vaddr, PAddrBits)
-
+    val refill_reg = RegNext(io.ptw.resp.valid)
     req(i).ready := resp(i).ready
     resp(i).valid := validReg
     resp(i).bits.paddr := Mux(vmEnable, paddr, if (!q.sameCycle) RegNext(vaddr) else vaddr)
-    resp(i).bits.miss := { if (q.missSameCycle) miss_sameCycle else miss }
-    resp(i).bits.fast_miss := fast_miss
+    resp(i).bits.miss := { if (q.missSameCycle) miss_sameCycle else (miss || refill_reg) }
+    resp(i).bits.fast_miss := fast_miss || refill_reg
     resp(i).bits.ptwBack := io.ptw.resp.fire()
 
     // for timing optimization, pmp check is divided into dynamic and static
-- 
GitLab