diff --git a/src/main/scala/xiangshan/decoupled-frontend/FrontendBundle.scala b/src/main/scala/xiangshan/decoupled-frontend/FrontendBundle.scala
index 8cc1df8c985cd2115eefea00a9900e60bedeb34b..b8a5b3b222ffe072bbb27bcf94dd2a369a0e8153 100644
--- a/src/main/scala/xiangshan/decoupled-frontend/FrontendBundle.scala
+++ b/src/main/scala/xiangshan/decoupled-frontend/FrontendBundle.scala
@@ -12,6 +12,12 @@ class FetchRequestBundle(implicit p: Parameters) extends XSBundle {
   val ftqIdx       = new FtqPtr
   val ftqOffset    = ValidUndirectioned(UInt(log2Ceil(32).W))
   val target       = UInt(VAddrBits.W)
+
+  override def toPrintable: Printable = {
+    p"[start] ${Hexadecimal(startAddr)} [pft] ${Hexadecimal(fallThruAddr)}" +
+    p"[tgt] ${Hexadecimal(target)} [ftqIdx] $ftqIdx [jmp] v:${ftqOffset.valid}" +
+    p" offset: ${ftqOffset.bits}\n"
+  }
 }
 
 class PredecodeWritebackBundle(implicit p:Parameters) extends XSBundle {
@@ -99,6 +105,11 @@ class BranchPredictionBundle(implicit p: Parameters) extends XSBundle with HasBP
   val meta = UInt(MaxMetaLength.W)
 
   val ftb_entry = new FTBEntry() // TODO: Send this entry to ftq
+
+  override def toPrintable: Printable = {
+    p"[pc] ${Hexadecimal(pc)} [pft] ${Hexadecimal(ftb_entry.pftAddr)}" +
+    p"[tgt] ${Hexadecimal(preds.target)} [hit] $hit\n"
+  }
 }
 
 class BranchPredictionResp(implicit p: Parameters) extends XSBundle with HasBPUConst {
diff --git a/src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala b/src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala
index 293bff0aa45156937f429c4cb9385033e875c58b..48ab47b258c1081c68d79f19a129f4e8a5c08f9b 100644
--- a/src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala
+++ b/src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala
@@ -222,7 +222,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
     VecInit(Seq.fill(PredictWidth)(s_invalid))
   }))
   
-  val f_to_send :: f_sent :: Nil = Enum(2)
+  val f_to_send :: f_sent :: f_wb :: Nil = Enum(3)
   val entry_fetch_status = RegInit(VecInit(Seq.fill(FtqSize)(f_sent)))
   
   when (enq_fire) {
@@ -264,6 +264,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   when (ifu_wb_valid) {
     val ifuWbIdx = pdWb.bits.ftqIdx.value
     commitStateQueue(ifuWbIdx) := VecInit(pds.map(_.valid))
+    entry_fetch_status(ifuWbIdx) := f_wb
   }
 
   // ****************************************************************
@@ -519,9 +520,10 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
     }
   }
 
-  val canDeq = Cat(commitStateQueue(commPtr.value).map(s => {
-    s === s_invalid || s === s_commited
-  })).andR()
+  val canDeq = entry_fetch_status(commPtr.value) === f_wb &&
+    Cat(commitStateQueue(commPtr.value).map(s => {
+      s === s_invalid || s === s_commited
+    })).andR()
   when(canDeq && commPtr =/= bpuPtr) {
     commPtr := commPtr + 1.U
   }
@@ -534,6 +536,15 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   io.toBpu.update := DontCare
   ftq_meta_1r_sram.io.ren(0) := false.B
   ftq_meta_1r_sram.io.raddr(0) := 0.U
+
+
+  // --------------------------- Debug --------------------------------
+  XSDebug(enq_fire, io.fromBpu.resp.bits.toPrintable)
+  XSDebug(io.toIfu.req.fire, p"fire to ifu " + io.toIfu.req.bits.toPrintable)
+  XSDebug(canDeq, p"deq! [ptr] $commPtr\n")
+  XSDebug(true.B, p"[bpuPtr] $bpuPtr, [ifuPtr] $ifuPtr, [commPtr] $commPtr\n")
+  XSDebug(true.B, p"[in] v:${io.fromBpu.resp.valid} r:${io.fromBpu.resp.ready} " +
+    p"[out] v:${io.toIfu.req.valid} r:${io.toIfu.req.ready}\n")
 }
 
 trait HasPerfDebug { this: Ftq =>