diff --git a/difftest b/difftest index 66e222ec4dcd828a3fae4aeea81122719197390f..a09bc12442ac53f6a774e5d0f7af5530bd03c6aa 160000 --- a/difftest +++ b/difftest @@ -1 +1 @@ -Subproject commit 66e222ec4dcd828a3fae4aeea81122719197390f +Subproject commit a09bc12442ac53f6a774e5d0f7af5530bd03c6aa diff --git a/src/main/scala/xiangshan/backend/decode/VecDecoder.scala b/src/main/scala/xiangshan/backend/decode/VecDecoder.scala index 3415333d3cb83ac94a2bc7729077985799167139..189ed35716a98ffd1960eb927cca2e4bad81a1e0 100644 --- a/src/main/scala/xiangshan/backend/decode/VecDecoder.scala +++ b/src/main/scala/xiangshan/backend/decode/VecDecoder.scala @@ -106,159 +106,165 @@ case class VST(src2: BitPat, fuOp: BitPat, strided: Boolean = false, indexed: Bo object VecDecoder extends DecodeConstants { val opivv: Array[(BitPat, XSDecodeBase)] = Array( - VADD_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.add, T, F, F), - VSUB_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.sub, T, F, F), + VADD_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vadd_vv, T, F, F), + VSUB_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vsub_vv, T, F, F), - VMINU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VMIN_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VMAXU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VMAX_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), + VMINU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vminu_vv, T, F, F), + VMIN_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vmin_vv, T, F, F), + VMAXU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vmaxu_vv, T, F, F), + VMAX_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vmax_vv, T, F, F), - VAND_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VOR_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VXOR_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), + VAND_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vand_vv, T, F, F), + VOR_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vor_vv, T, F, F), + VXOR_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vxor_vv, T, F, F), VRGATHER_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), VRGATHEREI16_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VADC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.adc, T, F, F), - VMADC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.madc, F, T, F), - VMADC_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.madc0, F, T, F), + VADC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.vadc_vvm, T, F, F), + VMADC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.vmadc_vvm, F, T, F), + VMADC_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vmadc_vv, F, T, F), - VSBC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), - VMSBC_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSBC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F), + VSBC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.vsbc_vvm, T, F, F), + VMSBC_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vmsbc_vvm, F, T, F), + VMSBC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.vmsbc_vv, F, T, F), - VMERGE_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), + VMERGE_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.vmerge_vvm, T, F, F), - VMSEQ_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSNE_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSLTU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSLT_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSLEU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSLE_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), + VMV_V_V -> OPIVV(SrcType.vp, FuType.vipu, VipuType.vmv_v_v, T, F, F), - VSLL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VSRL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VSRA_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VNSRL_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VNSRA_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), + VMSEQ_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vmseq_vv, F, T, F), + VMSNE_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vmsne_vv, F, T, F), + VMSLTU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vmsltu_vv, F, T, F), + VMSLT_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vmslt_vv, F, T, F), + VMSLEU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vmsleu_vv, F, T, F), + VMSLE_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vmsle_vv, F, T, F), - VSADDU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), - VSADD_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), - VSSUBU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), - VSSUB_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), + VSLL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vsll_vv, T, F, F), + VSRL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vsrl_vv, T, F, F), + VSRA_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vsra_vv, T, F, F), + VNSRL_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vnsrl_wv, T, F, F), + VNSRA_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vnsra_wv, T, F, F), + + VSADDU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vsaddu_vv, T, F, T), + VSADD_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vsadd_vv, T, F, T), + VSSUBU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vssubu_vv, T, F, T), + VSSUB_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vssub_vv, T, F, T), VSMUL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), - VSSRL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VSSRA_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), + VSSRL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vssrl_vv, T, F, F), + VSSRA_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vssra_vv, T, F, F), - VNCLIPU_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), - VNCLIP_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), + VNCLIPU_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vnclipu_wv, T, F, T), + VNCLIP_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.vnclip_wv, T, F, T), - VWREDSUMU_VS -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VWREDSUM_VS -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), + VWREDSUMU_VS -> OPIVV(SrcType.X, FuType.vipu, VipuType.vwredsumu_vs, T, F, F), + VWREDSUM_VS -> OPIVV(SrcType.X, FuType.vipu, VipuType.vwredsum_vs, T, F, F), ) val opivx: Array[(BitPat, XSDecodeBase)] = Array( - VADD_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.add, T, F, F), - VSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.sub, T, F, F), - VRSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.rsub, T, F, F), + VADD_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vadd_vv, T, F, F), + VSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vsub_vv, T, F, F), + VRSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vrsub_vv, T, F, F), - VMINU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VMIN_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VMAXU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VMAX_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), + VMINU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vminu_vv, T, F, F), + VMIN_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmin_vv, T, F, F), + VMAXU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmaxu_vv, T, F, F), + VMAX_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmax_vv, T, F, F), - VAND_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VOR_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VXOR_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), + VAND_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vand_vv, T, F, F), + VOR_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vor_vv, T, F, F), + VXOR_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vxor_vv, T, F, F), VRGATHER_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), VSLIDEUP_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), VSLIDEDOWN_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VADC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.adc, T, F, F), - VMADC_VXM -> OPIVX(SrcType.X, FuType.vipu, VipuType.madc, F, T, F), - VMADC_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.madc0, F, T, F), - VSBC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), - VMSBC_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSBC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F), - - VMERGE_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F), - - VMSEQ_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSNE_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSLTU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSLT_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSLEU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSLE_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSGTU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - VMSGT_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F), - - VSLL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VSRL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VSRA_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VNSRL_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VNSRA_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - - VSADDU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), - VSADD_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), - VSSUBU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), - VSSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), + VADC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.vadc_vvm, T, F, F), + VMADC_VXM -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmadc_vvm, F, T, F), + VMADC_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmadc_vv, F, T, F), + VSBC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.vsbc_vvm, T, F, F), + VMSBC_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmsbc_vvm, F, T, F), + VMSBC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.vmsbc_vv, F, T, F), + + VMERGE_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.vmerge_vvm, T, F, F), + + VMV_V_X -> OPIVX(SrcType.vp, FuType.vipu, VipuType.vmv_v_v, T, F, F), + + VMSEQ_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmseq_vv, F, T, F), + VMSNE_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmsne_vv, F, T, F), + VMSLTU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmsltu_vv, F, T, F), + VMSLT_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmslt_vv, F, T, F), + VMSLEU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmsleu_vv, F, T, F), + VMSLE_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmsle_vv, F, T, F), + VMSGTU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmsgtu_vv, F, T, F), + VMSGT_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vmsgt_vv, F, T, F), + + VSLL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vsll_vv, T, F, F), + VSRL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vsrl_vv, T, F, F), + VSRA_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vsra_vv, T, F, F), + VNSRL_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vnsrl_wv, T, F, F), + VNSRA_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vnsra_wv, T, F, F), + + VSADDU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vsaddu_vv, T, F, T), + VSADD_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vsadd_vv, T, F, T), + VSSUBU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vssubu_vv, T, F, T), + VSSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vssub_vv, T, F, T), VSMUL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), - VSSRL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), - VSSRA_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F), + VSSRL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vssrl_vv, T, F, F), + VSSRA_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vssra_vv, T, F, F), - VNCLIPU_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), - VNCLIP_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T), + VNCLIPU_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vnclipu_wv, T, F, T), + VNCLIP_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.vnclip_wv, T, F, T), ) val opivi: Array[(BitPat, XSDecodeBase)] = Array( - VADD_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.add, T, F, F, SelImm.IMM_OPIVIS), - VRSUB_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.rsub, T, F, F, SelImm.IMM_OPIVIS), + VADD_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vadd_vv, T, F, F, SelImm.IMM_OPIVIS), + VRSUB_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vrsub_vv, T, F, F, SelImm.IMM_OPIVIS), - VAND_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), - VOR_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), - VXOR_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), + VAND_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vand_vv, T, F, F, SelImm.IMM_OPIVIS), + VOR_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vor_vv, T, F, F, SelImm.IMM_OPIVIS), + VXOR_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vxor_vv, T, F, F, SelImm.IMM_OPIVIS), VRGATHER_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), VSLIDEUP_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), VSLIDEDOWN_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), - VADC_VIM -> OPIVI(SrcType.vp, FuType.vipu, VipuType.adc, T, F, F, SelImm.IMM_OPIVIS), - VMADC_VIM -> OPIVI(SrcType.X, FuType.vipu, VipuType.madc, T, F, F, SelImm.IMM_OPIVIS), - VMADC_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.madc0, T, F, F, SelImm.IMM_OPIVIS), + VADC_VIM -> OPIVI(SrcType.vp, FuType.vipu, VipuType.vadc_vvm, T, F, F, SelImm.IMM_OPIVIS), + VMADC_VIM -> OPIVI(SrcType.X, FuType.vipu, VipuType.vmadc_vvm, T, F, F, SelImm.IMM_OPIVIS), + VMADC_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vmadc_vv, T, F, F, SelImm.IMM_OPIVIS), - VMERGE_VIM -> OPIVI(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), + VMERGE_VIM -> OPIVI(SrcType.vp, FuType.vipu, VipuType.vmerge_vvm, T, F, F, SelImm.IMM_OPIVIS), + + VMV_V_I -> OPIVI(SrcType.vp, FuType.vipu, VipuType.vmv_v_v, T, F, F, SelImm.IMM_OPIVIS), - VMSEQ_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), - VMSNE_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), - VMSLEU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), - VMSLE_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), - VMSGTU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), - VMSGT_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS), + VMSEQ_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vmseq_vv, F, T, F, SelImm.IMM_OPIVIS), + VMSNE_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vmsne_vv, F, T, F, SelImm.IMM_OPIVIS), + VMSLEU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vmsleu_vv, F, T, F, SelImm.IMM_OPIVIS), + VMSLE_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vmsle_vv, F, T, F, SelImm.IMM_OPIVIS), + VMSGTU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vmsgtu_vv, F, T, F, SelImm.IMM_OPIVIS), + VMSGT_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vmsgt_vv, F, T, F, SelImm.IMM_OPIVIS), - VSLL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), - VSRL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), - VSRA_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), - VNSRL_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), - VNSRA_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), + VSLL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vsll_vv, T, F, F, SelImm.IMM_OPIVIU), + VSRL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vsrl_vv, T, F, F, SelImm.IMM_OPIVIU), + VSRA_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vsra_vv, T, F, F, SelImm.IMM_OPIVIU), + VNSRL_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vnsrl_wv, T, F, F, SelImm.IMM_OPIVIU), + VNSRA_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vnsra_wv, T, F, F, SelImm.IMM_OPIVIU), - VSADDU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIS), - VSADD_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIS), + VSADDU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vsaddu_vv, T, F, T, SelImm.IMM_OPIVIS), + VSADD_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vsadd_vv, T, F, T, SelImm.IMM_OPIVIS), - VSSRL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), - VSSRA_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU), + VSSRL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vssrl_vv, T, F, F, SelImm.IMM_OPIVIU), + VSSRA_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vssra_vv, T, F, F, SelImm.IMM_OPIVIU), - VNCLIPU_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIU), - VNCLIP_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIU), + VNCLIPU_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vnclipu_wv, T, F, T, SelImm.IMM_OPIVIU), + VNCLIP_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.vnclip_wv, T, F, T, SelImm.IMM_OPIVIU), VMV1R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), VMV2R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS), @@ -267,32 +273,32 @@ object VecDecoder extends DecodeConstants { ) val opmvv: Array[(BitPat, XSDecodeBase)] = Array( - VAADD_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VAADDU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VASUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VASUBU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), + VAADD_VV -> OPMVV(F, FuType.vipu, VipuType.vaadd_vv, F, T, F), + VAADDU_VV -> OPMVV(F, FuType.vipu, VipuType.vaaddu_vv, F, T, F), + VASUB_VV -> OPMVV(F, FuType.vipu, VipuType.vasub_vv, F, T, F), + VASUBU_VV -> OPMVV(F, FuType.vipu, VipuType.vasubu_vv, F, T, F), VCOMPRESS_VM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VCPOP_M -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F), + VCPOP_M -> OPMVV(F, FuType.vipu, VipuType.vcpop_m, T, F, F), VDIV_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), VDIVU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VFIRST_M -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F), - VID_V -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VIOTA_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), + VFIRST_M -> OPMVV(F, FuType.vipu, VipuType.vfirst_m, T, F, F), + VID_V -> OPMVV(F, FuType.vipu, VipuType.vid_v, F, T, F), + VIOTA_M -> OPMVV(F, FuType.vipu, VipuType.viota_m, F, T, F), // VMACC_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), VMADD_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), - VMAND_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VMANDN_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VMNAND_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VMNOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VMOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VMORN_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VMXNOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VMXOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VMSBF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VMSIF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VMSOF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), + VMAND_MM -> OPMVV(F, FuType.vipu, VipuType.vmand_mm, F, T, F), + VMANDN_MM -> OPMVV(F, FuType.vipu, VipuType.vmandn_mm, F, T, F), + VMNAND_MM -> OPMVV(F, FuType.vipu, VipuType.vmnand_mm, F, T, F), + VMNOR_MM -> OPMVV(F, FuType.vipu, VipuType.vmnor_mm, F, T, F), + VMOR_MM -> OPMVV(F, FuType.vipu, VipuType.vmor_mm, F, T, F), + VMORN_MM -> OPMVV(F, FuType.vipu, VipuType.vmorn_mm, F, T, F), + VMXNOR_MM -> OPMVV(F, FuType.vipu, VipuType.vmxnor_mm, F, T, F), + VMXOR_MM -> OPMVV(F, FuType.vipu, VipuType.vmxor_mm, F, T, F), + VMSBF_M -> OPMVV(F, FuType.vipu, VipuType.vmsbf_m, F, T, F), + VMSIF_M -> OPMVV(F, FuType.vipu, VipuType.vmsif_m, F, T, F), + VMSOF_M -> OPMVV(F, FuType.vipu, VipuType.vmsof_m, F, T, F), VMUL_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), VMULH_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), VMULHSU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), @@ -301,43 +307,43 @@ object VecDecoder extends DecodeConstants { VMV_X_S -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F), VNMSAC_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), VNMSUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VREDAND_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VREDMAX_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VREDMAXU_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VREDMIN_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VREDMINU_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VREDOR_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VREDSUM_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VREDXOR_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), + VREDAND_VS -> OPMVV(F, FuType.vipu, VipuType.vredand_vs, F, T, F), + VREDMAX_VS -> OPMVV(F, FuType.vipu, VipuType.vredmax_vs, F, T, F), + VREDMAXU_VS -> OPMVV(F, FuType.vipu, VipuType.vredmaxu_vs, F, T, F), + VREDMIN_VS -> OPMVV(F, FuType.vipu, VipuType.vredmin_vs, F, T, F), + VREDMINU_VS -> OPMVV(F, FuType.vipu, VipuType.vredminu_vs, F, T, F), + VREDOR_VS -> OPMVV(F, FuType.vipu, VipuType.vredor_vs, F, T, F), + VREDSUM_VS -> OPMVV(F, FuType.vipu, VipuType.vredsum_vs, F, T, F), + VREDXOR_VS -> OPMVV(F, FuType.vipu, VipuType.vredxor_vs, F, T, F), VREM_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), VREMU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VSEXT_VF2 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VSEXT_VF4 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VSEXT_VF8 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VZEXT_VF2 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VZEXT_VF4 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VZEXT_VF8 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VWADD_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VWADD_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VWADDU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VWADDU_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), + VSEXT_VF2 -> OPMVV(F, FuType.vipu, VipuType.vsext_vf2, F, T, F), + VSEXT_VF4 -> OPMVV(F, FuType.vipu, VipuType.vsext_vf4, F, T, F), + VSEXT_VF8 -> OPMVV(F, FuType.vipu, VipuType.vsext_vf8, F, T, F), + VZEXT_VF2 -> OPMVV(F, FuType.vipu, VipuType.vzext_vf2, F, T, F), + VZEXT_VF4 -> OPMVV(F, FuType.vipu, VipuType.vzext_vf4, F, T, F), + VZEXT_VF8 -> OPMVV(F, FuType.vipu, VipuType.vzext_vf8, F, T, F), + VWADD_VV -> OPMVV(F, FuType.vipu, VipuType.vwadd_vv, F, T, F), + VWADD_WV -> OPMVV(F, FuType.vipu, VipuType.vwadd_wv, F, T, F), + VWADDU_VV -> OPMVV(F, FuType.vipu, VipuType.vwaddu_vv, F, T, F), + VWADDU_WV -> OPMVV(F, FuType.vipu, VipuType.vwaddu_wv, F, T, F), VWMACC_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), VWMACCSU_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), VWMACCU_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F), VWMUL_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), VWMULSU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), VWMULU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VWSUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), - VWSUB_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), + VWSUB_VV -> OPMVV(F, FuType.vipu, VipuType.vwsub_vv, F, T, F), + VWSUB_WV -> OPMVV(F, FuType.vipu, VipuType.vwsub_wv, F, T, F), VWSUBU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), VWSUBU_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F), ) val opmvx: Array[(BitPat, XSDecodeBase)] = Array( - VAADD_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), - VAADDU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), - VASUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), - VASUBU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), + VAADD_VX -> OPMVX(F, FuType.vipu, VipuType.vaadd_vv, F, T, F), + VAADDU_VX -> OPMVX(F, FuType.vipu, VipuType.vaaddu_vv, F, T, F), + VASUB_VX -> OPMVX(F, FuType.vipu, VipuType.vasub_vv, F, T, F), + VASUBU_VX -> OPMVX(F, FuType.vipu, VipuType.vasubu_vv, F, T, F), VDIV_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), VDIVU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), VMACC_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), @@ -346,7 +352,7 @@ object VecDecoder extends DecodeConstants { VMULH_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), VMULHSU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), VMULHU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), - VMV_S_X -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, UopDivType.VEC_MV), + VMV_S_X -> OPMVX(F, FuType.vipu, VipuType.vmv_s_x, F, T, F, UopDivType.VEC_MV), VNMSAC_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), VNMSUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), @@ -355,10 +361,10 @@ object VecDecoder extends DecodeConstants { VSLIDE1DOWN_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), VSLIDE1UP_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), - VWADD_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), - VWADD_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), - VWADDU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), - VWADDU_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), + VWADD_VX -> OPMVX(F, FuType.vipu, VipuType.vwadd_vv, F, T, F), + VWADD_WX -> OPMVX(F, FuType.vipu, VipuType.vwadd_wv, F, T, F), + VWADDU_VX -> OPMVX(F, FuType.vipu, VipuType.vwaddu_vv, F, T, F), + VWADDU_WX -> OPMVX(F, FuType.vipu, VipuType.vwaddu_wv, F, T, F), // OutOfMemoryError VWMACC_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F), @@ -370,8 +376,8 @@ object VecDecoder extends DecodeConstants { VWMULSU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), // Ok VWMULU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), - VWSUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), - VWSUB_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), + VWSUB_VX -> OPMVX(F, FuType.vipu, VipuType.vwsub_vv, F, T, F), + VWSUB_WX -> OPMVX(F, FuType.vipu, VipuType.vwsub_wv, F, T, F), VWSUBU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), VWSUBU_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F), ) diff --git a/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala b/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala index 253cfcd93b5ea9455c742e58e85b85378d802bbc..36961204c60a1bcdd5f6b670785a8f2887d79779 100644 --- a/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala +++ b/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala @@ -23,7 +23,6 @@ import chisel3._ import chisel3.util._ import utils._ import utility._ -import yunsuan.vector.VectorIntAdder import yunsuan.vector.alu.{VAluOpcode, VIAlu} import yunsuan.{VectorElementFormat, VipuType} import xiangshan.{SelImm, SrcType, UopDivType, XSCoreParamsKey, XSModule} @@ -107,9 +106,124 @@ class VIAluDecoder (implicit p: Parameters) extends XSModule { // ) // val opcode :: srcType1 :: srcType2 :: vdType :: Nil = ListLookup(Cat(io.in.fuOpType, io.in.sew), DecodeDefault, DecodeTable) -// u 00 s 01 f 10 mask 1111 + // u 00 s 01 f 10 mask 1111 + val uSew = Cat(0.U(2.W), io.in.sew) + val uSew2 = Cat(0.U(2.W), (io.in.sew+1.U)) + val uSewf2 = Cat(0.U(2.W), (io.in.sew-1.U)) + val uSewf4 = Cat(0.U(2.W), (io.in.sew-2.U)) + val uSewf8 = Cat(0.U(2.W), (io.in.sew-3.U)) + val sSew = Cat(1.U(2.W), io.in.sew) + val sSew2 = Cat(1.U(2.W), (io.in.sew+1.U)) + val sSewf2 = Cat(1.U(2.W), (io.in.sew - 1.U)) + val sSewf4 = Cat(1.U(2.W), (io.in.sew - 2.U)) + val sSewf8 = Cat(1.U(2.W), (io.in.sew - 3.U)) + val mask = "b1111".U(4.W) + val out = LookupTree(io.in.fuOpType, List( - VipuType.add -> Cat(VAluOpcode.vadd, Cat(1.U(2.W), io.in.sew), Cat(1.U(2.W), io.in.sew), Cat(1.U(2.W), io.in.sew)).asUInt() + // --------------------- opcode srcType(0) (1) vdType + VipuType.vadd_vv -> Cat(VAluOpcode.vadd, uSew, uSew, uSew).asUInt(), + VipuType.vsub_vv -> Cat(VAluOpcode.vsub, uSew, uSew, uSew).asUInt(), + VipuType.vrsub_vv -> Cat(VAluOpcode.vsub, uSew, uSew, uSew).asUInt(), + + VipuType.vwaddu_vv -> Cat(VAluOpcode.vadd, uSew, uSew, uSew2).asUInt(), + VipuType.vwsubu_vv -> Cat(VAluOpcode.vsub, uSew, uSew, uSew2).asUInt(), + VipuType.vwadd_vv -> Cat(VAluOpcode.vadd, sSew, sSew, sSew2).asUInt(), + VipuType.vwsub_vv -> Cat(VAluOpcode.vsub, sSew, sSew, sSew2).asUInt(), + VipuType.vwaddu_wv -> Cat(VAluOpcode.vadd, uSew2, uSew, uSew2).asUInt(), + VipuType.vwsubu_wv -> Cat(VAluOpcode.vsub, uSew2, uSew, uSew2).asUInt(), + VipuType.vwadd_wv -> Cat(VAluOpcode.vadd, sSew2, sSew, sSew2).asUInt(), + VipuType.vwsub_wv -> Cat(VAluOpcode.vsub, sSew2, sSew, sSew2).asUInt(), + + VipuType.vzext_vf2 -> Cat(VAluOpcode.vext, uSewf2, uSewf2, uSew).asUInt(), + VipuType.vsext_vf2 -> Cat(VAluOpcode.vext, sSewf2, sSewf2, sSew).asUInt(), + VipuType.vzext_vf4 -> Cat(VAluOpcode.vext, uSewf4, uSewf4, uSew).asUInt(), + VipuType.vsext_vf4 -> Cat(VAluOpcode.vext, sSewf4, sSewf4, sSew).asUInt(), + VipuType.vzext_vf8 -> Cat(VAluOpcode.vext, uSewf8, uSewf8, uSew).asUInt(), + VipuType.vsext_vf8 -> Cat(VAluOpcode.vext, sSewf8, sSewf8, sSew).asUInt(), + + VipuType.vadc_vvm -> Cat(VAluOpcode.vadc, uSew, uSew, uSew).asUInt(), + VipuType.vmadc_vvm -> Cat(VAluOpcode.vmadc, uSew, uSew, mask).asUInt(), + VipuType.vmadc_vv -> Cat(VAluOpcode.vmadc, uSew, uSew, mask).asUInt(), + + VipuType.vsbc_vvm -> Cat(VAluOpcode.vsbc, uSew, uSew, uSew).asUInt(), + VipuType.vmsbc_vvm -> Cat(VAluOpcode.vsbc, uSew, uSew, mask).asUInt(), + VipuType.vmsbc_vv -> Cat(VAluOpcode.vsbc, uSew, uSew, mask).asUInt(), + + VipuType.vand_vv -> Cat(VAluOpcode.vand, uSew, uSew, uSew).asUInt(), + VipuType.vor_vv -> Cat(VAluOpcode.vor, uSew, uSew, uSew).asUInt(), + VipuType.vxor_vv -> Cat(VAluOpcode.vxor, uSew, uSew, uSew).asUInt(), + + VipuType.vsll_vv -> Cat(VAluOpcode.vsll, uSew, uSew, uSew).asUInt(), + VipuType.vsrl_vv -> Cat(VAluOpcode.vsrl, uSew, uSew, uSew).asUInt(), + VipuType.vsra_vv -> Cat(VAluOpcode.vsra, uSew, uSew, uSew).asUInt(), + + VipuType.vnsrl_wv -> Cat(VAluOpcode.vsrl, uSew2, uSew, uSew).asUInt(), + VipuType.vnsra_wv -> Cat(VAluOpcode.vsra, uSew2, uSew, uSew).asUInt(), + + VipuType.vmseq_vv -> Cat(VAluOpcode.vmseq, uSew, uSew, mask).asUInt(), + VipuType.vmsne_vv -> Cat(VAluOpcode.vmsne, uSew, uSew, mask).asUInt(), + VipuType.vmsltu_vv -> Cat(VAluOpcode.vmslt, uSew, uSew, mask).asUInt(), + VipuType.vmslt_vv -> Cat(VAluOpcode.vmslt, sSew, sSew, mask).asUInt(), + VipuType.vmsleu_vv -> Cat(VAluOpcode.vmsle, uSew, uSew, mask).asUInt(), + VipuType.vmsle_vv -> Cat(VAluOpcode.vmsle, sSew, sSew, mask).asUInt(), + VipuType.vmsgtu_vv -> Cat(VAluOpcode.vmsgt, uSew, uSew, mask).asUInt(), + VipuType.vmsgt_vv -> Cat(VAluOpcode.vmsgt, sSew, sSew, mask).asUInt(), + + VipuType.vminu_vv -> Cat(VAluOpcode.vmin, uSew, uSew, uSew).asUInt(), + VipuType.vmin_vv -> Cat(VAluOpcode.vmin, sSew, sSew, sSew).asUInt(), + VipuType.vmaxu_vv -> Cat(VAluOpcode.vmax, uSew, uSew, uSew).asUInt(), + VipuType.vmax_vv -> Cat(VAluOpcode.vmax, sSew, sSew, sSew).asUInt(), + + VipuType.vmerge_vvm -> Cat(VAluOpcode.vmerge, uSew, uSew, mask).asUInt(), + + VipuType.vmv_v_v -> Cat(VAluOpcode.vmv, uSew, uSew, uSew).asUInt(), + + VipuType.vsaddu_vv -> Cat(VAluOpcode.vsadd, uSew, uSew, uSew).asUInt(), + VipuType.vsadd_vv -> Cat(VAluOpcode.vsadd, sSew, sSew, sSew).asUInt(), + VipuType.vssubu_vv -> Cat(VAluOpcode.vssub, uSew, uSew, uSew).asUInt(), + VipuType.vssub_vv -> Cat(VAluOpcode.vssub, sSew, sSew, sSew).asUInt(), + + VipuType.vaaddu_vv -> Cat(VAluOpcode.vaadd, uSew, uSew, uSew).asUInt(), + VipuType.vaadd_vv -> Cat(VAluOpcode.vaadd, sSew, sSew, sSew).asUInt(), + VipuType.vasubu_vv -> Cat(VAluOpcode.vasub, uSew, uSew, uSew).asUInt(), + VipuType.vasub_vv -> Cat(VAluOpcode.vasub, sSew, sSew, sSew).asUInt(), + + VipuType.vssrl_vv -> Cat(VAluOpcode.vssrl, uSew, uSew, uSew).asUInt(), + VipuType.vssra_vv -> Cat(VAluOpcode.vssra, uSew, uSew, uSew).asUInt(), + + VipuType.vnclipu_wv -> Cat(VAluOpcode.vssrl, uSew2, uSew, uSew).asUInt(), + VipuType.vnclip_wv -> Cat(VAluOpcode.vssra, uSew2, uSew, uSew).asUInt(), + + VipuType.vredsum_vs -> Cat(VAluOpcode.vredsum, uSew, uSew, uSew).asUInt(), + VipuType.vredmaxu_vs -> Cat(VAluOpcode.vredmax, uSew, uSew, uSew).asUInt(), + VipuType.vredmax_vs -> Cat(VAluOpcode.vredmax, sSew, sSew, sSew).asUInt(), + VipuType.vredminu_vs -> Cat(VAluOpcode.vredmin, uSew, uSew, uSew).asUInt(), + VipuType.vredmin_vs -> Cat(VAluOpcode.vredmin, sSew, sSew, sSew).asUInt(), + VipuType.vredand_vs -> Cat(VAluOpcode.vredand, uSew, uSew, uSew).asUInt(), + VipuType.vredor_vs -> Cat(VAluOpcode.vredor, uSew, uSew, uSew).asUInt(), + VipuType.vredxor_vs -> Cat(VAluOpcode.vredxor, uSew, uSew, uSew).asUInt(), + + VipuType.vwredsumu_vs -> Cat(VAluOpcode.vredsum, uSew, uSew, uSew2).asUInt(), + VipuType.vwredsum_vs -> Cat(VAluOpcode.vredsum, sSew, sSew, sSew2).asUInt(), + + VipuType.vmand_mm -> Cat(VAluOpcode.vand, mask, mask, mask).asUInt(), + VipuType.vmnand_mm -> Cat(VAluOpcode.vnand, mask, mask, mask).asUInt(), + VipuType.vmandn_mm -> Cat(VAluOpcode.vandn, mask, mask, mask).asUInt(), + VipuType.vmxor_mm -> Cat(VAluOpcode.vxor, mask, mask, mask).asUInt(), + VipuType.vmor_mm -> Cat(VAluOpcode.vor, mask, mask, mask).asUInt(), + VipuType.vmnor_mm -> Cat(VAluOpcode.vnor, mask, mask, mask).asUInt(), + VipuType.vmorn_mm -> Cat(VAluOpcode.vorn, mask, mask, mask).asUInt(), + VipuType.vmxnor_mm -> Cat(VAluOpcode.vxnor, mask, mask, mask).asUInt(), + + VipuType.vcpop_m -> Cat(VAluOpcode.vcpop, mask, mask, mask).asUInt(), + VipuType.vfirst_m -> Cat(VAluOpcode.vfirst, mask, mask, mask).asUInt(), + VipuType.vmsbf_m -> Cat(VAluOpcode.vmsbf, mask, mask, mask).asUInt(), + VipuType.vmsif_m -> Cat(VAluOpcode.vmsif, mask, mask, mask).asUInt(), + VipuType.vmsof_m -> Cat(VAluOpcode.vmsof, mask, mask, mask).asUInt(), + + VipuType.viota_m -> Cat(VAluOpcode.viota, mask, mask, uSew).asUInt(), + VipuType.vid_v -> Cat(VAluOpcode.vid, uSew, uSew, uSew).asUInt(), + )).asTypeOf(new VIAluDecodeResultBundle) io.out <> out @@ -129,15 +243,16 @@ class VIAluWrapper(implicit p: Parameters) extends VPUSubModule(p(XSCoreParamsK // generate src1 and src2 val imm = VecInit(Seq.fill(VLEN/XLEN)(VecImmExtractor(ctrl.selImm, vtype.vsew, ctrl.imm))).asUInt - val _src1 = Mux(SrcType.isImm(ctrl.srcType(0)), imm, Mux(ctrl.uopDivType === UopDivType.VEC_MV_LMUL, VecExtractor(vtype.vsew, io.in.bits.src(0)), io.in.bits.src(0))) - val _src2 = in.src(1) - val src1 = Mux(VipuType.needReverse(ctrl.fuOpType), _src2, _src1) - val src2 = Mux(VipuType.needReverse(ctrl.fuOpType), _src1, _src2) + val _vs1 = Mux(SrcType.isImm(ctrl.srcType(0)), imm, Mux(ctrl.uopDivType === UopDivType.VEC_MV_LMUL, VecExtractor(vtype.vsew, io.in.bits.src(0)), io.in.bits.src(0))) + val _vs2 = in.src(1) + val vs1 = Mux(VipuType.needReverse(ctrl.fuOpType), _vs2, _vs1) + val vs2 = Mux(VipuType.needReverse(ctrl.fuOpType), _vs1, _vs2) + val mask = Mux(VipuType.needClearMask(ctrl.fuOpType), 0.U, in.src(3)) // connect VIAlu val decoder = Module(new VIAluDecoder) val vialu = Module(new VIAlu) - decoder.io.in.fuOpType := in.uop.ctrl.fuType + decoder.io.in.fuOpType := in.uop.ctrl.fuOpType decoder.io.in.sew := in.uop.ctrl.vconfig.vtype.vsew(1,0) vialu.io.in.bits.opcode := decoder.io.out.opcode @@ -146,16 +261,18 @@ class VIAluWrapper(implicit p: Parameters) extends VPUSubModule(p(XSCoreParamsK vialu.io.in.bits.info.ta := in.uop.ctrl.vconfig.vtype.vta vialu.io.in.bits.info.vlmul := in.uop.ctrl.vconfig.vtype.vlmul vialu.io.in.bits.info.vl := in.uop.ctrl.vconfig.vl + vialu.io.in.bits.info.vstart := 0.U // TODO : vialu.io.in.bits.info.uopIdx := in.uop.ctrl.uopIdx + vialu.io.in.bits.info.vxrm := vxrm vialu.io.in.bits.srcType(0) := decoder.io.out.srcType(0) vialu.io.in.bits.srcType(1) := decoder.io.out.srcType(1) vialu.io.in.bits.vdType := decoder.io.out.vdType - vialu.io.in.bits.vs1 := src1 - vialu.io.in.bits.vs2 := src2 + vialu.io.in.bits.vs1 := vs1 + vialu.io.in.bits.vs2 := vs2 vialu.io.in.bits.old_vd := in.src(2) - vialu.io.in.bits.mask := in.src(3) + vialu.io.in.bits.mask := mask val vdOut = vialu.io.out.bits.vd val vxsatOut = vialu.io.out.bits.vxsat diff --git a/yunsuan b/yunsuan index 5671d0d2b3467dfa880ddae201fe5938a86f1a13..763f2d1380b04bbc1e93b257a05f22b3a30b90ab 160000 --- a/yunsuan +++ b/yunsuan @@ -1 +1 @@ -Subproject commit 5671d0d2b3467dfa880ddae201fe5938a86f1a13 +Subproject commit 763f2d1380b04bbc1e93b257a05f22b3a30b90ab