From 61711d24c5ab45fd7102dd9d5f1c81dde3f777cd Mon Sep 17 00:00:00 2001 From: William Wang Date: Tue, 23 Feb 2021 16:36:49 +0800 Subject: [PATCH] LSQ: fix vaddrModule raddr * Alternative plan: use async vaddr module --- src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala | 3 ++- src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala index bcb0d4b2b..fd4374aa0 100644 --- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala +++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala @@ -604,7 +604,8 @@ class LoadQueue extends XSModule } // Read vaddr for mem exception - vaddrModule.io.raddr(0) := deqPtr + io.roq.lcommit + // Note that both io.roq.lcommit and RegNext(io.roq.lcommit) should be take into consideration + vaddrModule.io.raddr(0) := (deqPtrExt + commitCount + io.roq.lcommit).value io.exceptionAddr.vaddr := vaddrModule.io.rdata(0) // misprediction recovery / exception redirect diff --git a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala index 943294bbe..a25504a81 100644 --- a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala +++ b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala @@ -104,7 +104,9 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue dataModule.io.raddr(i) := deqPtrExtNext(i).value paddrModule.io.raddr(i) := deqPtrExtNext(i).value } - vaddrModule.io.raddr(0) := cmtPtr + io.roq.scommit + + // Note that both io.roq.scommit and RegNext(io.roq.scommit) should be take into consideration + vaddrModule.io.raddr(0) := (cmtPtrExt(0) + commitCount + io.roq.scommit).value /** * Enqueue at dispatch -- GitLab