From 55a5548283af036b31407bd77f7fc5eff98c9b17 Mon Sep 17 00:00:00 2001 From: ZhangZifei <1773908404@qq.com> Date: Sat, 22 Aug 2020 23:19:34 +0800 Subject: [PATCH] TLB: change Cat to VecInit for Cat will reverse --- src/main/scala/xiangshan/cache/dtlb.scala | 2 +- src/main/scala/xiangshan/cache/ptw.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/cache/dtlb.scala b/src/main/scala/xiangshan/cache/dtlb.scala index e20079e10..335f5b595 100644 --- a/src/main/scala/xiangshan/cache/dtlb.scala +++ b/src/main/scala/xiangshan/cache/dtlb.scala @@ -201,7 +201,7 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{ val v = RegInit(0.U(TlbEntrySize.W)) val pf = RegInit(0.U(TlbEntrySize.W)) // TODO: when ptw resp a pf(now only page not found), store here val entry = Reg(Vec(TlbEntrySize, new TlbEntry)) - val g = Cat(entry.map(_.perm.g)) // TODO: need check if reverse is needed + val g = VecInit(entry.map(_.perm.g)).asUInt // TODO: need check if reverse is needed val entryHitVec = widthMapSeq{i => VecInit(entry.map(_.hit(reqAddr(i).vpn/*, satp.asid*/))) } val hitVec = widthMapSeq{ i => (v.asBools zip entryHitVec(i)).map{ case (a,b) => a&b } } diff --git a/src/main/scala/xiangshan/cache/ptw.scala b/src/main/scala/xiangshan/cache/ptw.scala index 08dd24891..8543c4d46 100644 --- a/src/main/scala/xiangshan/cache/ptw.scala +++ b/src/main/scala/xiangshan/cache/ptw.scala @@ -178,7 +178,7 @@ class PTWImp(outer: PTW) extends PtwModule(outer){ val tlbg = RegInit(0.U(TlbL2EntrySize.W)) // global val ptwl1 = Reg(Vec(PtwL1EntrySize, new PtwEntry(tagLen = tagLen1))) val l1v = RegInit(0.U(PtwL1EntrySize.W)) // valid - val l1g = Cat(ptwl1.map(_.perm.g)) + val l1g = VecInit((ptwl1.map(_.perm.g))).asUInt val ptwl2 = SyncReadMem(PtwL2EntrySize, new PtwEntry(tagLen = tagLen2)) // NOTE: the Mem could be only single port(r&w) val l2v = RegInit(0.U(PtwL2EntrySize.W)) // valid val l2g = RegInit(0.U(PtwL2EntrySize.W)) // global -- GitLab