From 54ae8c26abc9ba46387adb0f0b9872fba9b955fd Mon Sep 17 00:00:00 2001 From: Lingrui98 Date: Wed, 17 Feb 2021 23:19:07 +0800 Subject: [PATCH] bpu: use built-in reset method for sram in tage and sc --- src/main/scala/xiangshan/frontend/SC.scala | 17 ++++--------- src/main/scala/xiangshan/frontend/Tage.scala | 26 ++++++++++---------- 2 files changed, 18 insertions(+), 25 deletions(-) diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala index a103909ff..8b0c9fc0d 100644 --- a/src/main/scala/xiangshan/frontend/SC.scala +++ b/src/main/scala/xiangshan/frontend/SC.scala @@ -53,19 +53,13 @@ class FakeSCTable extends BaseSCTable { class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int) extends BaseSCTable(nRows, ctrBits, histLen) with HasFoldedHistory { - val table = Module(new SRAMTemplate(SInt(ctrBits.W), set=nRows, way=2*TageBanks, shouldReset=false, holdRead=true, singlePort=false)) + val table = Module(new SRAMTemplate(SInt(ctrBits.W), set=nRows, way=2*TageBanks, shouldReset=true, holdRead=true, singlePort=false)) def getIdx(hist: UInt, pc: UInt) = { (compute_folded_hist(hist, log2Ceil(nRows)) ^ (pc >> instOffsetBits.U))(log2Ceil(nRows)-1,0) } def ctrUpdate(ctr: SInt, cond: Bool): SInt = signedSatUpdate(ctr, ctrBits, cond) - - val doing_reset = RegInit(true.B) - val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) - reset_idx := reset_idx + doing_reset - when (reset_idx === (nRows-1).U) { doing_reset := false.B } - val if2_idx = getIdx(io.req.bits.hist, io.req.bits.pc) val if3_idx = RegEnable(if2_idx, enable=io.req.valid) @@ -82,19 +76,18 @@ class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int) VecInit((0 until TageBanks).map(w => ctrUpdate(io.update.oldCtrs(w), io.update.takens(w)))) - table.reset := reset.asBool table.io.r.req.valid := io.req.valid table.io.r.req.bits.setIdx := if2_idx val updateWayMask = VecInit((0 until TageBanks).map(b => VecInit((0 to 1).map(i => - (io.update.mask(b) && i.U === io.update.tagePreds(b).asUInt) || doing_reset)))).asUInt + (io.update.mask(b) && i.U === io.update.tagePreds(b).asUInt))))).asUInt table.io.w.apply( - valid = io.update.mask.asUInt.orR || doing_reset, - data = Mux(doing_reset, VecInit((0 until TageBanks*2).map(_ => 0.S(ctrBits.W))), VecInit((0 until TageBanks*2).map(i => update_wdatas(i/2)))), - setIdx = Mux(doing_reset, reset_idx, update_idx), + valid = io.update.mask.asUInt.orR, + data = VecInit((0 until TageBanks*2).map(i => update_wdatas(i/2))), + setIdx = update_idx, waymask = updateWayMask ) diff --git a/src/main/scala/xiangshan/frontend/Tage.scala b/src/main/scala/xiangshan/frontend/Tage.scala index 6d8c81117..c5138cf73 100644 --- a/src/main/scala/xiangshan/frontend/Tage.scala +++ b/src/main/scala/xiangshan/frontend/Tage.scala @@ -139,9 +139,9 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio val (if2_idx, if2_tag) = compute_tag_and_hash(if2_unhashed_idx, io.req.bits.hist) val (if3_idx, if3_tag) = (RegEnable(if2_idx, io.req.valid), RegEnable(if2_tag, io.req.valid)) - val hi_us = Module(new SRAMTemplate(Bool(), set=nRows, way=TageBanks, shouldReset=false, holdRead=true, singlePort=false)) - val lo_us = Module(new SRAMTemplate(Bool(), set=nRows, way=TageBanks, shouldReset=false, holdRead=true, singlePort=false)) - val table = Module(new SRAMTemplate(new TageEntry, set=nRows, way=TageBanks, shouldReset=false, holdRead=true, singlePort=false)) + val hi_us = Module(new SRAMTemplate(Bool(), set=nRows, way=TageBanks, shouldReset=true, holdRead=true, singlePort=false)) + val lo_us = Module(new SRAMTemplate(Bool(), set=nRows, way=TageBanks, shouldReset=true, holdRead=true, singlePort=false)) + val table = Module(new SRAMTemplate(new TageEntry, set=nRows, way=TageBanks, shouldReset=true, holdRead=true, singlePort=false)) table.reset := reset.asBool hi_us.reset := reset.asBool @@ -186,25 +186,25 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio table.io.w.apply( valid = io.update.mask.asUInt.orR || doing_reset, - data = Mux(doing_reset, 0.U.asTypeOf(Vec(TageBanks, new TageEntry)), update_wdata), - setIdx = Mux(doing_reset, reset_idx, update_idx), + data = update_wdata, + setIdx = update_idx, waymask = io.update.mask.asUInt ) val update_hi_wdata = Wire(Vec(TageBanks, Bool())) hi_us.io.w.apply( - valid = io.update.uMask.asUInt.orR || doing_reset || doing_clear_u_hi, - data = Mux(doing_reset || doing_clear_u_hi, 0.U.asTypeOf(Vec(TageBanks, Bool())), update_hi_wdata), - setIdx = Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)), - waymask = Mux(doing_reset || doing_clear_u_hi, Fill(TageBanks, "b1".U), io.update.uMask.asUInt) + valid = io.update.uMask.asUInt.orR || doing_clear_u_hi, + data = Mux(doing_clear_u_hi, 0.U.asTypeOf(Vec(TageBanks, Bool())), update_hi_wdata), + setIdx = Mux(doing_clear_u_hi, clear_u_idx, update_idx), + waymask = Mux(doing_clear_u_hi, Fill(TageBanks, "b1".U), io.update.uMask.asUInt) ) val update_lo_wdata = Wire(Vec(TageBanks, Bool())) lo_us.io.w.apply( - valid = io.update.uMask.asUInt.orR || doing_reset || doing_clear_u_lo, - data = Mux(doing_reset || doing_clear_u_lo, 0.U.asTypeOf(Vec(TageBanks, Bool())), update_lo_wdata), - setIdx = Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)), - waymask = Mux(doing_reset || doing_clear_u_lo, Fill(TageBanks, "b1".U), io.update.uMask.asUInt) + valid = io.update.uMask.asUInt.orR || doing_clear_u_lo, + data = Mux(doing_clear_u_lo, 0.U.asTypeOf(Vec(TageBanks, Bool())), update_lo_wdata), + setIdx = Mux(doing_clear_u_lo, clear_u_idx, update_idx), + waymask = Mux(doing_clear_u_lo, Fill(TageBanks, "b1".U), io.update.uMask.asUInt) ) val wrbypass_tags = Reg(Vec(wrBypassEntries, UInt(tagLen.W))) -- GitLab