diff --git a/src/main/scala/xiangshan/backend/exu/Alu.scala b/src/main/scala/xiangshan/backend/exu/Alu.scala
index ca65366d29bbd85ef35e824872c83f64a66ba35c..bafa903779e650d964978098c562d7313948bb4a 100644
--- a/src/main/scala/xiangshan/backend/exu/Alu.scala
+++ b/src/main/scala/xiangshan/backend/exu/Alu.scala
@@ -99,6 +99,9 @@ class Alu extends Exu(alu.litValue(), hasRedirect = true) {
 
   io.in.ready := io.out.ready
   val pcLatchSlot = Mux(isRVC, pc + 2.U, pc + 4.U)
+  //TODO fix me
+  io.out.bits.redirect := DontCare
+
   io.out.bits.redirectValid := io.out.valid && isBru//isBranch
   io.out.bits.redirect.pc := uop.cf.pc
   io.out.bits.redirect.target := Mux(!taken && isBranch, pcLatchSlot, target)
diff --git a/src/main/scala/xiangshan/backend/exu/Bru.scala b/src/main/scala/xiangshan/backend/exu/Bru.scala
index 2a1bd981b17890bb34e086cc5864aa22fbde1041..22dfa6d3f31f14cb94dc81c3440b8d89f1fc953e 100644
--- a/src/main/scala/xiangshan/backend/exu/Bru.scala
+++ b/src/main/scala/xiangshan/backend/exu/Bru.scala
@@ -35,6 +35,9 @@ class Bru extends Exu(FuType.bru.litValue(), writeFpRf = true, hasRedirect = tru
   val pcDelaySlot = Mux(isRVC, pc + 2.U, pc + 4.U)
   val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset)
 
+  //TODO fix me
+  io.out.bits.redirect := DontCare
+
   io.out.bits.redirectValid := valid && isJUMP
   io.out.bits.redirect.pc := io.in.bits.uop.cf.pc
   io.out.bits.redirect.target := target