diff --git a/src/main/scala/xiangshan/XSCore.scala b/src/main/scala/xiangshan/XSCore.scala index 4389d77347d3b98fd0e2e74ee3d230275bb77db8..510b322a8a4874893ab1881d6b094c9cfa98025e 100644 --- a/src/main/scala/xiangshan/XSCore.scala +++ b/src/main/scala/xiangshan/XSCore.scala @@ -27,8 +27,7 @@ trait HasXSParameter { val HasFPU = true val FetchWidth = 8 val IBufSize = 64 - val DecodeWidth = 8 - val DecBufSize = 8 + val DecodeWidth = 6 val RenameWidth = 6 val CommitWidth = 6 val BrqSize = 16 diff --git a/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala b/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala index efdea9bcf7751edc33647631ea04af0830c6f529..208ffde95e0c03422148b03625b7933eb709dfe4 100644 --- a/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala +++ b/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala @@ -12,20 +12,32 @@ class DecodeBuffer extends XSModule { val out = Vec(RenameWidth, DecoupledIO(new CfCtrl)) }) - val q = Module(new MIMOQueue[CfCtrl]( - gen = new CfCtrl, - entries = DecBufSize, - inCnt = io.in.size, - outCnt = io.out.size, - mem = true, - perf = false - )) - - q.io.flush := io.redirect.valid - q.io.enq <> io.in - for((out, deq) <- io.out.zip(q.io.deq)){ - out.bits := deq.bits - out.valid := deq.valid && !io.redirect.valid - deq.ready := out.ready + require(DecodeWidth == RenameWidth) + + val validVec = RegInit(VecInit(Seq.fill(DecodeWidth)(false.B))) + + val leftCanIn = ParallelAND( + validVec.zip(io.out.map(_.fire())).map({ + case (v, fire) => + !v || fire + }) + ).asBool() + + val rightRdyVec = io.out.map(_.ready && leftCanIn) + + for( i <- 0 until RenameWidth){ + when(io.out(i).fire()){ + validVec(i) := false.B + } + when(io.in(i).fire()){ + validVec(i) := true.B + } + when(io.redirect.valid){ + validVec(i) := false.B + } + + io.in(i).ready := rightRdyVec(i) + io.out(i).bits <> RegEnable(io.in(i).bits, io.in(i).fire()) + io.out(i).valid := validVec(i) && !io.redirect.valid } }