From 4f1163c3a8c4ed1258e71a6de0c11b013fb833e6 Mon Sep 17 00:00:00 2001
From: LinJiawei <linjiav@outlook.com>
Date: Wed, 21 Oct 2020 17:17:01 +0800
Subject: [PATCH] [WIP] fix module name print

---
 src/test/scala/cache/L2CacheTest.scala | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/test/scala/cache/L2CacheTest.scala b/src/test/scala/cache/L2CacheTest.scala
index 70eb74b35..59bab8ceb 100644
--- a/src/test/scala/cache/L2CacheTest.scala
+++ b/src/test/scala/cache/L2CacheTest.scala
@@ -7,6 +7,7 @@ import chiseltest.experimental.TestOptionBuilder._
 import chiseltest.internal.VerilatorBackendAnnotation
 import chiseltest._
 import chisel3.experimental.BundleLiterals._
+import firrtl.stage.RunFirrtlTransformAnnotation
 import chiseltest.ChiselScalatestTester
 import device.AXI4RAM
 import freechips.rocketchip.amba.axi4.AXI4UserYanker
@@ -18,6 +19,7 @@ import utils.{DebugIdentityNode, HoldUnless, XSDebug}
 import xiangshan.HasXSLog
 import xiangshan.cache.{DCache, DCacheLineReq, DCacheWordReq, MemoryOpConstants}
 import xiangshan.testutils.AddSinks
+import xstransforms.PrintModuleName
 
 import scala.util.Random
 
@@ -260,7 +262,10 @@ class L2CacheTest extends FlatSpec with ChiselScalatestTester with Matchers{
     })
 
     test(LazyModule(new L2TestTopWrapper()).module)
-      .withAnnotations(Seq(VerilatorBackendAnnotation)){ c =>
+      .withAnnotations(Seq(
+        VerilatorBackendAnnotation,
+        RunFirrtlTransformAnnotation(new PrintModuleName)
+      )){ c =>
 
         c.io.in.initSource().setSourceClock(c.clock)
         c.io.out.initSink().setSinkClock(c.clock)
-- 
GitLab