From 4cb1b537c4ca36fbe961b1b4505e66ebbd3db68b Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Fri, 27 Nov 2020 14:28:16 +0800 Subject: [PATCH] dispatch1: set prevCanOut to true.B when !io.Rename(i).valid --- src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala b/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala index 4691fba71..136499455 100644 --- a/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala +++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala @@ -85,7 +85,7 @@ class Dispatch1 extends XSModule { // For i in [0, DqEnqWidth], previous instructions can always enqueue when ROB and LSQ are ready if (i <= dpParams.DqEnqWidth) true.B // They need to check their previous ones - else Cat((dpParams.DqEnqWidth until i).map(thisCanOut(_))).andR + else Cat((dpParams.DqEnqWidth until i).map(j => thisCanOut(j) || !io.fromRename(j).valid)).andR )) // this instruction can actually dequeue: 3 conditions -- GitLab