From 4b4a08ce34ebc541d752e69b7bb69cb800ebaf55 Mon Sep 17 00:00:00 2001 From: czw <1753182770@qq.com> Date: Mon, 13 Mar 2023 16:15:09 +0800 Subject: [PATCH] func(vstart): add vstart from CSR to VIPU --- src/main/scala/xiangshan/XSCore.scala | 1 + .../scala/xiangshan/backend/FUBlock.scala | 4 +++ .../scala/xiangshan/backend/exu/ExeUnit.scala | 2 ++ .../scala/xiangshan/backend/exu/Exu.scala | 1 + .../xiangshan/backend/fu/vector/VIPU.scala | 32 +++++++------------ .../backend/fu/vector/VPUSubModule.scala | 1 + 6 files changed, 21 insertions(+), 20 deletions(-) diff --git a/src/main/scala/xiangshan/XSCore.scala b/src/main/scala/xiangshan/XSCore.scala index dc11dc64e..1c0544975 100644 --- a/src/main/scala/xiangshan/XSCore.scala +++ b/src/main/scala/xiangshan/XSCore.scala @@ -456,6 +456,7 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) csrioIn.vpu.set_vl.bits <> ZeroExt(vconfigDiff.vl, XLEN) csrioIn.vpu.set_vtype.bits <> ZeroExt(vconfigDiff.vtype.asUInt, XLEN) csrioIn.vpu.vxrm <> vecExuBlock.extraio.fuExtra.vxrm + csrioIn.vpu.vstart <> vecExuBlock.extraio.fuExtra.vstart csrioIn.exception <> ctrlBlock.io.robio.exception csrioIn.isXRet <> ctrlBlock.io.robio.toCSR.isXRet csrioIn.trapTarget <> ctrlBlock.io.robio.toCSR.trapTarget diff --git a/src/main/scala/xiangshan/backend/FUBlock.scala b/src/main/scala/xiangshan/backend/FUBlock.scala index 298088896..e1ac9f65a 100644 --- a/src/main/scala/xiangshan/backend/FUBlock.scala +++ b/src/main/scala/xiangshan/backend/FUBlock.scala @@ -156,6 +156,7 @@ class VecFUBlockExtraIO(configs: Seq[(ExuConfig, Int)])(implicit p: Parameters) val frm = Input(UInt(3.W)) val vxrm = Input(UInt(2.W)) + val vstart = Input(UInt(XLEN.W)) override def toString: String = { s"VecFUBlockExtraIO: " + configs.map(a => a._1.name + "*" + a._2).reduce(_ + " " + _) + s" hasFrm" @@ -176,6 +177,9 @@ class VecFUBlockImp(configVec: Seq[(ExuConfig, Int)], out: VecFUBlock)(implicit if (exu.vxrm.isDefined){ exu.vxrm.get := extraio.vxrm } + if (exu.vstart.isDefined) { + exu.vstart.get := extraio.vstart + } } println(extraio) } \ No newline at end of file diff --git a/src/main/scala/xiangshan/backend/exu/ExeUnit.scala b/src/main/scala/xiangshan/backend/exu/ExeUnit.scala index 500a8b39e..341483f1f 100644 --- a/src/main/scala/xiangshan/backend/exu/ExeUnit.scala +++ b/src/main/scala/xiangshan/backend/exu/ExeUnit.scala @@ -40,6 +40,7 @@ class ExeUnit(config: ExuConfig)(implicit p: Parameters) extends Exu(config) { val disableSfence = WireInit(false.B) val csr_frm = WireInit(frm.getOrElse(0.U(3.W))) val csr_vxrm = WireInit(vxrm.getOrElse(0.U(2.W))) + val csr_vstart = WireInit(vstart.getOrElse(0.U(XLEN.W))) val hasRedirect = config.fuConfigs.zip(functionUnits).filter(_._1.hasRedirect).map(_._2) println(s"ExeUnit: ${functionUnits.map(_.name).reduce(_ + " " + _)} ${hasRedirect} hasRedirect: ${hasRedirect.length}") @@ -104,6 +105,7 @@ class ExeUnit(config: ExuConfig)(implicit p: Parameters) extends Exu(config) { if (vipuModules.nonEmpty) { vipuModules.map(_._1.asInstanceOf[VIPU]).foreach(mod => { mod.vxrm := csr_vxrm + mod.vstart := csr_vstart io.out.bits.vxsat := mod.vxsat }) } diff --git a/src/main/scala/xiangshan/backend/exu/Exu.scala b/src/main/scala/xiangshan/backend/exu/Exu.scala index 784adf897..d3d1205e3 100644 --- a/src/main/scala/xiangshan/backend/exu/Exu.scala +++ b/src/main/scala/xiangshan/backend/exu/Exu.scala @@ -147,6 +147,7 @@ abstract class Exu(cfg: ExuConfig)(implicit p: Parameters) extends XSModule { @public val fenceio = if (config == JumpCSRExeUnitCfg) Some(IO(new FenceIO)) else None @public val frm = if (config == FmacExeUnitCfg || config == FmiscExeUnitCfg) Some(IO(Input(UInt(3.W)))) else None @public val vxrm = if (config == FmacExeUnitCfg) Some(IO(Input(UInt(2.W)))) else None // TODO: only VIPU need vxrm + @public val vstart = if (config == FmacExeUnitCfg) Some(IO(Input(UInt(XLEN.W)))) else None // TODO: only VPU need vstart val functionUnits = config.fuConfigs.map(cfg => { val mod = Module(cfg.fuGen(p)) diff --git a/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala b/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala index 75cf12821..342529c28 100644 --- a/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala +++ b/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala @@ -41,9 +41,9 @@ class VIPU(implicit p: Parameters) extends VPUSubModule(p(XSCoreParamsKey).VLEN) val dataWire = Wire(dataReg.cloneType) val s_idle :: s_compute :: s_finish :: Nil = Enum(3) val state = RegInit(s_idle) - val vialu = Module(new VIAluWrapper) - val outValid = vialu.io.out.valid - val outFire = vialu.io.out.fire() + val vialuWp = Module(new VIAluWrapper) + val outValid = vialuWp.io.out.valid + val outFire = vialuWp.io.out.fire() // reg input signal val s0_uopReg = Reg(io.in.bits.uop.cloneType) @@ -68,17 +68,18 @@ class VIPU(implicit p: Parameters) extends VPUSubModule(p(XSCoreParamsKey).VLEN) } // connect VIAlu - dataWire := vialu.io.out.bits.data - vialu.io.in.bits <> io.in.bits - vialu.io.redirectIn := DontCare // TODO : - vialu.vxrm := vxrm + dataWire := vialuWp.io.out.bits.data + vialuWp.io.in.bits <> io.in.bits + vialuWp.io.redirectIn := DontCare // TODO : + vialuWp.vxrm := vxrm + vialuWp.vstart := vstart io.out.bits.data := Mux(state === s_compute && outFire, dataWire, dataReg) io.out.bits.uop := s0_uopReg - vxsat := vialu.vxsat + vxsat := vialuWp.vxsat - vialu.io.in.valid := io.in.valid && state === s_idle + vialuWp.io.in.valid := io.in.valid && state === s_idle io.out.valid := state === s_compute && outValid || state === s_finish - vialu.io.out.ready := io.out.ready + vialuWp.io.out.ready := io.out.ready io.in.ready := state === s_idle } @@ -98,15 +99,6 @@ class VIAluDecoder (implicit p: Parameters) extends XSModule { val out = Output(new VIAluDecodeResultBundle) }) -// val DecodeDefault = List(VAluOpcode.dummy, VpuDataType.dummy, VpuDataType.dummy, VpuDataType.dummy) -// val DecodeTable = Array( -// BitPat("b" + Cat(VipuType.add, "b00".U).litValue().toString()) -> List(VAluOpcode.vadd, VpuDataType.s8, VpuDataType.s8, VpuDataType.s8), -// BitPat("b" + Cat(VipuType.add, "b01".U).litValue().toString()) -> List(VAluOpcode.vadd, VpuDataType.s16, VpuDataType.s16, VpuDataType.s16), -// BitPat("b" + Cat(VipuType.add, "b10".U).litValue().toString()) -> List(VAluOpcode.vadd, VpuDataType.s32, VpuDataType.s32, VpuDataType.s32), -// BitPat("b" + Cat(VipuType.add, "b11".U).litValue().toString()) -> List(VAluOpcode.vadd, VpuDataType.s64, VpuDataType.s64, VpuDataType.s64), -// ) -// val opcode :: srcType1 :: srcType2 :: vdType :: Nil = ListLookup(Cat(io.in.fuOpType, io.in.sew), DecodeDefault, DecodeTable) - // u 00 s 01 f 10 mask 1111 val uSew = Cat(0.U(2.W), io.in.sew) val uSew2 = Cat(0.U(2.W), (io.in.sew+1.U)) @@ -263,7 +255,7 @@ class VIAluWrapper(implicit p: Parameters) extends VPUSubModule(p(XSCoreParamsK vialu.io.in.bits.info.vlmul := in.uop.ctrl.vconfig.vtype.vlmul vialu.io.in.bits.info.vl := in.uop.ctrl.vconfig.vl - vialu.io.in.bits.info.vstart := 0.U // TODO : + vialu.io.in.bits.info.vstart := vstart // TODO : vialu.io.in.bits.info.uopIdx := in.uop.ctrl.uopIdx vialu.io.in.bits.info.vxrm := vxrm diff --git a/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala b/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala index c647e8388..41e7fd9c9 100644 --- a/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala +++ b/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala @@ -24,4 +24,5 @@ import xiangshan.backend.fu.{FunctionUnit} abstract class VPUSubModule(len: Int = 128)(implicit p: Parameters) extends FunctionUnit(len: Int) { + val vstart = IO(Input(UInt(XLEN.W))) } -- GitLab