diff --git a/src/main/scala/xiangshan/backend/decode/StoreSet.scala b/src/main/scala/xiangshan/backend/decode/StoreSet.scala
index f209206346be181e90936ab8ec702b305228e547..439227513f33e5bb94fbcba1f5fe640f65295f46 100644
--- a/src/main/scala/xiangshan/backend/decode/StoreSet.scala
+++ b/src/main/scala/xiangshan/backend/decode/StoreSet.scala
@@ -106,6 +106,11 @@ class SSIT extends XSModule {
     }
   }
 
+  XSPerf("ssit_update_lxsx", memPredUpdateReqReg.valid && !loadAssigned && !storeAssigned)
+  XSPerf("ssit_update_lysx", memPredUpdateReqReg.valid && loadAssigned && !storeAssigned)
+  XSPerf("ssit_update_lxsy", memPredUpdateReqReg.valid && !loadAssigned && storeAssigned)
+  XSPerf("ssit_update_lysy", memPredUpdateReqReg.valid && loadAssigned && storeAssigned)
+
   // reset period: ResetTimeMax2Pow
   when(resetCounter(ResetTimeMax2Pow-1, ResetTimeMin2Pow)(RegNext(io.csrCtrl.waittable_timeout))) {
     for (j <- 0 until SSITSize) {
@@ -169,6 +174,13 @@ class LFST extends XSModule  {
       io.csrCtrl.no_spec_load) && !io.csrCtrl.lvpred_disable
   }
 
+  // when store is issued, mark it as invalid
+  (0 until exuParameters.StuCnt).map(i => {
+    when(io.storeIssue(i).valid){
+      valid(io.storeIssue(i).bits.uop.cf.ssid) := false.B
+    }
+  })
+
   // when store is dispatched, mark it as valid
   (0 until RenameWidth).map(i => {
     when(io.dispatch(i).valid){
@@ -179,13 +191,6 @@ class LFST extends XSModule  {
     }
   })
 
-  // when store is issued, mark it as invalid
-  (0 until exuParameters.StuCnt).map(i => {
-    when(io.storeIssue(i).valid){
-      valid(io.storeIssue(i).bits.uop.cf.ssid) := false.B
-    }
-  })
-
   // when redirect, cancel store influenced
   (0 until LFSTSize).map(i => {
     when(roqIdx(i).needFlush(io.redirect, io.flush)){
diff --git a/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala b/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
index 9d90137f8a982840b4d5f4e996d42963adfa0762..2aed85fb2c1707ae62cf220dada2b5cfc1639cb8 100644
--- a/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
+++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
@@ -160,6 +160,32 @@ class Dispatch1 extends XSModule with HasExceptionNO {
     io.lfst(i).bits.ssid := updatedUop(i).cf.ssid
   }
 
+  // store set perf count
+  XSPerf("waittable_load_wait", PopCount((0 until RenameWidth).map(i => 
+    io.fromRename(i).fire() && io.fromRename(i).bits.cf.loadWaitBit && !isStore(i) && isLs(i)
+  )))
+  XSPerf("storeset_load_wait", PopCount((0 until RenameWidth).map(i => 
+    io.fromRename(i).fire() && updatedUop(i).cf.loadWaitBit && !isStore(i) && isLs(i)
+  )))
+  XSPerf("storeset_store_wait", PopCount((0 until RenameWidth).map(i => 
+    io.fromRename(i).fire() && updatedUop(i).cf.loadWaitBit && isStore(i)
+  )))
+  XSPerf("loadwait_diffmat_sywy", PopCount((0 until RenameWidth).map(i => 
+    io.fromRename(i).fire() && updatedUop(i).cf.loadWaitBit && io.fromRename(i).bits.cf.loadWaitBit &&
+    !isStore(i) && isLs(i)
+  )))
+  XSPerf("loadwait_diffmat_sywx", PopCount((0 until RenameWidth).map(i => 
+    io.fromRename(i).fire() && updatedUop(i).cf.loadWaitBit && !io.fromRename(i).bits.cf.loadWaitBit &&
+    !isStore(i) && isLs(i)
+  )))
+  XSPerf("loadwait_diffmat_sxwy", PopCount((0 until RenameWidth).map(i => 
+    io.fromRename(i).fire() && !updatedUop(i).cf.loadWaitBit && io.fromRename(i).bits.cf.loadWaitBit &&
+    !isStore(i) && isLs(i)
+  )))
+  XSPerf("loadwait_diffmat_sxwx", PopCount((0 until RenameWidth).map(i => 
+    io.fromRename(i).fire() && !updatedUop(i).cf.loadWaitBit && !io.fromRename(i).bits.cf.loadWaitBit &&
+    !isStore(i) && isLs(i)
+  )))
 
   /**
     * Part 3: