diff --git a/src/main/scala/xiangshan/backend/issue/IssueQueue.scala b/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
index 5d9e017a976e250b13c810905a4f75ea71425097..1518e79292493031fe848ec156592fc582b2ef09 100644
--- a/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
+++ b/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
@@ -94,7 +94,7 @@ class IssueQueue
   def writeBackHit(src: UInt, srcType: UInt, wbUop: (Bool, MicroOp)): Bool = {
     val (v, uop) = wbUop
     val isSameType =
-      (SrcType.isReg(srcType) && uop.ctrl.rfWen) || (SrcType.isFp(srcType) && uop.ctrl.fpWen)
+      (SrcType.isReg(srcType) && uop.ctrl.rfWen && src =/= 0.U) || (SrcType.isFp(srcType) && uop.ctrl.fpWen)
 
     v && isSameType && (src===uop.pdest)
   }
diff --git a/src/main/scala/xiangshan/backend/issue/ReservationStation.scala b/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
index 4b37003458f9b7f5e1771f8d20acad0f7b195ed0..a6db45a915fc8f9958ffffc997f71d3dac05f086 100644
--- a/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
+++ b/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
@@ -284,7 +284,7 @@ class ReservationStation
 
     for(i <- idQue.indices) { // Should be IssQue.indices but Mem() does not support
       for(j <- 0 until srcListenNum) {
-        val hitVec = cdbValid.indices.map(k => psrc(i)(j) === cdbPdest(k) && cdbValid(k) && (srcType(i)(j)===SrcType.reg && cdbrfWen(k) || srcType(i)(j)===SrcType.fp && cdbfpWen(k)))
+        val hitVec = cdbValid.indices.map(k => psrc(i)(j) === cdbPdest(k) && cdbValid(k) && (srcType(i)(j)===SrcType.reg && cdbrfWen(k) && cdbPdest(i) =/= 0.U || srcType(i)(j)===SrcType.fp && cdbfpWen(k)))
         val hit = ParallelOR(hitVec).asBool
         val data = ParallelMux(hitVec zip cdbData)
         when (validQue(i) && !srcRdyVec(i)(j) && hit) { 
@@ -306,7 +306,7 @@ class ReservationStation
 
     for (i <- idQue.indices) { // Should be IssQue.indices but Mem() does not support
       for (j <- 0 until srcListenNum) {
-        val hitVec = bpValid.indices.map(k => psrc(i)(j) === bpPdest(k) && bpValid(k) && (srcType(i)(j)===SrcType.reg && bprfWen(k) || srcType(i)(j)===SrcType.fp && bpfpWen(k)))
+        val hitVec = bpValid.indices.map(k => psrc(i)(j) === bpPdest(k) && bpValid(k) && (srcType(i)(j)===SrcType.reg && bprfWen(k) && cdbPdest(i) =/= 0.U || srcType(i)(j)===SrcType.fp && bpfpWen(k)))
         val hitVecNext = hitVec.map(RegNext(_))
         val hit = ParallelOR(hitVec).asBool
         when (validQue(i) && !srcRdyVec(i)(j) && hit) {
diff --git a/src/test/csrc/uart.cpp b/src/test/csrc/uart.cpp
index e86201acae3c8b1e911441dc3d6c394ec20ee2c2..bd1d91d08b886f50e45cd3c1fbbe67c663e06b24 100644
--- a/src/test/csrc/uart.cpp
+++ b/src/test/csrc/uart.cpp
@@ -40,9 +40,9 @@ uint8_t uart_getc() {
     eprintf(ANSI_COLOR_RED "now = %ds\n" ANSI_COLOR_RESET, now / 1000);
     lasttime = now;
   }
-  if (now > 4 * 3600 * 1000) { // 4 hours
-    ch = uart_dequeue();
-  }
+  // if (now > 4 * 3600 * 1000) { // 4 hours
+  //   ch = uart_dequeue();
+  // }
   return ch;
 }