diff --git a/build.sc b/build.sc index 490b8ef917198c0ed7c8a538a05b74bb76055b00..3cdf215f188e55d9ba53995d1eb3e287acfdcd3f 100644 --- a/build.sc +++ b/build.sc @@ -99,6 +99,8 @@ object rocketchip extends `rocket-chip`.common.CommonRocketChip { def chisel3IvyDeps = if(chisel3Module.isEmpty) Agg( common.getVersion("chisel3") ) else Agg.empty[Dep] + + def chisel3PluginIvyDeps = Agg(common.getVersion("chisel3-plugin", cross=true)) } def hardfloatModule = hardfloatRocket diff --git a/src/main/scala/utils/CircularQueuePtr.scala b/src/main/scala/utils/CircularQueuePtr.scala index 0b188255a6f0ef60d7c32fe58461db472c2b14d6..348db586109b982ecdc14ca7a76e2c907ca90e68 100644 --- a/src/main/scala/utils/CircularQueuePtr.scala +++ b/src/main/scala/utils/CircularQueuePtr.scala @@ -61,6 +61,8 @@ class CircularQueuePtr[T <: CircularQueuePtr[T]](val entries: Int) extends Bundl final def === (that_ptr: T): Bool = this.asUInt()===that_ptr.asUInt() final def =/= (that_ptr: T): Bool = this.asUInt()=/=that_ptr.asUInt() + + def toOH: UInt = UIntToOH(value, entries) } trait HasCircularQueuePtrHelper { diff --git a/src/main/scala/utils/PerfCounterUtils.scala b/src/main/scala/utils/PerfCounterUtils.scala index 2d58ed28ecb7305e328d64cbcde1f072de300431..d0b95d2ef789604e6522b76f003df9c50c886ff5 100644 --- a/src/main/scala/utils/PerfCounterUtils.scala +++ b/src/main/scala/utils/PerfCounterUtils.scala @@ -203,14 +203,14 @@ class HPerfCounter(val numPCnt: Int)(implicit p: Parameters) extends XSModule wi val events_sets = Input(Vec(numPCnt, new PerfEvent)) }) - val events_incr_0 = io.events_sets(io.hpm_event( 9, 0)) - val events_incr_1 = io.events_sets(io.hpm_event(19, 10)) - val events_incr_2 = io.events_sets(io.hpm_event(29, 20)) - val events_incr_3 = io.events_sets(io.hpm_event(39, 30)) + val events_incr_0 = RegNext(io.events_sets(io.hpm_event( 9, 0))) + val events_incr_1 = RegNext(io.events_sets(io.hpm_event(19, 10))) + val events_incr_2 = RegNext(io.events_sets(io.hpm_event(29, 20))) + val events_incr_3 = RegNext(io.events_sets(io.hpm_event(39, 30))) - val event_op_0 = io.hpm_event(44, 40) - val event_op_1 = io.hpm_event(49, 45) - val event_op_2 = io.hpm_event(54, 50) + val event_op_0 = RegNext(io.hpm_event(44, 40)) + val event_op_1 = RegNext(io.hpm_event(49, 45)) + val event_op_2 = RegNext(io.hpm_event(54, 50)) val event_step_0 = Mux(event_op_0(0), events_incr_3.value & events_incr_2.value, diff --git a/src/main/scala/xiangshan/Bundle.scala b/src/main/scala/xiangshan/Bundle.scala index d4bd8b6bd26f6ae92c1fd17970350c6a16a64ecb..784e62666039c9e94f37e7e51cd483f8de52ac29 100644 --- a/src/main/scala/xiangshan/Bundle.scala +++ b/src/main/scala/xiangshan/Bundle.scala @@ -163,7 +163,6 @@ class CtrlSignals(implicit p: Parameters) extends XSBundle { val noSpecExec = Bool() // wait forward val blockBackward = Bool() // block backward val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit - val isRVF = Bool() val selImm = SelImm() val imm = UInt(ImmUnion.maxLen.W) val commitType = CommitType() @@ -175,7 +174,7 @@ class CtrlSignals(implicit p: Parameters) extends XSBundle { val replayInst = Bool() private def allSignals = srcType ++ Seq(fuType, fuOpType, rfWen, fpWen, - isXSTrap, noSpecExec, blockBackward, flushPipe, isRVF, selImm) + isXSTrap, noSpecExec, blockBackward, flushPipe, selImm) def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): CtrlSignals = { val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, XDecode.decodeDefault, table) @@ -349,6 +348,8 @@ class RobCommitInfo(implicit p: Parameters) extends XSBundle { class RobCommitIO(implicit p: Parameters) extends XSBundle { val isWalk = Output(Bool()) val valid = Vec(CommitWidth, Output(Bool())) + // valid bits optimized for walk + val walkValid = Vec(CommitWidth, Output(Bool())) val info = Vec(CommitWidth, Output(new RobCommitInfo)) def hasWalkInstr = isWalk && valid.asUInt.orR diff --git a/src/main/scala/xiangshan/backend/decode/DecodeStage.scala b/src/main/scala/xiangshan/backend/decode/DecodeStage.scala index 6a26f999bd6c6b176e0989dba26c6cbd9f56af84..6ac73ca2f4340c5bf5de53185c55c26660b8cde0 100644 --- a/src/main/scala/xiangshan/backend/decode/DecodeStage.scala +++ b/src/main/scala/xiangshan/backend/decode/DecodeStage.scala @@ -101,11 +101,13 @@ class DecodeStage(implicit p: Parameters) extends XSModule with HasPerfEvents { XSPerfAccumulate("waitInstr", PopCount((0 until DecodeWidth).map(i => io.in(i).valid && !io.in(i).ready))) XSPerfAccumulate("stall_cycle", hasValid && !io.out(0).ready) + val fusionValid = RegNext(VecInit(fusionDecoder.io.out.map(_.fire))) + val inFire = io.in.map(in => RegNext(in.valid && !in.ready)) val perfEvents = Seq( - ("decoder_fused_instr ", PopCount(fusionDecoder.io.out.map(_.fire)) ), - ("decoder_waitInstr ", PopCount((0 until DecodeWidth).map(i => io.in(i).valid && !io.in(i).ready))), - ("decoder_stall_cycle ", hasValid && !io.out(0).ready ), - ("decoder_utilization ", PopCount(io.in.map(_.valid)) ), + ("decoder_fused_instr", PopCount(fusionValid) ), + ("decoder_waitInstr", PopCount(inFire) ), + ("decoder_stall_cycle", hasValid && !io.out(0).ready), + ("decoder_utilization", PopCount(io.in.map(_.valid))), ) generatePerfEvent() } diff --git a/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala b/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala index ff52d6c7ae2b9ddce06754fdad802a56b01229a1..c957ec7c4665b4b992f6eca4422431b080dae668 100644 --- a/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala +++ b/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala @@ -36,15 +36,15 @@ abstract trait DecodeConstants { def Y = BitPat("b1") def decodeDefault: List[BitPat] = // illegal instruction - // srcType(0) srcType(1) srcType(2) fuType fuOpType rfWen - // | | | | | | fpWen - // | | | | | | | isXSTrap - // | | | | | | | | noSpecExec - // | | | | | | | | | blockBackward - // | | | | | | | | | | flushPipe - // | | | | | | | | | | | isRVF - // | | | | | | | | | | | | selImm - List(SrcType.DC, SrcType.DC, SrcType.DC, FuType.alu, ALUOpType.sll, N, N, N, N, N, N, N, SelImm.INVALID_INSTR) // Use SelImm to indicate invalid instr + // srcType(0) srcType(1) srcType(2) fuType fuOpType rfWen + // | | | | | | fpWen + // | | | | | | | isXSTrap + // | | | | | | | | noSpecExec + // | | | | | | | | | blockBackward + // | | | | | | | | | | flushPipe + // | | | | | | | | | | | selImm + // | | | | | | | | | | | | + List(SrcType.X, SrcType.X, SrcType.X, FuType.X, FuOpType.X, N, N, N, N, N, N, SelImm.INVALID_INSTR) // Use SelImm to indicate invalid instr val table: Array[(BitPat, List[BitPat])] } @@ -72,28 +72,28 @@ trait DecodeUnitConstants */ object X64Decode extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - LD -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.ld, Y, N, N, N, N, N, N, SelImm.IMM_I), - LWU -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lwu, Y, N, N, N, N, N, N, SelImm.IMM_I), - SD -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.stu, LSUOpType.sd, N, N, N, N, N, N, N, SelImm.IMM_S), - - SLLI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sll, Y, N, N, N, N, N, N, SelImm.IMM_I), - SRLI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.srl, Y, N, N, N, N, N, N, SelImm.IMM_I), - SRAI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sra, Y, N, N, N, N, N, N, SelImm.IMM_I), - - ADDIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.addw, Y, N, N, N, N, N, N, SelImm.IMM_I), - SLLIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sllw, Y, N, N, N, N, N, N, SelImm.IMM_I), - SRAIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sraw, Y, N, N, N, N, N, N, SelImm.IMM_I), - SRLIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.srlw, Y, N, N, N, N, N, N, SelImm.IMM_I), - - ADDW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.addw, Y, N, N, N, N, N, N, SelImm.IMM_X), - SUBW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.subw, Y, N, N, N, N, N, N, SelImm.IMM_X), - SLLW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sllw, Y, N, N, N, N, N, N, SelImm.IMM_X), - SRAW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sraw, Y, N, N, N, N, N, N, SelImm.IMM_X), - SRLW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.srlw, Y, N, N, N, N, N, N, SelImm.IMM_X), - - RORW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.rorw, Y, N, N, N, N, N, N, SelImm.IMM_X), - RORIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.rorw, Y, N, N, N, N, N, N, SelImm.IMM_I), - ROLW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.rolw, Y, N, N, N, N, N, N, SelImm.IMM_X) + LD -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld, Y, N, N, N, N, N, SelImm.IMM_I), + LWU -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lwu, Y, N, N, N, N, N, SelImm.IMM_I), + SD -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sd, N, N, N, N, N, N, SelImm.IMM_S), + + SLLI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sll, Y, N, N, N, N, N, SelImm.IMM_I), + SRLI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srl, Y, N, N, N, N, N, SelImm.IMM_I), + SRAI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sra, Y, N, N, N, N, N, SelImm.IMM_I), + + ADDIW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.addw, Y, N, N, N, N, N, SelImm.IMM_I), + SLLIW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sllw, Y, N, N, N, N, N, SelImm.IMM_I), + SRAIW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sraw, Y, N, N, N, N, N, SelImm.IMM_I), + SRLIW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srlw, Y, N, N, N, N, N, SelImm.IMM_I), + + ADDW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.addw, Y, N, N, N, N, N, SelImm.X), + SUBW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.subw, Y, N, N, N, N, N, SelImm.X), + SLLW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sllw, Y, N, N, N, N, N, SelImm.X), + SRAW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sraw, Y, N, N, N, N, N, SelImm.X), + SRLW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srlw, Y, N, N, N, N, N, SelImm.X), + + RORW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rorw, Y, N, N, N, N, N, SelImm.X), + RORIW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.rorw, Y, N, N, N, N, N, SelImm.IMM_I), + ROLW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rolw, Y, N, N, N, N, N, SelImm.X) ) } @@ -102,147 +102,147 @@ object X64Decode extends DecodeConstants { */ object XDecode extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - LW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lw, Y, N, N, N, N, N, N, SelImm.IMM_I), - LH -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lh, Y, N, N, N, N, N, N, SelImm.IMM_I), - LHU -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lhu, Y, N, N, N, N, N, N, SelImm.IMM_I), - LB -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lb, Y, N, N, N, N, N, N, SelImm.IMM_I), - LBU -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lbu, Y, N, N, N, N, N, N, SelImm.IMM_I), - - SW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.stu, LSUOpType.sw, N, N, N, N, N, N, N, SelImm.IMM_S), - SH -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.stu, LSUOpType.sh, N, N, N, N, N, N, N, SelImm.IMM_S), - SB -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.stu, LSUOpType.sb, N, N, N, N, N, N, N, SelImm.IMM_S), - - LUI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, N, SelImm.IMM_U), - - ADDI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, N, SelImm.IMM_I), - ANDI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.and, Y, N, N, N, N, N, N, SelImm.IMM_I), - ORI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.or, Y, N, N, N, N, N, N, SelImm.IMM_I), - XORI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.xor, Y, N, N, N, N, N, N, SelImm.IMM_I), - SLTI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.slt, Y, N, N, N, N, N, N, SelImm.IMM_I), - SLTIU -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sltu, Y, N, N, N, N, N, N, SelImm.IMM_I), - - SLL -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sll, Y, N, N, N, N, N, N, SelImm.IMM_X), - ADD -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, N, SelImm.IMM_X), - SUB -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sub, Y, N, N, N, N, N, N, SelImm.IMM_X), - SLT -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.slt, Y, N, N, N, N, N, N, SelImm.IMM_X), - SLTU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sltu, Y, N, N, N, N, N, N, SelImm.IMM_X), - AND -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.and, Y, N, N, N, N, N, N, SelImm.IMM_X), - OR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.or, Y, N, N, N, N, N, N, SelImm.IMM_X), - XOR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.xor, Y, N, N, N, N, N, N, SelImm.IMM_X), - SRA -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sra, Y, N, N, N, N, N, N, SelImm.IMM_X), - SRL -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.srl, Y, N, N, N, N, N, N, SelImm.IMM_X), - - MUL -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mul, Y, N, N, N, N, N, N, SelImm.IMM_X), - MULH -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mulh, Y, N, N, N, N, N, N, SelImm.IMM_X), - MULHU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mulhu, Y, N, N, N, N, N, N, SelImm.IMM_X), - MULHSU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mulhsu, Y, N, N, N, N, N, N, SelImm.IMM_X), - MULW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mulw, Y, N, N, N, N, N, N, SelImm.IMM_X), - - DIV -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.div, Y, N, N, N, N, N, N, SelImm.IMM_X), - DIVU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.divu, Y, N, N, N, N, N, N, SelImm.IMM_X), - REM -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.rem, Y, N, N, N, N, N, N, SelImm.IMM_X), - REMU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.remu, Y, N, N, N, N, N, N, SelImm.IMM_X), - DIVW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.divw, Y, N, N, N, N, N, N, SelImm.IMM_X), - DIVUW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.divuw, Y, N, N, N, N, N, N, SelImm.IMM_X), - REMW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.remw, Y, N, N, N, N, N, N, SelImm.IMM_X), - REMUW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.remuw, Y, N, N, N, N, N, N, SelImm.IMM_X), - - AUIPC -> List(SrcType.pc , SrcType.imm, SrcType.DC, FuType.jmp, JumpOpType.auipc, Y, N, N, N, N, N, N, SelImm.IMM_U), - JAL -> List(SrcType.pc , SrcType.imm, SrcType.DC, FuType.jmp, JumpOpType.jal, Y, N, N, N, N, N, N, SelImm.IMM_UJ), - JALR -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.jmp, JumpOpType.jalr, Y, N, N, N, N, N, N, SelImm.IMM_I), - BEQ -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.beq, N, N, N, N, N, N, N, SelImm.IMM_SB), - BNE -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bne, N, N, N, N, N, N, N, SelImm.IMM_SB), - BGE -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bge, N, N, N, N, N, N, N, SelImm.IMM_SB), - BGEU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bgeu, N, N, N, N, N, N, N, SelImm.IMM_SB), - BLT -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.blt, N, N, N, N, N, N, N, SelImm.IMM_SB), - BLTU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bltu, N, N, N, N, N, N, N, SelImm.IMM_SB), + LW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw, Y, N, N, N, N, N, SelImm.IMM_I), + LH -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lh, Y, N, N, N, N, N, SelImm.IMM_I), + LHU -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lhu, Y, N, N, N, N, N, SelImm.IMM_I), + LB -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lb, Y, N, N, N, N, N, SelImm.IMM_I), + LBU -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lbu, Y, N, N, N, N, N, SelImm.IMM_I), + + SW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sw, N, N, N, N, N, N, SelImm.IMM_S), + SH -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sh, N, N, N, N, N, N, SelImm.IMM_S), + SB -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sb, N, N, N, N, N, N, SelImm.IMM_S), + + LUI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, SelImm.IMM_U), + + ADDI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, SelImm.IMM_I), + ANDI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.and, Y, N, N, N, N, N, SelImm.IMM_I), + ORI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.or, Y, N, N, N, N, N, SelImm.IMM_I), + XORI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.xor, Y, N, N, N, N, N, SelImm.IMM_I), + SLTI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slt, Y, N, N, N, N, N, SelImm.IMM_I), + SLTIU -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sltu, Y, N, N, N, N, N, SelImm.IMM_I), + + SLL -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sll, Y, N, N, N, N, N, SelImm.X), + ADD -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, SelImm.X), + SUB -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sub, Y, N, N, N, N, N, SelImm.X), + SLT -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.slt, Y, N, N, N, N, N, SelImm.X), + SLTU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sltu, Y, N, N, N, N, N, SelImm.X), + AND -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.and, Y, N, N, N, N, N, SelImm.X), + OR -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.or, Y, N, N, N, N, N, SelImm.X), + XOR -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xor, Y, N, N, N, N, N, SelImm.X), + SRA -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sra, Y, N, N, N, N, N, SelImm.X), + SRL -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srl, Y, N, N, N, N, N, SelImm.X), + + MUL -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mul, Y, N, N, N, N, N, SelImm.X), + MULH -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulh, Y, N, N, N, N, N, SelImm.X), + MULHU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhu, Y, N, N, N, N, N, SelImm.X), + MULHSU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhsu, Y, N, N, N, N, N, SelImm.X), + MULW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulw, Y, N, N, N, N, N, SelImm.X), + + DIV -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.div, Y, N, N, N, N, N, SelImm.X), + DIVU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divu, Y, N, N, N, N, N, SelImm.X), + REM -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.rem, Y, N, N, N, N, N, SelImm.X), + REMU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remu, Y, N, N, N, N, N, SelImm.X), + DIVW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divw, Y, N, N, N, N, N, SelImm.X), + DIVUW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divuw, Y, N, N, N, N, N, SelImm.X), + REMW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remw, Y, N, N, N, N, N, SelImm.X), + REMUW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remuw, Y, N, N, N, N, N, SelImm.X), + + AUIPC -> List(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.auipc, Y, N, N, N, N, N, SelImm.IMM_U), + JAL -> List(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jal, Y, N, N, N, N, N, SelImm.IMM_UJ), + JALR -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jalr, Y, N, N, N, N, N, SelImm.IMM_I), + BEQ -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.beq, N, N, N, N, N, N, SelImm.IMM_SB), + BNE -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bne, N, N, N, N, N, N, SelImm.IMM_SB), + BGE -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bge, N, N, N, N, N, N, SelImm.IMM_SB), + BGEU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bgeu, N, N, N, N, N, N, SelImm.IMM_SB), + BLT -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.blt, N, N, N, N, N, N, SelImm.IMM_SB), + BLTU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bltu, N, N, N, N, N, N, SelImm.IMM_SB), // I-type, the immediate12 holds the CSR register. - CSRRW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.wrt, Y, N, N, Y, Y, N, N, SelImm.IMM_I), - CSRRS -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.set, Y, N, N, Y, Y, N, N, SelImm.IMM_I), - CSRRC -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.clr, Y, N, N, Y, Y, N, N, SelImm.IMM_I), + CSRRW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrt, Y, N, N, Y, Y, N, SelImm.IMM_I), + CSRRS -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.set, Y, N, N, Y, Y, N, SelImm.IMM_I), + CSRRC -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clr, Y, N, N, Y, Y, N, SelImm.IMM_I), - CSRRWI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.wrti, Y, N, N, Y, Y, N, N, SelImm.IMM_Z), - CSRRSI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.seti, Y, N, N, Y, Y, N, N, SelImm.IMM_Z), - CSRRCI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.clri, Y, N, N, Y, Y, N, N, SelImm.IMM_Z), + CSRRWI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrti, Y, N, N, Y, Y, N, SelImm.IMM_Z), + CSRRSI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.seti, Y, N, N, Y, Y, N, SelImm.IMM_Z), + CSRRCI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clri, Y, N, N, Y, Y, N, SelImm.IMM_Z), - SFENCE_VMA->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.fence, FenceOpType.sfence, N, N, N, Y, Y, Y, N, SelImm.IMM_X), - EBREAK -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, N, SelImm.IMM_I), - ECALL -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, N, SelImm.IMM_I), - SRET -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, N, SelImm.IMM_I), - MRET -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, N, SelImm.IMM_I), - DRET -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, N, SelImm.IMM_I), + SFENCE_VMA->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, N, N, N, Y, Y, Y, SelImm.X), + EBREAK -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, SelImm.IMM_I), + ECALL -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, SelImm.IMM_I), + SRET -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, SelImm.IMM_I), + MRET -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, SelImm.IMM_I), + DRET -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, SelImm.IMM_I), - WFI -> List(SrcType.pc, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.wfi, Y, N, N, Y, Y, N, N, SelImm.IMM_X), + WFI -> List(SrcType.pc, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wfi, Y, N, N, Y, Y, N, SelImm.X), - FENCE_I -> List(SrcType.pc, SrcType.imm, SrcType.DC, FuType.fence, FenceOpType.fencei, N, N, N, Y, Y, Y, N, SelImm.IMM_X), - FENCE -> List(SrcType.pc, SrcType.imm, SrcType.DC, FuType.fence, FenceOpType.fence, N, N, N, Y, Y, Y, N, SelImm.IMM_X), + FENCE_I -> List(SrcType.pc, SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fencei, N, N, N, Y, Y, Y, SelImm.X), + FENCE -> List(SrcType.pc, SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fence, N, N, N, Y, Y, Y, SelImm.X), // A-type - AMOADD_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoadd_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOXOR_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoxor_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOSWAP_W->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoswap_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOAND_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoand_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOOR_W -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoor_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOMIN_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomin_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOMINU_W->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amominu_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOMAX_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomax_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOMAXU_W->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomaxu_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - - AMOADD_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoadd_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOXOR_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoxor_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOSWAP_D->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoswap_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOAND_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoand_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOOR_D -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoor_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOMIN_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomin_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOMINU_D->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amominu_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOMAX_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomax_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - AMOMAXU_D->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomaxu_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - - LR_W -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.mou, LSUOpType.lr_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - LR_D -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.mou, LSUOpType.lr_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - SC_W -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.sc_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - SC_D -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.sc_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), - - ANDN -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.andn, Y, N, N, N, N, N, N, SelImm.IMM_X), - ORN -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.orn, Y, N, N, N, N, N, N, SelImm.IMM_X), - XNOR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.xnor, Y, N, N, N, N, N, N, SelImm.IMM_X), - ORC_B -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.alu, ALUOpType.orcb, Y, N, N, N, N, N, N, SelImm.IMM_X), - - MIN -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.min, Y, N, N, N, N, N, N, SelImm.IMM_X), - MINU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.minu, Y, N, N, N, N, N, N, SelImm.IMM_X), - MAX -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.max, Y, N, N, N, N, N, N, SelImm.IMM_X), - MAXU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.maxu, Y, N, N, N, N, N, N, SelImm.IMM_X), - - SEXT_B -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.alu, ALUOpType.sextb, Y, N, N, N, N, N, N, SelImm.IMM_X), - PACKH -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.packh, Y, N, N, N, N, N, N, SelImm.IMM_X), - SEXT_H -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.alu, ALUOpType.sexth, Y, N, N, N, N, N, N, SelImm.IMM_X), - PACKW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.packw, Y, N, N, N, N, N, N, SelImm.IMM_X), - BREV8 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.alu, ALUOpType.revb, Y, N, N, N, N, N, N, SelImm.IMM_X), - REV8 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.alu, ALUOpType.rev8, Y, N, N, N, N, N, N, SelImm.IMM_X), - PACK -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.pack, Y, N, N, N, N, N, N, SelImm.IMM_X), - - BSET -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bset, Y, N, N, N, N, N, N, SelImm.IMM_X), - BSETI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.bset, Y, N, N, N, N, N, N, SelImm.IMM_I), - BCLR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bclr, Y, N, N, N, N, N, N, SelImm.IMM_X), - BCLRI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.bclr, Y, N, N, N, N, N, N, SelImm.IMM_I), - BINV -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.binv, Y, N, N, N, N, N, N, SelImm.IMM_X), - BINVI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.binv, Y, N, N, N, N, N, N, SelImm.IMM_I), - BEXT -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bext, Y, N, N, N, N, N, N, SelImm.IMM_X), - BEXTI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.bext, Y, N, N, N, N, N, N, SelImm.IMM_I), - - ROR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.ror, Y, N, N, N, N, N, N, SelImm.IMM_X), - RORI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.ror, Y, N, N, N, N, N, N, SelImm.IMM_I), - ROL -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.rol, Y, N, N, N, N, N, N, SelImm.IMM_X), - - SH1ADD -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh1add, Y, N, N, N, N, N, N, SelImm.IMM_X), - SH2ADD -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh2add, Y, N, N, N, N, N, N, SelImm.IMM_X), - SH3ADD -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh3add, Y, N, N, N, N, N, N, SelImm.IMM_X), - SH1ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh1adduw, Y, N, N, N, N, N, N, SelImm.IMM_X), - SH2ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh2adduw, Y, N, N, N, N, N, N, SelImm.IMM_X), - SH3ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sh3adduw, Y, N, N, N, N, N, N, SelImm.IMM_X), - ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.adduw, Y, N, N, N, N, N, N, SelImm.IMM_X), - SLLI_UW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.slliuw, Y, N, N, N, N, N, N, SelImm.IMM_I) + AMOADD_W-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_w, Y, N, N, Y, Y, N, SelImm.X), + AMOXOR_W-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_w, Y, N, N, Y, Y, N, SelImm.X), + AMOSWAP_W->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_w, Y, N, N, Y, Y, N, SelImm.X), + AMOAND_W-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_w, Y, N, N, Y, Y, N, SelImm.X), + AMOOR_W -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_w, Y, N, N, Y, Y, N, SelImm.X), + AMOMIN_W-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_w, Y, N, N, Y, Y, N, SelImm.X), + AMOMINU_W->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_w, Y, N, N, Y, Y, N, SelImm.X), + AMOMAX_W-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_w, Y, N, N, Y, Y, N, SelImm.X), + AMOMAXU_W->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_w, Y, N, N, Y, Y, N, SelImm.X), + + AMOADD_D-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_d, Y, N, N, Y, Y, N, SelImm.X), + AMOXOR_D-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_d, Y, N, N, Y, Y, N, SelImm.X), + AMOSWAP_D->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_d, Y, N, N, Y, Y, N, SelImm.X), + AMOAND_D-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_d, Y, N, N, Y, Y, N, SelImm.X), + AMOOR_D -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_d, Y, N, N, Y, Y, N, SelImm.X), + AMOMIN_D-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_d, Y, N, N, Y, Y, N, SelImm.X), + AMOMINU_D->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_d, Y, N, N, Y, Y, N, SelImm.X), + AMOMAX_D-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_d, Y, N, N, Y, Y, N, SelImm.X), + AMOMAXU_D->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_d, Y, N, N, Y, Y, N, SelImm.X), + + LR_W -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_w, Y, N, N, Y, Y, N, SelImm.X), + LR_D -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_d, Y, N, N, Y, Y, N, SelImm.X), + SC_W -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_w, Y, N, N, Y, Y, N, SelImm.X), + SC_D -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_d, Y, N, N, Y, Y, N, SelImm.X), + + ANDN -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.andn, Y, N, N, N, N, N, SelImm.X), + ORN -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.orn, Y, N, N, N, N, N, SelImm.X), + XNOR -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xnor, Y, N, N, N, N, N, SelImm.X), + ORC_B -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.orcb, Y, N, N, N, N, N, SelImm.X), + + MIN -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.min, Y, N, N, N, N, N, SelImm.X), + MINU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.minu, Y, N, N, N, N, N, SelImm.X), + MAX -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.max, Y, N, N, N, N, N, SelImm.X), + MAXU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.maxu, Y, N, N, N, N, N, SelImm.X), + + SEXT_B -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sextb, Y, N, N, N, N, N, SelImm.X), + PACKH -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packh, Y, N, N, N, N, N, SelImm.X), + SEXT_H -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sexth, Y, N, N, N, N, N, SelImm.X), + PACKW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packw, Y, N, N, N, N, N, SelImm.X), + BREV8 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.revb, Y, N, N, N, N, N, SelImm.X), + REV8 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.rev8, Y, N, N, N, N, N, SelImm.X), + PACK -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.pack, Y, N, N, N, N, N, SelImm.X), + + BSET -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bset, Y, N, N, N, N, N, SelImm.X), + BSETI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bset, Y, N, N, N, N, N, SelImm.IMM_I), + BCLR -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bclr, Y, N, N, N, N, N, SelImm.X), + BCLRI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bclr, Y, N, N, N, N, N, SelImm.IMM_I), + BINV -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.binv, Y, N, N, N, N, N, SelImm.X), + BINVI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.binv, Y, N, N, N, N, N, SelImm.IMM_I), + BEXT -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bext, Y, N, N, N, N, N, SelImm.X), + BEXTI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bext, Y, N, N, N, N, N, SelImm.IMM_I), + + ROR -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.ror, Y, N, N, N, N, N, SelImm.X), + RORI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.ror, Y, N, N, N, N, N, SelImm.IMM_I), + ROL -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rol, Y, N, N, N, N, N, SelImm.X), + + SH1ADD -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1add, Y, N, N, N, N, N, SelImm.X), + SH2ADD -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2add, Y, N, N, N, N, N, SelImm.X), + SH3ADD -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3add, Y, N, N, N, N, N, SelImm.X), + SH1ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1adduw, Y, N, N, N, N, N, SelImm.X), + SH2ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2adduw, Y, N, N, N, N, N, SelImm.X), + SH3ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3adduw, Y, N, N, N, N, N, SelImm.X), + ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.adduw, Y, N, N, N, N, N, SelImm.X), + SLLI_UW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slliuw, Y, N, N, N, N, N, SelImm.IMM_I) ) } @@ -252,81 +252,81 @@ object XDecode extends DecodeConstants { object FDecode extends DecodeConstants{ val table: Array[(BitPat, List[BitPat])] = Array( - FLW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lw, N, Y, N, N, N, N, Y, SelImm.IMM_I), - FLD -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.ld, N, Y, N, N, N, N, N, SelImm.IMM_I), - FSW -> List(SrcType.reg, SrcType.fp, SrcType.DC, FuType.stu, LSUOpType.sw, N, N, N, N, N, N, Y, SelImm.IMM_S), - FSD -> List(SrcType.reg, SrcType.fp, SrcType.DC, FuType.stu, LSUOpType.sd, N, N, N, N, N, N, N, SelImm.IMM_S), + FLW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw, N, Y, N, N, N, N, SelImm.IMM_I), + FLD -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld, N, Y, N, N, N, N, SelImm.IMM_I), + FSW -> List(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sw, N, N, N, N, N, N, SelImm.IMM_S), + FSD -> List(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sd, N, N, N, N, N, N, SelImm.IMM_S), - FCLASS_S-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), - FCLASS_D-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), + FCLASS_S-> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + FCLASS_D-> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), - FMV_D_X -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - FMV_X_D -> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), - FMV_X_W -> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), - FMV_W_X -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), + FMV_D_X -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FMV_X_D -> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + FMV_X_W -> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + FMV_W_X -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), - FSGNJ_S -> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FSGNJ_D -> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - FSGNJX_S-> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FSGNJX_D-> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - FSGNJN_S-> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FSGNJN_D-> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), + FSGNJ_S -> List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FSGNJ_D -> List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FSGNJX_S-> List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FSGNJX_D-> List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FSGNJN_S-> List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FSGNJN_D-> List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), // FP to FP - FCVT_S_D-> List(SrcType.fp, SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FCVT_D_S-> List(SrcType.fp, SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), + FCVT_S_D-> List(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FCVT_D_S-> List(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), // Int to FP - FCVT_S_W-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FCVT_S_WU->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FCVT_S_L-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FCVT_S_LU->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), + FCVT_S_W-> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FCVT_S_WU->List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FCVT_S_L-> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FCVT_S_LU->List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), - FCVT_D_W-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - FCVT_D_WU->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - FCVT_D_L-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - FCVT_D_LU->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), + FCVT_D_W-> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FCVT_D_WU->List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FCVT_D_L-> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FCVT_D_LU->List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), // FP to Int - FCVT_W_S-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), - FCVT_WU_S->List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), - FCVT_L_S-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), - FCVT_LU_S->List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), + FCVT_W_S-> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + FCVT_WU_S->List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + FCVT_L_S-> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + FCVT_LU_S->List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), - FCVT_W_D-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), - FCVT_WU_D->List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), - FCVT_L_D-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), - FCVT_LU_D->List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), + FCVT_W_D-> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + FCVT_WU_D->List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + FCVT_L_D-> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + FCVT_LU_D->List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), // "fp_single" is used for wb_data formatting (and debugging) - FEQ_S ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), - FLT_S ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), - FLE_S ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, Y, SelImm.IMM_X), - - FEQ_D ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), - FLT_D ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), - FLE_D ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, N, SelImm.IMM_X), - - FMIN_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FMAX_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FMIN_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - FMAX_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - - FADD_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FMUL_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FADD_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - FSUB_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - FMUL_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - - FMADD_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FMSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FNMADD_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FNMSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FMADD_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - FMSUB_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - FNMADD_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - FNMSUB_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X) + FEQ_S ->List(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + FLT_S ->List(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + FLE_S ->List(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + + FEQ_D ->List(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + FLT_D ->List(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + FLE_D ->List(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), + + FMIN_S ->List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FMAX_S ->List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FMIN_D ->List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FMAX_D ->List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + + FADD_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FMUL_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FADD_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FSUB_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FMUL_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + + FMADD_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FMSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FNMADD_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FNMSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FMADD_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FMSUB_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FNMADD_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FNMSUB_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X) ) } @@ -336,45 +336,45 @@ object FDecode extends DecodeConstants{ object BDecode extends DecodeConstants{ val table: Array[(BitPat, List[BitPat])] = Array( // Basic bit manipulation - CLZ -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.clz, Y, N, N, N, N, N, N, SelImm.IMM_X), - CTZ -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.ctz, Y, N, N, N, N, N, N, SelImm.IMM_X), - CPOP -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.cpop, Y, N, N, N, N, N, N, SelImm.IMM_X), - XPERM8 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.xpermb, Y, N, N, N, N, N, N, SelImm.IMM_X), - XPERM4 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.xpermn, Y, N, N, N, N, N, N, SelImm.IMM_X), - - CLZW -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.clzw, Y, N, N, N, N, N, N, SelImm.IMM_X), - CTZW -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.ctzw, Y, N, N, N, N, N, N, SelImm.IMM_X), - CPOPW -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.cpopw, Y, N, N, N, N, N, N, SelImm.IMM_X), - - CLMUL -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.clmul, Y, N, N, N, N, N, N, SelImm.IMM_X), - CLMULH -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.clmulh, Y, N, N, N, N, N, N, SelImm.IMM_X), - CLMULR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.clmulr, Y, N, N, N, N, N, N, SelImm.IMM_X), - - AES64ES -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.aes64es, Y, N, N, N, N, N, N, SelImm.IMM_X), - AES64ESM -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.aes64esm, Y, N, N, N, N, N, N, SelImm.IMM_X), - AES64DS -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.aes64ds, Y, N, N, N, N, N, N, SelImm.IMM_X), - AES64DSM -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.aes64dsm, Y, N, N, N, N, N, N, SelImm.IMM_X), - AES64IM -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.aes64im, Y, N, N, N, N, N, N, SelImm.IMM_X), - AES64KS1I -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.bku, BKUOpType.aes64ks1i, Y, N, N, N, N, N, N, SelImm.IMM_I), - AES64KS2 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.aes64ks2, Y, N, N, N, N, N, N, SelImm.IMM_X), - SHA256SUM0 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha256sum0, Y, N, N, N, N, N, N, SelImm.IMM_X), - SHA256SUM1 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha256sum1, Y, N, N, N, N, N, N, SelImm.IMM_X), - SHA256SIG0 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha256sig0, Y, N, N, N, N, N, N, SelImm.IMM_X), - SHA256SIG1 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha256sig1, Y, N, N, N, N, N, N, SelImm.IMM_X), - SHA512SUM0 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha512sum0, Y, N, N, N, N, N, N, SelImm.IMM_X), - SHA512SUM1 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha512sum1, Y, N, N, N, N, N, N, SelImm.IMM_X), - SHA512SIG0 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha512sig0, Y, N, N, N, N, N, N, SelImm.IMM_X), - SHA512SIG1 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sha512sig1, Y, N, N, N, N, N, N, SelImm.IMM_X), - SM3P0 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sm3p0, Y, N, N, N, N, N, N, SelImm.IMM_X), - SM3P1 -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.bku, BKUOpType.sm3p1, Y, N, N, N, N, N, N, SelImm.IMM_X), - SM4KS0 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ks0, Y, N, N, N, N, N, N, SelImm.IMM_X), - SM4KS1 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ks1, Y, N, N, N, N, N, N, SelImm.IMM_X), - SM4KS2 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ks2, Y, N, N, N, N, N, N, SelImm.IMM_X), - SM4KS3 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ks3, Y, N, N, N, N, N, N, SelImm.IMM_X), - SM4ED0 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ed0, Y, N, N, N, N, N, N, SelImm.IMM_X), - SM4ED1 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ed1, Y, N, N, N, N, N, N, SelImm.IMM_X), - SM4ED2 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ed2, Y, N, N, N, N, N, N, SelImm.IMM_X), - SM4ED3 -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.bku, BKUOpType.sm4ed3, Y, N, N, N, N, N, N, SelImm.IMM_X), + CLZ -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clz, Y, N, N, N, N, N, SelImm.X), + CTZ -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctz, Y, N, N, N, N, N, SelImm.X), + CPOP -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpop, Y, N, N, N, N, N, SelImm.X), + XPERM8 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermb, Y, N, N, N, N, N, SelImm.X), + XPERM4 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermn, Y, N, N, N, N, N, SelImm.X), + + CLZW -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clzw, Y, N, N, N, N, N, SelImm.X), + CTZW -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctzw, Y, N, N, N, N, N, SelImm.X), + CPOPW -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpopw, Y, N, N, N, N, N, SelImm.X), + + CLMUL -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmul, Y, N, N, N, N, N, SelImm.X), + CLMULH -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulh, Y, N, N, N, N, N, SelImm.X), + CLMULR -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulr, Y, N, N, N, N, N, SelImm.X), + + AES64ES -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64es, Y, N, N, N, N, N, SelImm.X), + AES64ESM -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64esm, Y, N, N, N, N, N, SelImm.X), + AES64DS -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ds, Y, N, N, N, N, N, SelImm.X), + AES64DSM -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64dsm, Y, N, N, N, N, N, SelImm.X), + AES64IM -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.aes64im, Y, N, N, N, N, N, SelImm.X), + AES64KS1I -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.bku, BKUOpType.aes64ks1i, Y, N, N, N, N, N, SelImm.IMM_I), + AES64KS2 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ks2, Y, N, N, N, N, N, SelImm.X), + SHA256SUM0 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum0, Y, N, N, N, N, N, SelImm.X), + SHA256SUM1 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum1, Y, N, N, N, N, N, SelImm.X), + SHA256SIG0 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig0, Y, N, N, N, N, N, SelImm.X), + SHA256SIG1 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig1, Y, N, N, N, N, N, SelImm.X), + SHA512SUM0 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum0, Y, N, N, N, N, N, SelImm.X), + SHA512SUM1 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum1, Y, N, N, N, N, N, SelImm.X), + SHA512SIG0 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig0, Y, N, N, N, N, N, SelImm.X), + SHA512SIG1 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig1, Y, N, N, N, N, N, SelImm.X), + SM3P0 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p0, Y, N, N, N, N, N, SelImm.X), + SM3P1 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p1, Y, N, N, N, N, N, SelImm.X), + SM4KS0 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks0, Y, N, N, N, N, N, SelImm.X), + SM4KS1 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks1, Y, N, N, N, N, N, SelImm.X), + SM4KS2 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks2, Y, N, N, N, N, N, SelImm.X), + SM4KS3 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks3, Y, N, N, N, N, N, SelImm.X), + SM4ED0 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed0, Y, N, N, N, N, N, SelImm.X), + SM4ED1 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed1, Y, N, N, N, N, N, SelImm.X), + SM4ED2 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed2, Y, N, N, N, N, N, SelImm.X), + SM4ED3 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed3, Y, N, N, N, N, N, SelImm.X), ) } @@ -383,10 +383,10 @@ object BDecode extends DecodeConstants{ */ object FDivSqrtDecode extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - FDIV_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FDIV_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X), - FSQRT_S ->List(SrcType.fp, SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, Y, SelImm.IMM_X), - FSQRT_D ->List(SrcType.fp, SrcType.imm, SrcType.DC, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, N, SelImm.IMM_X) + FDIV_S ->List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FDIV_D ->List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FSQRT_S ->List(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), + FSQRT_D ->List(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X) ) } @@ -398,19 +398,19 @@ object SvinvalDecode extends DecodeConstants { /* sinval_vma is like sfence.vma , but sinval_vma can be dispatched and issued like normal instructions while sfence.vma * must assure it is the ONLY instrucion executing in backend. */ - SINVAL_VMA ->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.fence, FenceOpType.sfence, N, N, N, N, N, N, N, SelImm.IMM_X), + SINVAL_VMA ->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, N, N, N, N, N, N, SelImm.X), /* sfecne.w.inval is the begin instrucion of a TLB flush which set *noSpecExec* and *blockBackward* signals * so when it comes to dispatch , it will block all instruction after itself until all instrucions ahead of it in rob commit * then dispatch and issue this instrucion to flush sbuffer to dcache * after this instrucion commits , issue following sinval_vma instructions (out of order) to flush TLB */ - SFENCE_W_INVAL ->List(SrcType.DC, SrcType.DC, SrcType.DC, FuType.fence, FenceOpType.nofence, N, N, N, Y, Y, N, N, SelImm.IMM_X), + SFENCE_W_INVAL ->List(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, N, N, N, Y, Y, N, SelImm.X), /* sfecne.inval.ir is the end instrucion of a TLB flush which set *noSpecExec* *blockBackward* and *flushPipe* signals * so when it comes to dispatch , it will wait until all sinval_vma ahead of it in rob commit * then dispatch and issue this instrucion * when it commit at the head of rob , flush the pipeline since some instrucions have been fetched to ibuffer using old TLB map */ - SFENCE_INVAL_IR ->List(SrcType.DC, SrcType.DC, SrcType.DC, FuType.fence, FenceOpType.nofence, N, N, N, Y, Y, Y, N, SelImm.IMM_X) + SFENCE_INVAL_IR ->List(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, N, N, N, Y, Y, Y, SelImm.X) /* what is Svinval extension ? * -----> sfecne.w.inval * sfence.vma vpn1 -----> sinval_vma vpn1 @@ -427,10 +427,10 @@ object SvinvalDecode extends DecodeConstants { */ object CBODecode extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( - CBO_ZERO -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.stu, LSUOpType.cbo_zero , N, N, N, N, N, N, N, SelImm.IMM_S), - CBO_CLEAN -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.stu, LSUOpType.cbo_clean, N, N, N, N, N, N, N, SelImm.IMM_S), - CBO_FLUSH -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.stu, LSUOpType.cbo_flush, N, N, N, N, N, N, N, SelImm.IMM_S), - CBO_INVAL -> List(SrcType.reg, SrcType.DC, SrcType.DC, FuType.stu, LSUOpType.cbo_inval, N, N, N, N, N, N, N, SelImm.IMM_S) + CBO_ZERO -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_zero , N, N, N, N, N, N, SelImm.IMM_S), + CBO_CLEAN -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_clean, N, N, N, N, N, N, SelImm.IMM_S), + CBO_FLUSH -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_flush, N, N, N, N, N, N, SelImm.IMM_S), + CBO_INVAL -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_inval, N, N, N, N, N, N, SelImm.IMM_S) ) } @@ -439,11 +439,8 @@ object CBODecode extends DecodeConstants { */ object XSTrapDecode extends DecodeConstants { def TRAP = BitPat("b000000000000?????000000001101011") - // calculate as ADDI => addi zero, a0, 0 - // replace rs '?????' with '01010'(a0) in decode stage - def lsrc1 = "b01010".U // $a0 val table: Array[(BitPat, List[BitPat])] = Array( - TRAP -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, Y, Y, Y, N, N, SelImm.IMM_I) + TRAP -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add, Y, N, Y, Y, Y, N, SelImm.IMM_I) ) } @@ -595,7 +592,7 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan // output cf_ctrl.cf := ctrl_flow - val cs = Wire(new CtrlSignals()).decode(ctrl_flow.instr, decode_table) + val cs: CtrlSignals = Wire(new CtrlSignals()).decode(ctrl_flow.instr, decode_table) cs.singleStep := false.B cs.replayInst := false.B @@ -634,11 +631,6 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan cs.blockBackward := false.B } - // fix isXSTrap - when (cs.isXSTrap) { - cs.lsrc(0) := XSTrapDecode.lsrc1 - } - //to selectout prefetch.r/prefetch.w val isORI = BitPat("b?????????????????110?????0010011") === ctrl_flow.instr when(isORI && io.csrCtrl.soft_prefetch_enable) { @@ -686,10 +678,10 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan io.deq.cf_ctrl.ctrl.srcType(0), io.deq.cf_ctrl.ctrl.srcType(1), io.deq.cf_ctrl.ctrl.srcType(2), io.deq.cf_ctrl.ctrl.lsrc(0), io.deq.cf_ctrl.ctrl.lsrc(1), io.deq.cf_ctrl.ctrl.lsrc(2), io.deq.cf_ctrl.ctrl.ldest, io.deq.cf_ctrl.ctrl.fuType, io.deq.cf_ctrl.ctrl.fuOpType) - XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d flushPipe=%d isRVF=%d imm=%x\n", + XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d flushPipe=%d imm=%x\n", io.deq.cf_ctrl.ctrl.rfWen, io.deq.cf_ctrl.ctrl.fpWen, io.deq.cf_ctrl.ctrl.isXSTrap, io.deq.cf_ctrl.ctrl.noSpecExec, io.deq.cf_ctrl.ctrl.blockBackward, io.deq.cf_ctrl.ctrl.flushPipe, - io.deq.cf_ctrl.ctrl.isRVF, io.deq.cf_ctrl.ctrl.imm) + io.deq.cf_ctrl.ctrl.imm) XSDebug("out: excepVec=%b intrVec=%b\n", io.deq.cf_ctrl.cf.exceptionVec.asUInt, io.deq.cf_ctrl.cf.intrVec.asUInt) } diff --git a/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala b/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala index abe7c5e437d3c861757cf9b927b56ae9d788b5d3..ee9f57c37f51b2a4a89829eefdf132ff96cbc9d7 100644 --- a/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala +++ b/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala @@ -45,9 +45,7 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int)(implicit p: Parameters) val s_invalid :: s_valid :: Nil = Enum(2) // queue data array - val dataModule = Module(new SyncDataModuleTemplate(new MicroOp, size, deqnum, enqnum)) - val robIdxEntries = Reg(Vec(size, new RobPtr)) - val debug_uopEntries = Mem(size, new MicroOp) + val data = Reg(Vec(size, new MicroOp)) val stateEntries = RegInit(VecInit(Seq.fill(size)(s_invalid))) class DispatchQueuePtr extends CircularQueuePtr[DispatchQueuePtr](size) @@ -55,14 +53,20 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int)(implicit p: Parameters) // head: first valid entry (dispatched entry) val headPtr = RegInit(VecInit((0 until deqnum).map(_.U.asTypeOf(new DispatchQueuePtr)))) val headPtrMask = UIntToMask(headPtr(0).value, size) + val headPtrOH = RegInit(1.U(size.W)) + val headPtrOHShift = CircularShift(headPtrOH) + val headPtrOHVec = VecInit.tabulate(deqnum + 1)(headPtrOHShift.left) // tail: first invalid entry (free entry) val tailPtr = RegInit(VecInit((0 until enqnum).map(_.U.asTypeOf(new DispatchQueuePtr)))) val tailPtrMask = UIntToMask(tailPtr(0).value, size) + val tailPtrOH = RegInit(1.U(size.W)) + val tailPtrOHShift = CircularShift(tailPtrOH) + val tailPtrOHVec = VecInit.tabulate(enqnum + 1)(tailPtrOHShift.left) // valid entries counter val validCounter = RegInit(0.U(log2Ceil(size + 1).W)) val allowEnqueue = RegInit(true.B) - val isTrueEmpty = ~Cat((0 until size).map(i => stateEntries(i) === s_valid)).orR + val isTrueEmpty = !VecInit(stateEntries.map(_ === s_valid)).asUInt.orR val canEnqueue = allowEnqueue val canActualEnqueue = canEnqueue && !io.redirect.valid @@ -80,41 +84,34 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int)(implicit p: Parameters) */ // enqueue: from s_invalid to s_valid io.enq.canAccept := canEnqueue - dataModule.io.wen := VecInit((0 until enqnum).map(_ => false.B)) - dataModule.io.waddr := DontCare - dataModule.io.wdata := VecInit(io.enq.req.map(_.bits)) - for (i <- 0 until enqnum) { - when(io.enq.req(i).valid && canActualEnqueue) { - dataModule.io.wen(i) := true.B - val sel = if (i == 0) 0.U else PopCount(io.enq.needAlloc.take(i)) - dataModule.io.waddr(i) := tailPtr(sel).value - robIdxEntries(tailPtr(sel).value) := io.enq.req(i).bits.robIdx - debug_uopEntries(tailPtr(sel).value) := io.enq.req(i).bits - stateEntries(tailPtr(sel).value) := s_valid - XSError(sel =/= PopCount(io.enq.req.take(i).map(_.valid)), "why not continuous??\n") + val enqIndexOH = (0 until enqnum).map(i => tailPtrOHVec(PopCount(io.enq.needAlloc.take(i)))) + for (i <- 0 until size) { + val validVec = io.enq.req.map(_.valid).zip(enqIndexOH).map{ case (v, oh) => v && oh(i) } + when (VecInit(validVec).asUInt.orR && canActualEnqueue) { + data(i) := Mux1H(validVec, io.enq.req.map(_.bits)) + stateEntries(i) := s_valid } } // dequeue: from s_valid to s_dispatched - for (i <- 0 until deqnum) { - when(io.deq(i).fire() && !io.redirect.valid) { - stateEntries(headPtr(i).value) := s_invalid - - // XSError(stateEntries(headPtr(i).value) =/= s_valid, "state of the dispatch entry is not s_valid\n") + for (i <- 0 until size) { + val validVec = io.deq.map(_.fire).zip(headPtrOHVec).map{ case (v, oh) => v && oh(i) } + when (VecInit(validVec).asUInt.orR && !io.redirect.valid) { + stateEntries(i) := s_invalid } } // redirect: cancel uops currently in the queue val needCancel = Wire(Vec(size, Bool())) for (i <- 0 until size) { - needCancel(i) := stateEntries(i) =/= s_invalid && robIdxEntries(i).needFlush(io.redirect) + needCancel(i) := stateEntries(i) =/= s_invalid && data(i).robIdx.needFlush(io.redirect) when(needCancel(i)) { stateEntries(i) := s_invalid } - XSInfo(needCancel(i), p"valid entry($i)(pc = ${Hexadecimal(debug_uopEntries(i).cf.pc)}) " + - p"robIndex ${robIdxEntries(i)} " + + XSInfo(needCancel(i), p"valid entry($i)(pc = ${Hexadecimal(data(i).cf.pc)}) " + + p"robIndex ${data(i).robIdx} " + p"cancelled with redirect robIndex 0x${Hexadecimal(io.redirect.bits.robIdx.asUInt)}\n") } @@ -132,7 +129,7 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int)(implicit p: Parameters) // For dequeue, the first entry should never be s_invalid // Otherwise, there should be a redirect and tail walks back // in this case, we set numDeq to 0 - !deq.fire() && (if (i == 0) true.B else stateEntries(headPtr(i).value) =/= s_invalid) + !deq.fire && (if (i == 0) true.B else stateEntries(headPtr(i).value) =/= s_invalid) } :+ true.B) val numDeq = Mux(numDeqTry > numDeqFire, numDeqFire, numDeqTry) // agreement with reservation station: don't dequeue when redirect.valid @@ -141,6 +138,8 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int)(implicit p: Parameters) nextHeadPtr(i) := Mux(io.redirect.valid, headPtr(i), headPtr(i) + numDeq) headPtr(i) := nextHeadPtr(i) } + headPtrOH := Mux(io.redirect.valid, headPtrOH, headPtrOHVec(numDeq)) + XSError(headPtrOH =/= headPtr.head.toOH, p"head: $headPtrOH != UIntToOH(${headPtr.head})") // For branch mis-prediction or memory violation replay, // we delay updating the indices for one clock cycle. @@ -149,7 +148,7 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int)(implicit p: Parameters) // find the last one's position, starting from headPtr and searching backwards val validBitVec = VecInit((0 until size).map(i => stateEntries(i) === s_valid)) val loValidBitVec = Cat((0 until size).map(i => validBitVec(i) && headPtrMask(i))) - val hiValidBitVec = Cat((0 until size).map(i => validBitVec(i) && ~headPtrMask(i))) + val hiValidBitVec = Cat((0 until size).map(i => validBitVec(i) && !headPtrMask(i))) val flippedFlag = loValidBitVec.orR || validBitVec(size - 1) val leadingZeros = PriorityEncoder(Mux(loValidBitVec.orR, loValidBitVec, hiValidBitVec)) val lastOneIndex = Mux(leadingZeros === 0.U, 0.U, size.U - leadingZeros) @@ -174,6 +173,9 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int)(implicit p: Parameters) tailPtr(i) + numEnq) ) } + tailPtrOH := Mux(lastLastCycleMisprediction, tailPtr.head.toOH, tailPtrOHVec(numEnq)) + val tailPtrOHAccurate = !lastCycleMisprediction && !lastLastCycleMisprediction + XSError(tailPtrOHAccurate && tailPtrOH =/= tailPtr.head.toOH, p"tail: $tailPtrOH != UIntToOH(${tailPtr.head})") // update valid counter and allowEnqueue reg validCounter := Mux(io.redirect.valid, @@ -187,14 +189,10 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int)(implicit p: Parameters) /** * Part 3: set output and input */ - // TODO: remove this when replay moves to rob - dataModule.io.raddr := VecInit(nextHeadPtr.map(_.value)) for (i <- 0 until deqnum) { - io.deq(i).bits := dataModule.io.rdata(i) - io.deq(i).bits.robIdx := robIdxEntries(headPtr(i).value) - // io.deq(i).bits := debug_uopEntries(headPtr(i).value) + io.deq(i).bits := Mux1H(headPtrOHVec(i), data) // do not dequeue when io.redirect valid because it may cause dispatchPtr work improperly - io.deq(i).valid := stateEntries(headPtr(i).value) === s_valid && !lastCycleMisprediction + io.deq(i).valid := Mux1H(headPtrOHVec(i), stateEntries) === s_valid && !lastCycleMisprediction } // debug: dump dispatch queue states @@ -217,20 +215,21 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int)(implicit p: Parameters) QueuePerf(size, PopCount(stateEntries.map(_ =/= s_invalid)), !canEnqueue) io.dqFull := !canEnqueue XSPerfAccumulate("in", numEnq) - XSPerfAccumulate("out", PopCount(io.deq.map(_.fire()))) + XSPerfAccumulate("out", PopCount(io.deq.map(_.fire))) XSPerfAccumulate("out_try", PopCount(io.deq.map(_.valid))) val fake_block = currentValidCounter <= (size - enqnum).U && !canEnqueue XSPerfAccumulate("fake_block", fake_block) + val validEntries = RegNext(PopCount(stateEntries.map(_ =/= s_invalid))) val perfEvents = Seq( - ("dispatchq_in ", numEnq), - ("dispatchq_out ", PopCount(io.deq.map(_.fire()))), - ("dispatchq_out_try ", PopCount(io.deq.map(_.valid))), - ("dispatchq_fake_block", fake_block), - ("dispatchq_1_4_valid ", (PopCount(stateEntries.map(_ =/= s_invalid)) < (size.U / 4.U))), - ("dispatchq_2_4_valid ", (PopCount(stateEntries.map(_ =/= s_invalid)) > (size.U / 4.U)) & (PopCount(stateEntries.map(_ =/= s_invalid)) <= (size.U / 2.U))), - ("dispatchq_3_4_valid ", (PopCount(stateEntries.map(_ =/= s_invalid)) > (size.U / 2.U)) & (PopCount(stateEntries.map(_ =/= s_invalid)) <= (size.U * 3.U / 4.U))), - ("dispatchq_4_4_valid ", (PopCount(stateEntries.map(_ =/= s_invalid)) > (size.U * 3.U / 4.U))), + ("dispatchq_in", numEnq ), + ("dispatchq_out", PopCount(io.deq.map(_.fire)) ), + ("dispatchq_out_try", PopCount(io.deq.map(_.valid)) ), + ("dispatchq_fake_block", fake_block ), + ("dispatchq_1_4_valid ", validEntries < (size / 4).U ), + ("dispatchq_2_4_valid ", validEntries >= (size / 4).U && validEntries <= (size / 2).U ), + ("dispatchq_3_4_valid ", validEntries >= (size / 2).U && validEntries <= (size * 3 / 4).U), + ("dispatchq_4_4_valid ", validEntries >= (size * 3 / 4).U ) ) generatePerfEvent() } diff --git a/src/main/scala/xiangshan/backend/rename/Rename.scala b/src/main/scala/xiangshan/backend/rename/Rename.scala index 5a613050e8ecee1065f82f72413b34bcb0c1ff51..492e08339392cbd750563f4e5b40064ecd734ac5 100644 --- a/src/main/scala/xiangshan/backend/rename/Rename.scala +++ b/src/main/scala/xiangshan/backend/rename/Rename.scala @@ -65,7 +65,7 @@ class Rename(implicit p: Parameters) extends XSModule with HasPerfEvents { fl.io.walk := io.robCommits.isWalk // when isWalk, use stepBack to restore head pointer of free list // (if ME enabled, stepBack of intFreeList should be useless thus optimized out) - fl.io.stepBack := PopCount(io.robCommits.valid.zip(io.robCommits.info).map{case (v, i) => v && needDestRegCommit(isFp, i)}) + fl.io.stepBack := PopCount(io.robCommits.walkValid.zip(io.robCommits.info).map{case (v, i) => v && needDestRegCommit(isFp, i)}) } // walk has higher priority than allocation and thus we don't use isWalk here // only when both fp and int free list and dispatch1 has enough space can we do allocation diff --git a/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala b/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala index abba9cc91ba991ed6197ddd66d4b7190622b6b23..a144390f916d04f5d8a74a1294a3b2d798a6148b 100644 --- a/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala +++ b/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala @@ -39,9 +39,7 @@ abstract class BaseFreeList(size: Int)(implicit p: Parameters) extends XSModule val stepBack = Input(UInt(log2Up(CommitWidth + 1).W)) }) - class FreeListPtr extends CircularQueuePtr[FreeListPtr](size) { - def toOH: UInt = UIntToOH(value, size) - } + class FreeListPtr extends CircularQueuePtr[FreeListPtr](size) object FreeListPtr { def apply(f: Boolean, v: Int): FreeListPtr = { diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala index 263ffc7ed967c4bf22cbb472043cec4a6fb3855a..a48f2493faaf1671ede67c8495fc9298caf3cec9 100644 --- a/src/main/scala/xiangshan/backend/rob/Rob.scala +++ b/src/main/scala/xiangshan/backend/rob/Rob.scala @@ -303,7 +303,6 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer) val writeback = MixedVec(numWbPorts.map(num => Vec(num, Flipped(ValidIO(new ExuOutput))))) val commits = new RobCommitIO val lsq = new RobLsqIO - val bcommit = Output(UInt(log2Up(CommitWidth + 1).W)) val robDeqPtr = Output(new RobPtr) val csr = new RobCSRIO val robFull = Output(Bool()) @@ -562,17 +561,17 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer) (v & info.wflags, v & info.fpWen) }).unzip val fflags = Wire(Valid(UInt(5.W))) - fflags.valid := Mux(io.commits.isWalk, false.B, Cat(wflags).orR()) + fflags.valid := Mux(io.commits.isWalk, false.B, Cat(wflags).orR) fflags.bits := wflags.zip(fflagsDataRead).map({ case (w, f) => Mux(w, f, 0.U) }).reduce(_|_) - val dirty_fs = Mux(io.commits.isWalk, false.B, Cat(fpWen).orR()) + val dirty_fs = Mux(io.commits.isWalk, false.B, Cat(fpWen).orR) // when mispredict branches writeback, stop commit in the next 2 cycles // TODO: don't check all exu write back val misPredWb = Cat(VecInit(exuWriteback.map(wb => wb.bits.redirect.cfiUpdate.isMisPred && wb.bits.redirectValid - ))).orR() + ))).orR val misPredBlockCounter = Reg(UInt(3.W)) misPredBlockCounter := Mux(misPredWb, "b111".U, @@ -593,12 +592,15 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer) // when intrBitSetReg, allow only one instruction to commit at each clock cycle val isBlocked = if (i != 0) Cat(commit_block.take(i)).orR || allowOnlyOneCommit else intrEnable || deqHasException || deqHasReplayInst io.commits.valid(i) := commit_v(i) && commit_w(i) && !isBlocked && !misPredBlock && !isReplaying && !lastCycleFlush && !hasWFI + io.commits.walkValid(i) := DontCare io.commits.info(i) := dispatchDataRead(i) when (state === s_walk) { io.commits.valid(i) := commit_v(i) && shouldWalkVec(i) + io.commits.walkValid(i) := commit_v(i) && shouldWalkVec(i) }.elsewhen(state === s_extrawalk) { io.commits.valid(i) := (if (i < RenameWidth) usedSpaceForMPR(RenameWidth-i-1) else false.B) + io.commits.walkValid(i) := (if (i < RenameWidth) usedSpaceForMPR(RenameWidth-i-1) else false.B) io.commits.info(i) := (if (i < RenameWidth) extraSpaceForMPR(RenameWidth-i-1) else DontCare) } @@ -631,10 +633,6 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer) io.csr.fflags := RegNext(fflags) io.csr.dirty_fs := RegNext(dirty_fs) - // commit branch to brq - val cfiCommitVec = VecInit(io.commits.valid.zip(io.commits.info.map(_.commitType)).map{case(v, t) => v && CommitType.isBranch(t)}) - io.bcommit := Mux(io.commits.isWalk, 0.U, PopCount(cfiCommitVec)) - // commit load/store to lsq val ldCommitVec = VecInit((0 until CommitWidth).map(i => io.commits.valid(i) && io.commits.info(i).commitType === CommitType.LOAD)) val stCommitVec = VecInit((0 until CommitWidth).map(i => io.commits.valid(i) && io.commits.info(i).commitType === CommitType.STORE)) @@ -941,7 +939,7 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer) val commitIsStore = io.commits.info.map(_.commitType).map(_ === CommitType.STORE) XSPerfAccumulate("commitInstrStore", ifCommit(PopCount(io.commits.valid.zip(commitIsStore).map{ case (v, t) => v && t }))) XSPerfAccumulate("writeback", PopCount((0 until RobSize).map(i => valid(i) && writebacked(i)))) - // XSPerfAccumulate("enqInstr", PopCount(io.dp1Req.map(_.fire()))) + // XSPerfAccumulate("enqInstr", PopCount(io.dp1Req.map(_.fire))) // XSPerfAccumulate("d2rVnR", PopCount(io.dp1Req.map(p => p.valid && !p.ready))) XSPerfAccumulate("walkInstr", Mux(io.commits.isWalk, PopCount(io.commits.valid), 0.U)) XSPerfAccumulate("walkCycle", state === s_walk || state === s_extrawalk) @@ -973,7 +971,7 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer) XSPerfAccumulate(s"${fuName}_latency_execute", ifCommit(latencySum(commitIsFuType, executeLatency))) XSPerfAccumulate(s"${fuName}_latency_enq_rs_execute", ifCommit(latencySum(commitIsFuType, rsFuLatency))) XSPerfAccumulate(s"${fuName}_latency_commit", ifCommit(latencySum(commitIsFuType, commitLatency))) - if (fuType == FuType.fmac.litValue()) { + if (fuType == FuType.fmac.litValue) { val commitIsFma = commitIsFuType.zip(commitDebugUop).map(x => x._1 && x._2.ctrl.fpu.ren3 ) XSPerfAccumulate(s"${fuName}_instr_cnt_fma", ifCommit(PopCount(commitIsFma))) XSPerfAccumulate(s"${fuName}_latency_enq_rs_execute_fma", ifCommit(latencySum(commitIsFma, rsFuLatency))) diff --git a/src/main/scala/xiangshan/package.scala b/src/main/scala/xiangshan/package.scala index 592a110e2bcd9f27ab75527839ad77959095bad2..23b326d4be76b13b43b6076b0b03698db5e27dab 100644 --- a/src/main/scala/xiangshan/package.scala +++ b/src/main/scala/xiangshan/package.scala @@ -31,7 +31,8 @@ package object xiangshan { def imm = "b01".U def fp = "b10".U - def DC = imm // Don't Care + def DC = imm // Don't Care + def X = BitPat("b??") def isReg(srcType: UInt) = srcType===reg def isPc(srcType: UInt) = srcType===pc @@ -69,6 +70,8 @@ package object xiangshan { def stu = "b1101".U def mou = "b1111".U // for amo, lr, sc, fence + def X = BitPat("b????") + def num = 14 def apply() = UInt(log2Up(num).W) @@ -500,6 +503,8 @@ package object xiangshan { def INVALID_INSTR = "b0110".U def IMM_B6 = "b1000".U + def X = BitPat("b????") + def apply() = UInt(4.W) }