From 44277a7f644703b4c7cb864439b644ed05f7382b Mon Sep 17 00:00:00 2001 From: jinyue110 Date: Wed, 20 Jan 2021 11:08:41 +0800 Subject: [PATCH] icache: add refill sam cacheline check --- src/main/scala/xiangshan/cache/icache.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/cache/icache.scala b/src/main/scala/xiangshan/cache/icache.scala index 2e255bddd..b0914c964 100644 --- a/src/main/scala/xiangshan/cache/icache.scala +++ b/src/main/scala/xiangshan/cache/icache.scala @@ -445,6 +445,10 @@ class ICache extends ICacheModule val refillDataVec = icacheMissQueue.io.resp.bits.data.asTypeOf(Vec(blockWords,UInt(wordBits.W))) val refillDataOut = cutHelper(refillDataVec, s3_req_pc,s3_req_mask ) + val is_same_cacheline = s3_miss && s2_valid && (groupAligned(s2_req_pc) ===groupAligned(s3_req_pc)) + val useRefillReg = RegNext(is_same_cacheline && icacheMissQueue.io.resp.fire()) + val refillDataVecReg = RegEnable(next=refillDataVec, enable= (is_same_cacheline && icacheMissQueue.io.resp.fire())) + //FIXME!! val mmio_packet = io.mmio_grant.bits.data @@ -458,7 +462,7 @@ class ICache extends ICacheModule for (i <- 0 until nWays) { val wayResp = Wire(new ICacheResp) val wayData = cutHelper(VecInit(s3_data.map(b => b(i).asUInt)), s3_req_pc, s3_req_mask) - val refillData = cutHelper(refillDataVec, s3_req_pc,s3_req_mask) + val refillData = Mux(useRefillReg,cutHelper(refillDataVecReg, s3_req_pc,s3_req_mask),cutHelper(refillDataVec, s3_req_pc,s3_req_mask)) wayResp.pc := s3_req_pc wayResp.data := Mux(s3_valid && s3_hit, wayData, Mux(s3_mmio ,mmio_packet ,refillData)) wayResp.mask := Mux(s3_mmio,mmioMask,s3_req_mask) -- GitLab