From 3a64b51588f643b9d78e93e4f7afe7d4002ae6fc Mon Sep 17 00:00:00 2001
From: Yinan Xu <xuyinan1997@gmail.com>
Date: Sat, 27 Feb 2021 19:59:29 +0800
Subject: [PATCH] intWb: set wb.valid when !fpwen to allow writeback if !fpwen
 and !rfwen (#601)

---
 src/main/scala/xiangshan/backend/IntegerBlock.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/xiangshan/backend/IntegerBlock.scala b/src/main/scala/xiangshan/backend/IntegerBlock.scala
index d6eaeb2ea..0a4cc7e57 100644
--- a/src/main/scala/xiangshan/backend/IntegerBlock.scala
+++ b/src/main/scala/xiangshan/backend/IntegerBlock.scala
@@ -51,7 +51,7 @@ trait HasExeBlockHelper {
   }
   def intOutValid(x: ValidIO[ExuOutput]): ValidIO[ExuOutput] = {
     val out = WireInit(x)
-    out.valid := x.valid && x.bits.uop.ctrl.rfWen
+    out.valid := x.valid && !x.bits.uop.ctrl.fpWen
     out
   }
   def intOutValid(x: DecoupledIO[ExuOutput], connectReady: Boolean = false): DecoupledIO[ExuOutput] = {
-- 
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