From 392c0eb2a8763dda8b2667ffb9721a78fb997fb4 Mon Sep 17 00:00:00 2001
From: JinYue <jinyue20s@ict.ac.cn>
Date: Tue, 20 Jul 2021 16:18:50 +0800
Subject: [PATCH] ICache: fix nWays SRAMs bug

---
 src/main/scala/xiangshan/decoupled-frontend/ICache.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/xiangshan/decoupled-frontend/ICache.scala b/src/main/scala/xiangshan/decoupled-frontend/ICache.scala
index 2f2fa8b53..a4817e235 100644
--- a/src/main/scala/xiangshan/decoupled-frontend/ICache.scala
+++ b/src/main/scala/xiangshan/decoupled-frontend/ICache.scala
@@ -203,14 +203,14 @@ class ICacheDataArray(implicit p: Parameters) extends ICacheArray
   io.read.ready := !io.write.valid
   
   val dataArrays = (0 until 2) map { i =>
-    val dataArray = Seq.fill(nWays){Module(new SRAMTemplate(
+    val dataArray = Module(new SRAMTemplate(
       UInt(blockBits.W),
       set=nSets/2,
       way=nWays,
       shouldReset = true,
       holdRead = true,
       singlePort = true
-    ))}
+    ))
 
     dataArray.map{ way =>
       //meta connection
-- 
GitLab