diff --git a/src/main/scala/xiangshan/backend/CtrlBlock.scala b/src/main/scala/xiangshan/backend/CtrlBlock.scala
index 39063eaf918a2ac5ed74ce11b3c15931d6a2df14..9e07db6da90741b3a17a4f8293adf052f0caf3e2 100644
--- a/src/main/scala/xiangshan/backend/CtrlBlock.scala
+++ b/src/main/scala/xiangshan/backend/CtrlBlock.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import utils._
 import xiangshan._
-import xiangshan.backend.decode.DecodeStage
+import xiangshan.backend.decode.{DecodeStage, ImmUnion}
 import xiangshan.backend.rename.{BusyTable, Rename}
 import xiangshan.backend.dispatch.Dispatch
 import xiangshan.backend.exu._
@@ -122,7 +122,7 @@ class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper {
 
   val ftqRead = io.stage2FtqRead.entry
   val pc = GetPcByFtq(ftqRead.ftqPC, s2_redirect_bits_reg.ftqOffset)
-  val brTarget = pc + SignExt(s2_imm12_reg, XLEN)
+  val brTarget = pc + SignExt(ImmUnion.B.toImm32(s2_imm12_reg), XLEN)
   val snpc = pc + Mux(s2_pd.isRVC, 2.U, 4.U)
   val isReplay = RedirectLevel.flushItself(s2_redirect_bits_reg.level)
   val target = Mux(isReplay,
diff --git a/src/main/scala/xiangshan/frontend/IFU.scala b/src/main/scala/xiangshan/frontend/IFU.scala
index 77f9cb43b09668b7cfb5a84d7c9b0e597984eeb8..0ebbb7ce6bc0bc409bad0155a444fe30b2336bd7 100644
--- a/src/main/scala/xiangshan/frontend/IFU.scala
+++ b/src/main/scala/xiangshan/frontend/IFU.scala
@@ -438,19 +438,25 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
   when (if4_pendingPrevHalfInstr) {
     toFtqBuf.metas(0) := if4_prevHalfInstr.bits.meta
   }
-  val cfiIsCall = if4_pd.pd(if4_bp.jmpIdx).isCall
-  val cfiIsRet  = if4_pd.pd(if4_bp.jmpIdx).isRet
-  val cfiIsRVC  = if4_pd.pd(if4_bp.jmpIdx).isRVC
+  val if4_jmpIdx = WireInit(if4_bp.jmpIdx)
+  val if4_taken = WireInit(if4_bp.taken)
+  val if4_real_valids = if4_pd.mask &
+    (Fill(PredictWidth, !if4_taken) |
+      (Fill(PredictWidth, 1.U(1.W)) >> (~if4_jmpIdx)))
+
+  val cfiIsCall = if4_pd.pd(if4_jmpIdx).isCall
+  val cfiIsRet  = if4_pd.pd(if4_jmpIdx).isRet
+  val cfiIsRVC  = if4_pd.pd(if4_jmpIdx).isRVC
   toFtqBuf.cfiIsCall := cfiIsCall
   toFtqBuf.cfiIsRet  := cfiIsRet
   toFtqBuf.cfiIsRVC  := cfiIsRVC
-  toFtqBuf.cfiIndex.valid := if4_bp.taken
-  toFtqBuf.cfiIndex.bits  := Mux(cfiIsRVC, if4_bp.jmpIdx, if4_bp.jmpIdx - 1.U)
+  toFtqBuf.cfiIndex.valid := if4_taken
+  toFtqBuf.cfiIndex.bits  := Mux(cfiIsRVC, if4_jmpIdx, if4_jmpIdx - 1.U)
 
   toFtqBuf.br_mask   := if4_bp.brMask.asTypeOf(Vec(PredictWidth, Bool()))
   toFtqBuf.rvc_mask  := VecInit(if4_pd.pd.map(_.isRVC))
-  toFtqBuf.valids    := if4_pd.mask.asTypeOf(Vec(PredictWidth, Bool()))
-  toFtqBuf.target := Mux(if4_bp.taken, if4_bp.target, if4_snpc)
+  toFtqBuf.valids    := if4_real_valids.asTypeOf(Vec(PredictWidth, Bool()))
+  toFtqBuf.target := Mux(if4_taken, if4_target, if4_snpc)
 
 
 
@@ -520,7 +526,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
 
 
   fetchPacketWire.instrs := if4_pd.instrs
-  fetchPacketWire.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx)))
+  fetchPacketWire.mask := if4_real_valids
   fetchPacketWire.pdmask := if4_pd.mask
 
   fetchPacketWire.pc := if4_pd.pc