diff --git a/src/main/scala/xiangshan/backend/fu/CSR.scala b/src/main/scala/xiangshan/backend/fu/CSR.scala
index a56121e293f2c2b850b34a1bbf7c8baa09af8d34..54a113c035b83303c33b284da02d9556521c4465 100644
--- a/src/main/scala/xiangshan/backend/fu/CSR.scala
+++ b/src/main/scala/xiangshan/backend/fu/CSR.scala
@@ -788,7 +788,9 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
   }
 
   val xstrap = WireInit(false.B)
-  BoringUtils.addSink(xstrap, "XSTRAP")
+  if(!env.FPGAPlatform && EnableBPU){
+    ExcitingUtils.addSink(xstrap, "XSTRAP", ConnectionType.Debug)
+  }
   def readWithScala(addr: Int): UInt = mapping(addr)._1
 
   if (!env.FPGAPlatform) {
diff --git a/src/main/scala/xiangshan/backend/roq/Roq.scala b/src/main/scala/xiangshan/backend/roq/Roq.scala
index 8a5182cc81f6a3e533bb73c3ec86805b9a07f3be..c5b36d9f58026c11973baaa0b80530a9d5cd4eb9 100644
--- a/src/main/scala/xiangshan/backend/roq/Roq.scala
+++ b/src/main/scala/xiangshan/backend/roq/Roq.scala
@@ -1,5 +1,6 @@
 package xiangshan.backend.roq
 
+import chisel3.ExcitingUtils.ConnectionType
 import chisel3._
 import chisel3.util._
 import xiangshan._
@@ -291,14 +292,14 @@ class Roq extends XSModule {
     val trapCode = PriorityMux(wdata.zip(trapVec).map(x => x._2 -> x._1))
     val trapPC = PriorityMux(wpc.zip(trapVec).map(x => x._2 ->x._1))
 
-    ExcitingUtils.addSource(hitTrap, "trapValid")
-    ExcitingUtils.addSource(trapCode, "trapCode")
-    ExcitingUtils.addSource(trapPC, "trapPC")
-    ExcitingUtils.addSource(GTimer(), "trapCycleCnt")
-    ExcitingUtils.addSource(instrCnt, "trapInstrCnt")
+    ExcitingUtils.addSource(RegNext(hitTrap), "trapValid")
+    ExcitingUtils.addSource(RegNext(trapCode), "trapCode")
+    ExcitingUtils.addSource(RegNext(trapPC), "trapPC")
+    ExcitingUtils.addSource(RegNext(GTimer()), "trapCycleCnt")
+    ExcitingUtils.addSource(RegNext(instrCnt), "trapInstrCnt")
 
     if(EnableBPU){
-      BoringUtils.addSource(hitTrap, "XSTRAP")
+      ExcitingUtils.addSource(hitTrap, "XSTRAP", ConnectionType.Debug)
     }
   }
 }