From 2f6a87d4ded8ac2f176224d3d92edd87f06ee6cd Mon Sep 17 00:00:00 2001 From: William Wang Date: Mon, 25 Jan 2021 22:11:29 +0800 Subject: [PATCH] LoadQueue: fix load miss data fwd logic --- src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala index ecf0023b0..2cd298e4a 100644 --- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala +++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala @@ -181,7 +181,7 @@ class LoadQueue extends XSModule val loadWbData = Wire(new LQDataEntry) loadWbData.paddr := io.loadIn(i).bits.paddr loadWbData.mask := io.loadIn(i).bits.mask - loadWbData.data := io.loadIn(i).bits.data // fwd data + loadWbData.data := io.loadIn(i).bits.forwardData.asUInt // fwd data loadWbData.fwdMask := io.loadIn(i).bits.forwardMask dataModule.io.wbWrite(i, loadWbIndex, loadWbData) dataModule.io.wb.wen(i) := true.B -- GitLab