From 2ece232e6977e6b0ac61486f12eafa1d606bbc51 Mon Sep 17 00:00:00 2001 From: JinYue Date: Mon, 2 Aug 2021 15:12:40 +0800 Subject: [PATCH] PreDecode: add ret miss prediction & takens --- src/main/scala/xiangshan/decoupled-frontend/PreDecode.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/decoupled-frontend/PreDecode.scala b/src/main/scala/xiangshan/decoupled-frontend/PreDecode.scala index 19867aa44..81c620f49 100644 --- a/src/main/scala/xiangshan/decoupled-frontend/PreDecode.scala +++ b/src/main/scala/xiangshan/decoupled-frontend/PreDecode.scala @@ -138,7 +138,7 @@ class PreDecode(implicit p: Parameters) extends XSModule with HasPdconst with Ha expander.io.in := inst io.out.instrs(i) := expander.io.out.bits - takens(i) := (validStart(i) && (bbTaken && bbOffset === i.U && !io.out.pd(i).notCFI || io.out.pd(i).isJal)) + takens(i) := (validStart(i) && (bbTaken && bbOffset === i.U && !io.out.pd(i).notCFI || io.out.pd(i).isJal || io.out.pd(i).isRet)) val jumpTarget = io.out.pc(i) + Mux(io.out.pd(i).isBr, brOffset, jalOffset) targets(i) := Mux(takens(i), jumpTarget, pcEnd) @@ -148,10 +148,11 @@ class PreDecode(implicit p: Parameters) extends XSModule with HasPdconst with Ha val notCFIFault = (validStart(i) && i.U === bbOffset && io.out.pd(i).notCFI && bbTaken) //A jal instruction is predicted not taken val jalFault = (validStart(i) && !bbTaken && io.out.pd(i).isJal) + val retFault = (validStart(i) && !bbTaken && io.out.pd(i).isRet) //An invalid instruction is predicted taken val invalidInsFault = (!validStart(i) && i.U === bbOffset && bbTaken) - misPred(i) := targetFault || notCFIFault || jalFault || invalidInsFault + misPred(i) := targetFault || notCFIFault || jalFault || retFault || invalidInsFault falseHit(i) := invalidInsFault || notCFIFault realMissPred(i) := misPred(i) && instRange(i) -- GitLab