diff --git a/src/main/scala/xiangshan/Bundle.scala b/src/main/scala/xiangshan/Bundle.scala
index a0879dbbd5498baf28f4f29b93978d1be87d90e3..6870ab6b566d87fef5cd9f8027468bf6c2aecb09 100644
--- a/src/main/scala/xiangshan/Bundle.scala
+++ b/src/main/scala/xiangshan/Bundle.scala
@@ -143,8 +143,8 @@ class CtrlSignals extends XSBundle {
   val rfWen = Bool()
   val fpWen = Bool()
   val isXSTrap = Bool()
-  val noSpecExec = Bool()  // This inst can not be speculated
-  val isBlocked  = Bool()  // This inst requires pipeline to be blocked
+  val noSpecExec = Bool()  // wait forward
+  val blockBackward  = Bool()  // block backward
   val flushPipe  = Bool()  // This inst will flush all the pipe when commit, like exception but can commit
   val isRVF = Bool()
   val imm = UInt(XLEN.W)
diff --git a/src/main/scala/xiangshan/backend/decode/Decoder.scala b/src/main/scala/xiangshan/backend/decode/Decoder.scala
index 4887eaac2cf38e5a6ef782bbf2e8f1dc1d929983..dae71f3d6c87043cb6ff563e290ad09a456dc630 100644
--- a/src/main/scala/xiangshan/backend/decode/Decoder.scala
+++ b/src/main/scala/xiangshan/backend/decode/Decoder.scala
@@ -182,7 +182,21 @@ class Decoder extends XSModule with HasInstrType {
   when(io.out.ctrl.isXSTrap){
     io.out.ctrl.lsrc1 := 10.U // a0
   }
-  io.out.ctrl.noSpecExec := io.out.ctrl.isXSTrap || io.out.ctrl.fuType===FuType.csr || io.out.ctrl.fuType===FuType.mou || io.out.ctrl.fuType===FuType.fence/*noSpecExec make it sent to alu0,for roq is empty*/
+
+  /*noSpecExec make it sent to alu0,for roq is empty*/
+  io.out.ctrl.noSpecExec := io.out.ctrl.isXSTrap ||
+    io.out.ctrl.fuType===FuType.csr ||
+    io.out.ctrl.fuType===FuType.mou ||
+    io.out.ctrl.fuType===FuType.fence
+
+  //                           fflags    zero csrrs rd    csr
+  val isFrflags = BitPat("b000000000001_00000_010_?????_1110011") === io.in.instr
+
+  io.out.ctrl.blockBackward := io.out.ctrl.isXSTrap ||
+    (io.out.ctrl.fuType===FuType.csr && !isFrflags) ||
+    io.out.ctrl.fuType===FuType.mou ||
+    io.out.ctrl.fuType===FuType.fence
+
   io.out.ctrl.flushPipe := io.out.ctrl.fuType===FuType.fence
 
   io.out.ctrl.isRVF := instr(26, 25) === 0.U
@@ -193,5 +207,5 @@ class Decoder extends XSModule with HasInstrType {
   XSDebug("out: src1Type=%b src2Type=%b src3Type=%b lsrc1=%d lsrc2=%d lsrc3=%d ldest=%d fuType=%b fuOpType=%b\n",
     io.out.ctrl.src1Type, io.out.ctrl.src2Type, io.out.ctrl.src3Type, io.out.ctrl.lsrc1, io.out.ctrl.lsrc2, io.out.ctrl.lsrc3, io.out.ctrl.ldest, io.out.ctrl.fuType, io.out.ctrl.fuOpType)
   XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d flushPipe=%d isRVF=%d imm=%x\n",
-    io.out.ctrl.rfWen, io.out.ctrl.fpWen, io.out.ctrl.isXSTrap, io.out.ctrl.noSpecExec, io.out.ctrl.isBlocked, io.out.ctrl.flushPipe, io.out.ctrl.isRVF, io.out.ctrl.imm)
+    io.out.ctrl.rfWen, io.out.ctrl.fpWen, io.out.ctrl.isXSTrap, io.out.ctrl.noSpecExec, io.out.ctrl.blockBackward, io.out.ctrl.flushPipe, io.out.ctrl.isRVF, io.out.ctrl.imm)
 }
diff --git a/src/main/scala/xiangshan/backend/roq/Roq.scala b/src/main/scala/xiangshan/backend/roq/Roq.scala
index c87c2e1d90164b51debdfa5a9caea28d266fe66c..56caf81d9f45fef37c340864df207f65e513220e 100644
--- a/src/main/scala/xiangshan/backend/roq/Roq.scala
+++ b/src/main/scala/xiangshan/backend/roq/Roq.scala
@@ -81,7 +81,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
   io.roqDeqPtr := deqPtrExt
 
   // Dispatch
-  val noSpecEnq = io.dp1Req.map(i => i.bits.ctrl.noSpecExec)
+  val noSpecEnq = io.dp1Req.map(i => i.bits.ctrl.blockBackward)
   val hasNoSpec = RegInit(false.B)
   when(isEmpty){ hasNoSpec:= false.B }
   val validDispatch = io.dp1Req.map(_.valid)