diff --git a/src/main/scala/xiangshan/backend/exu/Alu.scala b/src/main/scala/xiangshan/backend/exu/Alu.scala
index a3322a9ef0115841459ad82b6a5d4453407b1af5..7163e49bf05d03372195f59ed4add3c7529fdc87 100644
--- a/src/main/scala/xiangshan/backend/exu/Alu.scala
+++ b/src/main/scala/xiangshan/backend/exu/Alu.scala
@@ -28,8 +28,8 @@ object ALUOpType {
   def isWordOp(func: UInt) = func(5)
 
   // TODO: move jal/jalr/call/ret from ALU to BRU&CSR
-  // def jal  = "b011000".U
-  // def jalr = "b011010".U
+  def jal  = "b011000".U
+  def jalr = "b011010".U
   // def cjalr= "b111010".U // pc + 2 instead of 4
   def beq  = "b010000".U
   def bne  = "b010001".U
@@ -39,25 +39,28 @@ object ALUOpType {
   def bgeu = "b010111".U
 
   // for RAS
-  // def call = "b011100".U
-  // def ret  = "b011110".U
+  def call = "b011100".U
+  def ret  = "b011110".U
 
   // def pcPlus2(func: UInt) = func(5)//[important]
-  def isBranch(func: UInt) = func(4)
+  def isBranch(func: UInt) = func(4,3)===2.U
+  def isBru(func: UInt) = func(4)
+  def isJump(func: UInt) = func(4,3)===3.U//isBru(func) && !isBranch(func)
   def getBranchType(func: UInt) = func(2, 1)
   def isBranchInvert(func: UInt) = func(0)
 }
 
-class Alu extends Exu(alu.litValue()) with NeedImpl {
+class Alu extends Exu(alu.litValue()) {
   override def toString: String = "Alu"
 
   val (iovalid, src1, src2, offset, func, pc, uop) = (io.in.valid, io.in.bits.src1, io.in.bits.src2, 
-    io.in.bits.uop.ctrl.imm, io.in.bits.uop.ctrl.fuOpType, io.in.bits.uop.cf.pc, io.in.bits.uop)
+    io.in.bits.uop.ctrl.imm, io.in.bits.uop.ctrl.fuOpType, SignExt(io.in.bits.uop.cf.pc, AddrBits), io.in.bits.uop)
 
-  val valid = iovalid && !(io.redirect.valid && 
+  val redirectHit = (io.redirect.valid && 
     ((UIntToOH(io.redirect.bits.brTag) & uop.brMask).orR || io.redirect.bits.isException))
+  val valid = iovalid && !redirectHit
 
-  val isAdderSub = (func =/= ALUOpType.add) && (func =/= ALUOpType.addw)
+  val isAdderSub = (func =/= ALUOpType.add) && (func =/= ALUOpType.addw) && !ALUOpType.isJump(func)
   val adderRes = (src1 +& (src2 ^ Fill(XLEN, isAdderSub))) + isAdderSub
   val xorRes = src1 ^ src2
   val sltu = !adderRes(XLEN)
@@ -86,20 +89,34 @@ class Alu extends Exu(alu.litValue()) with NeedImpl {
     ALUOpType.getBranchType(ALUOpType.bltu) -> sltu
   )
 
-  val isBranch =  io.in.bits.uop.cf.isBr// ALUOpType.isBranch(func)
+  val isBru = ALUOpType.isBru(func)
+  // val isBranch =  io.in.bits.uop.cf.isBr// ALUOpType.isBranch(func)
+  val isBranch =  ALUOpType.isBranch(func)
+  val isJump = ALUOpType.isJump(func)
   val taken = LookupTree(ALUOpType.getBranchType(func), branchOpTable) ^ ALUOpType.isBranchInvert(func)
   val target = Mux(isBranch, pc + offset, adderRes)(VAddrBits-1,0)
   val isRVC = uop.cf.isRVC//(io.in.bits.cf.instr(1,0) =/= "b11".U)
 
   io.in.ready := io.out.ready
-  
-  io.out.bits.redirect.valid := io.out.valid && isBranch
-  io.out.bits.redirect.bits.target := Mux(!taken && isBranch, Mux(isRVC, pc + 2.U, pc + 4.U), target)
+  val pcLatchSlot = Mux(isRVC, pc + 2.U, pc + 4.U)
+  io.out.bits.redirect.valid := io.out.valid && isBru//isBranch
+  io.out.bits.redirect.bits.target := Mux(!taken && isBranch, pcLatchSlot, target)
   io.out.bits.redirect.bits.brTag := uop.brTag
   io.out.bits.redirect.bits.isException := DontCare // false.B
   io.out.bits.redirect.bits.roqIdx := uop.roqIdx
+  io.out.bits.redirect.bits.freelistAllocPtr := uop.freelistAllocPtr
 
   io.out.valid := valid
   io.out.bits.uop <> io.in.bits.uop
-  io.out.bits.data := aluRes
+  io.out.bits.data := Mux(isJump, pcLatchSlot, aluRes)
+
+  io.dmem <> DontCare
+  io.out.bits.debug.isMMIO := DontCare // FIXME: dont know how to do with it
+  
+  XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:%x, brMask:%x\n",
+    io.in.valid, io.in.ready, io.out.valid, io.out.ready, io.redirect.valid, io.redirect.bits.isException, redirectHit, io.redirect.bits.brTag, uop.brMask)
+  XSDebug(io.in.valid, "src1:%x src2:%x offset:%x func:%b pc:%x\n",
+    src1, src2, offset, func, pc)
+  XSDebug(io.in.valid, "res:%x aluRes:%x isRVC:%d isBru:%d isBranch:%d isJump:%d target:%x taken:%d\n",
+     io.out.bits.data, aluRes, isRVC, isBru, isBranch, isJump, target, taken)
 }
\ No newline at end of file
diff --git a/src/main/scala/xiangshan/backend/exu/Exu.scala b/src/main/scala/xiangshan/backend/exu/Exu.scala
index b30a75109206f09825d5565b2ce1002f709fbeaf..b9849be4961869860c9e1dd0e72b3a9a12c6b41d 100644
--- a/src/main/scala/xiangshan/backend/exu/Exu.scala
+++ b/src/main/scala/xiangshan/backend/exu/Exu.scala
@@ -34,7 +34,7 @@ abstract class Exu
   val writeFpRf: Boolean = false,
   val enableBypass: Boolean = false, // join bypass group or not, require readIntRf & writeIntRf now
   val fixedDelay: Int = 1 // IssueQueue's selectUop's delay
-) extends Module {
+) extends XSModule {
   val io = IO(new ExuIO)
 }
 
diff --git a/stale_outputs_checked b/stale_outputs_checked
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391