diff --git a/src/main/scala/xiangshan/Bundle.scala b/src/main/scala/xiangshan/Bundle.scala
index 911fdc90bc8639ea58d312b1e57fe3feb296ae02..ff5f2c4141ade47fccfa19d2d77ef3b11bb29e6f 100644
--- a/src/main/scala/xiangshan/Bundle.scala
+++ b/src/main/scala/xiangshan/Bundle.scala
@@ -360,7 +360,7 @@ class DebugBundle(implicit p: Parameters) extends XSBundle {
 
 class ExuInput(implicit p: Parameters) extends XSBundle {
   val uop = new MicroOp
-  val src1, src2, src3 = UInt((XLEN + 1).W)
+  val src = Vec(3, UInt((XLEN + 1).W))
 }
 
 class ExuOutput(implicit p: Parameters) extends XSBundle {
diff --git a/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala b/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala
index 5701b5cdbd4a7b248f3fd2c9d11cf8a3044e23d4..7eefea7fde2a19e25b30f52d493c6cf27afafa10 100644
--- a/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala
+++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala
@@ -136,15 +136,15 @@ class Dispatch2Fp(implicit p: Parameters) extends XSModule {
 //    dataValidRegDebug(i) := io.enqIQCtrl(i).fire()
 //
 //    io.enqIQData(i) := DontCare
-//    io.enqIQData(i).src1 := io.readRf(readPortIndexReg(i)).data
-//    io.enqIQData(i).src2 := io.readRf(readPortIndexReg(i) + 1.U).data
-//    io.enqIQData(i).src3 := io.readRf(readPortIndexReg(i) + 2.U).data
+//    io.enqIQData(i).src(0) := io.readRf(readPortIndexReg(i)).data
+//    io.enqIQData(i).src(1) := io.readRf(readPortIndexReg(i) + 1.U).data
+//    io.enqIQData(i).src(2) := io.readRf(readPortIndexReg(i) + 2.U).data
 //
 //    XSDebug(dataValidRegDebug(i),
 //      p"pc 0x${Hexadecimal(uopReg(i).cf.pc)} reads operands from " +
-//        p"(${readPortIndexReg(i)    }, ${uopReg(i).psrc(0)}, ${Hexadecimal(io.enqIQData(i).src1)}), " +
-//        p"(${readPortIndexReg(i)+1.U}, ${uopReg(i).psrc(1)}, ${Hexadecimal(io.enqIQData(i).src2)}), " +
-//        p"(${readPortIndexReg(i)+2.U}, ${uopReg(i).psrc(2)}, ${Hexadecimal(io.enqIQData(i).src3)})\n")
+//        p"(${readPortIndexReg(i)    }, ${uopReg(i).psrc(0)}, ${Hexadecimal(io.enqIQData(i).src(0))}), " +
+//        p"(${readPortIndexReg(i)+1.U}, ${uopReg(i).psrc(1)}, ${Hexadecimal(io.enqIQData(i).src(1))}), " +
+//        p"(${readPortIndexReg(i)+2.U}, ${uopReg(i).psrc(2)}, ${Hexadecimal(io.enqIQData(i).src(2))})\n")
 //  }
 
   XSPerfAccumulate("in", PopCount(io.fromDq.map(_.valid)))
diff --git a/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala b/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala
index 24f9accd9c03c95951464bf1bbe2759028a43c79..dcd2f86f773dc743f12b330109cdf3c933e70d79 100644
--- a/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala
+++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala
@@ -141,15 +141,15 @@ class Dispatch2Int(implicit p: Parameters) extends XSModule {
 //    dataValidRegDebug(i) := io.enqIQCtrl(i).fire()
 //
 //    io.enqIQData(i) := DontCare
-//    io.enqIQData(i).src1 := Mux(uopReg(i).ctrl.srcType(0) === SrcType.pc,
+//    io.enqIQData(i).src(0) := Mux(uopReg(i).ctrl.srcType(0) === SrcType.pc,
 //      SignExt(uopReg(i).cf.pc, XLEN), io.readRf(readPortIndexReg(i)).data)
-//    io.enqIQData(i).src2 := Mux(uopReg(i).ctrl.srcType(1) === SrcType.imm,
+//    io.enqIQData(i).src(1) := Mux(uopReg(i).ctrl.srcType(1) === SrcType.imm,
 //      uopReg(i).ctrl.imm, io.readRf(readPortIndexReg(i) + 1.U).data)
 //
 //    XSDebug(dataValidRegDebug(i),
 //      p"pc 0x${Hexadecimal(uopReg(i).cf.pc)} reads operands from " +
-//        p"(${readPortIndexReg(i)    }, ${uopReg(i).psrc(0)}, ${Hexadecimal(io.enqIQData(i).src1)}), " +
-//        p"(${readPortIndexReg(i)+1.U}, ${uopReg(i).psrc(1)}, ${Hexadecimal(io.enqIQData(i).src2)})\n")
+//        p"(${readPortIndexReg(i)    }, ${uopReg(i).psrc(0)}, ${Hexadecimal(io.enqIQData(i).src(0))}), " +
+//        p"(${readPortIndexReg(i)+1.U}, ${uopReg(i).psrc(1)}, ${Hexadecimal(io.enqIQData(i).src(1))})\n")
 //  }
 
   XSPerfAccumulate("in", PopCount(io.fromDq.map(_.valid)))
diff --git a/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala b/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala
index 9c6f2422c4b840c9bcd64a5c14d7c4640bb746f6..b6087ea6dd7e37647e7023311f9dbd06058526eb 100644
--- a/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala
+++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala
@@ -130,9 +130,9 @@ class Dispatch2Ls(implicit p: Parameters) extends XSModule {
 //
 //    io.enqIQData(i) := DontCare
 //    // assert(uopReg(i).ctrl.srcType(0) =/= SrcType.pc)
-//    io.enqIQData(i).src1 := io.readIntRf(readPort(i)).data
+//    io.enqIQData(i).src(0) := io.readIntRf(readPort(i)).data
 //    if (i >= exuParameters.LduCnt) {
-//      io.enqIQData(i).src2 := Mux(
+//      io.enqIQData(i).src(1) := Mux(
 //        uopReg(i).ctrl.srcType(1) === SrcType.imm,
 //        uopReg(i).ctrl.imm,
 //        Mux(uopReg(i).ctrl.srcType(1) === SrcType.fp,
@@ -142,8 +142,8 @@ class Dispatch2Ls(implicit p: Parameters) extends XSModule {
 //
 //    XSDebug(dataValidRegDebug(i),
 //      p"pc 0x${Hexadecimal(uopReg(i).cf.pc)} reads operands from " +
-//        p"(${readPort(i)  }, ${uopReg(i).psrc(0)}, ${Hexadecimal(io.enqIQData(i).src1)}), " +
-//        p"(${readPort(i)+1}, ${uopReg(i).psrc(1)}, ${Hexadecimal(io.enqIQData(i).src2)})\n")
+//        p"(${readPort(i)  }, ${uopReg(i).psrc(0)}, ${Hexadecimal(io.enqIQData(i).src(0))}), " +
+//        p"(${readPort(i)+1}, ${uopReg(i).psrc(1)}, ${Hexadecimal(io.enqIQData(i).src(1))})\n")
 //  }
 
   XSPerfAccumulate("in", PopCount(io.fromDq.map(_.valid)))
diff --git a/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala b/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala
index eadda84ed4a5cf7d866bbb42a164b6f7bb3bfdbb..d7f330ce541386d60a43f17dd484453e991161c3 100644
--- a/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala
+++ b/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala
@@ -22,8 +22,8 @@ class AluExeUnit(implicit p: Parameters) extends Exu(AluExeUnitCfg)
       p"Redirect:(${io.redirect.valid}) roqIdx:${io.redirect.bits.roqIdx}\n",
   )
   XSDebug(io.fromInt.valid,
-    p"src1:${Hexadecimal(io.fromInt.bits.src1)} src2:${Hexadecimal(io.fromInt.bits.src2)} " +
-      p"src3:${Hexadecimal(io.fromInt.bits.src3)} func:${Binary(io.fromInt.bits.uop.ctrl.fuOpType)} " +
+    p"src1:${Hexadecimal(io.fromInt.bits.src(0))} src2:${Hexadecimal(io.fromInt.bits.src(1))} " +
+      p"src3:${Hexadecimal(io.fromInt.bits.src(2))} func:${Binary(io.fromInt.bits.uop.ctrl.fuOpType)} " +
       p"pc:${Hexadecimal(io.fromInt.bits.uop.cf.pc)} roqIdx:${io.fromInt.bits.uop.roqIdx}\n"
   )
   XSDebug(io.out.valid,
diff --git a/src/main/scala/xiangshan/backend/exu/Exu.scala b/src/main/scala/xiangshan/backend/exu/Exu.scala
index 6a61f4e9e47d63837ba3d794f53a7d7fb0248c94..73a889d4f5a4bf32c5a65cb57c8a07e766c79ecc 100644
--- a/src/main/scala/xiangshan/backend/exu/Exu.scala
+++ b/src/main/scala/xiangshan/backend/exu/Exu.scala
@@ -94,9 +94,9 @@ abstract class Exu(val config: ExuConfig)(implicit p: Parameters) extends XSModu
       io.fromFp
     }
 
-    val src1 = in.bits.src1
-    val src2 = in.bits.src2
-    val src3 = in.bits.src3
+    val src1 = in.bits.src(0)
+    val src2 = in.bits.src(1)
+    val src3 = in.bits.src(2)
 
     fu.io.in.valid := in.valid && sel
     fu.io.in.bits.uop := in.bits.uop
diff --git a/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala b/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala
index a78e637d768b56ba36199816bd001a7df30a8db7..cbf410e6952771611d02fdd82f82f8f9fa0b9e93 100644
--- a/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala
+++ b/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala
@@ -14,7 +14,7 @@ class FmacExeUnit(implicit p: Parameters) extends Exu(FmacExeUnitCfg)
   val input = io.fromFp.bits
   val fmaOut = fma.io.out.bits
   val isRVD = !io.fromFp.bits.uop.ctrl.isRVF
-  fma.io.in.bits.src := VecInit(Seq(input.src1, input.src2, input.src3))
+  fma.io.in.bits.src := VecInit(Seq(input.src(0), input.src(1), input.src(2)))
   val instr_rm = io.fromFp.bits.uop.ctrl.fpu.rm
   fma.rm := Mux(instr_rm =/= 7.U, instr_rm, frm)
 
diff --git a/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala b/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala
index ff0d30a4c121ec2e026680becfe1c96d5c9cfdea..5b9d62453d9cbfb6293858c1071b0f887b9dd026 100644
--- a/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala
+++ b/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala
@@ -16,7 +16,7 @@ class FmiscExeUnit(implicit p: Parameters) extends Exu(FmiscExeUnitCfg) {
   val input = io.fromFp
   val isRVF = input.bits.uop.ctrl.isRVF
   val instr_rm = input.bits.uop.ctrl.fpu.rm
-  val (src1, src2) = (input.bits.src1, input.bits.src2)
+  val (src1, src2) = (input.bits.src(0), input.bits.src(1))
 
   supportedFunctionUnits.foreach { module =>
     module.io.in.bits.src(0) := src1
diff --git a/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala b/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala
index aa295060fe0e090010005e517acb0cc4720d713f..6c15b6340d599b10508421cbb48298a0d1e4262d 100644
--- a/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala
+++ b/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala
@@ -11,8 +11,8 @@ class MulDivExeUnit(implicit p: Parameters) extends Exu(MulDivExeUnitCfg) {
 
   val func = io.fromInt.bits.uop.ctrl.fuOpType
   val (src1, src2) = (
-    io.fromInt.bits.src1(XLEN - 1, 0),
-    io.fromInt.bits.src2(XLEN - 1, 0)
+    io.fromInt.bits.src(0)(XLEN - 1, 0),
+    io.fromInt.bits.src(1)(XLEN - 1, 0)
   )
 
   val mul = supportedFunctionUnits.collectFirst {
diff --git a/src/main/scala/xiangshan/backend/fu/Alu.scala b/src/main/scala/xiangshan/backend/fu/Alu.scala
index 5a373708d13062b1d9507e919da0f69c3d3f727f..202f3389ef1c52e6844ae718558791890dde32ef 100644
--- a/src/main/scala/xiangshan/backend/fu/Alu.scala
+++ b/src/main/scala/xiangshan/backend/fu/Alu.scala
@@ -8,18 +8,18 @@ import xiangshan._
 
 class AddModule(implicit p: Parameters) extends XSModule {
   val io = IO(new Bundle() {
-    val src1, src2 = Input(UInt(XLEN.W))
+    val src = Vec(2, Input(UInt(XLEN.W)))
     val out = Output(UInt((XLEN+1).W))
   })
-  io.out := io.src1 +& io.src2
+  io.out := io.src(0) +& io.src(1)
 }
 
 class SubModule(implicit p: Parameters) extends XSModule {
   val io = IO(new Bundle() {
-    val src1, src2 = Input(UInt(XLEN.W))
+    val src = Vec(2, Input(UInt(XLEN.W)))
     val out = Output(UInt((XLEN+1).W))
   })
-  io.out := (io.src1 +& (~io.src2).asUInt()) + 1.U
+  io.out := (io.src(0) +& (~io.src(1)).asUInt()) + 1.U
 }
 
 class LeftShiftModule(implicit p: Parameters) extends XSModule {
@@ -80,21 +80,21 @@ class AluResSel(implicit p: Parameters) extends XSModule {
 
 class AluDataModule(implicit p: Parameters) extends XSModule {
   val io = IO(new Bundle() {
-    val src1, src2 = Input(UInt(XLEN.W))
+    val src = Vec(2, Input(UInt(XLEN.W)))
     val func = Input(FuOpType())
     val pred_taken, isBranch = Input(Bool())
     val result = Output(UInt(XLEN.W))
     val taken, mispredict = Output(Bool())
   })
-  val (src1, src2, func) = (io.src1, io.src2, io.func)
+  val (src1, src2, func) = (io.src(0), io.src(1), io.func)
 
   val isAdderSub = (func =/= ALUOpType.add) && (func =/= ALUOpType.addw)
   val addModule = Module(new AddModule)
-  addModule.io.src1 := src1
-  addModule.io.src2 := src2
+  addModule.io.src(0) := src1
+  addModule.io.src(1) := src2
   val subModule = Module(new SubModule)
-  subModule.io.src1 := src1
-  subModule.io.src2 := src2
+  subModule.io.src(0) := src1
+  subModule.io.src(1) := src2
   val addRes = addModule.io.out
   val subRes = subModule.io.out
   val xorRes = src1 ^ src2
@@ -164,8 +164,8 @@ class Alu(implicit p: Parameters) extends FunctionUnit with HasRedirectOut {
   val isBranch = ALUOpType.isBranch(func)
   val dataModule = Module(new AluDataModule)
 
-  dataModule.io.src1 := src1
-  dataModule.io.src2 := src2
+  dataModule.io.src(0) := src1
+  dataModule.io.src(1) := src2
   dataModule.io.func := func
   dataModule.io.pred_taken := uop.cf.pred_taken
   dataModule.io.isBranch := isBranch
diff --git a/src/main/scala/xiangshan/backend/fu/Jump.scala b/src/main/scala/xiangshan/backend/fu/Jump.scala
index 31b54672fbcebcd8ff775d603de486e0b714fe0e..7bc3bae67506ebbbf02eaf449f540e656b57cae8 100644
--- a/src/main/scala/xiangshan/backend/fu/Jump.scala
+++ b/src/main/scala/xiangshan/backend/fu/Jump.scala
@@ -16,7 +16,7 @@ trait HasRedirectOut { this: XSModule =>
 
 class JumpDataModule(implicit p: Parameters) extends XSModule {
   val io = IO(new Bundle() {
-    val src1 = Input(UInt(XLEN.W))
+    val src = Input(UInt(XLEN.W))
     val pc = Input(UInt(XLEN.W)) // sign-ext to XLEN
     val immMin = Input(UInt(ImmUnion.maxLen.W))
     val func = Input(FuOpType())
@@ -24,7 +24,7 @@ class JumpDataModule(implicit p: Parameters) extends XSModule {
     val result, target = Output(UInt(XLEN.W))
     val isAuipc = Output(Bool())
   })
-  val (src1, pc, immMin, func, isRVC) = (io.src1, io.pc, io.immMin, io.func, io.isRVC)
+  val (src1, pc, immMin, func, isRVC) = (io.src, io.pc, io.immMin, io.func, io.isRVC)
 
   val isJalr = JumpOpType.jumpOpisJalr(func)
   val isAuipc = JumpOpType.jumpOpisAuipc(func)
@@ -58,7 +58,7 @@ class Jump(implicit p: Parameters) extends FunctionUnit with HasRedirectOut {
   val isRVC = uop.cf.pd.isRVC
 
   val jumpDataModule = Module(new JumpDataModule)
-  jumpDataModule.io.src1 := src1
+  jumpDataModule.io.src := src1
   jumpDataModule.io.pc := pc
   jumpDataModule.io.immMin := immMin
   jumpDataModule.io.func := func
diff --git a/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala b/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala
index caf61545f92eb4ab7a6a4201c4967206046a928e..baf5a34d9afcfd5c50a568146811005b63001a1b 100644
--- a/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala
+++ b/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala
@@ -14,7 +14,7 @@ import xiangshan.backend.fu.util.CSA3_2
   */
 class SRT4DividerDataModule(len: Int) extends Module {
   val io = IO(new Bundle() {
-    val src1, src2 = Input(UInt(len.W))
+    val src = Vec(2, Input(UInt(len.W)))
     val valid, sign, kill_w, kill_r, isHi, isW = Input(Bool())
     val in_ready = Output(Bool())
     val out_valid = Output(Bool())
@@ -23,7 +23,7 @@ class SRT4DividerDataModule(len: Int) extends Module {
   })
 
   val (a, b, sign, valid, kill_w, kill_r, isHi, isW) =
-    (io.src1, io.src2, io.sign, io.valid, io.kill_w, io.kill_r, io.isHi, io.isW)
+    (io.src(0), io.src(1), io.sign, io.valid, io.kill_w, io.kill_r, io.isHi, io.isW)
   val in_fire = valid && io.in_ready
   val out_fire = io.out_ready && io.out_valid
 
@@ -267,8 +267,8 @@ class SRT4Divider(len: Int)(implicit p: Parameters) extends AbstractDivider(len)
   val kill_w = uop.roqIdx.needFlush(io.redirectIn, io.flushIn)
   val kill_r = !divDataModule.io.in_ready && uopReg.roqIdx.needFlush(io.redirectIn, io.flushIn)
 
-  divDataModule.io.src1 := io.in.bits.src(0)
-  divDataModule.io.src2 := io.in.bits.src(1)
+  divDataModule.io.src(0) := io.in.bits.src(0)
+  divDataModule.io.src(1) := io.in.bits.src(1)
   divDataModule.io.valid := io.in.valid
   divDataModule.io.sign := sign
   divDataModule.io.kill_w := kill_w
diff --git a/src/main/scala/xiangshan/backend/issue/ReservationStation.scala b/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
index fe660ab4f6a9e455dedb71d6b88434977b7f05df..282ad1355c0d2c5116191751b74e4ca03acfd387 100644
--- a/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
+++ b/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
@@ -203,9 +203,9 @@ class ReservationStation
   io.deq.bits.uop  := ctrl.io.out.bits
   io.deq.bits.uop.cf.exceptionVec := 0.U.asTypeOf(ExceptionVec())
   io.deq.valid     := ctrl.io.out.valid
-  io.deq.bits.src1 := data.io.out(0)
-  if (srcNum > 1) { io.deq.bits.src2 := data.io.out(1) }
-  if (srcNum > 2) { io.deq.bits.src3 := data.io.out(2) }
+  io.deq.bits.src(0) := data.io.out(0)
+  if (srcNum > 1) { io.deq.bits.src(1) := data.io.out(1) }
+  if (srcNum > 2) { io.deq.bits.src(2) := data.io.out(2) }
   if (exuCfg == JumpExeUnitCfg) { io.deq.bits.uop.cf.pc := data.io.pc }
 
   if (exuCfg == StExeUnitCfg) {
diff --git a/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala b/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
index 7480e5da17aef98eeaf9cd25d0eaa8680b86dd8a..08f7470b8646b24ede185914a2f8958b3549dcf4 100644
--- a/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
+++ b/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
@@ -48,7 +48,7 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstant
   val fuop_reg = Reg(UInt(8.W))
 
   io.exceptionAddr.valid := atom_override_xtval
-  io.exceptionAddr.bits  := in.src1
+  io.exceptionAddr.bits  := in.src(0)
 
   // assign default value to output signals
   io.in.ready          := false.B
@@ -71,11 +71,11 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstant
     io.in.ready := true.B
     when (io.in.fire()) {
       in := io.in.bits
-      in.src2 := in.src2 // leave src2 unchanged
+      in.src(1) := in.src(1) // leave src2 unchanged
       addr_valid := true.B
     }
     when (io.storeDataIn.fire()) {
-      in.src2 := io.storeDataIn.bits.data
+      in.src(1) := io.storeDataIn.bits.data
       data_valid := true.B
     }
     when(data_valid && addr_valid) {
@@ -101,7 +101,7 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstant
     // send req to dtlb
     // keep firing until tlb hit
     io.dtlb.req.valid       := true.B
-    io.dtlb.req.bits.vaddr  := in.src1
+    io.dtlb.req.bits.vaddr  := in.src(0)
     io.dtlb.req.bits.roqIdx := in.uop.roqIdx
     io.dtlb.resp.ready      := true.B
     val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d
@@ -113,9 +113,9 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstant
       // exception handling
       val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List(
         "b00".U   -> true.B,              //b
-        "b01".U   -> (in.src1(0) === 0.U),   //h
-        "b10".U   -> (in.src1(1,0) === 0.U), //w
-        "b11".U   -> (in.src1(2,0) === 0.U)  //d
+        "b01".U   -> (in.src(0)(0) === 0.U),   //h
+        "b10".U   -> (in.src(0)(1,0) === 0.U), //w
+        "b11".U   -> (in.src(0)(2,0) === 0.U)  //d
       ))
       exceptionVec(storeAddrMisaligned) := !addrAligned
       exceptionVec(storePageFault)      := io.dtlb.resp.bits.excp.pf.st
@@ -181,7 +181,7 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstant
     ))
 
     io.dcache.req.bits.addr := paddr
-    io.dcache.req.bits.data := genWdata(in.src2, in.uop.ctrl.fuOpType(1,0))
+    io.dcache.req.bits.data := genWdata(in.src(1), in.uop.ctrl.fuOpType(1,0))
     // TODO: atomics do need mask: fix mask
     io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0))
     io.dcache.req.bits.id   := DontCare
diff --git a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
index 918b1535beba41cb64ea7723cf101d0224e1ecb0..33d9dfda4321cfb9c38c690c9fcf4e65455083e5 100644
--- a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
+++ b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
@@ -29,13 +29,13 @@ class LoadUnit_S0(implicit p: Parameters) extends XSModule {
   })
 
   val s0_uop = io.in.bits.uop
-  // val s0_vaddr = io.in.bits.src1 + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits)
+  // val s0_vaddr = io.in.bits.src(0) + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits)
   // val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0))
   val imm12 = WireInit(s0_uop.ctrl.imm(11,0))
-  val s0_vaddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12)
+  val s0_vaddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12)
   val s0_vaddr_hi = Mux(s0_vaddr_lo(12),
-    Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+1.U),
-    Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src1(VAddrBits-1, 12)),
+    Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U),
+    Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)),
   )
   val s0_vaddr = Cat(s0_vaddr_hi, s0_vaddr_lo(11,0))
   val s0_mask = genWmask(s0_vaddr_lo, s0_uop.ctrl.fuOpType(1,0))
@@ -82,10 +82,10 @@ class LoadUnit_S0(implicit p: Parameters) extends XSModule {
   XSPerfAccumulate("in", io.in.valid)
   XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready && io.dcacheReq.ready)
   XSPerfAccumulate("stall_dcache", io.out.valid && io.out.ready && !io.dcacheReq.ready)
-  XSPerfAccumulate("addr_spec_success", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src1(VAddrBits-1, 12))
-  XSPerfAccumulate("addr_spec_failed", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src1(VAddrBits-1, 12))
-  XSPerfAccumulate("addr_spec_success_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src1(VAddrBits-1, 12) && io.isFirstIssue)
-  XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src1(VAddrBits-1, 12) && io.isFirstIssue)
+  XSPerfAccumulate("addr_spec_success", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12))
+  XSPerfAccumulate("addr_spec_failed", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12))
+  XSPerfAccumulate("addr_spec_success_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue)
+  XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue)
 }
 
 
diff --git a/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala b/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
index 78d9881899ec9fe5f89b1c5ba87df9103aaf65dc..520544d81eaa95e09516bb6e8dbcedd425c55818 100644
--- a/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
+++ b/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
@@ -20,12 +20,12 @@ class StoreUnit_S0(implicit p: Parameters) extends XSModule {
   })
 
   // send req to dtlb
-  // val saddr = io.in.bits.src1 + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits)
+  // val saddr = io.in.bits.src(0) + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits)
   val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0))
-  val saddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12)
+  val saddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12)
   val saddr_hi = Mux(saddr_lo(12),
-    Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+1.U),
-    Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src1(VAddrBits-1, 12)),
+    Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U),
+    Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)),
   )
   val saddr = Cat(saddr_hi, saddr_lo(11,0))
 
@@ -40,8 +40,8 @@ class StoreUnit_S0(implicit p: Parameters) extends XSModule {
   io.out.bits.vaddr := saddr
 
   // Now data use its own io
-  // io.out.bits.data := genWdata(io.in.bits.src2, io.in.bits.uop.ctrl.fuOpType(1,0))
-  io.out.bits.data := io.in.bits.src2 // FIXME: remove data from pipeline
+  // io.out.bits.data := genWdata(io.in.bits.src(1), io.in.bits.uop.ctrl.fuOpType(1,0))
+  io.out.bits.data := io.in.bits.src(1) // FIXME: remove data from pipeline
   io.out.bits.uop := io.in.bits.uop
   io.out.bits.miss := DontCare
   io.out.bits.rsIdx := io.rsIdx
@@ -58,10 +58,10 @@ class StoreUnit_S0(implicit p: Parameters) extends XSModule {
   ))
   io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned
 
-  XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src1(VAddrBits-1, 12))
-  XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src1(VAddrBits-1, 12))
-  XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src1(VAddrBits-1, 12) && io.isFirstIssue)
-  XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src1(VAddrBits-1, 12) && io.isFirstIssue)
+  XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12))
+  XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12))
+  XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue)
+  XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue)
 }
 
 // Load Pipeline Stage 1
diff --git a/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala b/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
index 990fa974370f9810561cf4004fe1e096480ba46f..bdfa6c81eb33b5d240cc57acf7fa7d14c0a3daec 100644
--- a/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
+++ b/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
@@ -35,8 +35,8 @@ object TestCaseGenerator {
 
   def genAluInput(fuOpType: UInt)(x: => ExuInput, src1: Long, src2: Long, imm: Long): ExuInput = {
     chiselTypeOf(x).Lit(
-      _.src1 -> src1.U,
-      _.src2 -> src2.U,
+      _.src(0) -> src1.U,
+      _.src(1) -> src2.U,
       _.uop.ctrl.imm -> imm.U,
       _.uop.ctrl.fuOpType -> fuOpType
     )
@@ -52,8 +52,8 @@ object TestCaseGenerator {
    */
   def genLsuInput(fuOpType: UInt)(x: => ExuInput, base: Long, offset: Long, stData: Long): ExuInput ={
     chiselTypeOf(x).Lit(
-      _.src1 -> base.U,
-      _.src2 -> stData.U,
+      _.src(0) -> base.U,
+      _.src(1) -> stData.U,
       _.uop.ctrl.imm -> offset.U,
       _.uop.ctrl.fuOpType -> fuOpType
     )