From 28958354979421a6ba4dca0f2897d0ca0561c159 Mon Sep 17 00:00:00 2001
From: zhanglinjuan <zhanglinjuan16@mails.ucas.ac.cn>
Date: Wed, 29 Jul 2020 18:55:03 +0800
Subject: [PATCH] bundle: re-define FetchPacket and CtrlFlow

---
 src/main/scala/xiangshan/Bundle.scala | 19 ++++++-------------
 1 file changed, 6 insertions(+), 13 deletions(-)

diff --git a/src/main/scala/xiangshan/Bundle.scala b/src/main/scala/xiangshan/Bundle.scala
index 8b3c8a4eb..729972479 100644
--- a/src/main/scala/xiangshan/Bundle.scala
+++ b/src/main/scala/xiangshan/Bundle.scala
@@ -9,20 +9,14 @@ import xiangshan.frontend.PreDecodeInfo
 
 // Fetch FetchWidth x 32-bit insts from Icache
 class FetchPacket extends XSBundle {
-  val instrs = Vec(FetchWidth, UInt(32.W))
-  val mask = UInt((FetchWidth*2).W)
-  val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group
-  val pnpc = Vec(FetchWidth*2, UInt(VAddrBits.W))
-  val hist = Vec(FetchWidth*2, UInt(HistoryLength.W))
-  // val btbVictimWay = UInt(log2Up(BtbWays).W)
-  val predCtr = Vec(FetchWidth*2, UInt(2.W))
-  val btbHit = Vec(FetchWidth*2, Bool())
-  val tageMeta = Vec(FetchWidth*2, (new TageMeta))
-  val rasSp = UInt(log2Up(RasSize).W)
-  val rasTopCtr = UInt(8.W)
+  val instrs = Vec(PredictWidth, UInt(32.W))
+  val mask = UInt(PredictWidth.W)
+  val pc = UInt(VAddrBits.W)
+  val pnpc = Vec(PredictWidth, UInt(VAddrBits.W))
+  val brInfo = Vec(PredictWidth, (new BranchInfo))
+  val pd = Vec(PredictWidth, (new PreDecodeInfo))
 }
 
-
 class ValidUndirectioned[T <: Data](gen: T) extends Bundle {
   val valid = Bool()
   val bits = gen.asInstanceOf[T]
@@ -72,7 +66,6 @@ class Predecode extends XSBundle {
   val pd = Vec(FetchWidth*2, (new PreDecodeInfo))
 }
 
-
 class BranchUpdateInfo extends XSBundle {
   // from backend
   val pnpc = UInt(VAddrBits.W)
-- 
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