diff --git a/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala b/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala
index b5c1561bb1d975e1cf0f633328b4c758ba1afac1..3981c45db5617da9944b16ef71106886e1b8717e 100644
--- a/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala
+++ b/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala
@@ -271,71 +271,4 @@ class MEFreeList(implicit val p: config.Parameters) extends MultiIOModule with M
     archRefCounter(i) :=   Mux(clearArchRefCounter(i), 0.U, Mux(updateArchRefCounter(i), archRefCounterNext(i), archRefCounter(i) ))
     cmtCounter(i)     :=   Mux(clearCmtCounter(i),     0.U, Mux(updateCmtCounter(i),     cmtCounterNext(i),     cmtCounter(i)     ))
   }
-
-
-  /*
-  Re-direct: restore by walking, handled by rename using `dec` port
-   */
-
-
-
-  /*
-  Debug Info
-   */
-  for (i <- 0 until NRPhyRegs) {
-    XSDebug(specRefCounter(i) =/= 0.U || archRefCounter(i) =/= 0.U || cmtCounter(i) =/= 0.U, 
-      p"preg[$i] specRefCounter:${specRefCounter(i)} archRefCounter:${archRefCounter(i)} cmtCounter:${cmtCounter(i)}\n")
-    XSDebug(specRefCounter(i) =/= 0.U || archRefCounter(i) =/= 0.U || cmtCounter(i) =/= 0.U, 
-      p"preg[$i] specRefCounterNext:${specRefCounterNext(i)} archRefCounterNext:${archRefCounterNext(i)} cmtCounterNext:${cmtCounterNext(i)}\n")
-
-    // specRefCounter(i) must >= cmtCounter(i)
-    XSError(specRefCounter(i) < cmtCounter(i), p"Commits Overflow of preg${i}")
-  }
-
-  XSDebug(Array.range(0, MEFreeListSize).map(x => x.toString()).mkString("Free List (idx): ", "\t", "\n"))
-  XSDebug(p"Free List (val): " + Array.range(0, MEFreeListSize).map(x => p"${freeList(x)}\t").reduceLeft(_ + _) + "\n")
-
-  XSDebug(p"head:$headPtr tail:$tailPtr headPtrNext:$headPtrNext tailPtrNext:$tailPtrNext freeRegCnt:$freeRegCnt\n")
-
-  XSDebug(p"flush ${flush} redirect ${redirect} walk ${walk}\n")
-
-  XSDebug(PopCount(freeReq) =/= PopCount(freeVec), p"WARNING: Please check DEC requirement\n")
-  XSDebug(PopCount(allocateReq) =/= PopCount(needAllocatingVec), p"WARNING: Please check INC requirement\n")
-
-
-  /*
-  Assertions
-   */
-  val enableFreeListCheck = false
-
-  if (enableFreeListCheck) {
-
-    for (i <- 0 until RenameWidth) {
-      for (j <- (i + 1) until RenameWidth) {
-        XSError(needAllocatingVec(i) && needAllocatingVec(j) && allocatePhyReg(i) === allocatePhyReg(j),
-          p"Duplicate INC requirements detected!" + allocatePhyReg.zipWithIndex.map{case (p, idx) => p" ($idx):$p"}.reduceLeft(_ + _) + "\n")
-        XSError(allocateReq(i) && allocateReq(j) && canAllocate && doAllocate && psrcOfMove(i).valid && psrcOfMove(j).valid && psrcOfMove(i).bits === psrcOfMove(j).bits,
-          p"Duplicate ME requirements detected! Cannot inc same specRefCount in 1 cycle!\n")
-      }
-      // also, we cannot count ref numbers more than 3 (which is very rare)
-      XSError(needAllocatingVec(i) && !psrcOfMove(i).valid && specRefCounter(allocatePhyReg(i)).andR(), p"(norm) Exceeding specRefCounter Max Value: preg[${allocatePhyReg(i)}]\n")
-      XSError(allocateReq(i) && canAllocate && doAllocate && psrcOfMove(i).valid && specRefCounter(psrcOfMove(i).bits).andR(), p"(move) Exceeding specRefCounter Max Value: preg[${psrcOfMove(i).bits}]\n")
-    }
-
-    for (i <- 0 until CommitWidth) {
-      // we cannot handle duplicate inc/dec requirements on a preg in 1 cycle for now
-      for (j <- (i + 1) until CommitWidth) {
-        XSInfo(freeReq(i) && freeReq(j) && freePhyReg(i) === freePhyReg(j), 
-          p"Duplicate DEC requirements detected!" + freePhyReg.zipWithIndex.map{case (p, idx) => p" ($idx):$p"}.reduceLeft(_ + _) + "\n")
-        XSInfo(freeReq(i) && freeReq(j) && eliminatedMove(i) && eliminatedMove(j) && multiRefPhyReg(i) === multiRefPhyReg(j), 
-          p"Duplicate INC requirements on archRefCount detected!" + multiRefPhyReg.zipWithIndex.map{case (p, idx) => p" ($idx):$p"}.reduceLeft(_ + _) + "\n")
-        XSError(freeVec(i) && freeVec(j) && freePhyReg(i) === freePhyReg(j), "Fatal Error: free 1 reg 2 times in 1 cycle!\n")
-      }
-      // not inc and dec same reg in 1 cycle
-      for (j <- 0 until RenameWidth) {
-        XSDebug(allocateReq(j) && canAllocate && doAllocate && psrcOfMove(j).valid && !redirect && !walk &&
-          freeReq(i) && freePhyReg(i) === allocatePhyReg(j), p"INC and DEC Conflict Detected! inc($j): preg ${allocatePhyReg(j)}, dec($i): preg ${freePhyReg(i)}\n")
-      }
-    }
-  }
 }