From 1d0717ae7d7f24adbe9ae0e7ff8a56ac927357f2 Mon Sep 17 00:00:00 2001
From: zoujr <18870680299@163.com>
Date: Thu, 21 Jan 2021 22:12:18 +0800
Subject: [PATCH] BPU: Fix uBtb and Btb bug

---
 src/main/scala/utils/ExcitingUtils.scala      |  2 +-
 src/main/scala/xiangshan/backend/fu/CSR.scala | 10 +++++-----
 src/main/scala/xiangshan/frontend/Btb.scala   |  2 +-
 src/main/scala/xiangshan/frontend/uBTB.scala  |  2 +-
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/main/scala/utils/ExcitingUtils.scala b/src/main/scala/utils/ExcitingUtils.scala
index 14cd5bba2..4281f3fe1 100644
--- a/src/main/scala/utils/ExcitingUtils.scala
+++ b/src/main/scala/utils/ExcitingUtils.scala
@@ -59,7 +59,7 @@ object ExcitingUtils {
     forceExists: Boolean = false
   ): Unit = {
     val conn = map.getOrElseUpdate(name, new Connection(connType))
-    require(conn.sinkModule.isEmpty)
+    // require(conn.sinkModule.isEmpty)
     require(conn.connType == connType)
     conn.sinkModule = Some(component.parentModName)
     BoringUtils.addSink(component, name, disableDedup, forceExists)
diff --git a/src/main/scala/xiangshan/backend/fu/CSR.scala b/src/main/scala/xiangshan/backend/fu/CSR.scala
index b7b2381ae..4fd98c845 100644
--- a/src/main/scala/xiangshan/backend/fu/CSR.scala
+++ b/src/main/scala/xiangshan/backend/fu/CSR.scala
@@ -803,7 +803,7 @@ class CSR extends FunctionUnit with HasCSRConst
     "LoopExit"   -> (0x102a, "perfCntLoopExit"     ),
     "isReplay"   -> (0x102b, "Replay"     ),
     // "FetchFromICache" -> (0x102a, "CntFetchFromICache"),
-    "ICacheMMIO" -> (0x102a, "perfCntIcacheMMIOCnt"),
+    "ICacheMMIO" -> (0x102c, "perfCntIcacheMMIOCnt"),
     // "FetchFromLoopBuffer" -> (0x102b, "CntFetchFromLoopBuffer"),
     // "ExitLoop1" -> (0x102c, "CntExitLoop1"),
     // "ExitLoop2" -> (0x102d, "CntExitLoop2"),
@@ -820,19 +820,19 @@ class CSR extends FunctionUnit with HasCSRConst
     // "L2cacheHit" -> (0x1023, "perfCntCondL2cacheHit")
   ) ++ (
     (0 until dcacheParameters.nMissEntries).map(i =>
-      ("DCacheMissQueuePenalty" + Integer.toString(i, 10), (0x102a + i, "perfCntDCacheMissQueuePenaltyEntry" + Integer.toString(i, 10)))
+      ("DCacheMissQueuePenalty" + Integer.toString(i, 10), (0x1040 + i, "perfCntDCacheMissQueuePenaltyEntry" + Integer.toString(i, 10)))
     ).toMap
   ) ++ (
     (0 until icacheParameters.nMissEntries).map(i =>
-      ("ICacheMissQueuePenalty" + Integer.toString(i, 10), (0x102a + dcacheParameters.nMissEntries + i, "perfCntICacheMissQueuePenaltyEntry" + Integer.toString(i, 10)))
+      ("ICacheMissQueuePenalty" + Integer.toString(i, 10), (0x1040 + dcacheParameters.nMissEntries + i, "perfCntICacheMissQueuePenaltyEntry" + Integer.toString(i, 10)))
     ).toMap
   ) ++ (
     (0 until l1plusPrefetcherParameters.nEntries).map(i =>
-      ("L1+PrefetchPenalty" + Integer.toString(i, 10), (0x102a + dcacheParameters.nMissEntries + icacheParameters.nMissEntries + i, "perfCntL1plusPrefetchPenaltyEntry" + Integer.toString(i, 10)))
+      ("L1+PrefetchPenalty" + Integer.toString(i, 10), (0x1040 + dcacheParameters.nMissEntries + icacheParameters.nMissEntries + i, "perfCntL1plusPrefetchPenaltyEntry" + Integer.toString(i, 10)))
     ).toMap
   ) ++ (
     (0 until l2PrefetcherParameters.nEntries).map(i =>
-      ("L2PrefetchPenalty" + Integer.toString(i, 10), (0x102a + dcacheParameters.nMissEntries + icacheParameters.nMissEntries + l1plusPrefetcherParameters.nEntries + i, "perfCntL2PrefetchPenaltyEntry" + Integer.toString(i, 10)))
+      ("L2PrefetchPenalty" + Integer.toString(i, 10), (0x1040 + dcacheParameters.nMissEntries + icacheParameters.nMissEntries + l1plusPrefetcherParameters.nEntries + i, "perfCntL2PrefetchPenaltyEntry" + Integer.toString(i, 10)))
     ).toMap
   )
 
diff --git a/src/main/scala/xiangshan/frontend/Btb.scala b/src/main/scala/xiangshan/frontend/Btb.scala
index ca274a599..1b1e797a4 100644
--- a/src/main/scala/xiangshan/frontend/Btb.scala
+++ b/src/main/scala/xiangshan/frontend/Btb.scala
@@ -189,7 +189,7 @@ class BTB extends BasePredictor with BTBParams{
   val dataWrite = BtbDataEntry(new_lower, new_extended)
 
   val jalFirstEncountered = !u.isMisPred && !u.bpuMeta.btbHitJal && updateType === BTBtype.J
-  val updateValid = io.update.valid && (u.isMisPred || jalFirstEncountered) && !u.isReplay
+  val updateValid = io.update.bits.taken && io.update.valid && (u.isMisPred || jalFirstEncountered) && !u.isReplay
   // Update btb
   for (w <- 0 until BtbWays) {
     for (b <- 0 until BtbBanks) {
diff --git a/src/main/scala/xiangshan/frontend/uBTB.scala b/src/main/scala/xiangshan/frontend/uBTB.scala
index 86ff187fc..3040e4b0b 100644
--- a/src/main/scala/xiangshan/frontend/uBTB.scala
+++ b/src/main/scala/xiangshan/frontend/uBTB.scala
@@ -229,7 +229,7 @@ class MicroBTB extends BasePredictor
   
   
     val jalFirstEncountered = !u.isMisPred && !u.bpuMeta.btbHitJal && (u.pd.brType === BrType.jal)
-    val entry_write_valid = io.update.valid && (u.isMisPred || jalFirstEncountered) && !u.isReplay //io.update.valid //&& update_is_BR_or_JAL
+    val entry_write_valid = io.update.valid && update_taken && (u.isMisPred || jalFirstEncountered) && !u.isReplay //io.update.valid //&& update_is_BR_or_JAL
     val meta_write_valid = io.update.valid && (u.isMisPred || jalFirstEncountered) && !u.isReplay//io.update.valid //&& update_is_BR_or_JAL
 
     for (b <- 0 until PredictWidth) {
-- 
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