diff --git a/src/main/scala/xiangshan/mem/Lsroq.scala b/src/main/scala/xiangshan/mem/Lsroq.scala
index 88e254124cf941614a2acb7960ece8c9f749941f..f285f11c1061284c2fd58bd101604c41484c4d48 100644
--- a/src/main/scala/xiangshan/mem/Lsroq.scala
+++ b/src/main/scala/xiangshan/mem/Lsroq.scala
@@ -326,11 +326,6 @@ class Lsroq extends XSModule {
   // send commited store inst to sbuffer
   // select up to 2 writebacked store insts
   // scommitPending, scommitIn, scommitOut are for debug only
-  val scommitPending = RegInit(0.U(log2Up(LsroqSize).W))
-  val scommitIn = PopCount(VecInit(storeCommit).asUInt)
-  val scommitOut = PopCount(VecInit((0 until 2).map(i => io.sbuffer(i).fire())).asUInt)
-  scommitPending := scommitPending + scommitIn - scommitOut
-
   val commitedStoreQueue = Module(new MIMOQueue(
     UInt(InnerLsroqIdxWidth.W),
     entries = LsroqSize,
@@ -340,6 +335,12 @@ class Lsroq extends XSModule {
     perf = true
   ))
 
+  // scommit counter for debugging
+  val scommitPending = RegInit(0.U(log2Up(LsroqSize).W))
+  val scommitIn = PopCount(VecInit(storeCommit).asUInt)
+  val scommitOut = PopCount(VecInit((0 until 2).map(i => commitedStoreQueue.io.deq(i).fire())).asUInt)
+  scommitPending := scommitPending + scommitIn - scommitOut
+
   commitedStoreQueue.io.flush := false.B
 
   // When store commited, mark it as commited (will not be influenced by redirect),