diff --git a/src/main/scala/xiangshan/cache/atomicsMissQueue.scala b/src/main/scala/xiangshan/cache/atomicsMissQueue.scala
index 06934a9ed79827cf5fcc78d519a140114b5c5a0a..8702d09f39fe706bf33c5f621ef074a105fbed4b 100644
--- a/src/main/scala/xiangshan/cache/atomicsMissQueue.scala
+++ b/src/main/scala/xiangshan/cache/atomicsMissQueue.scala
@@ -56,6 +56,9 @@ class AtomicsMissQueue extends DCacheModule
   when (state === s_replay_req) {
     io.replay.req.valid := true.B
     io.replay.req.bits  := req
+    // use our own storeMissEntryId
+    // miss resp are routed by this id
+    io.replay.req.bits.meta.id := id
     when (io.replay.req.fire()) {
       state := s_replay_resp
     }
@@ -113,6 +116,8 @@ class AtomicsMissQueue extends DCacheModule
   when (state === s_resp) {
     io.lsu.resp.valid := true.B
     io.lsu.resp.bits  := resp
+    // response to sbuffer should carry the original request id
+    io.lsu.resp.bits.meta.id := req.meta.id
 
     when (io.lsu.resp.fire()) {
       state := s_invalid
diff --git a/src/main/scala/xiangshan/cache/storeMissQueue.scala b/src/main/scala/xiangshan/cache/storeMissQueue.scala
index 28c2f234262c4b82c3a77f7ba49b2ef39e1d213b..4b28456da312d0e5aa36ebd41a774bb35028459d 100644
--- a/src/main/scala/xiangshan/cache/storeMissQueue.scala
+++ b/src/main/scala/xiangshan/cache/storeMissQueue.scala
@@ -70,6 +70,9 @@ class StoreMissEntry extends DCacheModule
   when (state === s_replay_req) {
     io.replay.req.valid := true.B
     io.replay.req.bits  := req
+    // use our own storeMissEntryId
+    // miss resp are routed by this id
+    io.replay.req.bits.meta.id := io.id
     when (io.replay.req.fire()) {
       state := s_replay_resp
     }
@@ -127,6 +130,8 @@ class StoreMissEntry extends DCacheModule
   when (state === s_resp) {
     io.lsu.resp.valid := true.B
     io.lsu.resp.bits  := resp
+    // response to sbuffer should carry the original request id
+    io.lsu.resp.bits.meta.id := req.meta.id
 
     when (io.lsu.resp.fire()) {
       state := s_invalid