From 1545277abc67bbe5123a324f0b61142535bfe61f Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Thu, 11 Nov 2021 10:03:16 +0800 Subject: [PATCH] top: enable fpga option for simulation emu (#1213) * disable log as default * code clean up --- .github/workflows/emu.yml | 8 +- Makefile | 28 ++- README.md | 2 +- difftest | 2 +- readme.zh-cn.md | 192 +++++++++--------- scripts/xiangshan.py | 9 +- src/main/scala/top/ArgParser.scala | 26 +-- src/main/scala/utils/LogUtils.scala | 7 +- src/main/scala/xiangshan/Parameters.scala | 5 +- src/main/scala/xiangshan/XSCore.scala | 8 - .../scala/xiangshan/backend/Scheduler.scala | 4 +- .../xiangshan/backend/dispatch/Dispatch.scala | 2 +- src/main/scala/xiangshan/backend/fu/CSR.scala | 19 +- .../scala/xiangshan/backend/rob/Rob.scala | 16 +- .../cache/dcache/mainpipe/MissQueue.scala | 2 +- .../xiangshan/mem/lsqueue/StoreQueue.scala | 2 +- .../xiangshan/mem/pipeline/AtomicsUnit.scala | 2 +- .../scala/xiangshan/mem/sbuffer/Sbuffer.scala | 2 +- src/test/scala/top/SimTop.scala | 20 +- 19 files changed, 170 insertions(+), 186 deletions(-) diff --git a/.github/workflows/emu.yml b/.github/workflows/emu.yml index b55cca223..4034e782b 100644 --- a/.github/workflows/emu.yml +++ b/.github/workflows/emu.yml @@ -31,10 +31,10 @@ jobs: - name: check verilog run: python3 $GITHUB_WORKSPACE/.github/workflows/check_verilog.py build/XSTop.v - - name: build MinimalConfig emu + - name: build MinimalConfig Release emu run: | python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build \ - --disable-log --threads 4 --config MinimalConfig + --threads 4 --config MinimalConfig --release - name: run MinimalConfig - Linux run: | python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 4 --numa --ci linux-hello 2> perf.log @@ -59,7 +59,7 @@ jobs: mkdir -p /bigdata/xs-wave/${HEAD_SHA} - name: Build EMU run: | - python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --build --disable-log --threads 8 + python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --build --threads 8 - name: Basic Test - cputest run: | python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --ci cputest 2> /dev/zero @@ -107,7 +107,7 @@ jobs: run: | python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build \ --dramsim3 /home/ci-runner/xsenv/DRAMsim3 \ - --disable-log --with-dramsim3 --threads 16 + --with-dramsim3 --threads 16 - name: SPEC06 Test - mcf run: | python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 16 --max-instr 5000000 --numa --ci mcf 2> perf.log diff --git a/Makefile b/Makefile index c00ee511b..81300c45a 100644 --- a/Makefile +++ b/Makefile @@ -35,6 +35,13 @@ endif override SIM_ARGS += --with-dramsim3 endif +# emu for the release version +RELEASE_ARGS = --disable-all --remove-assert --fpga-platform +DEBUG_ARGS = --enable-difftest +ifeq ($(RELEASE),1) +override SIM_ARGS += $(RELEASE_ARGS) +endif + TIMELOG = $(BUILD_DIR)/time.log TIME_CMD = time -a -o $(TIMELOG) @@ -45,12 +52,11 @@ help: $(TOP_V): $(SCALA_FILE) mkdir -p $(@D) - mill -i XiangShan.runMain $(FPGATOP) -td $(@D) \ - --config $(CONFIG) --full-stacktrace --output-file $(@F) \ - --disable-all --remove-assert --infer-rw \ - --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf \ - --gen-mem-verilog full $(SIM_ARGS) \ - --num-cores $(NUM_CORES) + mill -i XiangShan.runMain $(FPGATOP) -td $(@D) \ + --config $(CONFIG) --full-stacktrace --output-file $(@F) \ + --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --infer-rw \ + --gen-mem-verilog full --num-cores $(NUM_CORES) \ + $(RELEASE_ARGS) sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@ @git log -n 1 >> .__head__ @git diff >> .__diff__ @@ -68,11 +74,11 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) mkdir -p $(@D) @echo "\n[mill] Generating Verilog files..." > $(TIMELOG) @date -R | tee -a $(TIMELOG) - $(TIME_CMD) mill -i XiangShan.test.runMain $(SIMTOP) -td $(@D) \ - --config $(CONFIG) --full-stacktrace --output-file $(@F) \ - --num-cores $(NUM_CORES) $(SIM_ARGS) --infer-rw \ - --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf \ - --gen-mem-verilog full + $(TIME_CMD) mill -i XiangShan.test.runMain $(SIMTOP) -td $(@D) \ + --config $(CONFIG) --full-stacktrace --output-file $(@F) \ + --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --infer-rw \ + --gen-mem-verilog full --num-cores $(NUM_CORES) \ + $(DEBUG_ARGS) $(SIM_ARGS) @git log -n 1 >> .__head__ @git diff >> .__diff__ @sed -i 's/^/\/\// ' .__head__ diff --git a/README.md b/README.md index 36615721e..a247712fb 100644 --- a/README.md +++ b/README.md @@ -86,7 +86,7 @@ Some of the key directories are shown below. Example: ```bash -make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10 +make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10 ./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so ``` diff --git a/difftest b/difftest index ccc5d7338..fb00a5a7b 160000 --- a/difftest +++ b/difftest @@ -1 +1 @@ -Subproject commit ccc5d73381c4e3a1bf79d8f51aa068dc118b6963 +Subproject commit fb00a5a7b020a1d66f854322c862c8cdaf2fb5a9 diff --git a/readme.zh-cn.md b/readme.zh-cn.md index 92c6d7ce3..3ee78b096 100644 --- a/readme.zh-cn.md +++ b/readme.zh-cn.md @@ -1,96 +1,96 @@ -# 香山 - -香山是一款开源的高性能 RISC-V 处理器。采用 Chisel 硬件设计语言开发，支持 RV64GC 指令集。 - -详细文档将在未来放出。 -English Readme is [here](README.md). - -©2020-2021 中国科学院计算技术研究所版权所有。 - -## 文档和报告 - -在 2021 年 6 月的 RISC-V 中国峰会上，我们给出了超过 20 个技术报告。报告已经更新到[我们的文档仓库](https://github.com/OpenXiangShan/XiangShan-doc)。 - -更多的文档也将持续更新到相同的仓库。 - -## 关注我们 - -Wechat/微信：香山开源处理器 - -
- -Zhihu/知乎：[香山开源处理器](https://www.zhihu.com/people/openxiangshan) - -Weibo/微博：[香山开源处理器](https://weibo.com/u/7706264932) - -可以通过[我们的邮件列表](mailto:xiangshan-all@ict.ac.cn)联系我们。列表中的所有邮件会存档到[这里](https://www.mail-archive.com/xiangshan-all@ict.ac.cn/)。 - -## 处理器架构 - -自 2020 年 6 月开始开发的[雁栖湖](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu)为香山处理器的首个稳定的微架构。目前版本的香山（即南湖）正在 master 分支上不断开发中。 - -微架构概览： -![xs-arch-single](images/xs-arch-simple.svg) - -## 目录概览 - -以下是一些关键目录： - -``` -. -├── fpga # 支持的 FPGA 开发板、用于构建 Vivado 项目的文件 -├── read-to-run # 预建的仿真镜像文件 -├── scripts # 用于敏捷开发的脚本文件 -└── src - ├── test # 测试文件（包括差异测试（diff-test）和模块测试（module-test） 等） - └── main/scala # 设计文件 - ├── bus/tilelink # tilelink 实用工具 - ├── device # 用于仿真的虚拟设备 - ├── difftest # chisel 差异测试接口 - ├── system # SoC 封装 - ├── top # 顶层模块 - ├── utils # 复用封装 - ├── xiangshan # 主体设计代码 - └── xstransforms # 一些实用的 firrtl 变换代码 -``` - -## 生成 Verilog - -* 运行 `make verilog` 以生成 verilog 代码。输出文件为 `build/XSTop.v`。 -* 更多信息详见 `Makefile`。 - -## 仿真运行 - -### 环境搭建 - -* 设定环境变量 `NEMU_HOME` 为[香山 NEMU](https://github.com/OpenXiangShan/NEMU) 在您机器上的绝对路径。 -* 设定环境变量 `NOOP_HOME` 为香山工程文件夹的绝对路径。 -* 设定环境变量 `AM_HOME` 为[香山 AM](https://github.com/OpenXiangShan/nexus-am) 的绝对路径。 -* 项目使用 `mill` 进行 scala 编译，因此需要安装 `mill`，详见 [mill 手动安装指南](https://com-lihaoyi.github.io/mill/mill/Intro_to_Mill.html#_installation)（目前仅英文版本）。 -* 克隆本项目，运行 `make init` 以初始化本项目引用的开源子模块。 - -### 运行仿真 - -* 安装开源 verilog 仿真器 [Verilator](https://verilator.org/guide/latest/)。 -* 运行 `make emu` 以利用 Verilator 构建 C++ 仿真器 `./build/emu`。 -* 运行 `./build/emu --help` 可以获得仿真器的各种运行时参数。 -* 更多细节详见 `Makefile` 与 `verilator.mk`。 - -运行示例： - -```bash -make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10 -./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so -``` - -## 致谢 - -在香山的开发过程中，我们采用了来自开源社区的子模块。具体情况如下： - -| 子模块 | 来源 | 详细用途 | -| ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ | -| L2 Cache/LLC | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | 我们增强了原模块的功能和时序，最终使之能胜任 L2/LLC 任务的缓存生成器 | -| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | 我们复用了来自 rocket-chip 的外接框架和链接，来调度总线 | -| FPU | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | 我们使用了 Barkeley-hardfloat 作为浮点运算器并为之设计了 SRT-4 除法/开方运算单元。此外我们分割了 FMA 流水线以优化时序 | - -我们深深地感谢来自开源社区的支持，我们也鼓励其他开源项目在[木兰宽松许可证](LICENSE)的范围下复用我们的代码。:) +# 香山 + +香山是一款开源的高性能 RISC-V 处理器。采用 Chisel 硬件设计语言开发，支持 RV64GC 指令集。 + +详细文档将在未来放出。 +English Readme is [here](README.md). + +©2020-2021 中国科学院计算技术研究所版权所有。 + +## 文档和报告 + +在 2021 年 6 月的 RISC-V 中国峰会上，我们给出了超过 20 个技术报告。报告已经更新到[我们的文档仓库](https://github.com/OpenXiangShan/XiangShan-doc)。 + +更多的文档也将持续更新到相同的仓库。 + +## 关注我们 + +Wechat/微信：香山开源处理器 + +
+ +Zhihu/知乎：[香山开源处理器](https://www.zhihu.com/people/openxiangshan) + +Weibo/微博：[香山开源处理器](https://weibo.com/u/7706264932) + +可以通过[我们的邮件列表](mailto:xiangshan-all@ict.ac.cn)联系我们。列表中的所有邮件会存档到[这里](https://www.mail-archive.com/xiangshan-all@ict.ac.cn/)。 + +## 处理器架构 + +自 2020 年 6 月开始开发的[雁栖湖](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu)为香山处理器的首个稳定的微架构。目前版本的香山（即南湖）正在 master 分支上不断开发中。 + +微架构概览： +![xs-arch-single](images/xs-arch-simple.svg) + +## 目录概览 + +以下是一些关键目录： + +``` +. +├── fpga # 支持的 FPGA 开发板、用于构建 Vivado 项目的文件 +├── read-to-run # 预建的仿真镜像文件 +├── scripts # 用于敏捷开发的脚本文件 +└── src + ├── test # 测试文件（包括差异测试（diff-test）和模块测试（module-test） 等） + └── main/scala # 设计文件 + ├── bus/tilelink # tilelink 实用工具 + ├── device # 用于仿真的虚拟设备 + ├── difftest # chisel 差异测试接口 + ├── system # SoC 封装 + ├── top # 顶层模块 + ├── utils # 复用封装 + ├── xiangshan # 主体设计代码 + └── xstransforms # 一些实用的 firrtl 变换代码 +``` + +## 生成 Verilog + +* 运行 `make verilog` 以生成 verilog 代码。输出文件为 `build/XSTop.v`。 +* 更多信息详见 `Makefile`。 + +## 仿真运行 + +### 环境搭建 + +* 设定环境变量 `NEMU_HOME` 为[香山 NEMU](https://github.com/OpenXiangShan/NEMU) 在您机器上的绝对路径。 +* 设定环境变量 `NOOP_HOME` 为香山工程文件夹的绝对路径。 +* 设定环境变量 `AM_HOME` 为[香山 AM](https://github.com/OpenXiangShan/nexus-am) 的绝对路径。 +* 项目使用 `mill` 进行 scala 编译，因此需要安装 `mill`，详见 [mill 手动安装指南](https://com-lihaoyi.github.io/mill/mill/Intro_to_Mill.html#_installation)（目前仅英文版本）。 +* 克隆本项目，运行 `make init` 以初始化本项目引用的开源子模块。 + +### 运行仿真 + +* 安装开源 verilog 仿真器 [Verilator](https://verilator.org/guide/latest/)。 +* 运行 `make emu` 以利用 Verilator 构建 C++ 仿真器 `./build/emu`。 +* 运行 `./build/emu --help` 可以获得仿真器的各种运行时参数。 +* 更多细节详见 `Makefile` 与 `verilator.mk`。 + +运行示例： + +```bash +make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10 +./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so +``` + +## 致谢 + +在香山的开发过程中，我们采用了来自开源社区的子模块。具体情况如下： + +| 子模块 | 来源 | 详细用途 | +| ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ | +| L2 Cache/LLC | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | 我们增强了原模块的功能和时序，最终使之能胜任 L2/LLC 任务的缓存生成器 | +| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | 我们复用了来自 rocket-chip 的外接框架和链接，来调度总线 | +| FPU | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | 我们使用了 Barkeley-hardfloat 作为浮点运算器并为之设计了 SRT-4 除法/开方运算单元。此外我们分割了 FMA 流水线以优化时序 | + +我们深深地感谢来自开源社区的支持，我们也鼓励其他开源项目在[木兰宽松许可证](LICENSE)的范围下复用我们的代码。:) diff --git a/scripts/xiangshan.py b/scripts/xiangshan.py index 6527c3e5d..856a7d68e 100644 --- a/scripts/xiangshan.py +++ b/scripts/xiangshan.py @@ -48,11 +48,12 @@ class XSArgs(object): for (arg_in, env, default, set_func) in all_path: set_func(self.__extract_path(arg_in, env, default)) # Chisel arguments - self.disable_log = args.disable_log + self.enable_log = args.enable_log self.num_cores = args.num_cores # Makefile arguments self.threads = args.threads self.with_dramsim3 = 1 if args.with_dramsim3 else None + self.is_release = 1 if args.release else None self.trace = 1 if args.trace or not args.disable_fork else None self.config = args.config # emu arguments @@ -79,7 +80,7 @@ class XSArgs(object): def get_chisel_args(self, prefix=None): chisel_args = [ - (self.disable_log, "disable-log") + (self.enable_log, "enable-log") ] args = map(lambda x: x[1], filter(lambda arg: arg[0], chisel_args)) if prefix is not None: @@ -90,6 +91,7 @@ class XSArgs(object): makefile_args = [ (self.threads, "EMU_THREADS"), (self.with_dramsim3, "WITH_DRAMSIM3"), + (self.is_release, "RELEASE"), (self.trace, "EMU_TRACE"), (self.config, "CONFIG"), (self.num_cores, "NUM_CORES") @@ -300,9 +302,10 @@ if __name__ == "__main__": parser.add_argument('--rvtest', nargs='?', type=str, help='path to riscv-tests') parser.add_argument('--wave-dump', nargs='?', type=str , help='path to dump wave') # chisel arguments - parser.add_argument('--disable-log', action='store_true', help='disable log') + parser.add_argument('--enable-log', action='store_true', help='enable log') parser.add_argument('--num-cores', type=int, help='number of cores') # makefile arguments + parser.add_argument('--release', action='store_true', help='enable release') parser.add_argument('--with-dramsim3', action='store_true', help='enable dramsim3') parser.add_argument('--threads', nargs='?', type=int, help='number of emu threads') parser.add_argument('--trace', action='store_true', help='enable waveform') diff --git a/src/main/scala/top/ArgParser.scala b/src/main/scala/top/ArgParser.scala index 24ec4bee3..3002641d5 100644 --- a/src/main/scala/top/ArgParser.scala +++ b/src/main/scala/top/ArgParser.scala @@ -31,9 +31,10 @@ object ArgParser { |--xs-help print this help message |--config |--num-cores - |--dual-core same as '--num-cores 2' |--with-dramsim3 - |--disable-log + |--fpga-platform + |--enable-difftest + |--enable-log |--disable-perf |""".stripMargin @@ -45,7 +46,7 @@ object ArgParser { val c = Class.forName(prefix + confString).getConstructor(Integer.TYPE) c.newInstance(1.asInstanceOf[Object]).asInstanceOf[Parameters] } - def parse(args: Array[String], fpga: Boolean = true): (Parameters, Array[String]) = { + def parse(args: Array[String]): (Parameters, Array[String]) = { val default = new DefaultConfig(1) var firrtlOpts = Array[String]() @tailrec @@ -64,15 +65,21 @@ object ArgParser { up(XSTileKey).head.copy(HartId = i) } }), tail) - case "--dual-core" :: tail => - nextOption(config, "--num-cores" :: "2" :: tail) case "--with-dramsim3" :: tail => nextOption(config.alter((site, here, up) => { case DebugOptionsKey => up(DebugOptionsKey).copy(UseDRAMSim = true) }), tail) - case "--disable-log" :: tail => + case "--fpga-platform" :: tail => nextOption(config.alter((site, here, up) => { - case DebugOptionsKey => up(DebugOptionsKey).copy(EnableDebug = false) + case DebugOptionsKey => up(DebugOptionsKey).copy(FPGAPlatform = true) + }), tail) + case "--enable-difftest" :: tail => + nextOption(config.alter((site, here, up) => { + case DebugOptionsKey => up(DebugOptionsKey).copy(EnableDifftest = true) + }), tail) + case "--enable-log" :: tail => + nextOption(config.alter((site, here, up) => { + case DebugOptionsKey => up(DebugOptionsKey).copy(EnableDebug = true) }), tail) case "--disable-perf" :: tail => nextOption(config.alter((site, here, up) => { @@ -85,11 +92,6 @@ object ArgParser { } } var config = nextOption(default, args.toList) - if(!fpga){ - config = config.alter((site, here, up) => { - case DebugOptionsKey => up(DebugOptionsKey).copy(FPGAPlatform = false) - }) - } (config, firrtlOpts) } } diff --git a/src/main/scala/utils/LogUtils.scala b/src/main/scala/utils/LogUtils.scala index 5329b0bfa..c216e176d 100644 --- a/src/main/scala/utils/LogUtils.scala +++ b/src/main/scala/utils/LogUtils.scala @@ -43,7 +43,7 @@ object XSLog { val logTimestamp = WireInit(0.U(64.W)) val enableDebug = debugOpts.EnableDebug && debugLevel != XSLogLevel.PERF val enablePerf = debugOpts.EnablePerfDebug && debugLevel == XSLogLevel.PERF - if (enableDebug || enablePerf || debugLevel == XSLogLevel.ERROR) { + if (!debugOpts.FPGAPlatform && (enableDebug || enablePerf || debugLevel == XSLogLevel.ERROR)) { ExcitingUtils.addSink(logEnable, "DISPLAY_LOG_ENABLE") ExcitingUtils.addSink(logTimestamp, "logTimestamp") val check_cond = (if (debugLevel == XSLogLevel.ERROR) true.B else logEnable) && cond @@ -58,9 +58,10 @@ object XSLog { } def displayLog(implicit p: Parameters): Bool = { - val logEnable = WireInit(false.B) + val debugOpts = p(DebugOptionsKey) val ret = WireInit(false.B) - if(p(DebugOptionsKey).EnableDebug) { + if (!debugOpts.FPGAPlatform && debugOpts.EnableDebug) { + val logEnable = WireInit(false.B) ExcitingUtils.addSink(logEnable, "DISPLAY_LOG_ENABLE") ret := logEnable } diff --git a/src/main/scala/xiangshan/Parameters.scala b/src/main/scala/xiangshan/Parameters.scala index e8f613b6e..6c2baff4d 100644 --- a/src/main/scala/xiangshan/Parameters.scala +++ b/src/main/scala/xiangshan/Parameters.scala @@ -226,8 +226,9 @@ case object DebugOptionsKey extends Field[DebugOptions] case class DebugOptions ( - FPGAPlatform: Boolean = true, - EnableDebug: Boolean = true, + FPGAPlatform: Boolean = false, + EnableDifftest: Boolean = false, + EnableDebug: Boolean = false, EnablePerfDebug: Boolean = true, UseDRAMSim: Boolean = false ) diff --git a/src/main/scala/xiangshan/XSCore.scala b/src/main/scala/xiangshan/XSCore.scala index bbfd33bd1..921d6c60c 100644 --- a/src/main/scala/xiangshan/XSCore.scala +++ b/src/main/scala/xiangshan/XSCore.scala @@ -52,14 +52,6 @@ trait NeedImpl { abstract class XSBundle(implicit val p: Parameters) extends Bundle with HasXSParameter -case class EnviromentParameters -( - FPGAPlatform: Boolean = true, - EnableDebug: Boolean = false, - EnablePerfDebug: Boolean = true, - DualCore: Boolean = false -) - abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule with HasXSParameter with HasExuWbMappingHelper { diff --git a/src/main/scala/xiangshan/backend/Scheduler.scala b/src/main/scala/xiangshan/backend/Scheduler.scala index 634ee7bc0..0b0b6d475 100644 --- a/src/main/scala/xiangshan/backend/Scheduler.scala +++ b/src/main/scala/xiangshan/backend/Scheduler.scala @@ -448,13 +448,13 @@ class SchedulerImp(outer: Scheduler) extends LazyModuleImp(outer) with HasXSPara } } - if (!env.FPGAPlatform && intRfConfig._1) { + if (env.EnableDifftest && intRfConfig._1) { val difftest = Module(new DifftestArchIntRegState) difftest.io.clock := clock difftest.io.coreid := hardId.U difftest.io.gpr := intRfReadData.takeRight(32) } - if (!env.FPGAPlatform && fpRfConfig._1) { + if (env.EnableDifftest && fpRfConfig._1) { val difftest = Module(new DifftestArchFpRegState) difftest.io.clock := clock difftest.io.coreid := hardId.U diff --git a/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala b/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala index 4ef3e6b6c..ea273c082 100644 --- a/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala +++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala @@ -156,7 +156,7 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasExceptionNO { // update singleStep updatedUop(i).ctrl.singleStep := io.singleStep && (if (i == 0) singleStepStatus else true.B) - if (!env.FPGAPlatform) { + if (env.EnableDifftest) { // debug runahead hint val debug_runahead_checkpoint_id = Wire(checkpoint_id.cloneType) if(i == 0){ diff --git a/src/main/scala/xiangshan/backend/fu/CSR.scala b/src/main/scala/xiangshan/backend/fu/CSR.scala index 61664fe47..26c024492 100644 --- a/src/main/scala/xiangshan/backend/fu/CSR.scala +++ b/src/main/scala/xiangshan/backend/fu/CSR.scala @@ -517,18 +517,6 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP // Hart Priviledge Mode val priviledgeMode = RegInit(UInt(2.W), ModeM) - // Emu perfcnt - val hasEmuPerfCnt = !env.FPGAPlatform - val nrEmuPerfCnts = if (hasEmuPerfCnt) 0x80 else 0x3 - - val emuPerfCnts = List.fill(nrEmuPerfCnts)(RegInit(0.U(XLEN.W))) - val emuPerfCntCond = List.fill(nrEmuPerfCnts)(WireInit(false.B)) - (emuPerfCnts zip emuPerfCntCond).map { case (c, e) => when (e) { c := c + 1.U } } - - val emuPerfCntsLoMapping = (0 until nrEmuPerfCnts).map(i => MaskedRegMap(0x1000 + i, emuPerfCnts(i))) - val emuPerfCntsHiMapping = (0 until nrEmuPerfCnts).map(i => MaskedRegMap(0x1080 + i, emuPerfCnts(i)(63, 32))) - println(s"CSR: hasEmuPerfCnt:${hasEmuPerfCnt}") - //val perfEventscounten = List.fill(nrPerfCnts)(RegInit(false(Bool()))) // Perf Counter val nrPerfCnts = 29 // 3...31 @@ -746,8 +734,6 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP perfCntMapping ++ pmpMapping ++ pmaMapping ++ - emuPerfCntsLoMapping ++ - (if (XLEN == 32) emuPerfCntsHiMapping else Nil) ++ (if (HasFPU) fcsrMapping else Nil) ++ (if (HasCustomCSRCacheOp) cacheopMapping else Nil) @@ -1094,7 +1080,7 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP val difftestIntrNO = Mux(raiseIntr, causeNO, 0.U) - if (!env.FPGAPlatform) { + if (env.EnableDifftest) { val difftest = Module(new DifftestArchEvent) difftest.io.clock := clock difftest.io.coreid := hardId.U @@ -1103,7 +1089,7 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP difftest.io.exceptionPC := RegNext(SignExt(csrio.exception.bits.uop.cf.pc, XLEN)) } - if (!env.FPGAPlatform) { + if (env.EnableDifftest) { val difftest = Module(new DifftestCSRState) difftest.io.clock := clock difftest.io.coreid := hardId.U @@ -1127,6 +1113,7 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP difftest.io.medeleg := medeleg } } + class PFEvent(implicit p: Parameters) extends XSModule with HasCSRConst { val io = IO(new Bundle { val distribute_csr = Flipped(new DistributedCSRIO()) diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala index cae5a30a3..5d6907eda 100644 --- a/src/main/scala/xiangshan/backend/rob/Rob.scala +++ b/src/main/scala/xiangshan/backend/rob/Rob.scala @@ -547,7 +547,7 @@ class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCirc io.commits.info(i).ldest ) } - if (!env.FPGAPlatform) { + if (env.EnableDifftest) { io.commits.info.map(info => dontTouch(info.pc)) } @@ -905,11 +905,6 @@ class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCirc XSPerfAccumulate(s"${fuName}_latency_execute_fma", ifCommit(latencySum(commitIsFma, executeLatency))) } } - val l1Miss = Wire(Bool()) - l1Miss := false.B - ExcitingUtils.addSink(l1Miss, "TMA_l1miss") - XSPerfAccumulate("TMA_L1miss", deqNotWritebacked && deqUopCommitType === CommitType.LOAD && l1Miss) - //difftest signals val firstValidCommit = (deqPtr + PriorityMux(io.commits.valid, VecInit(List.tabulate(CommitWidth)(_.U)))).value @@ -931,7 +926,7 @@ class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCirc val trapCode = PriorityMux(wdata.zip(trapVec).map(x => x._2 -> x._1)) val trapPC = SignExt(PriorityMux(wpc.zip(trapVec).map(x => x._2 ->x._1)), XLEN) - if (!env.FPGAPlatform) { + if (env.EnableDifftest) { for (i <- 0 until CommitWidth) { val difftest = Module(new DifftestInstrCommit) difftest.io.clock := clock @@ -957,8 +952,6 @@ class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCirc difftest.io.wdata := RegNext(exuData) difftest.io.wdest := RegNext(uop.ctrl.ldest) - // XSDebug(p"[difftest-instr-commit]valid:${difftest.io.valid},pc:${difftest.io.pc},instr:${difftest.io.instr},skip:${difftest.io.skip},isRVC:${difftest.io.isRVC},scFailed:${difftest.io.scFailed},wen:${difftest.io.wen},wdata:${difftest.io.wdata},wdest:${difftest.io.wdest}\n") - // runahead commit hint val runahead_commit = Module(new DifftestRunaheadCommitEvent) runahead_commit.io.clock := clock @@ -971,7 +964,7 @@ class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCirc } } - if (!env.FPGAPlatform) { + if (env.EnableDifftest) { for (i <- 0 until CommitWidth) { val difftest = Module(new DifftestLoadEvent) difftest.io.clock := clock @@ -988,7 +981,7 @@ class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCirc } } - if (!env.FPGAPlatform) { + if (env.EnableDifftest) { val difftest = Module(new DifftestTrapEvent) difftest.io.clock := clock difftest.io.coreid := hardId.U @@ -998,6 +991,7 @@ class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCirc difftest.io.cycleCnt := timer difftest.io.instrCnt := instrCnt } + val perfinfo = IO(new Bundle(){ val perfEvents = Output(new PerfEventsBundle(18)) }) diff --git a/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala b/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala index a6f1cccb2..e6dfd8f11 100644 --- a/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala +++ b/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala @@ -518,7 +518,7 @@ class MissQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule { io.full := ~Cat(entries.map(_.io.primary_ready)).andR - if (!env.FPGAPlatform) { + if (env.EnableDifftest) { val difftest = Module(new DifftestRefillEvent) difftest.io.clock := clock difftest.io.coreid := hardId.U diff --git a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala index 31a3e6bbb..b0ecf0f38 100644 --- a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala +++ b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala @@ -556,7 +556,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule with HasDCacheParamete } } - if (!env.FPGAPlatform) { + if (env.EnableDifftest) { for (i <- 0 until StorePipelineWidth) { val storeCommit = io.sbuffer(i).fire() val waddr = SignExt(io.sbuffer(i).bits.addr, 64) diff --git a/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala b/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala index 4c4d7df99..a91dc89f8 100644 --- a/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala +++ b/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala @@ -290,7 +290,7 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstant atom_override_xtval := false.B } - if (!env.FPGAPlatform) { + if (env.EnableDifftest) { val difftest = Module(new DifftestAtomicEvent) difftest.io.clock := clock difftest.io.coreid := hardId.U diff --git a/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala b/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala index 45b2e1223..dd66b2c18 100644 --- a/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala +++ b/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala @@ -485,7 +485,7 @@ class Sbuffer(implicit p: Parameters) extends DCacheModule with HasSbufferConst // val num_valids = PopCount(entries.map(e => !e.io.lsu.req.ready)) // XSPerfHistogram("num_valids", num_valids, true.B, 0, cfg.nStoreReplayEntries, 1) - if (!env.FPGAPlatform) { + if (env.EnableDifftest) { // hit resp io.dcache.hit_resps.zipWithIndex.map{case (resp, index) => { val difftest = Module(new DifftestSbufferEvent) diff --git a/src/test/scala/top/SimTop.scala b/src/test/scala/top/SimTop.scala index 7d45ddb92..756b5d83a 100644 --- a/src/test/scala/top/SimTop.scala +++ b/src/test/scala/top/SimTop.scala @@ -74,14 +74,14 @@ class SimTop(implicit p: Parameters) extends Module { io.memAXI <> soc.memory } - if (debugOpts.EnableDebug || debugOpts.EnablePerfDebug) { + if (!debugOpts.FPGAPlatform && (debugOpts.EnableDebug || debugOpts.EnablePerfDebug)) { val timer = GTimer() val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end) ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE") ExcitingUtils.addSource(timer, "logTimestamp") } - if (debugOpts.EnablePerfDebug) { + if (!debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug) { val clean = io.perfInfo.clean val dump = io.perfInfo.dump ExcitingUtils.addSource(clean, "XSPERF_CLEAN") @@ -94,15 +94,13 @@ class SimTop(implicit p: Parameters) extends Module { } object SimTop extends App { - override def main(args: Array[String]): Unit = { - val (config, firrtlOpts) = ArgParser.parse(args, fpga = false) - // generate verilog - XiangShanStage.execute( - firrtlOpts, - Seq( - ChiselGeneratorAnnotation(() => DisableMonitors(p => new SimTop()(p))(config)) - ) - ) + // Keep this the same as TopMain except that SimTop is used here instead of XSTop + val (config, firrtlOpts) = ArgParser.parse(args) + XiangShanStage.execute(firrtlOpts, Seq( + ChiselGeneratorAnnotation(() => { + DisableMonitors(p => new SimTop()(p))(config) + }) + )) } } -- GitLab