diff --git a/src/main/scala/xiangshan/backend/Backend.scala b/src/main/scala/xiangshan/backend/Backend.scala index 23c97a35f623eadc25ea92c3cede0840f997080c..3ee3b5e4ed6d72dcb02aea908052ce49b59992eb 100644 --- a/src/main/scala/xiangshan/backend/Backend.scala +++ b/src/main/scala/xiangshan/backend/Backend.scala @@ -125,8 +125,8 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) private val vconfig = dataPath.io.vconfigReadPort.data - private val og1CancelVec: Vec[Bool] = VecInit(dataPath.io.toIQCancelVec.map(_("OG1"))) - private val og0CancelVecFromDataPath: Vec[Bool] = VecInit(dataPath.io.toIQCancelVec.map(_("OG0"))) + private val og1CancelVec: Vec[Bool] = dataPath.io.og1CancelVec + private val og0CancelVecFromDataPath: Vec[Bool] = dataPath.io.og0CancelVec private val og0CancelVecFromCancelNet: Vec[Bool] = cancelNetwork.io.out.og0CancelVec private val og0CancelVec: Vec[Bool] = VecInit(og0CancelVecFromDataPath.zip(og0CancelVecFromCancelNet).map(x => x._1 | x._2)) dontTouch(og0CancelVecFromDataPath) diff --git a/src/main/scala/xiangshan/backend/Bundles.scala b/src/main/scala/xiangshan/backend/Bundles.scala index 5011f432e07e8946c671816fd1fd73ad04f729bd..dc8bec3dc5eadf5a1e76958d4f16307b708653c0 100644 --- a/src/main/scala/xiangshan/backend/Bundles.scala +++ b/src/main/scala/xiangshan/backend/Bundles.scala @@ -270,18 +270,6 @@ object Bundles { } } - /** - * This bundle is used to set srcState as NotReady. - * @param cancelSeq cancel stage seq - */ - class IssueQueueCancelBundle(val exuIdx: Int, cancelSeq: Seq[String]) extends Bundle { - val cancelVec: Vec[Bool] = Vec(cancelSeq.size, Bool()) - - def apply(cancelStage: String): Bool = { - this.cancelVec(cancelSeq.indexOf(cancelStage.toUpperCase)) - } - } - class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { // vtype val vill = Bool() diff --git a/src/main/scala/xiangshan/backend/datapath/DataPath.scala b/src/main/scala/xiangshan/backend/datapath/DataPath.scala index da3ace09a65d070eb0982f2f34ca740c89efc083..5378ab07a8a8b5eeffcfd1d073309edbd1e08076 100644 --- a/src/main/scala/xiangshan/backend/datapath/DataPath.scala +++ b/src/main/scala/xiangshan/backend/datapath/DataPath.scala @@ -159,13 +159,15 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params private val fromExus = fromIntExus ++ fromVfExus + private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten + + private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten + private val intWbBusyArbiter = Module(new WbBusyArbiter(true)) private val vfWbBusyArbiter = Module(new WbBusyArbiter(false)) private val intRFReadArbiter = Module(new RFReadArbiter(true)) private val vfRFReadArbiter = Module(new RFReadArbiter(false)) - private val og0FailedVec: Vec[Bool] = Wire(Vec(backendParams.numExu, Bool())) - private val og1FailedVec: Vec[Bool] = Wire(Vec(backendParams.numExu, Bool())) private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())))) private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())))) @@ -491,12 +493,9 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params } } - io.toIQCancelVec.zipWithIndex.foreach { case (cancelBundle: IssueQueueCancelBundle, i) => - og0FailedVec(i) := (fromIQ.flatten.find(_.bits.exuIdx == cancelBundle.exuIdx).get match { case x => x.valid && !x.fire }) - og1FailedVec(i) := (toExu.flatten.find(_.bits.exuIdx == cancelBundle.exuIdx).get match { case x => x.valid && !x.fire }) - cancelBundle("OG0") := og0FailedVec(i) - cancelBundle("OG1") := og1FailedVec(i) - cancelBundle("IS") := false.B + io.og0CancelVec.zip(io.og1CancelVec).zipWithIndex.foreach { case ((og0Cancel, og1Cancel), i) => + og0Cancel := fromFlattenIQ(i).valid && !fromFlattenIQ(i).fire + og1Cancel := toFlattenExu(i).valid && !toFlattenExu(i).fire } for (i <- toExu.indices) { @@ -595,7 +594,9 @@ class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBund val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) - val toIQCancelVec = Output(MixedVec(exuParams.map(x => new IssueQueueCancelBundle(x.exuIdx, cancelStages)))) + val og0CancelVec = Output(ExuVec(backendParams.numExu)) + + val og1CancelVec = Output(ExuVec(backendParams.numExu)) val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle diff --git a/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala b/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala index 2e03bd4c59aded569dd3c8fd90c2d0c3fc2aac71..254bcd7cb5cb728521bec8f5bbdc73c5149b21bb 100644 --- a/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala +++ b/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala @@ -242,10 +242,6 @@ case class IssueBlockParams( MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) } - def genCancelBundle(cancelStages: Seq[String]): MixedVec[IssueQueueCancelBundle] = { - MixedVec(backendParam.allExuParams.map(x => new IssueQueueCancelBundle(x.exuIdx, cancelStages))) - } - def genOGRespBundle(implicit p: Parameters) = { implicit val issueBlockParams = this MixedVec(exuBlockParams.map(_ => new OGRespBundle)) diff --git a/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala b/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala index 2503381fe9c3f718b7eeb234aef752660e579630..b9f90970c2e1ca13c0ed4cd57d4f550f1c16c034 100644 --- a/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala +++ b/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala @@ -4,7 +4,7 @@ import chipsalliance.rocketchip.config.Parameters import chisel3.util._ import utils.SeqUtils import xiangshan.backend.BackendParams -import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput, IssueQueueCancelBundle, IssueQueueIQWakeUpBundle, IssueQueueWBWakeUpBundle} +import xiangshan.backend.Bundles._ import xiangshan.backend.datapath.WakeUpSource import xiangshan.backend.datapath.WbConfig.WbConfig @@ -149,10 +149,6 @@ case class SchdBlockParams( MixedVec(this.wakeUpOutExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) } - def genCancelBundle(cancelStages: Seq[String]): MixedVec[IssueQueueCancelBundle] = { - MixedVec(backendParam.allExuParams.map(x => new IssueQueueCancelBundle(x.exuIdx, cancelStages))) - } - def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq diff --git a/src/main/scala/xiangshan/backend/issue/Scheduler.scala b/src/main/scala/xiangshan/backend/issue/Scheduler.scala index 1e74902deaeb0896e6668951d0d127b55ccf03c9..2e0f3d8848e71bfa398e2c13ba39eb1e812a83c2 100644 --- a/src/main/scala/xiangshan/backend/issue/Scheduler.scala +++ b/src/main/scala/xiangshan/backend/issue/Scheduler.scala @@ -5,12 +5,11 @@ import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} import xiangshan._ -import xiangshan.backend.Bundles +import xiangshan.backend.Bundles._ import xiangshan.backend.datapath.DataConfig.VAddrData import xiangshan.backend.regfile.RfWritePortWithConfig import xiangshan.backend.rename.BusyTable import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} -import xiangshan.backend.Bundles.{DynInst, ExuVec, IssueQueueCancelBundle, IssueQueueIQWakeUpBundle, IssueQueueWBWakeUpBundle} sealed trait SchedulerType @@ -64,7 +63,7 @@ class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends Bun new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) val vfWriteBack = MixedVec(Vec(backendParams.vfPregParams.numWrite, new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) - val toDataPath: MixedVec[MixedVec[DecoupledIO[Bundles.IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) + val toDataPath: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) val fromSchedulers = new Bundle { val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) @@ -75,7 +74,7 @@ class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends Bun } val fromDataPath = new Bundle { - val resp: MixedVec[MixedVec[Bundles.OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) + val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) val og0Cancel = Input(ExuVec(backendParams.numExu)) // Todo: remove this after no cancel signal from og1 val og1Cancel = Input(ExuVec(backendParams.numExu))