diff --git a/src/main/scala/xiangshan/backend/FloatBlock.scala b/src/main/scala/xiangshan/backend/FloatBlock.scala
index c972f5b72b722458b08c08bf94eb4e156d5944d2..fad104f2514302b004694278163d5dfbbc85cd37 100644
--- a/src/main/scala/xiangshan/backend/FloatBlock.scala
+++ b/src/main/scala/xiangshan/backend/FloatBlock.scala
@@ -58,6 +58,7 @@ class FloatBlock
   def needData(a: ExuConfig, b: ExuConfig): Boolean =
     (a.readIntRf && b.writeIntRf) || (a.readFpRf && b.writeFpRf)
 
+  val readPortIndex = RegNext(io.fromCtrlBlock.readPortIndex)
   val reservedStations = exeUnits.map(_.config).zipWithIndex.map({ case (cfg, i) =>
     var certainLatency = -1
     if (cfg.hasCertainLatency) {
@@ -86,10 +87,11 @@ class FloatBlock
     rsCtrl.io.redirect <> redirect // TODO: remove it
     rsCtrl.io.numExist <> io.toCtrlBlock.numExist(i)
     rsCtrl.io.enqCtrl <> io.fromCtrlBlock.enqIqCtrl(i)
-    rsData.io.readPortIndex := io.fromCtrlBlock.readPortIndex(i)
-    rsData.io.readFpRf.zipWithIndex.foreach({
-      case (port, i) => port.data := fpRf.io.readPorts(i).data
-    })
+
+    rsData.io.srcRegValue := DontCare
+    rsData.io.srcRegValue(0) := fpRf.io.readPorts(readPortIndex(i)).data
+    rsData.io.srcRegValue(1) := fpRf.io.readPorts(readPortIndex(i) + 1.U).data
+    rsData.io.srcRegValue(2) := fpRf.io.readPorts(readPortIndex(i) + 2.U).data
     rsData.io.enqData <> io.fromCtrlBlock.enqIqData(i)
     rsData.io.redirect <> redirect
 
diff --git a/src/main/scala/xiangshan/backend/IntegerBlock.scala b/src/main/scala/xiangshan/backend/IntegerBlock.scala
index 53727bacf5d44d20316114ab6e909843025fb032..88abdd34a0a50eccf0c84431ea178c9204cdd8a7 100644
--- a/src/main/scala/xiangshan/backend/IntegerBlock.scala
+++ b/src/main/scala/xiangshan/backend/IntegerBlock.scala
@@ -112,6 +112,7 @@ class IntegerBlock
   def needData(a: ExuConfig, b: ExuConfig): Boolean =
     (a.readIntRf && b.writeIntRf) || (a.readFpRf && b.writeFpRf)
 
+  val readPortIndex = RegNext(io.fromCtrlBlock.readPortIndex)
   val reservationStations = exeUnits.map(_.config).zipWithIndex.map({ case (cfg, i) =>
     var certainLatency = -1
     if (cfg.hasCertainLatency) {
@@ -142,10 +143,10 @@ class IntegerBlock
     rsCtrl.io.redirect <> redirect // TODO: remove it
     rsCtrl.io.numExist <> io.toCtrlBlock.numExist(i)
     rsCtrl.io.enqCtrl <> io.fromCtrlBlock.enqIqCtrl(i)
-    rsData.io.readPortIndex := io.fromCtrlBlock.readPortIndex(i)
-    rsData.io.readIntRf.zipWithIndex.foreach({
-      case (port, i) => port.data := intRf.io.readPorts(i).data
-    })
+
+    rsData.io.srcRegValue := DontCare
+    rsData.io.srcRegValue(0) := intRf.io.readPorts(readPortIndex(i)).data
+    rsData.io.srcRegValue(1) := intRf.io.readPorts(readPortIndex(i) + 1.U).data
     rsData.io.enqData <> io.fromCtrlBlock.enqIqData(i)
     rsData.io.redirect <> redirect
 
diff --git a/src/main/scala/xiangshan/backend/MemBlock.scala b/src/main/scala/xiangshan/backend/MemBlock.scala
index 95231e6900870bbb6ebd0e33167849883467432f..7ab5f09896ea101face289fb1c20a1a8b4a09d63 100644
--- a/src/main/scala/xiangshan/backend/MemBlock.scala
+++ b/src/main/scala/xiangshan/backend/MemBlock.scala
@@ -10,7 +10,6 @@ import xiangshan.cache._
 import xiangshan.mem._
 import xiangshan.backend.fu.FenceToSbuffer
 import xiangshan.backend.issue.{ReservationStationCtrl, ReservationStationData}
-import xiangshan.backend.fu.FunctionUnit.{lduCfg, mouCfg, stuCfg}
 import xiangshan.backend.regfile.RfReadPort
 
 class LsBlockToCtrlIO extends XSBundle {
@@ -87,6 +86,8 @@ class MemBlock
   val exeWbReqs = ldOut0 +: loadUnits.tail.map(_.io.ldout)
 
   val readPortIndex = Seq(0, 1, 2, 4)
+  io.fromIntBlock.readIntRf.foreach(_.addr := DontCare)
+  io.fromFpBlock.readFpRf.foreach(_.addr := DontCare)
   val reservationStations = (loadExuConfigs ++ storeExuConfigs).zipWithIndex.map({ case (cfg, i) =>
     var certainLatency = -1
     if (cfg.hasCertainLatency) {
@@ -122,9 +123,13 @@ class MemBlock
     rsCtrl.io.redirect <> redirect // TODO: remove it
     rsCtrl.io.numExist <> io.toCtrlBlock.numExist(i)
     rsCtrl.io.enqCtrl <> io.fromCtrlBlock.enqIqCtrl(i)
-    rsData.io.readPortIndex := readPortIndex(i).U
-    rsData.io.readIntRf <> io.fromIntBlock.readIntRf
-    rsData.io.readFpRf <> io.fromFpBlock.readFpRf
+
+    val src2IsFp = RegNext(io.fromCtrlBlock.enqIqCtrl(i).bits.ctrl.src2Type === SrcType.fp)
+    rsData.io.srcRegValue := DontCare
+    rsData.io.srcRegValue(0) := io.fromIntBlock.readIntRf(readPortIndex(i)).data
+    if (i >= exuParameters.LduCnt) {
+      rsData.io.srcRegValue(1) := Mux(src2IsFp, io.fromFpBlock.readFpRf(i - exuParameters.LduCnt).data, io.fromIntBlock.readIntRf(readPortIndex(i) + 1).data)
+    }
     rsData.io.enqData <> io.fromCtrlBlock.enqIqData(i)
     rsData.io.redirect <> redirect
 
diff --git a/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala b/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala
index 62b9add812920f168f196b388ff1157a57a9063a..cdb4446228cbfe4365de77dca18cce602c3a35b4 100644
--- a/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala
+++ b/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala
@@ -339,23 +339,7 @@ class ReservationStationData
     val ctrl = Flipped(new RSCtrlDataIO)
 
     // read src op value
-    // TODO: define index width as parameters
-    val readPortIndex: UInt = dispatchType(exuCfg) match {
-      case DispatchType.Disp2Int => Input(UInt(log2Ceil(NRIntReadPorts).W))
-      case DispatchType.Disp2Fp => Input(UInt(log2Ceil(NRFpReadPorts - exuParameters.StuCnt).W))
-      case DispatchType.Disp2Ls => Input(UInt(3.W))
-    }
-
-    val readIntRf: Vec[RfReadPort] = dispatchType(exuCfg) match {
-      case DispatchType.Disp2Fp => null
-      case DispatchType.Disp2Int => Vec(NRIntReadPorts - NRMemReadPorts, Flipped(new RfReadPort))
-      case DispatchType.Disp2Ls => Vec(NRMemReadPorts, Flipped(new RfReadPort))
-    }
-    val readFpRf: Vec[RfReadPort] = dispatchType(exuCfg) match {
-      case DispatchType.Disp2Fp => Vec(NRFpReadPorts - exuParameters.StuCnt, Flipped(new RfReadPort))
-      case DispatchType.Disp2Int => null
-      case DispatchType.Disp2Ls => Vec(exuParameters.StuCnt, Flipped(new RfReadPort))
-    }
+    val srcRegValue = Vec(srcNum, Input(UInt(XLEN.W)))
     // broadcast selected uop to other issue queues
     val selectedUop = ValidIO(new MicroOp)
 
@@ -384,12 +368,6 @@ class ReservationStationData
   val enqCtrl = io.ctrl.enqCtrl
   val enqUop = enqCtrl.bits
 
-  val readIntRf = io.readIntRf
-  if (readIntRf != null) readIntRf.foreach(_.addr := DontCare)
-  val readFpRf = io.readFpRf
-  if (readFpRf != null) readFpRf.foreach(_.addr := DontCare)
-  val readPortIndex = RegNext(io.readPortIndex)
-
   // enq
   val enqPtr = enq(log2Up(IssQueSize)-1,0)
   val enqPtrReg = RegEnable(enqPtr, enqCtrl.valid)
@@ -402,52 +380,55 @@ class ReservationStationData
       p"${enqUop.src3State}|${enqUop.ctrl.src3Type} pc:0x${Hexadecimal(enqUop.cf.pc)} roqIdx:${enqUop.roqIdx}\n")
   }
 
-  val srcOp: Vec[UInt] = Wire(Vec(srcNum, UInt(XLEN.W)))
-  srcOp := DontCare
-
   when (enqEnReg) { // TODO: turn to srcNum, not the 3
     exuCfg match {
       case Exu.aluExeUnitCfg =>
         // src1: pc or reg
-        srcOp(0) := Mux(enqUop.ctrl.src1Type === SrcType.pc, SignExt(enqUop.cf.pc, XLEN), readIntRf(readPortIndex).data)
+        data(enqPtrReg)(0) := Mux(uop(enqPtrReg).ctrl.src1Type === SrcType.pc, SignExt(uop(enqPtrReg).cf.pc, XLEN), io.srcRegValue(0))
         // src2: imm or reg
-        srcOp(1) := Mux(enqUop.ctrl.src2Type === SrcType.imm, enqUop.ctrl.imm, readIntRf(readPortIndex + 1.U).data)
+        data(enqPtrReg)(1) := Mux(uop(enqPtrReg).ctrl.src2Type === SrcType.imm, uop(enqPtrReg).ctrl.imm, io.srcRegValue(1))
 
         XSDebug(p"${exuCfg.name}: enqPtrReg:${enqPtrReg}\n")
-        XSDebug(p"newSrc1: ${Hexadecimal(srcOp(0))} newSrc2: ${Hexadecimal(srcOp(1))}\n")
+        XSDebug(p"newSrc1: ${Hexadecimal(io.srcRegValue(0))} newSrc2: ${Hexadecimal(io.srcRegValue(1))}\n")
         XSDebug(p"src1:${Hexadecimal(io.enqData.src1)} src2:${Hexadecimal(io.enqData.src2)}\n")
 
       case Exu.jumpExeUnitCfg =>
         // src1: pc or reg
-        srcOp(0) := Mux(enqUop.ctrl.src1Type === SrcType.pc, SignExt(enqUop.cf.pc, XLEN), readIntRf(readPortIndex).data)
+        data(enqPtrReg)(0) := Mux(uop(enqPtrReg).ctrl.src1Type === SrcType.pc, SignExt(uop(enqPtrReg).cf.pc, XLEN), io.srcRegValue(0))
         // src2: imm
-        srcOp(1) := enqUop.ctrl.imm
+        data(enqPtrReg)(1) := uop(enqPtrReg).ctrl.imm
 
         XSDebug(p"${exuCfg.name}: enqPtrReg:${enqPtrReg}\n")
-        XSDebug(p"newSrc1: ${Hexadecimal(srcOp(0))} newSrc2: ${Hexadecimal(srcOp(1))}\n")
+        XSDebug(p"newSrc1: ${Hexadecimal(io.srcRegValue(0))} newSrc2: ${Hexadecimal(io.srcRegValue(1))}\n")
         XSDebug(p"src1:${Hexadecimal(io.enqData.src1)} src2:${Hexadecimal(io.enqData.src2)}\n")
 
       case Exu.mulDivExeUnitCfg =>
         // src1: reg
-        srcOp(0) := readIntRf(readPortIndex).data
+        data(enqPtrReg)(0) := io.srcRegValue(0)
         // src2: reg
-        srcOp(1) := readIntRf(readPortIndex + 1.U).data
+        data(enqPtrReg)(1) := io.srcRegValue(1)
 
         XSDebug(p"${exuCfg.name}: enqPtrReg:${enqPtrReg}\n")
-        XSDebug(p"newSrc1: ${Hexadecimal(srcOp(0))} newSrc2: ${Hexadecimal(srcOp(1))}\n")
+        XSDebug(p"newSrc1: ${Hexadecimal(io.srcRegValue(0))} newSrc2: ${Hexadecimal(io.srcRegValue(1))}\n")
         XSDebug(p"src1:${Hexadecimal(io.enqData.src1)} src2:${Hexadecimal(io.enqData.src2)}\n")
 
+      case Exu.fmacExeUnitCfg =>
+        (0 until srcNum).foreach(i => data(enqPtrReg)(i) := io.srcRegValue(i))
+        XSDebug(p"New-src: src1: ${Hexadecimal(io.srcRegValue(0))} src2: ${Hexadecimal(io.srcRegValue(1))} src3: ${Hexadecimal(io.srcRegValue(2))}\n")
+        XSDebug(p"${exuCfg.name}: enqPtrReg:${enqPtrReg} src1:${Hexadecimal(io.enqData.src1)}" +
+          p" src2:${Hexadecimal(io.enqData.src2)} src3:${Hexadecimal(io.enqData.src3)}\n")
+
+      case Exu.fmiscExeUnitCfg =>
+        (0 until srcNum).foreach(i => data(enqPtrReg)(i) := io.srcRegValue(i))
+      case Exu.ldExeUnitCfg =>
+        data(enqPtrReg)(0) := io.srcRegValue(0)
+        data(enqPtrReg)(1) := Mux(uop(enqPtrReg).ctrl.src2Type === SrcType.imm, uop(enqPtrReg).ctrl.imm, io.srcRegValue(1))
+      case Exu.stExeUnitCfg =>
+        data(enqPtrReg)(0) := io.srcRegValue(0)
+        data(enqPtrReg)(1) := Mux(uop(enqPtrReg).ctrl.src2Type === SrcType.imm, uop(enqPtrReg).ctrl.imm, io.srcRegValue(1))
       // default
       case _ =>
-        data(enqPtrReg)(0) := io.enqData.src1
-        data(enqPtrReg)(1) := io.enqData.src2
-        data(enqPtrReg)(2) := io.enqData.src3
-        XSDebug(p"${exuCfg.name}-enqData: enqPtrReg:${enqPtrReg} src1:${Hexadecimal(io.enqData.src1)}" +
-          p" src2:${Hexadecimal(io.enqData.src2)} src3:${Hexadecimal(io.enqData.src3)}\n")
-    }
-    // FIXME: this is temporary for  testing
-    if (dispatchType(exuCfg) == DispatchType.Disp2Int) {
-      (0 until 3).foreach(i => data(enqPtrReg)(i) := srcOp(i))
+        XSDebug(false.B, "Unhandled exu-config")
     }
   }