diff --git a/Makefile b/Makefile
index b727e3ecaf54108911ea0c93093f16282078deaf..0de0dd404cecb41791a65f2c5df71f01415757d9 100644
--- a/Makefile
+++ b/Makefile
@@ -50,7 +50,7 @@ TIME_CMD = time -a -o $(TIMELOG)
 .DEFAULT_GOAL = verilog
 
 help:
-	mill XiangShan.test.runMain $(SIMTOP) --help
+	mill -i XiangShan.test.runMain $(SIMTOP) --help
 
 $(TOP_V): $(SCALA_FILE)
 	mkdir -p $(@D)
@@ -106,6 +106,9 @@ bump:
 bsp:
 	mill -i mill.bsp.BSP/install
 
+idea:
+	mill -i mill.scalalib.GenIdea/idea
+
 # verilator simulation
 emu:
 	$(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
diff --git a/README.md b/README.md
index d9c2a8533201501b3fe821f582b537d6f8c85c90..1a1f7732001e680df89325c1134880003ab00cfa 100644
--- a/README.md
+++ b/README.md
@@ -55,6 +55,17 @@ Some of the key directories are shown below.
         └── xstransforms   # some useful firrtl transforms
 ```
 
+## IDE Support
+
+### bsp
+```
+make bsp
+```
+
+### IDEA
+```
+make idea
+```
 
 
 ## Generate Verilog