diff --git a/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala b/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala
index a0a32b4f6fca651b2e3577b17efa3d59ed7b0630..973d4ed894979fbb1860c9e0238e87a5657eb6f6 100644
--- a/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala
+++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala
@@ -84,8 +84,7 @@ class Dispatch2Ls extends XSModule {
     */
   for (i <- 0 until exuParameters.LsExuCnt) {
     val enq = io.enqIQCtrl(i)
-    // TODO: cache only has 1 load and 1 store
-    enq.valid := (if (i % 2 == 1) false.B else validVec(i))
+    enq.valid := validVec(i)
     enq.bits := io.fromDq(indexVec(i)).bits
     enq.bits.src1State := io.intRegRdy(readPort(i))
     if (i < exuParameters.LduCnt) {
@@ -105,8 +104,7 @@ class Dispatch2Ls extends XSModule {
     * Part 4: response to dispatch queue
     */
   for (i <- 0 until dpParams.LsDqDeqWidth) {
-    // TODO: cache only has 1 load and 1 store
-    io.fromDq(i).ready := rsValidVec(i) && Mux(rsIndexVec(i)(0) === 1.U, false.B, io.enqIQCtrl(rsIndexVec(i)).ready)
+    io.fromDq(i).ready := rsValidVec(i) && io.enqIQCtrl(rsIndexVec(i)).ready
 
     XSInfo(io.fromDq(i).fire(),
       p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} leaves Ls dispatch queue $i with nroq ${io.fromDq(i).bits.roqIdx}\n")
diff --git a/src/main/scala/xiangshan/backend/issue/IssueQueue.scala b/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
index 9efe809c975ff288244473d334963f1bf6580825..f817702117b4e21feb61218503b42e61224ced37 100644
--- a/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
+++ b/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
@@ -277,8 +277,7 @@ class IssueQueue
 
 
   // assign outputs
-  // TODO currently set to zero
-  io.numExist := 0.U//Mux(isFull, (qsize-1).U, tailPtr)
+  io.numExist := Mux(isFull, (qsize-1).U, tailPtr)
 
   // Debug sigs
   XSInfo(