From 09348ee5557de5685bb9da798f779f9b3b88367c Mon Sep 17 00:00:00 2001 From: ljw Date: Thu, 4 Mar 2021 00:11:21 +0800 Subject: [PATCH] Ftq: save 'hist' and br_mask in regs (#629) * Ftq: save 'hist' in regs * Ftq: save 'br_mask' in regs --- src/main/scala/xiangshan/backend/CtrlBlock.scala | 11 +++++++---- src/main/scala/xiangshan/backend/ftq/Ftq.scala | 16 ++++++++-------- 2 files changed, 15 insertions(+), 12 deletions(-) diff --git a/src/main/scala/xiangshan/backend/CtrlBlock.scala b/src/main/scala/xiangshan/backend/CtrlBlock.scala index 45c442fd7..5b8c2d34a 100644 --- a/src/main/scala/xiangshan/backend/CtrlBlock.scala +++ b/src/main/scala/xiangshan/backend/CtrlBlock.scala @@ -170,6 +170,11 @@ class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper with Wai io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx + val s2_br_mask = RegEnable(ftqRead.br_mask, enable = s1_redirect_valid_reg) + val s2_sawNotTakenBranch = RegEnable(VecInit((0 until PredictWidth).map{ i => + if(i == 0) false.B else Cat(ftqRead.br_mask.take(i)).orR() + })(s1_redirect_bits_reg.ftqOffset), enable = s1_redirect_valid_reg) + val s2_hist = RegEnable(ftqRead.hist, enable = s1_redirect_valid_reg) val s2_target = RegEnable(target, enable = s1_redirect_valid_reg) val s2_pd = RegEnable(s1_pd, enable = s1_redirect_valid_reg) val s2_cfiUpdata_pc = RegEnable(cfiUpdate_pc, enable = s1_redirect_valid_reg) @@ -186,11 +191,9 @@ class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper with Wai stage3CfiUpdate.rasEntry := s2_ftqRead.rasTop stage3CfiUpdate.predHist := s2_ftqRead.predHist stage3CfiUpdate.specCnt := s2_ftqRead.specCnt - stage3CfiUpdate.hist := s2_ftqRead.hist + stage3CfiUpdate.hist := s2_hist stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken - stage3CfiUpdate.sawNotTakenBranch := VecInit((0 until PredictWidth).map{ i => - if(i == 0) false.B else Cat(s2_ftqRead.br_mask.take(i)).orR() - })(s2_redirect_bits_reg.ftqOffset) + stage3CfiUpdate.sawNotTakenBranch := s2_sawNotTakenBranch stage3CfiUpdate.target := s2_target stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred diff --git a/src/main/scala/xiangshan/backend/ftq/Ftq.scala b/src/main/scala/xiangshan/backend/ftq/Ftq.scala index a6542d174..44e2ee581 100644 --- a/src/main/scala/xiangshan/backend/ftq/Ftq.scala +++ b/src/main/scala/xiangshan/backend/ftq/Ftq.scala @@ -62,16 +62,16 @@ class FtqNRSRAM[T <: Data](gen: T, numRead: Int) extends XSModule { class Ftq_4R_SRAMEntry extends XSBundle { val ftqPC = UInt(VAddrBits.W) val lastPacketPC = ValidUndirectioned(UInt(VAddrBits.W)) + val hist = new GlobalHistory + val br_mask = Vec(PredictWidth, Bool()) } // redirect and commit need read these infos class Ftq_2R_SRAMEntry extends XSBundle { val rasSp = UInt(log2Ceil(RasSize).W) val rasEntry = new RASEntry - val hist = new GlobalHistory val predHist = new GlobalHistory val specCnt = Vec(PredictWidth, UInt(10.W)) - val br_mask = Vec(PredictWidth, Bool()) } class Ftq_1R_Commit_SRAMEntry extends XSBundle { @@ -127,15 +127,15 @@ class Ftq extends XSModule with HasCircularQueuePtrHelper { ftq_pc_mem.io.waddr(0) := tailPtr.value ftq_pc_mem.io.wdata(0).ftqPC := io.enq.bits.ftqPC ftq_pc_mem.io.wdata(0).lastPacketPC := io.enq.bits.lastPacketPC + ftq_pc_mem.io.wdata(0).hist := io.enq.bits.hist + ftq_pc_mem.io.wdata(0).br_mask := io.enq.bits.br_mask val ftq_2r_sram = Module(new FtqNRSRAM(new Ftq_2R_SRAMEntry, 2)) ftq_2r_sram.io.wen := real_fire ftq_2r_sram.io.waddr := tailPtr.value ftq_2r_sram.io.wdata.rasSp := io.enq.bits.rasSp ftq_2r_sram.io.wdata.rasEntry := io.enq.bits.rasTop - ftq_2r_sram.io.wdata.hist := io.enq.bits.hist ftq_2r_sram.io.wdata.predHist := io.enq.bits.predHist ftq_2r_sram.io.wdata.specCnt := io.enq.bits.specCnt - ftq_2r_sram.io.wdata.br_mask := io.enq.bits.br_mask val pred_target_sram = Module(new FtqNRSRAM(UInt(VAddrBits.W), 1)) pred_target_sram.io.wen := real_fire pred_target_sram.io.waddr := tailPtr.value @@ -229,13 +229,13 @@ class Ftq extends XSModule with HasCircularQueuePtrHelper { // from 4r sram commitEntry.ftqPC := RegNext(ftq_pc_mem.io.rdata(0).ftqPC) commitEntry.lastPacketPC := RegNext(ftq_pc_mem.io.rdata(0).lastPacketPC) + commitEntry.hist := RegNext(ftq_pc_mem.io.rdata(0).hist) + commitEntry.br_mask := RegNext(ftq_pc_mem.io.rdata(0).br_mask) // from 2r sram commitEntry.rasSp := RegNext(ftq_2r_sram.io.rdata(0).rasSp) commitEntry.rasTop := RegNext(ftq_2r_sram.io.rdata(0).rasEntry) - commitEntry.hist := RegNext(ftq_2r_sram.io.rdata(0).hist) commitEntry.predHist := RegNext(ftq_2r_sram.io.rdata(0).predHist) commitEntry.specCnt := RegNext(ftq_2r_sram.io.rdata(0).specCnt) - commitEntry.br_mask := RegNext(ftq_2r_sram.io.rdata(0).br_mask) // from 1r sram commitEntry.metas := RegNext(ftq_1r_sram.io.rdata(0).metas) commitEntry.rvc_mask := RegNext(ftq_1r_sram.io.rdata(0).rvc_mask) @@ -258,6 +258,8 @@ class Ftq extends XSModule with HasCircularQueuePtrHelper { ftq_pc_mem.io.raddr(1 + i) := req.ptr.value req.entry.ftqPC := ftq_pc_mem.io.rdata(1 + i).ftqPC req.entry.lastPacketPC := ftq_pc_mem.io.rdata(1 + i).lastPacketPC + req.entry.hist := ftq_pc_mem.io.rdata(1 + i).hist + req.entry.br_mask := ftq_pc_mem.io.rdata(1 + i).br_mask if(i == 0){ // jump, read npc pred_target_sram.io.raddr(0) := req.ptr.value pred_target_sram.io.ren(0) := true.B @@ -269,10 +271,8 @@ class Ftq extends XSModule with HasCircularQueuePtrHelper { io.cfiRead.entry := DontCare io.cfiRead.entry.rasTop := ftq_2r_sram.io.rdata(1).rasEntry io.cfiRead.entry.rasSp := ftq_2r_sram.io.rdata(1).rasSp - io.cfiRead.entry.hist := ftq_2r_sram.io.rdata(1).hist io.cfiRead.entry.predHist := ftq_2r_sram.io.rdata(1).predHist io.cfiRead.entry.specCnt := ftq_2r_sram.io.rdata(1).specCnt - io.cfiRead.entry.br_mask := ftq_2r_sram.io.rdata(1).br_mask // redirect, reset ptr when(io.flush || io.redirect.valid){ val idx = Mux(io.flush, io.flushIdx, io.redirect.bits.ftqIdx) -- GitLab