From f986a0977fa1a21e41134c88c5c467c2599bb56e Mon Sep 17 00:00:00 2001
From: Zihao Yu <yuzihao@ict.ac.cn>
Date: Sat, 19 Oct 2019 18:56:58 +0800
Subject: [PATCH] riscv64,csr: fix delegation

* machine level interrupts can not be delegated
---
 src/isa/riscv64/reg.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/isa/riscv64/reg.c b/src/isa/riscv64/reg.c
index 02904916..0ca1db72 100644
--- a/src/isa/riscv64/reg.c
+++ b/src/isa/riscv64/reg.c
@@ -80,6 +80,10 @@ void csr_write(uint32_t addr, rtlreg_t *src) {
     mie->val = (mie->val & ~SIE_MASK) | (*src & SIE_MASK);
   } else if (dest == (void *)sip) {
     mip->val = (mip->val & ~SIP_MASK) | (*src & SIP_MASK);
+  } else if (dest == (void *)medeleg) {
+    *dest = *src & 0xbbff;
+  } else if (dest == (void *)mideleg) {
+    *dest = *src & 0x222;
   } else {
     *dest = *src;
   }
-- 
GitLab