From a968eb807feede46f61fbe3ebe1f5950708ba802 Mon Sep 17 00:00:00 2001
From: Zihao Yu <yuzihao@ict.ac.cn>
Date: Mon, 9 Sep 2019 23:38:18 +0800
Subject: [PATCH] riscv64,exec: fix sra with shift amount >= 32

* the LSB of funct7 may be "1" due to the shift amount can be >= 32
---
 src/isa/riscv64/exec/compute.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/isa/riscv64/exec/compute.c b/src/isa/riscv64/exec/compute.c
index d934b508..79192966 100644
--- a/src/isa/riscv64/exec/compute.c
+++ b/src/isa/riscv64/exec/compute.c
@@ -24,8 +24,8 @@ make_EHelper(sll) {
 
 make_EHelper(srl) {
   rtl_andi(&id_src2->val, &id_src2->val, 0x3f);
-
-  if (decinfo.isa.instr.funct7 == 32) {
+  // the LSB of funct7 may be "1" due to the shift amount can be >= 32
+  if ((decinfo.isa.instr.funct7 & ~0x1) == 32) {
     // sra
     rtl_sar(&s0, &id_src->val, &id_src2->val);
     print_asm_template3(sra);
@@ -34,7 +34,6 @@ make_EHelper(srl) {
     rtl_shr(&s0, &id_src->val, &id_src2->val);
     print_asm_template3(srl);
   }
-
   rtl_sr(id_dest->reg, &s0, 4);
 }
 
@@ -118,6 +117,7 @@ make_EHelper(sllw) {
 
 make_EHelper(srlw) {
   rtl_andi(&id_src2->val, &id_src2->val, 0x1f);
+  assert((decinfo.isa.instr.funct7 & 0x1) == 0);
   if (decinfo.isa.instr.funct7 == 32) {
     // sraw
     rtl_sext(&id_src->val, &id_src->val, 4);
-- 
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