diff --git a/src/isa/riscv64/exec/compute.c b/src/isa/riscv64/exec/compute.c
index d934b5084ea4d15f43dac3f03003a861bfd51119..791929661e03a651522699edb4a486d305ec7cae 100644
--- a/src/isa/riscv64/exec/compute.c
+++ b/src/isa/riscv64/exec/compute.c
@@ -24,8 +24,8 @@ make_EHelper(sll) {
 
 make_EHelper(srl) {
   rtl_andi(&id_src2->val, &id_src2->val, 0x3f);
-
-  if (decinfo.isa.instr.funct7 == 32) {
+  // the LSB of funct7 may be "1" due to the shift amount can be >= 32
+  if ((decinfo.isa.instr.funct7 & ~0x1) == 32) {
     // sra
     rtl_sar(&s0, &id_src->val, &id_src2->val);
     print_asm_template3(sra);
@@ -34,7 +34,6 @@ make_EHelper(srl) {
     rtl_shr(&s0, &id_src->val, &id_src2->val);
     print_asm_template3(srl);
   }
-
   rtl_sr(id_dest->reg, &s0, 4);
 }
 
@@ -118,6 +117,7 @@ make_EHelper(sllw) {
 
 make_EHelper(srlw) {
   rtl_andi(&id_src2->val, &id_src2->val, 0x1f);
+  assert((decinfo.isa.instr.funct7 & 0x1) == 0);
   if (decinfo.isa.instr.funct7 == 32) {
     // sraw
     rtl_sext(&id_src->val, &id_src->val, 4);