From 8fa364beac1689108ca78f910301540bbc52a0d3 Mon Sep 17 00:00:00 2001
From: Zihao Yu <yuzihao@ict.ac.cn>
Date: Sun, 3 May 2020 19:16:23 +0800
Subject: [PATCH] riscv{32,64},exec: do not mask the LSB in jalr for a
 non-interpreter engine

* the hardware will do this for us
---
 src/isa/riscv32/exec/control.h | 2 ++
 src/isa/riscv64/exec/control.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/isa/riscv32/exec/control.h b/src/isa/riscv32/exec/control.h
index 56e68174..8b64d191 100644
--- a/src/isa/riscv32/exec/control.h
+++ b/src/isa/riscv32/exec/control.h
@@ -9,7 +9,9 @@ static inline make_EHelper(jal) {
 
 static inline make_EHelper(jalr) {
   rtl_addi(s, s0, dsrc1, id_src2->imm);
+#ifdef __ENGINE_interpreter__
   rtl_andi(s, s0, s0, ~0x1u);
+#endif
   rtl_jr(s, s0);
 
   rtl_li(s, ddest, s->seq_pc);
diff --git a/src/isa/riscv64/exec/control.h b/src/isa/riscv64/exec/control.h
index cd70a4bd..577f57ed 100644
--- a/src/isa/riscv64/exec/control.h
+++ b/src/isa/riscv64/exec/control.h
@@ -9,7 +9,9 @@ static inline make_EHelper(jal) {
 
 static inline make_EHelper(jalr) {
   rtl_addi(s, s0, dsrc1, id_src2->imm);
+#ifdef __ENGINE_interpreter__
   rtl_andi(s, s0, s0, ~0x1lu);
+#endif
   rtl_jr(s, s0);
 
   rtl_li(s, ddest, s->seq_pc);
-- 
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