From 8bc2ca84d45281b9edb9bb4ccf37fd504ca05a9c Mon Sep 17 00:00:00 2001
From: Zihao Yu <yuzihao@ict.ac.cn>
Date: Tue, 21 Apr 2020 21:11:10 +0800
Subject: [PATCH] engine,rv64: support riscv32 guest

---
 src/engine/rv64/isa/mips32.c  | 10 +++++-----
 src/engine/rv64/isa/riscv32.c | 23 +++++++++++++++--------
 src/engine/rv64/tran.h        |  4 ++--
 3 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/src/engine/rv64/isa/mips32.c b/src/engine/rv64/isa/mips32.c
index 0a3aecd2..1be3ab18 100644
--- a/src/engine/rv64/isa/mips32.c
+++ b/src/engine/rv64/isa/mips32.c
@@ -13,11 +13,11 @@ uint32_t rtlreg2varidx(DecodeExecState *s, const rtlreg_t* dest) {
   if (dest >= gpr_start && dest < gpr_end) {
     int rvidx = dest - gpr_start;
     switch (rvidx) {
-      case tmp0:         return 1 | SPMIDX_MASK; break;   // fixed to tmp0
-      case spm_base:     return 2 | SPMIDX_MASK; break;   // used to store sratchpad addr
-      case tmp_reg1:     return 3 | SPMIDX_MASK; break;   // tmp_reg 1
-      case tmp_reg2:     return 4 | SPMIDX_MASK; break;   // tmp_reg 2
-      case mask32:       return 5 | SPMIDX_MASK; break;   // fixed to mask32
+      case tmp0:     return 1 | SPMIDX_MASK;   // fixed to tmp0
+      case spm_base: return 2 | SPMIDX_MASK;   // used to store sratchpad addr
+      case tmp_reg1: return 3 | SPMIDX_MASK;   // tmp_reg 1
+      case tmp_reg2: return 4 | SPMIDX_MASK;   // tmp_reg 2
+      case mask32:   return 5 | SPMIDX_MASK;   // fixed to mask32
       default: return rvidx;
     }
   }
diff --git a/src/engine/rv64/isa/riscv32.c b/src/engine/rv64/isa/riscv32.c
index fa20e9a5..56ffd2a5 100644
--- a/src/engine/rv64/isa/riscv32.c
+++ b/src/engine/rv64/isa/riscv32.c
@@ -6,22 +6,29 @@
 #include <isa/riscv64.h>
 #include "../tran.h"
 
-uint32_t rtlreg2rvidx(DecodeExecState *s, const rtlreg_t* dest) {
+uint32_t rtlreg2varidx(DecodeExecState *s, const rtlreg_t* dest) {
   rtlreg_t* gpr_start = (rtlreg_t *)cpu.gpr;
   rtlreg_t* gpr_end = (void *)gpr_start + sizeof(cpu.gpr);
 
   if (dest >= gpr_start && dest < gpr_end) {
     int rvidx = dest - gpr_start;
-    switch (rvidx) { // idx
-      case 3: case 4: case 31: assert(0); break; // gp, tp, t6
+    switch (rvidx) {
+      case tmp0:     return 1 | SPMIDX_MASK;   // fixed to tmp0
+      case spm_base: return 2 | SPMIDX_MASK;   // used to store sratchpad addr
+      case tmp_reg1: return 3 | SPMIDX_MASK;   // tmp_reg 1
+      case tmp_reg2: return 4 | SPMIDX_MASK;   // tmp_reg 2
+      case mask32:   return 5 | SPMIDX_MASK;   // fixed to mask32
       default: return rvidx;
     }
   }
+  if (dest == rz) return 0;
+
+  // other temps
+  if (dest == s0)      return 6 | SPMIDX_MASK;
+  if (dest == s1)      return 7 | SPMIDX_MASK;
 
-#define CASE(ptr, idx) if (dest == ptr) return idx;
-  CASE(rz, 0)
-  CASE(s0, 31)
   panic("bad ptr = %p", dest);
+  return 0;
 }
 
 void guest_getregs(CPU_state *riscv32) {
@@ -30,7 +37,7 @@ void guest_getregs(CPU_state *riscv32) {
   int i;
   for (i = 0; i < 32; i ++) {
     switch (i) {
-      case 3: case 4: case 31: continue;
+      case tmp0: case mask32: case spm_base: case tmp_reg1: case tmp_reg2: continue;
     }
     riscv32->gpr[i]._32 = r.gpr[i]._64;
   }
@@ -42,7 +49,7 @@ void guest_setregs(const CPU_state *riscv32) {
   int i;
   for (i = 0; i < 32; i ++) {
     switch (i) {
-      case 3: case 4: case 31: continue;
+      case tmp0: case mask32: case spm_base: case tmp_reg1: case tmp_reg2: continue;
     }
     r.gpr[i]._64 = riscv32->gpr[i]._32;
   }
diff --git a/src/engine/rv64/tran.h b/src/engine/rv64/tran.h
index 29a9dc4b..db2b7dd0 100644
--- a/src/engine/rv64/tran.h
+++ b/src/engine/rv64/tran.h
@@ -36,8 +36,8 @@ enum { tmp0 = 30, mask32 = 24, mask16 = 25, spm_base = 0, tmp_reg1 = 0, tmp_reg2
 enum { tmp0 = 1, mask32 = 28, mask16 = 0, spm_base = 25, tmp_reg1 = 26, tmp_reg2 = 27 };
 #define REG_SPILLING
 #elif defined(__ISA_riscv32__)
-enum { tmp0 = 3, mask32 = 4, mask16 = 0, spm_base = 0, tmp_reg1 = 0, tmp_reg2 = 0 };
-//#define REG_SPILLING
+enum { tmp0 = 31, mask32 = 27, mask16 = 0, spm_base = 26, tmp_reg1 = 3, tmp_reg2 = 4 };
+#define REG_SPILLING
 #endif
 
 #endif
-- 
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