diff --git a/src/isa/riscv64/exec/compute.c b/src/isa/riscv64/exec/compute.c index f9aea25108ce5ea3896078fd46fce4dcd48bb075..6ea6bbc2ea23f4092d1623601d1f8508a5e21ced 100644 --- a/src/isa/riscv64/exec/compute.c +++ b/src/isa/riscv64/exec/compute.c @@ -22,25 +22,25 @@ make_EHelper(sll) { print_asm_template3(sll); } -make_EHelper(srl) { +make_EHelper(sra) { rtl_andi(&id_src2->val, &id_src2->val, 0x3f); + rtl_sar(&s0, &id_src->val, &id_src2->val); + print_asm_template3(sra); + rtl_sr(id_dest->reg, &s0, 4); +} + +make_EHelper(srl) { // the LSB of funct7 may be "1" due to the shift amount can be >= 32 if ((decinfo.isa.instr.funct7 & ~0x1) == 32) { - // sra - rtl_sar(&s0, &id_src->val, &id_src2->val); - print_asm_template3(sra); - } - else { - rtl_shr(&s0, &id_src->val, &id_src2->val); - print_asm_template3(srl); + exec_sra(pc); + return; } + rtl_andi(&id_src2->val, &id_src2->val, 0x3f); + rtl_shr(&s0, &id_src->val, &id_src2->val); + print_asm_template3(srl); rtl_sr(id_dest->reg, &s0, 4); } -make_EHelper(sra) { - exec_srl(NULL); -} - make_EHelper(slt) { rtl_setrelop(RELOP_LT, &s0, &id_src->val, &id_src2->val); rtl_sr(id_dest->reg, &s0, 4); diff --git a/src/isa/riscv64/exec/exec.c b/src/isa/riscv64/exec/exec.c index e0684636afa44426ce11fcc1a9e8afa593380808..6ba82bdc30540290b1b5e2027e5d0689f025f722 100644 --- a/src/isa/riscv64/exec/exec.c +++ b/src/isa/riscv64/exec/exec.c @@ -97,7 +97,7 @@ static make_EHelper(C_01_100) { if (func == 3) { decode_CR(pc); static OpcodeEntry table [8] = { - EX(sub), EMPTY, EX(or), EX(and), EX(subw), EX(addw), EMPTY, EMPTY, + EX(sub), EX(xor), EX(or), EX(and), EX(subw), EX(addw), EMPTY, EMPTY, }; uint32_t idx2 = (decinfo.isa.instr.c_func6 >> 2) & 0x1; @@ -107,7 +107,7 @@ static make_EHelper(C_01_100) { idex(pc, &table[idx]); } else { decode_C_rs1__imm_rd_(pc); - static OpcodeEntry table [3] = { EX(srl), EMPTY, EX(and) }; + static OpcodeEntry table [3] = { EX(srl), EX(sra), EX(and) }; idex(pc, &table[func]); } }