From 5d0ba0672abb6e964840d1102740821113de3d8a Mon Sep 17 00:00:00 2001
From: Zihao Yu <yuzihao@ict.ac.cn>
Date: Mon, 9 Sep 2019 23:37:00 +0800
Subject: [PATCH] riscv64,exec: fix sraw

* the src should be first sign-extended
---
 src/isa/riscv64/exec/compute.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/isa/riscv64/exec/compute.c b/src/isa/riscv64/exec/compute.c
index 301fa3d8..d934b508 100644
--- a/src/isa/riscv64/exec/compute.c
+++ b/src/isa/riscv64/exec/compute.c
@@ -120,6 +120,7 @@ make_EHelper(srlw) {
   rtl_andi(&id_src2->val, &id_src2->val, 0x1f);
   if (decinfo.isa.instr.funct7 == 32) {
     // sraw
+    rtl_sext(&id_src->val, &id_src->val, 4);
     rtl_sar(&s0, &id_src->val, &id_src2->val);
     rtl_sext(&s0, &s0, 4);
     print_asm_template3(sraw);
-- 
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