From 06a0867923001688bb7b3f215c9d709f9529e3f4 Mon Sep 17 00:00:00 2001
From: Zihao Yu <yuzihao@ict.ac.cn>
Date: Sun, 15 Sep 2019 04:02:12 +0800
Subject: [PATCH] riscv64,exec: pass wanshu

---
 src/isa/riscv64/decode.c             | 66 +++++++++++++++++++---------
 src/isa/riscv64/exec/all-instr.h     |  1 +
 src/isa/riscv64/exec/control.c       |  5 +++
 src/isa/riscv64/exec/exec.c          |  8 ++--
 src/isa/riscv64/include/isa/decode.h | 10 +++--
 5 files changed, 61 insertions(+), 29 deletions(-)

diff --git a/src/isa/riscv64/decode.c b/src/isa/riscv64/decode.c
index a13cdf8a..01b384f1 100644
--- a/src/isa/riscv64/decode.c
+++ b/src/isa/riscv64/decode.c
@@ -95,14 +95,6 @@ make_DHelper(csr) {
 
 #define creg2reg(creg) (creg + 8)
 
-make_DHelper(CI) {
-  decode_op_r(id_src, decinfo.isa.instr.c_rd_rs1, true);
-  sword_t simm = (decinfo.isa.instr.c_simm12 << 5) | decinfo.isa.instr.c_imm6_2;
-  assert(simm != 0);
-  decode_op_i(id_src2, simm, true);
-  decode_op_r(id_dest, decinfo.isa.instr.c_rd_rs1, false);
-}
-
 make_DHelper(CR) {
   decode_op_r(id_src, creg2reg(decinfo.isa.instr.c_rd_rs1_), true);
   decode_op_r(id_src2, creg2reg(decinfo.isa.instr.c_rs2_), true);
@@ -124,6 +116,22 @@ make_DHelper(CB) {
   decode_op_r(id_src2, 0, true);
 }
 
+static make_DHelper(CJ) {
+  sword_t simm11 = decinfo.isa.instr.c_simm12;
+  uint32_t imm10  = (decinfo.isa.instr.c_target >> 6) & 0x1;
+  uint32_t imm9_8 = (decinfo.isa.instr.c_target >> 7) & 0x3;
+  uint32_t imm7   = (decinfo.isa.instr.c_target >> 4) & 0x1;
+  uint32_t imm6   = (decinfo.isa.instr.c_target >> 5) & 0x1;
+  uint32_t imm5   = (decinfo.isa.instr.c_target >> 0) & 0x1;
+  uint32_t imm4   = (decinfo.isa.instr.c_target >> 9) & 0x1;
+  uint32_t imm3_1 = (decinfo.isa.instr.c_target >> 1) & 0x7;
+
+  sword_t offset = (simm11 << 11) | (imm10 << 10) | (imm9_8 << 8) |
+    (imm7 << 7) | (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | (imm3_1 << 1);
+  decinfo.jmp_pc = cpu.pc + offset;
+  decode_op_i(id_src, decinfo.jmp_pc, true);
+}
+
 make_DHelper(C_SDSP) {
   decode_op_r(id_src, 2, true);
   uint32_t imm8_6 = (decinfo.isa.instr.c_imm12_7 & 0x7);
@@ -154,26 +162,37 @@ make_DHelper(C_LDSP) {
   decinfo.width = 8;
 }
 
-make_DHelper(C_LI) {
-  decode_op_r(id_src, 0, true);
+static void decode_C_xxx_imm_rd(bool is_rs1_zero) {
+  decode_op_r(id_src, (is_rs1_zero ? 0 : decinfo.isa.instr.c_rd_rs1), true);
   sword_t simm = (decinfo.isa.instr.c_simm12 << 5) | decinfo.isa.instr.c_imm6_2;
   decode_op_i(id_src2, simm, true);
   decode_op_r(id_dest, decinfo.isa.instr.c_rd_rs1, false);
 }
 
-make_DHelper(C_MV) {
-  decode_op_r(id_src, 0, true);
-  decode_op_r(id_src2, decinfo.isa.instr.c_rs2, true);
-  decode_op_r(id_dest, decinfo.isa.instr.c_rd_rs1, false);
-  assert(decinfo.isa.instr.c_rs2 != 0);
-  assert(decinfo.isa.instr.c_rd_rs1 != 0);
+make_DHelper(C_0_imm_rd) {
+  decode_C_xxx_imm_rd(true);
 }
 
-make_DHelper(C_10_100) {
-  decode_op_r(id_src, decinfo.isa.instr.c_rd_rs1, true);
-  decode_op_r(id_src2, decinfo.isa.instr.c_rs2, true);
-  decode_op_r(id_dest, 0, false);
-  // overwrite id_dest if necessary
+make_DHelper(C_rs1_imm_rd) {
+  decode_C_xxx_imm_rd(false);
+}
+
+static void decode_C_xxx_xxx_xxx(bool is_rs1_zero, bool is_rs2_zero, bool is_rd_zero) {
+  decode_op_r(id_src, (is_rs1_zero ? 0 : decinfo.isa.instr.c_rd_rs1), true);
+  decode_op_r(id_src2, (is_rs2_zero ? 0 : decinfo.isa.instr.c_rs2), true);
+  decode_op_r(id_dest, (is_rd_zero ? 0 : decinfo.isa.instr.c_rd_rs1), false);
+}
+
+make_DHelper(C_0_rs2_rd) {
+  decode_C_xxx_xxx_xxx(true, false, false);
+}
+
+make_DHelper(C_rs1_rs2_0) {
+  decode_C_xxx_xxx_xxx(false, false, true);
+}
+
+make_DHelper(C_rs1_rs2_rd) {
+  decode_C_xxx_xxx_xxx(false, false, false);
 }
 
 make_DHelper(C_ADDI16SP) {
@@ -203,3 +222,8 @@ make_DHelper(C_LW) {
 
   decinfo.width = 4;
 }
+
+make_DHelper(C_J) {
+  decode_CJ(pc);
+  decode_op_r(id_dest, 0, false);
+}
diff --git a/src/isa/riscv64/exec/all-instr.h b/src/isa/riscv64/exec/all-instr.h
index 83b7e0ca..f7602511 100644
--- a/src/isa/riscv64/exec/all-instr.h
+++ b/src/isa/riscv64/exec/all-instr.h
@@ -21,6 +21,7 @@ make_EHelper(jal);
 make_EHelper(jalr);
 make_EHelper(branch);
 make_EHelper(beq);
+make_EHelper(bne);
 
 make_EHelper(inv);
 make_EHelper(nemu_trap);
diff --git a/src/isa/riscv64/exec/control.c b/src/isa/riscv64/exec/control.c
index 5dbda15d..e28cb028 100644
--- a/src/isa/riscv64/exec/control.c
+++ b/src/isa/riscv64/exec/control.c
@@ -45,3 +45,8 @@ make_EHelper(beq) {
   rtl_jrelop(RELOP_EQ, &id_src->val, &id_src2->val, decinfo.jmp_pc);
   print_asm("beq %s,%s,%s", id_src->str, id_src2->str, id_dest->str);
 }
+
+make_EHelper(bne) {
+  rtl_jrelop(RELOP_NE, &id_src->val, &id_src2->val, decinfo.jmp_pc);
+  print_asm("bne %s,%s,%s", id_src->str, id_src2->str, id_dest->str);
+}
diff --git a/src/isa/riscv64/exec/exec.c b/src/isa/riscv64/exec/exec.c
index a4e90969..6c134ecc 100644
--- a/src/isa/riscv64/exec/exec.c
+++ b/src/isa/riscv64/exec/exec.c
@@ -75,7 +75,7 @@ static OpcodeEntry opcode_table [32] = {
 
 static make_EHelper(C_10_100) {
   static OpcodeEntry table [8] = {
-    EMPTY, EMPTY, EX(jalr), IDEX(C_MV, add), EMPTY, EMPTY, EMPTY, EMPTY,
+    EMPTY, EMPTY, IDEX(C_rs1_rs2_0, jalr), IDEX(C_0_rs2_rd, add), EMPTY, EMPTY, EMPTY, IDEX(C_rs1_rs2_rd, add),
   };
   uint32_t cond_c_simm12_not0 = (decinfo.isa.instr.c_simm12 != 0);
   uint32_t cond_c_rd_rs1_not0 = (decinfo.isa.instr.c_rd_rs1 != 0);
@@ -98,7 +98,7 @@ static make_EHelper(C_01_100) {
     case 3: {
       decode_CR(pc);
       static OpcodeEntry table [8] = {
-        EX(sub), EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
+        EX(sub), EMPTY, EMPTY, EMPTY, EMPTY, EX(addw), EMPTY, EMPTY,
       };
 
       uint32_t idx2 = (decinfo.isa.instr.c_func6 >> 2) & 0x1;
@@ -114,8 +114,8 @@ static make_EHelper(C_01_100) {
 
 static OpcodeEntry rvc_table [3][8] = {
   {EMPTY, EMPTY, IDEX(C_LW, lds), EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, },
-  {IDEX(CI, add), EMPTY, IDEX(C_LI, add), EX(C_01_011), EX(C_01_100), EMPTY, IDEX(CB, beq), EMPTY, },
-  {EMPTY, EMPTY, EMPTY, IDEX(C_LDSP, ld), IDEX(C_10_100, C_10_100), EMPTY, EMPTY, IDEX(C_SDSP, st), },
+  {IDEX(C_rs1_imm_rd, add), IDEX(C_rs1_imm_rd, addw), IDEX(C_0_imm_rd, add), EX(C_01_011), EX(C_01_100), IDEX(C_J, jal), IDEX(CB, beq), IDEX(CB, bne), },
+  {EMPTY, EMPTY, EMPTY, IDEX(C_LDSP, ld), EX(C_10_100), EMPTY, EMPTY, IDEX(C_SDSP, st), },
 };
 
 void isa_exec(vaddr_t *pc) {
diff --git a/src/isa/riscv64/include/isa/decode.h b/src/isa/riscv64/include/isa/decode.h
index 537716ac..b8a4469c 100644
--- a/src/isa/riscv64/include/isa/decode.h
+++ b/src/isa/riscv64/include/isa/decode.h
@@ -111,15 +111,17 @@ make_DHelper(ld);
 make_DHelper(st);
 make_DHelper(csr);
 
-make_DHelper(CI);
 make_DHelper(CR);
 make_DHelper(CB);
 make_DHelper(C_SDSP);
 make_DHelper(C_LDSP);
-make_DHelper(C_MV);
-make_DHelper(C_LI);
-make_DHelper(C_10_100);
+make_DHelper(C_0_imm_rd);
+make_DHelper(C_rs1_imm_rd);
+make_DHelper(C_0_rs2_rd);
+make_DHelper(C_rs1_rs2_0);
+make_DHelper(C_rs1_rs2_rd);
 make_DHelper(C_ADDI16SP);
 make_DHelper(C_LW);
+make_DHelper(C_J);
 
 #endif
-- 
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