From 86d7b7a34756b89f95e923e22fc1927d36ba22d6 Mon Sep 17 00:00:00 2001 From: BernardXiong Date: Sun, 27 Jan 2019 01:11:35 +0000 Subject: [PATCH] [BSP] remove imxrt1052-evk and use imxrt later --- bsp/imxrt1052-evk/.config | 447 - bsp/imxrt1052-evk/Kconfig | 463 - .../CMSIS/Include/arm_common_tables.h | 121 - .../CMSIS/Include/arm_const_structs.h | 66 - .../Libraries/CMSIS/Include/arm_math.h | 7226 ---- .../Libraries/CMSIS/Include/cmsis_armcc.h | 814 - .../Libraries/CMSIS/Include/cmsis_armclang.h | 1802 - .../Libraries/CMSIS/Include/cmsis_compiler.h | 353 - .../Libraries/CMSIS/Include/cmsis_gcc.h | 1979 - .../Libraries/CMSIS/Include/cmsis_version.h | 39 - .../Libraries/CMSIS/Include/core_armv8mbl.h | 1878 - .../Libraries/CMSIS/Include/core_armv8mml.h | 2902 -- .../Libraries/CMSIS/Include/core_cm0.h | 888 - .../Libraries/CMSIS/Include/core_cm0plus.h | 1021 - .../Libraries/CMSIS/Include/core_cm23.h | 1878 - .../Libraries/CMSIS/Include/core_cm3.h | 1928 - .../Libraries/CMSIS/Include/core_cm33.h | 2898 -- .../Libraries/CMSIS/Include/core_cm4.h | 2113 -- .../Libraries/CMSIS/Include/core_cm7.h | 2655 -- .../Libraries/CMSIS/Include/core_sc000.h | 1016 - .../Libraries/CMSIS/Include/core_sc300.h | 1903 - .../Libraries/CMSIS/Include/mpu_armv7.h | 182 - .../Libraries/CMSIS/Include/tz_context.h | 69 - bsp/imxrt1052-evk/Libraries/CMSIS/LICENSE.txt | 201 - bsp/imxrt1052-evk/Libraries/MIMXRT1052.h | 29863 ---------------- .../Libraries/MIMXRT1052_features.h | 615 - bsp/imxrt1052-evk/Libraries/SConscript | 27 - .../arm/MIMXRT1052xxxxx_flexspi_nor.scf | 127 - .../Libraries/arm/MIMXRT1052xxxxx_ram.scf | 92 - .../Libraries/arm/MIMXRT1052xxxxx_sdram.scf | 99 - .../arm/MIMXRT1052xxxxx_sdram_txt.scf | 99 - .../arm/evkmimxrt1050_flexspi_nor.ini | 45 - .../Libraries/arm/startup_MIMXRT1052.s | 1044 - bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.c | 306 - bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.h | 446 - .../Libraries/drivers/fsl_adc_etc.c | 365 - .../Libraries/drivers/fsl_adc_etc.h | 342 - .../Libraries/drivers/fsl_aipstz.c | 66 - .../Libraries/drivers/fsl_aipstz.h | 155 - bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.c | 157 - bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.h | 213 - bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.c | 244 - bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.h | 228 - .../Libraries/drivers/fsl_cache.c | 470 - .../Libraries/drivers/fsl_cache.h | 494 - .../Libraries/drivers/fsl_clock.c | 917 - .../Libraries/drivers/fsl_clock.h | 1466 - bsp/imxrt1052-evk/Libraries/drivers/fsl_cmp.c | 295 - bsp/imxrt1052-evk/Libraries/drivers/fsl_cmp.h | 347 - .../Libraries/drivers/fsl_common.c | 192 - .../Libraries/drivers/fsl_common.h | 576 - bsp/imxrt1052-evk/Libraries/drivers/fsl_csi.c | 694 - bsp/imxrt1052-evk/Libraries/drivers/fsl_csi.h | 562 - .../Libraries/drivers/fsl_dcdc.c | 351 - .../Libraries/drivers/fsl_dcdc.h | 490 - bsp/imxrt1052-evk/Libraries/drivers/fsl_dcp.c | 1129 - bsp/imxrt1052-evk/Libraries/drivers/fsl_dcp.h | 557 - .../Libraries/drivers/fsl_dmamux.c | 103 - .../Libraries/drivers/fsl_dmamux.h | 204 - .../Libraries/drivers/fsl_edma.c | 2299 -- .../Libraries/drivers/fsl_edma.h | 957 - .../Libraries/drivers/fsl_elcdif.c | 303 - .../Libraries/drivers/fsl_elcdif.h | 768 - bsp/imxrt1052-evk/Libraries/drivers/fsl_enc.c | 489 - bsp/imxrt1052-evk/Libraries/drivers/fsl_enc.h | 484 - .../Libraries/drivers/fsl_enet.c | 2975 -- .../Libraries/drivers/fsl_enet.h | 1635 - bsp/imxrt1052-evk/Libraries/drivers/fsl_ewm.c | 112 - bsp/imxrt1052-evk/Libraries/drivers/fsl_ewm.h | 245 - .../Libraries/drivers/fsl_flexcan.c | 2127 -- .../Libraries/drivers/fsl_flexcan.h | 1327 - .../Libraries/drivers/fsl_flexio.c | 320 - .../Libraries/drivers/fsl_flexio.h | 726 - .../Libraries/drivers/fsl_flexio_i2c_master.c | 818 - .../Libraries/drivers/fsl_flexio_i2c_master.h | 487 - .../Libraries/drivers/fsl_flexio_i2s.c | 668 - .../Libraries/drivers/fsl_flexio_i2s.h | 574 - .../Libraries/drivers/fsl_flexio_i2s_edma.c | 377 - .../Libraries/drivers/fsl_flexio_i2s_edma.h | 229 - .../Libraries/drivers/fsl_flexio_spi.c | 1005 - .../Libraries/drivers/fsl_flexio_spi.h | 707 - .../Libraries/drivers/fsl_flexio_spi_edma.c | 442 - .../Libraries/drivers/fsl_flexio_spi_edma.h | 233 - .../Libraries/drivers/fsl_flexio_uart.c | 730 - .../Libraries/drivers/fsl_flexio_uart.h | 586 - .../Libraries/drivers/fsl_flexio_uart_edma.c | 360 - .../Libraries/drivers/fsl_flexio_uart_edma.h | 204 - .../Libraries/drivers/fsl_flexram.c | 233 - .../Libraries/drivers/fsl_flexram.h | 323 - .../Libraries/drivers/fsl_flexspi.c | 868 - .../Libraries/drivers/fsl_flexspi.h | 844 - bsp/imxrt1052-evk/Libraries/drivers/fsl_gpc.c | 111 - bsp/imxrt1052-evk/Libraries/drivers/fsl_gpc.h | 257 - .../Libraries/drivers/fsl_gpio.c | 166 - .../Libraries/drivers/fsl_gpio.h | 368 - bsp/imxrt1052-evk/Libraries/drivers/fsl_gpt.c | 124 - bsp/imxrt1052-evk/Libraries/drivers/fsl_gpt.h | 533 - .../Libraries/drivers/fsl_iomuxc.h | 1272 - bsp/imxrt1052-evk/Libraries/drivers/fsl_kpp.c | 202 - bsp/imxrt1052-evk/Libraries/drivers/fsl_kpp.h | 203 - .../Libraries/drivers/fsl_lpi2c.c | 1927 - .../Libraries/drivers/fsl_lpi2c.h | 1293 - .../Libraries/drivers/fsl_lpi2c_edma.c | 486 - .../Libraries/drivers/fsl_lpi2c_edma.h | 183 - .../Libraries/drivers/fsl_lpspi.c | 1851 - .../Libraries/drivers/fsl_lpspi.h | 1145 - .../Libraries/drivers/fsl_lpspi_edma.c | 1056 - .../Libraries/drivers/fsl_lpspi_edma.h | 328 - .../Libraries/drivers/fsl_lpuart.c | 1771 - .../Libraries/drivers/fsl_lpuart.h | 880 - .../Libraries/drivers/fsl_lpuart_edma.c | 380 - .../Libraries/drivers/fsl_lpuart_edma.h | 199 - bsp/imxrt1052-evk/Libraries/drivers/fsl_pit.c | 138 - bsp/imxrt1052-evk/Libraries/drivers/fsl_pit.h | 358 - bsp/imxrt1052-evk/Libraries/drivers/fsl_pmu.c | 77 - bsp/imxrt1052-evk/Libraries/drivers/fsl_pmu.h | 690 - bsp/imxrt1052-evk/Libraries/drivers/fsl_pwm.c | 693 - bsp/imxrt1052-evk/Libraries/drivers/fsl_pwm.h | 696 - bsp/imxrt1052-evk/Libraries/drivers/fsl_pxp.c | 533 - bsp/imxrt1052-evk/Libraries/drivers/fsl_pxp.h | 1235 - .../Libraries/drivers/fsl_qtmr.c | 477 - .../Libraries/drivers/fsl_qtmr.h | 461 - .../Libraries/drivers/fsl_rtwdog.c | 105 - .../Libraries/drivers/fsl_rtwdog.h | 404 - bsp/imxrt1052-evk/Libraries/drivers/fsl_sai.c | 2104 -- bsp/imxrt1052-evk/Libraries/drivers/fsl_sai.h | 1043 - .../Libraries/drivers/fsl_sai_edma.c | 509 - .../Libraries/drivers/fsl_sai_edma.h | 268 - .../Libraries/drivers/fsl_semc.c | 986 - .../Libraries/drivers/fsl_semc.h | 807 - .../Libraries/drivers/fsl_snvs_hp.c | 463 - .../Libraries/drivers/fsl_snvs_hp.h | 309 - .../Libraries/drivers/fsl_snvs_lp.c | 609 - .../Libraries/drivers/fsl_snvs_lp.h | 381 - .../Libraries/drivers/fsl_spdif.c | 678 - .../Libraries/drivers/fsl_spdif.h | 767 - .../Libraries/drivers/fsl_spdif_edma.c | 521 - .../Libraries/drivers/fsl_spdif_edma.h | 217 - bsp/imxrt1052-evk/Libraries/drivers/fsl_src.c | 70 - bsp/imxrt1052-evk/Libraries/drivers/fsl_src.h | 623 - .../Libraries/drivers/fsl_trng.c | 1664 - .../Libraries/drivers/fsl_trng.h | 245 - bsp/imxrt1052-evk/Libraries/drivers/fsl_tsc.c | 221 - bsp/imxrt1052-evk/Libraries/drivers/fsl_tsc.h | 548 - .../Libraries/drivers/fsl_usdhc.c | 1796 - .../Libraries/drivers/fsl_usdhc.h | 1505 - .../Libraries/drivers/fsl_wdog.c | 141 - .../Libraries/drivers/fsl_wdog.h | 303 - .../Libraries/drivers/fsl_xbara.c | 222 - .../Libraries/drivers/fsl_xbara.h | 211 - .../Libraries/drivers/fsl_xbarb.c | 112 - .../Libraries/drivers/fsl_xbarb.h | 111 - .../Libraries/fsl_device_registers.h | 64 - .../gcc/MIMXRT1052xxxxx_flexspi_nor.ld | 276 - .../Libraries/gcc/MIMXRT1052xxxxx_ram.ld | 256 - .../Libraries/gcc/MIMXRT1052xxxxx_sdram.ld | 245 - .../gcc/MIMXRT1052xxxxx_sdram_txt.ld | 245 - .../Libraries/gcc/startup_MIMXRT1052.S | 1090 - .../Libraries/iar/MIMXRT1052xxx6A_ram.icf | 94 - .../Libraries/iar/MIMXRT1052xxx6A_sdram.icf | 91 - .../iar/MIMXRT1052xxxxx_flexspi_nor.icf | 117 - .../Libraries/iar/MIMXRT1052xxxxx_ram.icf | 101 - .../Libraries/iar/MIMXRT1052xxxxx_sdram.icf | 109 - .../iar/MIMXRT1052xxxxx_sdram_txt.icf | 109 - .../Libraries/iar/startup_MIMXRT1052.s | 1009 - .../Libraries/system_MIMXRT1052.c | 255 - .../Libraries/system_MIMXRT1052.h | 147 - bsp/imxrt1052-evk/README.md | 105 - bsp/imxrt1052-evk/SConscript | 14 - bsp/imxrt1052-evk/SConstruct | 76 - bsp/imxrt1052-evk/applications/SConscript | 17 - bsp/imxrt1052-evk/applications/device_test.c | 517 - bsp/imxrt1052-evk/applications/lcd_init.c | 42 - bsp/imxrt1052-evk/applications/main.c | 150 - bsp/imxrt1052-evk/applications/mem_dump.c | 50 - bsp/imxrt1052-evk/applications/mem_test.c | 103 - bsp/imxrt1052-evk/drivers/SConscript | 76 - bsp/imxrt1052-evk/drivers/board.c | 204 - bsp/imxrt1052-evk/drivers/board.h | 52 - bsp/imxrt1052-evk/drivers/drv_cache.c | 75 - bsp/imxrt1052-evk/drivers/drv_codec.c | 395 - bsp/imxrt1052-evk/drivers/drv_codec.h | 228 - bsp/imxrt1052-evk/drivers/drv_eth.c | 1430 - bsp/imxrt1052-evk/drivers/drv_eth_fire.c | 1120 - bsp/imxrt1052-evk/drivers/drv_ft5406.c | 354 - bsp/imxrt1052-evk/drivers/drv_hwtimer.c | 189 - bsp/imxrt1052-evk/drivers/drv_hwtimer.h | 34 - bsp/imxrt1052-evk/drivers/drv_i2c.c | 475 - bsp/imxrt1052-evk/drivers/drv_i2c.h | 34 - bsp/imxrt1052-evk/drivers/drv_lcd.c | 211 - bsp/imxrt1052-evk/drivers/drv_lcd.h | 23 - bsp/imxrt1052-evk/drivers/drv_pcf8574.c | 69 - bsp/imxrt1052-evk/drivers/drv_pcf8574.h | 28 - bsp/imxrt1052-evk/drivers/drv_pin.c | 695 - bsp/imxrt1052-evk/drivers/drv_pin.h | 24 - bsp/imxrt1052-evk/drivers/drv_rtc.c | 149 - bsp/imxrt1052-evk/drivers/drv_rtc.h | 23 - bsp/imxrt1052-evk/drivers/drv_sdio.c | 564 - bsp/imxrt1052-evk/drivers/drv_sdram.c | 195 - bsp/imxrt1052-evk/drivers/drv_spi_bus.c | 428 - bsp/imxrt1052-evk/drivers/drv_spi_bus.h | 24 - bsp/imxrt1052-evk/drivers/drv_spi_flash.c | 51 - bsp/imxrt1052-evk/drivers/drv_spi_flash.h | 23 - bsp/imxrt1052-evk/drivers/drv_uart.c | 568 - bsp/imxrt1052-evk/drivers/drv_uart.h | 22 - bsp/imxrt1052-evk/drivers/drv_usbd.c | 561 - bsp/imxrt1052-evk/drivers/fsl_phy.c | 361 - bsp/imxrt1052-evk/drivers/fsl_phy.h | 241 - bsp/imxrt1052-evk/drivers/fsl_wm8960.c | 621 - bsp/imxrt1052-evk/drivers/fsl_wm8960.h | 426 - .../drivers/usb/device/usb_device.h | 644 - .../drivers/usb/device/usb_device_dci.c | 1459 - .../drivers/usb/device/usb_device_dci.h | 177 - .../drivers/usb/device/usb_device_ehci.c | 1807 - .../drivers/usb/device/usb_device_ehci.h | 219 - bsp/imxrt1052-evk/drivers/usb/host/usb_host.h | 726 - .../drivers/usb/host/usb_host_devices.c | 1414 - .../drivers/usb/host/usb_host_devices.h | 178 - .../drivers/usb/host/usb_host_ehci.c | 4747 --- .../drivers/usb/host/usb_host_ehci.h | 499 - .../drivers/usb/host/usb_host_hci.c | 1052 - .../drivers/usb/host/usb_host_hci.h | 131 - bsp/imxrt1052-evk/drivers/usb/include/usb.h | 140 - .../drivers/usb/include/usb_device_config.h | 185 - .../drivers/usb/include/usb_ehci.h | 140 - .../drivers/usb/include/usb_misc.h | 452 - .../drivers/usb/include/usb_spec.h | 296 - bsp/imxrt1052-evk/drivers/usb/phy/usb_phy.c | 240 - bsp/imxrt1052-evk/drivers/usb/phy/usb_phy.h | 113 - bsp/imxrt1052-evk/project.ewd | 2908 -- bsp/imxrt1052-evk/project.ewp | 2478 -- bsp/imxrt1052-evk/project.eww | 10 - bsp/imxrt1052-evk/project.uvoptx | 190 - bsp/imxrt1052-evk/project.uvprojx | 1704 - bsp/imxrt1052-evk/rtconfig.h | 251 - bsp/imxrt1052-evk/rtconfig.py | 144 - bsp/imxrt1052-evk/template.ewp | 1823 - bsp/imxrt1052-evk/template.uvoptx | 190 - bsp/imxrt1052-evk/template.uvprojx | 400 - bsp/imxrt1052-evk/xip/SConscript | 23 - bsp/imxrt1052-evk/xip/fsl_flexspi_nor_boot.c | 139 - bsp/imxrt1052-evk/xip/fsl_flexspi_nor_boot.h | 118 - bsp/imxrt1052-evk/xip/fsl_flexspi_nor_flash.c | 76 - bsp/imxrt1052-evk/xip/fsl_flexspi_nor_flash.h | 299 - 244 files changed, 181340 deletions(-) delete mode 100644 bsp/imxrt1052-evk/.config delete mode 100644 bsp/imxrt1052-evk/Kconfig delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/arm_common_tables.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/arm_const_structs.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/arm_math.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_armcc.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_armclang.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_compiler.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_gcc.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_version.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_armv8mbl.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_armv8mml.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm0.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm0plus.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm23.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm3.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm33.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm4.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm7.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_sc000.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_sc300.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/mpu_armv7.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/Include/tz_context.h delete mode 100644 bsp/imxrt1052-evk/Libraries/CMSIS/LICENSE.txt delete mode 100644 bsp/imxrt1052-evk/Libraries/MIMXRT1052.h delete mode 100644 bsp/imxrt1052-evk/Libraries/MIMXRT1052_features.h delete mode 100644 bsp/imxrt1052-evk/Libraries/SConscript delete mode 100644 bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf delete mode 100644 bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_ram.scf delete mode 100644 bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_sdram.scf delete mode 100644 bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_sdram_txt.scf delete mode 100644 bsp/imxrt1052-evk/Libraries/arm/evkmimxrt1050_flexspi_nor.ini delete mode 100644 bsp/imxrt1052-evk/Libraries/arm/startup_MIMXRT1052.s delete mode 100644 bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.c delete mode 100644 bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.h delete mode 100644 bsp/imxrt1052-evk/Libraries/drivers/fsl_adc_etc.c delete mode 100644 bsp/imxrt1052-evk/Libraries/drivers/fsl_adc_etc.h delete mode 100644 bsp/imxrt1052-evk/Libraries/drivers/fsl_aipstz.c delete mode 100644 bsp/imxrt1052-evk/Libraries/drivers/fsl_aipstz.h delete mode 100644 bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.c delete mode 100644 bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.h delete mode 100644 bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.c delete mode 100644 bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.h delete mode 100644 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bsp/imxrt1052-evk/applications/mem_dump.c delete mode 100644 bsp/imxrt1052-evk/applications/mem_test.c delete mode 100644 bsp/imxrt1052-evk/drivers/SConscript delete mode 100644 bsp/imxrt1052-evk/drivers/board.c delete mode 100644 bsp/imxrt1052-evk/drivers/board.h delete mode 100644 bsp/imxrt1052-evk/drivers/drv_cache.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_codec.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_codec.h delete mode 100644 bsp/imxrt1052-evk/drivers/drv_eth.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_eth_fire.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_ft5406.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_hwtimer.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_hwtimer.h delete mode 100644 bsp/imxrt1052-evk/drivers/drv_i2c.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_i2c.h delete mode 100644 bsp/imxrt1052-evk/drivers/drv_lcd.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_lcd.h delete mode 100644 bsp/imxrt1052-evk/drivers/drv_pcf8574.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_pcf8574.h delete mode 100644 bsp/imxrt1052-evk/drivers/drv_pin.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_pin.h delete mode 100644 bsp/imxrt1052-evk/drivers/drv_rtc.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_rtc.h delete mode 100644 bsp/imxrt1052-evk/drivers/drv_sdio.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_sdram.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_spi_bus.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_spi_bus.h delete mode 100644 bsp/imxrt1052-evk/drivers/drv_spi_flash.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_spi_flash.h delete mode 100644 bsp/imxrt1052-evk/drivers/drv_uart.c delete mode 100644 bsp/imxrt1052-evk/drivers/drv_uart.h delete mode 100644 bsp/imxrt1052-evk/drivers/drv_usbd.c delete mode 100644 bsp/imxrt1052-evk/drivers/fsl_phy.c delete mode 100644 bsp/imxrt1052-evk/drivers/fsl_phy.h delete mode 100644 bsp/imxrt1052-evk/drivers/fsl_wm8960.c delete mode 100644 bsp/imxrt1052-evk/drivers/fsl_wm8960.h delete mode 100644 bsp/imxrt1052-evk/drivers/usb/device/usb_device.h delete mode 100644 bsp/imxrt1052-evk/drivers/usb/device/usb_device_dci.c delete mode 100644 bsp/imxrt1052-evk/drivers/usb/device/usb_device_dci.h delete mode 100644 bsp/imxrt1052-evk/drivers/usb/device/usb_device_ehci.c delete mode 100644 bsp/imxrt1052-evk/drivers/usb/device/usb_device_ehci.h delete mode 100644 bsp/imxrt1052-evk/drivers/usb/host/usb_host.h delete mode 100644 bsp/imxrt1052-evk/drivers/usb/host/usb_host_devices.c delete mode 100644 bsp/imxrt1052-evk/drivers/usb/host/usb_host_devices.h delete mode 100644 bsp/imxrt1052-evk/drivers/usb/host/usb_host_ehci.c delete mode 100644 bsp/imxrt1052-evk/drivers/usb/host/usb_host_ehci.h delete mode 100644 bsp/imxrt1052-evk/drivers/usb/host/usb_host_hci.c delete mode 100644 bsp/imxrt1052-evk/drivers/usb/host/usb_host_hci.h delete mode 100644 bsp/imxrt1052-evk/drivers/usb/include/usb.h delete mode 100644 bsp/imxrt1052-evk/drivers/usb/include/usb_device_config.h delete mode 100644 bsp/imxrt1052-evk/drivers/usb/include/usb_ehci.h delete mode 100644 bsp/imxrt1052-evk/drivers/usb/include/usb_misc.h delete mode 100644 bsp/imxrt1052-evk/drivers/usb/include/usb_spec.h delete mode 100644 bsp/imxrt1052-evk/drivers/usb/phy/usb_phy.c delete mode 100644 bsp/imxrt1052-evk/drivers/usb/phy/usb_phy.h delete mode 100644 bsp/imxrt1052-evk/project.ewd delete mode 100644 bsp/imxrt1052-evk/project.ewp delete mode 100644 bsp/imxrt1052-evk/project.eww delete mode 100644 bsp/imxrt1052-evk/project.uvoptx delete mode 100644 bsp/imxrt1052-evk/project.uvprojx delete mode 100644 bsp/imxrt1052-evk/rtconfig.h delete mode 100644 bsp/imxrt1052-evk/rtconfig.py delete mode 100644 bsp/imxrt1052-evk/template.ewp delete mode 100644 bsp/imxrt1052-evk/template.uvoptx delete mode 100644 bsp/imxrt1052-evk/template.uvprojx delete mode 100644 bsp/imxrt1052-evk/xip/SConscript delete mode 100644 bsp/imxrt1052-evk/xip/fsl_flexspi_nor_boot.c delete mode 100644 bsp/imxrt1052-evk/xip/fsl_flexspi_nor_boot.h delete mode 100644 bsp/imxrt1052-evk/xip/fsl_flexspi_nor_flash.c delete mode 100644 bsp/imxrt1052-evk/xip/fsl_flexspi_nor_flash.h diff --git a/bsp/imxrt1052-evk/.config b/bsp/imxrt1052-evk/.config deleted file mode 100644 index 88643d85b4..0000000000 --- a/bsp/imxrt1052-evk/.config +++ /dev/null @@ -1,447 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -CONFIG_RT_ALIGN_SIZE=4 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_DEBUG=y -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_DEBUG_INIT=0 -CONFIG_RT_DEBUG_THREAD=0 -CONFIG_RT_USING_HOOK=y -CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -# CONFIG_RT_USING_MEMPOOL is not set -CONFIG_RT_USING_MEMHEAP=y -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_SMALL_MEM is not set -# CONFIG_RT_USING_SLAB is not set -CONFIG_RT_USING_MEMHEAP_AS_HEAP=y -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -# CONFIG_RT_USING_MODULE is not set -CONFIG_ARCH_ARM=y -CONFIG_ARCH_ARM_CORTEX_M=y -CONFIG_ARCH_ARM_CORTEX_M7=y - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 - -# -# C++ features -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Command shell -# -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_CMD_SIZE=80 -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set -CONFIG_FINSH_ARG_MAX=10 - -# -# Device virtual file system -# -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 -CONFIG_DFS_FD_MAX=4 -CONFIG_RT_USING_DFS_ELMFAT=y - -# -# elm-chan's FatFs, Generic FAT Filesystem Module -# -CONFIG_RT_DFS_ELM_CODE_PAGE=437 -CONFIG_RT_DFS_ELM_WORD_ACCESS=y -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -CONFIG_RT_DFS_ELM_USE_LFN_3=y -CONFIG_RT_DFS_ELM_USE_LFN=3 -CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=2 -CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 -# CONFIG_RT_DFS_ELM_USE_ERASE is not set -CONFIG_RT_DFS_ELM_REENTRANT=y -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_NET is not set -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_UFFS is not set -# CONFIG_RT_USING_DFS_JFFS2 is not set -# CONFIG_RT_USING_DFS_NFS is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_SERIAL_USING_DMA=y -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y -CONFIG_RT_USING_I2C_BITOPS=y -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RTC_SYNC_USING_NTP is not set -CONFIG_RT_USING_SDIO=y -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_MSD is not set -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_W25QXX is not set -# CONFIG_RT_USING_GD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_AUDIO is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# POSIX layer and C standard library -# -CONFIG_RT_USING_LIBC=y -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_POSIX is not set - -# -# Network stack -# - -# -# light weight TCP/IP stack -# -CONFIG_RT_USING_LWIP=y -# CONFIG_RT_USING_LWIP141 is not set -CONFIG_RT_USING_LWIP202=y -# CONFIG_RT_USING_LWIP_IPV6 is not set -# CONFIG_RT_LWIP_IGMP is not set -CONFIG_RT_LWIP_ICMP=y -# CONFIG_RT_LWIP_SNMP is not set -CONFIG_RT_LWIP_DNS=y -CONFIG_RT_LWIP_DHCP=y -CONFIG_IP_SOF_BROADCAST=1 -CONFIG_IP_SOF_BROADCAST_RECV=1 - -# -# Static IPv4 Address -# -CONFIG_RT_LWIP_IPADDR="192.168.1.30" -CONFIG_RT_LWIP_GWADDR="192.168.1.1" -CONFIG_RT_LWIP_MSKADDR="255.255.255.0" -CONFIG_RT_LWIP_UDP=y -CONFIG_RT_LWIP_TCP=y -# CONFIG_RT_LWIP_RAW is not set -# CONFIG_RT_LWIP_PPP is not set -CONFIG_RT_MEMP_NUM_NETCONN=8 -CONFIG_RT_LWIP_PBUF_NUM=16 -CONFIG_RT_LWIP_RAW_PCB_NUM=4 -CONFIG_RT_LWIP_UDP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_SEG_NUM=40 -CONFIG_RT_LWIP_TCP_SND_BUF=8196 -CONFIG_RT_LWIP_TCP_WND=8196 -CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 -CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 -CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 -# CONFIG_LWIP_NO_RX_THREAD is not set -# CONFIG_LWIP_NO_TX_THREAD is not set -CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 -CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 -CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 -# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set -CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 -CONFIG_SO_REUSE=1 -CONFIG_LWIP_SO_RCVTIMEO=1 -CONFIG_LWIP_SO_SNDTIMEO=1 -CONFIG_LWIP_SO_RCVBUF=1 -# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set -CONFIG_LWIP_NETIF_LOOPBACK=0 - -# -# Modbus master and slave stack -# -# CONFIG_RT_USING_MODBUS is not set -# CONFIG_LWIP_USING_DHCPD is not set - -# -# VBUS(Virtual Software BUS) -# -# CONFIG_RT_USING_VBUS is not set - -# -# Utilities -# -# CONFIG_RT_USING_LOGTRACE is not set -# CONFIG_RT_USING_RYM is not set - -# -# ARM CMSIS -# -# CONFIG_RT_USING_CMSIS_OS is not set -# CONFIG_RT_USING_RTT_CMSIS is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_NANOPB is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_ONENET is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_libsodium is not set -# CONFIG_PKG_USING_TINYCRYPT is not set - -# -# language packages -# -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set - -# -# multimedia packages -# -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set - -# -# system packages -# - -# -# RT-Thread GUI Engine -# -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_GUIENGINE_V200 is not set -# CONFIG_PKG_USING_GUIENGINE_LATEST_VERSION is not set -# CONFIG_GUIENGINE_IMAGE_LODEPNG is not set -# CONFIG_GUIENGINE_IMAGE_PNG is not set -# CONFIG_PKG_USING_PERSIMMON is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FAL is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_STM32F4_HAL is not set -# CONFIG_PKG_USING_STM32F4_DRIVERS is not set - -# -# miscellaneous packages -# -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_DSTR is not set - -# -# sample package -# -# CONFIG_PKG_USING_SAMPLES is not set - -# -# example package: hello -# -# CONFIG_PKG_USING_HELLO is not set - -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_MDNS is not set -# CONFIG_PKG_USING_UPNP is not set -# CONFIG_PKG_USING_WLAN_WICED_SRC is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RT_AT is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -CONFIG_SOC_IMXRT1052=y -CONFIG_BOARD_USING_HYPERFLASH=y -# CONFIG_BOARD_USING_QSPIFLASH is not set -CONFIG_BOARD_RT1050_EVK=y -# CONFIG_BOARD_RT1050_FIRE is not set -# CONFIG_BOARD_RT1050_ShareBoard is not set -# CONFIG_BOARD_RT1050_ATK is not set -# CONFIG_BOARD_RT1050_SeeedStudio is not set - -# -# RT1050 Bsp Config -# - -# -# Select uart drivers -# -CONFIG_RT_USING_UART1=y -# CONFIG_RT_USING_UART2 is not set -# CONFIG_RT_USING_UART3 is not set -# CONFIG_RT_USING_UART4 is not set -# CONFIG_RT_USING_UART5 is not set -# CONFIG_RT_USING_UART6 is not set -# CONFIG_RT_USING_UART7 is not set -# CONFIG_RT_USING_UART8 is not set - -# -# Select spi bus and dev drivers -# -CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD1=y -# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD0 is not set -# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2 is not set -# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2PFD2 is not set -CONFIG_LPSPI_CLK_SOURCE=0 -CONFIG_LPSPI_CLK_SOURCE_DIVIDER=8 -# CONFIG_RT_USING_SPIBUS1 is not set -# CONFIG_RT_USING_SPIBUS2 is not set -# CONFIG_RT_USING_SPIBUS3 is not set -CONFIG_RT_USING_SPIBUS4=y -CONFIG_LPSPI4_SCK_GPIO_1=y -# CONFIG_LPSPI4_SCK_GPIO_2 is not set -CONFIG_LPSPI4_SDO_GPIO_1=y -# CONFIG_LPSPI4_SDO_GPIO_2 is not set -CONFIG_LPSPI4_SDI_GPIO_1=y -# CONFIG_LPSPI4_SDI_GPIO_2 is not set -# CONFIG_RT_USING_SPI_FLASH is not set - -# -# Select iic bus drivers -# -CONFIG_RT_USING_HW_I2C1=y -CONFIG_HW_I2C1_BADURATE_100kHZ=y -# CONFIG_HW_I2C1_BADURATE_400kHZ is not set -# CONFIG_RT_USING_HW_I2C2 is not set -# CONFIG_RT_USING_HW_I2C3 is not set -# CONFIG_RT_USING_HW_I2C4 is not set - -# -# Select lcd driver -# - -# -# Notice: Evk Board para: 480*272 4 4 8 2 40 10 106 45 -# -CONFIG_RT_USING_LCD=y -CONFIG_LCD_WIDTH=480 -CONFIG_LCD_HEIGHT=272 -CONFIG_LCD_HFP=4 -CONFIG_LCD_VFP=4 -CONFIG_LCD_HBP=8 -CONFIG_LCD_VBP=2 -CONFIG_LCD_HSW=40 -CONFIG_LCD_VSW=10 -CONFIG_LCD_BL_PIN=106 -CONFIG_LCD_RST_PIN=45 -CONFIG_RT_USING_SDRAM=y -CONFIG_RT_USING_RTC_HP=y diff --git a/bsp/imxrt1052-evk/Kconfig b/bsp/imxrt1052-evk/Kconfig deleted file mode 100644 index f5d321e667..0000000000 --- a/bsp/imxrt1052-evk/Kconfig +++ /dev/null @@ -1,463 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" - -config SOC_IMXRT1052 - bool - select ARCH_ARM_CORTEX_M7 - default y - -config BOARD_USING_HYPERFLASH - bool - default n -config BOARD_USING_QSPIFLASH - bool - default n - -# RT1050 board select! -choice - prompt "RT1050 Board select" - default BOARD_RT1050_EVK - config BOARD_RT1050_EVK - bool "RT1050_EVK" - select BOARD_USING_HYPERFLASH - config BOARD_RT1050_FIRE - bool "RT1050_FIRE" - select BOARD_USING_QSPIFLASH - config BOARD_RT1050_ShareBoard - bool "RT1050_ShareBoard" - select BOARD_USING_QSPIFLASH - config BOARD_RT1050_ATK - bool "RT1050_ATK" - select BOARD_USING_QSPIFLASH - config BOARD_RT1050_SeeedStudio - bool "RT1050_SeeedStudio" - select BOARD_USING_HYPERFLASH -endchoice - -menu "RT1050 Bsp Config" - -menu "Select uart drivers" - config RT_USING_UART1 - bool "Using uart1" - select RT_USING_SERIAL - default y - config RT_USING_UART2 - bool "Using uart2" - select RT_USING_SERIAL - default n - config RT_USING_UART3 - bool "Using uart3" - select RT_USING_SERIAL - default n -if !BOARD_RT1050_SeeedStudio - config RT_USING_UART4 - bool "Using uart4" - select RT_USING_SERIAL - default n - config RT_USING_UART5 - bool "Using uart5" - select RT_USING_SERIAL - default n - config RT_USING_UART6 - bool "Using uart6" - select RT_USING_SERIAL - default n -endif -if !BOARD_RT1050_ATK && !BOARD_RT1050_SeeedStudio - config RT_USING_UART7 - bool "Using uart7" - select RT_USING_SERIAL - default n -endif - config RT_USING_UART8 - bool "Using uart8" - select RT_USING_SERIAL - default n -endmenu - -menu "Select spi bus and dev drivers" - choice - prompt "SPI bus clock source" - default LPSPI_CLK_SOURCE_FROM_PLL3PFD1 - - config LPSPI_CLK_SOURCE_FROM_PLL3PFD1 - bool "PLL3PFD1" - config LPSPI_CLK_SOURCE_FROM_PLL3PFD0 - bool "PLL3PFD0" - config LPSPI_CLK_SOURCE_FROM_PLL2 - bool "PLL2" - config LPSPI_CLK_SOURCE_FROM_PLL2PFD2 - bool "PLL2PFD2" - endchoice - config LPSPI_CLK_SOURCE - int - default 0 if LPSPI_CLK_SOURCE_FROM_PLL3PFD1 - default 1 if LPSPI_CLK_SOURCE_FROM_PLL3PFD0 - default 2 if LPSPI_CLK_SOURCE_FROM_PLL2 - default 3 if LPSPI_CLK_SOURCE_FROM_PLL2PFD2 - - config LPSPI_CLK_SOURCE_DIVIDER - int "SPI bus clock source divider" - range 1 8 - default 8 -if !BOARD_RT1050_SeeedStudio - config RT_USING_SPIBUS1 - bool "Using spi1 bus" - select RT_USING_SPI - default n - choice - prompt "spi1 bus sck io choice" - default LPSPI1_SCK_GPIO_1 - depends on RT_USING_SPIBUS1 - config LPSPI1_SCK_GPIO_1 - bool "GPIO_EMC_27" - config LPSPI1_SCK_GPIO_2 - bool "GPIO_SD_B0_00" - endchoice - choice - prompt "spi1 bus sdo io choice" - default LPSPI1_SDO_GPIO_1 - depends on RT_USING_SPIBUS1 - config LPSPI1_SDO_GPIO_1 - bool "GPIO_EMC_28" - config LPSPI1_SDO_GPIO_2 - bool "GPIO_SD_B0_02" - endchoice - choice - prompt "spi1 bus sdi io choice" - default LPSPI1_SDI_GPIO_1 - depends on RT_USING_SPIBUS1 - config LPSPI1_SDI_GPIO_1 - bool "GPIO_EMC_29" - config LPSPI1_SDI_GPIO_2 - bool "GPIO_SD_B0_03" - endchoice - - config RT_USING_SPIBUS2 - bool "Using spi2 bus" - select RT_USING_SPI - default n - choice - prompt "spi2 bus sck io choice" - default LPSPI2_SCK_GPIO_1 - depends on RT_USING_SPIBUS2 - config LPSPI2_SCK_GPIO_1 - bool "GPIO_SD_B1_07" - config LPSPI2_SCK_GPIO_2 - bool "GPIO_EMC_00" - endchoice - choice - prompt "spi2 bus sdo io choice" - default LPSPI2_SDO_GPIO_1 - depends on RT_USING_SPIBUS2 - config LPSPI2_SDO_GPIO_1 - bool "GPIO_SD_B1_08" - config LPSPI2_SDO_GPIO_2 - bool "GPIO_EMC_02" - endchoice - choice - prompt "spi2 bus sdi io choice" - default LPSPI2_SDI_GPIO_1 - depends on RT_USING_SPIBUS2 - config LPSPI2_SDI_GPIO_1 - bool "GPIO_SD_B1_09" - config LPSPI2_SDI_GPIO_2 - bool "GPIO_EMC_03" - endchoice -endif - config RT_USING_SPIBUS3 - bool "Using spi3 bus" - select RT_USING_SPI - default n - choice - prompt "spi3 bus sck io choice" - default LPSPI3_SCK_GPIO_1 - depends on RT_USING_SPIBUS3 - config LPSPI3_SCK_GPIO_1 - bool "GPIO_AD_B1_15" - config LPSPI3_SCK_GPIO_2 - bool "GPIO_AD_B0_00" - depends on !BOARD_RT1050_SeeedStudio - endchoice - choice - prompt "spi3 bus sdo io choice" - default LPSPI3_SDO_GPIO_1 - depends on RT_USING_SPIBUS3 - config LPSPI3_SDO_GPIO_1 - bool "GPIO_AD_B1_14" - config LPSPI3_SDO_GPIO_2 - bool "GPIO_AD_B0_01" - depends on !BOARD_RT1050_SeeedStudio - endchoice - choice - prompt "spi3 bus sdi io choice" - default LPSPI3_SDI_GPIO_1 - depends on RT_USING_SPIBUS3 - config LPSPI3_SDI_GPIO_1 - bool "GPIO_AD_B1_13" - config LPSPI3_SDI_GPIO_2 - bool "GPIO_AD_B0_02" - depends on !BOARD_RT1050_SeeedStudio - endchoice - - config RT_USING_SPIBUS4 - bool "Using spi4 bus" - select RT_USING_SPI - default y - choice - prompt "spi4 bus sck io choice" - default LPSPI4_SCK_GPIO_1 - depends on RT_USING_SPIBUS4 - config LPSPI4_SCK_GPIO_1 - bool "GPIO_B0_03" - depends on !BOARD_RT1050_SeeedStudio - config LPSPI4_SCK_GPIO_2 - bool "GPIO_B1_07" - endchoice - choice - prompt "spi4 bus sdo io choice" - default LPSPI4_SDO_GPIO_1 - depends on RT_USING_SPIBUS4 - config LPSPI4_SDO_GPIO_1 - bool "GPIO_B0_02" - depends on !BOARD_RT1050_SeeedStudio - config LPSPI4_SDO_GPIO_2 - bool "GPIO_B1_06" - endchoice - choice - prompt "spi4 bus sdi io choice" - default LPSPI4_SDI_GPIO_1 - depends on RT_USING_SPIBUS4 - config LPSPI4_SDI_GPIO_1 - bool "GPIO_B0_01" - depends on !BOARD_RT1050_SeeedStudio - config LPSPI4_SDI_GPIO_2 - bool "GPIO_B1_05" - endchoice - - config RT_USING_SPI_FLASH - bool "Using spi flash with sfud" - default n - select RT_USING_SPI - select RT_USING_SFUD - select RT_USING_PIN - choice - prompt "SPI flash using spibus" - default SPI_FLASH_USING_SPIBUS4 - depends on RT_USING_SPI_FLASH - - config SPI_FLASH_USING_SPIBUS1 - bool "spi1" - select RT_USING_SPIBUS1 - config SPI_FLASH_USING_SPIBUS2 - bool "spi2" - select RT_USING_SPIBUS2 - config SPI_FLASH_USING_SPIBUS3 - bool "spi3" - select RT_USING_SPIBUS3 - config SPI_FLASH_USING_SPIBUS4 - bool "spi4" - select RT_USING_SPIBUS4 - endchoice - config SPI_FLASH_USING_SPIBUS_NAME - string - default "spi1" if SPI_FLASH_USING_SPIBUS1 - default "spi2" if SPI_FLASH_USING_SPIBUS2 - default "spi3" if SPI_FLASH_USING_SPIBUS3 - default "spi4" if SPI_FLASH_USING_SPIBUS4 - - config SPI_FLASH_NAME - string "SPI flash device name" - default "flash0" - depends on RT_USING_SPI_FLASH - - config SPI_FLASH_USING_CS_PIN - int "SPI flash cs pin index" - default 79 - range 1 127 - depends on RT_USING_SPI_FLASH -endmenu - -menu "Select iic bus drivers" - - config RT_USING_HW_I2C1 - bool "using hardware i2c1" - select RT_USING_I2C - default y - choice - prompt "i2c1 bus badurate choice" - default HW_I2C1_BADURATE_100kHZ - depends on RT_USING_HW_I2C1 - config HW_I2C1_BADURATE_100kHZ - bool "100kHZ" - config HW_I2C1_BADURATE_400kHZ - bool "400kHZ" - endchoice -if !BOARD_RT1050_SeeedStudio - config RT_USING_HW_I2C2 - bool "using hardware i2c2" - select RT_USING_I2C - default n - choice - prompt "i2c2 bus badurate choice" - default HW_I2C2_BADURATE_100kHZ - depends on RT_USING_HW_I2C2 - config HW_I2C2_BADURATE_100kHZ - bool "100kHZ" - config HW_I2C2_BADURATE_400kHZ - bool "400kHZ" - endchoice -endif - config RT_USING_HW_I2C3 - bool "using hardware i2c3" - select RT_USING_I2C - default n - choice - prompt "i2c3 bus badurate choice" - default HW_I2C3_BADURATE_100kHZ - depends on RT_USING_HW_I2C3 - config HW_I2C3_BADURATE_100kHZ - bool "100kHZ" - config HW_I2C3_BADURATE_400kHZ - bool "400kHZ" - endchoice - - config RT_USING_HW_I2C4 - bool "using hardware i2c4" - select RT_USING_I2C - default n - choice - prompt "i2c4 bus badurate choice" - default HW_I2C4_BADURATE_100kHZ - depends on RT_USING_HW_I2C4 - config HW_I2C4_BADURATE_100kHZ - bool "100kHZ" - config HW_I2C4_BADURATE_400kHZ - bool "400kHZ" - endchoice - -endmenu - -menu "Select lcd driver" - if RT_USING_LCD && BOARD_RT1050_EVK - comment "Notice: Evk Board para: 480*272 4 4 8 2 40 10 106 45" - endif - - if RT_USING_LCD && BOARD_RT1050_ShareBoard - comment "Notice: ShareBoard Board para: 800*480 4 4 8 2 40 10 58 45" - endif - - if RT_USING_LCD && BOARD_RT1050_FIRE - comment "Notice: Fire Board para: 800*480 4 4 8 2 40 10 58 45" - endif - - if RT_USING_LCD && BOARD_RT1050_ATK - comment "Notice: ATK Board para: 480*272 4 4 8 2 40 10 109 45" - endif - - if RT_USING_LCD && BOARD_RT1050_SeeedStudio - comment "Notice: SeeedStudio Board para: 480*272 4 4 8 2 40 10 127 45" - endif - - config RT_USING_LCD - bool "Using lcd" - default n - - config LCD_WIDTH - int "Width pixel num" - default 480 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) - default 800 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) - depends on RT_USING_LCD - config LCD_HEIGHT - int "Height pixel num" - default 272 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) - default 480 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) - depends on RT_USING_LCD - config LCD_HFP - int "HFP" - default 4 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) - default 4 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) - depends on RT_USING_LCD - config LCD_VFP - int "VFP" - default 4 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) - default 4 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) - depends on RT_USING_LCD - config LCD_HBP - int "HBP" - default 8 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) - default 8 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) - depends on RT_USING_LCD - config LCD_VBP - int "VBP" - default 2 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) - default 2 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) - depends on RT_USING_LCD - config LCD_HSW - int "HSW" - default 40 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) - default 40 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) - depends on RT_USING_LCD - config LCD_VSW - int "VSW" - default 10 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) - default 10 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) - depends on RT_USING_LCD - config LCD_BL_PIN - int "Backlight pin index" - default 127 if BOARD_RT1050_SeeedStudio - default 109 if BOARD_RT1050_ATK - default 106 if BOARD_RT1050_EVK - default 58 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) - depends on RT_USING_LCD - config LCD_RST_PIN - int "Reset pin index" - default 45 if (BOARD_RT1050_EVK || BOARD_RT1050_ATK || BOARD_RT1050_SeeedStudio) - default 45 if (BOARD_RT1050_FIRE || BOARD_RT1050_ShareBoard) - depends on RT_USING_LCD -endmenu - -#menu "Select SDRAM driver" - config RT_USING_SDRAM - bool "Using sdram" - default y -#endmenu - -#menu "Select RTC driver" - config RT_USING_RTC_HP - bool "Using hp rtc" - select RT_USING_RTC - select RT_USING_LIBC - default n -#endmenu - -if RT_USING_USB_DEVICE - choice - prompt "select usb device controller" - default RT_USING_EHCI0_AS_DEVICE - - config RT_USING_EHCI0_AS_DEVICE - bool "set EHCI0 as device" - config RT_USING_EHCI1_AS_DEVICE - bool "set EHCI1 as device" - endchoice -endif - -endmenu diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/arm_common_tables.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index dfea7460e9..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,121 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_common_tables.h - * Description: Extern declaration for common tables - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) -#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) -#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) -#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) -#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) -#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) -#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) -#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/arm_const_structs.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 80a3e8bbe7..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_const_structs.h - * Description: Constant structs that are initialized for user convenience. - * For example, some can be given as arguments to the arm_cfft_f32() function. - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/arm_math.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/arm_math.h deleted file mode 100644 index 4be7e8c848..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7226 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_math.h - * Description: Public header file for CMSIS DSP Library - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) - * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) - * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) - * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) - * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) - * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) - * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) - * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) - * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) - * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) - * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) - * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) - * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) - * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) - * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian) - * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian) - * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit) - * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions) - * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. - * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions. - * - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - ARM_MATH_ARMV8MxL: - * - * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library - * on ARMv8M Mainline target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. - * - * - __DSP_PRESENT: - * - * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions. - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MBL) - #include "core_armv8mbl.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MML) - #include "core_armv8mml.h" - #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) - #define ARM_MATH_DSP - #endif -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI - #define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined ( __CC_ARM ) - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __GNUC__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ICCARM__ ) - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#elif defined ( __TI_ARM__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE - -#elif defined ( __CSMC__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#elif defined ( __TASKING__ ) - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#if !defined (ARM_MATH_DSP) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#endif /* !defined (ARM_MATH_DSP) */ - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( - q31_t data); - - CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while ((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if (in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if (in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - CMSIS_INLINE __STATIC_INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if (x > 0) - { - posMax = (posMax - 1); - - if (x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if (x < negMin) - { - x = negMin; - } - } - return (x); - } -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#if !defined (ARM_MATH_DSP) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - - /* - * @brief C custom defined SMMLA for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( - int32_t x, - int32_t y, - int32_t sum) - { - return (sum + (int32_t) (((int64_t) x * y) >> 32)); - } - -#if 0 - /* - * @brief C custom defined PKHBT for unavailable DSP extension - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT( - uint32_t x, - uint32_t y, - uint32_t leftshift) - { - return ( ((x ) & 0x0000FFFFUL) | - ((y << leftshift) & 0xFFFF0000UL) ); - } - - /* - * @brief C custom defined PKHTB for unavailable DSP extension - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB( - uint32_t x, - uint32_t y, - uint32_t rightshift) - { - return ( ((x ) & 0xFFFF0000UL) | - ((y >> rightshift) & 0x0000FFFFUL) ); - } -#endif - -/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#endif /* !defined (ARM_MATH_DSP) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#if !defined (ARM_MATH_DSP) - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#if defined (ARM_MATH_DSP) - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - CMSIS_INLINE __STATIC_INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if (i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if ((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if (index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if (in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __GNUC__ ) - #define LOW_OPTIMIZATION_ENTER \ - __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __ICCARM__ ) - /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TI_ARM__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __CSMC__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TASKING__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_armcc.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_armcc.h deleted file mode 100644 index 1d6a5fbd5c..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_armcc.h +++ /dev/null @@ -1,814 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (ARM compiler V5) header file - * @version V5.0.2 - * @date 13. February 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ - (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) - #define __ARM_ARCH_6M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) - #define __ARM_ARCH_7M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) - #define __ARM_ARCH_7EM__ 1 -#endif - - /* __ARM_ARCH_8M_BASE__ not applicable */ - /* __ARM_ARCH_8M_MAIN__ not applicable */ - - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION __packed union -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_armclang.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_armclang.h deleted file mode 100644 index 2148297082..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_armclang.h +++ /dev/null @@ -1,1802 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file - * @version V5.0.3 - * @date 27. March 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#ifndef __ARM_COMPAT_H -#include /* Compatibility header for ARM Compiler 5 intrinsics */ -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); see arm_compat.h */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); see arm_compat.h */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -/* #define __get_FPSCR __builtin_arm_get_fpscr */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -/* #define __set_FPSCR __builtin_arm_set_fpscr */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory"); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __builtin_bswap32 - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_compiler.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_compiler.h deleted file mode 100644 index 0f703ff9f2..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_compiler.h +++ /dev/null @@ -1,353 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.0.2 - * @date 13. February 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * ARM Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * ARM Compiler 6 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - - #include - - /* CMSIS compiler control architecture macros */ - #if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__) - #ifndef __ARM_ARCH_6M__ - #define __ARM_ARCH_6M__ 1 - #endif - #elif (__CORE__ == __ARM7M__) - #ifndef __ARM_ARCH_7M__ - #define __ARM_ARCH_7M__ 1 - #endif - #elif (__CORE__ == __ARM7EM__) - #ifndef __ARM_ARCH_7EM__ - #define __ARM_ARCH_7EM__ 1 - #endif - #endif - - #ifndef __NO_RETURN - #define __NO_RETURN __noreturn - #endif - #ifndef __USED - #define __USED __root - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED __packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION __packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - __packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - // Workaround for missing __CLZ intrinsic in - // various versions of the IAR compilers. - // __IAR_FEATURE_CLZ__ should be defined by - // the compiler that supports __CLZ internally. - #if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__)) - __STATIC_INLINE uint32_t __CLZ(uint32_t data) - { - if (data == 0u) { return 32u; } - - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while ((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } - #endif - - -/* - * TI ARM Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_gcc.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_gcc.h deleted file mode 100644 index 05f7570394..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_gcc.h +++ /dev/null @@ -1,1979 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.0.2 - * @date 13. February 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -//{ -// __ASM volatile ("nop"); -//} -#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -//{ -// __ASM volatile ("wfi"); -//} -#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -//{ -// __ASM volatile ("wfe"); -//} -#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -//{ -// __ASM volatile ("sev"); -//} -#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_version.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_version.h deleted file mode 100644 index d458a6c859..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/cmsis_version.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_armv8mbl.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_armv8mbl.h deleted file mode 100644 index 13003e1cd6..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_armv8mbl.h +++ /dev/null @@ -1,1878 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mbl.h - * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MBL_H_GENERIC -#define __CORE_ARMV8MBL_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MBL - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MBL_H_DEPENDANT -#define __CORE_ARMV8MBL_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MBL_REV - #define __ARMv8MBL_REV 0x0000U - #warning "__ARMv8MBL_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MBL */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_armv8mml.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_armv8mml.h deleted file mode 100644 index 5c4d6f6ee1..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_armv8mml.h +++ /dev/null @@ -1,2902 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mml.h - * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MML_H_GENERIC -#define __CORE_ARMV8MML_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MML - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS ARMv8MML definitions */ -#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (81U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MML_H_DEPENDANT -#define __CORE_ARMV8MML_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MML_REV - #define __ARMv8MML_REV 0x0000U - #warning "__ARMv8MML_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm0.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm0.h deleted file mode 100644 index 2f63b68610..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,888 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)0x0U; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)0x0U; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index 5c6135802b..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,1021 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; - -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm23.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm23.h deleted file mode 100644 index b97fa9dd3f..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm23.h +++ /dev/null @@ -1,1878 +0,0 @@ -/**************************************************************************//** - * @file core_cm23.h - * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM23_H_GENERIC -#define __CORE_CM23_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M23 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ - __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (23U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM23_H_DEPENDANT -#define __CORE_CM23_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM23_REV - #define __CM23_REV 0x0000U - #warning "__CM23_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M23 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm3.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm3.h deleted file mode 100644 index 3c1f01f497..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1928 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (3U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm33.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm33.h deleted file mode 100644 index fab2f9a118..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm33.h +++ /dev/null @@ -1,2898 +0,0 @@ -/**************************************************************************//** - * @file core_cm33.h - * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM33_REV - #define __CM33_REV 0x0000U - #warning "__CM33_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm4.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm4.h deleted file mode 100644 index ad3bc27d58..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,2113 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (4U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm7.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm7.h deleted file mode 100644 index bf701fe8ef..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2655 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (7U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - register uint32_t ccsidr; - register uint32_t sets; - register uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_sc000.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_sc000.h deleted file mode 100644 index bd26eaa0db..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,1016 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_sc300.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_sc300.h deleted file mode 100644 index 780372a350..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1903 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/mpu_armv7.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/mpu_armv7.h deleted file mode 100644 index fb1a339bec..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/mpu_armv7.h +++ /dev/null @@ -1,182 +0,0 @@ -/****************************************************************************** - * @file mpu_armv7.h - * @brief CMSIS MPU API for ARMv7 MPU - * @version V5.0.2 - * @date 09. June 2017 - ******************************************************************************/ -/* - * Copyright (c) 2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ARM_MPU_ARMV7_H -#define ARM_MPU_ARMV7_H - -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) - -#define ARM_MPU_AP_NONE 0u -#define ARM_MPU_AP_PRIV 1u -#define ARM_MPU_AP_URO 2u -#define ARM_MPU_AP_FULL 3u -#define ARM_MPU_AP_PRO 5u -#define ARM_MPU_AP_RO 6u - -/** MPU Region Base Address Register Value -* -* \param Region The region to be configured, number 0 to 15. -* \param BaseAddress The base address for the region. -*/ -#define ARM_MPU_RBAR(Region, BaseAddress) ((BaseAddress & MPU_RBAR_ADDR_Msk) | (Region & MPU_RBAR_REGION_Msk) | (1UL << MPU_RBAR_VALID_Pos)) - -/** -* MPU Region Attribut and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ((DisableExec << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - ((AccessPermission << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - ((TypeExtField << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - ((IsShareable << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - ((IsCacheable << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - ((IsBufferable << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ - ((SubRegionDisable << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ - ((Size << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ - ((1UL << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk) - - -/** -* Struct for a single MPU Region -*/ -typedef struct _ARM_MPU_Region_t { - uint32_t RBAR; //!< The region base address register value (RBAR) - uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DSB(); - __ISB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable() -{ - __DSB(); - __ISB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - MPU->RNR = rnr; - MPU->RASR = 0u; -} - -/** Configure an MPU region. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) -{ - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) -{ - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Memcopy with strictly ordered memory access, e.g. for register targets. -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0u; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) -{ - orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(ARM_MPU_Region_t)/4u); -} - -#endif diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/tz_context.h b/bsp/imxrt1052-evk/Libraries/CMSIS/Include/tz_context.h deleted file mode 100644 index 0784d26cac..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/Include/tz_context.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2015-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------------- - * - * $Date: 21. September 2016 - * $Revision: V1.0 - * - * Project: TrustZone for ARMv8-M - * Title: Context Management for ARMv8-M TrustZone - * - * Version 1.0 - * Initial Release - *---------------------------------------------------------------------------*/ - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H diff --git a/bsp/imxrt1052-evk/Libraries/CMSIS/LICENSE.txt b/bsp/imxrt1052-evk/Libraries/CMSIS/LICENSE.txt deleted file mode 100644 index 8dada3edaf..0000000000 --- a/bsp/imxrt1052-evk/Libraries/CMSIS/LICENSE.txt +++ /dev/null @@ -1,201 +0,0 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. 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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 0.1 (2017-01-10) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file MIMXRT1052.h - * @version 0.1 - * @date 2017-01-10 - * @brief CMSIS Peripheral Access Layer for MIMXRT1052 - * - * CMSIS Peripheral Access Layer for MIMXRT1052 - */ - -#ifndef _MIMXRT1052_H_ -#define _MIMXRT1052_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0000U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 176 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */ - - /* Device specific interrupts */ - DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */ - DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */ - DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */ - DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */ - DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */ - DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */ - DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */ - DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */ - DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */ - DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */ - DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */ - DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */ - DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */ - DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */ - DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */ - DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */ - DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */ - CTI0_ERROR_IRQn = 17, /**< CTI0_Error */ - CTI1_ERROR_IRQn = 18, /**< CTI1_Error */ - CORE_IRQn = 19, /**< CorePlatform exception IRQ */ - LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */ - LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */ - LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */ - LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */ - LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */ - LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */ - LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */ - LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */ - LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */ - LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */ - LPI2C3_IRQn = 30, /**< LPI2C3 interrupt */ - LPI2C4_IRQn = 31, /**< LPI2C4 interrupt */ - LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */ - LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */ - LPSPI3_IRQn = 34, /**< LPSPI3 single interrupt vector for all sources */ - LPSPI4_IRQn = 35, /**< LPSPI4 single interrupt vector for all sources */ - CAN1_IRQn = 36, /**< CAN1 interrupt */ - CAN2_IRQn = 37, /**< CAN2 interrupt */ - FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */ - KPP_IRQn = 39, /**< Keypad nterrupt */ - TSC_DIG_IRQn = 40, /**< TSC interrupt */ - GPR_IRQ_IRQn = 41, /**< GPR interrupt */ - LCDIF_IRQn = 42, /**< LCDIF interrupt */ - CSI_IRQn = 43, /**< CSI interrupt */ - PXP_IRQn = 44, /**< PXP interrupt */ - WDOG2_IRQn = 45, /**< WDOG2 interrupt */ - SNVS_HP_WRAPPER_IRQn = 46, /**< SRTC Consolidated Interrupt. Non TZ */ - SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SRTC Security Interrupt. TZ */ - SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */ - CSU_IRQn = 49, /**< CSU interrupt */ - DCP_IRQn = 50, /**< DCP_IRQ interrupt */ - DCP_VMI_IRQn = 51, /**< DCP_VMI_IRQ interrupt */ - Reserved68_IRQn = 52, /**< Reserved interrupt */ - TRNG_IRQn = 53, /**< TRNG interrupt */ - SJC_IRQn = 54, /**< SJC interrupt */ - BEE_IRQn = 55, /**< BEE interrupt */ - SAI1_IRQn = 56, /**< SAI1 interrupt */ - SAI2_IRQn = 57, /**< SAI1 interrupt */ - SAI3_RX_IRQn = 58, /**< SAI3 interrupt */ - SAI3_TX_IRQn = 59, /**< SAI3 interrupt */ - SPDIF_IRQn = 60, /**< SPDIF interrupt */ - ANATOP_EVENT0_IRQn = 61, /**< ANATOP interrupt */ - ANATOP_EVENT1_IRQn = 62, /**< ANATOP interrupt */ - ANATOP_TAMP_LOW_HIGH_IRQn = 63, /**< ANATOP interrupt */ - ANATOP_TEMP_PANIC_IRQn = 64, /**< ANATOP interrupt */ - USB_PHY1_IRQn = 65, /**< USBPHY (UTMI0), Interrupt */ - USB_PHY2_IRQn = 66, /**< USBPHY (UTMI0), Interrupt */ - ADC1_IRQn = 67, /**< ADC1 interrupt */ - ADC2_IRQn = 68, /**< ADC2 interrupt */ - DCDC_IRQn = 69, /**< DCDC interrupt */ - Reserved86_IRQn = 70, /**< Reserved interrupt */ - Reserved87_IRQn = 71, /**< Reserved interrupt */ - GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */ - GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */ - GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */ - GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */ - GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */ - GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */ - GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */ - GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */ - GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ - GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ - GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ - GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */ - GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ - GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */ - GPIO4_Combined_0_15_IRQn = 86, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */ - GPIO4_Combined_16_31_IRQn = 87, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */ - GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */ - GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */ - FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */ - FLEXIO2_IRQn = 91, /**< FLEXIO2 interrupt */ - WDOG1_IRQn = 92, /**< WDOG1 interrupt */ - RTWDOG_IRQn = 93, /**< RTWDOG interrupt */ - EWM_IRQn = 94, /**< EWM interrupt */ - CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */ - CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */ - GPC_IRQn = 97, /**< GPC interrupt */ - SRC_IRQn = 98, /**< SRC interrupt */ - Reserved115_IRQn = 99, /**< Reserved interrupt */ - GPT1_IRQn = 100, /**< GPT1 interrupt */ - GPT2_IRQn = 101, /**< GPT2 interrupt */ - PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */ - PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */ - PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */ - PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */ - PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */ - Reserved123_IRQn = 107, /**< Reserved interrupt */ - FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */ - SEMC_IRQn = 109, /**< Reserved interrupt */ - USDHC1_IRQn = 110, /**< USDHC1 interrupt */ - USDHC2_IRQn = 111, /**< USDHC2 interrupt */ - USB_OTG2_IRQn = 112, /**< USBO2 USB OTG2 */ - USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */ - ENET_IRQn = 114, /**< ENET interrupt */ - ENET_1588_Timer_IRQn = 115, /**< ENET_1588_Timer interrupt */ - XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */ - XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */ - ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */ - ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */ - ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */ - ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */ - PIT_IRQn = 122, /**< PIT interrupt */ - ACMP1_IRQn = 123, /**< ACMP interrupt */ - ACMP2_IRQn = 124, /**< ACMP interrupt */ - ACMP3_IRQn = 125, /**< ACMP interrupt */ - ACMP4_IRQn = 126, /**< ACMP interrupt */ - Reserved143_IRQn = 127, /**< Reserved interrupt */ - Reserved144_IRQn = 128, /**< Reserved interrupt */ - ENC1_IRQn = 129, /**< ENC1 interrupt */ - ENC2_IRQn = 130, /**< ENC2 interrupt */ - ENC3_IRQn = 131, /**< ENC3 interrupt */ - ENC4_IRQn = 132, /**< ENC4 interrupt */ - TMR1_IRQn = 133, /**< TMR1 interrupt */ - TMR2_IRQn = 134, /**< TMR2 interrupt */ - TMR3_IRQn = 135, /**< TMR3 interrupt */ - TMR4_IRQn = 136, /**< TMR4 interrupt */ - PWM2_0_IRQn = 137, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */ - PWM2_1_IRQn = 138, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */ - PWM2_2_IRQn = 139, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */ - PWM2_3_IRQn = 140, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */ - PWM2_FAULT_IRQn = 141, /**< PWM2 fault or reload error interrupt */ - PWM3_0_IRQn = 142, /**< PWM3 capture 0, compare 0, or reload 0 interrupt */ - PWM3_1_IRQn = 143, /**< PWM3 capture 1, compare 1, or reload 0 interrupt */ - PWM3_2_IRQn = 144, /**< PWM3 capture 2, compare 2, or reload 0 interrupt */ - PWM3_3_IRQn = 145, /**< PWM3 capture 3, compare 3, or reload 0 interrupt */ - PWM3_FAULT_IRQn = 146, /**< PWM3 fault or reload error interrupt */ - PWM4_0_IRQn = 147, /**< PWM4 capture 0, compare 0, or reload 0 interrupt */ - PWM4_1_IRQn = 148, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */ - PWM4_2_IRQn = 149, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */ - PWM4_3_IRQn = 150, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */ - PWM4_FAULT_IRQn = 151, /**< PWM4 fault or reload error interrupt */ - Reserved168_IRQn = 152, /**< Reserved interrupt */ - Reserved169_IRQn = 153, /**< Reserved interrupt */ - Reserved170_IRQn = 154, /**< Reserved interrupt */ - Reserved171_IRQn = 155, /**< Reserved interrupt */ - Reserved172_IRQn = 156, /**< Reserved interrupt */ - Reserved173_IRQn = 157, /**< Reserved interrupt */ - SJC_ARM_DEBUG_IRQn = 158, /**< SJC ARM debug interrupt */ - NMI_WAKEUP_IRQn = 159 /**< NMI wake up */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M7 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */ -#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */ -#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */ -#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ -#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ - -#include "core_cm7.h" /* Core Peripheral Access Layer */ -#include "system_MIMXRT1052.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup edma_request - * @{ */ - -/******************************************************************************* - * Definitions -*******************************************************************************/ - -/*! - * @brief Enumeration for the DMA0 hardware request - * - * Defines the enumeration for the DMA0 hardware request collections. - */ -typedef enum _dma_request_source -{ - kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 */ - kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 */ - kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */ - kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */ - kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */ - kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */ - kDmaRequestMuxLPUART5Tx = 6|0x100U, /**< LPUART5 Transmit */ - kDmaRequestMuxLPUART5Rx = 7|0x100U, /**< LPUART5 Receive */ - kDmaRequestMuxLPUART7Tx = 8|0x100U, /**< LPUART7 Transmit */ - kDmaRequestMuxLPUART7Rx = 9|0x100U, /**< LPUART7 Receive */ - kDmaRequestMuxCSI = 12|0x100U, /**< CSI */ - kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */ - kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */ - kDmaRequestMuxLPSPI3Rx = 15|0x100U, /**< LPSPI3 Receive */ - kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */ - kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */ - kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */ - kDmaRequestMuxSai1Rx = 19|0x100U, /**< Sai1 Receive */ - kDmaRequestMuxSai1Tx = 20|0x100U, /**< Sai1 Transmit */ - kDmaRequestMuxSai2Rx = 21|0x100U, /**< Sai2 Receive */ - kDmaRequestMuxSai2Tx = 22|0x100U, /**< Sai2 Transmit */ - kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */ - kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */ - kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */ - kDmaRequestMuxACMP2 = 26|0x100U, /**< ACMP2 */ - kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */ - kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */ - kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */ - kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR1 Request 1 */ - kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */ - kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */ - kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */ - kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */ - kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */ - kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */ - kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */ - kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */ - kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, /**< FlexPWM3 Capture sub-module0 */ - kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U, /**< FlexPWM3 Capture sub-module1 */ - kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, /**< FlexPWM3 Capture sub-module2 */ - kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, /**< FlexPWM3 Capture sub-module3 */ - kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U, /**< FlexPWM3 Value sub-module0 */ - kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U, /**< FlexPWM3 Value sub-module1 */ - kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, /**< FlexPWM3 Value sub-module2 */ - kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, /**< FlexPWM3 Value sub-module3 */ - kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< QTIMER1 Capture timer 0 */ - kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< QTIMER1 Capture timer 1 */ - kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< QTIMER1 Capture timer 2 */ - kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< QTIMER1 Capture timer 3 */ - kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< QTIMER1 cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< QTIMER1 cmpld1 in timer 1 or cmpld2 in timer 0 */ - kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< QTIMER1 cmpld1 in timer 2 or cmpld2 in timer 3 */ - kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< QTIMER1 cmpld1 in timer 3 or cmpld2 in timer 2 */ - kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< QTIMER3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer0Cmpld2Timer1 = 57|0x100U, /**< QTIMER3 capture timer 1, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer0Cmpld2Timer1 = 58|0x100U, /**< QTIMER3 capture timer 2, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer0Cmpld2Timer1 = 59|0x100U, /**< QTIMER3 capture timer 3, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 */ - kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 */ - kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */ - kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */ - kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */ - kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */ - kDmaRequestMuxLPUART6Tx = 70|0x100U, /**< LPUART6 Transmit */ - kDmaRequestMuxLPUART6Rx = 71|0x100U, /**< LPUART6 Receive */ - kDmaRequestMuxLPUART8Tx = 72|0x100U, /**< LPUART8 Transmit */ - kDmaRequestMuxLPUART8Rx = 73|0x100U, /**< LPUART8 Receive */ - kDmaRequestMuxPxp = 75|0x100U, /**< PXP */ - kDmaRequestMuxLCDIF = 76|0x100U, /**< LCDIF */ - kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */ - kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */ - kDmaRequestMuxLPSPI4Rx = 79|0x100U, /**< LPSPI4 Receive */ - kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */ - kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */ - kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */ - kDmaRequestMuxSai3Rx = 83|0x100U, /**< Sai3 Receive */ - kDmaRequestMuxSai3Tx = 84|0x100U, /**< Sai3 Transmit */ - kDmaRequestMuxSpdifRx = 85|0x100U, /**< Spdif Receive */ - kDmaRequestMuxSpdifTx = 86|0x100U, /**< Spdif Transmit */ - kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */ - kDmaRequestMuxACMP3 = 89|0x100U, /**< ACMP3 */ - kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */ - kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< Enet Timer0 */ - kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< Enet Timer1 */ - kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */ - kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */ - kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */ - kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */ - kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */ - kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */ - kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, /**< FlexPWM2 Value sub-module0 */ - kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, /**< FlexPWM2 Value sub-module1 */ - kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U, /**< FlexPWM2 Value sub-module2 */ - kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, /**< FlexPWM2 Value sub-module3 */ - kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, /**< FlexPWM4 Capture sub-module0 */ - kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, /**< FlexPWM4 Capture sub-module1 */ - kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U, /**< FlexPWM4 Capture sub-module2 */ - kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, /**< FlexPWM4 Capture sub-module3 */ - kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U, /**< FlexPWM4 Value sub-module0 */ - kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, /**< FlexPWM4 Value sub-module1 */ - kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U, /**< FlexPWM4 Value sub-module2 */ - kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, /**< FlexPWM4 Value sub-module3 */ - kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< QTIMER2 Capture timer 0 */ - kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< QTIMER2 Capture timer 1 */ - kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< QTIMER2 Capture timer 2 */ - kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< QTIMER2 Capture timer 3 */ - kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< QTIMER2 cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< QTIMER2 cmpld1 in timer 1 or cmpld2 in timer 0 */ - kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< QTIMER2 cmpld1 in timer 2 or cmpld2 in timer 3 */ - kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< QTIMER2 cmpld1 in timer 3 or cmpld2 in timer 2 */ - kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< QTIMER4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer0Cmpld2Timer1 = 121|0x100U, /**< QTIMER4 capture timer 1, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer0Cmpld2Timer1 = 122|0x100U, /**< QTIMER4 capture timer 2, cmpld1 in timer 0 or cmpld2 in timer 1 */ - kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer0Cmpld2Timer1 = 123|0x100U, /**< QTIMER4 capture timer 3, cmpld1 in timer 0 or cmpld2 in timer 1 */ -} dma_request_source_t; - -/* @} */ - -/*! - * @addtogroup iomuxc_pads - * @{ */ - -/******************************************************************************* - * Definitions -*******************************************************************************/ - -/*! - * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD - * - * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. - */ -typedef enum _iomuxc_sw_mux_ctl_pad -{ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */ - kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */ -} iomuxc_sw_mux_ctl_pad_t; - -/* @} */ - -/*! - * @addtogroup iomuxc_pads - * @{ */ - -/******************************************************************************* - * Definitions -*******************************************************************************/ - -/*! - * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD - * - * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. - */ -typedef enum _iomuxc_sw_pad_ctl_pad -{ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */ - kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */ -} iomuxc_sw_pad_ctl_pad_t; - -/* @} */ - -/*! - * @brief Enumeration for the IOMUXC select input - * - * Defines the enumeration for the IOMUXC select input collections. - */ -typedef enum _iomuxc_select_input -{ - kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */ - kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */ - kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */ - kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */ - kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */ - kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U, /**< IOMUXC select input index */ - kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U, /**< IOMUXC select input index */ - kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U, /**< IOMUXC select input index */ - kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U, /**< IOMUXC select input index */ - kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U, /**< IOMUXC select input index */ - kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U, /**< IOMUXC select input index */ - kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U, /**< IOMUXC select input index */ - kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U, /**< IOMUXC select input index */ - kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U, /**< IOMUXC select input index */ - kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U, /**< IOMUXC select input index */ - kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U, /**< IOMUXC select input index */ - kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U, /**< IOMUXC select input index */ - kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U, /**< IOMUXC select input index */ - kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U, /**< IOMUXC select input index */ - kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */ - kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U, /**< IOMUXC select input index */ - kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */ - kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U, /**< IOMUXC select input index */ - kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U, /**< IOMUXC select input index */ - kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U, /**< IOMUXC select input index */ - kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U, /**< IOMUXC select input index */ - kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U, /**< IOMUXC select input index */ - kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U, /**< IOMUXC select input index */ - kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U, /**< IOMUXC select input index */ - kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U, /**< IOMUXC select input index */ - kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U, /**< IOMUXC select input index */ - kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U, /**< IOMUXC select input index */ - kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U, /**< IOMUXC select input index */ - kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U, /**< IOMUXC select input index */ - kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U, /**< IOMUXC select input index */ - kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U, /**< IOMUXC select input index */ - kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U, /**< IOMUXC select input index */ - kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U, /**< IOMUXC select input index */ - kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U, /**< IOMUXC select input index */ - kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U, /**< IOMUXC select input index */ - kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U, /**< IOMUXC select input index */ - kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U, /**< IOMUXC select input index */ - kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U, /**< IOMUXC select input index */ - kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U, /**< IOMUXC select input index */ - kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U, /**< IOMUXC select input index */ - kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U, /**< IOMUXC select input index */ - kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U, /**< IOMUXC select input index */ - kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U, /**< IOMUXC select input index */ - kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U, /**< IOMUXC select input index */ - kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U, /**< IOMUXC select input index */ - kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U, /**< IOMUXC select input index */ - kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U, /**< IOMUXC select input index */ - kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U, /**< IOMUXC select input index */ - kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U, /**< IOMUXC select input index */ - kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U, /**< IOMUXC select input index */ - kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U, /**< IOMUXC select input index */ - kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U, /**< IOMUXC select input index */ - kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U, /**< IOMUXC select input index */ - kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U, /**< IOMUXC select input index */ - kIOMUXC_NMI_SELECT_INPUT = 93U, /**< IOMUXC select input index */ - kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U, /**< IOMUXC select input index */ - kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U, /**< IOMUXC select input index */ - kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U, /**< IOMUXC select input index */ - kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U, /**< IOMUXC select input index */ - kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U, /**< IOMUXC select input index */ - kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U, /**< IOMUXC select input index */ - kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U, /**< IOMUXC select input index */ - kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U, /**< IOMUXC select input index */ - kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U, /**< IOMUXC select input index */ - kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U, /**< IOMUXC select input index */ - kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U, /**< IOMUXC select input index */ - kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U, /**< IOMUXC select input index */ - kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U, /**< IOMUXC select input index */ - kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U, /**< IOMUXC select input index */ - kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U, /**< IOMUXC select input index */ - kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U, /**< IOMUXC select input index */ - kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U, /**< IOMUXC select input index */ - kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U, /**< IOMUXC select input index */ - kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U, /**< IOMUXC select input index */ - kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */ - kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U, /**< IOMUXC select input index */ - kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U, /**< IOMUXC select input index */ - kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U, /**< IOMUXC select input index */ - kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U, /**< IOMUXC select input index */ - kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U, /**< IOMUXC select input index */ - kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U, /**< IOMUXC select input index */ - kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U, /**< IOMUXC select input index */ - kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */ - kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U, /**< IOMUXC select input index */ - kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U, /**< IOMUXC select input index */ - kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U, /**< IOMUXC select input index */ - kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U, /**< IOMUXC select input index */ - kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U, /**< IOMUXC select input index */ - kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U, /**< IOMUXC select input index */ - kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U, /**< IOMUXC select input index */ - kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U, /**< IOMUXC select input index */ - kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U, /**< IOMUXC select input index */ - kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U, /**< IOMUXC select input index */ - kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U, /**< IOMUXC select input index */ - kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U, /**< IOMUXC select input index */ - kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */ -} iomuxc_select_input_t; - -typedef enum _xbar_input_signal -{ - kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */ - kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */ - kXBARA1_InputIomuxXbarIn02 = 2|0x100U, /**< IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */ - kXBARA1_InputIomuxXbarIn03 = 3|0x100U, /**< IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */ - kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ - kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ - kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ - kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ - kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ - kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ - kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ - kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ - kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ - kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ - kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ - kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ - kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ - kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ - kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ - kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ - kXBARA1_InputIomuxXbarIn20 = 20|0x100U, /**< IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */ - kXBARA1_InputIomuxXbarIn21 = 21|0x100U, /**< IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */ - kXBARA1_InputIomuxXbarIn22 = 22|0x100U, /**< IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */ - kXBARA1_InputIomuxXbarIn23 = 23|0x100U, /**< IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */ - kXBARA1_InputIomuxXbarIn24 = 24|0x100U, /**< IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */ - kXBARA1_InputIomuxXbarIn25 = 25|0x100U, /**< IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */ - kXBARA1_InputAcmp1Out = 26|0x100U, /**< ACMP1_OUT output assigned to XBARA1_IN26 input. */ - kXBARA1_InputAcmp2Out = 27|0x100U, /**< ACMP2_OUT output assigned to XBARA1_IN27 input. */ - kXBARA1_InputAcmp3Out = 28|0x100U, /**< ACMP3_OUT output assigned to XBARA1_IN28 input. */ - kXBARA1_InputAcmp4Out = 29|0x100U, /**< ACMP4_OUT output assigned to XBARA1_IN29 input. */ - kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA1_IN30 input is reserved. */ - kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA1_IN31 input is reserved. */ - kXBARA1_InputQtimer3Tmr0Output = 32|0x100U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ - kXBARA1_InputQtimer3Tmr1Output = 33|0x100U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ - kXBARA1_InputQtimer3Tmr2Output = 34|0x100U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ - kXBARA1_InputQtimer3Tmr3Output = 35|0x100U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */ - kXBARA1_InputQtimer4Tmr0Output = 36|0x100U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */ - kXBARA1_InputQtimer4Tmr1Output = 37|0x100U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */ - kXBARA1_InputQtimer4Tmr2Output = 38|0x100U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */ - kXBARA1_InputQtimer4Tmr3Output = 39|0x100U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */ - kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */ - kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */ - kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */ - kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */ - kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */ - kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */ - kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */ - kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */ - kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */ - kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */ - kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */ - kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */ - kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */ - kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */ - kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */ - kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */ - kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ - kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ - kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ - kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ - kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ - kXBARA1_InputEnc2PosMatch = 61|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ - kXBARA1_InputEnc3PosMatch = 62|0x100U, /**< ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */ - kXBARA1_InputEnc4PosMatch = 63|0x100U, /**< ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */ - kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA1_IN64 input. */ - kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA1_IN65 input. */ - kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA1_IN66 input. */ - kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA1_IN67 input. */ - kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA1_IN68 input. */ - kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA1_IN69 input. */ - kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA1_IN70 input. */ - kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA1_IN71 input. */ - kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA1_IN72 input. */ - kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA1_IN73 input. */ - kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA1_IN74 input. */ - kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA1_IN75 input. */ - kXBARA1_InputAoi2Out0 = 76|0x100U, /**< AOI2_OUT0 output assigned to XBARA1_IN76 input. */ - kXBARA1_InputAoi2Out1 = 77|0x100U, /**< AOI2_OUT1 output assigned to XBARA1_IN77 input. */ - kXBARA1_InputAoi2Out2 = 78|0x100U, /**< AOI2_OUT2 output assigned to XBARA1_IN78 input. */ - kXBARA1_InputAoi2Out3 = 79|0x100U, /**< AOI2_OUT3 output assigned to XBARA1_IN79 input. */ - kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ - kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ - kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ - kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ - kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ - kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ - kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ - kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ - kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */ - kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */ - kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB2_IN2 input is reserved. */ - kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB2_IN3 input is reserved. */ - kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB2_IN4 input is reserved. */ - kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB2_IN5 input is reserved. */ - kXBARB2_InputAcmp1Out = 6|0x200U, /**< ACMP1_OUT output assigned to XBARB2_IN6 input. */ - kXBARB2_InputAcmp2Out = 7|0x200U, /**< ACMP2_OUT output assigned to XBARB2_IN7 input. */ - kXBARB2_InputAcmp3Out = 8|0x200U, /**< ACMP3_OUT output assigned to XBARB2_IN8 input. */ - kXBARB2_InputAcmp4Out = 9|0x200U, /**< ACMP4_OUT output assigned to XBARB2_IN9 input. */ - kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB2_IN10 input is reserved. */ - kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB2_IN11 input is reserved. */ - kXBARB2_InputQtimer3Tmr0Output = 12|0x200U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ - kXBARB2_InputQtimer3Tmr1Output = 13|0x200U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ - kXBARB2_InputQtimer3Tmr2Output = 14|0x200U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ - kXBARB2_InputQtimer3Tmr3Output = 15|0x200U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */ - kXBARB2_InputQtimer4Tmr0Output = 16|0x200U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */ - kXBARB2_InputQtimer4Tmr1Output = 17|0x200U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */ - kXBARB2_InputQtimer4Tmr2Output = 18|0x200U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */ - kXBARB2_InputQtimer4Tmr3Output = 19|0x200U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */ - kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */ - kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */ - kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */ - kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */ - kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */ - kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */ - kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */ - kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */ - kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */ - kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */ - kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */ - kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */ - kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */ - kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */ - kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */ - kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */ - kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ - kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ - kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ - kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ - kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ - kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ - kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ - kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ - kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ - kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ - kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ - kXBARB2_InputEnc2PosMatch = 47|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ - kXBARB2_InputEnc3PosMatch = 48|0x200U, /**< ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */ - kXBARB2_InputEnc4PosMatch = 49|0x200U, /**< ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */ - kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB2_IN50 input. */ - kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB2_IN51 input. */ - kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB2_IN52 input. */ - kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB2_IN53 input. */ - kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB2_IN54 input. */ - kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB2_IN55 input. */ - kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB2_IN56 input. */ - kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB2_IN57 input. */ - kXBARB3_InputLogicLow = 0|0x300U, /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */ - kXBARB3_InputLogicHigh = 1|0x300U, /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */ - kXBARB3_InputRESERVED2 = 2|0x300U, /**< XBARB3_IN2 input is reserved. */ - kXBARB3_InputRESERVED3 = 3|0x300U, /**< XBARB3_IN3 input is reserved. */ - kXBARB3_InputRESERVED4 = 4|0x300U, /**< XBARB3_IN4 input is reserved. */ - kXBARB3_InputRESERVED5 = 5|0x300U, /**< XBARB3_IN5 input is reserved. */ - kXBARB3_InputAcmp1Out = 6|0x300U, /**< ACMP1_OUT output assigned to XBARB3_IN6 input. */ - kXBARB3_InputAcmp2Out = 7|0x300U, /**< ACMP2_OUT output assigned to XBARB3_IN7 input. */ - kXBARB3_InputAcmp3Out = 8|0x300U, /**< ACMP3_OUT output assigned to XBARB3_IN8 input. */ - kXBARB3_InputAcmp4Out = 9|0x300U, /**< ACMP4_OUT output assigned to XBARB3_IN9 input. */ - kXBARB3_InputRESERVED10 = 10|0x300U, /**< XBARB3_IN10 input is reserved. */ - kXBARB3_InputRESERVED11 = 11|0x300U, /**< XBARB3_IN11 input is reserved. */ - kXBARB3_InputQtimer3Tmr0Output = 12|0x300U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */ - kXBARB3_InputQtimer3Tmr1Output = 13|0x300U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */ - kXBARB3_InputQtimer3Tmr2Output = 14|0x300U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */ - kXBARB3_InputQtimer3Tmr3Output = 15|0x300U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */ - kXBARB3_InputQtimer4Tmr0Output = 16|0x300U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */ - kXBARB3_InputQtimer4Tmr1Output = 17|0x300U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */ - kXBARB3_InputQtimer4Tmr2Output = 18|0x300U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */ - kXBARB3_InputQtimer4Tmr3Output = 19|0x300U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */ - kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */ - kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */ - kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */ - kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */ - kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */ - kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */ - kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */ - kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */ - kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */ - kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */ - kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */ - kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */ - kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */ - kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */ - kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */ - kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */ - kXBARB3_InputPitTrigger0 = 36|0x300U, /**< PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */ - kXBARB3_InputPitTrigger1 = 37|0x300U, /**< PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */ - kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */ - kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */ - kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */ - kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */ - kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */ - kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */ - kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */ - kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */ - kXBARB3_InputEnc1PosMatch = 46|0x300U, /**< ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */ - kXBARB3_InputEnc2PosMatch = 47|0x300U, /**< ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */ - kXBARB3_InputEnc3PosMatch = 48|0x300U, /**< ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */ - kXBARB3_InputEnc4PosMatch = 49|0x300U, /**< ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */ - kXBARB3_InputDmaDone0 = 50|0x300U, /**< DMA_DONE0 output assigned to XBARB3_IN50 input. */ - kXBARB3_InputDmaDone1 = 51|0x300U, /**< DMA_DONE1 output assigned to XBARB3_IN51 input. */ - kXBARB3_InputDmaDone2 = 52|0x300U, /**< DMA_DONE2 output assigned to XBARB3_IN52 input. */ - kXBARB3_InputDmaDone3 = 53|0x300U, /**< DMA_DONE3 output assigned to XBARB3_IN53 input. */ - kXBARB3_InputDmaDone4 = 54|0x300U, /**< DMA_DONE4 output assigned to XBARB3_IN54 input. */ - kXBARB3_InputDmaDone5 = 55|0x300U, /**< DMA_DONE5 output assigned to XBARB3_IN55 input. */ - kXBARB3_InputDmaDone6 = 56|0x300U, /**< DMA_DONE6 output assigned to XBARB3_IN56 input. */ - kXBARB3_InputDmaDone7 = 57|0x300U, /**< DMA_DONE7 output assigned to XBARB3_IN57 input. */ -} xbar_input_signal_t; - -typedef enum _xbar_output_signal -{ - kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ - kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ - kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ - kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ - kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ - kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ - kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ - kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ - kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ - kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ - kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ - kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ - kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ - kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ - kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ - kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ - kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ - kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ - kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ - kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ - kXBARA1_OutputAcmp1Sample = 20|0x100U, /**< XBARA1_OUT20 output assigned to ACMP1_SAMPLE */ - kXBARA1_OutputAcmp2Sample = 21|0x100U, /**< XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ - kXBARA1_OutputAcmp3Sample = 22|0x100U, /**< XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ - kXBARA1_OutputAcmp4Sample = 23|0x100U, /**< XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ - kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA1_OUT24 output is reserved. */ - kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA1_OUT25 output is reserved. */ - kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ - kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ - kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ - kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */ - kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ - kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ - kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ - kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ - kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */ - kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */ - kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */ - kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U, /**< XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */ - kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U, /**< XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */ - kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ - kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U, /**< XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */ - kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U, /**< XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */ - kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U, /**< XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */ - kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U, /**< XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */ - kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, /**< XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ - kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, /**< XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ - kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, /**< XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ - kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U, /**< XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ - kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U, /**< XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */ - kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, /**< XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ - kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, /**< XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ - kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U, /**< XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ - kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U, /**< XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */ - kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */ - kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */ - kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */ - kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */ - kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U, /**< XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */ - kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U, /**< XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */ - kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U, /**< XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */ - kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U, /**< XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */ - kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U, /**< XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */ - kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U, /**< XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */ - kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U, /**< XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */ - kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U, /**< XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */ - kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U, /**< XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */ - kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT */ - kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT */ - kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA1_OUT68 output assigned to ENC1_INDEX */ - kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA1_OUT69 output assigned to ENC1_HOME */ - kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA1_OUT70 output assigned to ENC1_TRIGGER */ - kXBARA1_OutputEnc2PhaseAInput = 71|0x100U, /**< XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT */ - kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, /**< XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT */ - kXBARA1_OutputEnc2Index = 73|0x100U, /**< XBARA1_OUT73 output assigned to ENC2_INDEX */ - kXBARA1_OutputEnc2Home = 74|0x100U, /**< XBARA1_OUT74 output assigned to ENC2_HOME */ - kXBARA1_OutputEnc2Trigger = 75|0x100U, /**< XBARA1_OUT75 output assigned to ENC2_TRIGGER */ - kXBARA1_OutputEnc3PhaseAInput = 76|0x100U, /**< XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT */ - kXBARA1_OutputEnc3PhaseBInput = 77|0x100U, /**< XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT */ - kXBARA1_OutputEnc3Index = 78|0x100U, /**< XBARA1_OUT78 output assigned to ENC3_INDEX */ - kXBARA1_OutputEnc3Home = 79|0x100U, /**< XBARA1_OUT79 output assigned to ENC3_HOME */ - kXBARA1_OutputEnc3Trigger = 80|0x100U, /**< XBARA1_OUT80 output assigned to ENC3_TRIGGER */ - kXBARA1_OutputEnc4PhaseAInput = 81|0x100U, /**< XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT */ - kXBARA1_OutputEnc4PhaseBInput = 82|0x100U, /**< XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT */ - kXBARA1_OutputEnc4Index = 83|0x100U, /**< XBARA1_OUT83 output assigned to ENC4_INDEX */ - kXBARA1_OutputEnc4Home = 84|0x100U, /**< XBARA1_OUT84 output assigned to ENC4_HOME */ - kXBARA1_OutputEnc4Trigger = 85|0x100U, /**< XBARA1_OUT85 output assigned to ENC4_TRIGGER */ - kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U, /**< XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT */ - kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U, /**< XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT */ - kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U, /**< XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT */ - kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U, /**< XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT */ - kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U, /**< XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT */ - kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U, /**< XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT */ - kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U, /**< XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT */ - kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U, /**< XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT */ - kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U, /**< XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT */ - kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U, /**< XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT */ - kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U, /**< XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT */ - kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U, /**< XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT */ - kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U, /**< XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT */ - kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U, /**< XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT */ - kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U, /**< XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT */ - kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U, /**< XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT */ - kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA1_OUT102 output assigned to EWM_EWM_IN */ - kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U, /**< XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ - kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U, /**< XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ - kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U, /**< XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */ - kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U, /**< XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */ - kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U, /**< XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */ - kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U, /**< XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */ - kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U, /**< XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */ - kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U, /**< XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */ - kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT */ - kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT */ - kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, /**< XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT */ - kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, /**< XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT */ - kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT */ - kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT */ - kXBARA1_OutputLpspi3TrgInput = 117|0x100U, /**< XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT */ - kXBARA1_OutputLpspi4TrgInput = 118|0x100U, /**< XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT */ - kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT */ - kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT */ - kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT */ - kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT */ - kXBARA1_OutputLpuart5TrgInput = 123|0x100U, /**< XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT */ - kXBARA1_OutputLpuart6TrgInput = 124|0x100U, /**< XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT */ - kXBARA1_OutputLpuart7TrgInput = 125|0x100U, /**< XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT */ - kXBARA1_OutputLpuart8TrgInput = 126|0x100U, /**< XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT */ - kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ - kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ - kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U, /**< XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */ - kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U, /**< XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */ - kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB2_OUT0 output assigned to AOI1_IN00 */ - kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB2_OUT1 output assigned to AOI1_IN01 */ - kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB2_OUT2 output assigned to AOI1_IN02 */ - kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB2_OUT3 output assigned to AOI1_IN03 */ - kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB2_OUT4 output assigned to AOI1_IN04 */ - kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB2_OUT5 output assigned to AOI1_IN05 */ - kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB2_OUT6 output assigned to AOI1_IN06 */ - kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB2_OUT7 output assigned to AOI1_IN07 */ - kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB2_OUT8 output assigned to AOI1_IN08 */ - kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB2_OUT9 output assigned to AOI1_IN09 */ - kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB2_OUT10 output assigned to AOI1_IN10 */ - kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB2_OUT11 output assigned to AOI1_IN11 */ - kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB2_OUT12 output assigned to AOI1_IN12 */ - kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB2_OUT13 output assigned to AOI1_IN13 */ - kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB2_OUT14 output assigned to AOI1_IN14 */ - kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB2_OUT15 output assigned to AOI1_IN15 */ - kXBARB3_OutputAoi2In00 = 0|0x300U, /**< XBARB3_OUT0 output assigned to AOI2_IN00 */ - kXBARB3_OutputAoi2In01 = 1|0x300U, /**< XBARB3_OUT1 output assigned to AOI2_IN01 */ - kXBARB3_OutputAoi2In02 = 2|0x300U, /**< XBARB3_OUT2 output assigned to AOI2_IN02 */ - kXBARB3_OutputAoi2In03 = 3|0x300U, /**< XBARB3_OUT3 output assigned to AOI2_IN03 */ - kXBARB3_OutputAoi2In04 = 4|0x300U, /**< XBARB3_OUT4 output assigned to AOI2_IN04 */ - kXBARB3_OutputAoi2In05 = 5|0x300U, /**< XBARB3_OUT5 output assigned to AOI2_IN05 */ - kXBARB3_OutputAoi2In06 = 6|0x300U, /**< XBARB3_OUT6 output assigned to AOI2_IN06 */ - kXBARB3_OutputAoi2In07 = 7|0x300U, /**< XBARB3_OUT7 output assigned to AOI2_IN07 */ - kXBARB3_OutputAoi2In08 = 8|0x300U, /**< XBARB3_OUT8 output assigned to AOI2_IN08 */ - kXBARB3_OutputAoi2In09 = 9|0x300U, /**< XBARB3_OUT9 output assigned to AOI2_IN09 */ - kXBARB3_OutputAoi2In10 = 10|0x300U, /**< XBARB3_OUT10 output assigned to AOI2_IN10 */ - kXBARB3_OutputAoi2In11 = 11|0x300U, /**< XBARB3_OUT11 output assigned to AOI2_IN11 */ - kXBARB3_OutputAoi2In12 = 12|0x300U, /**< XBARB3_OUT12 output assigned to AOI2_IN12 */ - kXBARB3_OutputAoi2In13 = 13|0x300U, /**< XBARB3_OUT13 output assigned to AOI2_IN13 */ - kXBARB3_OutputAoi2In14 = 14|0x300U, /**< XBARB3_OUT14 output assigned to AOI2_IN14 */ - kXBARB3_OutputAoi2In15 = 15|0x300U, /**< XBARB3_OUT15 output assigned to AOI2_IN15 */ -} xbar_output_signal_t; - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */ - __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */ - __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */ - __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */ - __IO uint32_t GC; /**< General control register, offset: 0x48 */ - __IO uint32_t GS; /**< General status register, offset: 0x4C */ - __IO uint32_t CV; /**< Compare value register, offset: 0x50 */ - __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */ - __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name HC - Control register for hardware triggers */ -/*! @{ */ -#define ADC_HC_ADCH_MASK (0x1FU) -#define ADC_HC_ADCH_SHIFT (0U) -#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) -#define ADC_HC_AIEN_MASK (0x80U) -#define ADC_HC_AIEN_SHIFT (7U) -#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) -/*! @} */ - -/* The count of ADC_HC */ -#define ADC_HC_COUNT (8U) - -/*! @name HS - Status register for HW triggers */ -/*! @{ */ -#define ADC_HS_COCO0_MASK (0x1U) -#define ADC_HS_COCO0_SHIFT (0U) -#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) -/*! @} */ - -/*! @name R - Data result register for HW triggers */ -/*! @{ */ -#define ADC_R_CDATA_MASK (0xFFFU) -#define ADC_R_CDATA_SHIFT (0U) -#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) -/*! @} */ - -/* The count of ADC_R */ -#define ADC_R_COUNT (8U) - -/*! @name CFG - Configuration register */ -/*! @{ */ -#define ADC_CFG_ADICLK_MASK (0x3U) -#define ADC_CFG_ADICLK_SHIFT (0U) -#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) -#define ADC_CFG_MODE_MASK (0xCU) -#define ADC_CFG_MODE_SHIFT (2U) -#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) -#define ADC_CFG_ADLSMP_MASK (0x10U) -#define ADC_CFG_ADLSMP_SHIFT (4U) -#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) -#define ADC_CFG_ADIV_MASK (0x60U) -#define ADC_CFG_ADIV_SHIFT (5U) -#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) -#define ADC_CFG_ADLPC_MASK (0x80U) -#define ADC_CFG_ADLPC_SHIFT (7U) -#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) -#define ADC_CFG_ADSTS_MASK (0x300U) -#define ADC_CFG_ADSTS_SHIFT (8U) -#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) -#define ADC_CFG_ADHSC_MASK (0x400U) -#define ADC_CFG_ADHSC_SHIFT (10U) -#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) -#define ADC_CFG_REFSEL_MASK (0x1800U) -#define ADC_CFG_REFSEL_SHIFT (11U) -#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) -#define ADC_CFG_ADTRG_MASK (0x2000U) -#define ADC_CFG_ADTRG_SHIFT (13U) -#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) -#define ADC_CFG_AVGS_MASK (0xC000U) -#define ADC_CFG_AVGS_SHIFT (14U) -#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) -#define ADC_CFG_OVWREN_MASK (0x10000U) -#define ADC_CFG_OVWREN_SHIFT (16U) -#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) -/*! @} */ - -/*! @name GC - General control register */ -/*! @{ */ -#define ADC_GC_ADACKEN_MASK (0x1U) -#define ADC_GC_ADACKEN_SHIFT (0U) -#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) -#define ADC_GC_DMAEN_MASK (0x2U) -#define ADC_GC_DMAEN_SHIFT (1U) -#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) -#define ADC_GC_ACREN_MASK (0x4U) -#define ADC_GC_ACREN_SHIFT (2U) -#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) -#define ADC_GC_ACFGT_MASK (0x8U) -#define ADC_GC_ACFGT_SHIFT (3U) -#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) -#define ADC_GC_ACFE_MASK (0x10U) -#define ADC_GC_ACFE_SHIFT (4U) -#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) -#define ADC_GC_AVGE_MASK (0x20U) -#define ADC_GC_AVGE_SHIFT (5U) -#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) -#define ADC_GC_ADCO_MASK (0x40U) -#define ADC_GC_ADCO_SHIFT (6U) -#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) -#define ADC_GC_CAL_MASK (0x80U) -#define ADC_GC_CAL_SHIFT (7U) -#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) -/*! @} */ - -/*! @name GS - General status register */ -/*! @{ */ -#define ADC_GS_ADACT_MASK (0x1U) -#define ADC_GS_ADACT_SHIFT (0U) -#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) -#define ADC_GS_CALF_MASK (0x2U) -#define ADC_GS_CALF_SHIFT (1U) -#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) -#define ADC_GS_AWKST_MASK (0x4U) -#define ADC_GS_AWKST_SHIFT (2U) -#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) -/*! @} */ - -/*! @name CV - Compare value register */ -/*! @{ */ -#define ADC_CV_CV1_MASK (0xFFFU) -#define ADC_CV_CV1_SHIFT (0U) -#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) -#define ADC_CV_CV2_MASK (0xFFF0000U) -#define ADC_CV_CV2_SHIFT (16U) -#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) -/*! @} */ - -/*! @name OFS - Offset correction value register */ -/*! @{ */ -#define ADC_OFS_OFS_MASK (0xFFFU) -#define ADC_OFS_OFS_SHIFT (0U) -#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) -#define ADC_OFS_SIGN_MASK (0x1000U) -#define ADC_OFS_SIGN_SHIFT (12U) -#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) -/*! @} */ - -/*! @name CAL - Calibration value register */ -/*! @{ */ -#define ADC_CAL_CAL_CODE_MASK (0xFU) -#define ADC_CAL_CAL_CODE_SHIFT (0U) -#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -/** Peripheral ADC1 base address */ -#define ADC1_BASE (0x400C4000u) -/** Peripheral ADC1 base pointer */ -#define ADC1 ((ADC_Type *)ADC1_BASE) -/** Peripheral ADC2 base address */ -#define ADC2_BASE (0x400C8000u) -/** Peripheral ADC2 base pointer */ -#define ADC2 ((ADC_Type *)ADC2_BASE) -/** Array initializer of ADC peripheral base addresses */ -#define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE } -/** Array initializer of ADC peripheral base pointers */ -#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 } -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ADC_ETC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer - * @{ - */ - -/** ADC_ETC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */ - __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */ - __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */ - __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */ - struct { /* offset: 0x10, array step: 0x28 */ - __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */ - __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */ - __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */ - __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */ - __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */ - __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */ - __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */ - __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */ - __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */ - __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */ - } TRIG[8]; -} ADC_ETC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC_ETC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks - * @{ - */ - -/*! @name CTRL - ADC_ETC Global Control Register */ -/*! @{ */ -#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) -#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) -#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) -#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) -#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) -#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) -#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) -#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) -#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) -#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) -#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) -#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) -#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) -#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) -#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) -#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) -#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) -#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) -#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) -#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) -#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) -#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) -#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) -#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) -#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) -#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U) -#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) -/*! @} */ - -/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */ -/*! @{ */ -#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) -#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) -#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) -#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) -#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) -#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) -#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) -#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) -#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) -#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) -#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) -#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) -#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) -#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) -#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) -#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) -#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) -#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) -#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) -#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) -#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) -#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) -#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) -#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) -#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) -#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) -#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) -#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) -#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) -#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) -#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) -#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) -#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) -#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) -/*! @} */ - -/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */ -/*! @{ */ -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) -/*! @} */ - -/*! @name DMA_CTRL - ETC DMA control Register */ -/*! @{ */ -#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) -#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) -#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) -#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) -#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) -#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) -#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) -#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) -#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) -#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) -#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) -#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) -#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) -#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) -#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) -#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) -#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) -#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) -#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) -#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) -#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) -#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) -#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) -#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) -#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) -#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) -#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) -#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) -#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) -#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) -#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) -#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) -#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) -#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) -#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) -#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) -#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) -#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) -#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) -#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) -#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) -#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) -#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) -#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) -#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) -#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) -#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) -#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) -/*! @} */ - -/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */ -/*! @{ */ -#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) -#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) -#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) -#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) -#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) -#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) -#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) -#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) -#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) -#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) -#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) -#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) -#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) -#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) -#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) -/*! @} */ - -/* The count of ADC_ETC_TRIGn_CTRL */ -#define ADC_ETC_TRIGn_CTRL_COUNT (8U) - -/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */ -/*! @{ */ -#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) -#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) -#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) -#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) -#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) -#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) -/*! @} */ - -/* The count of ADC_ETC_TRIGn_COUNTER */ -#define ADC_ETC_TRIGn_COUNTER_COUNT (8U) - -/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */ -/*! @{ */ -#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) -#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) -#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) -#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) -#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) -#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) -#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) -#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) -#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) -#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) -#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) -#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) -#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) -#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) -#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) -#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) -#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) -#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) -#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) -#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) -#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) -#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) -#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) -#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) -/*! @} */ - -/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */ -#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) - -/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */ -/*! @{ */ -#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) -#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) -#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) -#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) -#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) -#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) -#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) -#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) -#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) -#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) -#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) -#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) -#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) -#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) -#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) -#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) -#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) -#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) -#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) -#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) -#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) -#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) -#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) -#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) -/*! @} */ - -/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */ -#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) - -/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */ -/*! @{ */ -#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) -#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) -#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) -#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) -#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U) -#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK) -#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U) -#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U) -#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK) -#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U) -#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U) -#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK) -#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U) -#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U) -#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK) -#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U) -#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U) -#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK) -#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U) -#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U) -#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK) -#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) -#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) -#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) -/*! @} */ - -/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */ -#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U) - -/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */ -/*! @{ */ -#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) -#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) -#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) -#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U) -#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U) -#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK) -#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U) -#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U) -#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK) -#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U) -#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U) -#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK) -#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U) -#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U) -#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK) -#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U) -#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U) -#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK) -#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U) -#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U) -#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK) -#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) -#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) -#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) -/*! @} */ - -/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */ -#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U) - -/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */ -/*! @{ */ -#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) -#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) -#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) -#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) -#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) -#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) -/*! @} */ - -/* The count of ADC_ETC_TRIGn_RESULT_1_0 */ -#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U) - -/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */ -/*! @{ */ -#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) -#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) -#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) -#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) -#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) -#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) -/*! @} */ - -/* The count of ADC_ETC_TRIGn_RESULT_3_2 */ -#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U) - -/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */ -/*! @{ */ -#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) -#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) -#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) -#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) -#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) -#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) -/*! @} */ - -/* The count of ADC_ETC_TRIGn_RESULT_5_4 */ -#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U) - -/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */ -/*! @{ */ -#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) -#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) -#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) -#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) -#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) -#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) -/*! @} */ - -/* The count of ADC_ETC_TRIGn_RESULT_7_6 */ -#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U) - - -/*! - * @} - */ /* end of group ADC_ETC_Register_Masks */ - - -/* ADC_ETC - Peripheral instance base addresses */ -/** Peripheral ADC_ETC base address */ -#define ADC_ETC_BASE (0x403B0000u) -/** Peripheral ADC_ETC base pointer */ -#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE) -/** Array initializer of ADC_ETC peripheral base addresses */ -#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE } -/** Array initializer of ADC_ETC peripheral base pointers */ -#define ADC_ETC_BASE_PTRS { ADC_ETC } -/** Interrupt vectors for the ADC_ETC peripheral type */ -#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } } -#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn } - -/*! - * @} - */ /* end of group ADC_ETC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- AIPSTZ Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer - * @{ - */ - -/** AIPSTZ - Register Layout Typedef */ -typedef struct { - __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ - uint8_t RESERVED_0[60]; - __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ - __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ - __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ - __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ - __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ -} AIPSTZ_Type; - -/* ---------------------------------------------------------------------------- - -- AIPSTZ Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks - * @{ - */ - -/*! @name MPR - Master Priviledge Registers */ -/*! @{ */ -#define AIPSTZ_MPR_MPROT5_MASK (0xF00U) -#define AIPSTZ_MPR_MPROT5_SHIFT (8U) -#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) -#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) -#define AIPSTZ_MPR_MPROT3_SHIFT (16U) -#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) -#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) -#define AIPSTZ_MPR_MPROT2_SHIFT (20U) -#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) -#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) -#define AIPSTZ_MPR_MPROT1_SHIFT (24U) -#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) -#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) -#define AIPSTZ_MPR_MPROT0_SHIFT (28U) -#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) -/*! @} */ - -/*! @name OPACR - Off-Platform Peripheral Access Control Registers */ -/*! @{ */ -#define AIPSTZ_OPACR_OPAC7_MASK (0xFU) -#define AIPSTZ_OPACR_OPAC7_SHIFT (0U) -#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) -#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) -#define AIPSTZ_OPACR_OPAC6_SHIFT (4U) -#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) -#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) -#define AIPSTZ_OPACR_OPAC5_SHIFT (8U) -#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) -#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) -#define AIPSTZ_OPACR_OPAC4_SHIFT (12U) -#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) -#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) -#define AIPSTZ_OPACR_OPAC3_SHIFT (16U) -#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) -#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) -#define AIPSTZ_OPACR_OPAC2_SHIFT (20U) -#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) -#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) -#define AIPSTZ_OPACR_OPAC1_SHIFT (24U) -#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) -#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) -#define AIPSTZ_OPACR_OPAC0_SHIFT (28U) -#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) -/*! @} */ - -/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ -/*! @{ */ -#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) -#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) -#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) -#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) -#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) -#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) -#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) -#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) -#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) -#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) -#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) -#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) -#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) -#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) -#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) -#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) -#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) -#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) -#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) -#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) -#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) -#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) -#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) -#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) -/*! @} */ - -/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ -/*! @{ */ -#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) -#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) -#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) -#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) -#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) -#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) -#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) -#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) -#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) -#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) -#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) -#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) -#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) -#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) -#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) -#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) -#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) -#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) -#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) -#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) -#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) -#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) -#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) -#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) -/*! @} */ - -/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ -/*! @{ */ -#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) -#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) -#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) -#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) -#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) -#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) -#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) -#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) -#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) -#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) -#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) -#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) -#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) -#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) -#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) -#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) -#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) -#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) -#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) -#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) -#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) -#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) -#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) -#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) -/*! @} */ - -/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ -/*! @{ */ -#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) -#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) -#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) -#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) -#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) -#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group AIPSTZ_Register_Masks */ - - -/* AIPSTZ - Peripheral instance base addresses */ -/** Peripheral AIPSTZ1 base address */ -#define AIPSTZ1_BASE (0x4007C000u) -/** Peripheral AIPSTZ1 base pointer */ -#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) -/** Peripheral AIPSTZ2 base address */ -#define AIPSTZ2_BASE (0x4017C000u) -/** Peripheral AIPSTZ2 base pointer */ -#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) -/** Peripheral AIPSTZ3 base address */ -#define AIPSTZ3_BASE (0x4027C000u) -/** Peripheral AIPSTZ3 base pointer */ -#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) -/** Peripheral AIPSTZ4 base address */ -#define AIPSTZ4_BASE (0x4037C000u) -/** Peripheral AIPSTZ4 base pointer */ -#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE) -/** Array initializer of AIPSTZ peripheral base addresses */ -#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE } -/** Array initializer of AIPSTZ peripheral base pointers */ -#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 } - -/*! - * @} - */ /* end of group AIPSTZ_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- AOI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer - * @{ - */ - -/** AOI - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x4 */ - __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */ - __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */ - } BFCRT[4]; -} AOI_Type; - -/* ---------------------------------------------------------------------------- - -- AOI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AOI_Register_Masks AOI Register Masks - * @{ - */ - -/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ -/*! @{ */ -#define AOI_BFCRT01_PT1_DC_MASK (0x3U) -#define AOI_BFCRT01_PT1_DC_SHIFT (0U) -#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) -#define AOI_BFCRT01_PT1_CC_MASK (0xCU) -#define AOI_BFCRT01_PT1_CC_SHIFT (2U) -#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) -#define AOI_BFCRT01_PT1_BC_MASK (0x30U) -#define AOI_BFCRT01_PT1_BC_SHIFT (4U) -#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) -#define AOI_BFCRT01_PT1_AC_MASK (0xC0U) -#define AOI_BFCRT01_PT1_AC_SHIFT (6U) -#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) -#define AOI_BFCRT01_PT0_DC_MASK (0x300U) -#define AOI_BFCRT01_PT0_DC_SHIFT (8U) -#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) -#define AOI_BFCRT01_PT0_CC_MASK (0xC00U) -#define AOI_BFCRT01_PT0_CC_SHIFT (10U) -#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) -#define AOI_BFCRT01_PT0_BC_MASK (0x3000U) -#define AOI_BFCRT01_PT0_BC_SHIFT (12U) -#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) -#define AOI_BFCRT01_PT0_AC_MASK (0xC000U) -#define AOI_BFCRT01_PT0_AC_SHIFT (14U) -#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) -/*! @} */ - -/* The count of AOI_BFCRT01 */ -#define AOI_BFCRT01_COUNT (4U) - -/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ -/*! @{ */ -#define AOI_BFCRT23_PT3_DC_MASK (0x3U) -#define AOI_BFCRT23_PT3_DC_SHIFT (0U) -#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) -#define AOI_BFCRT23_PT3_CC_MASK (0xCU) -#define AOI_BFCRT23_PT3_CC_SHIFT (2U) -#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) -#define AOI_BFCRT23_PT3_BC_MASK (0x30U) -#define AOI_BFCRT23_PT3_BC_SHIFT (4U) -#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) -#define AOI_BFCRT23_PT3_AC_MASK (0xC0U) -#define AOI_BFCRT23_PT3_AC_SHIFT (6U) -#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) -#define AOI_BFCRT23_PT2_DC_MASK (0x300U) -#define AOI_BFCRT23_PT2_DC_SHIFT (8U) -#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) -#define AOI_BFCRT23_PT2_CC_MASK (0xC00U) -#define AOI_BFCRT23_PT2_CC_SHIFT (10U) -#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) -#define AOI_BFCRT23_PT2_BC_MASK (0x3000U) -#define AOI_BFCRT23_PT2_BC_SHIFT (12U) -#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) -#define AOI_BFCRT23_PT2_AC_MASK (0xC000U) -#define AOI_BFCRT23_PT2_AC_SHIFT (14U) -#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) -/*! @} */ - -/* The count of AOI_BFCRT23 */ -#define AOI_BFCRT23_COUNT (4U) - - -/*! - * @} - */ /* end of group AOI_Register_Masks */ - - -/* AOI - Peripheral instance base addresses */ -/** Peripheral AOI1 base address */ -#define AOI1_BASE (0x403B4000u) -/** Peripheral AOI1 base pointer */ -#define AOI1 ((AOI_Type *)AOI1_BASE) -/** Peripheral AOI2 base address */ -#define AOI2_BASE (0x403B8000u) -/** Peripheral AOI2 base pointer */ -#define AOI2 ((AOI_Type *)AOI2_BASE) -/** Array initializer of AOI peripheral base addresses */ -#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE } -/** Array initializer of AOI peripheral base pointers */ -#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 } - -/*! - * @} - */ /* end of group AOI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- BEE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer - * @{ - */ - -/** BEE - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< BEE Control Register, offset: 0x0 */ - __IO uint32_t ADDR_OFFSET0; /**< , offset: 0x4 */ - __IO uint32_t ADDR_OFFSET1; /**< , offset: 0x8 */ - __IO uint32_t AES_KEY0_W0; /**< , offset: 0xC */ - __IO uint32_t AES_KEY0_W1; /**< , offset: 0x10 */ - __IO uint32_t AES_KEY0_W2; /**< , offset: 0x14 */ - __IO uint32_t AES_KEY0_W3; /**< , offset: 0x18 */ - __IO uint32_t STATUS; /**< , offset: 0x1C */ - __O uint32_t CTR_NONCE0_W0; /**< , offset: 0x20 */ - __O uint32_t CTR_NONCE0_W1; /**< , offset: 0x24 */ - __O uint32_t CTR_NONCE0_W2; /**< , offset: 0x28 */ - __O uint32_t CTR_NONCE0_W3; /**< , offset: 0x2C */ - __O uint32_t CTR_NONCE1_W0; /**< , offset: 0x30 */ - __O uint32_t CTR_NONCE1_W1; /**< , offset: 0x34 */ - __O uint32_t CTR_NONCE1_W2; /**< , offset: 0x38 */ - __O uint32_t CTR_NONCE1_W3; /**< , offset: 0x3C */ - __IO uint32_t REGION1_TOP; /**< , offset: 0x40 */ - __IO uint32_t REGION1_BOT; /**< , offset: 0x44 */ -} BEE_Type; - -/* ---------------------------------------------------------------------------- - -- BEE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup BEE_Register_Masks BEE Register Masks - * @{ - */ - -/*! @name CTRL - BEE Control Register */ -/*! @{ */ -#define BEE_CTRL_BEE_ENABLE_MASK (0x1U) -#define BEE_CTRL_BEE_ENABLE_SHIFT (0U) -#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK) -#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U) -#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U) -#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK) -#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U) -#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U) -#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK) -#define BEE_CTRL_KEY_VALID_MASK (0x10U) -#define BEE_CTRL_KEY_VALID_SHIFT (4U) -#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK) -#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U) -#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U) -#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK) -#define BEE_CTRL_AC_PROT_EN_MASK (0x40U) -#define BEE_CTRL_AC_PROT_EN_SHIFT (6U) -#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK) -#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U) -#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U) -#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK) -#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U) -#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U) -#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK) -#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U) -#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U) -#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK) -#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U) -#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U) -#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK) -#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U) -#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U) -#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK) -#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U) -#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U) -#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK) -#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U) -#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U) -#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK) -#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U) -#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U) -#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK) -#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U) -#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U) -#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK) -#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U) -#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U) -#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK) -#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U) -#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U) -#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK) -#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U) -#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U) -#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK) -#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U) -#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U) -#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK) -#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U) -#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U) -#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK) -#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U) -#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U) -#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK) -#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U) -#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U) -#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK) -#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U) -#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U) -#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK) -#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U) -#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U) -#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK) -#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U) -#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U) -#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK) -/*! @} */ - -/*! @name ADDR_OFFSET0 - */ -/*! @{ */ -#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU) -#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U) -#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK) -#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) -#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U) -#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK) -/*! @} */ - -/*! @name ADDR_OFFSET1 - */ -/*! @{ */ -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK (0xFFFFU) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT (0U) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT (16U) -#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK) -/*! @} */ - -/*! @name AES_KEY0_W0 - */ -/*! @{ */ -#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU) -#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U) -#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK) -/*! @} */ - -/*! @name AES_KEY0_W1 - */ -/*! @{ */ -#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU) -#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U) -#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK) -/*! @} */ - -/*! @name AES_KEY0_W2 - */ -/*! @{ */ -#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU) -#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U) -#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK) -/*! @} */ - -/*! @name AES_KEY0_W3 - */ -/*! @{ */ -#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU) -#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U) -#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK) -/*! @} */ - -/*! @name STATUS - */ -/*! @{ */ -#define BEE_STATUS_IRQ_VEC_MASK (0xFFU) -#define BEE_STATUS_IRQ_VEC_SHIFT (0U) -#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK) -#define BEE_STATUS_BEE_IDLE_MASK (0x100U) -#define BEE_STATUS_BEE_IDLE_SHIFT (8U) -#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK) -/*! @} */ - -/*! @name CTR_NONCE0_W0 - */ -/*! @{ */ -#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU) -#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U) -#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK) -/*! @} */ - -/*! @name CTR_NONCE0_W1 - */ -/*! @{ */ -#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU) -#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U) -#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK) -/*! @} */ - -/*! @name CTR_NONCE0_W2 - */ -/*! @{ */ -#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU) -#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U) -#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK) -/*! @} */ - -/*! @name CTR_NONCE0_W3 - */ -/*! @{ */ -#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU) -#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U) -#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK) -/*! @} */ - -/*! @name CTR_NONCE1_W0 - */ -/*! @{ */ -#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU) -#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U) -#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK) -/*! @} */ - -/*! @name CTR_NONCE1_W1 - */ -/*! @{ */ -#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU) -#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U) -#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK) -/*! @} */ - -/*! @name CTR_NONCE1_W2 - */ -/*! @{ */ -#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU) -#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U) -#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK) -/*! @} */ - -/*! @name CTR_NONCE1_W3 - */ -/*! @{ */ -#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU) -#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U) -#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK) -/*! @} */ - -/*! @name REGION1_TOP - */ -/*! @{ */ -#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU) -#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U) -#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK) -/*! @} */ - -/*! @name REGION1_BOT - */ -/*! @{ */ -#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU) -#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U) -#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group BEE_Register_Masks */ - - -/* BEE - Peripheral instance base addresses */ -/** Peripheral BEE base address */ -#define BEE_BASE (0x403EC000u) -/** Peripheral BEE base pointer */ -#define BEE ((BEE_Type *)BEE_BASE) -/** Array initializer of BEE peripheral base addresses */ -#define BEE_BASE_ADDRS { BEE_BASE } -/** Array initializer of BEE peripheral base pointers */ -#define BEE_BASE_PTRS { BEE } - -/*! - * @} - */ /* end of group BEE_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CAN Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer - * @{ - */ - -/** CAN - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ - __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ - __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ - __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ - __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ - __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ - __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ - __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ - __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ - __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ - __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ - __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ - __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ - uint8_t RESERVED_1[8]; - __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ - __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ - __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ - uint8_t RESERVED_2[48]; - struct { /* offset: 0x80, array step: 0x10 */ - __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ - __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ - __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ - __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ - } MB[64]; - uint8_t RESERVED_3[1024]; - __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ - uint8_t RESERVED_4[96]; - __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ -} CAN_Type; - -/* ---------------------------------------------------------------------------- - -- CAN Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CAN_Register_Masks CAN Register Masks - * @{ - */ - -/*! @name MCR - Module Configuration Register */ -/*! @{ */ -#define CAN_MCR_MAXMB_MASK (0x7FU) -#define CAN_MCR_MAXMB_SHIFT (0U) -#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) -#define CAN_MCR_IDAM_MASK (0x300U) -#define CAN_MCR_IDAM_SHIFT (8U) -#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) -#define CAN_MCR_AEN_MASK (0x1000U) -#define CAN_MCR_AEN_SHIFT (12U) -#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) -#define CAN_MCR_LPRIOEN_MASK (0x2000U) -#define CAN_MCR_LPRIOEN_SHIFT (13U) -#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) -#define CAN_MCR_IRMQ_MASK (0x10000U) -#define CAN_MCR_IRMQ_SHIFT (16U) -#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) -#define CAN_MCR_SRXDIS_MASK (0x20000U) -#define CAN_MCR_SRXDIS_SHIFT (17U) -#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) -#define CAN_MCR_WAKSRC_MASK (0x80000U) -#define CAN_MCR_WAKSRC_SHIFT (19U) -#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) -#define CAN_MCR_LPMACK_MASK (0x100000U) -#define CAN_MCR_LPMACK_SHIFT (20U) -#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) -#define CAN_MCR_WRNEN_MASK (0x200000U) -#define CAN_MCR_WRNEN_SHIFT (21U) -#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) -#define CAN_MCR_SLFWAK_MASK (0x400000U) -#define CAN_MCR_SLFWAK_SHIFT (22U) -#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) -#define CAN_MCR_SUPV_MASK (0x800000U) -#define CAN_MCR_SUPV_SHIFT (23U) -#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) -#define CAN_MCR_FRZACK_MASK (0x1000000U) -#define CAN_MCR_FRZACK_SHIFT (24U) -#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) -#define CAN_MCR_SOFTRST_MASK (0x2000000U) -#define CAN_MCR_SOFTRST_SHIFT (25U) -#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) -#define CAN_MCR_WAKMSK_MASK (0x4000000U) -#define CAN_MCR_WAKMSK_SHIFT (26U) -#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) -#define CAN_MCR_NOTRDY_MASK (0x8000000U) -#define CAN_MCR_NOTRDY_SHIFT (27U) -#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) -#define CAN_MCR_HALT_MASK (0x10000000U) -#define CAN_MCR_HALT_SHIFT (28U) -#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) -#define CAN_MCR_RFEN_MASK (0x20000000U) -#define CAN_MCR_RFEN_SHIFT (29U) -#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) -#define CAN_MCR_FRZ_MASK (0x40000000U) -#define CAN_MCR_FRZ_SHIFT (30U) -#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) -#define CAN_MCR_MDIS_MASK (0x80000000U) -#define CAN_MCR_MDIS_SHIFT (31U) -#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) -/*! @} */ - -/*! @name CTRL1 - Control 1 Register */ -/*! @{ */ -#define CAN_CTRL1_PROPSEG_MASK (0x7U) -#define CAN_CTRL1_PROPSEG_SHIFT (0U) -#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) -#define CAN_CTRL1_LOM_MASK (0x8U) -#define CAN_CTRL1_LOM_SHIFT (3U) -#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) -#define CAN_CTRL1_LBUF_MASK (0x10U) -#define CAN_CTRL1_LBUF_SHIFT (4U) -#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) -#define CAN_CTRL1_TSYN_MASK (0x20U) -#define CAN_CTRL1_TSYN_SHIFT (5U) -#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) -#define CAN_CTRL1_BOFFREC_MASK (0x40U) -#define CAN_CTRL1_BOFFREC_SHIFT (6U) -#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) -#define CAN_CTRL1_SMP_MASK (0x80U) -#define CAN_CTRL1_SMP_SHIFT (7U) -#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) -#define CAN_CTRL1_RWRNMSK_MASK (0x400U) -#define CAN_CTRL1_RWRNMSK_SHIFT (10U) -#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) -#define CAN_CTRL1_TWRNMSK_MASK (0x800U) -#define CAN_CTRL1_TWRNMSK_SHIFT (11U) -#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) -#define CAN_CTRL1_LPB_MASK (0x1000U) -#define CAN_CTRL1_LPB_SHIFT (12U) -#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) -#define CAN_CTRL1_ERRMSK_MASK (0x4000U) -#define CAN_CTRL1_ERRMSK_SHIFT (14U) -#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) -#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) -#define CAN_CTRL1_BOFFMSK_SHIFT (15U) -#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) -#define CAN_CTRL1_PSEG2_MASK (0x70000U) -#define CAN_CTRL1_PSEG2_SHIFT (16U) -#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) -#define CAN_CTRL1_PSEG1_MASK (0x380000U) -#define CAN_CTRL1_PSEG1_SHIFT (19U) -#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) -#define CAN_CTRL1_RJW_MASK (0xC00000U) -#define CAN_CTRL1_RJW_SHIFT (22U) -#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) -#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) -#define CAN_CTRL1_PRESDIV_SHIFT (24U) -#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) -/*! @} */ - -/*! @name TIMER - Free Running Timer Register */ -/*! @{ */ -#define CAN_TIMER_TIMER_MASK (0xFFFFU) -#define CAN_TIMER_TIMER_SHIFT (0U) -#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) -/*! @} */ - -/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ -/*! @{ */ -#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) -#define CAN_RXMGMASK_MG_SHIFT (0U) -#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) -/*! @} */ - -/*! @name RX14MASK - Rx Buffer 14 Mask Register */ -/*! @{ */ -#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) -#define CAN_RX14MASK_RX14M_SHIFT (0U) -#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) -/*! @} */ - -/*! @name RX15MASK - Rx Buffer 15 Mask Register */ -/*! @{ */ -#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) -#define CAN_RX15MASK_RX15M_SHIFT (0U) -#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) -/*! @} */ - -/*! @name ECR - Error Counter Register */ -/*! @{ */ -#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) -#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) -#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) -#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) -#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) -#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) -/*! @} */ - -/*! @name ESR1 - Error and Status 1 Register */ -/*! @{ */ -#define CAN_ESR1_WAKINT_MASK (0x1U) -#define CAN_ESR1_WAKINT_SHIFT (0U) -#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) -#define CAN_ESR1_ERRINT_MASK (0x2U) -#define CAN_ESR1_ERRINT_SHIFT (1U) -#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) -#define CAN_ESR1_BOFFINT_MASK (0x4U) -#define CAN_ESR1_BOFFINT_SHIFT (2U) -#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) -#define CAN_ESR1_RX_MASK (0x8U) -#define CAN_ESR1_RX_SHIFT (3U) -#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) -#define CAN_ESR1_FLTCONF_MASK (0x30U) -#define CAN_ESR1_FLTCONF_SHIFT (4U) -#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) -#define CAN_ESR1_TX_MASK (0x40U) -#define CAN_ESR1_TX_SHIFT (6U) -#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) -#define CAN_ESR1_IDLE_MASK (0x80U) -#define CAN_ESR1_IDLE_SHIFT (7U) -#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) -#define CAN_ESR1_RXWRN_MASK (0x100U) -#define CAN_ESR1_RXWRN_SHIFT (8U) -#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) -#define CAN_ESR1_TXWRN_MASK (0x200U) -#define CAN_ESR1_TXWRN_SHIFT (9U) -#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) -#define CAN_ESR1_STFERR_MASK (0x400U) -#define CAN_ESR1_STFERR_SHIFT (10U) -#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) -#define CAN_ESR1_FRMERR_MASK (0x800U) -#define CAN_ESR1_FRMERR_SHIFT (11U) -#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) -#define CAN_ESR1_CRCERR_MASK (0x1000U) -#define CAN_ESR1_CRCERR_SHIFT (12U) -#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) -#define CAN_ESR1_ACKERR_MASK (0x2000U) -#define CAN_ESR1_ACKERR_SHIFT (13U) -#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) -#define CAN_ESR1_BIT0ERR_MASK (0x4000U) -#define CAN_ESR1_BIT0ERR_SHIFT (14U) -#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) -#define CAN_ESR1_BIT1ERR_MASK (0x8000U) -#define CAN_ESR1_BIT1ERR_SHIFT (15U) -#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) -#define CAN_ESR1_RWRNINT_MASK (0x10000U) -#define CAN_ESR1_RWRNINT_SHIFT (16U) -#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) -#define CAN_ESR1_TWRNINT_MASK (0x20000U) -#define CAN_ESR1_TWRNINT_SHIFT (17U) -#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) -#define CAN_ESR1_SYNCH_MASK (0x40000U) -#define CAN_ESR1_SYNCH_SHIFT (18U) -#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) -/*! @} */ - -/*! @name IMASK2 - Interrupt Masks 2 Register */ -/*! @{ */ -#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) -#define CAN_IMASK2_BUFHM_SHIFT (0U) -#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) -/*! @} */ - -/*! @name IMASK1 - Interrupt Masks 1 Register */ -/*! @{ */ -#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) -#define CAN_IMASK1_BUFLM_SHIFT (0U) -#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) -/*! @} */ - -/*! @name IFLAG2 - Interrupt Flags 2 Register */ -/*! @{ */ -#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) -#define CAN_IFLAG2_BUFHI_SHIFT (0U) -#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) -/*! @} */ - -/*! @name IFLAG1 - Interrupt Flags 1 Register */ -/*! @{ */ -#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) -#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) -#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) -#define CAN_IFLAG1_BUF5I_MASK (0x20U) -#define CAN_IFLAG1_BUF5I_SHIFT (5U) -#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) -#define CAN_IFLAG1_BUF6I_MASK (0x40U) -#define CAN_IFLAG1_BUF6I_SHIFT (6U) -#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) -#define CAN_IFLAG1_BUF7I_MASK (0x80U) -#define CAN_IFLAG1_BUF7I_SHIFT (7U) -#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) -#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) -#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) -#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) -/*! @} */ - -/*! @name CTRL2 - Control 2 Register */ -/*! @{ */ -#define CAN_CTRL2_EACEN_MASK (0x10000U) -#define CAN_CTRL2_EACEN_SHIFT (16U) -#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) -#define CAN_CTRL2_RRS_MASK (0x20000U) -#define CAN_CTRL2_RRS_SHIFT (17U) -#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) -#define CAN_CTRL2_MRP_MASK (0x40000U) -#define CAN_CTRL2_MRP_SHIFT (18U) -#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) -#define CAN_CTRL2_TASD_MASK (0xF80000U) -#define CAN_CTRL2_TASD_SHIFT (19U) -#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) -#define CAN_CTRL2_RFFN_MASK (0xF000000U) -#define CAN_CTRL2_RFFN_SHIFT (24U) -#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) -#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) -#define CAN_CTRL2_WRMFRZ_SHIFT (28U) -#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) -/*! @} */ - -/*! @name ESR2 - Error and Status 2 Register */ -/*! @{ */ -#define CAN_ESR2_IMB_MASK (0x2000U) -#define CAN_ESR2_IMB_SHIFT (13U) -#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) -#define CAN_ESR2_VPS_MASK (0x4000U) -#define CAN_ESR2_VPS_SHIFT (14U) -#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) -#define CAN_ESR2_LPTM_MASK (0x7F0000U) -#define CAN_ESR2_LPTM_SHIFT (16U) -#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) -/*! @} */ - -/*! @name CRCR - CRC Register */ -/*! @{ */ -#define CAN_CRCR_TXCRC_MASK (0x7FFFU) -#define CAN_CRCR_TXCRC_SHIFT (0U) -#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) -#define CAN_CRCR_MBCRC_MASK (0x7F0000U) -#define CAN_CRCR_MBCRC_SHIFT (16U) -#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) -/*! @} */ - -/*! @name RXFGMASK - Rx FIFO Global Mask Register */ -/*! @{ */ -#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) -#define CAN_RXFGMASK_FGM_SHIFT (0U) -#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) -/*! @} */ - -/*! @name RXFIR - Rx FIFO Information Register */ -/*! @{ */ -#define CAN_RXFIR_IDHIT_MASK (0x1FFU) -#define CAN_RXFIR_IDHIT_SHIFT (0U) -#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) -/*! @} */ - -/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ -/*! @{ */ -#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) -#define CAN_CS_TIME_STAMP_SHIFT (0U) -#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) -#define CAN_CS_DLC_MASK (0xF0000U) -#define CAN_CS_DLC_SHIFT (16U) -#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) -#define CAN_CS_RTR_MASK (0x100000U) -#define CAN_CS_RTR_SHIFT (20U) -#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) -#define CAN_CS_IDE_MASK (0x200000U) -#define CAN_CS_IDE_SHIFT (21U) -#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) -#define CAN_CS_SRR_MASK (0x400000U) -#define CAN_CS_SRR_SHIFT (22U) -#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) -#define CAN_CS_CODE_MASK (0xF000000U) -#define CAN_CS_CODE_SHIFT (24U) -#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) -/*! @} */ - -/* The count of CAN_CS */ -#define CAN_CS_COUNT (64U) - -/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ -/*! @{ */ -#define CAN_ID_EXT_MASK (0x3FFFFU) -#define CAN_ID_EXT_SHIFT (0U) -#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) -#define CAN_ID_STD_MASK (0x1FFC0000U) -#define CAN_ID_STD_SHIFT (18U) -#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) -#define CAN_ID_PRIO_MASK (0xE0000000U) -#define CAN_ID_PRIO_SHIFT (29U) -#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) -/*! @} */ - -/* The count of CAN_ID */ -#define CAN_ID_COUNT (64U) - -/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ -/*! @{ */ -#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) -#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) -#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) -#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) -#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) -#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) -#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) -#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) -#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) -#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) -#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) -#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) -/*! @} */ - -/* The count of CAN_WORD0 */ -#define CAN_WORD0_COUNT (64U) - -/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ -/*! @{ */ -#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) -#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) -#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) -#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) -#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) -#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) -#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) -#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) -#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) -#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) -#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) -#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) -/*! @} */ - -/* The count of CAN_WORD1 */ -#define CAN_WORD1_COUNT (64U) - -/*! @name RXIMR - Rx Individual Mask Registers */ -/*! @{ */ -#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) -#define CAN_RXIMR_MI_SHIFT (0U) -#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) -/*! @} */ - -/* The count of CAN_RXIMR */ -#define CAN_RXIMR_COUNT (64U) - -/*! @name GFWR - Glitch Filter Width Registers */ -/*! @{ */ -#define CAN_GFWR_GFWR_MASK (0xFFU) -#define CAN_GFWR_GFWR_SHIFT (0U) -#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CAN_Register_Masks */ - - -/* CAN - Peripheral instance base addresses */ -/** Peripheral CAN1 base address */ -#define CAN1_BASE (0x401D0000u) -/** Peripheral CAN1 base pointer */ -#define CAN1 ((CAN_Type *)CAN1_BASE) -/** Peripheral CAN2 base address */ -#define CAN2_BASE (0x401D4000u) -/** Peripheral CAN2 base pointer */ -#define CAN2 ((CAN_Type *)CAN2_BASE) -/** Array initializer of CAN peripheral base addresses */ -#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE } -/** Array initializer of CAN peripheral base pointers */ -#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 } -/** Interrupt vectors for the CAN peripheral type */ -#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } -#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } -#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } -#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } -#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } -#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } -/* Backward compatibility */ -#define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK -#define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT -#define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x) -#define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK -#define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT -#define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x) - - -/*! - * @} - */ /* end of group CAN_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CCM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer - * @{ - */ - -/** CCM - Register Layout Typedef */ -typedef struct { - __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */ - uint8_t RESERVED_0[4]; - __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */ - __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */ - __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */ - __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */ - __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */ - __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */ - __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */ - __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */ - __IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */ - __IO uint32_t CS2CDR; /**< CCM Clock Divider Register, offset: 0x2C */ - __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */ - uint8_t RESERVED_1[4]; - __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */ - __IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */ - uint8_t RESERVED_2[8]; - __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */ - uint8_t RESERVED_3[8]; - __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */ - __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */ - __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ - __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */ - __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */ - __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */ - __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */ - __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */ - __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */ - __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */ - __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */ - __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */ - uint8_t RESERVED_4[4]; - __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */ -} CCM_Type; - -/* ---------------------------------------------------------------------------- - -- CCM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CCM_Register_Masks CCM Register Masks - * @{ - */ - -/*! @name CCR - CCM Control Register */ -/*! @{ */ -#define CCM_CCR_OSCNT_MASK (0xFFU) -#define CCM_CCR_OSCNT_SHIFT (0U) -#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) -#define CCM_CCR_COSC_EN_MASK (0x1000U) -#define CCM_CCR_COSC_EN_SHIFT (12U) -#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK) -#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U) -#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U) -#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK) -#define CCM_CCR_RBC_EN_MASK (0x8000000U) -#define CCM_CCR_RBC_EN_SHIFT (27U) -#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) -/*! @} */ - -/*! @name CSR - CCM Status Register */ -/*! @{ */ -#define CCM_CSR_REF_EN_B_MASK (0x1U) -#define CCM_CSR_REF_EN_B_SHIFT (0U) -#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) -#define CCM_CSR_CAMP2_READY_MASK (0x8U) -#define CCM_CSR_CAMP2_READY_SHIFT (3U) -#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK) -#define CCM_CSR_COSC_READY_MASK (0x20U) -#define CCM_CSR_COSC_READY_SHIFT (5U) -#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) -/*! @} */ - -/*! @name CCSR - CCM Clock Switcher Register */ -/*! @{ */ -#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) -#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) -#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) -/*! @} */ - -/*! @name CACRR - CCM Arm Clock Root Register */ -/*! @{ */ -#define CCM_CACRR_ARM_PODF_MASK (0x7U) -#define CCM_CACRR_ARM_PODF_SHIFT (0U) -#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) -/*! @} */ - -/*! @name CBCDR - CCM Bus Clock Divider Register */ -/*! @{ */ -#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U) -#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U) -#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK) -#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U) -#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U) -#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) -#define CCM_CBCDR_IPG_PODF_MASK (0x300U) -#define CCM_CBCDR_IPG_PODF_SHIFT (8U) -#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK) -#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U) -#define CCM_CBCDR_AHB_PODF_SHIFT (10U) -#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK) -#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U) -#define CCM_CBCDR_SEMC_PODF_SHIFT (16U) -#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK) -#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U) -#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U) -#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK) -#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) -#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) -#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) -/*! @} */ - -/*! @name CBCMR - CCM Bus Clock Multiplexer Register */ -/*! @{ */ -#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U) -#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U) -#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK) -#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U) -#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U) -#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) -#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U) -#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U) -#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK) -#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U) -#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U) -#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) -#define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U) -#define CCM_CBCMR_LCDIF_PODF_SHIFT (23U) -#define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK) -#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U) -#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U) -#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK) -/*! @} */ - -/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ -/*! @{ */ -#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) -#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) -#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) -#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U) -#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U) -#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) -#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U) -#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U) -#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK) -#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U) -#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U) -#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK) -#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U) -#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U) -#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK) -#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U) -#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U) -#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK) -#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U) -#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U) -#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK) -#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U) -#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U) -#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK) -#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U) -#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U) -#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK) -/*! @} */ - -/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ -/*! @{ */ -#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU) -#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U) -#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK) -#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U) -#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U) -#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK) -#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U) -#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U) -#define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK) -/*! @} */ - -/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ -/*! @{ */ -#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) -#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) -#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) -#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U) -#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U) -#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK) -#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U) -#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U) -#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK) -#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U) -#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U) -#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK) -#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U) -#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U) -#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK) -/*! @} */ - -/*! @name CS1CDR - CCM Clock Divider Register */ -/*! @{ */ -#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) -#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) -#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) -#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U) -#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U) -#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK) -#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U) -#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U) -#define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK) -#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U) -#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U) -#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK) -#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U) -#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U) -#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK) -#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U) -#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U) -#define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK) -/*! @} */ - -/*! @name CS2CDR - CCM Clock Divider Register */ -/*! @{ */ -#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) -#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) -#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) -#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) -#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) -#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) -/*! @} */ - -/*! @name CDCDR - CCM D1 Clock Divider Register */ -/*! @{ */ -#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U) -#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U) -#define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK) -#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U) -#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U) -#define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK) -#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U) -#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U) -#define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK) -#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U) -#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U) -#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK) -#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U) -#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U) -#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK) -#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) -#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) -#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) -/*! @} */ - -/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ -/*! @{ */ -#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U) -#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U) -#define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK) -#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U) -#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U) -#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) -#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U) -#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U) -#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK) -#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U) -#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U) -#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK) -/*! @} */ - -/*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */ -/*! @{ */ -#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U) -#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U) -#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK) -#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U) -#define CCM_CSCDR3_CSI_PODF_SHIFT (11U) -#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK) -/*! @} */ - -/*! @name CDHIPR - CCM Divider Handshake In-Process Register */ -/*! @{ */ -#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U) -#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U) -#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK) -#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U) -#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U) -#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK) -#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U) -#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U) -#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK) -#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U) -#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U) -#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK) -#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) -#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) -#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) -/*! @} */ - -/*! @name CLPCR - CCM Low Power Control Register */ -/*! @{ */ -#define CCM_CLPCR_LPM_MASK (0x3U) -#define CCM_CLPCR_LPM_SHIFT (0U) -#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) -#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U) -#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U) -#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK) -#define CCM_CLPCR_SBYOS_MASK (0x40U) -#define CCM_CLPCR_SBYOS_SHIFT (6U) -#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK) -#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U) -#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U) -#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK) -#define CCM_CLPCR_VSTBY_MASK (0x100U) -#define CCM_CLPCR_VSTBY_SHIFT (8U) -#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK) -#define CCM_CLPCR_STBY_COUNT_MASK (0x600U) -#define CCM_CLPCR_STBY_COUNT_SHIFT (9U) -#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK) -#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U) -#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U) -#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK) -#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U) -#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U) -#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK) -#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U) -#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U) -#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK) -#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U) -#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U) -#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK) -#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U) -#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U) -#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK) -#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) -#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) -#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) -/*! @} */ - -/*! @name CISR - CCM Interrupt Status Register */ -/*! @{ */ -#define CCM_CISR_LRF_PLL_MASK (0x1U) -#define CCM_CISR_LRF_PLL_SHIFT (0U) -#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) -#define CCM_CISR_COSC_READY_MASK (0x40U) -#define CCM_CISR_COSC_READY_SHIFT (6U) -#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK) -#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U) -#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U) -#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK) -#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) -#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) -#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK) -#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U) -#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U) -#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK) -#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) -#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U) -#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK) -#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) -#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) -#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) -/*! @} */ - -/*! @name CIMR - CCM Interrupt Mask Register */ -/*! @{ */ -#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) -#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) -#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) -#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U) -#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U) -#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK) -#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U) -#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U) -#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK) -#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) -#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) -#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK) -#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U) -#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U) -#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK) -#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) -#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U) -#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK) -#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) -#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) -#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) -/*! @} */ - -/*! @name CCOSR - CCM Clock Output Source Register */ -/*! @{ */ -#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU) -#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U) -#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK) -#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U) -#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U) -#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK) -#define CCM_CCOSR_CLKO1_EN_MASK (0x80U) -#define CCM_CCOSR_CLKO1_EN_SHIFT (7U) -#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK) -#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U) -#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U) -#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK) -#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U) -#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U) -#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK) -#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U) -#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U) -#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) -#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) -#define CCM_CCOSR_CLKO2_EN_SHIFT (24U) -#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) -/*! @} */ - -/*! @name CGPR - CCM General Purpose Register */ -/*! @{ */ -#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) -#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) -#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) -#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) -#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) -#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) -#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) -#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) -#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) -#define CCM_CGPR_FPL_MASK (0x10000U) -#define CCM_CGPR_FPL_SHIFT (16U) -#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) -#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) -#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) -#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) -/*! @} */ - -/*! @name CCGR0 - CCM Clock Gating Register 0 */ -/*! @{ */ -#define CCM_CCGR0_CG0_MASK (0x3U) -#define CCM_CCGR0_CG0_SHIFT (0U) -#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) -#define CCM_CCGR0_CG1_MASK (0xCU) -#define CCM_CCGR0_CG1_SHIFT (2U) -#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK) -#define CCM_CCGR0_CG2_MASK (0x30U) -#define CCM_CCGR0_CG2_SHIFT (4U) -#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK) -#define CCM_CCGR0_CG3_MASK (0xC0U) -#define CCM_CCGR0_CG3_SHIFT (6U) -#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK) -#define CCM_CCGR0_CG4_MASK (0x300U) -#define CCM_CCGR0_CG4_SHIFT (8U) -#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK) -#define CCM_CCGR0_CG5_MASK (0xC00U) -#define CCM_CCGR0_CG5_SHIFT (10U) -#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK) -#define CCM_CCGR0_CG6_MASK (0x3000U) -#define CCM_CCGR0_CG6_SHIFT (12U) -#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK) -#define CCM_CCGR0_CG7_MASK (0xC000U) -#define CCM_CCGR0_CG7_SHIFT (14U) -#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK) -#define CCM_CCGR0_CG8_MASK (0x30000U) -#define CCM_CCGR0_CG8_SHIFT (16U) -#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK) -#define CCM_CCGR0_CG9_MASK (0xC0000U) -#define CCM_CCGR0_CG9_SHIFT (18U) -#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK) -#define CCM_CCGR0_CG10_MASK (0x300000U) -#define CCM_CCGR0_CG10_SHIFT (20U) -#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK) -#define CCM_CCGR0_CG11_MASK (0xC00000U) -#define CCM_CCGR0_CG11_SHIFT (22U) -#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK) -#define CCM_CCGR0_CG12_MASK (0x3000000U) -#define CCM_CCGR0_CG12_SHIFT (24U) -#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK) -#define CCM_CCGR0_CG13_MASK (0xC000000U) -#define CCM_CCGR0_CG13_SHIFT (26U) -#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK) -#define CCM_CCGR0_CG14_MASK (0x30000000U) -#define CCM_CCGR0_CG14_SHIFT (28U) -#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK) -#define CCM_CCGR0_CG15_MASK (0xC0000000U) -#define CCM_CCGR0_CG15_SHIFT (30U) -#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) -/*! @} */ - -/*! @name CCGR1 - CCM Clock Gating Register 1 */ -/*! @{ */ -#define CCM_CCGR1_CG0_MASK (0x3U) -#define CCM_CCGR1_CG0_SHIFT (0U) -#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) -#define CCM_CCGR1_CG1_MASK (0xCU) -#define CCM_CCGR1_CG1_SHIFT (2U) -#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK) -#define CCM_CCGR1_CG2_MASK (0x30U) -#define CCM_CCGR1_CG2_SHIFT (4U) -#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK) -#define CCM_CCGR1_CG3_MASK (0xC0U) -#define CCM_CCGR1_CG3_SHIFT (6U) -#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK) -#define CCM_CCGR1_CG4_MASK (0x300U) -#define CCM_CCGR1_CG4_SHIFT (8U) -#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK) -#define CCM_CCGR1_CG5_MASK (0xC00U) -#define CCM_CCGR1_CG5_SHIFT (10U) -#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK) -#define CCM_CCGR1_CG6_MASK (0x3000U) -#define CCM_CCGR1_CG6_SHIFT (12U) -#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK) -#define CCM_CCGR1_CG7_MASK (0xC000U) -#define CCM_CCGR1_CG7_SHIFT (14U) -#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK) -#define CCM_CCGR1_CG8_MASK (0x30000U) -#define CCM_CCGR1_CG8_SHIFT (16U) -#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK) -#define CCM_CCGR1_CG9_MASK (0xC0000U) -#define CCM_CCGR1_CG9_SHIFT (18U) -#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK) -#define CCM_CCGR1_CG10_MASK (0x300000U) -#define CCM_CCGR1_CG10_SHIFT (20U) -#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK) -#define CCM_CCGR1_CG11_MASK (0xC00000U) -#define CCM_CCGR1_CG11_SHIFT (22U) -#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK) -#define CCM_CCGR1_CG12_MASK (0x3000000U) -#define CCM_CCGR1_CG12_SHIFT (24U) -#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK) -#define CCM_CCGR1_CG13_MASK (0xC000000U) -#define CCM_CCGR1_CG13_SHIFT (26U) -#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK) -#define CCM_CCGR1_CG14_MASK (0x30000000U) -#define CCM_CCGR1_CG14_SHIFT (28U) -#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK) -#define CCM_CCGR1_CG15_MASK (0xC0000000U) -#define CCM_CCGR1_CG15_SHIFT (30U) -#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) -/*! @} */ - -/*! @name CCGR2 - CCM Clock Gating Register 2 */ -/*! @{ */ -#define CCM_CCGR2_CG0_MASK (0x3U) -#define CCM_CCGR2_CG0_SHIFT (0U) -#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) -#define CCM_CCGR2_CG1_MASK (0xCU) -#define CCM_CCGR2_CG1_SHIFT (2U) -#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK) -#define CCM_CCGR2_CG2_MASK (0x30U) -#define CCM_CCGR2_CG2_SHIFT (4U) -#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK) -#define CCM_CCGR2_CG3_MASK (0xC0U) -#define CCM_CCGR2_CG3_SHIFT (6U) -#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK) -#define CCM_CCGR2_CG4_MASK (0x300U) -#define CCM_CCGR2_CG4_SHIFT (8U) -#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK) -#define CCM_CCGR2_CG5_MASK (0xC00U) -#define CCM_CCGR2_CG5_SHIFT (10U) -#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK) -#define CCM_CCGR2_CG6_MASK (0x3000U) -#define CCM_CCGR2_CG6_SHIFT (12U) -#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK) -#define CCM_CCGR2_CG7_MASK (0xC000U) -#define CCM_CCGR2_CG7_SHIFT (14U) -#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK) -#define CCM_CCGR2_CG8_MASK (0x30000U) -#define CCM_CCGR2_CG8_SHIFT (16U) -#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK) -#define CCM_CCGR2_CG9_MASK (0xC0000U) -#define CCM_CCGR2_CG9_SHIFT (18U) -#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK) -#define CCM_CCGR2_CG10_MASK (0x300000U) -#define CCM_CCGR2_CG10_SHIFT (20U) -#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK) -#define CCM_CCGR2_CG11_MASK (0xC00000U) -#define CCM_CCGR2_CG11_SHIFT (22U) -#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK) -#define CCM_CCGR2_CG12_MASK (0x3000000U) -#define CCM_CCGR2_CG12_SHIFT (24U) -#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK) -#define CCM_CCGR2_CG13_MASK (0xC000000U) -#define CCM_CCGR2_CG13_SHIFT (26U) -#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK) -#define CCM_CCGR2_CG14_MASK (0x30000000U) -#define CCM_CCGR2_CG14_SHIFT (28U) -#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK) -#define CCM_CCGR2_CG15_MASK (0xC0000000U) -#define CCM_CCGR2_CG15_SHIFT (30U) -#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) -/*! @} */ - -/*! @name CCGR3 - CCM Clock Gating Register 3 */ -/*! @{ */ -#define CCM_CCGR3_CG0_MASK (0x3U) -#define CCM_CCGR3_CG0_SHIFT (0U) -#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) -#define CCM_CCGR3_CG1_MASK (0xCU) -#define CCM_CCGR3_CG1_SHIFT (2U) -#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK) -#define CCM_CCGR3_CG2_MASK (0x30U) -#define CCM_CCGR3_CG2_SHIFT (4U) -#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK) -#define CCM_CCGR3_CG3_MASK (0xC0U) -#define CCM_CCGR3_CG3_SHIFT (6U) -#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK) -#define CCM_CCGR3_CG4_MASK (0x300U) -#define CCM_CCGR3_CG4_SHIFT (8U) -#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK) -#define CCM_CCGR3_CG5_MASK (0xC00U) -#define CCM_CCGR3_CG5_SHIFT (10U) -#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK) -#define CCM_CCGR3_CG6_MASK (0x3000U) -#define CCM_CCGR3_CG6_SHIFT (12U) -#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK) -#define CCM_CCGR3_CG7_MASK (0xC000U) -#define CCM_CCGR3_CG7_SHIFT (14U) -#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK) -#define CCM_CCGR3_CG8_MASK (0x30000U) -#define CCM_CCGR3_CG8_SHIFT (16U) -#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK) -#define CCM_CCGR3_CG9_MASK (0xC0000U) -#define CCM_CCGR3_CG9_SHIFT (18U) -#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK) -#define CCM_CCGR3_CG10_MASK (0x300000U) -#define CCM_CCGR3_CG10_SHIFT (20U) -#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK) -#define CCM_CCGR3_CG11_MASK (0xC00000U) -#define CCM_CCGR3_CG11_SHIFT (22U) -#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK) -#define CCM_CCGR3_CG12_MASK (0x3000000U) -#define CCM_CCGR3_CG12_SHIFT (24U) -#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK) -#define CCM_CCGR3_CG13_MASK (0xC000000U) -#define CCM_CCGR3_CG13_SHIFT (26U) -#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK) -#define CCM_CCGR3_CG14_MASK (0x30000000U) -#define CCM_CCGR3_CG14_SHIFT (28U) -#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK) -#define CCM_CCGR3_CG15_MASK (0xC0000000U) -#define CCM_CCGR3_CG15_SHIFT (30U) -#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) -/*! @} */ - -/*! @name CCGR4 - CCM Clock Gating Register 4 */ -/*! @{ */ -#define CCM_CCGR4_CG0_MASK (0x3U) -#define CCM_CCGR4_CG0_SHIFT (0U) -#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) -#define CCM_CCGR4_CG1_MASK (0xCU) -#define CCM_CCGR4_CG1_SHIFT (2U) -#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK) -#define CCM_CCGR4_CG2_MASK (0x30U) -#define CCM_CCGR4_CG2_SHIFT (4U) -#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK) -#define CCM_CCGR4_CG3_MASK (0xC0U) -#define CCM_CCGR4_CG3_SHIFT (6U) -#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK) -#define CCM_CCGR4_CG4_MASK (0x300U) -#define CCM_CCGR4_CG4_SHIFT (8U) -#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK) -#define CCM_CCGR4_CG5_MASK (0xC00U) -#define CCM_CCGR4_CG5_SHIFT (10U) -#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK) -#define CCM_CCGR4_CG6_MASK (0x3000U) -#define CCM_CCGR4_CG6_SHIFT (12U) -#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK) -#define CCM_CCGR4_CG7_MASK (0xC000U) -#define CCM_CCGR4_CG7_SHIFT (14U) -#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK) -#define CCM_CCGR4_CG8_MASK (0x30000U) -#define CCM_CCGR4_CG8_SHIFT (16U) -#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK) -#define CCM_CCGR4_CG9_MASK (0xC0000U) -#define CCM_CCGR4_CG9_SHIFT (18U) -#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK) -#define CCM_CCGR4_CG10_MASK (0x300000U) -#define CCM_CCGR4_CG10_SHIFT (20U) -#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK) -#define CCM_CCGR4_CG11_MASK (0xC00000U) -#define CCM_CCGR4_CG11_SHIFT (22U) -#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK) -#define CCM_CCGR4_CG12_MASK (0x3000000U) -#define CCM_CCGR4_CG12_SHIFT (24U) -#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK) -#define CCM_CCGR4_CG13_MASK (0xC000000U) -#define CCM_CCGR4_CG13_SHIFT (26U) -#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK) -#define CCM_CCGR4_CG14_MASK (0x30000000U) -#define CCM_CCGR4_CG14_SHIFT (28U) -#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK) -#define CCM_CCGR4_CG15_MASK (0xC0000000U) -#define CCM_CCGR4_CG15_SHIFT (30U) -#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) -/*! @} */ - -/*! @name CCGR5 - CCM Clock Gating Register 5 */ -/*! @{ */ -#define CCM_CCGR5_CG0_MASK (0x3U) -#define CCM_CCGR5_CG0_SHIFT (0U) -#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) -#define CCM_CCGR5_CG1_MASK (0xCU) -#define CCM_CCGR5_CG1_SHIFT (2U) -#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK) -#define CCM_CCGR5_CG2_MASK (0x30U) -#define CCM_CCGR5_CG2_SHIFT (4U) -#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK) -#define CCM_CCGR5_CG3_MASK (0xC0U) -#define CCM_CCGR5_CG3_SHIFT (6U) -#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK) -#define CCM_CCGR5_CG4_MASK (0x300U) -#define CCM_CCGR5_CG4_SHIFT (8U) -#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK) -#define CCM_CCGR5_CG5_MASK (0xC00U) -#define CCM_CCGR5_CG5_SHIFT (10U) -#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK) -#define CCM_CCGR5_CG6_MASK (0x3000U) -#define CCM_CCGR5_CG6_SHIFT (12U) -#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK) -#define CCM_CCGR5_CG7_MASK (0xC000U) -#define CCM_CCGR5_CG7_SHIFT (14U) -#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK) -#define CCM_CCGR5_CG8_MASK (0x30000U) -#define CCM_CCGR5_CG8_SHIFT (16U) -#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK) -#define CCM_CCGR5_CG9_MASK (0xC0000U) -#define CCM_CCGR5_CG9_SHIFT (18U) -#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK) -#define CCM_CCGR5_CG10_MASK (0x300000U) -#define CCM_CCGR5_CG10_SHIFT (20U) -#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK) -#define CCM_CCGR5_CG11_MASK (0xC00000U) -#define CCM_CCGR5_CG11_SHIFT (22U) -#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK) -#define CCM_CCGR5_CG12_MASK (0x3000000U) -#define CCM_CCGR5_CG12_SHIFT (24U) -#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK) -#define CCM_CCGR5_CG13_MASK (0xC000000U) -#define CCM_CCGR5_CG13_SHIFT (26U) -#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK) -#define CCM_CCGR5_CG14_MASK (0x30000000U) -#define CCM_CCGR5_CG14_SHIFT (28U) -#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK) -#define CCM_CCGR5_CG15_MASK (0xC0000000U) -#define CCM_CCGR5_CG15_SHIFT (30U) -#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) -/*! @} */ - -/*! @name CCGR6 - CCM Clock Gating Register 6 */ -/*! @{ */ -#define CCM_CCGR6_CG0_MASK (0x3U) -#define CCM_CCGR6_CG0_SHIFT (0U) -#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) -#define CCM_CCGR6_CG1_MASK (0xCU) -#define CCM_CCGR6_CG1_SHIFT (2U) -#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK) -#define CCM_CCGR6_CG2_MASK (0x30U) -#define CCM_CCGR6_CG2_SHIFT (4U) -#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK) -#define CCM_CCGR6_CG3_MASK (0xC0U) -#define CCM_CCGR6_CG3_SHIFT (6U) -#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK) -#define CCM_CCGR6_CG4_MASK (0x300U) -#define CCM_CCGR6_CG4_SHIFT (8U) -#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK) -#define CCM_CCGR6_CG5_MASK (0xC00U) -#define CCM_CCGR6_CG5_SHIFT (10U) -#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK) -#define CCM_CCGR6_CG6_MASK (0x3000U) -#define CCM_CCGR6_CG6_SHIFT (12U) -#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK) -#define CCM_CCGR6_CG7_MASK (0xC000U) -#define CCM_CCGR6_CG7_SHIFT (14U) -#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK) -#define CCM_CCGR6_CG8_MASK (0x30000U) -#define CCM_CCGR6_CG8_SHIFT (16U) -#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK) -#define CCM_CCGR6_CG9_MASK (0xC0000U) -#define CCM_CCGR6_CG9_SHIFT (18U) -#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK) -#define CCM_CCGR6_CG10_MASK (0x300000U) -#define CCM_CCGR6_CG10_SHIFT (20U) -#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK) -#define CCM_CCGR6_CG11_MASK (0xC00000U) -#define CCM_CCGR6_CG11_SHIFT (22U) -#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK) -#define CCM_CCGR6_CG12_MASK (0x3000000U) -#define CCM_CCGR6_CG12_SHIFT (24U) -#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK) -#define CCM_CCGR6_CG13_MASK (0xC000000U) -#define CCM_CCGR6_CG13_SHIFT (26U) -#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK) -#define CCM_CCGR6_CG14_MASK (0x30000000U) -#define CCM_CCGR6_CG14_SHIFT (28U) -#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK) -#define CCM_CCGR6_CG15_MASK (0xC0000000U) -#define CCM_CCGR6_CG15_SHIFT (30U) -#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) -/*! @} */ - -/*! @name CMEOR - CCM Module Enable Overide Register */ -/*! @{ */ -#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) -#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) -#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) -#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U) -#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U) -#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK) -#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U) -#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U) -#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK) -#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U) -#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U) -#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK) -#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U) -#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U) -#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK) -#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U) -#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U) -#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CCM_Register_Masks */ - - -/* CCM - Peripheral instance base addresses */ -/** Peripheral CCM base address */ -#define CCM_BASE (0x400FC000u) -/** Peripheral CCM base pointer */ -#define CCM ((CCM_Type *)CCM_BASE) -/** Array initializer of CCM peripheral base addresses */ -#define CCM_BASE_ADDRS { CCM_BASE } -/** Array initializer of CCM peripheral base pointers */ -#define CCM_BASE_PTRS { CCM } -/** Interrupt vectors for the CCM peripheral type */ -#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn } - -/*! - * @} - */ /* end of group CCM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CCM_ANALOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer - * @{ - */ - -/** CCM_ANALOG - Register Layout Typedef */ -typedef struct { - __IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */ - __IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */ - __IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */ - __IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */ - __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */ - __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */ - __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */ - __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */ - __IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */ - __IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */ - __IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */ - __IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */ - __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */ - __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */ - __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */ - __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */ - __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */ - uint8_t RESERVED_0[12]; - __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */ - uint8_t RESERVED_1[12]; - __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */ - uint8_t RESERVED_2[12]; - __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */ - __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */ - __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */ - __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */ - __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */ - uint8_t RESERVED_3[12]; - __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */ - uint8_t RESERVED_4[12]; - __IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */ - __IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */ - __IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */ - __IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */ - __IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */ - uint8_t RESERVED_5[12]; - __IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */ - uint8_t RESERVED_6[28]; - __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */ - __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */ - __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */ - __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */ - __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */ - __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */ - __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */ - __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */ - __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */ - __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */ - __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */ - __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */ - uint8_t RESERVED_7[64]; - __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ - __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ - __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ - __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ - __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ - __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ - __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ - __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ - __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */ - __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */ - __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */ - __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */ -} CCM_ANALOG_Type; - -/* ---------------------------------------------------------------------------- - -- CCM_ANALOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks - * @{ - */ - -/*! @name PLL_ARM - Analog ARM PLL control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU) -#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK) -#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK) -#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U) -#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U) -#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK) -#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK) -/*! @} */ - -/*! @name PLL_ARM_SET - Analog ARM PLL control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU) -#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK) -#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK) -#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U) -#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U) -#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK) -#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK) -/*! @} */ - -/*! @name PLL_ARM_CLR - Analog ARM PLL control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU) -#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK) -#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK) -#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U) -#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U) -#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK) -#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK) -/*! @} */ - -/*! @name PLL_ARM_TOG - Analog ARM PLL control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU) -#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK) -#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK) -#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U) -#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U) -#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK) -#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK) -/*! @} */ - -/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U) -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U) -#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) -#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) -#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK) -#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U) -#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U) -#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK) -#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK) -#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK) -#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) -/*! @} */ - -/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U) -#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U) -#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) -#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) -#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK) -#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U) -#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U) -#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK) -#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK) -#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK) -#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) -/*! @} */ - -/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U) -#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U) -#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) -#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) -#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK) -#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U) -#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U) -#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK) -#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK) -#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK) -#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) -/*! @} */ - -/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U) -#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U) -#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) -#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) -#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK) -#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U) -#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U) -#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK) -#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK) -#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK) -#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) -/*! @} */ - -/*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U) -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U) -#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U) -#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U) -#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK) -#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U) -#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U) -#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK) -#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK) -#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK) -#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK) -/*! @} */ - -/*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U) -#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U) -#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U) -#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U) -#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK) -#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U) -#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U) -#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK) -#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK) -#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK) -#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK) -/*! @} */ - -/*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U) -#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U) -#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U) -#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U) -#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK) -#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U) -#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U) -#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK) -#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK) -#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK) -#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK) -/*! @} */ - -/*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U) -#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U) -#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U) -#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U) -#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK) -#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U) -#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U) -#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK) -#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK) -#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK) -#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SYS - Analog System PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) -#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK) -#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK) -#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SYS_SET - Analog System PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) -#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK) -#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK) -#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SYS_CLR - Analog System PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) -#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) -#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK) -#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SYS_TOG - Analog System PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) -#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) -#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK) -#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) -/*! @} */ - -/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) -#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) -#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) -#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) -#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) -#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) -#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) -#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) -#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) -/*! @} */ - -/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) -#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) -#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) -/*! @} */ - -/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) -#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) -#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) -/*! @} */ - -/*! @name PLL_AUDIO - Analog Audio PLL control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK) -#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) -/*! @} */ - -/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) -#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) -#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK) -#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) -#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) -#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) -/*! @} */ - -/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) -#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK) -#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK) -#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U) -#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U) -#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) -/*! @} */ - -/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) -#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK) -#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK) -#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U) -#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U) -#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) -/*! @} */ - -/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) -#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) -#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) -/*! @} */ - -/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) -#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) -#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) -/*! @} */ - -/*! @name PLL_VIDEO - Analog Video PLL control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU) -#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK) -#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK) -#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U) -#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U) -#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) -/*! @} */ - -/*! @name PLL_VIDEO_SET - Analog Video PLL control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU) -#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK) -#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK) -#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U) -#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U) -#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK) -/*! @} */ - -/*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU) -#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK) -#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK) -#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U) -#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U) -#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK) -/*! @} */ - -/*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU) -#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK) -#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK) -#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U) -#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U) -#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK) -/*! @} */ - -/*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU) -#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U) -#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) -/*! @} */ - -/*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU) -#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U) -#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) -/*! @} */ - -/*! @name PLL_ENET - Analog ENET PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK) -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK) -#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U) -#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U) -#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK) -#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) -/*! @} */ - -/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK) -#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK) -#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U) -#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U) -#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK) -#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) -/*! @} */ - -/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U) -#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK) -#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) -/*! @} */ - -/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ -/*! @{ */ -#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U) -#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U) -#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) -#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) -#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U) -#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U) -#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) -#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U) -#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U) -#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U) -#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U) -#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK) -#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) -#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) -#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) -/*! @} */ - -/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ -/*! @{ */ -#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) -#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) -#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) -#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U) -#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U) -#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK) -#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U) -#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U) -#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK) -#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U) -#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U) -#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) -#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U) -#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U) -#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK) -#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U) -#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U) -#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK) -#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U) -#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U) -#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) -#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U) -#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U) -#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK) -#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U) -#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U) -#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK) -#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U) -#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U) -#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) -#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U) -#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U) -#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK) -#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) -#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) -#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) -/*! @} */ - -/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ -/*! @{ */ -#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) -#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) -#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) -#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U) -#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U) -#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK) -#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U) -#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U) -#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK) -#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U) -#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U) -#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK) -#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U) -#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U) -#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK) -#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U) -#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U) -#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK) -#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U) -#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U) -#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK) -#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U) -#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U) -#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK) -#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U) -#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U) -#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK) -#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U) -#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U) -#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK) -#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U) -#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U) -#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK) -#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) -#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) -#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) -/*! @} */ - -/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ -/*! @{ */ -#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) -#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) -#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) -#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U) -#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U) -#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK) -#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U) -#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U) -#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK) -#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U) -#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U) -#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK) -#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U) -#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U) -#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK) -#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U) -#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U) -#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK) -#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U) -#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U) -#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK) -#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U) -#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U) -#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK) -#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U) -#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U) -#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK) -#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U) -#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U) -#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK) -#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U) -#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U) -#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK) -#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) -#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) -#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) -/*! @} */ - -/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ -/*! @{ */ -#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) -#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) -#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) -#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U) -#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U) -#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK) -#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U) -#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U) -#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK) -#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U) -#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U) -#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK) -#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U) -#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U) -#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK) -#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U) -#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U) -#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK) -#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U) -#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U) -#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK) -#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U) -#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U) -#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK) -#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U) -#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U) -#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK) -#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U) -#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U) -#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) -#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U) -#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U) -#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK) -#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) -#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) -#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) -/*! @} */ - -/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ -/*! @{ */ -#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) -#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) -#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) -#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U) -#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U) -#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK) -#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U) -#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U) -#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK) -#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U) -#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U) -#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) -#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U) -#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U) -#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK) -#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U) -#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U) -#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK) -#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U) -#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U) -#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) -#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U) -#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U) -#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK) -#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U) -#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U) -#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK) -#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U) -#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U) -#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) -#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U) -#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U) -#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK) -#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) -#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) -#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) -/*! @} */ - -/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ -/*! @{ */ -#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) -#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) -#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) -#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U) -#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U) -#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK) -#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U) -#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U) -#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK) -#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U) -#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U) -#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) -#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U) -#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U) -#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK) -#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U) -#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U) -#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK) -#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U) -#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U) -#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) -#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U) -#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U) -#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK) -#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U) -#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U) -#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK) -#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U) -#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U) -#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) -#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U) -#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U) -#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK) -#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) -#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) -#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) -/*! @} */ - -/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ -/*! @{ */ -#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) -#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) -#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) -#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U) -#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U) -#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK) -#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U) -#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U) -#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK) -#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U) -#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U) -#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) -#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U) -#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U) -#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK) -#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U) -#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U) -#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK) -#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U) -#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U) -#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) -#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U) -#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U) -#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK) -#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U) -#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U) -#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK) -#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U) -#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U) -#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK) -#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U) -#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U) -#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK) -#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) -#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) -#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) -/*! @} */ - -/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ -/*! @{ */ -#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) -#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) -#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) -#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U) -#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U) -#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK) -#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U) -#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U) -#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK) -#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U) -#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U) -#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK) -#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U) -#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U) -#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK) -#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U) -#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U) -#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK) -#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U) -#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U) -#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK) -#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U) -#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U) -#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK) -#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U) -#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U) -#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK) -#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U) -#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U) -#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK) -#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U) -#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U) -#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK) -#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) -#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) -#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) -/*! @} */ - -/*! @name MISC0 - Miscellaneous Register 0 */ -/*! @{ */ -#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) -#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) -#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) -#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) -#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) -#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK) -#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U) -#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U) -#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) -#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U) -#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U) -#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) -#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) -#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U) -#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) -#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) -#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) -#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK) -#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U) -#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U) -#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK) -#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U) -#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U) -#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) -#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U) -#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U) -#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK) -#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U) -#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U) -#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK) -#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) -#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U) -#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) -#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) -#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) -#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK) -#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) -#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) -#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) -/*! @} */ - -/*! @name MISC0_SET - Miscellaneous Register 0 */ -/*! @{ */ -#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) -#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) -#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) -#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) -#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) -#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK) -#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) -#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) -#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) -#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) -#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) -#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK) -#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) -#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) -#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) -#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) -#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) -#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK) -#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U) -#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U) -#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK) -#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U) -#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U) -#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK) -#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) -#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) -#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK) -#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) -#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) -#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK) -#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) -#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) -#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) -#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) -#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) -#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK) -#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) -#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) -#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) -/*! @} */ - -/*! @name MISC0_CLR - Miscellaneous Register 0 */ -/*! @{ */ -#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) -#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) -#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) -#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) -#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) -#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) -#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) -#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) -#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) -#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) -#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) -#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK) -#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) -#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) -#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) -#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) -#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) -#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK) -#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U) -#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U) -#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK) -#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) -#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U) -#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK) -#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) -#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) -#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK) -#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) -#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) -#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK) -#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) -#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) -#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) -#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) -#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) -#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK) -#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) -#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) -#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) -/*! @} */ - -/*! @name MISC0_TOG - Miscellaneous Register 0 */ -/*! @{ */ -#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) -#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) -#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) -#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) -#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) -#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) -#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) -#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) -#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) -#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) -#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) -#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK) -#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) -#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) -#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) -#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) -#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) -#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK) -#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U) -#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U) -#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK) -#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) -#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U) -#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK) -#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) -#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) -#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK) -#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) -#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) -#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK) -#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) -#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) -#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) -#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) -#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) -#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK) -#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) -#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) -#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) -/*! @} */ - -/*! @name MISC1 - Miscellaneous Register 1 */ -/*! @{ */ -#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) -#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U) -#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK) -#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U) -#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U) -#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK) -#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) -#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U) -#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK) -#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) -#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) -#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK) -#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) -#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) -#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK) -#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) -#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U) -#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK) -#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) -#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U) -#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK) -#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) -#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U) -#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK) -#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U) -#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U) -#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK) -#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) -#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) -#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) -/*! @} */ - -/*! @name MISC1_SET - Miscellaneous Register 1 */ -/*! @{ */ -#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) -#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) -#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK) -#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) -#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) -#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK) -#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) -#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) -#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK) -#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) -#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) -#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) -#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) -#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) -#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) -#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) -#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) -#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK) -#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) -#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) -#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK) -#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) -#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) -#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK) -#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) -#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) -#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK) -#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) -#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) -#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) -/*! @} */ - -/*! @name MISC1_CLR - Miscellaneous Register 1 */ -/*! @{ */ -#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) -#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) -#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK) -#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) -#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) -#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK) -#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) -#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) -#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK) -#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) -#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) -#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) -#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) -#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) -#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) -#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) -#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) -#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK) -#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) -#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) -#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK) -#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) -#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) -#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK) -#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) -#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) -#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK) -#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) -#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) -#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) -/*! @} */ - -/*! @name MISC1_TOG - Miscellaneous Register 1 */ -/*! @{ */ -#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) -#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) -#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK) -#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) -#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) -#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK) -#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) -#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) -#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK) -#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) -#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) -#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) -#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) -#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) -#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) -#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) -#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) -#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK) -#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) -#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) -#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK) -#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) -#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) -#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK) -#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) -#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) -#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK) -#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) -#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) -#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) -/*! @} */ - -/*! @name MISC2 - Miscellaneous Register 2 */ -/*! @{ */ -#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) -#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) -#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) -#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U) -#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U) -#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK) -#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U) -#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U) -#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK) -#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U) -#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U) -#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK) -#define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U) -#define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U) -#define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK) -#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U) -#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U) -#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) -#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U) -#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U) -#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK) -#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U) -#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U) -#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK) -#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U) -#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U) -#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK) -#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) -#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U) -#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK) -#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U) -#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U) -#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) -#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U) -#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U) -#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK) -#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U) -#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U) -#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK) -#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U) -#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U) -#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK) -#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) -#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U) -#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK) -#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U) -#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U) -#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) -#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U) -#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U) -#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) -#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U) -#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U) -#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) -#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U) -#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U) -#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) -/*! @} */ - -/*! @name MISC2_SET - Miscellaneous Register 2 */ -/*! @{ */ -#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) -#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) -#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) -#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) -#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) -#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK) -#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) -#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) -#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK) -#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U) -#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U) -#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK) -#define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U) -#define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U) -#define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK) -#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) -#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) -#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) -#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) -#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) -#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK) -#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) -#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) -#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK) -#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U) -#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U) -#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK) -#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) -#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) -#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK) -#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) -#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) -#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) -#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) -#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) -#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK) -#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) -#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) -#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK) -#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U) -#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U) -#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK) -#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) -#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) -#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK) -#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) -#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) -#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) -#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) -#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) -#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) -#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) -#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) -#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) -#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) -#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U) -#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK) -/*! @} */ - -/*! @name MISC2_CLR - Miscellaneous Register 2 */ -/*! @{ */ -#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) -#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) -#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) -#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) -#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) -#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK) -#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) -#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) -#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK) -#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U) -#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U) -#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK) -#define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U) -#define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U) -#define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK) -#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) -#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) -#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) -#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) -#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) -#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK) -#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) -#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) -#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK) -#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U) -#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U) -#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK) -#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) -#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) -#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK) -#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) -#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) -#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) -#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) -#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) -#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK) -#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) -#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) -#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK) -#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U) -#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U) -#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK) -#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) -#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) -#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK) -#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) -#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) -#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) -#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) -#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) -#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) -#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) -#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) -#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) -#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) -#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U) -#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK) -/*! @} */ - -/*! @name MISC2_TOG - Miscellaneous Register 2 */ -/*! @{ */ -#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) -#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) -#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) -#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) -#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) -#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK) -#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) -#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) -#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK) -#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U) -#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U) -#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK) -#define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U) -#define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U) -#define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK) -#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) -#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) -#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) -#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) -#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) -#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK) -#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) -#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) -#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK) -#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U) -#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U) -#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK) -#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) -#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) -#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK) -#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) -#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) -#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) -#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) -#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) -#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK) -#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) -#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) -#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK) -#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U) -#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U) -#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK) -#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) -#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) -#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK) -#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) -#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) -#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) -#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) -#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) -#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) -#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) -#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) -#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) -#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) -#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U) -#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CCM_ANALOG_Register_Masks */ - - -/* CCM_ANALOG - Peripheral instance base addresses */ -/** Peripheral CCM_ANALOG base address */ -#define CCM_ANALOG_BASE (0x400D8000u) -/** Peripheral CCM_ANALOG base pointer */ -#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) -/** Array initializer of CCM_ANALOG peripheral base addresses */ -#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } -/** Array initializer of CCM_ANALOG peripheral base pointers */ -#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } - -/*! - * @} - */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CMP Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer - * @{ - */ - -/** CMP - Register Layout Typedef */ -typedef struct { - __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ - __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ - __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ - __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ - __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ - __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ -} CMP_Type; - -/* ---------------------------------------------------------------------------- - -- CMP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CMP_Register_Masks CMP Register Masks - * @{ - */ - -/*! @name CR0 - CMP Control Register 0 */ -/*! @{ */ -#define CMP_CR0_HYSTCTR_MASK (0x3U) -#define CMP_CR0_HYSTCTR_SHIFT (0U) -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) -#define CMP_CR0_FILTER_CNT_MASK (0x70U) -#define CMP_CR0_FILTER_CNT_SHIFT (4U) -#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) -/*! @} */ - -/*! @name CR1 - CMP Control Register 1 */ -/*! @{ */ -#define CMP_CR1_EN_MASK (0x1U) -#define CMP_CR1_EN_SHIFT (0U) -#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) -#define CMP_CR1_OPE_MASK (0x2U) -#define CMP_CR1_OPE_SHIFT (1U) -#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) -#define CMP_CR1_COS_MASK (0x4U) -#define CMP_CR1_COS_SHIFT (2U) -#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) -#define CMP_CR1_INV_MASK (0x8U) -#define CMP_CR1_INV_SHIFT (3U) -#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) -#define CMP_CR1_PMODE_MASK (0x10U) -#define CMP_CR1_PMODE_SHIFT (4U) -#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) -#define CMP_CR1_WE_MASK (0x40U) -#define CMP_CR1_WE_SHIFT (6U) -#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) -#define CMP_CR1_SE_MASK (0x80U) -#define CMP_CR1_SE_SHIFT (7U) -#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) -/*! @} */ - -/*! @name FPR - CMP Filter Period Register */ -/*! @{ */ -#define CMP_FPR_FILT_PER_MASK (0xFFU) -#define CMP_FPR_FILT_PER_SHIFT (0U) -#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) -/*! @} */ - -/*! @name SCR - CMP Status and Control Register */ -/*! @{ */ -#define CMP_SCR_COUT_MASK (0x1U) -#define CMP_SCR_COUT_SHIFT (0U) -#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) -#define CMP_SCR_CFF_MASK (0x2U) -#define CMP_SCR_CFF_SHIFT (1U) -#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) -#define CMP_SCR_CFR_MASK (0x4U) -#define CMP_SCR_CFR_SHIFT (2U) -#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) -#define CMP_SCR_IEF_MASK (0x8U) -#define CMP_SCR_IEF_SHIFT (3U) -#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) -#define CMP_SCR_IER_MASK (0x10U) -#define CMP_SCR_IER_SHIFT (4U) -#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) -#define CMP_SCR_DMAEN_MASK (0x40U) -#define CMP_SCR_DMAEN_SHIFT (6U) -#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) -/*! @} */ - -/*! @name DACCR - DAC Control Register */ -/*! @{ */ -#define CMP_DACCR_VOSEL_MASK (0x3FU) -#define CMP_DACCR_VOSEL_SHIFT (0U) -#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) -#define CMP_DACCR_VRSEL_MASK (0x40U) -#define CMP_DACCR_VRSEL_SHIFT (6U) -#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) -#define CMP_DACCR_DACEN_MASK (0x80U) -#define CMP_DACCR_DACEN_SHIFT (7U) -#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) -/*! @} */ - -/*! @name MUXCR - MUX Control Register */ -/*! @{ */ -#define CMP_MUXCR_MSEL_MASK (0x7U) -#define CMP_MUXCR_MSEL_SHIFT (0U) -#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) -#define CMP_MUXCR_PSEL_MASK (0x38U) -#define CMP_MUXCR_PSEL_SHIFT (3U) -#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CMP_Register_Masks */ - - -/* CMP - Peripheral instance base addresses */ -/** Peripheral CMP1 base address */ -#define CMP1_BASE (0x40094000u) -/** Peripheral CMP1 base pointer */ -#define CMP1 ((CMP_Type *)CMP1_BASE) -/** Peripheral CMP2 base address */ -#define CMP2_BASE (0x40094008u) -/** Peripheral CMP2 base pointer */ -#define CMP2 ((CMP_Type *)CMP2_BASE) -/** Peripheral CMP3 base address */ -#define CMP3_BASE (0x40094010u) -/** Peripheral CMP3 base pointer */ -#define CMP3 ((CMP_Type *)CMP3_BASE) -/** Peripheral CMP4 base address */ -#define CMP4_BASE (0x40094018u) -/** Peripheral CMP4 base pointer */ -#define CMP4 ((CMP_Type *)CMP4_BASE) -/** Array initializer of CMP peripheral base addresses */ -#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE } -/** Array initializer of CMP peripheral base pointers */ -#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 } -/** Interrupt vectors for the CMP peripheral type */ -#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn } - -/*! - * @} - */ /* end of group CMP_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CSI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer - * @{ - */ - -/** CSI - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */ - __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */ - __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */ - __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */ - __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */ - __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */ - __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */ - __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */ - __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */ - __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */ - __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */ - __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */ - uint8_t RESERVED_1[16]; - __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */ - __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */ -} CSI_Type; - -/* ---------------------------------------------------------------------------- - -- CSI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CSI_Register_Masks CSI Register Masks - * @{ - */ - -/*! @name CSICR1 - CSI Control Register 1 */ -/*! @{ */ -#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U) -#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U) -#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK) -#define CSI_CSICR1_REDGE_MASK (0x2U) -#define CSI_CSICR1_REDGE_SHIFT (1U) -#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK) -#define CSI_CSICR1_INV_PCLK_MASK (0x4U) -#define CSI_CSICR1_INV_PCLK_SHIFT (2U) -#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK) -#define CSI_CSICR1_INV_DATA_MASK (0x8U) -#define CSI_CSICR1_INV_DATA_SHIFT (3U) -#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK) -#define CSI_CSICR1_GCLK_MODE_MASK (0x10U) -#define CSI_CSICR1_GCLK_MODE_SHIFT (4U) -#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK) -#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U) -#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U) -#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK) -#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U) -#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U) -#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK) -#define CSI_CSICR1_PACK_DIR_MASK (0x80U) -#define CSI_CSICR1_PACK_DIR_SHIFT (7U) -#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK) -#define CSI_CSICR1_FCC_MASK (0x100U) -#define CSI_CSICR1_FCC_SHIFT (8U) -#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK) -#define CSI_CSICR1_CCIR_EN_MASK (0x400U) -#define CSI_CSICR1_CCIR_EN_SHIFT (10U) -#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK) -#define CSI_CSICR1_HSYNC_POL_MASK (0x800U) -#define CSI_CSICR1_HSYNC_POL_SHIFT (11U) -#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK) -#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U) -#define CSI_CSICR1_SOF_INTEN_SHIFT (16U) -#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK) -#define CSI_CSICR1_SOF_POL_MASK (0x20000U) -#define CSI_CSICR1_SOF_POL_SHIFT (17U) -#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK) -#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U) -#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U) -#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK) -#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) -#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U) -#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK) -#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) -#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U) -#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK) -#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U) -#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U) -#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK) -#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) -#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U) -#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK) -#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U) -#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U) -#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK) -#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U) -#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U) -#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK) -#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U) -#define CSI_CSICR1_COF_INT_EN_SHIFT (26U) -#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK) -#define CSI_CSICR1_CCIR_MODE_MASK (0x8000000U) -#define CSI_CSICR1_CCIR_MODE_SHIFT (27U) -#define CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK) -#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U) -#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U) -#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK) -#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U) -#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U) -#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK) -#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U) -#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U) -#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK) -#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U) -#define CSI_CSICR1_SWAP16_EN_SHIFT (31U) -#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK) -/*! @} */ - -/*! @name CSICR2 - CSI Control Register 2 */ -/*! @{ */ -#define CSI_CSICR2_HSC_MASK (0xFFU) -#define CSI_CSICR2_HSC_SHIFT (0U) -#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK) -#define CSI_CSICR2_VSC_MASK (0xFF00U) -#define CSI_CSICR2_VSC_SHIFT (8U) -#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK) -#define CSI_CSICR2_LVRM_MASK (0x70000U) -#define CSI_CSICR2_LVRM_SHIFT (16U) -#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK) -#define CSI_CSICR2_BTS_MASK (0x180000U) -#define CSI_CSICR2_BTS_SHIFT (19U) -#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK) -#define CSI_CSICR2_SCE_MASK (0x800000U) -#define CSI_CSICR2_SCE_SHIFT (23U) -#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK) -#define CSI_CSICR2_AFS_MASK (0x3000000U) -#define CSI_CSICR2_AFS_SHIFT (24U) -#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK) -#define CSI_CSICR2_DRM_MASK (0x4000000U) -#define CSI_CSICR2_DRM_SHIFT (26U) -#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK) -#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) -#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U) -#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK) -#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) -#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U) -#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK) -/*! @} */ - -/*! @name CSICR3 - CSI Control Register 3 */ -/*! @{ */ -#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U) -#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U) -#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK) -#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U) -#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U) -#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK) -#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U) -#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U) -#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK) -#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U) -#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U) -#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK) -#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U) -#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U) -#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK) -#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U) -#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U) -#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK) -#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U) -#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U) -#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK) -#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U) -#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U) -#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK) -#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U) -#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U) -#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK) -#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U) -#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U) -#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK) -#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U) -#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U) -#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK) -#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U) -#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U) -#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK) -#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U) -#define CSI_CSICR3_FRMCNT_SHIFT (16U) -#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK) -/*! @} */ - -/*! @name CSISTATFIFO - CSI Statistic FIFO Register */ -/*! @{ */ -#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU) -#define CSI_CSISTATFIFO_STAT_SHIFT (0U) -#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK) -/*! @} */ - -/*! @name CSIRFIFO - CSI RX FIFO Register */ -/*! @{ */ -#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU) -#define CSI_CSIRFIFO_IMAGE_SHIFT (0U) -#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK) -/*! @} */ - -/*! @name CSIRXCNT - CSI RX Count Register */ -/*! @{ */ -#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU) -#define CSI_CSIRXCNT_RXCNT_SHIFT (0U) -#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK) -/*! @} */ - -/*! @name CSISR - CSI Status Register */ -/*! @{ */ -#define CSI_CSISR_DRDY_MASK (0x1U) -#define CSI_CSISR_DRDY_SHIFT (0U) -#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK) -#define CSI_CSISR_ECC_INT_MASK (0x2U) -#define CSI_CSISR_ECC_INT_SHIFT (1U) -#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK) -#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U) -#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U) -#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK) -#define CSI_CSISR_COF_INT_MASK (0x2000U) -#define CSI_CSISR_COF_INT_SHIFT (13U) -#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK) -#define CSI_CSISR_F1_INT_MASK (0x4000U) -#define CSI_CSISR_F1_INT_SHIFT (14U) -#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK) -#define CSI_CSISR_F2_INT_MASK (0x8000U) -#define CSI_CSISR_F2_INT_SHIFT (15U) -#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK) -#define CSI_CSISR_SOF_INT_MASK (0x10000U) -#define CSI_CSISR_SOF_INT_SHIFT (16U) -#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK) -#define CSI_CSISR_EOF_INT_MASK (0x20000U) -#define CSI_CSISR_EOF_INT_SHIFT (17U) -#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK) -#define CSI_CSISR_RxFF_INT_MASK (0x40000U) -#define CSI_CSISR_RxFF_INT_SHIFT (18U) -#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK) -#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U) -#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U) -#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) -#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U) -#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U) -#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK) -#define CSI_CSISR_STATFF_INT_MASK (0x200000U) -#define CSI_CSISR_STATFF_INT_SHIFT (21U) -#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK) -#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U) -#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U) -#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK) -#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U) -#define CSI_CSISR_RF_OR_INT_SHIFT (24U) -#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK) -#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U) -#define CSI_CSISR_SF_OR_INT_SHIFT (25U) -#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK) -#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U) -#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U) -#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK) -#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U) -#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U) -#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK) -#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) -#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) -#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK) -/*! @} */ - -/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */ -/*! @{ */ -#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) -#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) -#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) -/*! @} */ - -/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */ -/*! @{ */ -#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) -#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) -#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) -/*! @} */ - -/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */ -/*! @{ */ -#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) -#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) -#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK) -/*! @} */ - -/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */ -/*! @{ */ -#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) -#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) -#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK) -/*! @} */ - -/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */ -/*! @{ */ -#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) -#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U) -#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) -#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) -#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) -#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK) -/*! @} */ - -/*! @name CSIIMAG_PARA - CSI Image Parameter Register */ -/*! @{ */ -#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) -#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) -#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK) -#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) -#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U) -#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK) -/*! @} */ - -/*! @name CSICR18 - CSI Control Register 18 */ -/*! @{ */ -#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U) -#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U) -#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK) -#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U) -#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U) -#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK) -#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U) -#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U) -#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK) -#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U) -#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U) -#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK) -#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U) -#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U) -#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK) -#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U) -#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U) -#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK) -#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U) -#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U) -#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK) -#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) -#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) -#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) -#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U) -#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U) -#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK) -#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U) -#define CSI_CSICR18_AHB_HPROT_SHIFT (12U) -#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK) -#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U) -#define CSI_CSICR18_MASK_OPTION_SHIFT (18U) -#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK) -#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U) -#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U) -#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK) -/*! @} */ - -/*! @name CSICR19 - CSI Control Register 19 */ -/*! @{ */ -#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) -#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) -#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CSI_Register_Masks */ - - -/* CSI - Peripheral instance base addresses */ -/** Peripheral CSI base address */ -#define CSI_BASE (0x402BC000u) -/** Peripheral CSI base pointer */ -#define CSI ((CSI_Type *)CSI_BASE) -/** Array initializer of CSI peripheral base addresses */ -#define CSI_BASE_ADDRS { CSI_BASE } -/** Array initializer of CSI peripheral base pointers */ -#define CSI_BASE_PTRS { CSI } -/** Interrupt vectors for the CSI peripheral type */ -#define CSI_IRQS { CSI_IRQn } - -/*! - * @} - */ /* end of group CSI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CSU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer - * @{ - */ - -/** CSU - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSL[32]; /**< Config security level register, array offset: 0x0, array step: 0x4 */ - uint8_t RESERVED_0[384]; - __IO uint32_t HP0; /**< HP0 register, offset: 0x200 */ - uint8_t RESERVED_1[20]; - __IO uint32_t SA; /**< Secure access register, offset: 0x218 */ - uint8_t RESERVED_2[316]; - __IO uint32_t HPCONTROL0; /**< HPCONTROL0 register, offset: 0x358 */ -} CSU_Type; - -/* ---------------------------------------------------------------------------- - -- CSU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CSU_Register_Masks CSU Register Masks - * @{ - */ - -/*! @name CSL - Config security level register */ -/*! @{ */ -#define CSU_CSL_SUR_S2_MASK (0x1U) -#define CSU_CSL_SUR_S2_SHIFT (0U) -#define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK) -#define CSU_CSL_SSR_S2_MASK (0x2U) -#define CSU_CSL_SSR_S2_SHIFT (1U) -#define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK) -#define CSU_CSL_NUR_S2_MASK (0x4U) -#define CSU_CSL_NUR_S2_SHIFT (2U) -#define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK) -#define CSU_CSL_NSR_S2_MASK (0x8U) -#define CSU_CSL_NSR_S2_SHIFT (3U) -#define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK) -#define CSU_CSL_SUW_S2_MASK (0x10U) -#define CSU_CSL_SUW_S2_SHIFT (4U) -#define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK) -#define CSU_CSL_SSW_S2_MASK (0x20U) -#define CSU_CSL_SSW_S2_SHIFT (5U) -#define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK) -#define CSU_CSL_NUW_S2_MASK (0x40U) -#define CSU_CSL_NUW_S2_SHIFT (6U) -#define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK) -#define CSU_CSL_NSW_S2_MASK (0x80U) -#define CSU_CSL_NSW_S2_SHIFT (7U) -#define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK) -#define CSU_CSL_LOCK_S2_MASK (0x100U) -#define CSU_CSL_LOCK_S2_SHIFT (8U) -#define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK) -#define CSU_CSL_SUR_S1_MASK (0x10000U) -#define CSU_CSL_SUR_S1_SHIFT (16U) -#define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK) -#define CSU_CSL_SSR_S1_MASK (0x20000U) -#define CSU_CSL_SSR_S1_SHIFT (17U) -#define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK) -#define CSU_CSL_NUR_S1_MASK (0x40000U) -#define CSU_CSL_NUR_S1_SHIFT (18U) -#define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK) -#define CSU_CSL_NSR_S1_MASK (0x80000U) -#define CSU_CSL_NSR_S1_SHIFT (19U) -#define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK) -#define CSU_CSL_SUW_S1_MASK (0x100000U) -#define CSU_CSL_SUW_S1_SHIFT (20U) -#define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK) -#define CSU_CSL_SSW_S1_MASK (0x200000U) -#define CSU_CSL_SSW_S1_SHIFT (21U) -#define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK) -#define CSU_CSL_NUW_S1_MASK (0x400000U) -#define CSU_CSL_NUW_S1_SHIFT (22U) -#define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK) -#define CSU_CSL_NSW_S1_MASK (0x800000U) -#define CSU_CSL_NSW_S1_SHIFT (23U) -#define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK) -#define CSU_CSL_LOCK_S1_MASK (0x1000000U) -#define CSU_CSL_LOCK_S1_SHIFT (24U) -#define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK) -/*! @} */ - -/* The count of CSU_CSL */ -#define CSU_CSL_COUNT (32U) - -/*! @name HP0 - HP0 register */ -/*! @{ */ -#define CSU_HP0_HP_DMA_MASK (0x4U) -#define CSU_HP0_HP_DMA_SHIFT (2U) -#define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK) -#define CSU_HP0_L_DMA_MASK (0x8U) -#define CSU_HP0_L_DMA_SHIFT (3U) -#define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK) -#define CSU_HP0_HP_LCDIF_MASK (0x10U) -#define CSU_HP0_HP_LCDIF_SHIFT (4U) -#define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK) -#define CSU_HP0_L_LCDIF_MASK (0x20U) -#define CSU_HP0_L_LCDIF_SHIFT (5U) -#define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK) -#define CSU_HP0_HP_CSI_MASK (0x40U) -#define CSU_HP0_HP_CSI_SHIFT (6U) -#define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK) -#define CSU_HP0_L_CSI_MASK (0x80U) -#define CSU_HP0_L_CSI_SHIFT (7U) -#define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK) -#define CSU_HP0_HP_PXP_MASK (0x100U) -#define CSU_HP0_HP_PXP_SHIFT (8U) -#define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK) -#define CSU_HP0_L_PXP_MASK (0x200U) -#define CSU_HP0_L_PXP_SHIFT (9U) -#define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK) -#define CSU_HP0_HP_DCP_MASK (0x400U) -#define CSU_HP0_HP_DCP_SHIFT (10U) -#define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK) -#define CSU_HP0_L_DCP_MASK (0x800U) -#define CSU_HP0_L_DCP_SHIFT (11U) -#define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK) -#define CSU_HP0_HP_ENET_MASK (0x4000U) -#define CSU_HP0_HP_ENET_SHIFT (14U) -#define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK) -#define CSU_HP0_L_ENET_MASK (0x8000U) -#define CSU_HP0_L_ENET_SHIFT (15U) -#define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK) -#define CSU_HP0_HP_USDHC1_MASK (0x10000U) -#define CSU_HP0_HP_USDHC1_SHIFT (16U) -#define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK) -#define CSU_HP0_L_USDHC1_MASK (0x20000U) -#define CSU_HP0_L_USDHC1_SHIFT (17U) -#define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK) -#define CSU_HP0_HP_USDHC2_MASK (0x40000U) -#define CSU_HP0_HP_USDHC2_SHIFT (18U) -#define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK) -#define CSU_HP0_L_USDHC2_MASK (0x80000U) -#define CSU_HP0_L_USDHC2_SHIFT (19U) -#define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK) -#define CSU_HP0_HP_TPSMP_MASK (0x100000U) -#define CSU_HP0_HP_TPSMP_SHIFT (20U) -#define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK) -#define CSU_HP0_L_TPSMP_MASK (0x200000U) -#define CSU_HP0_L_TPSMP_SHIFT (21U) -#define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK) -#define CSU_HP0_HP_USB_MASK (0x400000U) -#define CSU_HP0_HP_USB_SHIFT (22U) -#define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK) -#define CSU_HP0_L_USB_MASK (0x800000U) -#define CSU_HP0_L_USB_SHIFT (23U) -#define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK) -/*! @} */ - -/*! @name SA - Secure access register */ -/*! @{ */ -#define CSU_SA_NSA_DMA_MASK (0x4U) -#define CSU_SA_NSA_DMA_SHIFT (2U) -#define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK) -#define CSU_SA_L_DMA_MASK (0x8U) -#define CSU_SA_L_DMA_SHIFT (3U) -#define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK) -#define CSU_SA_NSA_LCDIF_MASK (0x10U) -#define CSU_SA_NSA_LCDIF_SHIFT (4U) -#define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK) -#define CSU_SA_L_LCDIF_MASK (0x20U) -#define CSU_SA_L_LCDIF_SHIFT (5U) -#define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK) -#define CSU_SA_NSA_CSI_MASK (0x40U) -#define CSU_SA_NSA_CSI_SHIFT (6U) -#define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK) -#define CSU_SA_L_CSI_MASK (0x80U) -#define CSU_SA_L_CSI_SHIFT (7U) -#define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK) -#define CSU_SA_NSA_PXP_MASK (0x100U) -#define CSU_SA_NSA_PXP_SHIFT (8U) -#define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK) -#define CSU_SA_L_PXP_MASK (0x200U) -#define CSU_SA_L_PXP_SHIFT (9U) -#define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK) -#define CSU_SA_NSA_DCP_MASK (0x400U) -#define CSU_SA_NSA_DCP_SHIFT (10U) -#define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK) -#define CSU_SA_L_DCP_MASK (0x800U) -#define CSU_SA_L_DCP_SHIFT (11U) -#define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK) -#define CSU_SA_NSA_ENET_MASK (0x4000U) -#define CSU_SA_NSA_ENET_SHIFT (14U) -#define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK) -#define CSU_SA_L_ENET_MASK (0x8000U) -#define CSU_SA_L_ENET_SHIFT (15U) -#define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK) -#define CSU_SA_NSA_USDHC1_MASK (0x10000U) -#define CSU_SA_NSA_USDHC1_SHIFT (16U) -#define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK) -#define CSU_SA_L_USDHC1_MASK (0x20000U) -#define CSU_SA_L_USDHC1_SHIFT (17U) -#define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK) -#define CSU_SA_NSA_USDHC2_MASK (0x40000U) -#define CSU_SA_NSA_USDHC2_SHIFT (18U) -#define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK) -#define CSU_SA_L_USDHC2_MASK (0x80000U) -#define CSU_SA_L_USDHC2_SHIFT (19U) -#define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK) -#define CSU_SA_NSA_TPSMP_MASK (0x100000U) -#define CSU_SA_NSA_TPSMP_SHIFT (20U) -#define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK) -#define CSU_SA_L_TPSMP_MASK (0x200000U) -#define CSU_SA_L_TPSMP_SHIFT (21U) -#define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK) -#define CSU_SA_NSA_USB_MASK (0x400000U) -#define CSU_SA_NSA_USB_SHIFT (22U) -#define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK) -#define CSU_SA_L_USB_MASK (0x800000U) -#define CSU_SA_L_USB_SHIFT (23U) -#define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK) -/*! @} */ - -/*! @name HPCONTROL0 - HPCONTROL0 register */ -/*! @{ */ -#define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U) -#define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U) -#define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK) -#define CSU_HPCONTROL0_L_DMA_MASK (0x8U) -#define CSU_HPCONTROL0_L_DMA_SHIFT (3U) -#define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK) -#define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U) -#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U) -#define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK) -#define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U) -#define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U) -#define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK) -#define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U) -#define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U) -#define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK) -#define CSU_HPCONTROL0_L_CSI_MASK (0x80U) -#define CSU_HPCONTROL0_L_CSI_SHIFT (7U) -#define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK) -#define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U) -#define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U) -#define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK) -#define CSU_HPCONTROL0_L_PXP_MASK (0x200U) -#define CSU_HPCONTROL0_L_PXP_SHIFT (9U) -#define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK) -#define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U) -#define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U) -#define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK) -#define CSU_HPCONTROL0_L_DCP_MASK (0x800U) -#define CSU_HPCONTROL0_L_DCP_SHIFT (11U) -#define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK) -#define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U) -#define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U) -#define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK) -#define CSU_HPCONTROL0_L_ENET_MASK (0x8000U) -#define CSU_HPCONTROL0_L_ENET_SHIFT (15U) -#define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK) -#define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U) -#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U) -#define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK) -#define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U) -#define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U) -#define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK) -#define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U) -#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U) -#define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK) -#define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U) -#define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U) -#define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK) -#define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U) -#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U) -#define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK) -#define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U) -#define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U) -#define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK) -#define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U) -#define CSU_HPCONTROL0_HPC_USB_SHIFT (22U) -#define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK) -#define CSU_HPCONTROL0_L_USB_MASK (0x800000U) -#define CSU_HPCONTROL0_L_USB_SHIFT (23U) -#define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CSU_Register_Masks */ - - -/* CSU - Peripheral instance base addresses */ -/** Peripheral CSU base address */ -#define CSU_BASE (0x400DC000u) -/** Peripheral CSU base pointer */ -#define CSU ((CSU_Type *)CSU_BASE) -/** Array initializer of CSU peripheral base addresses */ -#define CSU_BASE_ADDRS { CSU_BASE } -/** Array initializer of CSU peripheral base pointers */ -#define CSU_BASE_PTRS { CSU } - -/*! - * @} - */ /* end of group CSU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DCDC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer - * @{ - */ - -/** DCDC - Register Layout Typedef */ -typedef struct { - __IO uint32_t REG0; /**< DCDC Register 0, offset: 0x0 */ - __IO uint32_t REG1; /**< DCDC Register 1, offset: 0x4 */ - __IO uint32_t REG2; /**< DCDC Register 2, offset: 0x8 */ - __IO uint32_t REG3; /**< DCDC Register 3, offset: 0xC */ -} DCDC_Type; - -/* ---------------------------------------------------------------------------- - -- DCDC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DCDC_Register_Masks DCDC Register Masks - * @{ - */ - -/*! @name REG0 - DCDC Register 0 */ -/*! @{ */ -#define DCDC_REG0_PWD_ZCD_MASK (0x1U) -#define DCDC_REG0_PWD_ZCD_SHIFT (0U) -#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK) -#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) -#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) -#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK) -#define DCDC_REG0_SEL_CLK_MASK (0x4U) -#define DCDC_REG0_SEL_CLK_SHIFT (2U) -#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK) -#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U) -#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U) -#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK) -#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U) -#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U) -#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK) -#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U) -#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U) -#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK) -#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U) -#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U) -#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK) -#define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U) -#define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U) -#define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK) -#define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U) -#define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U) -#define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK) -#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U) -#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U) -#define DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK) -#define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U) -#define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U) -#define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK) -#define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U) -#define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U) -#define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK) -#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U) -#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U) -#define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK) -#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U) -#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U) -#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK) -#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U) -#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U) -#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK) -#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U) -#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U) -#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK) -#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U) -#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U) -#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK) -#define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U) -#define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U) -#define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK) -#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U) -#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U) -#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK) -#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U) -#define DCDC_REG0_STS_DC_OK_SHIFT (31U) -#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK) -/*! @} */ - -/*! @name REG1 - DCDC Register 1 */ -/*! @{ */ -#define DCDC_REG1_REG_FBK_SEL_MASK (0x180U) -#define DCDC_REG1_REG_FBK_SEL_SHIFT (7U) -#define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK) -#define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U) -#define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U) -#define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK) -#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U) -#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U) -#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK) -#define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U) -#define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U) -#define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK) -#define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U) -#define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U) -#define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK) -#define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) -#define DCDC_REG1_VBG_TRIM_SHIFT (24U) -#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK) -/*! @} */ - -/*! @name REG2 - DCDC Register 2 */ -/*! @{ */ -#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U) -#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U) -#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK) -#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU) -#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U) -#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK) -#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U) -#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U) -#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK) -#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U) -#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U) -#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK) -#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U) -#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U) -#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK) -#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U) -#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U) -#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK) -#define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U) -#define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U) -#define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK) -#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U) -#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U) -#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK) -/*! @} */ - -/*! @name REG3 - DCDC Register 3 */ -/*! @{ */ -#define DCDC_REG3_TRG_MASK (0x1FU) -#define DCDC_REG3_TRG_SHIFT (0U) -#define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK) -#define DCDC_REG3_TARGET_LP_MASK (0x700U) -#define DCDC_REG3_TARGET_LP_SHIFT (8U) -#define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK) -#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) -#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U) -#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK) -#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U) -#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U) -#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK) -#define DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U) -#define DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U) -#define DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK) -#define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U) -#define DCDC_REG3_DISABLE_STEP_SHIFT (30U) -#define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group DCDC_Register_Masks */ - - -/* DCDC - Peripheral instance base addresses */ -/** Peripheral DCDC base address */ -#define DCDC_BASE (0x40080000u) -/** Peripheral DCDC base pointer */ -#define DCDC ((DCDC_Type *)DCDC_BASE) -/** Array initializer of DCDC peripheral base addresses */ -#define DCDC_BASE_ADDRS { DCDC_BASE } -/** Array initializer of DCDC peripheral base pointers */ -#define DCDC_BASE_PTRS { DCDC } -/** Interrupt vectors for the DCDC peripheral type */ -#define DCDC_IRQS { DCDC_IRQn } - -/*! - * @} - */ /* end of group DCDC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DCP Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer - * @{ - */ - -/** DCP - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t STAT; /**< DCP status register, offset: 0x10 */ - uint8_t RESERVED_1[12]; - __IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */ - uint8_t RESERVED_2[12]; - __IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */ - uint8_t RESERVED_3[12]; - __I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */ - uint8_t RESERVED_4[12]; - __IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */ - uint8_t RESERVED_5[12]; - __IO uint32_t KEY; /**< DCP key index, offset: 0x60 */ - uint8_t RESERVED_6[12]; - __IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */ - uint8_t RESERVED_7[12]; - __I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */ - uint8_t RESERVED_8[12]; - __I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */ - uint8_t RESERVED_9[12]; - __I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */ - uint8_t RESERVED_10[12]; - __I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */ - uint8_t RESERVED_11[12]; - __I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */ - uint8_t RESERVED_12[12]; - __I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */ - uint8_t RESERVED_13[12]; - __I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */ - uint8_t RESERVED_14[28]; - __IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */ - uint8_t RESERVED_15[12]; - __IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */ - uint8_t RESERVED_16[12]; - __IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */ - uint8_t RESERVED_17[12]; - __IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */ - uint8_t RESERVED_18[12]; - __IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */ - uint8_t RESERVED_19[12]; - __IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */ - uint8_t RESERVED_20[12]; - __IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */ - uint8_t RESERVED_21[12]; - __IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */ - uint8_t RESERVED_22[12]; - __IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */ - uint8_t RESERVED_23[12]; - __IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */ - uint8_t RESERVED_24[12]; - __IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */ - uint8_t RESERVED_25[12]; - __IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */ - uint8_t RESERVED_26[12]; - __IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */ - uint8_t RESERVED_27[12]; - __IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */ - uint8_t RESERVED_28[12]; - __IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */ - uint8_t RESERVED_29[12]; - __IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */ - uint8_t RESERVED_30[524]; - __IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */ - uint8_t RESERVED_31[12]; - __I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */ - uint8_t RESERVED_32[12]; - __IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */ - uint8_t RESERVED_33[12]; - __I uint32_t VERSION; /**< DCP version register, offset: 0x430 */ -} DCP_Type; - -/* ---------------------------------------------------------------------------- - -- DCP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DCP_Register_Masks DCP Register Masks - * @{ - */ - -/*! @name CTRL - DCP control register 0 */ -/*! @{ */ -#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) -#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) -#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) -#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) -#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) -#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK) -#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) -#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) -#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK) -#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U) -#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U) -#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK) -#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U) -#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U) -#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK) -#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U) -#define DCP_CTRL_PRESENT_SHA_SHIFT (28U) -#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK) -#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U) -#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U) -#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK) -#define DCP_CTRL_CLKGATE_MASK (0x40000000U) -#define DCP_CTRL_CLKGATE_SHIFT (30U) -#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK) -#define DCP_CTRL_SFTRST_MASK (0x80000000U) -#define DCP_CTRL_SFTRST_SHIFT (31U) -#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) -/*! @} */ - -/*! @name STAT - DCP status register */ -/*! @{ */ -#define DCP_STAT_IRQ_MASK (0xFU) -#define DCP_STAT_IRQ_SHIFT (0U) -#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) -#define DCP_STAT_RSVD_IRQ_MASK (0x100U) -#define DCP_STAT_RSVD_IRQ_SHIFT (8U) -#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK) -#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U) -#define DCP_STAT_READY_CHANNELS_SHIFT (16U) -#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK) -#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U) -#define DCP_STAT_CUR_CHANNEL_SHIFT (24U) -#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK) -#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) -#define DCP_STAT_OTP_KEY_READY_SHIFT (28U) -#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) -/*! @} */ - -/*! @name CHANNELCTRL - DCP channel control register */ -/*! @{ */ -#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) -#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) -#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) -#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) -#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U) -#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK) -#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U) -#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U) -#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK) -#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) -#define DCP_CHANNELCTRL_RSVD_SHIFT (17U) -#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) -/*! @} */ - -/*! @name CAPABILITY0 - DCP capability 0 register */ -/*! @{ */ -#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) -#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) -#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) -#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U) -#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U) -#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK) -#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U) -#define DCP_CAPABILITY0_RSVD_SHIFT (12U) -#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK) -#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U) -#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U) -#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK) -#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) -#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) -#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) -/*! @} */ - -/*! @name CAPABILITY1 - DCP capability 1 register */ -/*! @{ */ -#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) -#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) -#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) -#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) -#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) -#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) -/*! @} */ - -/*! @name CONTEXT - DCP context buffer pointer */ -/*! @{ */ -#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) -#define DCP_CONTEXT_ADDR_SHIFT (0U) -#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) -/*! @} */ - -/*! @name KEY - DCP key index */ -/*! @{ */ -#define DCP_KEY_SUBWORD_MASK (0x3U) -#define DCP_KEY_SUBWORD_SHIFT (0U) -#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK) -#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU) -#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U) -#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK) -#define DCP_KEY_INDEX_MASK (0x30U) -#define DCP_KEY_INDEX_SHIFT (4U) -#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK) -#define DCP_KEY_RSVD_INDEX_MASK (0xC0U) -#define DCP_KEY_RSVD_INDEX_SHIFT (6U) -#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK) -#define DCP_KEY_RSVD_MASK (0xFFFFFF00U) -#define DCP_KEY_RSVD_SHIFT (8U) -#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK) -/*! @} */ - -/*! @name KEYDATA - DCP key data */ -/*! @{ */ -#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU) -#define DCP_KEYDATA_DATA_SHIFT (0U) -#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK) -/*! @} */ - -/*! @name PACKET0 - DCP work packet 0 status register */ -/*! @{ */ -#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU) -#define DCP_PACKET0_ADDR_SHIFT (0U) -#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK) -/*! @} */ - -/*! @name PACKET1 - DCP work packet 1 status register */ -/*! @{ */ -#define DCP_PACKET1_INTERRUPT_MASK (0x1U) -#define DCP_PACKET1_INTERRUPT_SHIFT (0U) -#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK) -#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U) -#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U) -#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK) -#define DCP_PACKET1_CHAIN_MASK (0x4U) -#define DCP_PACKET1_CHAIN_SHIFT (2U) -#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK) -#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U) -#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U) -#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK) -#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U) -#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U) -#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK) -#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U) -#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U) -#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK) -#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U) -#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U) -#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK) -#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U) -#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U) -#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK) -#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U) -#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U) -#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK) -#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U) -#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U) -#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK) -#define DCP_PACKET1_OTP_KEY_MASK (0x400U) -#define DCP_PACKET1_OTP_KEY_SHIFT (10U) -#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK) -#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U) -#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U) -#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK) -#define DCP_PACKET1_HASH_INIT_MASK (0x1000U) -#define DCP_PACKET1_HASH_INIT_SHIFT (12U) -#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK) -#define DCP_PACKET1_HASH_TERM_MASK (0x2000U) -#define DCP_PACKET1_HASH_TERM_SHIFT (13U) -#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK) -#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U) -#define DCP_PACKET1_CHECK_HASH_SHIFT (14U) -#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK) -#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U) -#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U) -#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK) -#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U) -#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U) -#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK) -#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U) -#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U) -#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK) -#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U) -#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U) -#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK) -#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U) -#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U) -#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK) -#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U) -#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U) -#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK) -#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U) -#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U) -#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK) -#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U) -#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U) -#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK) -#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U) -#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U) -#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK) -#define DCP_PACKET1_TAG_MASK (0xFF000000U) -#define DCP_PACKET1_TAG_SHIFT (24U) -#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK) -/*! @} */ - -/*! @name PACKET2 - DCP work packet 2 status register */ -/*! @{ */ -#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU) -#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U) -#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK) -#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U) -#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U) -#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK) -#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U) -#define DCP_PACKET2_KEY_SELECT_SHIFT (8U) -#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK) -#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U) -#define DCP_PACKET2_HASH_SELECT_SHIFT (16U) -#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK) -#define DCP_PACKET2_RSVD_MASK (0xF00000U) -#define DCP_PACKET2_RSVD_SHIFT (20U) -#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK) -#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U) -#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U) -#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK) -/*! @} */ - -/*! @name PACKET3 - DCP work packet 3 status register */ -/*! @{ */ -#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU) -#define DCP_PACKET3_ADDR_SHIFT (0U) -#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK) -/*! @} */ - -/*! @name PACKET4 - DCP work packet 4 status register */ -/*! @{ */ -#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU) -#define DCP_PACKET4_ADDR_SHIFT (0U) -#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK) -/*! @} */ - -/*! @name PACKET5 - DCP work packet 5 status register */ -/*! @{ */ -#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU) -#define DCP_PACKET5_COUNT_SHIFT (0U) -#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK) -/*! @} */ - -/*! @name PACKET6 - DCP work packet 6 status register */ -/*! @{ */ -#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU) -#define DCP_PACKET6_ADDR_SHIFT (0U) -#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK) -/*! @} */ - -/*! @name CH0CMDPTR - DCP channel 0 command pointer address register */ -/*! @{ */ -#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU) -#define DCP_CH0CMDPTR_ADDR_SHIFT (0U) -#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK) -/*! @} */ - -/*! @name CH0SEMA - DCP channel 0 semaphore register */ -/*! @{ */ -#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU) -#define DCP_CH0SEMA_INCREMENT_SHIFT (0U) -#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK) -#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U) -#define DCP_CH0SEMA_VALUE_SHIFT (16U) -#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK) -/*! @} */ - -/*! @name CH0STAT - DCP channel 0 status register */ -/*! @{ */ -#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U) -#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U) -#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK) -#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U) -#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U) -#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK) -#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U) -#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U) -#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK) -#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U) -#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U) -#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK) -#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U) -#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U) -#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK) -#define DCP_CH0STAT_ERROR_DST_MASK (0x20U) -#define DCP_CH0STAT_ERROR_DST_SHIFT (5U) -#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK) -#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U) -#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U) -#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK) -#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U) -#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U) -#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK) -#define DCP_CH0STAT_TAG_MASK (0xFF000000U) -#define DCP_CH0STAT_TAG_SHIFT (24U) -#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK) -/*! @} */ - -/*! @name CH0OPTS - DCP channel 0 options register */ -/*! @{ */ -#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU) -#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U) -#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK) -#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U) -#define DCP_CH0OPTS_RSVD_SHIFT (16U) -#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK) -/*! @} */ - -/*! @name CH1CMDPTR - DCP channel 1 command pointer address register */ -/*! @{ */ -#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU) -#define DCP_CH1CMDPTR_ADDR_SHIFT (0U) -#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK) -/*! @} */ - -/*! @name CH1SEMA - DCP channel 1 semaphore register */ -/*! @{ */ -#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU) -#define DCP_CH1SEMA_INCREMENT_SHIFT (0U) -#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK) -#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U) -#define DCP_CH1SEMA_VALUE_SHIFT (16U) -#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK) -/*! @} */ - -/*! @name CH1STAT - DCP channel 1 status register */ -/*! @{ */ -#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U) -#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U) -#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK) -#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U) -#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U) -#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK) -#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U) -#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U) -#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK) -#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U) -#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U) -#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK) -#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U) -#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U) -#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK) -#define DCP_CH1STAT_ERROR_DST_MASK (0x20U) -#define DCP_CH1STAT_ERROR_DST_SHIFT (5U) -#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK) -#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U) -#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U) -#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK) -#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U) -#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U) -#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK) -#define DCP_CH1STAT_TAG_MASK (0xFF000000U) -#define DCP_CH1STAT_TAG_SHIFT (24U) -#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK) -/*! @} */ - -/*! @name CH1OPTS - DCP channel 1 options register */ -/*! @{ */ -#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU) -#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U) -#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK) -#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U) -#define DCP_CH1OPTS_RSVD_SHIFT (16U) -#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK) -/*! @} */ - -/*! @name CH2CMDPTR - DCP channel 2 command pointer address register */ -/*! @{ */ -#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU) -#define DCP_CH2CMDPTR_ADDR_SHIFT (0U) -#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK) -/*! @} */ - -/*! @name CH2SEMA - DCP channel 2 semaphore register */ -/*! @{ */ -#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU) -#define DCP_CH2SEMA_INCREMENT_SHIFT (0U) -#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK) -#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U) -#define DCP_CH2SEMA_VALUE_SHIFT (16U) -#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK) -/*! @} */ - -/*! @name CH2STAT - DCP channel 2 status register */ -/*! @{ */ -#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U) -#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U) -#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK) -#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U) -#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U) -#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK) -#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U) -#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U) -#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK) -#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U) -#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U) -#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK) -#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U) -#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U) -#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK) -#define DCP_CH2STAT_ERROR_DST_MASK (0x20U) -#define DCP_CH2STAT_ERROR_DST_SHIFT (5U) -#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK) -#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U) -#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U) -#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK) -#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U) -#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U) -#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK) -#define DCP_CH2STAT_TAG_MASK (0xFF000000U) -#define DCP_CH2STAT_TAG_SHIFT (24U) -#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK) -/*! @} */ - -/*! @name CH2OPTS - DCP channel 2 options register */ -/*! @{ */ -#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU) -#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U) -#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK) -#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U) -#define DCP_CH2OPTS_RSVD_SHIFT (16U) -#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK) -/*! @} */ - -/*! @name CH3CMDPTR - DCP channel 3 command pointer address register */ -/*! @{ */ -#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU) -#define DCP_CH3CMDPTR_ADDR_SHIFT (0U) -#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK) -/*! @} */ - -/*! @name CH3SEMA - DCP channel 3 semaphore register */ -/*! @{ */ -#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU) -#define DCP_CH3SEMA_INCREMENT_SHIFT (0U) -#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK) -#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U) -#define DCP_CH3SEMA_VALUE_SHIFT (16U) -#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK) -/*! @} */ - -/*! @name CH3STAT - DCP channel 3 status register */ -/*! @{ */ -#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U) -#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U) -#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK) -#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U) -#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U) -#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK) -#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U) -#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U) -#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK) -#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U) -#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U) -#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK) -#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U) -#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U) -#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK) -#define DCP_CH3STAT_ERROR_DST_MASK (0x20U) -#define DCP_CH3STAT_ERROR_DST_SHIFT (5U) -#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK) -#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U) -#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U) -#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK) -#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U) -#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U) -#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK) -#define DCP_CH3STAT_TAG_MASK (0xFF000000U) -#define DCP_CH3STAT_TAG_SHIFT (24U) -#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK) -/*! @} */ - -/*! @name CH3OPTS - DCP channel 3 options register */ -/*! @{ */ -#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU) -#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U) -#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK) -#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U) -#define DCP_CH3OPTS_RSVD_SHIFT (16U) -#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK) -/*! @} */ - -/*! @name DBGSELECT - DCP debug select register */ -/*! @{ */ -#define DCP_DBGSELECT_INDEX_MASK (0xFFU) -#define DCP_DBGSELECT_INDEX_SHIFT (0U) -#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK) -#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U) -#define DCP_DBGSELECT_RSVD_SHIFT (8U) -#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK) -/*! @} */ - -/*! @name DBGDATA - DCP debug data register */ -/*! @{ */ -#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU) -#define DCP_DBGDATA_DATA_SHIFT (0U) -#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK) -/*! @} */ - -/*! @name PAGETABLE - DCP page table register */ -/*! @{ */ -#define DCP_PAGETABLE_ENABLE_MASK (0x1U) -#define DCP_PAGETABLE_ENABLE_SHIFT (0U) -#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK) -#define DCP_PAGETABLE_FLUSH_MASK (0x2U) -#define DCP_PAGETABLE_FLUSH_SHIFT (1U) -#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK) -#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU) -#define DCP_PAGETABLE_BASE_SHIFT (2U) -#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK) -/*! @} */ - -/*! @name VERSION - DCP version register */ -/*! @{ */ -#define DCP_VERSION_STEP_MASK (0xFFFFU) -#define DCP_VERSION_STEP_SHIFT (0U) -#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK) -#define DCP_VERSION_MINOR_MASK (0xFF0000U) -#define DCP_VERSION_MINOR_SHIFT (16U) -#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK) -#define DCP_VERSION_MAJOR_MASK (0xFF000000U) -#define DCP_VERSION_MAJOR_SHIFT (24U) -#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group DCP_Register_Masks */ - - -/* DCP - Peripheral instance base addresses */ -/** Peripheral DCP base address */ -#define DCP_BASE (0x402FC000u) -/** Peripheral DCP base pointer */ -#define DCP ((DCP_Type *)DCP_BASE) -/** Array initializer of DCP peripheral base addresses */ -#define DCP_BASE_ADDRS { DCP_BASE } -/** Array initializer of DCP peripheral base pointers */ -#define DCP_BASE_PTRS { DCP } -/** Interrupt vectors for the DCP peripheral type */ -#define DCP_IRQS { DCP_IRQn } -#define DCP_VMI_IRQS { DCP_VMI_IRQn } - -/*! - * @} - */ /* end of group DCP_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CR; /**< Control Register, offset: 0x0 */ - __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ - uint8_t RESERVED_1[4]; - __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ - __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ - __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ - __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ - __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ - __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ - __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ - __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ - __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ - uint8_t RESERVED_2[4]; - __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ - uint8_t RESERVED_4[4]; - __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ - uint8_t RESERVED_5[12]; - __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ - uint8_t RESERVED_6[184]; - __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ - __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ - __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ - __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ - __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ - __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ - __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ - __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ - __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ - __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ - __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ - __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ - __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ - __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ - __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ - __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ - __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */ - __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */ - __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */ - __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */ - __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */ - __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */ - __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */ - __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */ - __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */ - __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */ - __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */ - __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */ - __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */ - __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */ - __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */ - __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */ - uint8_t RESERVED_7[3808]; - struct { /* offset: 0x1000, array step: 0x20 */ - __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ - __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ - __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ - union { /* offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ - }; - __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ - __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ - __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ - union { /* offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ - }; - __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ - __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ - union { /* offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ - }; - } TCD[32]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CR - Control Register */ -/*! @{ */ -#define DMA_CR_EDBG_MASK (0x2U) -#define DMA_CR_EDBG_SHIFT (1U) -#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) -#define DMA_CR_ERCA_MASK (0x4U) -#define DMA_CR_ERCA_SHIFT (2U) -#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) -#define DMA_CR_ERGA_MASK (0x8U) -#define DMA_CR_ERGA_SHIFT (3U) -#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) -#define DMA_CR_HOE_MASK (0x10U) -#define DMA_CR_HOE_SHIFT (4U) -#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) -#define DMA_CR_HALT_MASK (0x20U) -#define DMA_CR_HALT_SHIFT (5U) -#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) -#define DMA_CR_CLM_MASK (0x40U) -#define DMA_CR_CLM_SHIFT (6U) -#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) -#define DMA_CR_EMLM_MASK (0x80U) -#define DMA_CR_EMLM_SHIFT (7U) -#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) -#define DMA_CR_GRP0PRI_MASK (0x100U) -#define DMA_CR_GRP0PRI_SHIFT (8U) -#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK) -#define DMA_CR_GRP1PRI_MASK (0x400U) -#define DMA_CR_GRP1PRI_SHIFT (10U) -#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) -#define DMA_CR_ECX_MASK (0x10000U) -#define DMA_CR_ECX_SHIFT (16U) -#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) -#define DMA_CR_CX_MASK (0x20000U) -#define DMA_CR_CX_SHIFT (17U) -#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) -#define DMA_CR_ACTIVE_MASK (0x80000000U) -#define DMA_CR_ACTIVE_SHIFT (31U) -#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) -/*! @} */ - -/*! @name ES - Error Status Register */ -/*! @{ */ -#define DMA_ES_DBE_MASK (0x1U) -#define DMA_ES_DBE_SHIFT (0U) -#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) -#define DMA_ES_SBE_MASK (0x2U) -#define DMA_ES_SBE_SHIFT (1U) -#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) -#define DMA_ES_SGE_MASK (0x4U) -#define DMA_ES_SGE_SHIFT (2U) -#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) -#define DMA_ES_NCE_MASK (0x8U) -#define DMA_ES_NCE_SHIFT (3U) -#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) -#define DMA_ES_DOE_MASK (0x10U) -#define DMA_ES_DOE_SHIFT (4U) -#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) -#define DMA_ES_DAE_MASK (0x20U) -#define DMA_ES_DAE_SHIFT (5U) -#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) -#define DMA_ES_SOE_MASK (0x40U) -#define DMA_ES_SOE_SHIFT (6U) -#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) -#define DMA_ES_SAE_MASK (0x80U) -#define DMA_ES_SAE_SHIFT (7U) -#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) -#define DMA_ES_ERRCHN_MASK (0x1F00U) -#define DMA_ES_ERRCHN_SHIFT (8U) -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) -#define DMA_ES_CPE_MASK (0x4000U) -#define DMA_ES_CPE_SHIFT (14U) -#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) -#define DMA_ES_GPE_MASK (0x8000U) -#define DMA_ES_GPE_SHIFT (15U) -#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) -#define DMA_ES_ECX_MASK (0x10000U) -#define DMA_ES_ECX_SHIFT (16U) -#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) -#define DMA_ES_VLD_MASK (0x80000000U) -#define DMA_ES_VLD_SHIFT (31U) -#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) -/*! @} */ - -/*! @name ERQ - Enable Request Register */ -/*! @{ */ -#define DMA_ERQ_ERQ0_MASK (0x1U) -#define DMA_ERQ_ERQ0_SHIFT (0U) -#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) -#define DMA_ERQ_ERQ1_MASK (0x2U) -#define DMA_ERQ_ERQ1_SHIFT (1U) -#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) -#define DMA_ERQ_ERQ2_MASK (0x4U) -#define DMA_ERQ_ERQ2_SHIFT (2U) -#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) -#define DMA_ERQ_ERQ3_MASK (0x8U) -#define DMA_ERQ_ERQ3_SHIFT (3U) -#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) -#define DMA_ERQ_ERQ4_MASK (0x10U) -#define DMA_ERQ_ERQ4_SHIFT (4U) -#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) -#define DMA_ERQ_ERQ5_MASK (0x20U) -#define DMA_ERQ_ERQ5_SHIFT (5U) -#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) -#define DMA_ERQ_ERQ6_MASK (0x40U) -#define DMA_ERQ_ERQ6_SHIFT (6U) -#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) -#define DMA_ERQ_ERQ7_MASK (0x80U) -#define DMA_ERQ_ERQ7_SHIFT (7U) -#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) -#define DMA_ERQ_ERQ8_MASK (0x100U) -#define DMA_ERQ_ERQ8_SHIFT (8U) -#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) -#define DMA_ERQ_ERQ9_MASK (0x200U) -#define DMA_ERQ_ERQ9_SHIFT (9U) -#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) -#define DMA_ERQ_ERQ10_MASK (0x400U) -#define DMA_ERQ_ERQ10_SHIFT (10U) -#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) -#define DMA_ERQ_ERQ11_MASK (0x800U) -#define DMA_ERQ_ERQ11_SHIFT (11U) -#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) -#define DMA_ERQ_ERQ12_MASK (0x1000U) -#define DMA_ERQ_ERQ12_SHIFT (12U) -#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) -#define DMA_ERQ_ERQ13_MASK (0x2000U) -#define DMA_ERQ_ERQ13_SHIFT (13U) -#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) -#define DMA_ERQ_ERQ14_MASK (0x4000U) -#define DMA_ERQ_ERQ14_SHIFT (14U) -#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) -#define DMA_ERQ_ERQ15_MASK (0x8000U) -#define DMA_ERQ_ERQ15_SHIFT (15U) -#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) -#define DMA_ERQ_ERQ16_MASK (0x10000U) -#define DMA_ERQ_ERQ16_SHIFT (16U) -#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) -#define DMA_ERQ_ERQ17_MASK (0x20000U) -#define DMA_ERQ_ERQ17_SHIFT (17U) -#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) -#define DMA_ERQ_ERQ18_MASK (0x40000U) -#define DMA_ERQ_ERQ18_SHIFT (18U) -#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) -#define DMA_ERQ_ERQ19_MASK (0x80000U) -#define DMA_ERQ_ERQ19_SHIFT (19U) -#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) -#define DMA_ERQ_ERQ20_MASK (0x100000U) -#define DMA_ERQ_ERQ20_SHIFT (20U) -#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) -#define DMA_ERQ_ERQ21_MASK (0x200000U) -#define DMA_ERQ_ERQ21_SHIFT (21U) -#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) -#define DMA_ERQ_ERQ22_MASK (0x400000U) -#define DMA_ERQ_ERQ22_SHIFT (22U) -#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) -#define DMA_ERQ_ERQ23_MASK (0x800000U) -#define DMA_ERQ_ERQ23_SHIFT (23U) -#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) -#define DMA_ERQ_ERQ24_MASK (0x1000000U) -#define DMA_ERQ_ERQ24_SHIFT (24U) -#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) -#define DMA_ERQ_ERQ25_MASK (0x2000000U) -#define DMA_ERQ_ERQ25_SHIFT (25U) -#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) -#define DMA_ERQ_ERQ26_MASK (0x4000000U) -#define DMA_ERQ_ERQ26_SHIFT (26U) -#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) -#define DMA_ERQ_ERQ27_MASK (0x8000000U) -#define DMA_ERQ_ERQ27_SHIFT (27U) -#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) -#define DMA_ERQ_ERQ28_MASK (0x10000000U) -#define DMA_ERQ_ERQ28_SHIFT (28U) -#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) -#define DMA_ERQ_ERQ29_MASK (0x20000000U) -#define DMA_ERQ_ERQ29_SHIFT (29U) -#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) -#define DMA_ERQ_ERQ30_MASK (0x40000000U) -#define DMA_ERQ_ERQ30_SHIFT (30U) -#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) -#define DMA_ERQ_ERQ31_MASK (0x80000000U) -#define DMA_ERQ_ERQ31_SHIFT (31U) -#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) -/*! @} */ - -/*! @name EEI - Enable Error Interrupt Register */ -/*! @{ */ -#define DMA_EEI_EEI0_MASK (0x1U) -#define DMA_EEI_EEI0_SHIFT (0U) -#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) -#define DMA_EEI_EEI1_MASK (0x2U) -#define DMA_EEI_EEI1_SHIFT (1U) -#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) -#define DMA_EEI_EEI2_MASK (0x4U) -#define DMA_EEI_EEI2_SHIFT (2U) -#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) -#define DMA_EEI_EEI3_MASK (0x8U) -#define DMA_EEI_EEI3_SHIFT (3U) -#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) -#define DMA_EEI_EEI4_MASK (0x10U) -#define DMA_EEI_EEI4_SHIFT (4U) -#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) -#define DMA_EEI_EEI5_MASK (0x20U) -#define DMA_EEI_EEI5_SHIFT (5U) -#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) -#define DMA_EEI_EEI6_MASK (0x40U) -#define DMA_EEI_EEI6_SHIFT (6U) -#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) -#define DMA_EEI_EEI7_MASK (0x80U) -#define DMA_EEI_EEI7_SHIFT (7U) -#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) -#define DMA_EEI_EEI8_MASK (0x100U) -#define DMA_EEI_EEI8_SHIFT (8U) -#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) -#define DMA_EEI_EEI9_MASK (0x200U) -#define DMA_EEI_EEI9_SHIFT (9U) -#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) -#define DMA_EEI_EEI10_MASK (0x400U) -#define DMA_EEI_EEI10_SHIFT (10U) -#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) -#define DMA_EEI_EEI11_MASK (0x800U) -#define DMA_EEI_EEI11_SHIFT (11U) -#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) -#define DMA_EEI_EEI12_MASK (0x1000U) -#define DMA_EEI_EEI12_SHIFT (12U) -#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) -#define DMA_EEI_EEI13_MASK (0x2000U) -#define DMA_EEI_EEI13_SHIFT (13U) -#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) -#define DMA_EEI_EEI14_MASK (0x4000U) -#define DMA_EEI_EEI14_SHIFT (14U) -#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) -#define DMA_EEI_EEI15_MASK (0x8000U) -#define DMA_EEI_EEI15_SHIFT (15U) -#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) -#define DMA_EEI_EEI16_MASK (0x10000U) -#define DMA_EEI_EEI16_SHIFT (16U) -#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) -#define DMA_EEI_EEI17_MASK (0x20000U) -#define DMA_EEI_EEI17_SHIFT (17U) -#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) -#define DMA_EEI_EEI18_MASK (0x40000U) -#define DMA_EEI_EEI18_SHIFT (18U) -#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) -#define DMA_EEI_EEI19_MASK (0x80000U) -#define DMA_EEI_EEI19_SHIFT (19U) -#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) -#define DMA_EEI_EEI20_MASK (0x100000U) -#define DMA_EEI_EEI20_SHIFT (20U) -#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) -#define DMA_EEI_EEI21_MASK (0x200000U) -#define DMA_EEI_EEI21_SHIFT (21U) -#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) -#define DMA_EEI_EEI22_MASK (0x400000U) -#define DMA_EEI_EEI22_SHIFT (22U) -#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) -#define DMA_EEI_EEI23_MASK (0x800000U) -#define DMA_EEI_EEI23_SHIFT (23U) -#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) -#define DMA_EEI_EEI24_MASK (0x1000000U) -#define DMA_EEI_EEI24_SHIFT (24U) -#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) -#define DMA_EEI_EEI25_MASK (0x2000000U) -#define DMA_EEI_EEI25_SHIFT (25U) -#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) -#define DMA_EEI_EEI26_MASK (0x4000000U) -#define DMA_EEI_EEI26_SHIFT (26U) -#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) -#define DMA_EEI_EEI27_MASK (0x8000000U) -#define DMA_EEI_EEI27_SHIFT (27U) -#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) -#define DMA_EEI_EEI28_MASK (0x10000000U) -#define DMA_EEI_EEI28_SHIFT (28U) -#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) -#define DMA_EEI_EEI29_MASK (0x20000000U) -#define DMA_EEI_EEI29_SHIFT (29U) -#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) -#define DMA_EEI_EEI30_MASK (0x40000000U) -#define DMA_EEI_EEI30_SHIFT (30U) -#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) -#define DMA_EEI_EEI31_MASK (0x80000000U) -#define DMA_EEI_EEI31_SHIFT (31U) -#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) -/*! @} */ - -/*! @name CEEI - Clear Enable Error Interrupt Register */ -/*! @{ */ -#define DMA_CEEI_CEEI_MASK (0x1FU) -#define DMA_CEEI_CEEI_SHIFT (0U) -#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) -#define DMA_CEEI_CAEE_MASK (0x40U) -#define DMA_CEEI_CAEE_SHIFT (6U) -#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) -#define DMA_CEEI_NOP_MASK (0x80U) -#define DMA_CEEI_NOP_SHIFT (7U) -#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) -/*! @} */ - -/*! @name SEEI - Set Enable Error Interrupt Register */ -/*! @{ */ -#define DMA_SEEI_SEEI_MASK (0x1FU) -#define DMA_SEEI_SEEI_SHIFT (0U) -#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) -#define DMA_SEEI_SAEE_MASK (0x40U) -#define DMA_SEEI_SAEE_SHIFT (6U) -#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) -#define DMA_SEEI_NOP_MASK (0x80U) -#define DMA_SEEI_NOP_SHIFT (7U) -#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) -/*! @} */ - -/*! @name CERQ - Clear Enable Request Register */ -/*! @{ */ -#define DMA_CERQ_CERQ_MASK (0x1FU) -#define DMA_CERQ_CERQ_SHIFT (0U) -#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) -#define DMA_CERQ_CAER_MASK (0x40U) -#define DMA_CERQ_CAER_SHIFT (6U) -#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) -#define DMA_CERQ_NOP_MASK (0x80U) -#define DMA_CERQ_NOP_SHIFT (7U) -#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) -/*! @} */ - -/*! @name SERQ - Set Enable Request Register */ -/*! @{ */ -#define DMA_SERQ_SERQ_MASK (0x1FU) -#define DMA_SERQ_SERQ_SHIFT (0U) -#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) -#define DMA_SERQ_SAER_MASK (0x40U) -#define DMA_SERQ_SAER_SHIFT (6U) -#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) -#define DMA_SERQ_NOP_MASK (0x80U) -#define DMA_SERQ_NOP_SHIFT (7U) -#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) -/*! @} */ - -/*! @name CDNE - Clear DONE Status Bit Register */ -/*! @{ */ -#define DMA_CDNE_CDNE_MASK (0x1FU) -#define DMA_CDNE_CDNE_SHIFT (0U) -#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) -#define DMA_CDNE_CADN_MASK (0x40U) -#define DMA_CDNE_CADN_SHIFT (6U) -#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) -#define DMA_CDNE_NOP_MASK (0x80U) -#define DMA_CDNE_NOP_SHIFT (7U) -#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) -/*! @} */ - -/*! @name SSRT - Set START Bit Register */ -/*! @{ */ -#define DMA_SSRT_SSRT_MASK (0x1FU) -#define DMA_SSRT_SSRT_SHIFT (0U) -#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) -#define DMA_SSRT_SAST_MASK (0x40U) -#define DMA_SSRT_SAST_SHIFT (6U) -#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) -#define DMA_SSRT_NOP_MASK (0x80U) -#define DMA_SSRT_NOP_SHIFT (7U) -#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) -/*! @} */ - -/*! @name CERR - Clear Error Register */ -/*! @{ */ -#define DMA_CERR_CERR_MASK (0x1FU) -#define DMA_CERR_CERR_SHIFT (0U) -#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) -#define DMA_CERR_CAEI_MASK (0x40U) -#define DMA_CERR_CAEI_SHIFT (6U) -#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) -#define DMA_CERR_NOP_MASK (0x80U) -#define DMA_CERR_NOP_SHIFT (7U) -#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) -/*! @} */ - -/*! @name CINT - Clear Interrupt Request Register */ -/*! @{ */ -#define DMA_CINT_CINT_MASK (0x1FU) -#define DMA_CINT_CINT_SHIFT (0U) -#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) -#define DMA_CINT_CAIR_MASK (0x40U) -#define DMA_CINT_CAIR_SHIFT (6U) -#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) -#define DMA_CINT_NOP_MASK (0x80U) -#define DMA_CINT_NOP_SHIFT (7U) -#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) -/*! @} */ - -/*! @name INT - Interrupt Request Register */ -/*! @{ */ -#define DMA_INT_INT0_MASK (0x1U) -#define DMA_INT_INT0_SHIFT (0U) -#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) -#define DMA_INT_INT1_MASK (0x2U) -#define DMA_INT_INT1_SHIFT (1U) -#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) -#define DMA_INT_INT2_MASK (0x4U) -#define DMA_INT_INT2_SHIFT (2U) -#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) -#define DMA_INT_INT3_MASK (0x8U) -#define DMA_INT_INT3_SHIFT (3U) -#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) -#define DMA_INT_INT4_MASK (0x10U) -#define DMA_INT_INT4_SHIFT (4U) -#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) -#define DMA_INT_INT5_MASK (0x20U) -#define DMA_INT_INT5_SHIFT (5U) -#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) -#define DMA_INT_INT6_MASK (0x40U) -#define DMA_INT_INT6_SHIFT (6U) -#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) -#define DMA_INT_INT7_MASK (0x80U) -#define DMA_INT_INT7_SHIFT (7U) -#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) -#define DMA_INT_INT8_MASK (0x100U) -#define DMA_INT_INT8_SHIFT (8U) -#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) -#define DMA_INT_INT9_MASK (0x200U) -#define DMA_INT_INT9_SHIFT (9U) -#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) -#define DMA_INT_INT10_MASK (0x400U) -#define DMA_INT_INT10_SHIFT (10U) -#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) -#define DMA_INT_INT11_MASK (0x800U) -#define DMA_INT_INT11_SHIFT (11U) -#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) -#define DMA_INT_INT12_MASK (0x1000U) -#define DMA_INT_INT12_SHIFT (12U) -#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) -#define DMA_INT_INT13_MASK (0x2000U) -#define DMA_INT_INT13_SHIFT (13U) -#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) -#define DMA_INT_INT14_MASK (0x4000U) -#define DMA_INT_INT14_SHIFT (14U) -#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) -#define DMA_INT_INT15_MASK (0x8000U) -#define DMA_INT_INT15_SHIFT (15U) -#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) -#define DMA_INT_INT16_MASK (0x10000U) -#define DMA_INT_INT16_SHIFT (16U) -#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) -#define DMA_INT_INT17_MASK (0x20000U) -#define DMA_INT_INT17_SHIFT (17U) -#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) -#define DMA_INT_INT18_MASK (0x40000U) -#define DMA_INT_INT18_SHIFT (18U) -#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) -#define DMA_INT_INT19_MASK (0x80000U) -#define DMA_INT_INT19_SHIFT (19U) -#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) -#define DMA_INT_INT20_MASK (0x100000U) -#define DMA_INT_INT20_SHIFT (20U) -#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) -#define DMA_INT_INT21_MASK (0x200000U) -#define DMA_INT_INT21_SHIFT (21U) -#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) -#define DMA_INT_INT22_MASK (0x400000U) -#define DMA_INT_INT22_SHIFT (22U) -#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) -#define DMA_INT_INT23_MASK (0x800000U) -#define DMA_INT_INT23_SHIFT (23U) -#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) -#define DMA_INT_INT24_MASK (0x1000000U) -#define DMA_INT_INT24_SHIFT (24U) -#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) -#define DMA_INT_INT25_MASK (0x2000000U) -#define DMA_INT_INT25_SHIFT (25U) -#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) -#define DMA_INT_INT26_MASK (0x4000000U) -#define DMA_INT_INT26_SHIFT (26U) -#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) -#define DMA_INT_INT27_MASK (0x8000000U) -#define DMA_INT_INT27_SHIFT (27U) -#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) -#define DMA_INT_INT28_MASK (0x10000000U) -#define DMA_INT_INT28_SHIFT (28U) -#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) -#define DMA_INT_INT29_MASK (0x20000000U) -#define DMA_INT_INT29_SHIFT (29U) -#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) -#define DMA_INT_INT30_MASK (0x40000000U) -#define DMA_INT_INT30_SHIFT (30U) -#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) -#define DMA_INT_INT31_MASK (0x80000000U) -#define DMA_INT_INT31_SHIFT (31U) -#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) -/*! @} */ - -/*! @name ERR - Error Register */ -/*! @{ */ -#define DMA_ERR_ERR0_MASK (0x1U) -#define DMA_ERR_ERR0_SHIFT (0U) -#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) -#define DMA_ERR_ERR1_MASK (0x2U) -#define DMA_ERR_ERR1_SHIFT (1U) -#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) -#define DMA_ERR_ERR2_MASK (0x4U) -#define DMA_ERR_ERR2_SHIFT (2U) -#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) -#define DMA_ERR_ERR3_MASK (0x8U) -#define DMA_ERR_ERR3_SHIFT (3U) -#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) -#define DMA_ERR_ERR4_MASK (0x10U) -#define DMA_ERR_ERR4_SHIFT (4U) -#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) -#define DMA_ERR_ERR5_MASK (0x20U) -#define DMA_ERR_ERR5_SHIFT (5U) -#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) -#define DMA_ERR_ERR6_MASK (0x40U) -#define DMA_ERR_ERR6_SHIFT (6U) -#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) -#define DMA_ERR_ERR7_MASK (0x80U) -#define DMA_ERR_ERR7_SHIFT (7U) -#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) -#define DMA_ERR_ERR8_MASK (0x100U) -#define DMA_ERR_ERR8_SHIFT (8U) -#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) -#define DMA_ERR_ERR9_MASK (0x200U) -#define DMA_ERR_ERR9_SHIFT (9U) -#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) -#define DMA_ERR_ERR10_MASK (0x400U) -#define DMA_ERR_ERR10_SHIFT (10U) -#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) -#define DMA_ERR_ERR11_MASK (0x800U) -#define DMA_ERR_ERR11_SHIFT (11U) -#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) -#define DMA_ERR_ERR12_MASK (0x1000U) -#define DMA_ERR_ERR12_SHIFT (12U) -#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) -#define DMA_ERR_ERR13_MASK (0x2000U) -#define DMA_ERR_ERR13_SHIFT (13U) -#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) -#define DMA_ERR_ERR14_MASK (0x4000U) -#define DMA_ERR_ERR14_SHIFT (14U) -#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) -#define DMA_ERR_ERR15_MASK (0x8000U) -#define DMA_ERR_ERR15_SHIFT (15U) -#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) -#define DMA_ERR_ERR16_MASK (0x10000U) -#define DMA_ERR_ERR16_SHIFT (16U) -#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) -#define DMA_ERR_ERR17_MASK (0x20000U) -#define DMA_ERR_ERR17_SHIFT (17U) -#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) -#define DMA_ERR_ERR18_MASK (0x40000U) -#define DMA_ERR_ERR18_SHIFT (18U) -#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) -#define DMA_ERR_ERR19_MASK (0x80000U) -#define DMA_ERR_ERR19_SHIFT (19U) -#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) -#define DMA_ERR_ERR20_MASK (0x100000U) -#define DMA_ERR_ERR20_SHIFT (20U) -#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) -#define DMA_ERR_ERR21_MASK (0x200000U) -#define DMA_ERR_ERR21_SHIFT (21U) -#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) -#define DMA_ERR_ERR22_MASK (0x400000U) -#define DMA_ERR_ERR22_SHIFT (22U) -#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) -#define DMA_ERR_ERR23_MASK (0x800000U) -#define DMA_ERR_ERR23_SHIFT (23U) -#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) -#define DMA_ERR_ERR24_MASK (0x1000000U) -#define DMA_ERR_ERR24_SHIFT (24U) -#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) -#define DMA_ERR_ERR25_MASK (0x2000000U) -#define DMA_ERR_ERR25_SHIFT (25U) -#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) -#define DMA_ERR_ERR26_MASK (0x4000000U) -#define DMA_ERR_ERR26_SHIFT (26U) -#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) -#define DMA_ERR_ERR27_MASK (0x8000000U) -#define DMA_ERR_ERR27_SHIFT (27U) -#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) -#define DMA_ERR_ERR28_MASK (0x10000000U) -#define DMA_ERR_ERR28_SHIFT (28U) -#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) -#define DMA_ERR_ERR29_MASK (0x20000000U) -#define DMA_ERR_ERR29_SHIFT (29U) -#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) -#define DMA_ERR_ERR30_MASK (0x40000000U) -#define DMA_ERR_ERR30_SHIFT (30U) -#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) -#define DMA_ERR_ERR31_MASK (0x80000000U) -#define DMA_ERR_ERR31_SHIFT (31U) -#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) -/*! @} */ - -/*! @name HRS - Hardware Request Status Register */ -/*! @{ */ -#define DMA_HRS_HRS0_MASK (0x1U) -#define DMA_HRS_HRS0_SHIFT (0U) -#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) -#define DMA_HRS_HRS1_MASK (0x2U) -#define DMA_HRS_HRS1_SHIFT (1U) -#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) -#define DMA_HRS_HRS2_MASK (0x4U) -#define DMA_HRS_HRS2_SHIFT (2U) -#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) -#define DMA_HRS_HRS3_MASK (0x8U) -#define DMA_HRS_HRS3_SHIFT (3U) -#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) -#define DMA_HRS_HRS4_MASK (0x10U) -#define DMA_HRS_HRS4_SHIFT (4U) -#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) -#define DMA_HRS_HRS5_MASK (0x20U) -#define DMA_HRS_HRS5_SHIFT (5U) -#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) -#define DMA_HRS_HRS6_MASK (0x40U) -#define DMA_HRS_HRS6_SHIFT (6U) -#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) -#define DMA_HRS_HRS7_MASK (0x80U) -#define DMA_HRS_HRS7_SHIFT (7U) -#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) -#define DMA_HRS_HRS8_MASK (0x100U) -#define DMA_HRS_HRS8_SHIFT (8U) -#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) -#define DMA_HRS_HRS9_MASK (0x200U) -#define DMA_HRS_HRS9_SHIFT (9U) -#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) -#define DMA_HRS_HRS10_MASK (0x400U) -#define DMA_HRS_HRS10_SHIFT (10U) -#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) -#define DMA_HRS_HRS11_MASK (0x800U) -#define DMA_HRS_HRS11_SHIFT (11U) -#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) -#define DMA_HRS_HRS12_MASK (0x1000U) -#define DMA_HRS_HRS12_SHIFT (12U) -#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) -#define DMA_HRS_HRS13_MASK (0x2000U) -#define DMA_HRS_HRS13_SHIFT (13U) -#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) -#define DMA_HRS_HRS14_MASK (0x4000U) -#define DMA_HRS_HRS14_SHIFT (14U) -#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) -#define DMA_HRS_HRS15_MASK (0x8000U) -#define DMA_HRS_HRS15_SHIFT (15U) -#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) -#define DMA_HRS_HRS16_MASK (0x10000U) -#define DMA_HRS_HRS16_SHIFT (16U) -#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) -#define DMA_HRS_HRS17_MASK (0x20000U) -#define DMA_HRS_HRS17_SHIFT (17U) -#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) -#define DMA_HRS_HRS18_MASK (0x40000U) -#define DMA_HRS_HRS18_SHIFT (18U) -#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) -#define DMA_HRS_HRS19_MASK (0x80000U) -#define DMA_HRS_HRS19_SHIFT (19U) -#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) -#define DMA_HRS_HRS20_MASK (0x100000U) -#define DMA_HRS_HRS20_SHIFT (20U) -#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) -#define DMA_HRS_HRS21_MASK (0x200000U) -#define DMA_HRS_HRS21_SHIFT (21U) -#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) -#define DMA_HRS_HRS22_MASK (0x400000U) -#define DMA_HRS_HRS22_SHIFT (22U) -#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) -#define DMA_HRS_HRS23_MASK (0x800000U) -#define DMA_HRS_HRS23_SHIFT (23U) -#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) -#define DMA_HRS_HRS24_MASK (0x1000000U) -#define DMA_HRS_HRS24_SHIFT (24U) -#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) -#define DMA_HRS_HRS25_MASK (0x2000000U) -#define DMA_HRS_HRS25_SHIFT (25U) -#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) -#define DMA_HRS_HRS26_MASK (0x4000000U) -#define DMA_HRS_HRS26_SHIFT (26U) -#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) -#define DMA_HRS_HRS27_MASK (0x8000000U) -#define DMA_HRS_HRS27_SHIFT (27U) -#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) -#define DMA_HRS_HRS28_MASK (0x10000000U) -#define DMA_HRS_HRS28_SHIFT (28U) -#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) -#define DMA_HRS_HRS29_MASK (0x20000000U) -#define DMA_HRS_HRS29_SHIFT (29U) -#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) -#define DMA_HRS_HRS30_MASK (0x40000000U) -#define DMA_HRS_HRS30_SHIFT (30U) -#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) -#define DMA_HRS_HRS31_MASK (0x80000000U) -#define DMA_HRS_HRS31_SHIFT (31U) -#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) -/*! @} */ - -/*! @name EARS - Enable Asynchronous Request in Stop Register */ -/*! @{ */ -#define DMA_EARS_EDREQ_0_MASK (0x1U) -#define DMA_EARS_EDREQ_0_SHIFT (0U) -#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) -#define DMA_EARS_EDREQ_1_MASK (0x2U) -#define DMA_EARS_EDREQ_1_SHIFT (1U) -#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) -#define DMA_EARS_EDREQ_2_MASK (0x4U) -#define DMA_EARS_EDREQ_2_SHIFT (2U) -#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) -#define DMA_EARS_EDREQ_3_MASK (0x8U) -#define DMA_EARS_EDREQ_3_SHIFT (3U) -#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) -#define DMA_EARS_EDREQ_4_MASK (0x10U) -#define DMA_EARS_EDREQ_4_SHIFT (4U) -#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) -#define DMA_EARS_EDREQ_5_MASK (0x20U) -#define DMA_EARS_EDREQ_5_SHIFT (5U) -#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) -#define DMA_EARS_EDREQ_6_MASK (0x40U) -#define DMA_EARS_EDREQ_6_SHIFT (6U) -#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) -#define DMA_EARS_EDREQ_7_MASK (0x80U) -#define DMA_EARS_EDREQ_7_SHIFT (7U) -#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) -#define DMA_EARS_EDREQ_8_MASK (0x100U) -#define DMA_EARS_EDREQ_8_SHIFT (8U) -#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) -#define DMA_EARS_EDREQ_9_MASK (0x200U) -#define DMA_EARS_EDREQ_9_SHIFT (9U) -#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) -#define DMA_EARS_EDREQ_10_MASK (0x400U) -#define DMA_EARS_EDREQ_10_SHIFT (10U) -#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) -#define DMA_EARS_EDREQ_11_MASK (0x800U) -#define DMA_EARS_EDREQ_11_SHIFT (11U) -#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) -#define DMA_EARS_EDREQ_12_MASK (0x1000U) -#define DMA_EARS_EDREQ_12_SHIFT (12U) -#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) -#define DMA_EARS_EDREQ_13_MASK (0x2000U) -#define DMA_EARS_EDREQ_13_SHIFT (13U) -#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) -#define DMA_EARS_EDREQ_14_MASK (0x4000U) -#define DMA_EARS_EDREQ_14_SHIFT (14U) -#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) -#define DMA_EARS_EDREQ_15_MASK (0x8000U) -#define DMA_EARS_EDREQ_15_SHIFT (15U) -#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) -#define DMA_EARS_EDREQ_16_MASK (0x10000U) -#define DMA_EARS_EDREQ_16_SHIFT (16U) -#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) -#define DMA_EARS_EDREQ_17_MASK (0x20000U) -#define DMA_EARS_EDREQ_17_SHIFT (17U) -#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) -#define DMA_EARS_EDREQ_18_MASK (0x40000U) -#define DMA_EARS_EDREQ_18_SHIFT (18U) -#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) -#define DMA_EARS_EDREQ_19_MASK (0x80000U) -#define DMA_EARS_EDREQ_19_SHIFT (19U) -#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) -#define DMA_EARS_EDREQ_20_MASK (0x100000U) -#define DMA_EARS_EDREQ_20_SHIFT (20U) -#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) -#define DMA_EARS_EDREQ_21_MASK (0x200000U) -#define DMA_EARS_EDREQ_21_SHIFT (21U) -#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) -#define DMA_EARS_EDREQ_22_MASK (0x400000U) -#define DMA_EARS_EDREQ_22_SHIFT (22U) -#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) -#define DMA_EARS_EDREQ_23_MASK (0x800000U) -#define DMA_EARS_EDREQ_23_SHIFT (23U) -#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) -#define DMA_EARS_EDREQ_24_MASK (0x1000000U) -#define DMA_EARS_EDREQ_24_SHIFT (24U) -#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) -#define DMA_EARS_EDREQ_25_MASK (0x2000000U) -#define DMA_EARS_EDREQ_25_SHIFT (25U) -#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) -#define DMA_EARS_EDREQ_26_MASK (0x4000000U) -#define DMA_EARS_EDREQ_26_SHIFT (26U) -#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) -#define DMA_EARS_EDREQ_27_MASK (0x8000000U) -#define DMA_EARS_EDREQ_27_SHIFT (27U) -#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) -#define DMA_EARS_EDREQ_28_MASK (0x10000000U) -#define DMA_EARS_EDREQ_28_SHIFT (28U) -#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) -#define DMA_EARS_EDREQ_29_MASK (0x20000000U) -#define DMA_EARS_EDREQ_29_SHIFT (29U) -#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) -#define DMA_EARS_EDREQ_30_MASK (0x40000000U) -#define DMA_EARS_EDREQ_30_SHIFT (30U) -#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) -#define DMA_EARS_EDREQ_31_MASK (0x80000000U) -#define DMA_EARS_EDREQ_31_SHIFT (31U) -#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) -/*! @} */ - -/*! @name DCHPRI3 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI3_CHPRI_MASK (0xFU) -#define DMA_DCHPRI3_CHPRI_SHIFT (0U) -#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) -#define DMA_DCHPRI3_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI3_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) -#define DMA_DCHPRI3_DPA_MASK (0x40U) -#define DMA_DCHPRI3_DPA_SHIFT (6U) -#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) -#define DMA_DCHPRI3_ECP_MASK (0x80U) -#define DMA_DCHPRI3_ECP_SHIFT (7U) -#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI2 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI2_CHPRI_MASK (0xFU) -#define DMA_DCHPRI2_CHPRI_SHIFT (0U) -#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) -#define DMA_DCHPRI2_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI2_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) -#define DMA_DCHPRI2_DPA_MASK (0x40U) -#define DMA_DCHPRI2_DPA_SHIFT (6U) -#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) -#define DMA_DCHPRI2_ECP_MASK (0x80U) -#define DMA_DCHPRI2_ECP_SHIFT (7U) -#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI1 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI1_CHPRI_MASK (0xFU) -#define DMA_DCHPRI1_CHPRI_SHIFT (0U) -#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) -#define DMA_DCHPRI1_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI1_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) -#define DMA_DCHPRI1_DPA_MASK (0x40U) -#define DMA_DCHPRI1_DPA_SHIFT (6U) -#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) -#define DMA_DCHPRI1_ECP_MASK (0x80U) -#define DMA_DCHPRI1_ECP_SHIFT (7U) -#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI0 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI0_CHPRI_MASK (0xFU) -#define DMA_DCHPRI0_CHPRI_SHIFT (0U) -#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) -#define DMA_DCHPRI0_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI0_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) -#define DMA_DCHPRI0_DPA_MASK (0x40U) -#define DMA_DCHPRI0_DPA_SHIFT (6U) -#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) -#define DMA_DCHPRI0_ECP_MASK (0x80U) -#define DMA_DCHPRI0_ECP_SHIFT (7U) -#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI7 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI7_CHPRI_MASK (0xFU) -#define DMA_DCHPRI7_CHPRI_SHIFT (0U) -#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) -#define DMA_DCHPRI7_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI7_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) -#define DMA_DCHPRI7_DPA_MASK (0x40U) -#define DMA_DCHPRI7_DPA_SHIFT (6U) -#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) -#define DMA_DCHPRI7_ECP_MASK (0x80U) -#define DMA_DCHPRI7_ECP_SHIFT (7U) -#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI6 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI6_CHPRI_MASK (0xFU) -#define DMA_DCHPRI6_CHPRI_SHIFT (0U) -#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) -#define DMA_DCHPRI6_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI6_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) -#define DMA_DCHPRI6_DPA_MASK (0x40U) -#define DMA_DCHPRI6_DPA_SHIFT (6U) -#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) -#define DMA_DCHPRI6_ECP_MASK (0x80U) -#define DMA_DCHPRI6_ECP_SHIFT (7U) -#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI5 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI5_CHPRI_MASK (0xFU) -#define DMA_DCHPRI5_CHPRI_SHIFT (0U) -#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) -#define DMA_DCHPRI5_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI5_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) -#define DMA_DCHPRI5_DPA_MASK (0x40U) -#define DMA_DCHPRI5_DPA_SHIFT (6U) -#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) -#define DMA_DCHPRI5_ECP_MASK (0x80U) -#define DMA_DCHPRI5_ECP_SHIFT (7U) -#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI4 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI4_CHPRI_MASK (0xFU) -#define DMA_DCHPRI4_CHPRI_SHIFT (0U) -#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) -#define DMA_DCHPRI4_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI4_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) -#define DMA_DCHPRI4_DPA_MASK (0x40U) -#define DMA_DCHPRI4_DPA_SHIFT (6U) -#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) -#define DMA_DCHPRI4_ECP_MASK (0x80U) -#define DMA_DCHPRI4_ECP_SHIFT (7U) -#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI11 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI11_CHPRI_MASK (0xFU) -#define DMA_DCHPRI11_CHPRI_SHIFT (0U) -#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) -#define DMA_DCHPRI11_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI11_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) -#define DMA_DCHPRI11_DPA_MASK (0x40U) -#define DMA_DCHPRI11_DPA_SHIFT (6U) -#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) -#define DMA_DCHPRI11_ECP_MASK (0x80U) -#define DMA_DCHPRI11_ECP_SHIFT (7U) -#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI10 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI10_CHPRI_MASK (0xFU) -#define DMA_DCHPRI10_CHPRI_SHIFT (0U) -#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) -#define DMA_DCHPRI10_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI10_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) -#define DMA_DCHPRI10_DPA_MASK (0x40U) -#define DMA_DCHPRI10_DPA_SHIFT (6U) -#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) -#define DMA_DCHPRI10_ECP_MASK (0x80U) -#define DMA_DCHPRI10_ECP_SHIFT (7U) -#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI9 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI9_CHPRI_MASK (0xFU) -#define DMA_DCHPRI9_CHPRI_SHIFT (0U) -#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) -#define DMA_DCHPRI9_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI9_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) -#define DMA_DCHPRI9_DPA_MASK (0x40U) -#define DMA_DCHPRI9_DPA_SHIFT (6U) -#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) -#define DMA_DCHPRI9_ECP_MASK (0x80U) -#define DMA_DCHPRI9_ECP_SHIFT (7U) -#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI8 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI8_CHPRI_MASK (0xFU) -#define DMA_DCHPRI8_CHPRI_SHIFT (0U) -#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) -#define DMA_DCHPRI8_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI8_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) -#define DMA_DCHPRI8_DPA_MASK (0x40U) -#define DMA_DCHPRI8_DPA_SHIFT (6U) -#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) -#define DMA_DCHPRI8_ECP_MASK (0x80U) -#define DMA_DCHPRI8_ECP_SHIFT (7U) -#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI15 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI15_CHPRI_MASK (0xFU) -#define DMA_DCHPRI15_CHPRI_SHIFT (0U) -#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) -#define DMA_DCHPRI15_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI15_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) -#define DMA_DCHPRI15_DPA_MASK (0x40U) -#define DMA_DCHPRI15_DPA_SHIFT (6U) -#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) -#define DMA_DCHPRI15_ECP_MASK (0x80U) -#define DMA_DCHPRI15_ECP_SHIFT (7U) -#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI14 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI14_CHPRI_MASK (0xFU) -#define DMA_DCHPRI14_CHPRI_SHIFT (0U) -#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) -#define DMA_DCHPRI14_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI14_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) -#define DMA_DCHPRI14_DPA_MASK (0x40U) -#define DMA_DCHPRI14_DPA_SHIFT (6U) -#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) -#define DMA_DCHPRI14_ECP_MASK (0x80U) -#define DMA_DCHPRI14_ECP_SHIFT (7U) -#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI13 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI13_CHPRI_MASK (0xFU) -#define DMA_DCHPRI13_CHPRI_SHIFT (0U) -#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) -#define DMA_DCHPRI13_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI13_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) -#define DMA_DCHPRI13_DPA_MASK (0x40U) -#define DMA_DCHPRI13_DPA_SHIFT (6U) -#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) -#define DMA_DCHPRI13_ECP_MASK (0x80U) -#define DMA_DCHPRI13_ECP_SHIFT (7U) -#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI12 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI12_CHPRI_MASK (0xFU) -#define DMA_DCHPRI12_CHPRI_SHIFT (0U) -#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) -#define DMA_DCHPRI12_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI12_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) -#define DMA_DCHPRI12_DPA_MASK (0x40U) -#define DMA_DCHPRI12_DPA_SHIFT (6U) -#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) -#define DMA_DCHPRI12_ECP_MASK (0x80U) -#define DMA_DCHPRI12_ECP_SHIFT (7U) -#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI19 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI19_CHPRI_MASK (0xFU) -#define DMA_DCHPRI19_CHPRI_SHIFT (0U) -#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) -#define DMA_DCHPRI19_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI19_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) -#define DMA_DCHPRI19_DPA_MASK (0x40U) -#define DMA_DCHPRI19_DPA_SHIFT (6U) -#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) -#define DMA_DCHPRI19_ECP_MASK (0x80U) -#define DMA_DCHPRI19_ECP_SHIFT (7U) -#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI18 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI18_CHPRI_MASK (0xFU) -#define DMA_DCHPRI18_CHPRI_SHIFT (0U) -#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) -#define DMA_DCHPRI18_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI18_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) -#define DMA_DCHPRI18_DPA_MASK (0x40U) -#define DMA_DCHPRI18_DPA_SHIFT (6U) -#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) -#define DMA_DCHPRI18_ECP_MASK (0x80U) -#define DMA_DCHPRI18_ECP_SHIFT (7U) -#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI17 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI17_CHPRI_MASK (0xFU) -#define DMA_DCHPRI17_CHPRI_SHIFT (0U) -#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) -#define DMA_DCHPRI17_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI17_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) -#define DMA_DCHPRI17_DPA_MASK (0x40U) -#define DMA_DCHPRI17_DPA_SHIFT (6U) -#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) -#define DMA_DCHPRI17_ECP_MASK (0x80U) -#define DMA_DCHPRI17_ECP_SHIFT (7U) -#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI16 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI16_CHPRI_MASK (0xFU) -#define DMA_DCHPRI16_CHPRI_SHIFT (0U) -#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) -#define DMA_DCHPRI16_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI16_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) -#define DMA_DCHPRI16_DPA_MASK (0x40U) -#define DMA_DCHPRI16_DPA_SHIFT (6U) -#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) -#define DMA_DCHPRI16_ECP_MASK (0x80U) -#define DMA_DCHPRI16_ECP_SHIFT (7U) -#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI23 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI23_CHPRI_MASK (0xFU) -#define DMA_DCHPRI23_CHPRI_SHIFT (0U) -#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) -#define DMA_DCHPRI23_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI23_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) -#define DMA_DCHPRI23_DPA_MASK (0x40U) -#define DMA_DCHPRI23_DPA_SHIFT (6U) -#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) -#define DMA_DCHPRI23_ECP_MASK (0x80U) -#define DMA_DCHPRI23_ECP_SHIFT (7U) -#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI22 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI22_CHPRI_MASK (0xFU) -#define DMA_DCHPRI22_CHPRI_SHIFT (0U) -#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) -#define DMA_DCHPRI22_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI22_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) -#define DMA_DCHPRI22_DPA_MASK (0x40U) -#define DMA_DCHPRI22_DPA_SHIFT (6U) -#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) -#define DMA_DCHPRI22_ECP_MASK (0x80U) -#define DMA_DCHPRI22_ECP_SHIFT (7U) -#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI21 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI21_CHPRI_MASK (0xFU) -#define DMA_DCHPRI21_CHPRI_SHIFT (0U) -#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) -#define DMA_DCHPRI21_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI21_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) -#define DMA_DCHPRI21_DPA_MASK (0x40U) -#define DMA_DCHPRI21_DPA_SHIFT (6U) -#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) -#define DMA_DCHPRI21_ECP_MASK (0x80U) -#define DMA_DCHPRI21_ECP_SHIFT (7U) -#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI20 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI20_CHPRI_MASK (0xFU) -#define DMA_DCHPRI20_CHPRI_SHIFT (0U) -#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) -#define DMA_DCHPRI20_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI20_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) -#define DMA_DCHPRI20_DPA_MASK (0x40U) -#define DMA_DCHPRI20_DPA_SHIFT (6U) -#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) -#define DMA_DCHPRI20_ECP_MASK (0x80U) -#define DMA_DCHPRI20_ECP_SHIFT (7U) -#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI27 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI27_CHPRI_MASK (0xFU) -#define DMA_DCHPRI27_CHPRI_SHIFT (0U) -#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) -#define DMA_DCHPRI27_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI27_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) -#define DMA_DCHPRI27_DPA_MASK (0x40U) -#define DMA_DCHPRI27_DPA_SHIFT (6U) -#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) -#define DMA_DCHPRI27_ECP_MASK (0x80U) -#define DMA_DCHPRI27_ECP_SHIFT (7U) -#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI26 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI26_CHPRI_MASK (0xFU) -#define DMA_DCHPRI26_CHPRI_SHIFT (0U) -#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) -#define DMA_DCHPRI26_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI26_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) -#define DMA_DCHPRI26_DPA_MASK (0x40U) -#define DMA_DCHPRI26_DPA_SHIFT (6U) -#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) -#define DMA_DCHPRI26_ECP_MASK (0x80U) -#define DMA_DCHPRI26_ECP_SHIFT (7U) -#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI25 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI25_CHPRI_MASK (0xFU) -#define DMA_DCHPRI25_CHPRI_SHIFT (0U) -#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) -#define DMA_DCHPRI25_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI25_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) -#define DMA_DCHPRI25_DPA_MASK (0x40U) -#define DMA_DCHPRI25_DPA_SHIFT (6U) -#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) -#define DMA_DCHPRI25_ECP_MASK (0x80U) -#define DMA_DCHPRI25_ECP_SHIFT (7U) -#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI24 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI24_CHPRI_MASK (0xFU) -#define DMA_DCHPRI24_CHPRI_SHIFT (0U) -#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) -#define DMA_DCHPRI24_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI24_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) -#define DMA_DCHPRI24_DPA_MASK (0x40U) -#define DMA_DCHPRI24_DPA_SHIFT (6U) -#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) -#define DMA_DCHPRI24_ECP_MASK (0x80U) -#define DMA_DCHPRI24_ECP_SHIFT (7U) -#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI31 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI31_CHPRI_MASK (0xFU) -#define DMA_DCHPRI31_CHPRI_SHIFT (0U) -#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) -#define DMA_DCHPRI31_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI31_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) -#define DMA_DCHPRI31_DPA_MASK (0x40U) -#define DMA_DCHPRI31_DPA_SHIFT (6U) -#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) -#define DMA_DCHPRI31_ECP_MASK (0x80U) -#define DMA_DCHPRI31_ECP_SHIFT (7U) -#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI30 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI30_CHPRI_MASK (0xFU) -#define DMA_DCHPRI30_CHPRI_SHIFT (0U) -#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) -#define DMA_DCHPRI30_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI30_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) -#define DMA_DCHPRI30_DPA_MASK (0x40U) -#define DMA_DCHPRI30_DPA_SHIFT (6U) -#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) -#define DMA_DCHPRI30_ECP_MASK (0x80U) -#define DMA_DCHPRI30_ECP_SHIFT (7U) -#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI29 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI29_CHPRI_MASK (0xFU) -#define DMA_DCHPRI29_CHPRI_SHIFT (0U) -#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) -#define DMA_DCHPRI29_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI29_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) -#define DMA_DCHPRI29_DPA_MASK (0x40U) -#define DMA_DCHPRI29_DPA_SHIFT (6U) -#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) -#define DMA_DCHPRI29_ECP_MASK (0x80U) -#define DMA_DCHPRI29_ECP_SHIFT (7U) -#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) -/*! @} */ - -/*! @name DCHPRI28 - Channel n Priority Register */ -/*! @{ */ -#define DMA_DCHPRI28_CHPRI_MASK (0xFU) -#define DMA_DCHPRI28_CHPRI_SHIFT (0U) -#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) -#define DMA_DCHPRI28_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI28_GRPPRI_SHIFT (4U) -#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) -#define DMA_DCHPRI28_DPA_MASK (0x40U) -#define DMA_DCHPRI28_DPA_SHIFT (6U) -#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) -#define DMA_DCHPRI28_ECP_MASK (0x80U) -#define DMA_DCHPRI28_ECP_SHIFT (7U) -#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) -/*! @} */ - -/*! @name SADDR - TCD Source Address */ -/*! @{ */ -#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) -#define DMA_SADDR_SADDR_SHIFT (0U) -#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) -/*! @} */ - -/* The count of DMA_SADDR */ -#define DMA_SADDR_COUNT (32U) - -/*! @name SOFF - TCD Signed Source Address Offset */ -/*! @{ */ -#define DMA_SOFF_SOFF_MASK (0xFFFFU) -#define DMA_SOFF_SOFF_SHIFT (0U) -#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) -/*! @} */ - -/* The count of DMA_SOFF */ -#define DMA_SOFF_COUNT (32U) - -/*! @name ATTR - TCD Transfer Attributes */ -/*! @{ */ -#define DMA_ATTR_DSIZE_MASK (0x7U) -#define DMA_ATTR_DSIZE_SHIFT (0U) -#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) -#define DMA_ATTR_DMOD_MASK (0xF8U) -#define DMA_ATTR_DMOD_SHIFT (3U) -#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) -#define DMA_ATTR_SSIZE_MASK (0x700U) -#define DMA_ATTR_SSIZE_SHIFT (8U) -#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) -#define DMA_ATTR_SMOD_MASK (0xF800U) -#define DMA_ATTR_SMOD_SHIFT (11U) -#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) -/*! @} */ - -/* The count of DMA_ATTR */ -#define DMA_ATTR_COUNT (32U) - -/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ -/*! @{ */ -#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) -#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) -/*! @} */ - -/* The count of DMA_NBYTES_MLNO */ -#define DMA_NBYTES_MLNO_COUNT (32U) - -/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ -/*! @{ */ -#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) -#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) -#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) -#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) -#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) -#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) -#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) -#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) -/*! @} */ - -/* The count of DMA_NBYTES_MLOFFNO */ -#define DMA_NBYTES_MLOFFNO_COUNT (32U) - -/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ -/*! @{ */ -#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) -#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) -#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) -#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) -#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) -#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) -#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) -#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) -#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) -#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) -#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) -#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) -/*! @} */ - -/* The count of DMA_NBYTES_MLOFFYES */ -#define DMA_NBYTES_MLOFFYES_COUNT (32U) - -/*! @name SLAST - TCD Last Source Address Adjustment */ -/*! @{ */ -#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) -#define DMA_SLAST_SLAST_SHIFT (0U) -#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) -/*! @} */ - -/* The count of DMA_SLAST */ -#define DMA_SLAST_COUNT (32U) - -/*! @name DADDR - TCD Destination Address */ -/*! @{ */ -#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) -#define DMA_DADDR_DADDR_SHIFT (0U) -#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) -/*! @} */ - -/* The count of DMA_DADDR */ -#define DMA_DADDR_COUNT (32U) - -/*! @name DOFF - TCD Signed Destination Address Offset */ -/*! @{ */ -#define DMA_DOFF_DOFF_MASK (0xFFFFU) -#define DMA_DOFF_DOFF_SHIFT (0U) -#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) -/*! @} */ - -/* The count of DMA_DOFF */ -#define DMA_DOFF_COUNT (32U) - -/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ -/*! @{ */ -#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) -#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) -#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) -#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) -#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) -#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) -/*! @} */ - -/* The count of DMA_CITER_ELINKNO */ -#define DMA_CITER_ELINKNO_COUNT (32U) - -/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ -/*! @{ */ -#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) -#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) -#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) -#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) -#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) -#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) -#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) -#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) -#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) -/*! @} */ - -/* The count of DMA_CITER_ELINKYES */ -#define DMA_CITER_ELINKYES_COUNT (32U) - -/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ -/*! @{ */ -#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) -#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) -#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) -/*! @} */ - -/* The count of DMA_DLAST_SGA */ -#define DMA_DLAST_SGA_COUNT (32U) - -/*! @name CSR - TCD Control and Status */ -/*! @{ */ -#define DMA_CSR_START_MASK (0x1U) -#define DMA_CSR_START_SHIFT (0U) -#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) -#define DMA_CSR_INTMAJOR_MASK (0x2U) -#define DMA_CSR_INTMAJOR_SHIFT (1U) -#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) -#define DMA_CSR_INTHALF_MASK (0x4U) -#define DMA_CSR_INTHALF_SHIFT (2U) -#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) -#define DMA_CSR_DREQ_MASK (0x8U) -#define DMA_CSR_DREQ_SHIFT (3U) -#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) -#define DMA_CSR_ESG_MASK (0x10U) -#define DMA_CSR_ESG_SHIFT (4U) -#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) -#define DMA_CSR_MAJORELINK_MASK (0x20U) -#define DMA_CSR_MAJORELINK_SHIFT (5U) -#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) -#define DMA_CSR_ACTIVE_MASK (0x40U) -#define DMA_CSR_ACTIVE_SHIFT (6U) -#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) -#define DMA_CSR_DONE_MASK (0x80U) -#define DMA_CSR_DONE_SHIFT (7U) -#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) -#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U) -#define DMA_CSR_MAJORLINKCH_SHIFT (8U) -#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) -#define DMA_CSR_BWC_MASK (0xC000U) -#define DMA_CSR_BWC_SHIFT (14U) -#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) -/*! @} */ - -/* The count of DMA_CSR */ -#define DMA_CSR_COUNT (32U) - -/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ -/*! @{ */ -#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) -#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) -#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) -#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) -#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) -#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) -/*! @} */ - -/* The count of DMA_BITER_ELINKNO */ -#define DMA_BITER_ELINKNO_COUNT (32U) - -/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ -/*! @{ */ -#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) -#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) -#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) -#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) -#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) -#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) -#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) -#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) -#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) -/*! @} */ - -/* The count of DMA_BITER_ELINKYES */ -#define DMA_BITER_ELINKYES_COUNT (32U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -/** Peripheral DMA0 base address */ -#define DMA0_BASE (0x400E8000u) -/** Peripheral DMA0 base pointer */ -#define DMA0 ((DMA_Type *)DMA0_BASE) -/** Array initializer of DMA peripheral base addresses */ -#define DMA_BASE_ADDRS { DMA0_BASE } -/** Array initializer of DMA peripheral base pointers */ -#define DMA_BASE_PTRS { DMA0 } -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } } -#define DMA_ERROR_IRQS { DMA_ERROR_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMAMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer - * @{ - */ - -/** DMAMUX - Register Layout Typedef */ -typedef struct { - __IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */ -} DMAMUX_Type; - -/* ---------------------------------------------------------------------------- - -- DMAMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks - * @{ - */ - -/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */ -/*! @{ */ -#define DMAMUX_CHCFG_SOURCE_MASK (0x7FU) -#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) -#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) -#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) -#define DMAMUX_CHCFG_A_ON_SHIFT (29U) -#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) -#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) -#define DMAMUX_CHCFG_TRIG_SHIFT (30U) -#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) -#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) -#define DMAMUX_CHCFG_ENBL_SHIFT (31U) -#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) -/*! @} */ - -/* The count of DMAMUX_CHCFG */ -#define DMAMUX_CHCFG_COUNT (32U) - - -/*! - * @} - */ /* end of group DMAMUX_Register_Masks */ - - -/* DMAMUX - Peripheral instance base addresses */ -/** Peripheral DMAMUX base address */ -#define DMAMUX_BASE (0x400EC000u) -/** Peripheral DMAMUX base pointer */ -#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) -/** Array initializer of DMAMUX peripheral base addresses */ -#define DMAMUX_BASE_ADDRS { DMAMUX_BASE } -/** Array initializer of DMAMUX peripheral base pointers */ -#define DMAMUX_BASE_PTRS { DMAMUX } - -/*! - * @} - */ /* end of group DMAMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ENC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer - * @{ - */ - -/** ENC - Register Layout Typedef */ -typedef struct { - __IO uint16_t CTRL; /**< Control Register, offset: 0x0 */ - __IO uint16_t FILT; /**< Input Filter Register, offset: 0x2 */ - __IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x4 */ - __IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x6 */ - __I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x8 */ - __IO uint16_t REV; /**< Revolution Counter Register, offset: 0xA */ - __I uint16_t REVH; /**< Revolution Hold Register, offset: 0xC */ - __IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xE */ - __IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0x10 */ - __I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x12 */ - __I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x14 */ - __IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x16 */ - __IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x18 */ - __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ - __IO uint16_t TST; /**< Test Register, offset: 0x1C */ - __IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x1E */ - __IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x20 */ - __IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x22 */ - __IO uint16_t UCOMP; /**< Upper Position Compare Register, offset: 0x24 */ - __IO uint16_t LCOMP; /**< Lower Position Compare Register, offset: 0x26 */ -} ENC_Type; - -/* ---------------------------------------------------------------------------- - -- ENC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENC_Register_Masks ENC Register Masks - * @{ - */ - -/*! @name CTRL - Control Register */ -/*! @{ */ -#define ENC_CTRL_CMPIE_MASK (0x1U) -#define ENC_CTRL_CMPIE_SHIFT (0U) -#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) -#define ENC_CTRL_CMPIRQ_MASK (0x2U) -#define ENC_CTRL_CMPIRQ_SHIFT (1U) -#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) -#define ENC_CTRL_WDE_MASK (0x4U) -#define ENC_CTRL_WDE_SHIFT (2U) -#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) -#define ENC_CTRL_DIE_MASK (0x8U) -#define ENC_CTRL_DIE_SHIFT (3U) -#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) -#define ENC_CTRL_DIRQ_MASK (0x10U) -#define ENC_CTRL_DIRQ_SHIFT (4U) -#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) -#define ENC_CTRL_XNE_MASK (0x20U) -#define ENC_CTRL_XNE_SHIFT (5U) -#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) -#define ENC_CTRL_XIP_MASK (0x40U) -#define ENC_CTRL_XIP_SHIFT (6U) -#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) -#define ENC_CTRL_XIE_MASK (0x80U) -#define ENC_CTRL_XIE_SHIFT (7U) -#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) -#define ENC_CTRL_XIRQ_MASK (0x100U) -#define ENC_CTRL_XIRQ_SHIFT (8U) -#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) -#define ENC_CTRL_PH1_MASK (0x200U) -#define ENC_CTRL_PH1_SHIFT (9U) -#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) -#define ENC_CTRL_REV_MASK (0x400U) -#define ENC_CTRL_REV_SHIFT (10U) -#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) -#define ENC_CTRL_SWIP_MASK (0x800U) -#define ENC_CTRL_SWIP_SHIFT (11U) -#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) -#define ENC_CTRL_HNE_MASK (0x1000U) -#define ENC_CTRL_HNE_SHIFT (12U) -#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) -#define ENC_CTRL_HIP_MASK (0x2000U) -#define ENC_CTRL_HIP_SHIFT (13U) -#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) -#define ENC_CTRL_HIE_MASK (0x4000U) -#define ENC_CTRL_HIE_SHIFT (14U) -#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) -#define ENC_CTRL_HIRQ_MASK (0x8000U) -#define ENC_CTRL_HIRQ_SHIFT (15U) -#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) -/*! @} */ - -/*! @name FILT - Input Filter Register */ -/*! @{ */ -#define ENC_FILT_FILT_PER_MASK (0xFFU) -#define ENC_FILT_FILT_PER_SHIFT (0U) -#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) -#define ENC_FILT_FILT_CNT_MASK (0x700U) -#define ENC_FILT_FILT_CNT_SHIFT (8U) -#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) -/*! @} */ - -/*! @name WTR - Watchdog Timeout Register */ -/*! @{ */ -#define ENC_WTR_WDOG_MASK (0xFFFFU) -#define ENC_WTR_WDOG_SHIFT (0U) -#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) -/*! @} */ - -/*! @name POSD - Position Difference Counter Register */ -/*! @{ */ -#define ENC_POSD_POSD_MASK (0xFFFFU) -#define ENC_POSD_POSD_SHIFT (0U) -#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) -/*! @} */ - -/*! @name POSDH - Position Difference Hold Register */ -/*! @{ */ -#define ENC_POSDH_POSDH_MASK (0xFFFFU) -#define ENC_POSDH_POSDH_SHIFT (0U) -#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) -/*! @} */ - -/*! @name REV - Revolution Counter Register */ -/*! @{ */ -#define ENC_REV_REV_MASK (0xFFFFU) -#define ENC_REV_REV_SHIFT (0U) -#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) -/*! @} */ - -/*! @name REVH - Revolution Hold Register */ -/*! @{ */ -#define ENC_REVH_REVH_MASK (0xFFFFU) -#define ENC_REVH_REVH_SHIFT (0U) -#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) -/*! @} */ - -/*! @name UPOS - Upper Position Counter Register */ -/*! @{ */ -#define ENC_UPOS_POS_MASK (0xFFFFU) -#define ENC_UPOS_POS_SHIFT (0U) -#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) -/*! @} */ - -/*! @name LPOS - Lower Position Counter Register */ -/*! @{ */ -#define ENC_LPOS_POS_MASK (0xFFFFU) -#define ENC_LPOS_POS_SHIFT (0U) -#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) -/*! @} */ - -/*! @name UPOSH - Upper Position Hold Register */ -/*! @{ */ -#define ENC_UPOSH_POSH_MASK (0xFFFFU) -#define ENC_UPOSH_POSH_SHIFT (0U) -#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) -/*! @} */ - -/*! @name LPOSH - Lower Position Hold Register */ -/*! @{ */ -#define ENC_LPOSH_POSH_MASK (0xFFFFU) -#define ENC_LPOSH_POSH_SHIFT (0U) -#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) -/*! @} */ - -/*! @name UINIT - Upper Initialization Register */ -/*! @{ */ -#define ENC_UINIT_INIT_MASK (0xFFFFU) -#define ENC_UINIT_INIT_SHIFT (0U) -#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) -/*! @} */ - -/*! @name LINIT - Lower Initialization Register */ -/*! @{ */ -#define ENC_LINIT_INIT_MASK (0xFFFFU) -#define ENC_LINIT_INIT_SHIFT (0U) -#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) -/*! @} */ - -/*! @name IMR - Input Monitor Register */ -/*! @{ */ -#define ENC_IMR_HOME_MASK (0x1U) -#define ENC_IMR_HOME_SHIFT (0U) -#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) -#define ENC_IMR_INDEX_MASK (0x2U) -#define ENC_IMR_INDEX_SHIFT (1U) -#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK) -#define ENC_IMR_PHB_MASK (0x4U) -#define ENC_IMR_PHB_SHIFT (2U) -#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK) -#define ENC_IMR_PHA_MASK (0x8U) -#define ENC_IMR_PHA_SHIFT (3U) -#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK) -#define ENC_IMR_FHOM_MASK (0x10U) -#define ENC_IMR_FHOM_SHIFT (4U) -#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK) -#define ENC_IMR_FIND_MASK (0x20U) -#define ENC_IMR_FIND_SHIFT (5U) -#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK) -#define ENC_IMR_FPHB_MASK (0x40U) -#define ENC_IMR_FPHB_SHIFT (6U) -#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK) -#define ENC_IMR_FPHA_MASK (0x80U) -#define ENC_IMR_FPHA_SHIFT (7U) -#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) -/*! @} */ - -/*! @name TST - Test Register */ -/*! @{ */ -#define ENC_TST_TEST_COUNT_MASK (0xFFU) -#define ENC_TST_TEST_COUNT_SHIFT (0U) -#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) -#define ENC_TST_TEST_PERIOD_MASK (0x1F00U) -#define ENC_TST_TEST_PERIOD_SHIFT (8U) -#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) -#define ENC_TST_QDN_MASK (0x2000U) -#define ENC_TST_QDN_SHIFT (13U) -#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) -#define ENC_TST_TCE_MASK (0x4000U) -#define ENC_TST_TCE_SHIFT (14U) -#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) -#define ENC_TST_TEN_MASK (0x8000U) -#define ENC_TST_TEN_SHIFT (15U) -#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) -/*! @} */ - -/*! @name CTRL2 - Control 2 Register */ -/*! @{ */ -#define ENC_CTRL2_UPDHLD_MASK (0x1U) -#define ENC_CTRL2_UPDHLD_SHIFT (0U) -#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) -#define ENC_CTRL2_UPDPOS_MASK (0x2U) -#define ENC_CTRL2_UPDPOS_SHIFT (1U) -#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) -#define ENC_CTRL2_MOD_MASK (0x4U) -#define ENC_CTRL2_MOD_SHIFT (2U) -#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) -#define ENC_CTRL2_DIR_MASK (0x8U) -#define ENC_CTRL2_DIR_SHIFT (3U) -#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) -#define ENC_CTRL2_RUIE_MASK (0x10U) -#define ENC_CTRL2_RUIE_SHIFT (4U) -#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) -#define ENC_CTRL2_RUIRQ_MASK (0x20U) -#define ENC_CTRL2_RUIRQ_SHIFT (5U) -#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) -#define ENC_CTRL2_ROIE_MASK (0x40U) -#define ENC_CTRL2_ROIE_SHIFT (6U) -#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) -#define ENC_CTRL2_ROIRQ_MASK (0x80U) -#define ENC_CTRL2_ROIRQ_SHIFT (7U) -#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) -#define ENC_CTRL2_REVMOD_MASK (0x100U) -#define ENC_CTRL2_REVMOD_SHIFT (8U) -#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) -#define ENC_CTRL2_OUTCTL_MASK (0x200U) -#define ENC_CTRL2_OUTCTL_SHIFT (9U) -#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) -#define ENC_CTRL2_SABIE_MASK (0x400U) -#define ENC_CTRL2_SABIE_SHIFT (10U) -#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) -#define ENC_CTRL2_SABIRQ_MASK (0x800U) -#define ENC_CTRL2_SABIRQ_SHIFT (11U) -#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) -/*! @} */ - -/*! @name UMOD - Upper Modulus Register */ -/*! @{ */ -#define ENC_UMOD_MOD_MASK (0xFFFFU) -#define ENC_UMOD_MOD_SHIFT (0U) -#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) -/*! @} */ - -/*! @name LMOD - Lower Modulus Register */ -/*! @{ */ -#define ENC_LMOD_MOD_MASK (0xFFFFU) -#define ENC_LMOD_MOD_SHIFT (0U) -#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) -/*! @} */ - -/*! @name UCOMP - Upper Position Compare Register */ -/*! @{ */ -#define ENC_UCOMP_COMP_MASK (0xFFFFU) -#define ENC_UCOMP_COMP_SHIFT (0U) -#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) -/*! @} */ - -/*! @name LCOMP - Lower Position Compare Register */ -/*! @{ */ -#define ENC_LCOMP_COMP_MASK (0xFFFFU) -#define ENC_LCOMP_COMP_SHIFT (0U) -#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ENC_Register_Masks */ - - -/* ENC - Peripheral instance base addresses */ -/** Peripheral ENC1 base address */ -#define ENC1_BASE (0x403C8000u) -/** Peripheral ENC1 base pointer */ -#define ENC1 ((ENC_Type *)ENC1_BASE) -/** Peripheral ENC2 base address */ -#define ENC2_BASE (0x403CC000u) -/** Peripheral ENC2 base pointer */ -#define ENC2 ((ENC_Type *)ENC2_BASE) -/** Peripheral ENC3 base address */ -#define ENC3_BASE (0x403D0000u) -/** Peripheral ENC3 base pointer */ -#define ENC3 ((ENC_Type *)ENC3_BASE) -/** Peripheral ENC4 base address */ -#define ENC4_BASE (0x403D4000u) -/** Peripheral ENC4 base pointer */ -#define ENC4 ((ENC_Type *)ENC4_BASE) -/** Array initializer of ENC peripheral base addresses */ -#define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE } -/** Array initializer of ENC peripheral base pointers */ -#define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 } -/** Interrupt vectors for the ENC peripheral type */ -#define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } -#define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } -#define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } -#define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } -#define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } - -/*! - * @} - */ /* end of group ENC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ENET Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer - * @{ - */ - -/** ENET - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4]; - __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ - __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ - uint8_t RESERVED_1[4]; - __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ - __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ - uint8_t RESERVED_2[12]; - __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ - uint8_t RESERVED_3[24]; - __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ - __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ - uint8_t RESERVED_4[28]; - __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ - uint8_t RESERVED_5[28]; - __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ - uint8_t RESERVED_6[60]; - __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ - uint8_t RESERVED_7[28]; - __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ - __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ - __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ - __IO uint32_t TXIC; /**< Transmit Interrupt Coalescing Register, offset: 0xF0 */ - uint8_t RESERVED_8[12]; - __IO uint32_t RXIC; /**< Receive Interrupt Coalescing Register, offset: 0x100 */ - uint8_t RESERVED_9[20]; - __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ - __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ - __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ - __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ - uint8_t RESERVED_10[28]; - __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ - uint8_t RESERVED_11[56]; - __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ - __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ - __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ - uint8_t RESERVED_12[4]; - __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ - __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ - __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ - __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ - __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ - __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ - __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ - __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ - __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ - uint8_t RESERVED_13[12]; - __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ - __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ - uint8_t RESERVED_14[56]; - uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ - __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ - __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ - __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ - __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ - __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ - __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ - __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ - __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ - __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ - __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ - __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ - __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ - __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ - __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ - __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ - __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ - __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ - uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ - __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ - __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ - __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ - __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ - __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ - __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ - __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ - __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ - __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ - __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ - __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ - uint8_t RESERVED_15[12]; - __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ - __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ - __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ - __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ - __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ - __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ - __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ - __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ - uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ - __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ - __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ - __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ - __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ - __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ - __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ - __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ - __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ - __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ - __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ - __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ - __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ - __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ - __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ - __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ - uint8_t RESERVED_16[284]; - __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ - __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ - __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ - __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ - __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ - __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ - __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ - uint8_t RESERVED_17[488]; - __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ - struct { /* offset: 0x608, array step: 0x8 */ - __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ - __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ - } CHANNEL[4]; -} ENET_Type; - -/* ---------------------------------------------------------------------------- - -- ENET Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENET_Register_Masks ENET Register Masks - * @{ - */ - -/*! @name EIR - Interrupt Event Register */ -/*! @{ */ -#define ENET_EIR_TS_TIMER_MASK (0x8000U) -#define ENET_EIR_TS_TIMER_SHIFT (15U) -#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) -#define ENET_EIR_TS_AVAIL_MASK (0x10000U) -#define ENET_EIR_TS_AVAIL_SHIFT (16U) -#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) -#define ENET_EIR_WAKEUP_MASK (0x20000U) -#define ENET_EIR_WAKEUP_SHIFT (17U) -#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) -#define ENET_EIR_PLR_MASK (0x40000U) -#define ENET_EIR_PLR_SHIFT (18U) -#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) -#define ENET_EIR_UN_MASK (0x80000U) -#define ENET_EIR_UN_SHIFT (19U) -#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) -#define ENET_EIR_RL_MASK (0x100000U) -#define ENET_EIR_RL_SHIFT (20U) -#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) -#define ENET_EIR_LC_MASK (0x200000U) -#define ENET_EIR_LC_SHIFT (21U) -#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) -#define ENET_EIR_EBERR_MASK (0x400000U) -#define ENET_EIR_EBERR_SHIFT (22U) -#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) -#define ENET_EIR_MII_MASK (0x800000U) -#define ENET_EIR_MII_SHIFT (23U) -#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) -#define ENET_EIR_RXB_MASK (0x1000000U) -#define ENET_EIR_RXB_SHIFT (24U) -#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) -#define ENET_EIR_RXF_MASK (0x2000000U) -#define ENET_EIR_RXF_SHIFT (25U) -#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) -#define ENET_EIR_TXB_MASK (0x4000000U) -#define ENET_EIR_TXB_SHIFT (26U) -#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) -#define ENET_EIR_TXF_MASK (0x8000000U) -#define ENET_EIR_TXF_SHIFT (27U) -#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) -#define ENET_EIR_GRA_MASK (0x10000000U) -#define ENET_EIR_GRA_SHIFT (28U) -#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) -#define ENET_EIR_BABT_MASK (0x20000000U) -#define ENET_EIR_BABT_SHIFT (29U) -#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) -#define ENET_EIR_BABR_MASK (0x40000000U) -#define ENET_EIR_BABR_SHIFT (30U) -#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) -/*! @} */ - -/*! @name EIMR - Interrupt Mask Register */ -/*! @{ */ -#define ENET_EIMR_TS_TIMER_MASK (0x8000U) -#define ENET_EIMR_TS_TIMER_SHIFT (15U) -#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) -#define ENET_EIMR_TS_AVAIL_MASK (0x10000U) -#define ENET_EIMR_TS_AVAIL_SHIFT (16U) -#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) -#define ENET_EIMR_WAKEUP_MASK (0x20000U) -#define ENET_EIMR_WAKEUP_SHIFT (17U) -#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) -#define ENET_EIMR_PLR_MASK (0x40000U) -#define ENET_EIMR_PLR_SHIFT (18U) -#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) -#define ENET_EIMR_UN_MASK (0x80000U) -#define ENET_EIMR_UN_SHIFT (19U) -#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) -#define ENET_EIMR_RL_MASK (0x100000U) -#define ENET_EIMR_RL_SHIFT (20U) -#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) -#define ENET_EIMR_LC_MASK (0x200000U) -#define ENET_EIMR_LC_SHIFT (21U) -#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) -#define ENET_EIMR_EBERR_MASK (0x400000U) -#define ENET_EIMR_EBERR_SHIFT (22U) -#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) -#define ENET_EIMR_MII_MASK (0x800000U) -#define ENET_EIMR_MII_SHIFT (23U) -#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) -#define ENET_EIMR_RXB_MASK (0x1000000U) -#define ENET_EIMR_RXB_SHIFT (24U) -#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) -#define ENET_EIMR_RXF_MASK (0x2000000U) -#define ENET_EIMR_RXF_SHIFT (25U) -#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) -#define ENET_EIMR_TXB_MASK (0x4000000U) -#define ENET_EIMR_TXB_SHIFT (26U) -#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) -#define ENET_EIMR_TXF_MASK (0x8000000U) -#define ENET_EIMR_TXF_SHIFT (27U) -#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) -#define ENET_EIMR_GRA_MASK (0x10000000U) -#define ENET_EIMR_GRA_SHIFT (28U) -#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) -#define ENET_EIMR_BABT_MASK (0x20000000U) -#define ENET_EIMR_BABT_SHIFT (29U) -#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) -#define ENET_EIMR_BABR_MASK (0x40000000U) -#define ENET_EIMR_BABR_SHIFT (30U) -#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) -/*! @} */ - -/*! @name RDAR - Receive Descriptor Active Register */ -/*! @{ */ -#define ENET_RDAR_RDAR_MASK (0x1000000U) -#define ENET_RDAR_RDAR_SHIFT (24U) -#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) -/*! @} */ - -/*! @name TDAR - Transmit Descriptor Active Register */ -/*! @{ */ -#define ENET_TDAR_TDAR_MASK (0x1000000U) -#define ENET_TDAR_TDAR_SHIFT (24U) -#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) -/*! @} */ - -/*! @name ECR - Ethernet Control Register */ -/*! @{ */ -#define ENET_ECR_RESET_MASK (0x1U) -#define ENET_ECR_RESET_SHIFT (0U) -#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) -#define ENET_ECR_ETHEREN_MASK (0x2U) -#define ENET_ECR_ETHEREN_SHIFT (1U) -#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) -#define ENET_ECR_MAGICEN_MASK (0x4U) -#define ENET_ECR_MAGICEN_SHIFT (2U) -#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) -#define ENET_ECR_SLEEP_MASK (0x8U) -#define ENET_ECR_SLEEP_SHIFT (3U) -#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) -#define ENET_ECR_EN1588_MASK (0x10U) -#define ENET_ECR_EN1588_SHIFT (4U) -#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) -#define ENET_ECR_DBGEN_MASK (0x40U) -#define ENET_ECR_DBGEN_SHIFT (6U) -#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) -#define ENET_ECR_DBSWP_MASK (0x100U) -#define ENET_ECR_DBSWP_SHIFT (8U) -#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) -/*! @} */ - -/*! @name MMFR - MII Management Frame Register */ -/*! @{ */ -#define ENET_MMFR_DATA_MASK (0xFFFFU) -#define ENET_MMFR_DATA_SHIFT (0U) -#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) -#define ENET_MMFR_TA_MASK (0x30000U) -#define ENET_MMFR_TA_SHIFT (16U) -#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) -#define ENET_MMFR_RA_MASK (0x7C0000U) -#define ENET_MMFR_RA_SHIFT (18U) -#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) -#define ENET_MMFR_PA_MASK (0xF800000U) -#define ENET_MMFR_PA_SHIFT (23U) -#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) -#define ENET_MMFR_OP_MASK (0x30000000U) -#define ENET_MMFR_OP_SHIFT (28U) -#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) -#define ENET_MMFR_ST_MASK (0xC0000000U) -#define ENET_MMFR_ST_SHIFT (30U) -#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) -/*! @} */ - -/*! @name MSCR - MII Speed Control Register */ -/*! @{ */ -#define ENET_MSCR_MII_SPEED_MASK (0x7EU) -#define ENET_MSCR_MII_SPEED_SHIFT (1U) -#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) -#define ENET_MSCR_DIS_PRE_MASK (0x80U) -#define ENET_MSCR_DIS_PRE_SHIFT (7U) -#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) -#define ENET_MSCR_HOLDTIME_MASK (0x700U) -#define ENET_MSCR_HOLDTIME_SHIFT (8U) -#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) -/*! @} */ - -/*! @name MIBC - MIB Control Register */ -/*! @{ */ -#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) -#define ENET_MIBC_MIB_CLEAR_SHIFT (29U) -#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) -#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) -#define ENET_MIBC_MIB_IDLE_SHIFT (30U) -#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) -#define ENET_MIBC_MIB_DIS_MASK (0x80000000U) -#define ENET_MIBC_MIB_DIS_SHIFT (31U) -#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) -/*! @} */ - -/*! @name RCR - Receive Control Register */ -/*! @{ */ -#define ENET_RCR_LOOP_MASK (0x1U) -#define ENET_RCR_LOOP_SHIFT (0U) -#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) -#define ENET_RCR_DRT_MASK (0x2U) -#define ENET_RCR_DRT_SHIFT (1U) -#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) -#define ENET_RCR_MII_MODE_MASK (0x4U) -#define ENET_RCR_MII_MODE_SHIFT (2U) -#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) -#define ENET_RCR_PROM_MASK (0x8U) -#define ENET_RCR_PROM_SHIFT (3U) -#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) -#define ENET_RCR_BC_REJ_MASK (0x10U) -#define ENET_RCR_BC_REJ_SHIFT (4U) -#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) -#define ENET_RCR_FCE_MASK (0x20U) -#define ENET_RCR_FCE_SHIFT (5U) -#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) -#define ENET_RCR_RMII_MODE_MASK (0x100U) -#define ENET_RCR_RMII_MODE_SHIFT (8U) -#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) -#define ENET_RCR_RMII_10T_MASK (0x200U) -#define ENET_RCR_RMII_10T_SHIFT (9U) -#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) -#define ENET_RCR_PADEN_MASK (0x1000U) -#define ENET_RCR_PADEN_SHIFT (12U) -#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) -#define ENET_RCR_PAUFWD_MASK (0x2000U) -#define ENET_RCR_PAUFWD_SHIFT (13U) -#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) -#define ENET_RCR_CRCFWD_MASK (0x4000U) -#define ENET_RCR_CRCFWD_SHIFT (14U) -#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) -#define ENET_RCR_CFEN_MASK (0x8000U) -#define ENET_RCR_CFEN_SHIFT (15U) -#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) -#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) -#define ENET_RCR_MAX_FL_SHIFT (16U) -#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) -#define ENET_RCR_NLC_MASK (0x40000000U) -#define ENET_RCR_NLC_SHIFT (30U) -#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) -#define ENET_RCR_GRS_MASK (0x80000000U) -#define ENET_RCR_GRS_SHIFT (31U) -#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) -/*! @} */ - -/*! @name TCR - Transmit Control Register */ -/*! @{ */ -#define ENET_TCR_GTS_MASK (0x1U) -#define ENET_TCR_GTS_SHIFT (0U) -#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) -#define ENET_TCR_FDEN_MASK (0x4U) -#define ENET_TCR_FDEN_SHIFT (2U) -#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) -#define ENET_TCR_TFC_PAUSE_MASK (0x8U) -#define ENET_TCR_TFC_PAUSE_SHIFT (3U) -#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) -#define ENET_TCR_RFC_PAUSE_MASK (0x10U) -#define ENET_TCR_RFC_PAUSE_SHIFT (4U) -#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) -#define ENET_TCR_ADDSEL_MASK (0xE0U) -#define ENET_TCR_ADDSEL_SHIFT (5U) -#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) -#define ENET_TCR_ADDINS_MASK (0x100U) -#define ENET_TCR_ADDINS_SHIFT (8U) -#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) -#define ENET_TCR_CRCFWD_MASK (0x200U) -#define ENET_TCR_CRCFWD_SHIFT (9U) -#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) -/*! @} */ - -/*! @name PALR - Physical Address Lower Register */ -/*! @{ */ -#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) -#define ENET_PALR_PADDR1_SHIFT (0U) -#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) -/*! @} */ - -/*! @name PAUR - Physical Address Upper Register */ -/*! @{ */ -#define ENET_PAUR_TYPE_MASK (0xFFFFU) -#define ENET_PAUR_TYPE_SHIFT (0U) -#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) -#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) -#define ENET_PAUR_PADDR2_SHIFT (16U) -#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) -/*! @} */ - -/*! @name OPD - Opcode/Pause Duration Register */ -/*! @{ */ -#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) -#define ENET_OPD_PAUSE_DUR_SHIFT (0U) -#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) -#define ENET_OPD_OPCODE_MASK (0xFFFF0000U) -#define ENET_OPD_OPCODE_SHIFT (16U) -#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) -/*! @} */ - -/*! @name TXIC - Transmit Interrupt Coalescing Register */ -/*! @{ */ -#define ENET_TXIC_ICTT_MASK (0xFFFFU) -#define ENET_TXIC_ICTT_SHIFT (0U) -#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) -#define ENET_TXIC_ICFT_MASK (0xFF00000U) -#define ENET_TXIC_ICFT_SHIFT (20U) -#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) -#define ENET_TXIC_ICCS_MASK (0x40000000U) -#define ENET_TXIC_ICCS_SHIFT (30U) -#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) -#define ENET_TXIC_ICEN_MASK (0x80000000U) -#define ENET_TXIC_ICEN_SHIFT (31U) -#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) -/*! @} */ - -/*! @name RXIC - Receive Interrupt Coalescing Register */ -/*! @{ */ -#define ENET_RXIC_ICTT_MASK (0xFFFFU) -#define ENET_RXIC_ICTT_SHIFT (0U) -#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) -#define ENET_RXIC_ICFT_MASK (0xFF00000U) -#define ENET_RXIC_ICFT_SHIFT (20U) -#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) -#define ENET_RXIC_ICCS_MASK (0x40000000U) -#define ENET_RXIC_ICCS_SHIFT (30U) -#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) -#define ENET_RXIC_ICEN_MASK (0x80000000U) -#define ENET_RXIC_ICEN_SHIFT (31U) -#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) -/*! @} */ - -/*! @name IAUR - Descriptor Individual Upper Address Register */ -/*! @{ */ -#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) -#define ENET_IAUR_IADDR1_SHIFT (0U) -#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) -/*! @} */ - -/*! @name IALR - Descriptor Individual Lower Address Register */ -/*! @{ */ -#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) -#define ENET_IALR_IADDR2_SHIFT (0U) -#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) -/*! @} */ - -/*! @name GAUR - Descriptor Group Upper Address Register */ -/*! @{ */ -#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) -#define ENET_GAUR_GADDR1_SHIFT (0U) -#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) -/*! @} */ - -/*! @name GALR - Descriptor Group Lower Address Register */ -/*! @{ */ -#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) -#define ENET_GALR_GADDR2_SHIFT (0U) -#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) -/*! @} */ - -/*! @name TFWR - Transmit FIFO Watermark Register */ -/*! @{ */ -#define ENET_TFWR_TFWR_MASK (0x3FU) -#define ENET_TFWR_TFWR_SHIFT (0U) -#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) -#define ENET_TFWR_STRFWD_MASK (0x100U) -#define ENET_TFWR_STRFWD_SHIFT (8U) -#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) -/*! @} */ - -/*! @name RDSR - Receive Descriptor Ring Start Register */ -/*! @{ */ -#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) -#define ENET_RDSR_R_DES_START_SHIFT (3U) -#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) -/*! @} */ - -/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ -/*! @{ */ -#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) -#define ENET_TDSR_X_DES_START_SHIFT (3U) -#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) -/*! @} */ - -/*! @name MRBR - Maximum Receive Buffer Size Register */ -/*! @{ */ -#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) -#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) -#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) -/*! @} */ - -/*! @name RSFL - Receive FIFO Section Full Threshold */ -/*! @{ */ -#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) -#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) -#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) -/*! @} */ - -/*! @name RSEM - Receive FIFO Section Empty Threshold */ -/*! @{ */ -#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) -#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) -#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) -#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) -#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) -#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) -/*! @} */ - -/*! @name RAEM - Receive FIFO Almost Empty Threshold */ -/*! @{ */ -#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) -#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) -#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) -/*! @} */ - -/*! @name RAFL - Receive FIFO Almost Full Threshold */ -/*! @{ */ -#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) -#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) -#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) -/*! @} */ - -/*! @name TSEM - Transmit FIFO Section Empty Threshold */ -/*! @{ */ -#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) -#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) -#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) -/*! @} */ - -/*! @name TAEM - Transmit FIFO Almost Empty Threshold */ -/*! @{ */ -#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) -#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) -#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) -/*! @} */ - -/*! @name TAFL - Transmit FIFO Almost Full Threshold */ -/*! @{ */ -#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) -#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) -#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) -/*! @} */ - -/*! @name TIPG - Transmit Inter-Packet Gap */ -/*! @{ */ -#define ENET_TIPG_IPG_MASK (0x1FU) -#define ENET_TIPG_IPG_SHIFT (0U) -#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) -/*! @} */ - -/*! @name FTRL - Frame Truncation Length */ -/*! @{ */ -#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) -#define ENET_FTRL_TRUNC_FL_SHIFT (0U) -#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) -/*! @} */ - -/*! @name TACC - Transmit Accelerator Function Configuration */ -/*! @{ */ -#define ENET_TACC_SHIFT16_MASK (0x1U) -#define ENET_TACC_SHIFT16_SHIFT (0U) -#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) -#define ENET_TACC_IPCHK_MASK (0x8U) -#define ENET_TACC_IPCHK_SHIFT (3U) -#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) -#define ENET_TACC_PROCHK_MASK (0x10U) -#define ENET_TACC_PROCHK_SHIFT (4U) -#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) -/*! @} */ - -/*! @name RACC - Receive Accelerator Function Configuration */ -/*! @{ */ -#define ENET_RACC_PADREM_MASK (0x1U) -#define ENET_RACC_PADREM_SHIFT (0U) -#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) -#define ENET_RACC_IPDIS_MASK (0x2U) -#define ENET_RACC_IPDIS_SHIFT (1U) -#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) -#define ENET_RACC_PRODIS_MASK (0x4U) -#define ENET_RACC_PRODIS_SHIFT (2U) -#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) -#define ENET_RACC_LINEDIS_MASK (0x40U) -#define ENET_RACC_LINEDIS_SHIFT (6U) -#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) -#define ENET_RACC_SHIFT16_MASK (0x80U) -#define ENET_RACC_SHIFT16_SHIFT (7U) -#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) -/*! @} */ - -/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_COL - Tx Collision Count Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) -#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) -#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) -/*! @} */ - -/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ -/*! @{ */ -#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) -#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) -#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) -/*! @} */ - -/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ -/*! @{ */ -#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) -#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ -/*! @{ */ -#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) -#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ -/*! @{ */ -#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) -#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ -/*! @{ */ -#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) -#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ -/*! @{ */ -#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) -#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ -/*! @{ */ -#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) -#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ -/*! @{ */ -#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) -#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ -/*! @{ */ -#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) -#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_T_SQE - Reserved Statistic Register */ -/*! @{ */ -#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) -#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ -/*! @{ */ -#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) -#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ -/*! @{ */ -#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) -#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) -#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) -#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) -#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) -#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) -#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) -#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) -#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) -#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) -#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_P64_COUNT_SHIFT (0U) -#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) -#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) -#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) -#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) -#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) -#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) -#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) -#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) -/*! @} */ - -/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ -/*! @{ */ -#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) -#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) -#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ -/*! @{ */ -#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) -#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ -/*! @{ */ -#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) -#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ -/*! @{ */ -#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) -#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ -/*! @{ */ -#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) -#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ -/*! @{ */ -#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) -#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ -/*! @{ */ -#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) -#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) -#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) -/*! @} */ - -/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ -/*! @{ */ -#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) -#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) -#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) -/*! @} */ - -/*! @name ATCR - Adjustable Timer Control Register */ -/*! @{ */ -#define ENET_ATCR_EN_MASK (0x1U) -#define ENET_ATCR_EN_SHIFT (0U) -#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) -#define ENET_ATCR_OFFEN_MASK (0x4U) -#define ENET_ATCR_OFFEN_SHIFT (2U) -#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) -#define ENET_ATCR_OFFRST_MASK (0x8U) -#define ENET_ATCR_OFFRST_SHIFT (3U) -#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) -#define ENET_ATCR_PEREN_MASK (0x10U) -#define ENET_ATCR_PEREN_SHIFT (4U) -#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) -#define ENET_ATCR_PINPER_MASK (0x80U) -#define ENET_ATCR_PINPER_SHIFT (7U) -#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) -#define ENET_ATCR_RESTART_MASK (0x200U) -#define ENET_ATCR_RESTART_SHIFT (9U) -#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) -#define ENET_ATCR_CAPTURE_MASK (0x800U) -#define ENET_ATCR_CAPTURE_SHIFT (11U) -#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) -#define ENET_ATCR_SLAVE_MASK (0x2000U) -#define ENET_ATCR_SLAVE_SHIFT (13U) -#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) -/*! @} */ - -/*! @name ATVR - Timer Value Register */ -/*! @{ */ -#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) -#define ENET_ATVR_ATIME_SHIFT (0U) -#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) -/*! @} */ - -/*! @name ATOFF - Timer Offset Register */ -/*! @{ */ -#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) -#define ENET_ATOFF_OFFSET_SHIFT (0U) -#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) -/*! @} */ - -/*! @name ATPER - Timer Period Register */ -/*! @{ */ -#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) -#define ENET_ATPER_PERIOD_SHIFT (0U) -#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) -/*! @} */ - -/*! @name ATCOR - Timer Correction Register */ -/*! @{ */ -#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) -#define ENET_ATCOR_COR_SHIFT (0U) -#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) -/*! @} */ - -/*! @name ATINC - Time-Stamping Clock Period Register */ -/*! @{ */ -#define ENET_ATINC_INC_MASK (0x7FU) -#define ENET_ATINC_INC_SHIFT (0U) -#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) -#define ENET_ATINC_INC_CORR_MASK (0x7F00U) -#define ENET_ATINC_INC_CORR_SHIFT (8U) -#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) -/*! @} */ - -/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ -/*! @{ */ -#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) -#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) -#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) -/*! @} */ - -/*! @name TGSR - Timer Global Status Register */ -/*! @{ */ -#define ENET_TGSR_TF0_MASK (0x1U) -#define ENET_TGSR_TF0_SHIFT (0U) -#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) -#define ENET_TGSR_TF1_MASK (0x2U) -#define ENET_TGSR_TF1_SHIFT (1U) -#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) -#define ENET_TGSR_TF2_MASK (0x4U) -#define ENET_TGSR_TF2_SHIFT (2U) -#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) -#define ENET_TGSR_TF3_MASK (0x8U) -#define ENET_TGSR_TF3_SHIFT (3U) -#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) -/*! @} */ - -/*! @name TCSR - Timer Control Status Register */ -/*! @{ */ -#define ENET_TCSR_TDRE_MASK (0x1U) -#define ENET_TCSR_TDRE_SHIFT (0U) -#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) -#define ENET_TCSR_TMODE_MASK (0x3CU) -#define ENET_TCSR_TMODE_SHIFT (2U) -#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) -#define ENET_TCSR_TIE_MASK (0x40U) -#define ENET_TCSR_TIE_SHIFT (6U) -#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) -#define ENET_TCSR_TF_MASK (0x80U) -#define ENET_TCSR_TF_SHIFT (7U) -#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) -#define ENET_TCSR_TPWC_MASK (0xF800U) -#define ENET_TCSR_TPWC_SHIFT (11U) -#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) -/*! @} */ - -/* The count of ENET_TCSR */ -#define ENET_TCSR_COUNT (4U) - -/*! @name TCCR - Timer Compare Capture Register */ -/*! @{ */ -#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) -#define ENET_TCCR_TCC_SHIFT (0U) -#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) -/*! @} */ - -/* The count of ENET_TCCR */ -#define ENET_TCCR_COUNT (4U) - - -/*! - * @} - */ /* end of group ENET_Register_Masks */ - - -/* ENET - Peripheral instance base addresses */ -/** Peripheral ENET base address */ -#define ENET_BASE (0x402D8000u) -/** Peripheral ENET base pointer */ -#define ENET ((ENET_Type *)ENET_BASE) -/** Array initializer of ENET peripheral base addresses */ -#define ENET_BASE_ADDRS { ENET_BASE } -/** Array initializer of ENET peripheral base pointers */ -#define ENET_BASE_PTRS { ENET } -/** Interrupt vectors for the ENET peripheral type */ -#define ENET_Transmit_IRQS { ENET_IRQn } -#define ENET_Receive_IRQS { ENET_IRQn } -#define ENET_Error_IRQS { ENET_IRQn } -#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn } -/* ENET Buffer Descriptor and Buffer Address Alignment. */ -#define ENET_BUFF_ALIGNMENT (64U) - - -/*! - * @} - */ /* end of group ENET_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- EWM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer - * @{ - */ - -/** EWM - Register Layout Typedef */ -typedef struct { - __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ - __O uint8_t SERV; /**< Service Register, offset: 0x1 */ - __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ - __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ - __IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */ - __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ -} EWM_Type; - -/* ---------------------------------------------------------------------------- - -- EWM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EWM_Register_Masks EWM Register Masks - * @{ - */ - -/*! @name CTRL - Control Register */ -/*! @{ */ -#define EWM_CTRL_EWMEN_MASK (0x1U) -#define EWM_CTRL_EWMEN_SHIFT (0U) -#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) -#define EWM_CTRL_ASSIN_MASK (0x2U) -#define EWM_CTRL_ASSIN_SHIFT (1U) -#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) -#define EWM_CTRL_INEN_MASK (0x4U) -#define EWM_CTRL_INEN_SHIFT (2U) -#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) -#define EWM_CTRL_INTEN_MASK (0x8U) -#define EWM_CTRL_INTEN_SHIFT (3U) -#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) -/*! @} */ - -/*! @name SERV - Service Register */ -/*! @{ */ -#define EWM_SERV_SERVICE_MASK (0xFFU) -#define EWM_SERV_SERVICE_SHIFT (0U) -#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) -/*! @} */ - -/*! @name CMPL - Compare Low Register */ -/*! @{ */ -#define EWM_CMPL_COMPAREL_MASK (0xFFU) -#define EWM_CMPL_COMPAREL_SHIFT (0U) -#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) -/*! @} */ - -/*! @name CMPH - Compare High Register */ -/*! @{ */ -#define EWM_CMPH_COMPAREH_MASK (0xFFU) -#define EWM_CMPH_COMPAREH_SHIFT (0U) -#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) -/*! @} */ - -/*! @name CLKCTRL - Clock Control Register */ -/*! @{ */ -#define EWM_CLKCTRL_CLKSEL_MASK (0x3U) -#define EWM_CLKCTRL_CLKSEL_SHIFT (0U) -#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) -/*! @} */ - -/*! @name CLKPRESCALER - Clock Prescaler Register */ -/*! @{ */ -#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) -#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) -#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group EWM_Register_Masks */ - - -/* EWM - Peripheral instance base addresses */ -/** Peripheral EWM base address */ -#define EWM_BASE (0x400B4000u) -/** Peripheral EWM base pointer */ -#define EWM ((EWM_Type *)EWM_BASE) -/** Array initializer of EWM peripheral base addresses */ -#define EWM_BASE_ADDRS { EWM_BASE } -/** Array initializer of EWM peripheral base pointers */ -#define EWM_BASE_PTRS { EWM } -/** Interrupt vectors for the EWM peripheral type */ -#define EWM_IRQS { EWM_IRQn } - -/*! - * @} - */ /* end of group EWM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer - * @{ - */ - -/** FLEXIO - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ - __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ - __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ - __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ - __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ - __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ - __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ - uint8_t RESERVED_2[12]; - __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ - uint8_t RESERVED_3[60]; - __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_4[112]; - __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_5[240]; - __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_6[112]; - __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ - uint8_t RESERVED_7[112]; - __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ - uint8_t RESERVED_8[112]; - __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ - uint8_t RESERVED_9[112]; - __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ - uint8_t RESERVED_10[112]; - __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ - uint8_t RESERVED_11[112]; - __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ - uint8_t RESERVED_12[368]; - __IO uint32_t SHIFTBUFNBS[4]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ - uint8_t RESERVED_13[112]; - __IO uint32_t SHIFTBUFHWS[4]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ - uint8_t RESERVED_14[112]; - __IO uint32_t SHIFTBUFNIS[4]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ -} FLEXIO_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) -#define FLEXIO_VERID_FEATURE_SHIFT (0U) -#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) -#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) -#define FLEXIO_VERID_MINOR_SHIFT (16U) -#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) -#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) -#define FLEXIO_VERID_MAJOR_SHIFT (24U) -#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) -#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) -#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) -#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) -#define FLEXIO_PARAM_TIMER_SHIFT (8U) -#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) -#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) -#define FLEXIO_PARAM_PIN_SHIFT (16U) -#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) -#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) -#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) -#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) -/*! @} */ - -/*! @name CTRL - FlexIO Control Register */ -/*! @{ */ -#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) -#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) -#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) -#define FLEXIO_CTRL_SWRST_MASK (0x2U) -#define FLEXIO_CTRL_SWRST_SHIFT (1U) -#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) -#define FLEXIO_CTRL_FASTACC_MASK (0x4U) -#define FLEXIO_CTRL_FASTACC_SHIFT (2U) -#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) -#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) -#define FLEXIO_CTRL_DBGE_SHIFT (30U) -#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) -#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) -#define FLEXIO_CTRL_DOZEN_SHIFT (31U) -#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) -/*! @} */ - -/*! @name PIN - Pin State Register */ -/*! @{ */ -#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) -#define FLEXIO_PIN_PDI_SHIFT (0U) -#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) -/*! @} */ - -/*! @name SHIFTSTAT - Shifter Status Register */ -/*! @{ */ -#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) -#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) -#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) -/*! @} */ - -/*! @name SHIFTERR - Shifter Error Register */ -/*! @{ */ -#define FLEXIO_SHIFTERR_SEF_MASK (0xFU) -#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) -#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) -/*! @} */ - -/*! @name TIMSTAT - Timer Status Register */ -/*! @{ */ -#define FLEXIO_TIMSTAT_TSF_MASK (0xFU) -#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) -#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) -/*! @} */ - -/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ -/*! @{ */ -#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) -#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) -#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) -/*! @} */ - -/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ -/*! @{ */ -#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) -#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) -#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) -/*! @} */ - -/*! @name TIMIEN - Timer Interrupt Enable Register */ -/*! @{ */ -#define FLEXIO_TIMIEN_TEIE_MASK (0xFU) -#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) -#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) -/*! @} */ - -/*! @name SHIFTSDEN - Shifter Status DMA Enable */ -/*! @{ */ -#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) -#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) -#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) -/*! @} */ - -/*! @name SHIFTSTATE - Shifter State Register */ -/*! @{ */ -#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) -#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) -#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) -/*! @} */ - -/*! @name SHIFTCTL - Shifter Control N Register */ -/*! @{ */ -#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) -#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) -#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) -#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) -#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) -#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) -#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) -#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) -#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) -#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) -#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) -#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) -#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) -#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) -#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) -#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) -#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) -#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTCTL */ -#define FLEXIO_SHIFTCTL_COUNT (4U) - -/*! @name SHIFTCFG - Shifter Configuration N Register */ -/*! @{ */ -#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) -#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) -#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) -#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) -#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) -#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) -#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) -#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) -#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) -#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) -#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) -#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTCFG */ -#define FLEXIO_SHIFTCFG_COUNT (4U) - -/*! @name SHIFTBUF - Shifter Buffer N Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) -#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUF */ -#define FLEXIO_SHIFTBUF_COUNT (4U) - -/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) -#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFBIS */ -#define FLEXIO_SHIFTBUFBIS_COUNT (4U) - -/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) -#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFBYS */ -#define FLEXIO_SHIFTBUFBYS_COUNT (4U) - -/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) -#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFBBS */ -#define FLEXIO_SHIFTBUFBBS_COUNT (4U) - -/*! @name TIMCTL - Timer Control N Register */ -/*! @{ */ -#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) -#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) -#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) -#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) -#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) -#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) -#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) -#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) -#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) -#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) -#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) -#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) -#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) -#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) -#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) -#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) -#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) -#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) -#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) -#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) -#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) -/*! @} */ - -/* The count of FLEXIO_TIMCTL */ -#define FLEXIO_TIMCTL_COUNT (4U) - -/*! @name TIMCFG - Timer Configuration N Register */ -/*! @{ */ -#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) -#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) -#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) -#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) -#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) -#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) -#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) -#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) -#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) -#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) -#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) -#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) -#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) -#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) -#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) -#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) -#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) -#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) -#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) -#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) -#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) -/*! @} */ - -/* The count of FLEXIO_TIMCFG */ -#define FLEXIO_TIMCFG_COUNT (4U) - -/*! @name TIMCMP - Timer Compare N Register */ -/*! @{ */ -#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) -#define FLEXIO_TIMCMP_CMP_SHIFT (0U) -#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) -/*! @} */ - -/* The count of FLEXIO_TIMCMP */ -#define FLEXIO_TIMCMP_COUNT (4U) - -/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) -#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFNBS */ -#define FLEXIO_SHIFTBUFNBS_COUNT (4U) - -/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) -#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFHWS */ -#define FLEXIO_SHIFTBUFHWS_COUNT (4U) - -/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ -/*! @{ */ -#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) -#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) -#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) -/*! @} */ - -/* The count of FLEXIO_SHIFTBUFNIS */ -#define FLEXIO_SHIFTBUFNIS_COUNT (4U) - - -/*! - * @} - */ /* end of group FLEXIO_Register_Masks */ - - -/* FLEXIO - Peripheral instance base addresses */ -/** Peripheral FLEXIO1 base address */ -#define FLEXIO1_BASE (0x401AC000u) -/** Peripheral FLEXIO1 base pointer */ -#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE) -/** Peripheral FLEXIO2 base address */ -#define FLEXIO2_BASE (0x401B0000u) -/** Peripheral FLEXIO2 base pointer */ -#define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE) -/** Array initializer of FLEXIO peripheral base addresses */ -#define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE } -/** Array initializer of FLEXIO peripheral base pointers */ -#define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 } -/** Interrupt vectors for the FLEXIO peripheral type */ -#define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn } - -/*! - * @} - */ /* end of group FLEXIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXRAM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer - * @{ - */ - -/** FLEXRAM - Register Layout Typedef */ -typedef struct { - __IO uint32_t TCM_CTRL; /**< TCM CRTL Register, offset: 0x0 */ - __IO uint32_t OCRAM_MAGIC_ADDR; /**< OCRAM Magic Address Register, offset: 0x4 */ - __IO uint32_t DTCM_MAGIC_ADDR; /**< DTCM Magic Address Register, offset: 0x8 */ - __IO uint32_t ITCM_MAGIC_ADDR; /**< ITCM Magic Address Register, offset: 0xC */ - __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ - __IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */ - __IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */ -} FLEXRAM_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXRAM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks - * @{ - */ - -/*! @name TCM_CTRL - TCM CRTL Register */ -/*! @{ */ -#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U) -#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U) -#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK) -#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U) -#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U) -#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK) -#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) -#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) -#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) -#define FLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U) -#define FLEXRAM_TCM_CTRL_Reserved_SHIFT (3U) -#define FLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK) -/*! @} */ - -/*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */ -/*! @{ */ -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK) -/*! @} */ - -/*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */ -/*! @{ */ -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK) -/*! @} */ - -/*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */ -/*! @{ */ -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U) -#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U) -#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt Status Register */ -/*! @{ */ -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U) -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U) -#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK) -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U) -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U) -#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK) -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U) -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U) -#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK) -#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U) -#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U) -#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) -#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U) -#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U) -#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) -#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U) -#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U) -#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) -#define FLEXRAM_INT_STATUS_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_STATUS_Reserved_SHIFT (6U) -#define FLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK) -/*! @} */ - -/*! @name INT_STAT_EN - Interrupt Status Enable Register */ -/*! @{ */ -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U) -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U) -#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U) -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U) -#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U) -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U) -#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) -#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) -#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U) -#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U) -#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U) -#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U) -#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) -#define FLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_STAT_EN_Reserved_SHIFT (6U) -#define FLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK) -/*! @} */ - -/*! @name INT_SIG_EN - Interrupt Enable Register */ -/*! @{ */ -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U) -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U) -#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U) -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U) -#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U) -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U) -#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) -#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) -#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U) -#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U) -#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U) -#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U) -#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) -#define FLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFFFFC0U) -#define FLEXRAM_INT_SIG_EN_Reserved_SHIFT (6U) -#define FLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLEXRAM_Register_Masks */ - - -/* FLEXRAM - Peripheral instance base addresses */ -/** Peripheral FLEXRAM base address */ -#define FLEXRAM_BASE (0x400B0000u) -/** Peripheral FLEXRAM base pointer */ -#define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE) -/** Array initializer of FLEXRAM peripheral base addresses */ -#define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE } -/** Array initializer of FLEXRAM peripheral base pointers */ -#define FLEXRAM_BASE_PTRS { FLEXRAM } -/** Interrupt vectors for the FLEXRAM peripheral type */ -#define FLEXRAM_IRQS { FLEXRAM_IRQn } - -/*! - * @} - */ /* end of group FLEXRAM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXSPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer - * @{ - */ - -/** FLEXSPI - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ - __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */ - __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */ - __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */ - __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */ - __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ - __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ - __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ - __IO uint32_t AHBRXBUFCR0[4]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_0[48]; - __IO uint32_t FLSHCR0[4]; /**< Flash A1 Control Register 0..Flash B2 Control Register 0, array offset: 0x60, array step: 0x4 */ - __IO uint32_t FLSHCR1[4]; /**< Flash A1 Control Register 1..Flash B2 Control Register 1, array offset: 0x70, array step: 0x4 */ - __IO uint32_t FLSHCR2[4]; /**< Flash A1 Control Register 2..Flash B2 Control Register 2, array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_1[4]; - __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ - uint8_t RESERVED_2[8]; - __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */ - __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ - uint8_t RESERVED_3[8]; - __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */ - uint8_t RESERVED_4[4]; - __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ - __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ - __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_5[24]; - __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ - __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ - __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */ - __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */ - __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ - __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */ - uint8_t RESERVED_6[8]; - __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ - __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ - __IO uint32_t LUT[64]; /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */ -} FLEXSPI_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXSPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks - * @{ - */ - -/*! @name MCR0 - Module Control Register 0 */ -/*! @{ */ -#define FLEXSPI_MCR0_SWRESET_MASK (0x1U) -#define FLEXSPI_MCR0_SWRESET_SHIFT (0U) -#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) -#define FLEXSPI_MCR0_MDIS_MASK (0x2U) -#define FLEXSPI_MCR0_MDIS_SHIFT (1U) -#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) -#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) -#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) -#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) -#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) -#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) -#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) -#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) -#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) -#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) -#define FLEXSPI_MCR0_HSEN_MASK (0x800U) -#define FLEXSPI_MCR0_HSEN_SHIFT (11U) -#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) -#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) -#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) -#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) -#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) -#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) -#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) -#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) -#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) -#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) -#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) -#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) -#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) -#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) -#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) -#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) -/*! @} */ - -/*! @name MCR1 - Module Control Register 1 */ -/*! @{ */ -#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) -#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) -#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) -#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) -#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) -#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) -/*! @} */ - -/*! @name MCR2 - Module Control Register 2 */ -/*! @{ */ -#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) -#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) -#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) -#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) -#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) -#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) -#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) -#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) -#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) -#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) -#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) -#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) -#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) -#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) -#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) -/*! @} */ - -/*! @name AHBCR - AHB Bus Control Register */ -/*! @{ */ -#define FLEXSPI_AHBCR_APAREN_MASK (0x1U) -#define FLEXSPI_AHBCR_APAREN_SHIFT (0U) -#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) -#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) -#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) -#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) -#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) -#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) -#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) -#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) -#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) -#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) -#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) -#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) -#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) -/*! @} */ - -/*! @name INTEN - Interrupt Enable Register */ -/*! @{ */ -#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) -#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) -#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) -#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) -#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) -#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) -#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) -#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) -#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) -#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) -#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) -#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) -#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) -#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) -#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) -#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) -#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) -#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) -#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) -#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) -#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) -#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) -#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) -#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) -#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) -#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) -#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) -#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) -#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) -#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) -#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) -#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) -#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) -/*! @} */ - -/*! @name INTR - Interrupt Register */ -/*! @{ */ -#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) -#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) -#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) -#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) -#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) -#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) -#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) -#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) -#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) -#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) -#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) -#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) -#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) -#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) -#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) -#define FLEXSPI_INTR_IPRXWA_MASK (0x20U) -#define FLEXSPI_INTR_IPRXWA_SHIFT (5U) -#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) -#define FLEXSPI_INTR_IPTXWE_MASK (0x40U) -#define FLEXSPI_INTR_IPTXWE_SHIFT (6U) -#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) -#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) -#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) -#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) -#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) -#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) -#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) -#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) -#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) -#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) -#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) -#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) -#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) -/*! @} */ - -/*! @name LUTKEY - LUT Key Register */ -/*! @{ */ -#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) -#define FLEXSPI_LUTKEY_KEY_SHIFT (0U) -#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) -/*! @} */ - -/*! @name LUTCR - LUT Control Register */ -/*! @{ */ -#define FLEXSPI_LUTCR_LOCK_MASK (0x1U) -#define FLEXSPI_LUTCR_LOCK_SHIFT (0U) -#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) -#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) -#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) -#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) -/*! @} */ - -/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 */ -/*! @{ */ -#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU) -#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) -#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) -#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) -#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) -#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) -#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U) -#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) -#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) -#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) -#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) -#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) -/*! @} */ - -/* The count of FLEXSPI_AHBRXBUFCR0 */ -#define FLEXSPI_AHBRXBUFCR0_COUNT (4U) - -/*! @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */ -/*! @{ */ -#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) -#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) -#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) -/*! @} */ - -/* The count of FLEXSPI_FLSHCR0 */ -#define FLEXSPI_FLSHCR0_COUNT (4U) - -/*! @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */ -/*! @{ */ -#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) -#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) -#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) -#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) -#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) -#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) -#define FLEXSPI_FLSHCR1_WA_MASK (0x400U) -#define FLEXSPI_FLSHCR1_WA_SHIFT (10U) -#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) -#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) -#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) -#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) -#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) -#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) -#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) -#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) -#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) -#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) -/*! @} */ - -/* The count of FLEXSPI_FLSHCR1 */ -#define FLEXSPI_FLSHCR1_COUNT (4U) - -/*! @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */ -/*! @{ */ -#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) -#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) -#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) -#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) -#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) -#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) -#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) -#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) -#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) -#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) -#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) -#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) -#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) -#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) -#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) -#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) -#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) -#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) -#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) -#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) -#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) -/*! @} */ - -/* The count of FLEXSPI_FLSHCR2 */ -#define FLEXSPI_FLSHCR2_COUNT (4U) - -/*! @name FLSHCR4 - Flash Control Register 4 */ -/*! @{ */ -#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) -#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) -#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) -#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) -#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) -#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) -#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) -#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) -#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) -/*! @} */ - -/*! @name IPCR0 - IP Control Register 0 */ -/*! @{ */ -#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) -#define FLEXSPI_IPCR0_SFAR_SHIFT (0U) -#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) -/*! @} */ - -/*! @name IPCR1 - IP Control Register 1 */ -/*! @{ */ -#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) -#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) -#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) -#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) -#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) -#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) -#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) -#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) -#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) -#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) -#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) -#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) -/*! @} */ - -/*! @name IPCMD - IP Command Register */ -/*! @{ */ -#define FLEXSPI_IPCMD_TRG_MASK (0x1U) -#define FLEXSPI_IPCMD_TRG_SHIFT (0U) -#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) -/*! @} */ - -/*! @name IPRXFCR - IP RX FIFO Control Register */ -/*! @{ */ -#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) -#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) -#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) -#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) -#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) -#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) -#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU) -#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) -#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) -/*! @} */ - -/*! @name IPTXFCR - IP TX FIFO Control Register */ -/*! @{ */ -#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) -#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) -#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) -#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) -#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) -#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) -#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU) -#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) -#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) -/*! @} */ - -/*! @name DLLCR - DLL Control Register 0 */ -/*! @{ */ -#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) -#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) -#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) -#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) -#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) -#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) -#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) -#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) -#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) -#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) -#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) -#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) -#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) -#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) -#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) -/*! @} */ - -/* The count of FLEXSPI_DLLCR */ -#define FLEXSPI_DLLCR_COUNT (2U) - -/*! @name STS0 - Status Register 0 */ -/*! @{ */ -#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) -#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) -#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) -#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) -#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) -#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) -#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) -#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) -#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) -/*! @} */ - -/*! @name STS1 - Status Register 1 */ -/*! @{ */ -#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) -#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) -#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) -#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) -#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) -#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) -#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) -#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) -#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) -#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) -#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) -#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) -/*! @} */ - -/*! @name STS2 - Status Register 2 */ -/*! @{ */ -#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) -#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) -#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) -#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) -#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) -#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) -#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) -#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) -#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) -#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) -#define FLEXSPI_STS2_AREFSEL_SHIFT (8U) -#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) -#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) -#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) -#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) -#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) -#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) -#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) -#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) -#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) -#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) -#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) -#define FLEXSPI_STS2_BREFSEL_SHIFT (24U) -#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) -/*! @} */ - -/*! @name AHBSPNDSTS - AHB Suspend Status Register */ -/*! @{ */ -#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) -#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) -#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) -#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) -#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) -#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) -#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) -#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) -#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) -/*! @} */ - -/*! @name IPRXFSTS - IP RX FIFO Status Register */ -/*! @{ */ -#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) -#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) -#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) -#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) -#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) -#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) -/*! @} */ - -/*! @name IPTXFSTS - IP TX FIFO Status Register */ -/*! @{ */ -#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) -#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) -#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) -#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) -#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) -#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) -/*! @} */ - -/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ -/*! @{ */ -#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) -#define FLEXSPI_RFDR_RXDATA_SHIFT (0U) -#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) -/*! @} */ - -/* The count of FLEXSPI_RFDR */ -#define FLEXSPI_RFDR_COUNT (32U) - -/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ -/*! @{ */ -#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) -#define FLEXSPI_TFDR_TXDATA_SHIFT (0U) -#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) -/*! @} */ - -/* The count of FLEXSPI_TFDR */ -#define FLEXSPI_TFDR_COUNT (32U) - -/*! @name LUT - LUT 0..LUT 63 */ -/*! @{ */ -#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) -#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) -#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) -#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) -#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) -#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) -#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) -#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) -#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) -#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) -#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) -#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) -#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) -#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) -#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) -#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) -#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) -#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) -/*! @} */ - -/* The count of FLEXSPI_LUT */ -#define FLEXSPI_LUT_COUNT (64U) - - -/*! - * @} - */ /* end of group FLEXSPI_Register_Masks */ - - -/* FLEXSPI - Peripheral instance base addresses */ -/** Peripheral FLEXSPI base address */ -#define FLEXSPI_BASE (0x402A8000u) -/** Peripheral FLEXSPI base pointer */ -#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) -/** Array initializer of FLEXSPI peripheral base addresses */ -#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } -/** Array initializer of FLEXSPI peripheral base pointers */ -#define FLEXSPI_BASE_PTRS { FLEXSPI } -/** Interrupt vectors for the FLEXSPI peripheral type */ -#define FLEXSPI_IRQS { FLEXSPI_IRQn } -/* FlexSPI AMBA address. */ -#define FlexSPI_AMBA_BASE (0x60000000U) -/* FlexSPI ASFM address. */ -#define FlexSPI_ASFM_BASE (0x00000000U) -/* Base Address of AHB address space mapped to IP RX FIFO. */ -#define FlexSPI_ARDF_BASE (0x7FC00000U) -/* Base Address of AHB address space mapped to IP TX FIFO. */ -#define FlexSPI_ATDF_BASE (0x7F800000U) - - -/*! - * @} - */ /* end of group FLEXSPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer - * @{ - */ - -/** GPC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */ - uint8_t RESERVED_0[4]; - __IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4 */ - __I uint32_t ISR[4]; /**< IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4 */ - uint8_t RESERVED_1[12]; - __IO uint32_t IMR5; /**< IRQ masking register 5, offset: 0x34 */ - __I uint32_t ISR5; /**< IRQ status resister 5, offset: 0x38 */ -} GPC_Type; - -/* ---------------------------------------------------------------------------- - -- GPC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPC_Register_Masks GPC Register Masks - * @{ - */ - -/*! @name CNTR - GPC Interface control register */ -/*! @{ */ -#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) -#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) -#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) -#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) -#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) -#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) -#define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U) -#define GPC_CNTR_PDRAM0_PGE_SHIFT (22U) -#define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK) -/*! @} */ - -/*! @name IMR - IRQ masking register 1..IRQ masking register 4 */ -/*! @{ */ -#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) -#define GPC_IMR_IMR1_SHIFT (0U) -#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) -#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU) -#define GPC_IMR_IMR2_SHIFT (0U) -#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK) -#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU) -#define GPC_IMR_IMR3_SHIFT (0U) -#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK) -#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) -#define GPC_IMR_IMR4_SHIFT (0U) -#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) -/*! @} */ - -/* The count of GPC_IMR */ -#define GPC_IMR_COUNT (4U) - -/*! @name ISR - IRQ status resister 1..IRQ status resister 4 */ -/*! @{ */ -#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) -#define GPC_ISR_ISR1_SHIFT (0U) -#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) -#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU) -#define GPC_ISR_ISR2_SHIFT (0U) -#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK) -#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU) -#define GPC_ISR_ISR3_SHIFT (0U) -#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK) -#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) -#define GPC_ISR_ISR4_SHIFT (0U) -#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) -/*! @} */ - -/* The count of GPC_ISR */ -#define GPC_ISR_COUNT (4U) - -/*! @name IMR5 - IRQ masking register 5 */ -/*! @{ */ -#define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU) -#define GPC_IMR5_IMR5_SHIFT (0U) -#define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK) -/*! @} */ - -/*! @name ISR5 - IRQ status resister 5 */ -/*! @{ */ -#define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU) -#define GPC_ISR5_ISR4_SHIFT (0U) -#define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group GPC_Register_Masks */ - - -/* GPC - Peripheral instance base addresses */ -/** Peripheral GPC base address */ -#define GPC_BASE (0x400F4000u) -/** Peripheral GPC base pointer */ -#define GPC ((GPC_Type *)GPC_BASE) -/** Array initializer of GPC peripheral base addresses */ -#define GPC_BASE_ADDRS { GPC_BASE } -/** Array initializer of GPC peripheral base pointers */ -#define GPC_BASE_PTRS { GPC } -/** Interrupt vectors for the GPC peripheral type */ -#define GPC_IRQS { GPC_IRQn } - -/*! - * @} - */ /* end of group GPC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ - __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ - __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ - __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ - __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ - __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ - __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ - __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ - uint8_t RESERVED_0[100]; - __O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */ - __O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */ - __O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name DR - GPIO data register */ -/*! @{ */ -#define GPIO_DR_DR_MASK (0xFFFFFFFFU) -#define GPIO_DR_DR_SHIFT (0U) -#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) -/*! @} */ - -/*! @name GDIR - GPIO direction register */ -/*! @{ */ -#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) -#define GPIO_GDIR_GDIR_SHIFT (0U) -#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) -/*! @} */ - -/*! @name PSR - GPIO pad status register */ -/*! @{ */ -#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) -#define GPIO_PSR_PSR_SHIFT (0U) -#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) -/*! @} */ - -/*! @name ICR1 - GPIO interrupt configuration register1 */ -/*! @{ */ -#define GPIO_ICR1_ICR0_MASK (0x3U) -#define GPIO_ICR1_ICR0_SHIFT (0U) -#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) -#define GPIO_ICR1_ICR1_MASK (0xCU) -#define GPIO_ICR1_ICR1_SHIFT (2U) -#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) -#define GPIO_ICR1_ICR2_MASK (0x30U) -#define GPIO_ICR1_ICR2_SHIFT (4U) -#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) -#define GPIO_ICR1_ICR3_MASK (0xC0U) -#define GPIO_ICR1_ICR3_SHIFT (6U) -#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) -#define GPIO_ICR1_ICR4_MASK (0x300U) -#define GPIO_ICR1_ICR4_SHIFT (8U) -#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) -#define GPIO_ICR1_ICR5_MASK (0xC00U) -#define GPIO_ICR1_ICR5_SHIFT (10U) -#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) -#define GPIO_ICR1_ICR6_MASK (0x3000U) -#define GPIO_ICR1_ICR6_SHIFT (12U) -#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) -#define GPIO_ICR1_ICR7_MASK (0xC000U) -#define GPIO_ICR1_ICR7_SHIFT (14U) -#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) -#define GPIO_ICR1_ICR8_MASK (0x30000U) -#define GPIO_ICR1_ICR8_SHIFT (16U) -#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) -#define GPIO_ICR1_ICR9_MASK (0xC0000U) -#define GPIO_ICR1_ICR9_SHIFT (18U) -#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) -#define GPIO_ICR1_ICR10_MASK (0x300000U) -#define GPIO_ICR1_ICR10_SHIFT (20U) -#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) -#define GPIO_ICR1_ICR11_MASK (0xC00000U) -#define GPIO_ICR1_ICR11_SHIFT (22U) -#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) -#define GPIO_ICR1_ICR12_MASK (0x3000000U) -#define GPIO_ICR1_ICR12_SHIFT (24U) -#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) -#define GPIO_ICR1_ICR13_MASK (0xC000000U) -#define GPIO_ICR1_ICR13_SHIFT (26U) -#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) -#define GPIO_ICR1_ICR14_MASK (0x30000000U) -#define GPIO_ICR1_ICR14_SHIFT (28U) -#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) -#define GPIO_ICR1_ICR15_MASK (0xC0000000U) -#define GPIO_ICR1_ICR15_SHIFT (30U) -#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) -/*! @} */ - -/*! @name ICR2 - GPIO interrupt configuration register2 */ -/*! @{ */ -#define GPIO_ICR2_ICR16_MASK (0x3U) -#define GPIO_ICR2_ICR16_SHIFT (0U) -#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) -#define GPIO_ICR2_ICR17_MASK (0xCU) -#define GPIO_ICR2_ICR17_SHIFT (2U) -#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) -#define GPIO_ICR2_ICR18_MASK (0x30U) -#define GPIO_ICR2_ICR18_SHIFT (4U) -#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) -#define GPIO_ICR2_ICR19_MASK (0xC0U) -#define GPIO_ICR2_ICR19_SHIFT (6U) -#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) -#define GPIO_ICR2_ICR20_MASK (0x300U) -#define GPIO_ICR2_ICR20_SHIFT (8U) -#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) -#define GPIO_ICR2_ICR21_MASK (0xC00U) -#define GPIO_ICR2_ICR21_SHIFT (10U) -#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) -#define GPIO_ICR2_ICR22_MASK (0x3000U) -#define GPIO_ICR2_ICR22_SHIFT (12U) -#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) -#define GPIO_ICR2_ICR23_MASK (0xC000U) -#define GPIO_ICR2_ICR23_SHIFT (14U) -#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) -#define GPIO_ICR2_ICR24_MASK (0x30000U) -#define GPIO_ICR2_ICR24_SHIFT (16U) -#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) -#define GPIO_ICR2_ICR25_MASK (0xC0000U) -#define GPIO_ICR2_ICR25_SHIFT (18U) -#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) -#define GPIO_ICR2_ICR26_MASK (0x300000U) -#define GPIO_ICR2_ICR26_SHIFT (20U) -#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) -#define GPIO_ICR2_ICR27_MASK (0xC00000U) -#define GPIO_ICR2_ICR27_SHIFT (22U) -#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) -#define GPIO_ICR2_ICR28_MASK (0x3000000U) -#define GPIO_ICR2_ICR28_SHIFT (24U) -#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) -#define GPIO_ICR2_ICR29_MASK (0xC000000U) -#define GPIO_ICR2_ICR29_SHIFT (26U) -#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) -#define GPIO_ICR2_ICR30_MASK (0x30000000U) -#define GPIO_ICR2_ICR30_SHIFT (28U) -#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) -#define GPIO_ICR2_ICR31_MASK (0xC0000000U) -#define GPIO_ICR2_ICR31_SHIFT (30U) -#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) -/*! @} */ - -/*! @name IMR - GPIO interrupt mask register */ -/*! @{ */ -#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) -#define GPIO_IMR_IMR_SHIFT (0U) -#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) -/*! @} */ - -/*! @name ISR - GPIO interrupt status register */ -/*! @{ */ -#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) -#define GPIO_ISR_ISR_SHIFT (0U) -#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) -/*! @} */ - -/*! @name EDGE_SEL - GPIO edge select register */ -/*! @{ */ -#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) -#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) -#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) -/*! @} */ - -/*! @name DR_SET - GPIO data register SET */ -/*! @{ */ -#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU) -#define GPIO_DR_SET_DR_SET_SHIFT (0U) -#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK) -/*! @} */ - -/*! @name DR_CLEAR - GPIO data register CLEAR */ -/*! @{ */ -#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU) -#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U) -#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK) -/*! @} */ - -/*! @name DR_TOGGLE - GPIO data register TOGGLE */ -/*! @{ */ -#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU) -#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U) -#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -/** Peripheral GPIO1 base address */ -#define GPIO1_BASE (0x401B8000u) -/** Peripheral GPIO1 base pointer */ -#define GPIO1 ((GPIO_Type *)GPIO1_BASE) -/** Peripheral GPIO2 base address */ -#define GPIO2_BASE (0x401BC000u) -/** Peripheral GPIO2 base pointer */ -#define GPIO2 ((GPIO_Type *)GPIO2_BASE) -/** Peripheral GPIO3 base address */ -#define GPIO3_BASE (0x401C0000u) -/** Peripheral GPIO3 base pointer */ -#define GPIO3 ((GPIO_Type *)GPIO3_BASE) -/** Peripheral GPIO4 base address */ -#define GPIO4_BASE (0x401C4000u) -/** Peripheral GPIO4 base pointer */ -#define GPIO4 ((GPIO_Type *)GPIO4_BASE) -/** Peripheral GPIO5 base address */ -#define GPIO5_BASE (0x400C0000u) -/** Peripheral GPIO5 base pointer */ -#define GPIO5 ((GPIO_Type *)GPIO5_BASE) -/** Array initializer of GPIO peripheral base addresses */ -#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } -/** Array initializer of GPIO peripheral base pointers */ -#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } -/** Interrupt vectors for the GPIO peripheral type */ -#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } -#define GPIO_COMBINED_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_16_31_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn } - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer - * @{ - */ - -/** GPT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ - __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ - __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ - __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ - __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ - __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ - __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ -} GPT_Type; - -/* ---------------------------------------------------------------------------- - -- GPT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPT_Register_Masks GPT Register Masks - * @{ - */ - -/*! @name CR - GPT Control Register */ -/*! @{ */ -#define GPT_CR_EN_MASK (0x1U) -#define GPT_CR_EN_SHIFT (0U) -#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) -#define GPT_CR_ENMOD_MASK (0x2U) -#define GPT_CR_ENMOD_SHIFT (1U) -#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) -#define GPT_CR_DBGEN_MASK (0x4U) -#define GPT_CR_DBGEN_SHIFT (2U) -#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) -#define GPT_CR_WAITEN_MASK (0x8U) -#define GPT_CR_WAITEN_SHIFT (3U) -#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) -#define GPT_CR_DOZEEN_MASK (0x10U) -#define GPT_CR_DOZEEN_SHIFT (4U) -#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) -#define GPT_CR_STOPEN_MASK (0x20U) -#define GPT_CR_STOPEN_SHIFT (5U) -#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) -#define GPT_CR_CLKSRC_MASK (0x1C0U) -#define GPT_CR_CLKSRC_SHIFT (6U) -#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) -#define GPT_CR_FRR_MASK (0x200U) -#define GPT_CR_FRR_SHIFT (9U) -#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) -#define GPT_CR_EN_24M_MASK (0x400U) -#define GPT_CR_EN_24M_SHIFT (10U) -#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) -#define GPT_CR_SWR_MASK (0x8000U) -#define GPT_CR_SWR_SHIFT (15U) -#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) -#define GPT_CR_IM1_MASK (0x30000U) -#define GPT_CR_IM1_SHIFT (16U) -#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) -#define GPT_CR_IM2_MASK (0xC0000U) -#define GPT_CR_IM2_SHIFT (18U) -#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) -#define GPT_CR_OM1_MASK (0x700000U) -#define GPT_CR_OM1_SHIFT (20U) -#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) -#define GPT_CR_OM2_MASK (0x3800000U) -#define GPT_CR_OM2_SHIFT (23U) -#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) -#define GPT_CR_OM3_MASK (0x1C000000U) -#define GPT_CR_OM3_SHIFT (26U) -#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) -#define GPT_CR_FO1_MASK (0x20000000U) -#define GPT_CR_FO1_SHIFT (29U) -#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) -#define GPT_CR_FO2_MASK (0x40000000U) -#define GPT_CR_FO2_SHIFT (30U) -#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) -#define GPT_CR_FO3_MASK (0x80000000U) -#define GPT_CR_FO3_SHIFT (31U) -#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) -/*! @} */ - -/*! @name PR - GPT Prescaler Register */ -/*! @{ */ -#define GPT_PR_PRESCALER_MASK (0xFFFU) -#define GPT_PR_PRESCALER_SHIFT (0U) -#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) -#define GPT_PR_PRESCALER24M_MASK (0xF000U) -#define GPT_PR_PRESCALER24M_SHIFT (12U) -#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) -/*! @} */ - -/*! @name SR - GPT Status Register */ -/*! @{ */ -#define GPT_SR_OF1_MASK (0x1U) -#define GPT_SR_OF1_SHIFT (0U) -#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) -#define GPT_SR_OF2_MASK (0x2U) -#define GPT_SR_OF2_SHIFT (1U) -#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) -#define GPT_SR_OF3_MASK (0x4U) -#define GPT_SR_OF3_SHIFT (2U) -#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) -#define GPT_SR_IF1_MASK (0x8U) -#define GPT_SR_IF1_SHIFT (3U) -#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) -#define GPT_SR_IF2_MASK (0x10U) -#define GPT_SR_IF2_SHIFT (4U) -#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) -#define GPT_SR_ROV_MASK (0x20U) -#define GPT_SR_ROV_SHIFT (5U) -#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) -/*! @} */ - -/*! @name IR - GPT Interrupt Register */ -/*! @{ */ -#define GPT_IR_OF1IE_MASK (0x1U) -#define GPT_IR_OF1IE_SHIFT (0U) -#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) -#define GPT_IR_OF2IE_MASK (0x2U) -#define GPT_IR_OF2IE_SHIFT (1U) -#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) -#define GPT_IR_OF3IE_MASK (0x4U) -#define GPT_IR_OF3IE_SHIFT (2U) -#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) -#define GPT_IR_IF1IE_MASK (0x8U) -#define GPT_IR_IF1IE_SHIFT (3U) -#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) -#define GPT_IR_IF2IE_MASK (0x10U) -#define GPT_IR_IF2IE_SHIFT (4U) -#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) -#define GPT_IR_ROVIE_MASK (0x20U) -#define GPT_IR_ROVIE_SHIFT (5U) -#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) -/*! @} */ - -/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ -/*! @{ */ -#define GPT_OCR_COMP_MASK (0xFFFFFFFFU) -#define GPT_OCR_COMP_SHIFT (0U) -#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) -/*! @} */ - -/* The count of GPT_OCR */ -#define GPT_OCR_COUNT (3U) - -/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ -/*! @{ */ -#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) -#define GPT_ICR_CAPT_SHIFT (0U) -#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) -/*! @} */ - -/* The count of GPT_ICR */ -#define GPT_ICR_COUNT (2U) - -/*! @name CNT - GPT Counter Register */ -/*! @{ */ -#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) -#define GPT_CNT_COUNT_SHIFT (0U) -#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group GPT_Register_Masks */ - - -/* GPT - Peripheral instance base addresses */ -/** Peripheral GPT1 base address */ -#define GPT1_BASE (0x401EC000u) -/** Peripheral GPT1 base pointer */ -#define GPT1 ((GPT_Type *)GPT1_BASE) -/** Peripheral GPT2 base address */ -#define GPT2_BASE (0x401F0000u) -/** Peripheral GPT2 base pointer */ -#define GPT2 ((GPT_Type *)GPT2_BASE) -/** Array initializer of GPT peripheral base addresses */ -#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE } -/** Array initializer of GPT peripheral base pointers */ -#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 } -/** Interrupt vectors for the GPT peripheral type */ -#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn } - -/*! - * @} - */ /* end of group GPT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ - __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ - __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ - __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ - __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ - __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ - __O uint32_t TDR[4]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_0[16]; - __I uint32_t TFR[4]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_1[16]; - __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ - uint8_t RESERVED_2[36]; - __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ - __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ - __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ - __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ - __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ - __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ - __I uint32_t RDR[4]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ - uint8_t RESERVED_3[16]; - __I uint32_t RFR[4]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_4[16]; - __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define I2S_VERID_FEATURE_MASK (0xFFFFU) -#define I2S_VERID_FEATURE_SHIFT (0U) -#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) -#define I2S_VERID_MINOR_MASK (0xFF0000U) -#define I2S_VERID_MINOR_SHIFT (16U) -#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) -#define I2S_VERID_MAJOR_MASK (0xFF000000U) -#define I2S_VERID_MAJOR_SHIFT (24U) -#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define I2S_PARAM_DATALINE_MASK (0xFU) -#define I2S_PARAM_DATALINE_SHIFT (0U) -#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) -#define I2S_PARAM_FIFO_MASK (0xF00U) -#define I2S_PARAM_FIFO_SHIFT (8U) -#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) -#define I2S_PARAM_FRAME_MASK (0xF0000U) -#define I2S_PARAM_FRAME_SHIFT (16U) -#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) -/*! @} */ - -/*! @name TCSR - SAI Transmit Control Register */ -/*! @{ */ -#define I2S_TCSR_FRDE_MASK (0x1U) -#define I2S_TCSR_FRDE_SHIFT (0U) -#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) -#define I2S_TCSR_FWDE_MASK (0x2U) -#define I2S_TCSR_FWDE_SHIFT (1U) -#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) -#define I2S_TCSR_FRIE_MASK (0x100U) -#define I2S_TCSR_FRIE_SHIFT (8U) -#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) -#define I2S_TCSR_FWIE_MASK (0x200U) -#define I2S_TCSR_FWIE_SHIFT (9U) -#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) -#define I2S_TCSR_FEIE_MASK (0x400U) -#define I2S_TCSR_FEIE_SHIFT (10U) -#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) -#define I2S_TCSR_SEIE_MASK (0x800U) -#define I2S_TCSR_SEIE_SHIFT (11U) -#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) -#define I2S_TCSR_WSIE_MASK (0x1000U) -#define I2S_TCSR_WSIE_SHIFT (12U) -#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) -#define I2S_TCSR_FRF_MASK (0x10000U) -#define I2S_TCSR_FRF_SHIFT (16U) -#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) -#define I2S_TCSR_FWF_MASK (0x20000U) -#define I2S_TCSR_FWF_SHIFT (17U) -#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) -#define I2S_TCSR_FEF_MASK (0x40000U) -#define I2S_TCSR_FEF_SHIFT (18U) -#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) -#define I2S_TCSR_SEF_MASK (0x80000U) -#define I2S_TCSR_SEF_SHIFT (19U) -#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) -#define I2S_TCSR_WSF_MASK (0x100000U) -#define I2S_TCSR_WSF_SHIFT (20U) -#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) -#define I2S_TCSR_SR_MASK (0x1000000U) -#define I2S_TCSR_SR_SHIFT (24U) -#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) -#define I2S_TCSR_FR_MASK (0x2000000U) -#define I2S_TCSR_FR_SHIFT (25U) -#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) -#define I2S_TCSR_BCE_MASK (0x10000000U) -#define I2S_TCSR_BCE_SHIFT (28U) -#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) -#define I2S_TCSR_DBGE_MASK (0x20000000U) -#define I2S_TCSR_DBGE_SHIFT (29U) -#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) -#define I2S_TCSR_STOPE_MASK (0x40000000U) -#define I2S_TCSR_STOPE_SHIFT (30U) -#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) -#define I2S_TCSR_TE_MASK (0x80000000U) -#define I2S_TCSR_TE_SHIFT (31U) -#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) -/*! @} */ - -/*! @name TCR1 - SAI Transmit Configuration 1 Register */ -/*! @{ */ -#define I2S_TCR1_TFW_MASK (0x1FU) -#define I2S_TCR1_TFW_SHIFT (0U) -#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) -/*! @} */ - -/*! @name TCR2 - SAI Transmit Configuration 2 Register */ -/*! @{ */ -#define I2S_TCR2_DIV_MASK (0xFFU) -#define I2S_TCR2_DIV_SHIFT (0U) -#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) -#define I2S_TCR2_BCD_MASK (0x1000000U) -#define I2S_TCR2_BCD_SHIFT (24U) -#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) -#define I2S_TCR2_BCP_MASK (0x2000000U) -#define I2S_TCR2_BCP_SHIFT (25U) -#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) -#define I2S_TCR2_MSEL_MASK (0xC000000U) -#define I2S_TCR2_MSEL_SHIFT (26U) -#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) -#define I2S_TCR2_BCI_MASK (0x10000000U) -#define I2S_TCR2_BCI_SHIFT (28U) -#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) -#define I2S_TCR2_BCS_MASK (0x20000000U) -#define I2S_TCR2_BCS_SHIFT (29U) -#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) -#define I2S_TCR2_SYNC_MASK (0xC0000000U) -#define I2S_TCR2_SYNC_SHIFT (30U) -#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) -/*! @} */ - -/*! @name TCR3 - SAI Transmit Configuration 3 Register */ -/*! @{ */ -#define I2S_TCR3_WDFL_MASK (0x1FU) -#define I2S_TCR3_WDFL_SHIFT (0U) -#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) -#define I2S_TCR3_TCE_MASK (0xF0000U) -#define I2S_TCR3_TCE_SHIFT (16U) -#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) -#define I2S_TCR3_CFR_MASK (0xF000000U) -#define I2S_TCR3_CFR_SHIFT (24U) -#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) -/*! @} */ - -/*! @name TCR4 - SAI Transmit Configuration 4 Register */ -/*! @{ */ -#define I2S_TCR4_FSD_MASK (0x1U) -#define I2S_TCR4_FSD_SHIFT (0U) -#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) -#define I2S_TCR4_FSP_MASK (0x2U) -#define I2S_TCR4_FSP_SHIFT (1U) -#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) -#define I2S_TCR4_ONDEM_MASK (0x4U) -#define I2S_TCR4_ONDEM_SHIFT (2U) -#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) -#define I2S_TCR4_FSE_MASK (0x8U) -#define I2S_TCR4_FSE_SHIFT (3U) -#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) -#define I2S_TCR4_MF_MASK (0x10U) -#define I2S_TCR4_MF_SHIFT (4U) -#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) -#define I2S_TCR4_CHMOD_MASK (0x20U) -#define I2S_TCR4_CHMOD_SHIFT (5U) -#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) -#define I2S_TCR4_SYWD_MASK (0x1F00U) -#define I2S_TCR4_SYWD_SHIFT (8U) -#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) -#define I2S_TCR4_FRSZ_MASK (0x1F0000U) -#define I2S_TCR4_FRSZ_SHIFT (16U) -#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) -#define I2S_TCR4_FPACK_MASK (0x3000000U) -#define I2S_TCR4_FPACK_SHIFT (24U) -#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) -#define I2S_TCR4_FCOMB_MASK (0xC000000U) -#define I2S_TCR4_FCOMB_SHIFT (26U) -#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) -#define I2S_TCR4_FCONT_MASK (0x10000000U) -#define I2S_TCR4_FCONT_SHIFT (28U) -#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) -/*! @} */ - -/*! @name TCR5 - SAI Transmit Configuration 5 Register */ -/*! @{ */ -#define I2S_TCR5_FBT_MASK (0x1F00U) -#define I2S_TCR5_FBT_SHIFT (8U) -#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) -#define I2S_TCR5_W0W_MASK (0x1F0000U) -#define I2S_TCR5_W0W_SHIFT (16U) -#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) -#define I2S_TCR5_WNW_MASK (0x1F000000U) -#define I2S_TCR5_WNW_SHIFT (24U) -#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) -/*! @} */ - -/*! @name TDR - SAI Transmit Data Register */ -/*! @{ */ -#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) -#define I2S_TDR_TDR_SHIFT (0U) -#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) -/*! @} */ - -/* The count of I2S_TDR */ -#define I2S_TDR_COUNT (4U) - -/*! @name TFR - SAI Transmit FIFO Register */ -/*! @{ */ -#define I2S_TFR_RFP_MASK (0x3FU) -#define I2S_TFR_RFP_SHIFT (0U) -#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) -#define I2S_TFR_WFP_MASK (0x3F0000U) -#define I2S_TFR_WFP_SHIFT (16U) -#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) -#define I2S_TFR_WCP_MASK (0x80000000U) -#define I2S_TFR_WCP_SHIFT (31U) -#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) -/*! @} */ - -/* The count of I2S_TFR */ -#define I2S_TFR_COUNT (4U) - -/*! @name TMR - SAI Transmit Mask Register */ -/*! @{ */ -#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) -#define I2S_TMR_TWM_SHIFT (0U) -#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) -/*! @} */ - -/*! @name RCSR - SAI Receive Control Register */ -/*! @{ */ -#define I2S_RCSR_FRDE_MASK (0x1U) -#define I2S_RCSR_FRDE_SHIFT (0U) -#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) -#define I2S_RCSR_FWDE_MASK (0x2U) -#define I2S_RCSR_FWDE_SHIFT (1U) -#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) -#define I2S_RCSR_FRIE_MASK (0x100U) -#define I2S_RCSR_FRIE_SHIFT (8U) -#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) -#define I2S_RCSR_FWIE_MASK (0x200U) -#define I2S_RCSR_FWIE_SHIFT (9U) -#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) -#define I2S_RCSR_FEIE_MASK (0x400U) -#define I2S_RCSR_FEIE_SHIFT (10U) -#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) -#define I2S_RCSR_SEIE_MASK (0x800U) -#define I2S_RCSR_SEIE_SHIFT (11U) -#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) -#define I2S_RCSR_WSIE_MASK (0x1000U) -#define I2S_RCSR_WSIE_SHIFT (12U) -#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) -#define I2S_RCSR_FRF_MASK (0x10000U) -#define I2S_RCSR_FRF_SHIFT (16U) -#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) -#define I2S_RCSR_FWF_MASK (0x20000U) -#define I2S_RCSR_FWF_SHIFT (17U) -#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) -#define I2S_RCSR_FEF_MASK (0x40000U) -#define I2S_RCSR_FEF_SHIFT (18U) -#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) -#define I2S_RCSR_SEF_MASK (0x80000U) -#define I2S_RCSR_SEF_SHIFT (19U) -#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) -#define I2S_RCSR_WSF_MASK (0x100000U) -#define I2S_RCSR_WSF_SHIFT (20U) -#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) -#define I2S_RCSR_SR_MASK (0x1000000U) -#define I2S_RCSR_SR_SHIFT (24U) -#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) -#define I2S_RCSR_FR_MASK (0x2000000U) -#define I2S_RCSR_FR_SHIFT (25U) -#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) -#define I2S_RCSR_BCE_MASK (0x10000000U) -#define I2S_RCSR_BCE_SHIFT (28U) -#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) -#define I2S_RCSR_DBGE_MASK (0x20000000U) -#define I2S_RCSR_DBGE_SHIFT (29U) -#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) -#define I2S_RCSR_STOPE_MASK (0x40000000U) -#define I2S_RCSR_STOPE_SHIFT (30U) -#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) -#define I2S_RCSR_RE_MASK (0x80000000U) -#define I2S_RCSR_RE_SHIFT (31U) -#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) -/*! @} */ - -/*! @name RCR1 - SAI Receive Configuration 1 Register */ -/*! @{ */ -#define I2S_RCR1_RFW_MASK (0x1FU) -#define I2S_RCR1_RFW_SHIFT (0U) -#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) -/*! @} */ - -/*! @name RCR2 - SAI Receive Configuration 2 Register */ -/*! @{ */ -#define I2S_RCR2_DIV_MASK (0xFFU) -#define I2S_RCR2_DIV_SHIFT (0U) -#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) -#define I2S_RCR2_BCD_MASK (0x1000000U) -#define I2S_RCR2_BCD_SHIFT (24U) -#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) -#define I2S_RCR2_BCP_MASK (0x2000000U) -#define I2S_RCR2_BCP_SHIFT (25U) -#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) -#define I2S_RCR2_MSEL_MASK (0xC000000U) -#define I2S_RCR2_MSEL_SHIFT (26U) -#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) -#define I2S_RCR2_BCI_MASK (0x10000000U) -#define I2S_RCR2_BCI_SHIFT (28U) -#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) -#define I2S_RCR2_BCS_MASK (0x20000000U) -#define I2S_RCR2_BCS_SHIFT (29U) -#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) -#define I2S_RCR2_SYNC_MASK (0xC0000000U) -#define I2S_RCR2_SYNC_SHIFT (30U) -#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) -/*! @} */ - -/*! @name RCR3 - SAI Receive Configuration 3 Register */ -/*! @{ */ -#define I2S_RCR3_WDFL_MASK (0x1FU) -#define I2S_RCR3_WDFL_SHIFT (0U) -#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) -#define I2S_RCR3_RCE_MASK (0xF0000U) -#define I2S_RCR3_RCE_SHIFT (16U) -#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) -#define I2S_RCR3_CFR_MASK (0xF000000U) -#define I2S_RCR3_CFR_SHIFT (24U) -#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) -/*! @} */ - -/*! @name RCR4 - SAI Receive Configuration 4 Register */ -/*! @{ */ -#define I2S_RCR4_FSD_MASK (0x1U) -#define I2S_RCR4_FSD_SHIFT (0U) -#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) -#define I2S_RCR4_FSP_MASK (0x2U) -#define I2S_RCR4_FSP_SHIFT (1U) -#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) -#define I2S_RCR4_ONDEM_MASK (0x4U) -#define I2S_RCR4_ONDEM_SHIFT (2U) -#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) -#define I2S_RCR4_FSE_MASK (0x8U) -#define I2S_RCR4_FSE_SHIFT (3U) -#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) -#define I2S_RCR4_MF_MASK (0x10U) -#define I2S_RCR4_MF_SHIFT (4U) -#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) -#define I2S_RCR4_SYWD_MASK (0x1F00U) -#define I2S_RCR4_SYWD_SHIFT (8U) -#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) -#define I2S_RCR4_FRSZ_MASK (0x1F0000U) -#define I2S_RCR4_FRSZ_SHIFT (16U) -#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) -#define I2S_RCR4_FPACK_MASK (0x3000000U) -#define I2S_RCR4_FPACK_SHIFT (24U) -#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) -#define I2S_RCR4_FCOMB_MASK (0xC000000U) -#define I2S_RCR4_FCOMB_SHIFT (26U) -#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) -#define I2S_RCR4_FCONT_MASK (0x10000000U) -#define I2S_RCR4_FCONT_SHIFT (28U) -#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) -/*! @} */ - -/*! @name RCR5 - SAI Receive Configuration 5 Register */ -/*! @{ */ -#define I2S_RCR5_FBT_MASK (0x1F00U) -#define I2S_RCR5_FBT_SHIFT (8U) -#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) -#define I2S_RCR5_W0W_MASK (0x1F0000U) -#define I2S_RCR5_W0W_SHIFT (16U) -#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) -#define I2S_RCR5_WNW_MASK (0x1F000000U) -#define I2S_RCR5_WNW_SHIFT (24U) -#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) -/*! @} */ - -/*! @name RDR - SAI Receive Data Register */ -/*! @{ */ -#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) -#define I2S_RDR_RDR_SHIFT (0U) -#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) -/*! @} */ - -/* The count of I2S_RDR */ -#define I2S_RDR_COUNT (4U) - -/*! @name RFR - SAI Receive FIFO Register */ -/*! @{ */ -#define I2S_RFR_RFP_MASK (0x3FU) -#define I2S_RFR_RFP_SHIFT (0U) -#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) -#define I2S_RFR_RCP_MASK (0x8000U) -#define I2S_RFR_RCP_SHIFT (15U) -#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) -#define I2S_RFR_WFP_MASK (0x3F0000U) -#define I2S_RFR_WFP_SHIFT (16U) -#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) -/*! @} */ - -/* The count of I2S_RFR */ -#define I2S_RFR_COUNT (4U) - -/*! @name RMR - SAI Receive Mask Register */ -/*! @{ */ -#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) -#define I2S_RMR_RWM_SHIFT (0U) -#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -/** Peripheral SAI1 base address */ -#define SAI1_BASE (0x40384000u) -/** Peripheral SAI1 base pointer */ -#define SAI1 ((I2S_Type *)SAI1_BASE) -/** Peripheral SAI2 base address */ -#define SAI2_BASE (0x40388000u) -/** Peripheral SAI2 base pointer */ -#define SAI2 ((I2S_Type *)SAI2_BASE) -/** Peripheral SAI3 base address */ -#define SAI3_BASE (0x4038C000u) -/** Peripheral SAI3 base pointer */ -#define SAI3 ((I2S_Type *)SAI3_BASE) -/** Array initializer of I2S peripheral base addresses */ -#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE } -/** Array initializer of I2S peripheral base pointers */ -#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 } -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn } -#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOMUXC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer - * @{ - */ - -/** IOMUXC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[20]; - __IO uint32_t SW_MUX_CTL_PAD[124]; /**< SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x14, array step: 0x4 */ - __IO uint32_t SW_PAD_CTL_PAD[124]; /**< SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x204, array step: 0x4 */ - __IO uint32_t SELECT_INPUT[154]; /**< ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register, array offset: 0x3F4, array step: 0x4 */ -} IOMUXC_Type; - -/* ---------------------------------------------------------------------------- - -- IOMUXC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks - * @{ - */ - -/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register */ -/*! @{ */ -#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) -#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) -#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) -#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) -#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) -#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) -/*! @} */ - -/* The count of IOMUXC_SW_MUX_CTL_PAD */ -#define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U) - -/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register */ -/*! @{ */ -#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) -#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) -#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) -#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U) -#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U) -#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) -#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) -#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) -#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) -#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U) -#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U) -#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) -#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) -#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U) -#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK) -#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) -#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U) -#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) -#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) -#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U) -#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) -#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) -#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U) -#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) -/*! @} */ - -/* The count of IOMUXC_SW_PAD_CTL_PAD */ -#define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U) - -/*! @name SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register */ -/*! @{ */ -#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ -#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) -#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ -/*! @} */ - -/* The count of IOMUXC_SELECT_INPUT */ -#define IOMUXC_SELECT_INPUT_COUNT (154U) - - -/*! - * @} - */ /* end of group IOMUXC_Register_Masks */ - - -/* IOMUXC - Peripheral instance base addresses */ -/** Peripheral IOMUXC base address */ -#define IOMUXC_BASE (0x401F8000u) -/** Peripheral IOMUXC base pointer */ -#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) -/** Array initializer of IOMUXC peripheral base addresses */ -#define IOMUXC_BASE_ADDRS { IOMUXC_BASE } -/** Array initializer of IOMUXC peripheral base pointers */ -#define IOMUXC_BASE_PTRS { IOMUXC } - -/*! - * @} - */ /* end of group IOMUXC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOMUXC_GPR Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer - * @{ - */ - -/** IOMUXC_GPR - Register Layout Typedef */ -typedef struct { - uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ - __IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ - __IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ - __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ - __IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */ - __IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */ - __IO uint32_t GPR6; /**< GPR6 General Purpose Register, offset: 0x18 */ - __IO uint32_t GPR7; /**< GPR7 General Purpose Register, offset: 0x1C */ - __IO uint32_t GPR8; /**< GPR8 General Purpose Register, offset: 0x20 */ - uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */ - __IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */ - __IO uint32_t GPR11; /**< GPR11 General Purpose Register, offset: 0x2C */ - __IO uint32_t GPR12; /**< GPR12 General Purpose Register, offset: 0x30 */ - __IO uint32_t GPR13; /**< GPR13 General Purpose Register, offset: 0x34 */ - __IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */ - uint32_t GPR15; /**< GPR15 General Purpose Register, offset: 0x3C */ - __IO uint32_t GPR16; /**< GPR16 General Purpose Register, offset: 0x40 */ - __IO uint32_t GPR17; /**< GPR17 General Purpose Register, offset: 0x44 */ - __IO uint32_t GPR18; /**< GPR18 General Purpose Register, offset: 0x48 */ - __IO uint32_t GPR19; /**< GPR19 General Purpose Register, offset: 0x4C */ - __IO uint32_t GPR20; /**< GPR20 General Purpose Register, offset: 0x50 */ - __IO uint32_t GPR21; /**< GPR21 General Purpose Register, offset: 0x54 */ - __IO uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */ - __IO uint32_t GPR23; /**< GPR23 General Purpose Register, offset: 0x5C */ - __IO uint32_t GPR24; /**< GPR24 General Purpose Register, offset: 0x60 */ - __IO uint32_t GPR25; /**< GPR25 General Purpose Register, offset: 0x64 */ -} IOMUXC_GPR_Type; - -/* ---------------------------------------------------------------------------- - -- IOMUXC_GPR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks - * @{ - */ - -/*! @name GPR1 - GPR1 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U) -#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U) -#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK) -#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U) -#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U) -#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK) -#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U) -#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U) -#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK) -#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U) -#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U) -#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK) -#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U) -#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U) -#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK) -#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U) -#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U) -#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK) -#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U) -#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U) -#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK) -#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U) -#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U) -#define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK) -#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U) -#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U) -#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) -#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U) -#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U) -#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK) -#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U) -#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U) -#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) -#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U) -#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U) -#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK) -#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U) -#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U) -#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK) -#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U) -#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U) -#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK) -#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U) -#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U) -#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK) -/*! @} */ - -/*! @name GPR2 - GPR2 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U) -#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U) -#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK) -#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U) -#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U) -#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK) -#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U) -#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U) -#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK) -#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U) -#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U) -#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK) -#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U) -#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U) -#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK) -#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U) -#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U) -#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK) -#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U) -#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U) -#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK) -#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U) -#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U) -#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK) -#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U) -#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U) -#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK) -#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U) -#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U) -#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK) -/*! @} */ - -/*! @name GPR3 - GPR3 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU) -#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U) -#define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK) -#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U) -#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U) -#define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK) -#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U) -#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U) -#define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK) -/*! @} */ - -/*! @name GPR4 - GPR4 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U) -#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U) -#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U) -#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U) -#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U) -#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U) -#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U) -#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U) -#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U) -#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U) -#define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U) -#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U) -#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U) -#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U) -#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U) -#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U) -#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U) -#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U) -#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U) -#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U) -#define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U) -#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U) -#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U) -#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U) -#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U) -#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U) -#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U) -#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U) -#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U) -#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U) -#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U) -#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U) -#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U) -#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U) -#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U) -#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U) -#define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U) -#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U) -#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U) -#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U) -#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U) -#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U) -#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U) -#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U) -#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U) -#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U) -#define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U) -#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U) -#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U) -#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U) -#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U) -#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U) -#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK) -/*! @} */ - -/*! @name GPR5 - GPR5 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U) -#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U) -#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK) -#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U) -#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U) -#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK) -#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U) -#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U) -#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK) -#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U) -#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U) -#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK) -#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U) -#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U) -#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK) -#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U) -#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U) -#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK) -/*! @} */ - -/*! @name GPR6 - GPR6 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U) -#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U) -#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U) -#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U) -#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U) -#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U) -#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U) -#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U) -#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U) -#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U) -#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U) -#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U) -#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U) -#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U) -#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U) -#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U) -#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U) -#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U) -#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U) -#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U) -#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U) -#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U) -#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U) -#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U) -#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U) -#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U) -#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U) -#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U) -#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U) -#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U) -#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U) -#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U) -#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U) -#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK) -/*! @} */ - -/*! @name GPR7 - GPR7 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U) -#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U) -#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U) -#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U) -#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U) -#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U) -#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U) -#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U) -#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U) -#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U) -#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U) -#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U) -#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U) -#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U) -#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U) -#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U) -#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U) -#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U) -#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U) -#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U) -#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U) -#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U) -#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U) -#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U) -#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U) -#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U) -#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U) -#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U) -#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U) -#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U) -#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U) -#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U) -#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK) -#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U) -#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U) -#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U) -#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U) -#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U) -#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U) -#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U) -#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U) -#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U) -#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U) -#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U) -#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U) -#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U) -#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U) -#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U) -#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U) -#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U) -#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U) -#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U) -#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U) -#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U) -#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U) -#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U) -#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U) -#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U) -#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U) -#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U) -#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U) -#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U) -#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U) -#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK) -#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U) -#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U) -#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK) -/*! @} */ - -/*! @name GPR8 - GPR8 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U) -#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U) -#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U) -#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U) -#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U) -#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U) -#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U) -#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U) -#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U) -#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U) -#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U) -#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U) -#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U) -#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U) -#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U) -#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U) -#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U) -#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U) -#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U) -#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U) -#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U) -#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U) -#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U) -#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U) -#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U) -#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U) -#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U) -#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U) -#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U) -#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U) -#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U) -#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U) -#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U) -#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U) -#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U) -#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U) -#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U) -#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U) -#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U) -#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U) -#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U) -#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U) -#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U) -#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U) -#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U) -#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U) -#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U) -#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U) -#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U) -#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U) -#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U) -#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U) -#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U) -#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U) -#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U) -#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U) -#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U) -#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U) -#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U) -#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U) -#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U) -#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U) -#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U) -#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U) -#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK) -/*! @} */ - -/*! @name GPR10 - GPR10 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U) -#define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U) -#define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK) -#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U) -#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U) -#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK) -#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U) -#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U) -#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK) -#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U) -#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U) -#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK) -#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U) -#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U) -#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK) -#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U) -#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U) -#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK) -#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U) -#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U) -#define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK) -#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U) -#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U) -#define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK) -#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U) -#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U) -#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK) -#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U) -#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U) -#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK) -#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U) -#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U) -#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK) -#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U) -#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U) -#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK) -/*! @} */ - -/*! @name GPR11 - GPR11 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U) -#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U) -#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK) -#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU) -#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U) -#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK) -#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U) -#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U) -#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK) -#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U) -#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U) -#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK) -#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U) -#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U) -#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK) -#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U) -#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U) -#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK) -#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U) -#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U) -#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK) -#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U) -#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U) -#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK) -#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U) -#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U) -#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK) -#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U) -#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U) -#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK) -/*! @} */ - -/*! @name GPR12 - GPR12 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U) -#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U) -#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U) -#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U) -#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U) -#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U) -#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK) -#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U) -#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U) -#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK) -#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U) -#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U) -#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK) -/*! @} */ - -/*! @name GPR13 - GPR13 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U) -#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U) -#define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK) -#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U) -#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U) -#define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK) -#define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U) -#define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U) -#define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK) -#define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U) -#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U) -#define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK) -/*! @} */ - -/*! @name GPR14 - GPR14 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U) -#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U) -#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK) -#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U) -#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U) -#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK) -#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U) -#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U) -#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK) -#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U) -#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U) -#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK) -#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U) -#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U) -#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK) -#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U) -#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U) -#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK) -#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U) -#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U) -#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK) -#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U) -#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U) -#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK) -#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U) -#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U) -#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK) -#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U) -#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U) -#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK) -#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U) -#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U) -#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK) -#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U) -#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U) -#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK) -#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U) -#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U) -#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK) -#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U) -#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U) -#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK) -/*! @} */ - -/*! @name GPR16 - GPR16 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U) -#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U) -#define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK) -#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U) -#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U) -#define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK) -#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U) -#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U) -#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U) -#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK) -/*! @} */ - -/*! @name GPR17 - GPR17 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU) -#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U) -#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK) -/*! @} */ - -/*! @name GPR18 - GPR18 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U) -#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U) -#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK) -#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U) -#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U) -#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK) -/*! @} */ - -/*! @name GPR19 - GPR19 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U) -#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U) -#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK) -#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U) -#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U) -#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK) -/*! @} */ - -/*! @name GPR20 - GPR20 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U) -#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U) -#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK) -#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U) -#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U) -#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK) -/*! @} */ - -/*! @name GPR21 - GPR21 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) -#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) -#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK) -#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U) -#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U) -#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK) -/*! @} */ - -/*! @name GPR22 - GPR22 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U) -#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U) -#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK) -#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) -#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U) -#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK) -/*! @} */ - -/*! @name GPR23 - GPR23 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) -#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) -#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK) -#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U) -#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U) -#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK) -/*! @} */ - -/*! @name GPR24 - GPR24 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U) -#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U) -#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK) -#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) -#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT (3U) -#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK) -/*! @} */ - -/*! @name GPR25 - GPR25 General Purpose Register */ -/*! @{ */ -#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U) -#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U) -#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK) -#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U) -#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U) -#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group IOMUXC_GPR_Register_Masks */ - - -/* IOMUXC_GPR - Peripheral instance base addresses */ -/** Peripheral IOMUXC_GPR base address */ -#define IOMUXC_GPR_BASE (0x400AC000u) -/** Peripheral IOMUXC_GPR base pointer */ -#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) -/** Array initializer of IOMUXC_GPR peripheral base addresses */ -#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } -/** Array initializer of IOMUXC_GPR peripheral base pointers */ -#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } - -/*! - * @} - */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOMUXC_SNVS Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer - * @{ - */ - -/** IOMUXC_SNVS - Register Layout Typedef */ -typedef struct { - __IO uint32_t SW_MUX_CTL_PAD_WAKEUP; /**< SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register, offset: 0x0 */ - __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ; /**< SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x4 */ - __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ; /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x8 */ - __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0xC */ - __IO uint32_t SW_PAD_CTL_PAD_POR_B; /**< SW_PAD_CTL_PAD_POR_B SW PAD Control Register, offset: 0x10 */ - __IO uint32_t SW_PAD_CTL_PAD_ONOFF; /**< SW_PAD_CTL_PAD_ONOFF SW PAD Control Register, offset: 0x14 */ - __IO uint32_t SW_PAD_CTL_PAD_WAKEUP; /**< SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register, offset: 0x18 */ - __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ; /**< SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register, offset: 0x1C */ - __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ; /**< SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register, offset: 0x20 */ -} IOMUXC_SNVS_Type; - -/* ---------------------------------------------------------------------------- - -- IOMUXC_SNVS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks - * @{ - */ - -/*! @name SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ -/*! @{ */ -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK) -/*! @} */ - -/*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ -/*! @{ */ -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK) -/*! @} */ - -/*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ -/*! @{ */ -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U) -#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK) -/*! @} */ - -/*! @name SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ -/*! @{ */ -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK) -/*! @} */ - -/*! @name SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ -/*! @{ */ -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK) -/*! @} */ - -/*! @name SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ -/*! @{ */ -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK) -/*! @} */ - -/*! @name SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ -/*! @{ */ -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK) -/*! @} */ - -/*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ -/*! @{ */ -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK) -/*! @} */ - -/*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ -/*! @{ */ -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U) -#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group IOMUXC_SNVS_Register_Masks */ - - -/* IOMUXC_SNVS - Peripheral instance base addresses */ -/** Peripheral IOMUXC_SNVS base address */ -#define IOMUXC_SNVS_BASE (0x400A8000u) -/** Peripheral IOMUXC_SNVS base pointer */ -#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE) -/** Array initializer of IOMUXC_SNVS peripheral base addresses */ -#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE } -/** Array initializer of IOMUXC_SNVS peripheral base pointers */ -#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS } - -/*! - * @} - */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOMUXC_SNVS_GPR Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer - * @{ - */ - -/** IOMUXC_SNVS_GPR - Register Layout Typedef */ -typedef struct { - uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ - uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ - uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ - __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ -} IOMUXC_SNVS_GPR_Type; - -/* ---------------------------------------------------------------------------- - -- IOMUXC_SNVS_GPR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks - * @{ - */ - -/*! @name GPR3 - GPR3 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U) -#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U) -#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK) -#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU) -#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U) -#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U) -#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group IOMUXC_SNVS_GPR_Register_Masks */ - - -/* IOMUXC_SNVS_GPR - Peripheral instance base addresses */ -/** Peripheral IOMUXC_SNVS_GPR base address */ -#define IOMUXC_SNVS_GPR_BASE (0x400A4000u) -/** Peripheral IOMUXC_SNVS_GPR base pointer */ -#define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE) -/** Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */ -#define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE } -/** Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */ -#define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR } - -/*! - * @} - */ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- KPP Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer - * @{ - */ - -/** KPP - Register Layout Typedef */ -typedef struct { - __IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */ - __IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */ - __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ - __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ -} KPP_Type; - -/* ---------------------------------------------------------------------------- - -- KPP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup KPP_Register_Masks KPP Register Masks - * @{ - */ - -/*! @name KPCR - Keypad Control Register */ -/*! @{ */ -#define KPP_KPCR_KRE_MASK (0xFFU) -#define KPP_KPCR_KRE_SHIFT (0U) -#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) -#define KPP_KPCR_KCO_MASK (0xFF00U) -#define KPP_KPCR_KCO_SHIFT (8U) -#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) -/*! @} */ - -/*! @name KPSR - Keypad Status Register */ -/*! @{ */ -#define KPP_KPSR_KPKD_MASK (0x1U) -#define KPP_KPSR_KPKD_SHIFT (0U) -#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) -#define KPP_KPSR_KPKR_MASK (0x2U) -#define KPP_KPSR_KPKR_SHIFT (1U) -#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) -#define KPP_KPSR_KDSC_MASK (0x4U) -#define KPP_KPSR_KDSC_SHIFT (2U) -#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) -#define KPP_KPSR_KRSS_MASK (0x8U) -#define KPP_KPSR_KRSS_SHIFT (3U) -#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) -#define KPP_KPSR_KDIE_MASK (0x100U) -#define KPP_KPSR_KDIE_SHIFT (8U) -#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) -#define KPP_KPSR_KRIE_MASK (0x200U) -#define KPP_KPSR_KRIE_SHIFT (9U) -#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) -/*! @} */ - -/*! @name KDDR - Keypad Data Direction Register */ -/*! @{ */ -#define KPP_KDDR_KRDD_MASK (0xFFU) -#define KPP_KDDR_KRDD_SHIFT (0U) -#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) -#define KPP_KDDR_KCDD_MASK (0xFF00U) -#define KPP_KDDR_KCDD_SHIFT (8U) -#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) -/*! @} */ - -/*! @name KPDR - Keypad Data Register */ -/*! @{ */ -#define KPP_KPDR_KRD_MASK (0xFFU) -#define KPP_KPDR_KRD_SHIFT (0U) -#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) -#define KPP_KPDR_KCD_MASK (0xFF00U) -#define KPP_KPDR_KCD_SHIFT (8U) -#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group KPP_Register_Masks */ - - -/* KPP - Peripheral instance base addresses */ -/** Peripheral KPP base address */ -#define KPP_BASE (0x401FC000u) -/** Peripheral KPP base pointer */ -#define KPP ((KPP_Type *)KPP_BASE) -/** Array initializer of KPP peripheral base addresses */ -#define KPP_BASE_ADDRS { KPP_BASE } -/** Array initializer of KPP peripheral base pointers */ -#define KPP_BASE_PTRS { KPP } -/** Interrupt vectors for the KPP peripheral type */ -#define KPP_IRQS { KPP_IRQn } - -/*! - * @} - */ /* end of group KPP_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LCDIF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer - * @{ - */ - -/** LCDIF - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */ - __IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */ - __IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */ - __IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */ - __IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */ - __IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */ - __IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */ - __IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */ - __IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */ - __IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */ - __IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */ - __IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */ - __IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ - uint8_t RESERVED_1[12]; - __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ - uint8_t RESERVED_2[28]; - __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ - __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ - __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ - __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ - __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ - uint8_t RESERVED_3[12]; - __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ - uint8_t RESERVED_4[12]; - __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ - uint8_t RESERVED_5[12]; - __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ - uint8_t RESERVED_6[220]; - __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ - uint8_t RESERVED_7[12]; - __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ - uint8_t RESERVED_8[12]; - __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ - uint8_t RESERVED_9[76]; - __IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */ - uint8_t RESERVED_10[380]; - __IO uint32_t PIGEONCTRL0; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */ - __IO uint32_t PIGEONCTRL0_SET; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */ - __IO uint32_t PIGEONCTRL0_CLR; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */ - __IO uint32_t PIGEONCTRL0_TOG; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x38C */ - __IO uint32_t PIGEONCTRL1; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x390 */ - __IO uint32_t PIGEONCTRL1_SET; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x394 */ - __IO uint32_t PIGEONCTRL1_CLR; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x398 */ - __IO uint32_t PIGEONCTRL1_TOG; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x39C */ - __IO uint32_t PIGEONCTRL2; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A0 */ - __IO uint32_t PIGEONCTRL2_SET; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */ - __IO uint32_t PIGEONCTRL2_CLR; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */ - __IO uint32_t PIGEONCTRL2_TOG; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */ - uint8_t RESERVED_11[1104]; - struct { /* offset: 0x800, array step: 0x40 */ - __IO uint32_t PIGEON_0; /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */ - uint8_t RESERVED_0[12]; - __IO uint32_t PIGEON_1; /**< Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40 */ - uint8_t RESERVED_1[12]; - __IO uint32_t PIGEON_2; /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */ - uint8_t RESERVED_2[28]; - } PIGEON[12]; - __IO uint32_t LUT_CTRL; /**< Lookup Table Data Register., offset: 0xB00 */ - uint8_t RESERVED_12[12]; - __IO uint32_t LUT0_ADDR; /**< Lookup Table Control Register., offset: 0xB10 */ - uint8_t RESERVED_13[12]; - __IO uint32_t LUT0_DATA; /**< Lookup Table Data Register., offset: 0xB20 */ - uint8_t RESERVED_14[12]; - __IO uint32_t LUT1_ADDR; /**< Lookup Table Control Register., offset: 0xB30 */ - uint8_t RESERVED_15[12]; - __IO uint32_t LUT1_DATA; /**< Lookup Table Data Register., offset: 0xB40 */ -} LCDIF_Type; - -/* ---------------------------------------------------------------------------- - -- LCDIF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LCDIF_Register_Masks LCDIF Register Masks - * @{ - */ - -/*! @name CTRL - LCDIF General Control Register */ -/*! @{ */ -#define LCDIF_CTRL_RUN_MASK (0x1U) -#define LCDIF_CTRL_RUN_SHIFT (0U) -#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) -#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) -#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) -#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) -#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) -#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) -#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) -#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) -#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) -#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) -#define LCDIF_CTRL_RSRVD0_MASK (0x10U) -#define LCDIF_CTRL_RSRVD0_SHIFT (4U) -#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) -#define LCDIF_CTRL_MASTER_MASK (0x20U) -#define LCDIF_CTRL_MASTER_SHIFT (5U) -#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) -#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) -#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) -#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) -#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) -#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) -#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) -#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) -#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) -#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) -#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) -#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) -#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) -#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) -#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) -#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) -#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) -#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) -#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) -#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) -#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) -#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) -#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) -#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) -#define LCDIF_CTRL_CLKGATE_SHIFT (30U) -#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) -#define LCDIF_CTRL_SFTRST_MASK (0x80000000U) -#define LCDIF_CTRL_SFTRST_SHIFT (31U) -#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_SET - LCDIF General Control Register */ -/*! @{ */ -#define LCDIF_CTRL_SET_RUN_MASK (0x1U) -#define LCDIF_CTRL_SET_RUN_SHIFT (0U) -#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) -#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) -#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) -#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) -#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) -#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) -#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) -#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) -#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) -#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) -#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) -#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) -#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) -#define LCDIF_CTRL_SET_MASTER_MASK (0x20U) -#define LCDIF_CTRL_SET_MASTER_SHIFT (5U) -#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) -#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) -#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) -#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) -#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) -#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) -#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) -#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) -#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) -#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) -#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) -#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) -#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) -#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) -#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) -#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) -#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) -#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) -#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) -#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) -#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) -#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) -#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) -#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) -#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) -#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) -#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) -#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) -#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) -#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) -#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) -#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_CLR - LCDIF General Control Register */ -/*! @{ */ -#define LCDIF_CTRL_CLR_RUN_MASK (0x1U) -#define LCDIF_CTRL_CLR_RUN_SHIFT (0U) -#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) -#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) -#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) -#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) -#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) -#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) -#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) -#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) -#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) -#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) -#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) -#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) -#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) -#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) -#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) -#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) -#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) -#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) -#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) -#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) -#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) -#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) -#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) -#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) -#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) -#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) -#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) -#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) -#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) -#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) -#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) -#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) -#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) -#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) -#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) -#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) -#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) -#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) -#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) -#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) -#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) -#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) -#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) -#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) -#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) -#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) -#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_TOG - LCDIF General Control Register */ -/*! @{ */ -#define LCDIF_CTRL_TOG_RUN_MASK (0x1U) -#define LCDIF_CTRL_TOG_RUN_SHIFT (0U) -#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) -#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) -#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) -#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) -#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) -#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) -#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) -#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) -#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) -#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) -#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) -#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) -#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) -#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) -#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) -#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) -#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) -#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) -#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) -#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) -#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) -#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) -#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) -#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) -#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) -#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) -#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) -#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) -#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) -#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) -#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) -#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) -#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) -#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) -#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) -#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) -#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) -#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) -#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) -#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) -#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) -#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) -#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) -#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) -#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) -#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) -#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) -#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL1 - LCDIF General Control1 Register */ -/*! @{ */ -#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) -#define LCDIF_CTRL1_RSRVD0_SHIFT (3U) -#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) -#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) -#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) -#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) -#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) -#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) -#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) -#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) -#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) -#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) -#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) -#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) -#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) -#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) -#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) -#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) -#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) -#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) -#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) -#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) -#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) -#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) -#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) -#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) -#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) -#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) -#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) -#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) -#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) -#define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U) -#define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U) -#define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK) -#define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U) -#define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U) -#define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK) -/*! @} */ - -/*! @name CTRL1_SET - LCDIF General Control1 Register */ -/*! @{ */ -#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) -#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) -#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) -#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) -#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) -#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) -#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) -#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) -#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) -#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) -#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) -#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) -#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) -#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) -#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) -#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) -#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) -#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) -#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) -#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) -#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) -#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) -#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) -#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) -#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) -#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) -#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) -#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) -#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) -#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) -#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) -#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) -#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) -#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) -#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) -#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) -#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) -#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) -#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) -#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) -#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) -#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) -#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) -#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) -#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) -#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) -#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) -#define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U) -#define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U) -#define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK) -#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U) -#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U) -#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK) -/*! @} */ - -/*! @name CTRL1_CLR - LCDIF General Control1 Register */ -/*! @{ */ -#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) -#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) -#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) -#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) -#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) -#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) -#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) -#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) -#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) -#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) -#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) -#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) -#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) -#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) -#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) -#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) -#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) -#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) -#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) -#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) -#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) -#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) -#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) -#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) -#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) -#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) -#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) -#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) -#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) -#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) -#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) -#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) -#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) -#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) -#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) -#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) -#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) -#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) -#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) -#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) -#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) -#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) -#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) -#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) -#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) -#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) -#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) -#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U) -#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U) -#define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK) -#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U) -#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U) -#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK) -/*! @} */ - -/*! @name CTRL1_TOG - LCDIF General Control1 Register */ -/*! @{ */ -#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) -#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) -#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) -#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) -#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) -#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) -#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) -#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) -#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) -#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) -#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) -#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) -#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) -#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) -#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) -#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) -#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) -#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) -#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) -#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) -#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) -#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) -#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) -#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) -#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) -#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) -#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) -#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) -#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) -#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) -#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) -#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) -#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) -#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) -#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) -#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) -#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) -#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) -#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) -#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) -#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) -#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) -#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) -#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) -#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) -#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) -#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) -#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) -#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) -#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U) -#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U) -#define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK) -#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U) -#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U) -#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK) -/*! @} */ - -/*! @name CTRL2 - LCDIF General Control2 Register */ -/*! @{ */ -#define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU) -#define LCDIF_CTRL2_RSRVD0_SHIFT (0U) -#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) -#define LCDIF_CTRL2_RSRVD3_SHIFT (15U) -#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) -#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) -#define LCDIF_CTRL2_RSRVD4_SHIFT (19U) -#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) -#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) -#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) -#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) -#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) -#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) -#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) -#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) -#define LCDIF_CTRL2_RSRVD5_SHIFT (24U) -#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) -/*! @} */ - -/*! @name CTRL2_SET - LCDIF General Control2 Register */ -/*! @{ */ -#define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU) -#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) -#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) -#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) -#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) -#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) -#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) -#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) -#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) -#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) -#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) -#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) -#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) -#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) -#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) -#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) -#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) -#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) -#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) -#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) -#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) -#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) -/*! @} */ - -/*! @name CTRL2_CLR - LCDIF General Control2 Register */ -/*! @{ */ -#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU) -#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) -#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) -#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) -#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) -#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) -#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) -#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) -#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) -#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) -#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) -#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) -#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) -#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) -#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) -#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) -#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) -#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) -#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) -#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) -#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) -#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) -/*! @} */ - -/*! @name CTRL2_TOG - LCDIF General Control2 Register */ -/*! @{ */ -#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU) -#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) -#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) -#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) -#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) -#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) -#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) -#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) -#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) -#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) -#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) -#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) -#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) -#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) -#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) -#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) -#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) -#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) -#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) -#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) -#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) -#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) -#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) -/*! @} */ - -/*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ -/*! @{ */ -#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) -#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) -#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) -#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) -#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) -#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) -/*! @} */ - -/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ -/*! @{ */ -#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) -#define LCDIF_CUR_BUF_ADDR_SHIFT (0U) -#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) -/*! @} */ - -/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ -/*! @{ */ -#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) -#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) -#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) -/*! @} */ - -/*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ -/*! @{ */ -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) -#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) -#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) -#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) -#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) -#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) -#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) -#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) -#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) -#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) -#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) -#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) -#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) -#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) -#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) -#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) -#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) -#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) -#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) -#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) -#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) -#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) -#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) -#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) -#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) -#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) -#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) -#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) -#define LCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U) -#define LCDIF_VDCTRL0_RSRVD2_SHIFT (29U) -#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) -/*! @} */ - -/*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ -/*! @{ */ -#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) -#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) -#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) -#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) -#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) -#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) -#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) -#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) -#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) -#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) -#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) -#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) -#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) -#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) -#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) -#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) -#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) -#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) -#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) -#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) -#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) -#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) -#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) -#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) -#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) -#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) -#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) -#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) -#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) -#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) -#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) -#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) -#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) -#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U) -#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U) -#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) -/*! @} */ - -/*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ -/*! @{ */ -#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) -#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) -#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) -#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) -#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) -#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) -#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) -#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) -#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) -#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) -#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) -#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) -#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) -#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) -#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) -#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) -#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) -#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) -#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) -#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) -#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) -#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) -#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) -#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) -#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) -#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) -#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) -#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) -#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) -#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) -#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) -#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) -#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) -#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U) -#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U) -#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) -/*! @} */ - -/*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ -/*! @{ */ -#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) -#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) -#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) -#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) -#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) -#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) -#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) -#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) -#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) -#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) -#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) -#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) -#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) -#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) -#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) -#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) -#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) -#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) -#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) -#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) -#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) -#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) -#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) -#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) -#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) -#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) -#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) -#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) -#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) -#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) -#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) -#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) -#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) -#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U) -#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U) -#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) -/*! @} */ - -/*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ -/*! @{ */ -#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) -#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) -#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) -/*! @} */ - -/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ -/*! @{ */ -#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) -#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) -#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) -/*! @} */ - -/*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ -/*! @{ */ -#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) -#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) -#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) -#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) -#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) -#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) -#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) -#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) -#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) -#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) -#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) -#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) -#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) -#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) -#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) -/*! @} */ - -/*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ -/*! @{ */ -#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) -#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) -#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) -#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) -#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) -#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) -#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) -#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) -#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) -#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) -#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) -#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) -/*! @} */ - -/*! @name BM_ERROR_STAT - Bus Master Error Status Register */ -/*! @{ */ -#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) -#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) -#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) -/*! @} */ - -/*! @name CRC_STAT - CRC Status Register */ -/*! @{ */ -#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) -#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) -#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) -/*! @} */ - -/*! @name STAT - LCD Interface Status Register */ -/*! @{ */ -#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) -#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) -#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) -#define LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U) -#define LCDIF_STAT_RSRVD0_SHIFT (9U) -#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) -#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) -#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) -#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) -#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) -#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) -#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) -#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) -#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) -#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) -#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) -#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) -#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) -#define LCDIF_STAT_DMA_REQ_MASK (0x40000000U) -#define LCDIF_STAT_DMA_REQ_SHIFT (30U) -#define LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK) -#define LCDIF_STAT_PRESENT_MASK (0x80000000U) -#define LCDIF_STAT_PRESENT_SHIFT (31U) -#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) -/*! @} */ - -/*! @name THRES - LCDIF Threshold Register */ -/*! @{ */ -#define LCDIF_THRES_PANIC_MASK (0x1FFU) -#define LCDIF_THRES_PANIC_SHIFT (0U) -#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) -#define LCDIF_THRES_RSRVD1_MASK (0xFE00U) -#define LCDIF_THRES_RSRVD1_SHIFT (9U) -#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) -#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) -#define LCDIF_THRES_FASTCLOCK_SHIFT (16U) -#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) -#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) -#define LCDIF_THRES_RSRVD2_SHIFT (25U) -#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) -/*! @} */ - -/*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */ -/*! @{ */ -#define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU) -#define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK) -#define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U) -#define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U) -#define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK) -/*! @} */ - -/*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */ -/*! @{ */ -#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU) -#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK) -#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U) -#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U) -#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK) -/*! @} */ - -/*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */ -/*! @{ */ -#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU) -#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK) -#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U) -#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U) -#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK) -/*! @} */ - -/*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */ -/*! @{ */ -#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU) -#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK) -#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U) -#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U) -#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK) -/*! @} */ - -/*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */ -/*! @{ */ -#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU) -#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK) -#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U) -#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U) -#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK) -/*! @} */ - -/*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */ -/*! @{ */ -#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU) -#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK) -#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U) -#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U) -#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK) -/*! @} */ - -/*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */ -/*! @{ */ -#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU) -#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK) -#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U) -#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U) -#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK) -/*! @} */ - -/*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */ -/*! @{ */ -#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU) -#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U) -#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK) -#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U) -#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U) -#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK) -/*! @} */ - -/*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */ -/*! @{ */ -#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U) -#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U) -#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK) -#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U) -#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U) -#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK) -/*! @} */ - -/*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */ -/*! @{ */ -#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U) -#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U) -#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK) -#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U) -#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U) -#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK) -/*! @} */ - -/*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */ -/*! @{ */ -#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U) -#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U) -#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK) -#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U) -#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U) -#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK) -/*! @} */ - -/*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */ -/*! @{ */ -#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U) -#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U) -#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK) -#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U) -#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U) -#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK) -/*! @} */ - -/*! @name PIGEON_0 - Panel Interface Signal Generator Register */ -/*! @{ */ -#define LCDIF_PIGEON_0_EN_MASK (0x1U) -#define LCDIF_PIGEON_0_EN_SHIFT (0U) -#define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK) -#define LCDIF_PIGEON_0_POL_MASK (0x2U) -#define LCDIF_PIGEON_0_POL_SHIFT (1U) -#define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK) -#define LCDIF_PIGEON_0_INC_SEL_MASK (0xCU) -#define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U) -#define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK) -#define LCDIF_PIGEON_0_OFFSET_MASK (0xF0U) -#define LCDIF_PIGEON_0_OFFSET_SHIFT (4U) -#define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK) -#define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U) -#define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U) -#define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK) -#define LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U) -#define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U) -#define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK) -#define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U) -#define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U) -#define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK) -/*! @} */ - -/* The count of LCDIF_PIGEON_0 */ -#define LCDIF_PIGEON_0_COUNT (12U) - -/*! @name PIGEON_1 - Panel Interface Signal Generator Register */ -/*! @{ */ -#define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU) -#define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U) -#define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK) -#define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U) -#define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U) -#define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK) -/*! @} */ - -/* The count of LCDIF_PIGEON_1 */ -#define LCDIF_PIGEON_1_COUNT (12U) - -/*! @name PIGEON_2 - Panel Interface Signal Generator Register */ -/*! @{ */ -#define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU) -#define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U) -#define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK) -#define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U) -#define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U) -#define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK) -#define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U) -#define LCDIF_PIGEON_2_RSVD_SHIFT (9U) -#define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK) -/*! @} */ - -/* The count of LCDIF_PIGEON_2 */ -#define LCDIF_PIGEON_2_COUNT (12U) - -/*! @name LUT_CTRL - Lookup Table Data Register. */ -/*! @{ */ -#define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U) -#define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U) -#define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK) -/*! @} */ - -/*! @name LUT0_ADDR - Lookup Table Control Register. */ -/*! @{ */ -#define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU) -#define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U) -#define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK) -/*! @} */ - -/*! @name LUT0_DATA - Lookup Table Data Register. */ -/*! @{ */ -#define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU) -#define LCDIF_LUT0_DATA_DATA_SHIFT (0U) -#define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK) -/*! @} */ - -/*! @name LUT1_ADDR - Lookup Table Control Register. */ -/*! @{ */ -#define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU) -#define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U) -#define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK) -/*! @} */ - -/*! @name LUT1_DATA - Lookup Table Data Register. */ -/*! @{ */ -#define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU) -#define LCDIF_LUT1_DATA_DATA_SHIFT (0U) -#define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LCDIF_Register_Masks */ - - -/* LCDIF - Peripheral instance base addresses */ -/** Peripheral LCDIF base address */ -#define LCDIF_BASE (0x402B8000u) -/** Peripheral LCDIF base pointer */ -#define LCDIF ((LCDIF_Type *)LCDIF_BASE) -/** Array initializer of LCDIF peripheral base addresses */ -#define LCDIF_BASE_ADDRS { LCDIF_BASE } -/** Array initializer of LCDIF peripheral base pointers */ -#define LCDIF_BASE_PTRS { LCDIF } -/** Interrupt vectors for the LCDIF peripheral type */ -#define LCDIF_IRQ0_IRQS { LCDIF_IRQn } - -/*! - * @} - */ /* end of group LCDIF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPI2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer - * @{ - */ - -/** LPI2C - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ - __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ - __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ - __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ - __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ - __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ - __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ - uint8_t RESERVED_1[16]; - __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ - uint8_t RESERVED_2[4]; - __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ - uint8_t RESERVED_3[4]; - __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ - uint8_t RESERVED_4[4]; - __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ - __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ - __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ - uint8_t RESERVED_5[12]; - __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ - uint8_t RESERVED_6[156]; - __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ - __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ - __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ - __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ - uint8_t RESERVED_7[4]; - __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ - __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ - uint8_t RESERVED_8[20]; - __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ - uint8_t RESERVED_9[12]; - __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ - __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ - uint8_t RESERVED_10[8]; - __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ - uint8_t RESERVED_11[12]; - __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ -} LPI2C_Type; - -/* ---------------------------------------------------------------------------- - -- LPI2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPI2C_Register_Masks LPI2C Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) -#define LPI2C_VERID_FEATURE_SHIFT (0U) -#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) -#define LPI2C_VERID_MINOR_MASK (0xFF0000U) -#define LPI2C_VERID_MINOR_SHIFT (16U) -#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) -#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) -#define LPI2C_VERID_MAJOR_SHIFT (24U) -#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) -#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) -#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) -#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) -#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) -#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) -/*! @} */ - -/*! @name MCR - Master Control Register */ -/*! @{ */ -#define LPI2C_MCR_MEN_MASK (0x1U) -#define LPI2C_MCR_MEN_SHIFT (0U) -#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) -#define LPI2C_MCR_RST_MASK (0x2U) -#define LPI2C_MCR_RST_SHIFT (1U) -#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) -#define LPI2C_MCR_DOZEN_MASK (0x4U) -#define LPI2C_MCR_DOZEN_SHIFT (2U) -#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) -#define LPI2C_MCR_DBGEN_MASK (0x8U) -#define LPI2C_MCR_DBGEN_SHIFT (3U) -#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) -#define LPI2C_MCR_RTF_MASK (0x100U) -#define LPI2C_MCR_RTF_SHIFT (8U) -#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) -#define LPI2C_MCR_RRF_MASK (0x200U) -#define LPI2C_MCR_RRF_SHIFT (9U) -#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) -/*! @} */ - -/*! @name MSR - Master Status Register */ -/*! @{ */ -#define LPI2C_MSR_TDF_MASK (0x1U) -#define LPI2C_MSR_TDF_SHIFT (0U) -#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) -#define LPI2C_MSR_RDF_MASK (0x2U) -#define LPI2C_MSR_RDF_SHIFT (1U) -#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) -#define LPI2C_MSR_EPF_MASK (0x100U) -#define LPI2C_MSR_EPF_SHIFT (8U) -#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) -#define LPI2C_MSR_SDF_MASK (0x200U) -#define LPI2C_MSR_SDF_SHIFT (9U) -#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) -#define LPI2C_MSR_NDF_MASK (0x400U) -#define LPI2C_MSR_NDF_SHIFT (10U) -#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) -#define LPI2C_MSR_ALF_MASK (0x800U) -#define LPI2C_MSR_ALF_SHIFT (11U) -#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) -#define LPI2C_MSR_FEF_MASK (0x1000U) -#define LPI2C_MSR_FEF_SHIFT (12U) -#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) -#define LPI2C_MSR_PLTF_MASK (0x2000U) -#define LPI2C_MSR_PLTF_SHIFT (13U) -#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) -#define LPI2C_MSR_DMF_MASK (0x4000U) -#define LPI2C_MSR_DMF_SHIFT (14U) -#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) -#define LPI2C_MSR_MBF_MASK (0x1000000U) -#define LPI2C_MSR_MBF_SHIFT (24U) -#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) -#define LPI2C_MSR_BBF_MASK (0x2000000U) -#define LPI2C_MSR_BBF_SHIFT (25U) -#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) -/*! @} */ - -/*! @name MIER - Master Interrupt Enable Register */ -/*! @{ */ -#define LPI2C_MIER_TDIE_MASK (0x1U) -#define LPI2C_MIER_TDIE_SHIFT (0U) -#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) -#define LPI2C_MIER_RDIE_MASK (0x2U) -#define LPI2C_MIER_RDIE_SHIFT (1U) -#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) -#define LPI2C_MIER_EPIE_MASK (0x100U) -#define LPI2C_MIER_EPIE_SHIFT (8U) -#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) -#define LPI2C_MIER_SDIE_MASK (0x200U) -#define LPI2C_MIER_SDIE_SHIFT (9U) -#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) -#define LPI2C_MIER_NDIE_MASK (0x400U) -#define LPI2C_MIER_NDIE_SHIFT (10U) -#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) -#define LPI2C_MIER_ALIE_MASK (0x800U) -#define LPI2C_MIER_ALIE_SHIFT (11U) -#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) -#define LPI2C_MIER_FEIE_MASK (0x1000U) -#define LPI2C_MIER_FEIE_SHIFT (12U) -#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) -#define LPI2C_MIER_PLTIE_MASK (0x2000U) -#define LPI2C_MIER_PLTIE_SHIFT (13U) -#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) -#define LPI2C_MIER_DMIE_MASK (0x4000U) -#define LPI2C_MIER_DMIE_SHIFT (14U) -#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) -/*! @} */ - -/*! @name MDER - Master DMA Enable Register */ -/*! @{ */ -#define LPI2C_MDER_TDDE_MASK (0x1U) -#define LPI2C_MDER_TDDE_SHIFT (0U) -#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) -#define LPI2C_MDER_RDDE_MASK (0x2U) -#define LPI2C_MDER_RDDE_SHIFT (1U) -#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) -/*! @} */ - -/*! @name MCFGR0 - Master Configuration Register 0 */ -/*! @{ */ -#define LPI2C_MCFGR0_HREN_MASK (0x1U) -#define LPI2C_MCFGR0_HREN_SHIFT (0U) -#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) -#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) -#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) -#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) -#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) -#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) -#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) -#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) -#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) -#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) -#define LPI2C_MCFGR0_RDMO_MASK (0x200U) -#define LPI2C_MCFGR0_RDMO_SHIFT (9U) -#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) -/*! @} */ - -/*! @name MCFGR1 - Master Configuration Register 1 */ -/*! @{ */ -#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) -#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) -#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) -#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) -#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) -#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) -#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) -#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) -#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) -#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) -#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) -#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) -#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) -#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) -#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) -#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) -#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) -#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) -/*! @} */ - -/*! @name MCFGR2 - Master Configuration Register 2 */ -/*! @{ */ -#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) -#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) -#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) -#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) -#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) -#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) -#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) -#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) -#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) -/*! @} */ - -/*! @name MCFGR3 - Master Configuration Register 3 */ -/*! @{ */ -#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) -#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) -#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) -/*! @} */ - -/*! @name MDMR - Master Data Match Register */ -/*! @{ */ -#define LPI2C_MDMR_MATCH0_MASK (0xFFU) -#define LPI2C_MDMR_MATCH0_SHIFT (0U) -#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) -#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) -#define LPI2C_MDMR_MATCH1_SHIFT (16U) -#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) -/*! @} */ - -/*! @name MCCR0 - Master Clock Configuration Register 0 */ -/*! @{ */ -#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) -#define LPI2C_MCCR0_CLKLO_SHIFT (0U) -#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) -#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) -#define LPI2C_MCCR0_CLKHI_SHIFT (8U) -#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) -#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) -#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) -#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) -#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) -#define LPI2C_MCCR0_DATAVD_SHIFT (24U) -#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) -/*! @} */ - -/*! @name MCCR1 - Master Clock Configuration Register 1 */ -/*! @{ */ -#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) -#define LPI2C_MCCR1_CLKLO_SHIFT (0U) -#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) -#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) -#define LPI2C_MCCR1_CLKHI_SHIFT (8U) -#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) -#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) -#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) -#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) -#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) -#define LPI2C_MCCR1_DATAVD_SHIFT (24U) -#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) -/*! @} */ - -/*! @name MFCR - Master FIFO Control Register */ -/*! @{ */ -#define LPI2C_MFCR_TXWATER_MASK (0x3U) -#define LPI2C_MFCR_TXWATER_SHIFT (0U) -#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) -#define LPI2C_MFCR_RXWATER_MASK (0x30000U) -#define LPI2C_MFCR_RXWATER_SHIFT (16U) -#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) -/*! @} */ - -/*! @name MFSR - Master FIFO Status Register */ -/*! @{ */ -#define LPI2C_MFSR_TXCOUNT_MASK (0x7U) -#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) -#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) -#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) -#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) -#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) -/*! @} */ - -/*! @name MTDR - Master Transmit Data Register */ -/*! @{ */ -#define LPI2C_MTDR_DATA_MASK (0xFFU) -#define LPI2C_MTDR_DATA_SHIFT (0U) -#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) -#define LPI2C_MTDR_CMD_MASK (0x700U) -#define LPI2C_MTDR_CMD_SHIFT (8U) -#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) -/*! @} */ - -/*! @name MRDR - Master Receive Data Register */ -/*! @{ */ -#define LPI2C_MRDR_DATA_MASK (0xFFU) -#define LPI2C_MRDR_DATA_SHIFT (0U) -#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) -#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) -#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) -#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) -/*! @} */ - -/*! @name SCR - Slave Control Register */ -/*! @{ */ -#define LPI2C_SCR_SEN_MASK (0x1U) -#define LPI2C_SCR_SEN_SHIFT (0U) -#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) -#define LPI2C_SCR_RST_MASK (0x2U) -#define LPI2C_SCR_RST_SHIFT (1U) -#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) -#define LPI2C_SCR_FILTEN_MASK (0x10U) -#define LPI2C_SCR_FILTEN_SHIFT (4U) -#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) -#define LPI2C_SCR_FILTDZ_MASK (0x20U) -#define LPI2C_SCR_FILTDZ_SHIFT (5U) -#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) -#define LPI2C_SCR_RTF_MASK (0x100U) -#define LPI2C_SCR_RTF_SHIFT (8U) -#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) -#define LPI2C_SCR_RRF_MASK (0x200U) -#define LPI2C_SCR_RRF_SHIFT (9U) -#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) -/*! @} */ - -/*! @name SSR - Slave Status Register */ -/*! @{ */ -#define LPI2C_SSR_TDF_MASK (0x1U) -#define LPI2C_SSR_TDF_SHIFT (0U) -#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) -#define LPI2C_SSR_RDF_MASK (0x2U) -#define LPI2C_SSR_RDF_SHIFT (1U) -#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) -#define LPI2C_SSR_AVF_MASK (0x4U) -#define LPI2C_SSR_AVF_SHIFT (2U) -#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) -#define LPI2C_SSR_TAF_MASK (0x8U) -#define LPI2C_SSR_TAF_SHIFT (3U) -#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) -#define LPI2C_SSR_RSF_MASK (0x100U) -#define LPI2C_SSR_RSF_SHIFT (8U) -#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) -#define LPI2C_SSR_SDF_MASK (0x200U) -#define LPI2C_SSR_SDF_SHIFT (9U) -#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) -#define LPI2C_SSR_BEF_MASK (0x400U) -#define LPI2C_SSR_BEF_SHIFT (10U) -#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) -#define LPI2C_SSR_FEF_MASK (0x800U) -#define LPI2C_SSR_FEF_SHIFT (11U) -#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) -#define LPI2C_SSR_AM0F_MASK (0x1000U) -#define LPI2C_SSR_AM0F_SHIFT (12U) -#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) -#define LPI2C_SSR_AM1F_MASK (0x2000U) -#define LPI2C_SSR_AM1F_SHIFT (13U) -#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) -#define LPI2C_SSR_GCF_MASK (0x4000U) -#define LPI2C_SSR_GCF_SHIFT (14U) -#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) -#define LPI2C_SSR_SARF_MASK (0x8000U) -#define LPI2C_SSR_SARF_SHIFT (15U) -#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) -#define LPI2C_SSR_SBF_MASK (0x1000000U) -#define LPI2C_SSR_SBF_SHIFT (24U) -#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) -#define LPI2C_SSR_BBF_MASK (0x2000000U) -#define LPI2C_SSR_BBF_SHIFT (25U) -#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) -/*! @} */ - -/*! @name SIER - Slave Interrupt Enable Register */ -/*! @{ */ -#define LPI2C_SIER_TDIE_MASK (0x1U) -#define LPI2C_SIER_TDIE_SHIFT (0U) -#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) -#define LPI2C_SIER_RDIE_MASK (0x2U) -#define LPI2C_SIER_RDIE_SHIFT (1U) -#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) -#define LPI2C_SIER_AVIE_MASK (0x4U) -#define LPI2C_SIER_AVIE_SHIFT (2U) -#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) -#define LPI2C_SIER_TAIE_MASK (0x8U) -#define LPI2C_SIER_TAIE_SHIFT (3U) -#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) -#define LPI2C_SIER_RSIE_MASK (0x100U) -#define LPI2C_SIER_RSIE_SHIFT (8U) -#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) -#define LPI2C_SIER_SDIE_MASK (0x200U) -#define LPI2C_SIER_SDIE_SHIFT (9U) -#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) -#define LPI2C_SIER_BEIE_MASK (0x400U) -#define LPI2C_SIER_BEIE_SHIFT (10U) -#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) -#define LPI2C_SIER_FEIE_MASK (0x800U) -#define LPI2C_SIER_FEIE_SHIFT (11U) -#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) -#define LPI2C_SIER_AM0IE_MASK (0x1000U) -#define LPI2C_SIER_AM0IE_SHIFT (12U) -#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) -#define LPI2C_SIER_AM1F_MASK (0x2000U) -#define LPI2C_SIER_AM1F_SHIFT (13U) -#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) -#define LPI2C_SIER_GCIE_MASK (0x4000U) -#define LPI2C_SIER_GCIE_SHIFT (14U) -#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) -#define LPI2C_SIER_SARIE_MASK (0x8000U) -#define LPI2C_SIER_SARIE_SHIFT (15U) -#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) -/*! @} */ - -/*! @name SDER - Slave DMA Enable Register */ -/*! @{ */ -#define LPI2C_SDER_TDDE_MASK (0x1U) -#define LPI2C_SDER_TDDE_SHIFT (0U) -#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) -#define LPI2C_SDER_RDDE_MASK (0x2U) -#define LPI2C_SDER_RDDE_SHIFT (1U) -#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) -#define LPI2C_SDER_AVDE_MASK (0x4U) -#define LPI2C_SDER_AVDE_SHIFT (2U) -#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) -/*! @} */ - -/*! @name SCFGR1 - Slave Configuration Register 1 */ -/*! @{ */ -#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) -#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) -#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) -#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) -#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) -#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) -#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) -#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) -#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) -#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) -#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) -#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) -#define LPI2C_SCFGR1_GCEN_MASK (0x100U) -#define LPI2C_SCFGR1_GCEN_SHIFT (8U) -#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) -#define LPI2C_SCFGR1_SAEN_MASK (0x200U) -#define LPI2C_SCFGR1_SAEN_SHIFT (9U) -#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) -#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) -#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) -#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) -#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) -#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) -#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) -#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) -#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) -#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) -#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) -#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) -#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) -#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) -#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) -#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) -/*! @} */ - -/*! @name SCFGR2 - Slave Configuration Register 2 */ -/*! @{ */ -#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) -#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) -#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) -#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) -#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) -#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) -#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) -#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) -#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) -#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) -#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) -#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) -/*! @} */ - -/*! @name SAMR - Slave Address Match Register */ -/*! @{ */ -#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) -#define LPI2C_SAMR_ADDR0_SHIFT (1U) -#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) -#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) -#define LPI2C_SAMR_ADDR1_SHIFT (17U) -#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) -/*! @} */ - -/*! @name SASR - Slave Address Status Register */ -/*! @{ */ -#define LPI2C_SASR_RADDR_MASK (0x7FFU) -#define LPI2C_SASR_RADDR_SHIFT (0U) -#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) -#define LPI2C_SASR_ANV_MASK (0x4000U) -#define LPI2C_SASR_ANV_SHIFT (14U) -#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) -/*! @} */ - -/*! @name STAR - Slave Transmit ACK Register */ -/*! @{ */ -#define LPI2C_STAR_TXNACK_MASK (0x1U) -#define LPI2C_STAR_TXNACK_SHIFT (0U) -#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) -/*! @} */ - -/*! @name STDR - Slave Transmit Data Register */ -/*! @{ */ -#define LPI2C_STDR_DATA_MASK (0xFFU) -#define LPI2C_STDR_DATA_SHIFT (0U) -#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) -/*! @} */ - -/*! @name SRDR - Slave Receive Data Register */ -/*! @{ */ -#define LPI2C_SRDR_DATA_MASK (0xFFU) -#define LPI2C_SRDR_DATA_SHIFT (0U) -#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) -#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) -#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) -#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) -#define LPI2C_SRDR_SOF_MASK (0x8000U) -#define LPI2C_SRDR_SOF_SHIFT (15U) -#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPI2C_Register_Masks */ - - -/* LPI2C - Peripheral instance base addresses */ -/** Peripheral LPI2C1 base address */ -#define LPI2C1_BASE (0x403F0000u) -/** Peripheral LPI2C1 base pointer */ -#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) -/** Peripheral LPI2C2 base address */ -#define LPI2C2_BASE (0x403F4000u) -/** Peripheral LPI2C2 base pointer */ -#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) -/** Peripheral LPI2C3 base address */ -#define LPI2C3_BASE (0x403F8000u) -/** Peripheral LPI2C3 base pointer */ -#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) -/** Peripheral LPI2C4 base address */ -#define LPI2C4_BASE (0x403FC000u) -/** Peripheral LPI2C4 base pointer */ -#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) -/** Array initializer of LPI2C peripheral base addresses */ -#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE } -/** Array initializer of LPI2C peripheral base pointers */ -#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 } -/** Interrupt vectors for the LPI2C peripheral type */ -#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn } - -/*! - * @} - */ /* end of group LPI2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPSPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer - * @{ - */ - -/** LPSPI - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - uint8_t RESERVED_0[8]; - __IO uint32_t CR; /**< Control Register, offset: 0x10 */ - __IO uint32_t SR; /**< Status Register, offset: 0x14 */ - __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ - __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ - uint8_t RESERVED_1[8]; - __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ - __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ - uint8_t RESERVED_2[8]; - __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ - uint8_t RESERVED_3[20]; - __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ - __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ - __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ - __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ - uint8_t RESERVED_4[8]; - __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ - __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ -} LPSPI_Type; - -/* ---------------------------------------------------------------------------- - -- LPSPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPSPI_Register_Masks LPSPI Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) -#define LPSPI_VERID_FEATURE_SHIFT (0U) -#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) -#define LPSPI_VERID_MINOR_MASK (0xFF0000U) -#define LPSPI_VERID_MINOR_SHIFT (16U) -#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) -#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) -#define LPSPI_VERID_MAJOR_SHIFT (24U) -#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) -#define LPSPI_PARAM_TXFIFO_SHIFT (0U) -#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) -#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) -#define LPSPI_PARAM_RXFIFO_SHIFT (8U) -#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) -#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) -#define LPSPI_PARAM_PCSNUM_SHIFT (16U) -#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) -/*! @} */ - -/*! @name CR - Control Register */ -/*! @{ */ -#define LPSPI_CR_MEN_MASK (0x1U) -#define LPSPI_CR_MEN_SHIFT (0U) -#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) -#define LPSPI_CR_RST_MASK (0x2U) -#define LPSPI_CR_RST_SHIFT (1U) -#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) -#define LPSPI_CR_DOZEN_MASK (0x4U) -#define LPSPI_CR_DOZEN_SHIFT (2U) -#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) -#define LPSPI_CR_DBGEN_MASK (0x8U) -#define LPSPI_CR_DBGEN_SHIFT (3U) -#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) -#define LPSPI_CR_RTF_MASK (0x100U) -#define LPSPI_CR_RTF_SHIFT (8U) -#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) -#define LPSPI_CR_RRF_MASK (0x200U) -#define LPSPI_CR_RRF_SHIFT (9U) -#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) -/*! @} */ - -/*! @name SR - Status Register */ -/*! @{ */ -#define LPSPI_SR_TDF_MASK (0x1U) -#define LPSPI_SR_TDF_SHIFT (0U) -#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) -#define LPSPI_SR_RDF_MASK (0x2U) -#define LPSPI_SR_RDF_SHIFT (1U) -#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) -#define LPSPI_SR_WCF_MASK (0x100U) -#define LPSPI_SR_WCF_SHIFT (8U) -#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) -#define LPSPI_SR_FCF_MASK (0x200U) -#define LPSPI_SR_FCF_SHIFT (9U) -#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) -#define LPSPI_SR_TCF_MASK (0x400U) -#define LPSPI_SR_TCF_SHIFT (10U) -#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) -#define LPSPI_SR_TEF_MASK (0x800U) -#define LPSPI_SR_TEF_SHIFT (11U) -#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) -#define LPSPI_SR_REF_MASK (0x1000U) -#define LPSPI_SR_REF_SHIFT (12U) -#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) -#define LPSPI_SR_DMF_MASK (0x2000U) -#define LPSPI_SR_DMF_SHIFT (13U) -#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) -#define LPSPI_SR_MBF_MASK (0x1000000U) -#define LPSPI_SR_MBF_SHIFT (24U) -#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) -/*! @} */ - -/*! @name IER - Interrupt Enable Register */ -/*! @{ */ -#define LPSPI_IER_TDIE_MASK (0x1U) -#define LPSPI_IER_TDIE_SHIFT (0U) -#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) -#define LPSPI_IER_RDIE_MASK (0x2U) -#define LPSPI_IER_RDIE_SHIFT (1U) -#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) -#define LPSPI_IER_WCIE_MASK (0x100U) -#define LPSPI_IER_WCIE_SHIFT (8U) -#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) -#define LPSPI_IER_FCIE_MASK (0x200U) -#define LPSPI_IER_FCIE_SHIFT (9U) -#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) -#define LPSPI_IER_TCIE_MASK (0x400U) -#define LPSPI_IER_TCIE_SHIFT (10U) -#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) -#define LPSPI_IER_TEIE_MASK (0x800U) -#define LPSPI_IER_TEIE_SHIFT (11U) -#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) -#define LPSPI_IER_REIE_MASK (0x1000U) -#define LPSPI_IER_REIE_SHIFT (12U) -#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) -#define LPSPI_IER_DMIE_MASK (0x2000U) -#define LPSPI_IER_DMIE_SHIFT (13U) -#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) -/*! @} */ - -/*! @name DER - DMA Enable Register */ -/*! @{ */ -#define LPSPI_DER_TDDE_MASK (0x1U) -#define LPSPI_DER_TDDE_SHIFT (0U) -#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) -#define LPSPI_DER_RDDE_MASK (0x2U) -#define LPSPI_DER_RDDE_SHIFT (1U) -#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) -/*! @} */ - -/*! @name CFGR0 - Configuration Register 0 */ -/*! @{ */ -#define LPSPI_CFGR0_HREN_MASK (0x1U) -#define LPSPI_CFGR0_HREN_SHIFT (0U) -#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) -#define LPSPI_CFGR0_HRPOL_MASK (0x2U) -#define LPSPI_CFGR0_HRPOL_SHIFT (1U) -#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) -#define LPSPI_CFGR0_HRSEL_MASK (0x4U) -#define LPSPI_CFGR0_HRSEL_SHIFT (2U) -#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) -#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) -#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) -#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) -#define LPSPI_CFGR0_RDMO_MASK (0x200U) -#define LPSPI_CFGR0_RDMO_SHIFT (9U) -#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) -/*! @} */ - -/*! @name CFGR1 - Configuration Register 1 */ -/*! @{ */ -#define LPSPI_CFGR1_MASTER_MASK (0x1U) -#define LPSPI_CFGR1_MASTER_SHIFT (0U) -#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) -#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) -#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) -#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) -#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) -#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) -#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) -#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) -#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) -#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) -#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) -#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) -#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) -#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) -#define LPSPI_CFGR1_MATCFG_SHIFT (16U) -#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) -#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) -#define LPSPI_CFGR1_PINCFG_SHIFT (24U) -#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) -#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) -#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) -#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) -#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) -#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) -#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) -/*! @} */ - -/*! @name DMR0 - Data Match Register 0 */ -/*! @{ */ -#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) -#define LPSPI_DMR0_MATCH0_SHIFT (0U) -#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) -/*! @} */ - -/*! @name DMR1 - Data Match Register 1 */ -/*! @{ */ -#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) -#define LPSPI_DMR1_MATCH1_SHIFT (0U) -#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) -/*! @} */ - -/*! @name CCR - Clock Configuration Register */ -/*! @{ */ -#define LPSPI_CCR_SCKDIV_MASK (0xFFU) -#define LPSPI_CCR_SCKDIV_SHIFT (0U) -#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) -#define LPSPI_CCR_DBT_MASK (0xFF00U) -#define LPSPI_CCR_DBT_SHIFT (8U) -#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) -#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) -#define LPSPI_CCR_PCSSCK_SHIFT (16U) -#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) -#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) -#define LPSPI_CCR_SCKPCS_SHIFT (24U) -#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) -/*! @} */ - -/*! @name FCR - FIFO Control Register */ -/*! @{ */ -#define LPSPI_FCR_TXWATER_MASK (0xFU) -#define LPSPI_FCR_TXWATER_SHIFT (0U) -#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) -#define LPSPI_FCR_RXWATER_MASK (0xF0000U) -#define LPSPI_FCR_RXWATER_SHIFT (16U) -#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) -/*! @} */ - -/*! @name FSR - FIFO Status Register */ -/*! @{ */ -#define LPSPI_FSR_TXCOUNT_MASK (0x1FU) -#define LPSPI_FSR_TXCOUNT_SHIFT (0U) -#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) -#define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U) -#define LPSPI_FSR_RXCOUNT_SHIFT (16U) -#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) -/*! @} */ - -/*! @name TCR - Transmit Command Register */ -/*! @{ */ -#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) -#define LPSPI_TCR_FRAMESZ_SHIFT (0U) -#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) -#define LPSPI_TCR_WIDTH_MASK (0x30000U) -#define LPSPI_TCR_WIDTH_SHIFT (16U) -#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) -#define LPSPI_TCR_TXMSK_MASK (0x40000U) -#define LPSPI_TCR_TXMSK_SHIFT (18U) -#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) -#define LPSPI_TCR_RXMSK_MASK (0x80000U) -#define LPSPI_TCR_RXMSK_SHIFT (19U) -#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) -#define LPSPI_TCR_CONTC_MASK (0x100000U) -#define LPSPI_TCR_CONTC_SHIFT (20U) -#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) -#define LPSPI_TCR_CONT_MASK (0x200000U) -#define LPSPI_TCR_CONT_SHIFT (21U) -#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) -#define LPSPI_TCR_BYSW_MASK (0x400000U) -#define LPSPI_TCR_BYSW_SHIFT (22U) -#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) -#define LPSPI_TCR_LSBF_MASK (0x800000U) -#define LPSPI_TCR_LSBF_SHIFT (23U) -#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) -#define LPSPI_TCR_PCS_MASK (0x3000000U) -#define LPSPI_TCR_PCS_SHIFT (24U) -#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) -#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) -#define LPSPI_TCR_PRESCALE_SHIFT (27U) -#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) -#define LPSPI_TCR_CPHA_MASK (0x40000000U) -#define LPSPI_TCR_CPHA_SHIFT (30U) -#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) -#define LPSPI_TCR_CPOL_MASK (0x80000000U) -#define LPSPI_TCR_CPOL_SHIFT (31U) -#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) -/*! @} */ - -/*! @name TDR - Transmit Data Register */ -/*! @{ */ -#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) -#define LPSPI_TDR_DATA_SHIFT (0U) -#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) -/*! @} */ - -/*! @name RSR - Receive Status Register */ -/*! @{ */ -#define LPSPI_RSR_SOF_MASK (0x1U) -#define LPSPI_RSR_SOF_SHIFT (0U) -#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) -#define LPSPI_RSR_RXEMPTY_MASK (0x2U) -#define LPSPI_RSR_RXEMPTY_SHIFT (1U) -#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) -/*! @} */ - -/*! @name RDR - Receive Data Register */ -/*! @{ */ -#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) -#define LPSPI_RDR_DATA_SHIFT (0U) -#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPSPI_Register_Masks */ - - -/* LPSPI - Peripheral instance base addresses */ -/** Peripheral LPSPI1 base address */ -#define LPSPI1_BASE (0x40394000u) -/** Peripheral LPSPI1 base pointer */ -#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) -/** Peripheral LPSPI2 base address */ -#define LPSPI2_BASE (0x40398000u) -/** Peripheral LPSPI2 base pointer */ -#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) -/** Peripheral LPSPI3 base address */ -#define LPSPI3_BASE (0x4039C000u) -/** Peripheral LPSPI3 base pointer */ -#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) -/** Peripheral LPSPI4 base address */ -#define LPSPI4_BASE (0x403A0000u) -/** Peripheral LPSPI4 base pointer */ -#define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) -/** Array initializer of LPSPI peripheral base addresses */ -#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE } -/** Array initializer of LPSPI peripheral base pointers */ -#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 } -/** Interrupt vectors for the LPSPI peripheral type */ -#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn } - -/*! - * @} - */ /* end of group LPSPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPUART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer - * @{ - */ - -/** LPUART - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ - __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ - __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ - __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ - __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ - __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ - __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ - __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ - __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ - __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ -} LPUART_Type; - -/* ---------------------------------------------------------------------------- - -- LPUART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup LPUART_Register_Masks LPUART Register Masks - * @{ - */ - -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define LPUART_VERID_FEATURE_MASK (0xFFFFU) -#define LPUART_VERID_FEATURE_SHIFT (0U) -#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) -#define LPUART_VERID_MINOR_MASK (0xFF0000U) -#define LPUART_VERID_MINOR_SHIFT (16U) -#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) -#define LPUART_VERID_MAJOR_MASK (0xFF000000U) -#define LPUART_VERID_MAJOR_SHIFT (24U) -#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) -/*! @} */ - -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define LPUART_PARAM_TXFIFO_MASK (0xFFU) -#define LPUART_PARAM_TXFIFO_SHIFT (0U) -#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) -#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) -#define LPUART_PARAM_RXFIFO_SHIFT (8U) -#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) -/*! @} */ - -/*! @name GLOBAL - LPUART Global Register */ -/*! @{ */ -#define LPUART_GLOBAL_RST_MASK (0x2U) -#define LPUART_GLOBAL_RST_SHIFT (1U) -#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) -/*! @} */ - -/*! @name PINCFG - LPUART Pin Configuration Register */ -/*! @{ */ -#define LPUART_PINCFG_TRGSEL_MASK (0x3U) -#define LPUART_PINCFG_TRGSEL_SHIFT (0U) -#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) -/*! @} */ - -/*! @name BAUD - LPUART Baud Rate Register */ -/*! @{ */ -#define LPUART_BAUD_SBR_MASK (0x1FFFU) -#define LPUART_BAUD_SBR_SHIFT (0U) -#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) -#define LPUART_BAUD_SBNS_MASK (0x2000U) -#define LPUART_BAUD_SBNS_SHIFT (13U) -#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) -#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) -#define LPUART_BAUD_RXEDGIE_SHIFT (14U) -#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) -#define LPUART_BAUD_LBKDIE_MASK (0x8000U) -#define LPUART_BAUD_LBKDIE_SHIFT (15U) -#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) -#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) -#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) -#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) -#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) -#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) -#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) -#define LPUART_BAUD_MATCFG_MASK (0xC0000U) -#define LPUART_BAUD_MATCFG_SHIFT (18U) -#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) -#define LPUART_BAUD_RIDMAE_MASK (0x100000U) -#define LPUART_BAUD_RIDMAE_SHIFT (20U) -#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) -#define LPUART_BAUD_RDMAE_MASK (0x200000U) -#define LPUART_BAUD_RDMAE_SHIFT (21U) -#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) -#define LPUART_BAUD_TDMAE_MASK (0x800000U) -#define LPUART_BAUD_TDMAE_SHIFT (23U) -#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) -#define LPUART_BAUD_OSR_MASK (0x1F000000U) -#define LPUART_BAUD_OSR_SHIFT (24U) -#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) -#define LPUART_BAUD_M10_MASK (0x20000000U) -#define LPUART_BAUD_M10_SHIFT (29U) -#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) -#define LPUART_BAUD_MAEN2_MASK (0x40000000U) -#define LPUART_BAUD_MAEN2_SHIFT (30U) -#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) -#define LPUART_BAUD_MAEN1_MASK (0x80000000U) -#define LPUART_BAUD_MAEN1_SHIFT (31U) -#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) -/*! @} */ - -/*! @name STAT - LPUART Status Register */ -/*! @{ */ -#define LPUART_STAT_MA2F_MASK (0x4000U) -#define LPUART_STAT_MA2F_SHIFT (14U) -#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) -#define LPUART_STAT_MA1F_MASK (0x8000U) -#define LPUART_STAT_MA1F_SHIFT (15U) -#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) -#define LPUART_STAT_PF_MASK (0x10000U) -#define LPUART_STAT_PF_SHIFT (16U) -#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) -#define LPUART_STAT_FE_MASK (0x20000U) -#define LPUART_STAT_FE_SHIFT (17U) -#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) -#define LPUART_STAT_NF_MASK (0x40000U) -#define LPUART_STAT_NF_SHIFT (18U) -#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) -#define LPUART_STAT_OR_MASK (0x80000U) -#define LPUART_STAT_OR_SHIFT (19U) -#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) -#define LPUART_STAT_IDLE_MASK (0x100000U) -#define LPUART_STAT_IDLE_SHIFT (20U) -#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) -#define LPUART_STAT_RDRF_MASK (0x200000U) -#define LPUART_STAT_RDRF_SHIFT (21U) -#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) -#define LPUART_STAT_TC_MASK (0x400000U) -#define LPUART_STAT_TC_SHIFT (22U) -#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) -#define LPUART_STAT_TDRE_MASK (0x800000U) -#define LPUART_STAT_TDRE_SHIFT (23U) -#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) -#define LPUART_STAT_RAF_MASK (0x1000000U) -#define LPUART_STAT_RAF_SHIFT (24U) -#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) -#define LPUART_STAT_LBKDE_MASK (0x2000000U) -#define LPUART_STAT_LBKDE_SHIFT (25U) -#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) -#define LPUART_STAT_BRK13_MASK (0x4000000U) -#define LPUART_STAT_BRK13_SHIFT (26U) -#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) -#define LPUART_STAT_RWUID_MASK (0x8000000U) -#define LPUART_STAT_RWUID_SHIFT (27U) -#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) -#define LPUART_STAT_RXINV_MASK (0x10000000U) -#define LPUART_STAT_RXINV_SHIFT (28U) -#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) -#define LPUART_STAT_MSBF_MASK (0x20000000U) -#define LPUART_STAT_MSBF_SHIFT (29U) -#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) -#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) -#define LPUART_STAT_RXEDGIF_SHIFT (30U) -#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) -#define LPUART_STAT_LBKDIF_MASK (0x80000000U) -#define LPUART_STAT_LBKDIF_SHIFT (31U) -#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) -/*! @} */ - -/*! @name CTRL - LPUART Control Register */ -/*! @{ */ -#define LPUART_CTRL_PT_MASK (0x1U) -#define LPUART_CTRL_PT_SHIFT (0U) -#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) -#define LPUART_CTRL_PE_MASK (0x2U) -#define LPUART_CTRL_PE_SHIFT (1U) -#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) -#define LPUART_CTRL_ILT_MASK (0x4U) -#define LPUART_CTRL_ILT_SHIFT (2U) -#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) -#define LPUART_CTRL_WAKE_MASK (0x8U) -#define LPUART_CTRL_WAKE_SHIFT (3U) -#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) -#define LPUART_CTRL_M_MASK (0x10U) -#define LPUART_CTRL_M_SHIFT (4U) -#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) -#define LPUART_CTRL_RSRC_MASK (0x20U) -#define LPUART_CTRL_RSRC_SHIFT (5U) -#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) -#define LPUART_CTRL_DOZEEN_MASK (0x40U) -#define LPUART_CTRL_DOZEEN_SHIFT (6U) -#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) -#define LPUART_CTRL_LOOPS_MASK (0x80U) -#define LPUART_CTRL_LOOPS_SHIFT (7U) -#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) -#define LPUART_CTRL_IDLECFG_MASK (0x700U) -#define LPUART_CTRL_IDLECFG_SHIFT (8U) -#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) -#define LPUART_CTRL_M7_MASK (0x800U) -#define LPUART_CTRL_M7_SHIFT (11U) -#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) -#define LPUART_CTRL_MA2IE_MASK (0x4000U) -#define LPUART_CTRL_MA2IE_SHIFT (14U) -#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) -#define LPUART_CTRL_MA1IE_MASK (0x8000U) -#define LPUART_CTRL_MA1IE_SHIFT (15U) -#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) -#define LPUART_CTRL_SBK_MASK (0x10000U) -#define LPUART_CTRL_SBK_SHIFT (16U) -#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) -#define LPUART_CTRL_RWU_MASK (0x20000U) -#define LPUART_CTRL_RWU_SHIFT (17U) -#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) -#define LPUART_CTRL_RE_MASK (0x40000U) -#define LPUART_CTRL_RE_SHIFT (18U) -#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) -#define LPUART_CTRL_TE_MASK (0x80000U) -#define LPUART_CTRL_TE_SHIFT (19U) -#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) -#define LPUART_CTRL_ILIE_MASK (0x100000U) -#define LPUART_CTRL_ILIE_SHIFT (20U) -#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) -#define LPUART_CTRL_RIE_MASK (0x200000U) -#define LPUART_CTRL_RIE_SHIFT (21U) -#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) -#define LPUART_CTRL_TCIE_MASK (0x400000U) -#define LPUART_CTRL_TCIE_SHIFT (22U) -#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) -#define LPUART_CTRL_TIE_MASK (0x800000U) -#define LPUART_CTRL_TIE_SHIFT (23U) -#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) -#define LPUART_CTRL_PEIE_MASK (0x1000000U) -#define LPUART_CTRL_PEIE_SHIFT (24U) -#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) -#define LPUART_CTRL_FEIE_MASK (0x2000000U) -#define LPUART_CTRL_FEIE_SHIFT (25U) -#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) -#define LPUART_CTRL_NEIE_MASK (0x4000000U) -#define LPUART_CTRL_NEIE_SHIFT (26U) -#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) -#define LPUART_CTRL_ORIE_MASK (0x8000000U) -#define LPUART_CTRL_ORIE_SHIFT (27U) -#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) -#define LPUART_CTRL_TXINV_MASK (0x10000000U) -#define LPUART_CTRL_TXINV_SHIFT (28U) -#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) -#define LPUART_CTRL_TXDIR_MASK (0x20000000U) -#define LPUART_CTRL_TXDIR_SHIFT (29U) -#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) -#define LPUART_CTRL_R9T8_MASK (0x40000000U) -#define LPUART_CTRL_R9T8_SHIFT (30U) -#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) -#define LPUART_CTRL_R8T9_MASK (0x80000000U) -#define LPUART_CTRL_R8T9_SHIFT (31U) -#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) -/*! @} */ - -/*! @name DATA - LPUART Data Register */ -/*! @{ */ -#define LPUART_DATA_R0T0_MASK (0x1U) -#define LPUART_DATA_R0T0_SHIFT (0U) -#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) -#define LPUART_DATA_R1T1_MASK (0x2U) -#define LPUART_DATA_R1T1_SHIFT (1U) -#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) -#define LPUART_DATA_R2T2_MASK (0x4U) -#define LPUART_DATA_R2T2_SHIFT (2U) -#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) -#define LPUART_DATA_R3T3_MASK (0x8U) -#define LPUART_DATA_R3T3_SHIFT (3U) -#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) -#define LPUART_DATA_R4T4_MASK (0x10U) -#define LPUART_DATA_R4T4_SHIFT (4U) -#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) -#define LPUART_DATA_R5T5_MASK (0x20U) -#define LPUART_DATA_R5T5_SHIFT (5U) -#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) -#define LPUART_DATA_R6T6_MASK (0x40U) -#define LPUART_DATA_R6T6_SHIFT (6U) -#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) -#define LPUART_DATA_R7T7_MASK (0x80U) -#define LPUART_DATA_R7T7_SHIFT (7U) -#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) -#define LPUART_DATA_R8T8_MASK (0x100U) -#define LPUART_DATA_R8T8_SHIFT (8U) -#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) -#define LPUART_DATA_R9T9_MASK (0x200U) -#define LPUART_DATA_R9T9_SHIFT (9U) -#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) -#define LPUART_DATA_IDLINE_MASK (0x800U) -#define LPUART_DATA_IDLINE_SHIFT (11U) -#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) -#define LPUART_DATA_RXEMPT_MASK (0x1000U) -#define LPUART_DATA_RXEMPT_SHIFT (12U) -#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) -#define LPUART_DATA_FRETSC_MASK (0x2000U) -#define LPUART_DATA_FRETSC_SHIFT (13U) -#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) -#define LPUART_DATA_PARITYE_MASK (0x4000U) -#define LPUART_DATA_PARITYE_SHIFT (14U) -#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) -#define LPUART_DATA_NOISY_MASK (0x8000U) -#define LPUART_DATA_NOISY_SHIFT (15U) -#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) -/*! @} */ - -/*! @name MATCH - LPUART Match Address Register */ -/*! @{ */ -#define LPUART_MATCH_MA1_MASK (0x3FFU) -#define LPUART_MATCH_MA1_SHIFT (0U) -#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) -#define LPUART_MATCH_MA2_MASK (0x3FF0000U) -#define LPUART_MATCH_MA2_SHIFT (16U) -#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) -/*! @} */ - -/*! @name MODIR - LPUART Modem IrDA Register */ -/*! @{ */ -#define LPUART_MODIR_TXCTSE_MASK (0x1U) -#define LPUART_MODIR_TXCTSE_SHIFT (0U) -#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) -#define LPUART_MODIR_TXRTSE_MASK (0x2U) -#define LPUART_MODIR_TXRTSE_SHIFT (1U) -#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) -#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) -#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) -#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) -#define LPUART_MODIR_RXRTSE_MASK (0x8U) -#define LPUART_MODIR_RXRTSE_SHIFT (3U) -#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) -#define LPUART_MODIR_TXCTSC_MASK (0x10U) -#define LPUART_MODIR_TXCTSC_SHIFT (4U) -#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) -#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) -#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) -#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) -#define LPUART_MODIR_RTSWATER_MASK (0x300U) -#define LPUART_MODIR_RTSWATER_SHIFT (8U) -#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) -#define LPUART_MODIR_TNP_MASK (0x30000U) -#define LPUART_MODIR_TNP_SHIFT (16U) -#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) -#define LPUART_MODIR_IREN_MASK (0x40000U) -#define LPUART_MODIR_IREN_SHIFT (18U) -#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) -/*! @} */ - -/*! @name FIFO - LPUART FIFO Register */ -/*! @{ */ -#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) -#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) -#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) -#define LPUART_FIFO_RXFE_MASK (0x8U) -#define LPUART_FIFO_RXFE_SHIFT (3U) -#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) -#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) -#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) -#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) -#define LPUART_FIFO_TXFE_MASK (0x80U) -#define LPUART_FIFO_TXFE_SHIFT (7U) -#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) -#define LPUART_FIFO_RXUFE_MASK (0x100U) -#define LPUART_FIFO_RXUFE_SHIFT (8U) -#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) -#define LPUART_FIFO_TXOFE_MASK (0x200U) -#define LPUART_FIFO_TXOFE_SHIFT (9U) -#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) -#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) -#define LPUART_FIFO_RXIDEN_SHIFT (10U) -#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) -#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) -#define LPUART_FIFO_RXFLUSH_SHIFT (14U) -#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) -#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) -#define LPUART_FIFO_TXFLUSH_SHIFT (15U) -#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) -#define LPUART_FIFO_RXUF_MASK (0x10000U) -#define LPUART_FIFO_RXUF_SHIFT (16U) -#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) -#define LPUART_FIFO_TXOF_MASK (0x20000U) -#define LPUART_FIFO_TXOF_SHIFT (17U) -#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) -#define LPUART_FIFO_RXEMPT_MASK (0x400000U) -#define LPUART_FIFO_RXEMPT_SHIFT (22U) -#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) -#define LPUART_FIFO_TXEMPT_MASK (0x800000U) -#define LPUART_FIFO_TXEMPT_SHIFT (23U) -#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) -/*! @} */ - -/*! @name WATER - LPUART Watermark Register */ -/*! @{ */ -#define LPUART_WATER_TXWATER_MASK (0x3U) -#define LPUART_WATER_TXWATER_SHIFT (0U) -#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) -#define LPUART_WATER_TXCOUNT_MASK (0x700U) -#define LPUART_WATER_TXCOUNT_SHIFT (8U) -#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) -#define LPUART_WATER_RXWATER_MASK (0x30000U) -#define LPUART_WATER_RXWATER_SHIFT (16U) -#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) -#define LPUART_WATER_RXCOUNT_MASK (0x7000000U) -#define LPUART_WATER_RXCOUNT_SHIFT (24U) -#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group LPUART_Register_Masks */ - - -/* LPUART - Peripheral instance base addresses */ -/** Peripheral LPUART1 base address */ -#define LPUART1_BASE (0x40184000u) -/** Peripheral LPUART1 base pointer */ -#define LPUART1 ((LPUART_Type *)LPUART1_BASE) -/** Peripheral LPUART2 base address */ -#define LPUART2_BASE (0x40188000u) -/** Peripheral LPUART2 base pointer */ -#define LPUART2 ((LPUART_Type *)LPUART2_BASE) -/** Peripheral LPUART3 base address */ -#define LPUART3_BASE (0x4018C000u) -/** Peripheral LPUART3 base pointer */ -#define LPUART3 ((LPUART_Type *)LPUART3_BASE) -/** Peripheral LPUART4 base address */ -#define LPUART4_BASE (0x40190000u) -/** Peripheral LPUART4 base pointer */ -#define LPUART4 ((LPUART_Type *)LPUART4_BASE) -/** Peripheral LPUART5 base address */ -#define LPUART5_BASE (0x40194000u) -/** Peripheral LPUART5 base pointer */ -#define LPUART5 ((LPUART_Type *)LPUART5_BASE) -/** Peripheral LPUART6 base address */ -#define LPUART6_BASE (0x40198000u) -/** Peripheral LPUART6 base pointer */ -#define LPUART6 ((LPUART_Type *)LPUART6_BASE) -/** Peripheral LPUART7 base address */ -#define LPUART7_BASE (0x4019C000u) -/** Peripheral LPUART7 base pointer */ -#define LPUART7 ((LPUART_Type *)LPUART7_BASE) -/** Peripheral LPUART8 base address */ -#define LPUART8_BASE (0x401A0000u) -/** Peripheral LPUART8 base pointer */ -#define LPUART8 ((LPUART_Type *)LPUART8_BASE) -/** Array initializer of LPUART peripheral base addresses */ -#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE } -/** Array initializer of LPUART peripheral base pointers */ -#define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 } -/** Interrupt vectors for the LPUART peripheral type */ -#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn } - -/*! - * @} - */ /* end of group LPUART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- OCOTP Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer - * @{ - */ - -/** OCOTP - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ - __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ - __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ - __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ - __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ - uint8_t RESERVED_1[12]; - __IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */ - uint8_t RESERVED_2[12]; - __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */ - uint8_t RESERVED_3[12]; - __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ - uint8_t RESERVED_4[12]; - __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ - __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ - __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ - __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ - uint8_t RESERVED_5[32]; - __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */ - uint8_t RESERVED_6[108]; - __IO uint32_t TIMING2; /**< OTP Controller Timing Register 2, offset: 0x100 */ - uint8_t RESERVED_7[764]; - __IO uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ - uint8_t RESERVED_8[12]; - __IO uint32_t CFG0; /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */ - uint8_t RESERVED_9[12]; - __IO uint32_t CFG1; /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */ - uint8_t RESERVED_10[12]; - __IO uint32_t CFG2; /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */ - uint8_t RESERVED_11[12]; - __IO uint32_t CFG3; /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */ - uint8_t RESERVED_12[12]; - __IO uint32_t CFG4; /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */ - uint8_t RESERVED_13[12]; - __IO uint32_t CFG5; /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */ - uint8_t RESERVED_14[12]; - __IO uint32_t CFG6; /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */ - uint8_t RESERVED_15[12]; - __IO uint32_t MEM0; /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */ - uint8_t RESERVED_16[12]; - __IO uint32_t MEM1; /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */ - uint8_t RESERVED_17[12]; - __IO uint32_t MEM2; /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */ - uint8_t RESERVED_18[12]; - __IO uint32_t MEM3; /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */ - uint8_t RESERVED_19[12]; - __IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */ - uint8_t RESERVED_20[12]; - __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Analog Info.), offset: 0x4D0 */ - uint8_t RESERVED_21[12]; - __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (Analog Info.), offset: 0x4E0 */ - uint8_t RESERVED_22[12]; - __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (Analog Info.), offset: 0x4F0 */ - uint8_t RESERVED_23[140]; - __IO uint32_t SRK0; /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */ - uint8_t RESERVED_24[12]; - __IO uint32_t SRK1; /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */ - uint8_t RESERVED_25[12]; - __IO uint32_t SRK2; /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */ - uint8_t RESERVED_26[12]; - __IO uint32_t SRK3; /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */ - uint8_t RESERVED_27[12]; - __IO uint32_t SRK4; /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */ - uint8_t RESERVED_28[12]; - __IO uint32_t SRK5; /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */ - uint8_t RESERVED_29[12]; - __IO uint32_t SRK6; /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */ - uint8_t RESERVED_30[12]; - __IO uint32_t SRK7; /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */ - uint8_t RESERVED_31[12]; - __IO uint32_t SJC_RESP0; /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */ - uint8_t RESERVED_32[12]; - __IO uint32_t SJC_RESP1; /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */ - uint8_t RESERVED_33[12]; - __IO uint32_t MAC0; /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */ - uint8_t RESERVED_34[12]; - __IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */ - uint8_t RESERVED_35[12]; - __IO uint32_t GP3; /**< Value of OTP Bank4 Word4 (MAC Address), offset: 0x640 */ - uint8_t RESERVED_36[28]; - __IO uint32_t GP1; /**< Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660 */ - uint8_t RESERVED_37[12]; - __IO uint32_t GP2; /**< Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670 */ - uint8_t RESERVED_38[12]; - __IO uint32_t SW_GP1; /**< Value of OTP Bank5 Word0 (SW GP1), offset: 0x680 */ - uint8_t RESERVED_39[12]; - __IO uint32_t SW_GP20; /**< Value of OTP Bank5 Word1 (SW GP2), offset: 0x690 */ - uint8_t RESERVED_40[12]; - __IO uint32_t SW_GP21; /**< Value of OTP Bank5 Word2 (SW GP2), offset: 0x6A0 */ - uint8_t RESERVED_41[12]; - __IO uint32_t SW_GP22; /**< Value of OTP Bank5 Word3 (SW GP2), offset: 0x6B0 */ - uint8_t RESERVED_42[12]; - __IO uint32_t SW_GP23; /**< Value of OTP Bank5 Word4 (SW GP2), offset: 0x6C0 */ - uint8_t RESERVED_43[12]; - __IO uint32_t MISC_CONF0; /**< Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0 */ - uint8_t RESERVED_44[12]; - __IO uint32_t MISC_CONF1; /**< Value of OTP Bank5 Word6 (Misc Conf), offset: 0x6E0 */ - uint8_t RESERVED_45[12]; - __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0 */ -} OCOTP_Type; - -/* ---------------------------------------------------------------------------- - -- OCOTP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OCOTP_Register_Masks OCOTP Register Masks - * @{ - */ - -/*! @name CTRL - OTP Controller Control Register */ -/*! @{ */ -#define OCOTP_CTRL_ADDR_MASK (0x3FU) -#define OCOTP_CTRL_ADDR_SHIFT (0U) -#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) -#define OCOTP_CTRL_BUSY_MASK (0x100U) -#define OCOTP_CTRL_BUSY_SHIFT (8U) -#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) -#define OCOTP_CTRL_ERROR_MASK (0x200U) -#define OCOTP_CTRL_ERROR_SHIFT (9U) -#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) -#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) -#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) -#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) -#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) -#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) -#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) -/*! @} */ - -/*! @name CTRL_SET - OTP Controller Control Register */ -/*! @{ */ -#define OCOTP_CTRL_SET_ADDR_MASK (0x3FU) -#define OCOTP_CTRL_SET_ADDR_SHIFT (0U) -#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) -#define OCOTP_CTRL_SET_BUSY_MASK (0x100U) -#define OCOTP_CTRL_SET_BUSY_SHIFT (8U) -#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) -#define OCOTP_CTRL_SET_ERROR_MASK (0x200U) -#define OCOTP_CTRL_SET_ERROR_SHIFT (9U) -#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) -#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U) -#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U) -#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) -#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) -#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) -#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) -/*! @} */ - -/*! @name CTRL_CLR - OTP Controller Control Register */ -/*! @{ */ -#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU) -#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) -#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) -#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U) -#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U) -#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) -#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U) -#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U) -#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) -#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U) -#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U) -#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) -#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) -#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) -#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) -/*! @} */ - -/*! @name CTRL_TOG - OTP Controller Control Register */ -/*! @{ */ -#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU) -#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) -#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) -#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U) -#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U) -#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) -#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U) -#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U) -#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) -#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U) -#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U) -#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) -#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) -#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) -#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) -/*! @} */ - -/*! @name TIMING - OTP Controller Timing Register */ -/*! @{ */ -#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) -#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) -#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) -#define OCOTP_TIMING_RELAX_MASK (0xF000U) -#define OCOTP_TIMING_RELAX_SHIFT (12U) -#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK) -#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U) -#define OCOTP_TIMING_STROBE_READ_SHIFT (16U) -#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK) -#define OCOTP_TIMING_WAIT_MASK (0xFC00000U) -#define OCOTP_TIMING_WAIT_SHIFT (22U) -#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) -/*! @} */ - -/*! @name DATA - OTP Controller Write Data Register */ -/*! @{ */ -#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) -#define OCOTP_DATA_DATA_SHIFT (0U) -#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) -/*! @} */ - -/*! @name READ_CTRL - OTP Controller Write Data Register */ -/*! @{ */ -#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) -#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) -#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) -/*! @} */ - -/*! @name READ_FUSE_DATA - OTP Controller Read Data Register */ -/*! @{ */ -#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) -#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) -#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) -/*! @} */ - -/*! @name SW_STICKY - Sticky bit Register */ -/*! @{ */ -#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U) -#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U) -#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK) -#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U) -#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U) -#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK) -#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) -#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) -#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) -#define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U) -#define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U) -#define OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK) -#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U) -#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U) -#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK) -/*! @} */ - -/*! @name SCS - Software Controllable Signals Register */ -/*! @{ */ -#define OCOTP_SCS_HAB_JDE_MASK (0x1U) -#define OCOTP_SCS_HAB_JDE_SHIFT (0U) -#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) -#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) -#define OCOTP_SCS_SPARE_SHIFT (1U) -#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK) -#define OCOTP_SCS_LOCK_MASK (0x80000000U) -#define OCOTP_SCS_LOCK_SHIFT (31U) -#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) -/*! @} */ - -/*! @name SCS_SET - Software Controllable Signals Register */ -/*! @{ */ -#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) -#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) -#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) -#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) -#define OCOTP_SCS_SET_SPARE_SHIFT (1U) -#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK) -#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) -#define OCOTP_SCS_SET_LOCK_SHIFT (31U) -#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) -/*! @} */ - -/*! @name SCS_CLR - Software Controllable Signals Register */ -/*! @{ */ -#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) -#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) -#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) -#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) -#define OCOTP_SCS_CLR_SPARE_SHIFT (1U) -#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK) -#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) -#define OCOTP_SCS_CLR_LOCK_SHIFT (31U) -#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) -/*! @} */ - -/*! @name SCS_TOG - Software Controllable Signals Register */ -/*! @{ */ -#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) -#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) -#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) -#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) -#define OCOTP_SCS_TOG_SPARE_SHIFT (1U) -#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK) -#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) -#define OCOTP_SCS_TOG_LOCK_SHIFT (31U) -#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) -/*! @} */ - -/*! @name VERSION - OTP Controller Version Register */ -/*! @{ */ -#define OCOTP_VERSION_STEP_MASK (0xFFFFU) -#define OCOTP_VERSION_STEP_SHIFT (0U) -#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) -#define OCOTP_VERSION_MINOR_MASK (0xFF0000U) -#define OCOTP_VERSION_MINOR_SHIFT (16U) -#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) -#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) -#define OCOTP_VERSION_MAJOR_SHIFT (24U) -#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) -/*! @} */ - -/*! @name TIMING2 - OTP Controller Timing Register 2 */ -/*! @{ */ -#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU) -#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U) -#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK) -#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U) -#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U) -#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK) -#define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U) -#define OCOTP_TIMING2_RELAX1_SHIFT (22U) -#define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK) -/*! @} */ - -/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ -/*! @{ */ -#define OCOTP_LOCK_TESTER_MASK (0x3U) -#define OCOTP_LOCK_TESTER_SHIFT (0U) -#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) -#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU) -#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U) -#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK) -#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U) -#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U) -#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK) -#define OCOTP_LOCK_SJC_RESP_MASK (0x40U) -#define OCOTP_LOCK_SJC_RESP_SHIFT (6U) -#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK) -#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U) -#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U) -#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK) -#define OCOTP_LOCK_GP1_MASK (0xC00U) -#define OCOTP_LOCK_GP1_SHIFT (10U) -#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK) -#define OCOTP_LOCK_GP2_MASK (0x3000U) -#define OCOTP_LOCK_GP2_SHIFT (12U) -#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) -#define OCOTP_LOCK_SRK_MASK (0x4000U) -#define OCOTP_LOCK_SRK_SHIFT (14U) -#define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK) -#define OCOTP_LOCK_OTPMK_MSB_MASK (0x8000U) -#define OCOTP_LOCK_OTPMK_MSB_SHIFT (15U) -#define OCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK) -#define OCOTP_LOCK_SW_GP1_MASK (0x10000U) -#define OCOTP_LOCK_SW_GP1_SHIFT (16U) -#define OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK) -#define OCOTP_LOCK_OTPMK_LSB_MASK (0x20000U) -#define OCOTP_LOCK_OTPMK_LSB_SHIFT (17U) -#define OCOTP_LOCK_OTPMK_LSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_LSB_SHIFT)) & OCOTP_LOCK_OTPMK_LSB_MASK) -#define OCOTP_LOCK_ANALOG_MASK (0xC0000U) -#define OCOTP_LOCK_ANALOG_SHIFT (18U) -#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK) -#define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U) -#define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U) -#define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK) -#define OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U) -#define OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U) -#define OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK) -#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U) -#define OCOTP_LOCK_MISC_CONF_SHIFT (22U) -#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK) -#define OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U) -#define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U) -#define OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK) -#define OCOTP_LOCK_GP3_MASK (0xC000000U) -#define OCOTP_LOCK_GP3_SHIFT (26U) -#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK) -#define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U) -#define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U) -#define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK) -/*! @} */ - -/*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */ -/*! @{ */ -#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_CFG0_BITS_SHIFT (0U) -#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK) -/*! @} */ - -/*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */ -/*! @{ */ -#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_CFG1_BITS_SHIFT (0U) -#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK) -/*! @} */ - -/*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */ -/*! @{ */ -#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_CFG2_BITS_SHIFT (0U) -#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK) -/*! @} */ - -/*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */ -/*! @{ */ -#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_CFG3_BITS_SHIFT (0U) -#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK) -/*! @} */ - -/*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */ -/*! @{ */ -#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_CFG4_BITS_SHIFT (0U) -#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK) -/*! @} */ - -/*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */ -/*! @{ */ -#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_CFG5_BITS_SHIFT (0U) -#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK) -/*! @} */ - -/*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */ -/*! @{ */ -#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_CFG6_BITS_SHIFT (0U) -#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK) -/*! @} */ - -/*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */ -/*! @{ */ -#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_MEM0_BITS_SHIFT (0U) -#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK) -/*! @} */ - -/*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */ -/*! @{ */ -#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_MEM1_BITS_SHIFT (0U) -#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK) -/*! @} */ - -/*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */ -/*! @{ */ -#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_MEM2_BITS_SHIFT (0U) -#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK) -/*! @} */ - -/*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */ -/*! @{ */ -#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_MEM3_BITS_SHIFT (0U) -#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK) -/*! @} */ - -/*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */ -/*! @{ */ -#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_MEM4_BITS_SHIFT (0U) -#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) -/*! @} */ - -/*! @name ANA0 - Value of OTP Bank1 Word5 (Analog Info.) */ -/*! @{ */ -#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_ANA0_BITS_SHIFT (0U) -#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) -/*! @} */ - -/*! @name ANA1 - Value of OTP Bank1 Word6 (Analog Info.) */ -/*! @{ */ -#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_ANA1_BITS_SHIFT (0U) -#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) -/*! @} */ - -/*! @name ANA2 - Value of OTP Bank1 Word7 (Analog Info.) */ -/*! @{ */ -#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_ANA2_BITS_SHIFT (0U) -#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK) -/*! @} */ - -/*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */ -/*! @{ */ -#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SRK0_BITS_SHIFT (0U) -#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) -/*! @} */ - -/*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */ -/*! @{ */ -#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SRK1_BITS_SHIFT (0U) -#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) -/*! @} */ - -/*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */ -/*! @{ */ -#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SRK2_BITS_SHIFT (0U) -#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) -/*! @} */ - -/*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */ -/*! @{ */ -#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SRK3_BITS_SHIFT (0U) -#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) -/*! @} */ - -/*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */ -/*! @{ */ -#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SRK4_BITS_SHIFT (0U) -#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) -/*! @} */ - -/*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */ -/*! @{ */ -#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SRK5_BITS_SHIFT (0U) -#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) -/*! @} */ - -/*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */ -/*! @{ */ -#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SRK6_BITS_SHIFT (0U) -#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) -/*! @} */ - -/*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */ -/*! @{ */ -#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SRK7_BITS_SHIFT (0U) -#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) -/*! @} */ - -/*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ -/*! @{ */ -#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SJC_RESP0_BITS_SHIFT (0U) -#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) -/*! @} */ - -/*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ -/*! @{ */ -#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SJC_RESP1_BITS_SHIFT (0U) -#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) -/*! @} */ - -/*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */ -/*! @{ */ -#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_MAC0_BITS_SHIFT (0U) -#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK) -/*! @} */ - -/*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */ -/*! @{ */ -#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_MAC1_BITS_SHIFT (0U) -#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) -/*! @} */ - -/*! @name GP3 - Value of OTP Bank4 Word4 (MAC Address) */ -/*! @{ */ -#define OCOTP_GP3_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_GP3_BITS_SHIFT (0U) -#define OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK) -/*! @} */ - -/*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */ -/*! @{ */ -#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_GP1_BITS_SHIFT (0U) -#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK) -/*! @} */ - -/*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */ -/*! @{ */ -#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_GP2_BITS_SHIFT (0U) -#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK) -/*! @} */ - -/*! @name SW_GP1 - Value of OTP Bank5 Word0 (SW GP1) */ -/*! @{ */ -#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SW_GP1_BITS_SHIFT (0U) -#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK) -/*! @} */ - -/*! @name SW_GP20 - Value of OTP Bank5 Word1 (SW GP2) */ -/*! @{ */ -#define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SW_GP20_BITS_SHIFT (0U) -#define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK) -/*! @} */ - -/*! @name SW_GP21 - Value of OTP Bank5 Word2 (SW GP2) */ -/*! @{ */ -#define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SW_GP21_BITS_SHIFT (0U) -#define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK) -/*! @} */ - -/*! @name SW_GP22 - Value of OTP Bank5 Word3 (SW GP2) */ -/*! @{ */ -#define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SW_GP22_BITS_SHIFT (0U) -#define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK) -/*! @} */ - -/*! @name SW_GP23 - Value of OTP Bank5 Word4 (SW GP2) */ -/*! @{ */ -#define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SW_GP23_BITS_SHIFT (0U) -#define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK) -/*! @} */ - -/*! @name MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf) */ -/*! @{ */ -#define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_MISC_CONF0_BITS_SHIFT (0U) -#define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK) -/*! @} */ - -/*! @name MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf) */ -/*! @{ */ -#define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_MISC_CONF1_BITS_SHIFT (0U) -#define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK) -/*! @} */ - -/*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */ -/*! @{ */ -#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) -#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group OCOTP_Register_Masks */ - - -/* OCOTP - Peripheral instance base addresses */ -/** Peripheral OCOTP base address */ -#define OCOTP_BASE (0x401F4000u) -/** Peripheral OCOTP base pointer */ -#define OCOTP ((OCOTP_Type *)OCOTP_BASE) -/** Array initializer of OCOTP peripheral base addresses */ -#define OCOTP_BASE_ADDRS { OCOTP_BASE } -/** Array initializer of OCOTP peripheral base pointers */ -#define OCOTP_BASE_PTRS { OCOTP } - -/*! - * @} - */ /* end of group OCOTP_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PGC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer - * @{ - */ - -/** PGC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[544]; - __IO uint32_t MEGA_CTRL; /**< PGC Mega Control Register, offset: 0x220 */ - __IO uint32_t MEGA_PUPSCR; /**< PGC Mega Power Up Sequence Control Register, offset: 0x224 */ - __IO uint32_t MEGA_PDNSCR; /**< PGC Mega Pull Down Sequence Control Register, offset: 0x228 */ - __IO uint32_t MEGA_SR; /**< PGC Mega Power Gating Controller Status Register, offset: 0x22C */ - uint8_t RESERVED_1[112]; - __IO uint32_t CPU_CTRL; /**< PGC CPU Control Register, offset: 0x2A0 */ - __IO uint32_t CPU_PUPSCR; /**< PGC CPU Power Up Sequence Control Register, offset: 0x2A4 */ - __IO uint32_t CPU_PDNSCR; /**< PGC CPU Pull Down Sequence Control Register, offset: 0x2A8 */ - __IO uint32_t CPU_SR; /**< PGC CPU Power Gating Controller Status Register, offset: 0x2AC */ -} PGC_Type; - -/* ---------------------------------------------------------------------------- - -- PGC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PGC_Register_Masks PGC Register Masks - * @{ - */ - -/*! @name MEGA_CTRL - PGC Mega Control Register */ -/*! @{ */ -#define PGC_MEGA_CTRL_PCR_MASK (0x1U) -#define PGC_MEGA_CTRL_PCR_SHIFT (0U) -#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK) -/*! @} */ - -/*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */ -/*! @{ */ -#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU) -#define PGC_MEGA_PUPSCR_SW_SHIFT (0U) -#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK) -#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U) -#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U) -#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK) -/*! @} */ - -/*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */ -/*! @{ */ -#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU) -#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U) -#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK) -#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U) -#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U) -#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK) -/*! @} */ - -/*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */ -/*! @{ */ -#define PGC_MEGA_SR_PSR_MASK (0x1U) -#define PGC_MEGA_SR_PSR_SHIFT (0U) -#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK) -/*! @} */ - -/*! @name CPU_CTRL - PGC CPU Control Register */ -/*! @{ */ -#define PGC_CPU_CTRL_PCR_MASK (0x1U) -#define PGC_CPU_CTRL_PCR_SHIFT (0U) -#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK) -/*! @} */ - -/*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */ -/*! @{ */ -#define PGC_CPU_PUPSCR_SW_MASK (0x3FU) -#define PGC_CPU_PUPSCR_SW_SHIFT (0U) -#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK) -#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) -#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U) -#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK) -/*! @} */ - -/*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */ -/*! @{ */ -#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU) -#define PGC_CPU_PDNSCR_ISO_SHIFT (0U) -#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK) -#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) -#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U) -#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK) -/*! @} */ - -/*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */ -/*! @{ */ -#define PGC_CPU_SR_PSR_MASK (0x1U) -#define PGC_CPU_SR_PSR_SHIFT (0U) -#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PGC_Register_Masks */ - - -/* PGC - Peripheral instance base addresses */ -/** Peripheral PGC base address */ -#define PGC_BASE (0x400F4000u) -/** Peripheral PGC base pointer */ -#define PGC ((PGC_Type *)PGC_BASE) -/** Array initializer of PGC peripheral base addresses */ -#define PGC_BASE_ADDRS { PGC_BASE } -/** Array initializer of PGC peripheral base pointers */ -#define PGC_BASE_PTRS { PGC } - -/*! - * @} - */ /* end of group PGC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PIT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer - * @{ - */ - -/** PIT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ - uint8_t RESERVED_0[220]; - __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ - __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ - uint8_t RESERVED_1[24]; - struct { /* offset: 0x100, array step: 0x10 */ - __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ - __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ - __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ - __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ - } CHANNEL[4]; -} PIT_Type; - -/* ---------------------------------------------------------------------------- - -- PIT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PIT_Register_Masks PIT Register Masks - * @{ - */ - -/*! @name MCR - PIT Module Control Register */ -/*! @{ */ -#define PIT_MCR_FRZ_MASK (0x1U) -#define PIT_MCR_FRZ_SHIFT (0U) -#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) -#define PIT_MCR_MDIS_MASK (0x2U) -#define PIT_MCR_MDIS_SHIFT (1U) -#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) -/*! @} */ - -/*! @name LTMR64H - PIT Upper Lifetime Timer Register */ -/*! @{ */ -#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) -#define PIT_LTMR64H_LTH_SHIFT (0U) -#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) -/*! @} */ - -/*! @name LTMR64L - PIT Lower Lifetime Timer Register */ -/*! @{ */ -#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) -#define PIT_LTMR64L_LTL_SHIFT (0U) -#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) -/*! @} */ - -/*! @name LDVAL - Timer Load Value Register */ -/*! @{ */ -#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) -#define PIT_LDVAL_TSV_SHIFT (0U) -#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) -/*! @} */ - -/* The count of PIT_LDVAL */ -#define PIT_LDVAL_COUNT (4U) - -/*! @name CVAL - Current Timer Value Register */ -/*! @{ */ -#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) -#define PIT_CVAL_TVL_SHIFT (0U) -#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) -/*! @} */ - -/* The count of PIT_CVAL */ -#define PIT_CVAL_COUNT (4U) - -/*! @name TCTRL - Timer Control Register */ -/*! @{ */ -#define PIT_TCTRL_TEN_MASK (0x1U) -#define PIT_TCTRL_TEN_SHIFT (0U) -#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) -#define PIT_TCTRL_TIE_MASK (0x2U) -#define PIT_TCTRL_TIE_SHIFT (1U) -#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) -#define PIT_TCTRL_CHN_MASK (0x4U) -#define PIT_TCTRL_CHN_SHIFT (2U) -#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) -/*! @} */ - -/* The count of PIT_TCTRL */ -#define PIT_TCTRL_COUNT (4U) - -/*! @name TFLG - Timer Flag Register */ -/*! @{ */ -#define PIT_TFLG_TIF_MASK (0x1U) -#define PIT_TFLG_TIF_SHIFT (0U) -#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) -/*! @} */ - -/* The count of PIT_TFLG */ -#define PIT_TFLG_COUNT (4U) - - -/*! - * @} - */ /* end of group PIT_Register_Masks */ - - -/* PIT - Peripheral instance base addresses */ -/** Peripheral PIT base address */ -#define PIT_BASE (0x40084000u) -/** Peripheral PIT base pointer */ -#define PIT ((PIT_Type *)PIT_BASE) -/** Array initializer of PIT peripheral base addresses */ -#define PIT_BASE_ADDRS { PIT_BASE } -/** Array initializer of PIT peripheral base pointers */ -#define PIT_BASE_PTRS { PIT } -/** Interrupt vectors for the PIT peripheral type */ -#define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } } - -/*! - * @} - */ /* end of group PIT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PMU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer - * @{ - */ - -/** PMU - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[272]; - __IO uint32_t REG_1P1; /**< Regulator 1P1 Register, offset: 0x110 */ - __IO uint32_t REG_1P1_SET; /**< Regulator 1P1 Register, offset: 0x114 */ - __IO uint32_t REG_1P1_CLR; /**< Regulator 1P1 Register, offset: 0x118 */ - __IO uint32_t REG_1P1_TOG; /**< Regulator 1P1 Register, offset: 0x11C */ - __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ - __IO uint32_t REG_3P0_SET; /**< Regulator 3P0 Register, offset: 0x124 */ - __IO uint32_t REG_3P0_CLR; /**< Regulator 3P0 Register, offset: 0x128 */ - __IO uint32_t REG_3P0_TOG; /**< Regulator 3P0 Register, offset: 0x12C */ - __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ - __IO uint32_t REG_2P5_SET; /**< Regulator 2P5 Register, offset: 0x134 */ - __IO uint32_t REG_2P5_CLR; /**< Regulator 2P5 Register, offset: 0x138 */ - __IO uint32_t REG_2P5_TOG; /**< Regulator 2P5 Register, offset: 0x13C */ - __IO uint32_t REG_CORE; /**< Digital Regulator Core Register, offset: 0x140 */ - __IO uint32_t REG_CORE_SET; /**< Digital Regulator Core Register, offset: 0x144 */ - __IO uint32_t REG_CORE_CLR; /**< Digital Regulator Core Register, offset: 0x148 */ - __IO uint32_t REG_CORE_TOG; /**< Digital Regulator Core Register, offset: 0x14C */ - __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ - __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ - __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ - __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ - __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ - __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ - __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ - __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ - __IO uint32_t MISC2; /**< Miscellaneous Control Register, offset: 0x170 */ - __IO uint32_t MISC2_SET; /**< Miscellaneous Control Register, offset: 0x174 */ - __IO uint32_t MISC2_CLR; /**< Miscellaneous Control Register, offset: 0x178 */ - __IO uint32_t MISC2_TOG; /**< Miscellaneous Control Register, offset: 0x17C */ -} PMU_Type; - -/* ---------------------------------------------------------------------------- - -- PMU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PMU_Register_Masks PMU Register Masks - * @{ - */ - -/*! @name REG_1P1 - Regulator 1P1 Register */ -/*! @{ */ -#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U) -#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U) -#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK) -#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U) -#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U) -#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK) -#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) -#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U) -#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK) -#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U) -#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U) -#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK) -#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U) -#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U) -#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK) -#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U) -#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U) -#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK) -#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U) -#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U) -#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK) -#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U) -#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U) -#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK) -#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U) -#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U) -#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK) -#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U) -#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U) -#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) -/*! @} */ - -/*! @name REG_1P1_SET - Regulator 1P1 Register */ -/*! @{ */ -#define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U) -#define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U) -#define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK) -#define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U) -#define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U) -#define PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK) -#define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U) -#define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U) -#define PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK) -#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U) -#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U) -#define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK) -#define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U) -#define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U) -#define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK) -#define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U) -#define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U) -#define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK) -#define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U) -#define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U) -#define PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK) -#define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U) -#define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U) -#define PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK) -#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) -#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U) -#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK) -#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U) -#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U) -#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK) -/*! @} */ - -/*! @name REG_1P1_CLR - Regulator 1P1 Register */ -/*! @{ */ -#define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U) -#define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U) -#define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK) -#define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U) -#define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U) -#define PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK) -#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U) -#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U) -#define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK) -#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U) -#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U) -#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK) -#define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U) -#define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U) -#define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK) -#define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U) -#define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U) -#define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK) -#define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U) -#define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U) -#define PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK) -#define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U) -#define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U) -#define PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK) -#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) -#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) -#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK) -#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U) -#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U) -#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK) -/*! @} */ - -/*! @name REG_1P1_TOG - Regulator 1P1 Register */ -/*! @{ */ -#define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U) -#define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U) -#define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK) -#define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U) -#define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U) -#define PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK) -#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U) -#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U) -#define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK) -#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U) -#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U) -#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK) -#define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U) -#define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U) -#define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK) -#define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U) -#define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U) -#define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK) -#define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U) -#define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U) -#define PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK) -#define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U) -#define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U) -#define PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK) -#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) -#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) -#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK) -#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U) -#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U) -#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK) -/*! @} */ - -/*! @name REG_3P0 - Regulator 3P0 Register */ -/*! @{ */ -#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) -#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U) -#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK) -#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U) -#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U) -#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK) -#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) -#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U) -#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK) -#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U) -#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U) -#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK) -#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U) -#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U) -#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK) -#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U) -#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U) -#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK) -#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U) -#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U) -#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK) -#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U) -#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U) -#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK) -/*! @} */ - -/*! @name REG_3P0_SET - Regulator 3P0 Register */ -/*! @{ */ -#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U) -#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U) -#define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK) -#define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U) -#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U) -#define PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK) -#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U) -#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U) -#define PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK) -#define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U) -#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U) -#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK) -#define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U) -#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U) -#define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK) -#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U) -#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U) -#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK) -#define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U) -#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U) -#define PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK) -#define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U) -#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U) -#define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK) -/*! @} */ - -/*! @name REG_3P0_CLR - Regulator 3P0 Register */ -/*! @{ */ -#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U) -#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U) -#define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK) -#define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U) -#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U) -#define PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK) -#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U) -#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U) -#define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK) -#define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U) -#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U) -#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK) -#define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U) -#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U) -#define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK) -#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U) -#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U) -#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) -#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U) -#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U) -#define PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK) -#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U) -#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U) -#define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK) -/*! @} */ - -/*! @name REG_3P0_TOG - Regulator 3P0 Register */ -/*! @{ */ -#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U) -#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U) -#define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK) -#define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U) -#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U) -#define PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK) -#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U) -#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U) -#define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK) -#define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U) -#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U) -#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK) -#define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U) -#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U) -#define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK) -#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U) -#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U) -#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) -#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U) -#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U) -#define PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK) -#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U) -#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U) -#define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK) -/*! @} */ - -/*! @name REG_2P5 - Regulator 2P5 Register */ -/*! @{ */ -#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U) -#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U) -#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK) -#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U) -#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U) -#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK) -#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) -#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U) -#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK) -#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U) -#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U) -#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK) -#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U) -#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U) -#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK) -#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) -#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U) -#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK) -#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U) -#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U) -#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK) -#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U) -#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U) -#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK) -#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U) -#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U) -#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK) -/*! @} */ - -/*! @name REG_2P5_SET - Regulator 2P5 Register */ -/*! @{ */ -#define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U) -#define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U) -#define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK) -#define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U) -#define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U) -#define PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK) -#define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U) -#define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U) -#define PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK) -#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U) -#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U) -#define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK) -#define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U) -#define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U) -#define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK) -#define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U) -#define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U) -#define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK) -#define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U) -#define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U) -#define PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK) -#define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U) -#define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U) -#define PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK) -#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) -#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U) -#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK) -/*! @} */ - -/*! @name REG_2P5_CLR - Regulator 2P5 Register */ -/*! @{ */ -#define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U) -#define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U) -#define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK) -#define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U) -#define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U) -#define PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK) -#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U) -#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U) -#define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK) -#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U) -#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U) -#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK) -#define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U) -#define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U) -#define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK) -#define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U) -#define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U) -#define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK) -#define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U) -#define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U) -#define PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK) -#define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U) -#define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U) -#define PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK) -#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) -#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) -#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK) -/*! @} */ - -/*! @name REG_2P5_TOG - Regulator 2P5 Register */ -/*! @{ */ -#define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U) -#define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U) -#define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK) -#define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U) -#define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U) -#define PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK) -#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U) -#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U) -#define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK) -#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U) -#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U) -#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK) -#define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U) -#define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U) -#define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK) -#define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U) -#define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U) -#define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK) -#define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U) -#define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U) -#define PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK) -#define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U) -#define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U) -#define PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK) -#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) -#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) -#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK) -/*! @} */ - -/*! @name REG_CORE - Digital Regulator Core Register */ -/*! @{ */ -#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU) -#define PMU_REG_CORE_REG0_TARG_SHIFT (0U) -#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK) -#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U) -#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U) -#define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK) -#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U) -#define PMU_REG_CORE_REG1_TARG_SHIFT (9U) -#define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK) -#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U) -#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U) -#define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK) -#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U) -#define PMU_REG_CORE_REG2_TARG_SHIFT (18U) -#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK) -#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U) -#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U) -#define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK) -#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U) -#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U) -#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK) -#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U) -#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U) -#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK) -/*! @} */ - -/*! @name REG_CORE_SET - Digital Regulator Core Register */ -/*! @{ */ -#define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU) -#define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U) -#define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK) -#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U) -#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U) -#define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK) -#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U) -#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U) -#define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK) -#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U) -#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U) -#define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK) -#define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U) -#define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U) -#define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK) -#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U) -#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U) -#define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK) -#define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U) -#define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U) -#define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK) -#define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U) -#define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U) -#define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK) -/*! @} */ - -/*! @name REG_CORE_CLR - Digital Regulator Core Register */ -/*! @{ */ -#define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU) -#define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U) -#define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK) -#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U) -#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U) -#define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK) -#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U) -#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U) -#define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK) -#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U) -#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U) -#define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK) -#define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U) -#define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U) -#define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK) -#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U) -#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U) -#define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK) -#define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U) -#define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U) -#define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK) -#define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U) -#define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U) -#define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK) -/*! @} */ - -/*! @name REG_CORE_TOG - Digital Regulator Core Register */ -/*! @{ */ -#define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU) -#define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U) -#define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK) -#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U) -#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U) -#define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK) -#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U) -#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U) -#define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK) -#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U) -#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U) -#define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK) -#define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U) -#define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U) -#define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK) -#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U) -#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U) -#define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK) -#define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U) -#define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U) -#define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK) -#define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U) -#define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U) -#define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK) -/*! @} */ - -/*! @name MISC0 - Miscellaneous Register 0 */ -/*! @{ */ -#define PMU_MISC0_REFTOP_PWD_MASK (0x1U) -#define PMU_MISC0_REFTOP_PWD_SHIFT (0U) -#define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK) -#define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) -#define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) -#define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK) -#define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U) -#define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U) -#define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK) -#define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U) -#define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U) -#define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK) -#define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) -#define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U) -#define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK) -#define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) -#define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) -#define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK) -#define PMU_MISC0_OSC_I_MASK (0x6000U) -#define PMU_MISC0_OSC_I_SHIFT (13U) -#define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK) -#define PMU_MISC0_OSC_XTALOK_MASK (0x8000U) -#define PMU_MISC0_OSC_XTALOK_SHIFT (15U) -#define PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK) -#define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U) -#define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U) -#define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK) -#define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U) -#define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U) -#define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK) -#define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) -#define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U) -#define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK) -#define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) -#define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) -#define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK) -#define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U) -#define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U) -#define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK) -#define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) -#define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U) -#define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK) -/*! @} */ - -/*! @name MISC0_SET - Miscellaneous Register 0 */ -/*! @{ */ -#define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U) -#define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U) -#define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK) -#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) -#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) -#define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK) -#define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) -#define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) -#define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK) -#define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) -#define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) -#define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK) -#define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) -#define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) -#define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK) -#define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) -#define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) -#define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK) -#define PMU_MISC0_SET_OSC_I_MASK (0x6000U) -#define PMU_MISC0_SET_OSC_I_SHIFT (13U) -#define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK) -#define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U) -#define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U) -#define PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK) -#define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) -#define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) -#define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK) -#define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) -#define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) -#define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK) -#define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) -#define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) -#define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK) -#define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) -#define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) -#define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK) -#define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) -#define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) -#define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK) -#define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) -#define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) -#define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK) -/*! @} */ - -/*! @name MISC0_CLR - Miscellaneous Register 0 */ -/*! @{ */ -#define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U) -#define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U) -#define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK) -#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) -#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) -#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) -#define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) -#define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) -#define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK) -#define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) -#define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) -#define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK) -#define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) -#define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) -#define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK) -#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) -#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) -#define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK) -#define PMU_MISC0_CLR_OSC_I_MASK (0x6000U) -#define PMU_MISC0_CLR_OSC_I_SHIFT (13U) -#define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK) -#define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) -#define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U) -#define PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK) -#define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) -#define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) -#define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK) -#define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) -#define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) -#define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK) -#define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) -#define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) -#define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK) -#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) -#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) -#define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK) -#define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) -#define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) -#define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK) -#define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) -#define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) -#define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK) -/*! @} */ - -/*! @name MISC0_TOG - Miscellaneous Register 0 */ -/*! @{ */ -#define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U) -#define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U) -#define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK) -#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) -#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) -#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) -#define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) -#define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) -#define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK) -#define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) -#define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) -#define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK) -#define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) -#define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) -#define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK) -#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) -#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) -#define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK) -#define PMU_MISC0_TOG_OSC_I_MASK (0x6000U) -#define PMU_MISC0_TOG_OSC_I_SHIFT (13U) -#define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK) -#define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) -#define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U) -#define PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK) -#define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) -#define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) -#define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK) -#define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) -#define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) -#define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK) -#define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) -#define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) -#define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK) -#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) -#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) -#define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK) -#define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) -#define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) -#define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK) -#define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) -#define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) -#define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK) -/*! @} */ - -/*! @name MISC1 - Miscellaneous Register 1 */ -/*! @{ */ -#define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) -#define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U) -#define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK) -#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) -#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U) -#define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK) -#define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U) -#define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U) -#define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK) -#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U) -#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U) -#define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK) -#define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) -#define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U) -#define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK) -#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) -#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U) -#define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK) -#define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) -#define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) -#define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK) -#define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) -#define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) -#define PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK) -#define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) -#define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U) -#define PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK) -#define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) -#define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U) -#define PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK) -#define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) -#define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U) -#define PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK) -#define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U) -#define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U) -#define PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK) -#define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U) -#define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U) -#define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK) -/*! @} */ - -/*! @name MISC1_SET - Miscellaneous Register 1 */ -/*! @{ */ -#define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) -#define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) -#define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK) -#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) -#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U) -#define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK) -#define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) -#define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) -#define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK) -#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U) -#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U) -#define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK) -#define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) -#define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) -#define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK) -#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U) -#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U) -#define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK) -#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) -#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) -#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) -#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) -#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) -#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) -#define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) -#define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) -#define PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK) -#define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) -#define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) -#define PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK) -#define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) -#define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) -#define PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK) -#define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) -#define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) -#define PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK) -#define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) -#define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) -#define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK) -/*! @} */ - -/*! @name MISC1_CLR - Miscellaneous Register 1 */ -/*! @{ */ -#define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) -#define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) -#define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK) -#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U) -#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U) -#define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK) -#define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) -#define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) -#define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK) -#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U) -#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U) -#define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK) -#define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) -#define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) -#define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK) -#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U) -#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U) -#define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK) -#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) -#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) -#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) -#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) -#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) -#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) -#define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) -#define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) -#define PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK) -#define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) -#define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) -#define PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK) -#define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) -#define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) -#define PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK) -#define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) -#define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) -#define PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK) -#define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) -#define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) -#define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK) -/*! @} */ - -/*! @name MISC1_TOG - Miscellaneous Register 1 */ -/*! @{ */ -#define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) -#define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) -#define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK) -#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U) -#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U) -#define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK) -#define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) -#define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) -#define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK) -#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U) -#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U) -#define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK) -#define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) -#define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) -#define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK) -#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U) -#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U) -#define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK) -#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) -#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) -#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) -#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) -#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) -#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) -#define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) -#define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) -#define PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK) -#define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) -#define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) -#define PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK) -#define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) -#define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) -#define PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK) -#define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) -#define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) -#define PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK) -#define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) -#define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) -#define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK) -/*! @} */ - -/*! @name MISC2 - Miscellaneous Control Register */ -/*! @{ */ -#define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U) -#define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U) -#define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK) -#define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U) -#define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U) -#define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK) -#define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U) -#define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U) -#define PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK) -#define PMU_MISC2_PLL3_disable_MASK (0x80U) -#define PMU_MISC2_PLL3_disable_SHIFT (7U) -#define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK) -#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U) -#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U) -#define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK) -#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U) -#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U) -#define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK) -#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U) -#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U) -#define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK) -#define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) -#define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U) -#define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK) -#define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) -#define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U) -#define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK) -#define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U) -#define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U) -#define PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK) -#define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U) -#define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U) -#define PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK) -#define PMU_MISC2_REG2_OK_MASK (0x400000U) -#define PMU_MISC2_REG2_OK_SHIFT (22U) -#define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK) -#define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) -#define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U) -#define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK) -#define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U) -#define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U) -#define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK) -#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U) -#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U) -#define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK) -#define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U) -#define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U) -#define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK) -#define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U) -#define PMU_MISC2_VIDEO_DIV_SHIFT (30U) -#define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK) -/*! @} */ - -/*! @name MISC2_SET - Miscellaneous Control Register */ -/*! @{ */ -#define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) -#define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) -#define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK) -#define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) -#define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) -#define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK) -#define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) -#define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) -#define PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK) -#define PMU_MISC2_SET_PLL3_disable_MASK (0x80U) -#define PMU_MISC2_SET_PLL3_disable_SHIFT (7U) -#define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK) -#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) -#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) -#define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK) -#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) -#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) -#define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK) -#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) -#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) -#define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK) -#define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) -#define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) -#define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK) -#define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) -#define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) -#define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK) -#define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) -#define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) -#define PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK) -#define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) -#define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) -#define PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK) -#define PMU_MISC2_SET_REG2_OK_MASK (0x400000U) -#define PMU_MISC2_SET_REG2_OK_SHIFT (22U) -#define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK) -#define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) -#define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) -#define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK) -#define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) -#define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) -#define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK) -#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) -#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) -#define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK) -#define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) -#define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) -#define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK) -#define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) -#define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U) -#define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK) -/*! @} */ - -/*! @name MISC2_CLR - Miscellaneous Control Register */ -/*! @{ */ -#define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) -#define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) -#define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK) -#define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) -#define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) -#define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK) -#define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) -#define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) -#define PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK) -#define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U) -#define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U) -#define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK) -#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) -#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) -#define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK) -#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) -#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) -#define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK) -#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) -#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) -#define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK) -#define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) -#define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) -#define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK) -#define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) -#define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) -#define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK) -#define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) -#define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) -#define PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK) -#define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) -#define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) -#define PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK) -#define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U) -#define PMU_MISC2_CLR_REG2_OK_SHIFT (22U) -#define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK) -#define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) -#define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) -#define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK) -#define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) -#define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) -#define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK) -#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) -#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) -#define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK) -#define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) -#define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) -#define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK) -#define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) -#define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U) -#define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK) -/*! @} */ - -/*! @name MISC2_TOG - Miscellaneous Control Register */ -/*! @{ */ -#define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) -#define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) -#define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK) -#define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) -#define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) -#define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK) -#define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) -#define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) -#define PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK) -#define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U) -#define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U) -#define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK) -#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) -#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) -#define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK) -#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) -#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) -#define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK) -#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) -#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) -#define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK) -#define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) -#define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) -#define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK) -#define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) -#define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) -#define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK) -#define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) -#define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) -#define PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK) -#define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) -#define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) -#define PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK) -#define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U) -#define PMU_MISC2_TOG_REG2_OK_SHIFT (22U) -#define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK) -#define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) -#define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) -#define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK) -#define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) -#define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) -#define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK) -#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) -#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) -#define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK) -#define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) -#define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) -#define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK) -#define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) -#define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U) -#define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PMU_Register_Masks */ - - -/* PMU - Peripheral instance base addresses */ -/** Peripheral PMU base address */ -#define PMU_BASE (0x400D8000u) -/** Peripheral PMU base pointer */ -#define PMU ((PMU_Type *)PMU_BASE) -/** Array initializer of PMU peripheral base addresses */ -#define PMU_BASE_ADDRS { PMU_BASE } -/** Array initializer of PMU peripheral base pointers */ -#define PMU_BASE_PTRS { PMU } - -/*! - * @} - */ /* end of group PMU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PWM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer - * @{ - */ - -/** PWM - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x60 */ - __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ - __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ - __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ - __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ - uint8_t RESERVED_0[2]; - __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ - __IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */ - __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ - __IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */ - __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ - __IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */ - __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ - __IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */ - __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ - __IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */ - __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ - __IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */ - __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ - __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ - __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ - __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ - __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ - __IO uint16_t DISMAP[2]; /**< Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2 */ - __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ - __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ - __IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */ - __IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */ - __IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */ - __IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */ - __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ - __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ - __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ - __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ - __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ - __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ - __I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */ - __I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */ - __I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */ - __I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */ - __I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */ - __I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */ - __I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */ - __I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */ - uint8_t RESERVED_1[8]; - } SM[4]; - __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ - __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ - __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ - __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ - __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ - __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ - __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ - __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ - __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ - __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ - __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ -} PWM_Type; - -/* ---------------------------------------------------------------------------- - -- PWM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PWM_Register_Masks PWM Register Masks - * @{ - */ - -/*! @name CNT - Counter Register */ -/*! @{ */ -#define PWM_CNT_CNT_MASK (0xFFFFU) -#define PWM_CNT_CNT_SHIFT (0U) -#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) -/*! @} */ - -/* The count of PWM_CNT */ -#define PWM_CNT_COUNT (4U) - -/*! @name INIT - Initial Count Register */ -/*! @{ */ -#define PWM_INIT_INIT_MASK (0xFFFFU) -#define PWM_INIT_INIT_SHIFT (0U) -#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) -/*! @} */ - -/* The count of PWM_INIT */ -#define PWM_INIT_COUNT (4U) - -/*! @name CTRL2 - Control 2 Register */ -/*! @{ */ -#define PWM_CTRL2_CLK_SEL_MASK (0x3U) -#define PWM_CTRL2_CLK_SEL_SHIFT (0U) -#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) -#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) -#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) -#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) -#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) -#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) -#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) -#define PWM_CTRL2_FORCE_MASK (0x40U) -#define PWM_CTRL2_FORCE_SHIFT (6U) -#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) -#define PWM_CTRL2_FRCEN_MASK (0x80U) -#define PWM_CTRL2_FRCEN_SHIFT (7U) -#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) -#define PWM_CTRL2_INIT_SEL_MASK (0x300U) -#define PWM_CTRL2_INIT_SEL_SHIFT (8U) -#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) -#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) -#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) -#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) -#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) -#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) -#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) -#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) -#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) -#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) -#define PWM_CTRL2_INDEP_MASK (0x2000U) -#define PWM_CTRL2_INDEP_SHIFT (13U) -#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) -#define PWM_CTRL2_WAITEN_MASK (0x4000U) -#define PWM_CTRL2_WAITEN_SHIFT (14U) -#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK) -#define PWM_CTRL2_DBGEN_MASK (0x8000U) -#define PWM_CTRL2_DBGEN_SHIFT (15U) -#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) -/*! @} */ - -/* The count of PWM_CTRL2 */ -#define PWM_CTRL2_COUNT (4U) - -/*! @name CTRL - Control Register */ -/*! @{ */ -#define PWM_CTRL_DBLEN_MASK (0x1U) -#define PWM_CTRL_DBLEN_SHIFT (0U) -#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) -#define PWM_CTRL_DBLX_MASK (0x2U) -#define PWM_CTRL_DBLX_SHIFT (1U) -#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) -#define PWM_CTRL_LDMOD_MASK (0x4U) -#define PWM_CTRL_LDMOD_SHIFT (2U) -#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) -#define PWM_CTRL_SPLIT_MASK (0x8U) -#define PWM_CTRL_SPLIT_SHIFT (3U) -#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) -#define PWM_CTRL_PRSC_MASK (0x70U) -#define PWM_CTRL_PRSC_SHIFT (4U) -#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) -#define PWM_CTRL_COMPMODE_MASK (0x80U) -#define PWM_CTRL_COMPMODE_SHIFT (7U) -#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) -#define PWM_CTRL_DT_MASK (0x300U) -#define PWM_CTRL_DT_SHIFT (8U) -#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) -#define PWM_CTRL_FULL_MASK (0x400U) -#define PWM_CTRL_FULL_SHIFT (10U) -#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) -#define PWM_CTRL_HALF_MASK (0x800U) -#define PWM_CTRL_HALF_SHIFT (11U) -#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) -#define PWM_CTRL_LDFQ_MASK (0xF000U) -#define PWM_CTRL_LDFQ_SHIFT (12U) -#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) -/*! @} */ - -/* The count of PWM_CTRL */ -#define PWM_CTRL_COUNT (4U) - -/*! @name VAL0 - Value Register 0 */ -/*! @{ */ -#define PWM_VAL0_VAL0_MASK (0xFFFFU) -#define PWM_VAL0_VAL0_SHIFT (0U) -#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) -/*! @} */ - -/* The count of PWM_VAL0 */ -#define PWM_VAL0_COUNT (4U) - -/*! @name FRACVAL1 - Fractional Value Register 1 */ -/*! @{ */ -#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) -#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) -#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) -/*! @} */ - -/* The count of PWM_FRACVAL1 */ -#define PWM_FRACVAL1_COUNT (4U) - -/*! @name VAL1 - Value Register 1 */ -/*! @{ */ -#define PWM_VAL1_VAL1_MASK (0xFFFFU) -#define PWM_VAL1_VAL1_SHIFT (0U) -#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) -/*! @} */ - -/* The count of PWM_VAL1 */ -#define PWM_VAL1_COUNT (4U) - -/*! @name FRACVAL2 - Fractional Value Register 2 */ -/*! @{ */ -#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) -#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) -#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) -/*! @} */ - -/* The count of PWM_FRACVAL2 */ -#define PWM_FRACVAL2_COUNT (4U) - -/*! @name VAL2 - Value Register 2 */ -/*! @{ */ -#define PWM_VAL2_VAL2_MASK (0xFFFFU) -#define PWM_VAL2_VAL2_SHIFT (0U) -#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) -/*! @} */ - -/* The count of PWM_VAL2 */ -#define PWM_VAL2_COUNT (4U) - -/*! @name FRACVAL3 - Fractional Value Register 3 */ -/*! @{ */ -#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) -#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) -#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) -/*! @} */ - -/* The count of PWM_FRACVAL3 */ -#define PWM_FRACVAL3_COUNT (4U) - -/*! @name VAL3 - Value Register 3 */ -/*! @{ */ -#define PWM_VAL3_VAL3_MASK (0xFFFFU) -#define PWM_VAL3_VAL3_SHIFT (0U) -#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) -/*! @} */ - -/* The count of PWM_VAL3 */ -#define PWM_VAL3_COUNT (4U) - -/*! @name FRACVAL4 - Fractional Value Register 4 */ -/*! @{ */ -#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) -#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) -#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) -/*! @} */ - -/* The count of PWM_FRACVAL4 */ -#define PWM_FRACVAL4_COUNT (4U) - -/*! @name VAL4 - Value Register 4 */ -/*! @{ */ -#define PWM_VAL4_VAL4_MASK (0xFFFFU) -#define PWM_VAL4_VAL4_SHIFT (0U) -#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) -/*! @} */ - -/* The count of PWM_VAL4 */ -#define PWM_VAL4_COUNT (4U) - -/*! @name FRACVAL5 - Fractional Value Register 5 */ -/*! @{ */ -#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) -#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) -#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) -/*! @} */ - -/* The count of PWM_FRACVAL5 */ -#define PWM_FRACVAL5_COUNT (4U) - -/*! @name VAL5 - Value Register 5 */ -/*! @{ */ -#define PWM_VAL5_VAL5_MASK (0xFFFFU) -#define PWM_VAL5_VAL5_SHIFT (0U) -#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) -/*! @} */ - -/* The count of PWM_VAL5 */ -#define PWM_VAL5_COUNT (4U) - -/*! @name FRCTRL - Fractional Control Register */ -/*! @{ */ -#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) -#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) -#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) -#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) -#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) -#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) -#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) -#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) -#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) -#define PWM_FRCTRL_FRAC_PU_MASK (0x100U) -#define PWM_FRCTRL_FRAC_PU_SHIFT (8U) -#define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK) -#define PWM_FRCTRL_TEST_MASK (0x8000U) -#define PWM_FRCTRL_TEST_SHIFT (15U) -#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) -/*! @} */ - -/* The count of PWM_FRCTRL */ -#define PWM_FRCTRL_COUNT (4U) - -/*! @name OCTRL - Output Control Register */ -/*! @{ */ -#define PWM_OCTRL_PWMXFS_MASK (0x3U) -#define PWM_OCTRL_PWMXFS_SHIFT (0U) -#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) -#define PWM_OCTRL_PWMBFS_MASK (0xCU) -#define PWM_OCTRL_PWMBFS_SHIFT (2U) -#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) -#define PWM_OCTRL_PWMAFS_MASK (0x30U) -#define PWM_OCTRL_PWMAFS_SHIFT (4U) -#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) -#define PWM_OCTRL_POLX_MASK (0x100U) -#define PWM_OCTRL_POLX_SHIFT (8U) -#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) -#define PWM_OCTRL_POLB_MASK (0x200U) -#define PWM_OCTRL_POLB_SHIFT (9U) -#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) -#define PWM_OCTRL_POLA_MASK (0x400U) -#define PWM_OCTRL_POLA_SHIFT (10U) -#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) -#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) -#define PWM_OCTRL_PWMX_IN_SHIFT (13U) -#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) -#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) -#define PWM_OCTRL_PWMB_IN_SHIFT (14U) -#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) -#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) -#define PWM_OCTRL_PWMA_IN_SHIFT (15U) -#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) -/*! @} */ - -/* The count of PWM_OCTRL */ -#define PWM_OCTRL_COUNT (4U) - -/*! @name STS - Status Register */ -/*! @{ */ -#define PWM_STS_CMPF_MASK (0x3FU) -#define PWM_STS_CMPF_SHIFT (0U) -#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) -#define PWM_STS_CFX0_MASK (0x40U) -#define PWM_STS_CFX0_SHIFT (6U) -#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) -#define PWM_STS_CFX1_MASK (0x80U) -#define PWM_STS_CFX1_SHIFT (7U) -#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) -#define PWM_STS_CFB0_MASK (0x100U) -#define PWM_STS_CFB0_SHIFT (8U) -#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) -#define PWM_STS_CFB1_MASK (0x200U) -#define PWM_STS_CFB1_SHIFT (9U) -#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) -#define PWM_STS_CFA0_MASK (0x400U) -#define PWM_STS_CFA0_SHIFT (10U) -#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) -#define PWM_STS_CFA1_MASK (0x800U) -#define PWM_STS_CFA1_SHIFT (11U) -#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) -#define PWM_STS_RF_MASK (0x1000U) -#define PWM_STS_RF_SHIFT (12U) -#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) -#define PWM_STS_REF_MASK (0x2000U) -#define PWM_STS_REF_SHIFT (13U) -#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) -#define PWM_STS_RUF_MASK (0x4000U) -#define PWM_STS_RUF_SHIFT (14U) -#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) -/*! @} */ - -/* The count of PWM_STS */ -#define PWM_STS_COUNT (4U) - -/*! @name INTEN - Interrupt Enable Register */ -/*! @{ */ -#define PWM_INTEN_CMPIE_MASK (0x3FU) -#define PWM_INTEN_CMPIE_SHIFT (0U) -#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) -#define PWM_INTEN_CX0IE_MASK (0x40U) -#define PWM_INTEN_CX0IE_SHIFT (6U) -#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) -#define PWM_INTEN_CX1IE_MASK (0x80U) -#define PWM_INTEN_CX1IE_SHIFT (7U) -#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) -#define PWM_INTEN_CB0IE_MASK (0x100U) -#define PWM_INTEN_CB0IE_SHIFT (8U) -#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) -#define PWM_INTEN_CB1IE_MASK (0x200U) -#define PWM_INTEN_CB1IE_SHIFT (9U) -#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) -#define PWM_INTEN_CA0IE_MASK (0x400U) -#define PWM_INTEN_CA0IE_SHIFT (10U) -#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) -#define PWM_INTEN_CA1IE_MASK (0x800U) -#define PWM_INTEN_CA1IE_SHIFT (11U) -#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) -#define PWM_INTEN_RIE_MASK (0x1000U) -#define PWM_INTEN_RIE_SHIFT (12U) -#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) -#define PWM_INTEN_REIE_MASK (0x2000U) -#define PWM_INTEN_REIE_SHIFT (13U) -#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) -/*! @} */ - -/* The count of PWM_INTEN */ -#define PWM_INTEN_COUNT (4U) - -/*! @name DMAEN - DMA Enable Register */ -/*! @{ */ -#define PWM_DMAEN_CX0DE_MASK (0x1U) -#define PWM_DMAEN_CX0DE_SHIFT (0U) -#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) -#define PWM_DMAEN_CX1DE_MASK (0x2U) -#define PWM_DMAEN_CX1DE_SHIFT (1U) -#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) -#define PWM_DMAEN_CB0DE_MASK (0x4U) -#define PWM_DMAEN_CB0DE_SHIFT (2U) -#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) -#define PWM_DMAEN_CB1DE_MASK (0x8U) -#define PWM_DMAEN_CB1DE_SHIFT (3U) -#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) -#define PWM_DMAEN_CA0DE_MASK (0x10U) -#define PWM_DMAEN_CA0DE_SHIFT (4U) -#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) -#define PWM_DMAEN_CA1DE_MASK (0x20U) -#define PWM_DMAEN_CA1DE_SHIFT (5U) -#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) -#define PWM_DMAEN_CAPTDE_MASK (0xC0U) -#define PWM_DMAEN_CAPTDE_SHIFT (6U) -#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) -#define PWM_DMAEN_FAND_MASK (0x100U) -#define PWM_DMAEN_FAND_SHIFT (8U) -#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) -#define PWM_DMAEN_VALDE_MASK (0x200U) -#define PWM_DMAEN_VALDE_SHIFT (9U) -#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) -/*! @} */ - -/* The count of PWM_DMAEN */ -#define PWM_DMAEN_COUNT (4U) - -/*! @name TCTRL - Output Trigger Control Register */ -/*! @{ */ -#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) -#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) -#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) -#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) -#define PWM_TCTRL_TRGFRQ_SHIFT (12U) -#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) -#define PWM_TCTRL_PWBOT1_MASK (0x4000U) -#define PWM_TCTRL_PWBOT1_SHIFT (14U) -#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) -#define PWM_TCTRL_PWAOT0_MASK (0x8000U) -#define PWM_TCTRL_PWAOT0_SHIFT (15U) -#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) -/*! @} */ - -/* The count of PWM_TCTRL */ -#define PWM_TCTRL_COUNT (4U) - -/*! @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */ -/*! @{ */ -#define PWM_DISMAP_DIS0A_MASK (0xFU) -#define PWM_DISMAP_DIS0A_SHIFT (0U) -#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) -#define PWM_DISMAP_DIS1A_MASK (0xFU) -#define PWM_DISMAP_DIS1A_SHIFT (0U) -#define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK) -#define PWM_DISMAP_DIS0B_MASK (0xF0U) -#define PWM_DISMAP_DIS0B_SHIFT (4U) -#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) -#define PWM_DISMAP_DIS1B_MASK (0xF0U) -#define PWM_DISMAP_DIS1B_SHIFT (4U) -#define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK) -#define PWM_DISMAP_DIS0X_MASK (0xF00U) -#define PWM_DISMAP_DIS0X_SHIFT (8U) -#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) -#define PWM_DISMAP_DIS1X_MASK (0xF00U) -#define PWM_DISMAP_DIS1X_SHIFT (8U) -#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK) -/*! @} */ - -/* The count of PWM_DISMAP */ -#define PWM_DISMAP_COUNT (4U) - -/* The count of PWM_DISMAP */ -#define PWM_DISMAP_COUNT2 (2U) - -/*! @name DTCNT0 - Deadtime Count Register 0 */ -/*! @{ */ -#define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU) -#define PWM_DTCNT0_DTCNT0_SHIFT (0U) -#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) -/*! @} */ - -/* The count of PWM_DTCNT0 */ -#define PWM_DTCNT0_COUNT (4U) - -/*! @name DTCNT1 - Deadtime Count Register 1 */ -/*! @{ */ -#define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU) -#define PWM_DTCNT1_DTCNT1_SHIFT (0U) -#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) -/*! @} */ - -/* The count of PWM_DTCNT1 */ -#define PWM_DTCNT1_COUNT (4U) - -/*! @name CAPTCTRLA - Capture Control A Register */ -/*! @{ */ -#define PWM_CAPTCTRLA_ARMA_MASK (0x1U) -#define PWM_CAPTCTRLA_ARMA_SHIFT (0U) -#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) -#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) -#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) -#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) -#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) -#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) -#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) -#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) -#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) -#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) -#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) -#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) -#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) -#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) -#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) -#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) -#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) -#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) -#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) -#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) -#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) -#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) -#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) -#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) -#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) -/*! @} */ - -/* The count of PWM_CAPTCTRLA */ -#define PWM_CAPTCTRLA_COUNT (4U) - -/*! @name CAPTCOMPA - Capture Compare A Register */ -/*! @{ */ -#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) -#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) -#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) -#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) -#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) -#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) -/*! @} */ - -/* The count of PWM_CAPTCOMPA */ -#define PWM_CAPTCOMPA_COUNT (4U) - -/*! @name CAPTCTRLB - Capture Control B Register */ -/*! @{ */ -#define PWM_CAPTCTRLB_ARMB_MASK (0x1U) -#define PWM_CAPTCTRLB_ARMB_SHIFT (0U) -#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) -#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) -#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) -#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) -#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) -#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) -#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) -#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) -#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) -#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) -#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) -#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) -#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) -#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) -#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) -#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) -#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) -#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) -#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) -#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) -#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) -#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) -#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) -#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) -#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) -/*! @} */ - -/* The count of PWM_CAPTCTRLB */ -#define PWM_CAPTCTRLB_COUNT (4U) - -/*! @name CAPTCOMPB - Capture Compare B Register */ -/*! @{ */ -#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) -#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) -#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) -#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) -#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) -#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) -/*! @} */ - -/* The count of PWM_CAPTCOMPB */ -#define PWM_CAPTCOMPB_COUNT (4U) - -/*! @name CAPTCTRLX - Capture Control X Register */ -/*! @{ */ -#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) -#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) -#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) -#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) -#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) -#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) -#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) -#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) -#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) -#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) -#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) -#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) -#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) -#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) -#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) -#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) -#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) -#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) -#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) -#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) -#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) -#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) -#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) -#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) -#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) -#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) -#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) -/*! @} */ - -/* The count of PWM_CAPTCTRLX */ -#define PWM_CAPTCTRLX_COUNT (4U) - -/*! @name CAPTCOMPX - Capture Compare X Register */ -/*! @{ */ -#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) -#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) -#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) -#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) -#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) -#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) -/*! @} */ - -/* The count of PWM_CAPTCOMPX */ -#define PWM_CAPTCOMPX_COUNT (4U) - -/*! @name CVAL0 - Capture Value 0 Register */ -/*! @{ */ -#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) -#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) -#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) -/*! @} */ - -/* The count of PWM_CVAL0 */ -#define PWM_CVAL0_COUNT (4U) - -/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ -/*! @{ */ -#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) -#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) -#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) -/*! @} */ - -/* The count of PWM_CVAL0CYC */ -#define PWM_CVAL0CYC_COUNT (4U) - -/*! @name CVAL1 - Capture Value 1 Register */ -/*! @{ */ -#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) -#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) -#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) -/*! @} */ - -/* The count of PWM_CVAL1 */ -#define PWM_CVAL1_COUNT (4U) - -/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ -/*! @{ */ -#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) -#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) -#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) -/*! @} */ - -/* The count of PWM_CVAL1CYC */ -#define PWM_CVAL1CYC_COUNT (4U) - -/*! @name CVAL2 - Capture Value 2 Register */ -/*! @{ */ -#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) -#define PWM_CVAL2_CAPTVAL2_SHIFT (0U) -#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) -/*! @} */ - -/* The count of PWM_CVAL2 */ -#define PWM_CVAL2_COUNT (4U) - -/*! @name CVAL2CYC - Capture Value 2 Cycle Register */ -/*! @{ */ -#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) -#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) -#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) -/*! @} */ - -/* The count of PWM_CVAL2CYC */ -#define PWM_CVAL2CYC_COUNT (4U) - -/*! @name CVAL3 - Capture Value 3 Register */ -/*! @{ */ -#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) -#define PWM_CVAL3_CAPTVAL3_SHIFT (0U) -#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) -/*! @} */ - -/* The count of PWM_CVAL3 */ -#define PWM_CVAL3_COUNT (4U) - -/*! @name CVAL3CYC - Capture Value 3 Cycle Register */ -/*! @{ */ -#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) -#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) -#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) -/*! @} */ - -/* The count of PWM_CVAL3CYC */ -#define PWM_CVAL3CYC_COUNT (4U) - -/*! @name CVAL4 - Capture Value 4 Register */ -/*! @{ */ -#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) -#define PWM_CVAL4_CAPTVAL4_SHIFT (0U) -#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) -/*! @} */ - -/* The count of PWM_CVAL4 */ -#define PWM_CVAL4_COUNT (4U) - -/*! @name CVAL4CYC - Capture Value 4 Cycle Register */ -/*! @{ */ -#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) -#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) -#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) -/*! @} */ - -/* The count of PWM_CVAL4CYC */ -#define PWM_CVAL4CYC_COUNT (4U) - -/*! @name CVAL5 - Capture Value 5 Register */ -/*! @{ */ -#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) -#define PWM_CVAL5_CAPTVAL5_SHIFT (0U) -#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) -/*! @} */ - -/* The count of PWM_CVAL5 */ -#define PWM_CVAL5_COUNT (4U) - -/*! @name CVAL5CYC - Capture Value 5 Cycle Register */ -/*! @{ */ -#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) -#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) -#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) -/*! @} */ - -/* The count of PWM_CVAL5CYC */ -#define PWM_CVAL5CYC_COUNT (4U) - -/*! @name OUTEN - Output Enable Register */ -/*! @{ */ -#define PWM_OUTEN_PWMX_EN_MASK (0xFU) -#define PWM_OUTEN_PWMX_EN_SHIFT (0U) -#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) -#define PWM_OUTEN_PWMB_EN_MASK (0xF0U) -#define PWM_OUTEN_PWMB_EN_SHIFT (4U) -#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) -#define PWM_OUTEN_PWMA_EN_MASK (0xF00U) -#define PWM_OUTEN_PWMA_EN_SHIFT (8U) -#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) -/*! @} */ - -/*! @name MASK - Mask Register */ -/*! @{ */ -#define PWM_MASK_MASKX_MASK (0xFU) -#define PWM_MASK_MASKX_SHIFT (0U) -#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) -#define PWM_MASK_MASKB_MASK (0xF0U) -#define PWM_MASK_MASKB_SHIFT (4U) -#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) -#define PWM_MASK_MASKA_MASK (0xF00U) -#define PWM_MASK_MASKA_SHIFT (8U) -#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) -#define PWM_MASK_UPDATE_MASK_MASK (0xF000U) -#define PWM_MASK_UPDATE_MASK_SHIFT (12U) -#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) -/*! @} */ - -/*! @name SWCOUT - Software Controlled Output Register */ -/*! @{ */ -#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) -#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) -#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) -#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) -#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) -#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) -#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) -#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) -#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) -#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) -#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) -#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) -#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) -#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) -#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) -#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) -#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) -#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) -#define PWM_SWCOUT_SM3OUT45_MASK (0x40U) -#define PWM_SWCOUT_SM3OUT45_SHIFT (6U) -#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) -#define PWM_SWCOUT_SM3OUT23_MASK (0x80U) -#define PWM_SWCOUT_SM3OUT23_SHIFT (7U) -#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) -/*! @} */ - -/*! @name DTSRCSEL - PWM Source Select Register */ -/*! @{ */ -#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) -#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) -#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) -#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) -#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) -#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) -#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) -#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) -#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) -#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) -#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) -#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) -#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) -#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) -#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) -#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) -#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) -#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) -#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) -#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) -#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) -#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) -#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) -#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) -/*! @} */ - -/*! @name MCTRL - Master Control Register */ -/*! @{ */ -#define PWM_MCTRL_LDOK_MASK (0xFU) -#define PWM_MCTRL_LDOK_SHIFT (0U) -#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) -#define PWM_MCTRL_CLDOK_MASK (0xF0U) -#define PWM_MCTRL_CLDOK_SHIFT (4U) -#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) -#define PWM_MCTRL_RUN_MASK (0xF00U) -#define PWM_MCTRL_RUN_SHIFT (8U) -#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) -#define PWM_MCTRL_IPOL_MASK (0xF000U) -#define PWM_MCTRL_IPOL_SHIFT (12U) -#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) -/*! @} */ - -/*! @name MCTRL2 - Master Control 2 Register */ -/*! @{ */ -#define PWM_MCTRL2_MONPLL_MASK (0x3U) -#define PWM_MCTRL2_MONPLL_SHIFT (0U) -#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) -/*! @} */ - -/*! @name FCTRL - Fault Control Register */ -/*! @{ */ -#define PWM_FCTRL_FIE_MASK (0xFU) -#define PWM_FCTRL_FIE_SHIFT (0U) -#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) -#define PWM_FCTRL_FSAFE_MASK (0xF0U) -#define PWM_FCTRL_FSAFE_SHIFT (4U) -#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) -#define PWM_FCTRL_FAUTO_MASK (0xF00U) -#define PWM_FCTRL_FAUTO_SHIFT (8U) -#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) -#define PWM_FCTRL_FLVL_MASK (0xF000U) -#define PWM_FCTRL_FLVL_SHIFT (12U) -#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) -/*! @} */ - -/*! @name FSTS - Fault Status Register */ -/*! @{ */ -#define PWM_FSTS_FFLAG_MASK (0xFU) -#define PWM_FSTS_FFLAG_SHIFT (0U) -#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) -#define PWM_FSTS_FFULL_MASK (0xF0U) -#define PWM_FSTS_FFULL_SHIFT (4U) -#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) -#define PWM_FSTS_FFPIN_MASK (0xF00U) -#define PWM_FSTS_FFPIN_SHIFT (8U) -#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) -#define PWM_FSTS_FHALF_MASK (0xF000U) -#define PWM_FSTS_FHALF_SHIFT (12U) -#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) -/*! @} */ - -/*! @name FFILT - Fault Filter Register */ -/*! @{ */ -#define PWM_FFILT_FILT_PER_MASK (0xFFU) -#define PWM_FFILT_FILT_PER_SHIFT (0U) -#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) -#define PWM_FFILT_FILT_CNT_MASK (0x700U) -#define PWM_FFILT_FILT_CNT_SHIFT (8U) -#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) -#define PWM_FFILT_GSTR_MASK (0x8000U) -#define PWM_FFILT_GSTR_SHIFT (15U) -#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) -/*! @} */ - -/*! @name FTST - Fault Test Register */ -/*! @{ */ -#define PWM_FTST_FTEST_MASK (0x1U) -#define PWM_FTST_FTEST_SHIFT (0U) -#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) -/*! @} */ - -/*! @name FCTRL2 - Fault Control 2 Register */ -/*! @{ */ -#define PWM_FCTRL2_NOCOMB_MASK (0xFU) -#define PWM_FCTRL2_NOCOMB_SHIFT (0U) -#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PWM_Register_Masks */ - - -/* PWM - Peripheral instance base addresses */ -/** Peripheral PWM1 base address */ -#define PWM1_BASE (0x403DC000u) -/** Peripheral PWM1 base pointer */ -#define PWM1 ((PWM_Type *)PWM1_BASE) -/** Peripheral PWM2 base address */ -#define PWM2_BASE (0x403E0000u) -/** Peripheral PWM2 base pointer */ -#define PWM2 ((PWM_Type *)PWM2_BASE) -/** Peripheral PWM3 base address */ -#define PWM3_BASE (0x403E4000u) -/** Peripheral PWM3 base pointer */ -#define PWM3 ((PWM_Type *)PWM3_BASE) -/** Peripheral PWM4 base address */ -#define PWM4_BASE (0x403E8000u) -/** Peripheral PWM4 base pointer */ -#define PWM4 ((PWM_Type *)PWM4_BASE) -/** Array initializer of PWM peripheral base addresses */ -#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE } -/** Array initializer of PWM peripheral base pointers */ -#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 } -/** Interrupt vectors for the PWM peripheral type */ -#define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } -#define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } -#define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } -#define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn } -#define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn } - -/*! - * @} - */ /* end of group PWM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PXP Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer - * @{ - */ - -/** PXP - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */ - __IO uint32_t CTRL_SET; /**< Control Register 0, offset: 0x4 */ - __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ - __IO uint32_t CTRL_TOG; /**< Control Register 0, offset: 0xC */ - __IO uint32_t STAT; /**< Status Register, offset: 0x10 */ - __IO uint32_t STAT_SET; /**< Status Register, offset: 0x14 */ - __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ - __IO uint32_t STAT_TOG; /**< Status Register, offset: 0x1C */ - __IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */ - __IO uint32_t OUT_CTRL_SET; /**< Output Buffer Control Register, offset: 0x24 */ - __IO uint32_t OUT_CTRL_CLR; /**< Output Buffer Control Register, offset: 0x28 */ - __IO uint32_t OUT_CTRL_TOG; /**< Output Buffer Control Register, offset: 0x2C */ - __IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */ - uint8_t RESERVED_0[12]; - __IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */ - uint8_t RESERVED_1[12]; - __IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */ - uint8_t RESERVED_2[12]; - __IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */ - uint8_t RESERVED_3[12]; - __IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */ - uint8_t RESERVED_4[12]; - __IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */ - uint8_t RESERVED_5[12]; - __IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */ - uint8_t RESERVED_6[12]; - __IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */ - uint8_t RESERVED_7[12]; - __IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */ - __IO uint32_t PS_CTRL_SET; /**< Processed Surface (PS) Control Register, offset: 0xB4 */ - __IO uint32_t PS_CTRL_CLR; /**< Processed Surface (PS) Control Register, offset: 0xB8 */ - __IO uint32_t PS_CTRL_TOG; /**< Processed Surface (PS) Control Register, offset: 0xBC */ - __IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */ - uint8_t RESERVED_8[12]; - __IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */ - uint8_t RESERVED_9[12]; - __IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */ - uint8_t RESERVED_10[12]; - __IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */ - uint8_t RESERVED_11[12]; - __IO uint32_t PS_BACKGROUND; /**< PS Background Color, offset: 0x100 */ - uint8_t RESERVED_12[12]; - __IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */ - uint8_t RESERVED_13[12]; - __IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */ - uint8_t RESERVED_14[12]; - __IO uint32_t PS_CLRKEYLOW; /**< PS Color Key Low, offset: 0x130 */ - uint8_t RESERVED_15[12]; - __IO uint32_t PS_CLRKEYHIGH; /**< PS Color Key High, offset: 0x140 */ - uint8_t RESERVED_16[12]; - __IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */ - uint8_t RESERVED_17[12]; - __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */ - uint8_t RESERVED_18[12]; - __IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */ - uint8_t RESERVED_19[12]; - __IO uint32_t AS_CLRKEYLOW; /**< Overlay Color Key Low, offset: 0x180 */ - uint8_t RESERVED_20[12]; - __IO uint32_t AS_CLRKEYHIGH; /**< Overlay Color Key High, offset: 0x190 */ - uint8_t RESERVED_21[12]; - __IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */ - uint8_t RESERVED_22[12]; - __IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */ - uint8_t RESERVED_23[12]; - __IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */ - uint8_t RESERVED_24[348]; - __IO uint32_t POWER; /**< PXP Power Control Register, offset: 0x320 */ - uint8_t RESERVED_25[220]; - __IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */ - uint8_t RESERVED_26[60]; - __IO uint32_t PORTER_DUFF_CTRL; /**< PXP Alpha Engine A Control Register., offset: 0x440 */ -} PXP_Type; - -/* ---------------------------------------------------------------------------- - -- PXP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PXP_Register_Masks PXP Register Masks - * @{ - */ - -/*! @name CTRL - Control Register 0 */ -/*! @{ */ -#define PXP_CTRL_ENABLE_MASK (0x1U) -#define PXP_CTRL_ENABLE_SHIFT (0U) -#define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK) -#define PXP_CTRL_IRQ_ENABLE_MASK (0x2U) -#define PXP_CTRL_IRQ_ENABLE_SHIFT (1U) -#define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK) -#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U) -#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U) -#define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK) -#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U) -#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U) -#define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK) -#define PXP_CTRL_RSVD0_MASK (0xE0U) -#define PXP_CTRL_RSVD0_SHIFT (5U) -#define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK) -#define PXP_CTRL_ROTATE_MASK (0x300U) -#define PXP_CTRL_ROTATE_SHIFT (8U) -#define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK) -#define PXP_CTRL_HFLIP_MASK (0x400U) -#define PXP_CTRL_HFLIP_SHIFT (10U) -#define PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK) -#define PXP_CTRL_VFLIP_MASK (0x800U) -#define PXP_CTRL_VFLIP_SHIFT (11U) -#define PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK) -#define PXP_CTRL_RSVD1_MASK (0x3FF000U) -#define PXP_CTRL_RSVD1_SHIFT (12U) -#define PXP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD1_SHIFT)) & PXP_CTRL_RSVD1_MASK) -#define PXP_CTRL_ROT_POS_MASK (0x400000U) -#define PXP_CTRL_ROT_POS_SHIFT (22U) -#define PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK) -#define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U) -#define PXP_CTRL_BLOCK_SIZE_SHIFT (23U) -#define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK) -#define PXP_CTRL_RSVD3_MASK (0xF000000U) -#define PXP_CTRL_RSVD3_SHIFT (24U) -#define PXP_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD3_SHIFT)) & PXP_CTRL_RSVD3_MASK) -#define PXP_CTRL_EN_REPEAT_MASK (0x10000000U) -#define PXP_CTRL_EN_REPEAT_SHIFT (28U) -#define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK) -#define PXP_CTRL_RSVD4_MASK (0x20000000U) -#define PXP_CTRL_RSVD4_SHIFT (29U) -#define PXP_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD4_SHIFT)) & PXP_CTRL_RSVD4_MASK) -#define PXP_CTRL_CLKGATE_MASK (0x40000000U) -#define PXP_CTRL_CLKGATE_SHIFT (30U) -#define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK) -#define PXP_CTRL_SFTRST_MASK (0x80000000U) -#define PXP_CTRL_SFTRST_SHIFT (31U) -#define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_SET - Control Register 0 */ -/*! @{ */ -#define PXP_CTRL_SET_ENABLE_MASK (0x1U) -#define PXP_CTRL_SET_ENABLE_SHIFT (0U) -#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK) -#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U) -#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U) -#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK) -#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U) -#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U) -#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK) -#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U) -#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U) -#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK) -#define PXP_CTRL_SET_RSVD0_MASK (0xE0U) -#define PXP_CTRL_SET_RSVD0_SHIFT (5U) -#define PXP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK) -#define PXP_CTRL_SET_ROTATE_MASK (0x300U) -#define PXP_CTRL_SET_ROTATE_SHIFT (8U) -#define PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK) -#define PXP_CTRL_SET_HFLIP_MASK (0x400U) -#define PXP_CTRL_SET_HFLIP_SHIFT (10U) -#define PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK) -#define PXP_CTRL_SET_VFLIP_MASK (0x800U) -#define PXP_CTRL_SET_VFLIP_SHIFT (11U) -#define PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK) -#define PXP_CTRL_SET_RSVD1_MASK (0x3FF000U) -#define PXP_CTRL_SET_RSVD1_SHIFT (12U) -#define PXP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD1_SHIFT)) & PXP_CTRL_SET_RSVD1_MASK) -#define PXP_CTRL_SET_ROT_POS_MASK (0x400000U) -#define PXP_CTRL_SET_ROT_POS_SHIFT (22U) -#define PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK) -#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U) -#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U) -#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK) -#define PXP_CTRL_SET_RSVD3_MASK (0xF000000U) -#define PXP_CTRL_SET_RSVD3_SHIFT (24U) -#define PXP_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD3_SHIFT)) & PXP_CTRL_SET_RSVD3_MASK) -#define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U) -#define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U) -#define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK) -#define PXP_CTRL_SET_RSVD4_MASK (0x20000000U) -#define PXP_CTRL_SET_RSVD4_SHIFT (29U) -#define PXP_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD4_SHIFT)) & PXP_CTRL_SET_RSVD4_MASK) -#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U) -#define PXP_CTRL_SET_CLKGATE_SHIFT (30U) -#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK) -#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U) -#define PXP_CTRL_SET_SFTRST_SHIFT (31U) -#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_CLR - Control Register 0 */ -/*! @{ */ -#define PXP_CTRL_CLR_ENABLE_MASK (0x1U) -#define PXP_CTRL_CLR_ENABLE_SHIFT (0U) -#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK) -#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U) -#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U) -#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK) -#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U) -#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U) -#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK) -#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U) -#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U) -#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK) -#define PXP_CTRL_CLR_RSVD0_MASK (0xE0U) -#define PXP_CTRL_CLR_RSVD0_SHIFT (5U) -#define PXP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK) -#define PXP_CTRL_CLR_ROTATE_MASK (0x300U) -#define PXP_CTRL_CLR_ROTATE_SHIFT (8U) -#define PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK) -#define PXP_CTRL_CLR_HFLIP_MASK (0x400U) -#define PXP_CTRL_CLR_HFLIP_SHIFT (10U) -#define PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK) -#define PXP_CTRL_CLR_VFLIP_MASK (0x800U) -#define PXP_CTRL_CLR_VFLIP_SHIFT (11U) -#define PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK) -#define PXP_CTRL_CLR_RSVD1_MASK (0x3FF000U) -#define PXP_CTRL_CLR_RSVD1_SHIFT (12U) -#define PXP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD1_SHIFT)) & PXP_CTRL_CLR_RSVD1_MASK) -#define PXP_CTRL_CLR_ROT_POS_MASK (0x400000U) -#define PXP_CTRL_CLR_ROT_POS_SHIFT (22U) -#define PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK) -#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U) -#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U) -#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK) -#define PXP_CTRL_CLR_RSVD3_MASK (0xF000000U) -#define PXP_CTRL_CLR_RSVD3_SHIFT (24U) -#define PXP_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD3_SHIFT)) & PXP_CTRL_CLR_RSVD3_MASK) -#define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U) -#define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U) -#define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK) -#define PXP_CTRL_CLR_RSVD4_MASK (0x20000000U) -#define PXP_CTRL_CLR_RSVD4_SHIFT (29U) -#define PXP_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD4_SHIFT)) & PXP_CTRL_CLR_RSVD4_MASK) -#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U) -#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U) -#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK) -#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U) -#define PXP_CTRL_CLR_SFTRST_SHIFT (31U) -#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_TOG - Control Register 0 */ -/*! @{ */ -#define PXP_CTRL_TOG_ENABLE_MASK (0x1U) -#define PXP_CTRL_TOG_ENABLE_SHIFT (0U) -#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK) -#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U) -#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U) -#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK) -#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U) -#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U) -#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK) -#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U) -#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U) -#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK) -#define PXP_CTRL_TOG_RSVD0_MASK (0xE0U) -#define PXP_CTRL_TOG_RSVD0_SHIFT (5U) -#define PXP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK) -#define PXP_CTRL_TOG_ROTATE_MASK (0x300U) -#define PXP_CTRL_TOG_ROTATE_SHIFT (8U) -#define PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK) -#define PXP_CTRL_TOG_HFLIP_MASK (0x400U) -#define PXP_CTRL_TOG_HFLIP_SHIFT (10U) -#define PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK) -#define PXP_CTRL_TOG_VFLIP_MASK (0x800U) -#define PXP_CTRL_TOG_VFLIP_SHIFT (11U) -#define PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK) -#define PXP_CTRL_TOG_RSVD1_MASK (0x3FF000U) -#define PXP_CTRL_TOG_RSVD1_SHIFT (12U) -#define PXP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD1_SHIFT)) & PXP_CTRL_TOG_RSVD1_MASK) -#define PXP_CTRL_TOG_ROT_POS_MASK (0x400000U) -#define PXP_CTRL_TOG_ROT_POS_SHIFT (22U) -#define PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK) -#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U) -#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U) -#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK) -#define PXP_CTRL_TOG_RSVD3_MASK (0xF000000U) -#define PXP_CTRL_TOG_RSVD3_SHIFT (24U) -#define PXP_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD3_SHIFT)) & PXP_CTRL_TOG_RSVD3_MASK) -#define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U) -#define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U) -#define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK) -#define PXP_CTRL_TOG_RSVD4_MASK (0x20000000U) -#define PXP_CTRL_TOG_RSVD4_SHIFT (29U) -#define PXP_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD4_SHIFT)) & PXP_CTRL_TOG_RSVD4_MASK) -#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U) -#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U) -#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK) -#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U) -#define PXP_CTRL_TOG_SFTRST_SHIFT (31U) -#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK) -/*! @} */ - -/*! @name STAT - Status Register */ -/*! @{ */ -#define PXP_STAT_IRQ_MASK (0x1U) -#define PXP_STAT_IRQ_SHIFT (0U) -#define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK) -#define PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U) -#define PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U) -#define PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK) -#define PXP_STAT_AXI_READ_ERROR_MASK (0x4U) -#define PXP_STAT_AXI_READ_ERROR_SHIFT (2U) -#define PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK) -#define PXP_STAT_NEXT_IRQ_MASK (0x8U) -#define PXP_STAT_NEXT_IRQ_SHIFT (3U) -#define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK) -#define PXP_STAT_AXI_ERROR_ID_MASK (0xF0U) -#define PXP_STAT_AXI_ERROR_ID_SHIFT (4U) -#define PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK) -#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) -#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) -#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK) -#define PXP_STAT_RSVD2_MASK (0xFE00U) -#define PXP_STAT_RSVD2_SHIFT (9U) -#define PXP_STAT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_RSVD2_SHIFT)) & PXP_STAT_RSVD2_MASK) -#define PXP_STAT_BLOCKY_MASK (0xFF0000U) -#define PXP_STAT_BLOCKY_SHIFT (16U) -#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK) -#define PXP_STAT_BLOCKX_MASK (0xFF000000U) -#define PXP_STAT_BLOCKX_SHIFT (24U) -#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK) -/*! @} */ - -/*! @name STAT_SET - Status Register */ -/*! @{ */ -#define PXP_STAT_SET_IRQ_MASK (0x1U) -#define PXP_STAT_SET_IRQ_SHIFT (0U) -#define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK) -#define PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U) -#define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U) -#define PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK) -#define PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U) -#define PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U) -#define PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK) -#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U) -#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U) -#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK) -#define PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U) -#define PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U) -#define PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK) -#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) -#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) -#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK) -#define PXP_STAT_SET_RSVD2_MASK (0xFE00U) -#define PXP_STAT_SET_RSVD2_SHIFT (9U) -#define PXP_STAT_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_RSVD2_SHIFT)) & PXP_STAT_SET_RSVD2_MASK) -#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U) -#define PXP_STAT_SET_BLOCKY_SHIFT (16U) -#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK) -#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U) -#define PXP_STAT_SET_BLOCKX_SHIFT (24U) -#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK) -/*! @} */ - -/*! @name STAT_CLR - Status Register */ -/*! @{ */ -#define PXP_STAT_CLR_IRQ_MASK (0x1U) -#define PXP_STAT_CLR_IRQ_SHIFT (0U) -#define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK) -#define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U) -#define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U) -#define PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK) -#define PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U) -#define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U) -#define PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK) -#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U) -#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U) -#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK) -#define PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U) -#define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U) -#define PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK) -#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) -#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) -#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK) -#define PXP_STAT_CLR_RSVD2_MASK (0xFE00U) -#define PXP_STAT_CLR_RSVD2_SHIFT (9U) -#define PXP_STAT_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_RSVD2_SHIFT)) & PXP_STAT_CLR_RSVD2_MASK) -#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U) -#define PXP_STAT_CLR_BLOCKY_SHIFT (16U) -#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK) -#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U) -#define PXP_STAT_CLR_BLOCKX_SHIFT (24U) -#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK) -/*! @} */ - -/*! @name STAT_TOG - Status Register */ -/*! @{ */ -#define PXP_STAT_TOG_IRQ_MASK (0x1U) -#define PXP_STAT_TOG_IRQ_SHIFT (0U) -#define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK) -#define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U) -#define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U) -#define PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK) -#define PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U) -#define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U) -#define PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK) -#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U) -#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U) -#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK) -#define PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U) -#define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U) -#define PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK) -#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) -#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) -#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK) -#define PXP_STAT_TOG_RSVD2_MASK (0xFE00U) -#define PXP_STAT_TOG_RSVD2_SHIFT (9U) -#define PXP_STAT_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_RSVD2_SHIFT)) & PXP_STAT_TOG_RSVD2_MASK) -#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U) -#define PXP_STAT_TOG_BLOCKY_SHIFT (16U) -#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK) -#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U) -#define PXP_STAT_TOG_BLOCKX_SHIFT (24U) -#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK) -/*! @} */ - -/*! @name OUT_CTRL - Output Buffer Control Register */ -/*! @{ */ -#define PXP_OUT_CTRL_FORMAT_MASK (0x1FU) -#define PXP_OUT_CTRL_FORMAT_SHIFT (0U) -#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK) -#define PXP_OUT_CTRL_RSVD0_MASK (0xE0U) -#define PXP_OUT_CTRL_RSVD0_SHIFT (5U) -#define PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK) -#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U) -#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U) -#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) -#define PXP_OUT_CTRL_RSVD1_MASK (0x7FFC00U) -#define PXP_OUT_CTRL_RSVD1_SHIFT (10U) -#define PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD1_SHIFT)) & PXP_OUT_CTRL_RSVD1_MASK) -#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U) -#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U) -#define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK) -#define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U) -#define PXP_OUT_CTRL_ALPHA_SHIFT (24U) -#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK) -/*! @} */ - -/*! @name OUT_CTRL_SET - Output Buffer Control Register */ -/*! @{ */ -#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU) -#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U) -#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK) -#define PXP_OUT_CTRL_SET_RSVD0_MASK (0xE0U) -#define PXP_OUT_CTRL_SET_RSVD0_SHIFT (5U) -#define PXP_OUT_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK) -#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U) -#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U) -#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK) -#define PXP_OUT_CTRL_SET_RSVD1_MASK (0x7FFC00U) -#define PXP_OUT_CTRL_SET_RSVD1_SHIFT (10U) -#define PXP_OUT_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD1_SHIFT)) & PXP_OUT_CTRL_SET_RSVD1_MASK) -#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U) -#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U) -#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK) -#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U) -#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U) -#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK) -/*! @} */ - -/*! @name OUT_CTRL_CLR - Output Buffer Control Register */ -/*! @{ */ -#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU) -#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U) -#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK) -#define PXP_OUT_CTRL_CLR_RSVD0_MASK (0xE0U) -#define PXP_OUT_CTRL_CLR_RSVD0_SHIFT (5U) -#define PXP_OUT_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK) -#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U) -#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U) -#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK) -#define PXP_OUT_CTRL_CLR_RSVD1_MASK (0x7FFC00U) -#define PXP_OUT_CTRL_CLR_RSVD1_SHIFT (10U) -#define PXP_OUT_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD1_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD1_MASK) -#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U) -#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U) -#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK) -#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U) -#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U) -#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK) -/*! @} */ - -/*! @name OUT_CTRL_TOG - Output Buffer Control Register */ -/*! @{ */ -#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU) -#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U) -#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK) -#define PXP_OUT_CTRL_TOG_RSVD0_MASK (0xE0U) -#define PXP_OUT_CTRL_TOG_RSVD0_SHIFT (5U) -#define PXP_OUT_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK) -#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U) -#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U) -#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK) -#define PXP_OUT_CTRL_TOG_RSVD1_MASK (0x7FFC00U) -#define PXP_OUT_CTRL_TOG_RSVD1_SHIFT (10U) -#define PXP_OUT_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD1_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD1_MASK) -#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U) -#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U) -#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK) -#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U) -#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U) -#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK) -/*! @} */ - -/*! @name OUT_BUF - Output Frame Buffer Pointer */ -/*! @{ */ -#define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU) -#define PXP_OUT_BUF_ADDR_SHIFT (0U) -#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK) -/*! @} */ - -/*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */ -/*! @{ */ -#define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU) -#define PXP_OUT_BUF2_ADDR_SHIFT (0U) -#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK) -/*! @} */ - -/*! @name OUT_PITCH - Output Buffer Pitch */ -/*! @{ */ -#define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU) -#define PXP_OUT_PITCH_PITCH_SHIFT (0U) -#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK) -#define PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U) -#define PXP_OUT_PITCH_RSVD_SHIFT (16U) -#define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK) -/*! @} */ - -/*! @name OUT_LRC - Output Surface Lower Right Coordinate */ -/*! @{ */ -#define PXP_OUT_LRC_Y_MASK (0x3FFFU) -#define PXP_OUT_LRC_Y_SHIFT (0U) -#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK) -#define PXP_OUT_LRC_RSVD0_MASK (0xC000U) -#define PXP_OUT_LRC_RSVD0_SHIFT (14U) -#define PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD0_SHIFT)) & PXP_OUT_LRC_RSVD0_MASK) -#define PXP_OUT_LRC_X_MASK (0x3FFF0000U) -#define PXP_OUT_LRC_X_SHIFT (16U) -#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK) -#define PXP_OUT_LRC_RSVD1_MASK (0xC0000000U) -#define PXP_OUT_LRC_RSVD1_SHIFT (30U) -#define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK) -/*! @} */ - -/*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */ -/*! @{ */ -#define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU) -#define PXP_OUT_PS_ULC_Y_SHIFT (0U) -#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK) -#define PXP_OUT_PS_ULC_RSVD0_MASK (0xC000U) -#define PXP_OUT_PS_ULC_RSVD0_SHIFT (14U) -#define PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD0_SHIFT)) & PXP_OUT_PS_ULC_RSVD0_MASK) -#define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U) -#define PXP_OUT_PS_ULC_X_SHIFT (16U) -#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK) -#define PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U) -#define PXP_OUT_PS_ULC_RSVD1_SHIFT (30U) -#define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK) -/*! @} */ - -/*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */ -/*! @{ */ -#define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU) -#define PXP_OUT_PS_LRC_Y_SHIFT (0U) -#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK) -#define PXP_OUT_PS_LRC_RSVD0_MASK (0xC000U) -#define PXP_OUT_PS_LRC_RSVD0_SHIFT (14U) -#define PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD0_SHIFT)) & PXP_OUT_PS_LRC_RSVD0_MASK) -#define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U) -#define PXP_OUT_PS_LRC_X_SHIFT (16U) -#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK) -#define PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U) -#define PXP_OUT_PS_LRC_RSVD1_SHIFT (30U) -#define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK) -/*! @} */ - -/*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */ -/*! @{ */ -#define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU) -#define PXP_OUT_AS_ULC_Y_SHIFT (0U) -#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK) -#define PXP_OUT_AS_ULC_RSVD0_MASK (0xC000U) -#define PXP_OUT_AS_ULC_RSVD0_SHIFT (14U) -#define PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD0_SHIFT)) & PXP_OUT_AS_ULC_RSVD0_MASK) -#define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U) -#define PXP_OUT_AS_ULC_X_SHIFT (16U) -#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK) -#define PXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U) -#define PXP_OUT_AS_ULC_RSVD1_SHIFT (30U) -#define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK) -/*! @} */ - -/*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */ -/*! @{ */ -#define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU) -#define PXP_OUT_AS_LRC_Y_SHIFT (0U) -#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK) -#define PXP_OUT_AS_LRC_RSVD0_MASK (0xC000U) -#define PXP_OUT_AS_LRC_RSVD0_SHIFT (14U) -#define PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD0_SHIFT)) & PXP_OUT_AS_LRC_RSVD0_MASK) -#define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U) -#define PXP_OUT_AS_LRC_X_SHIFT (16U) -#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK) -#define PXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U) -#define PXP_OUT_AS_LRC_RSVD1_SHIFT (30U) -#define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK) -/*! @} */ - -/*! @name PS_CTRL - Processed Surface (PS) Control Register */ -/*! @{ */ -#define PXP_PS_CTRL_FORMAT_MASK (0x1FU) -#define PXP_PS_CTRL_FORMAT_SHIFT (0U) -#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK) -#define PXP_PS_CTRL_WB_SWAP_MASK (0x20U) -#define PXP_PS_CTRL_WB_SWAP_SHIFT (5U) -#define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK) -#define PXP_PS_CTRL_RSVD0_MASK (0xC0U) -#define PXP_PS_CTRL_RSVD0_SHIFT (6U) -#define PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK) -#define PXP_PS_CTRL_DECY_MASK (0x300U) -#define PXP_PS_CTRL_DECY_SHIFT (8U) -#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK) -#define PXP_PS_CTRL_DECX_MASK (0xC00U) -#define PXP_PS_CTRL_DECX_SHIFT (10U) -#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK) -#define PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U) -#define PXP_PS_CTRL_RSVD1_SHIFT (12U) -#define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK) -/*! @} */ - -/*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */ -/*! @{ */ -#define PXP_PS_CTRL_SET_FORMAT_MASK (0x1FU) -#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U) -#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK) -#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x20U) -#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (5U) -#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK) -#define PXP_PS_CTRL_SET_RSVD0_MASK (0xC0U) -#define PXP_PS_CTRL_SET_RSVD0_SHIFT (6U) -#define PXP_PS_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK) -#define PXP_PS_CTRL_SET_DECY_MASK (0x300U) -#define PXP_PS_CTRL_SET_DECY_SHIFT (8U) -#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK) -#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U) -#define PXP_PS_CTRL_SET_DECX_SHIFT (10U) -#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK) -#define PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U) -#define PXP_PS_CTRL_SET_RSVD1_SHIFT (12U) -#define PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK) -/*! @} */ - -/*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */ -/*! @{ */ -#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x1FU) -#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U) -#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK) -#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x20U) -#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (5U) -#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK) -#define PXP_PS_CTRL_CLR_RSVD0_MASK (0xC0U) -#define PXP_PS_CTRL_CLR_RSVD0_SHIFT (6U) -#define PXP_PS_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK) -#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U) -#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U) -#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK) -#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U) -#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U) -#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK) -#define PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U) -#define PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U) -#define PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK) -/*! @} */ - -/*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */ -/*! @{ */ -#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x1FU) -#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U) -#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK) -#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x20U) -#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (5U) -#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK) -#define PXP_PS_CTRL_TOG_RSVD0_MASK (0xC0U) -#define PXP_PS_CTRL_TOG_RSVD0_SHIFT (6U) -#define PXP_PS_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK) -#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U) -#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U) -#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK) -#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U) -#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U) -#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK) -#define PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U) -#define PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U) -#define PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK) -/*! @} */ - -/*! @name PS_BUF - PS Input Buffer Address */ -/*! @{ */ -#define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU) -#define PXP_PS_BUF_ADDR_SHIFT (0U) -#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK) -/*! @} */ - -/*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */ -/*! @{ */ -#define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU) -#define PXP_PS_UBUF_ADDR_SHIFT (0U) -#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK) -/*! @} */ - -/*! @name PS_VBUF - PS V/Cr Input Buffer Address */ -/*! @{ */ -#define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU) -#define PXP_PS_VBUF_ADDR_SHIFT (0U) -#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK) -/*! @} */ - -/*! @name PS_PITCH - Processed Surface Pitch */ -/*! @{ */ -#define PXP_PS_PITCH_PITCH_MASK (0xFFFFU) -#define PXP_PS_PITCH_PITCH_SHIFT (0U) -#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK) -#define PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U) -#define PXP_PS_PITCH_RSVD_SHIFT (16U) -#define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK) -/*! @} */ - -/*! @name PS_BACKGROUND - PS Background Color */ -/*! @{ */ -#define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU) -#define PXP_PS_BACKGROUND_COLOR_SHIFT (0U) -#define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK) -#define PXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U) -#define PXP_PS_BACKGROUND_RSVD_SHIFT (24U) -#define PXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK) -/*! @} */ - -/*! @name PS_SCALE - PS Scale Factor Register */ -/*! @{ */ -#define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU) -#define PXP_PS_SCALE_XSCALE_SHIFT (0U) -#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK) -#define PXP_PS_SCALE_RSVD1_MASK (0x8000U) -#define PXP_PS_SCALE_RSVD1_SHIFT (15U) -#define PXP_PS_SCALE_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD1_SHIFT)) & PXP_PS_SCALE_RSVD1_MASK) -#define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U) -#define PXP_PS_SCALE_YSCALE_SHIFT (16U) -#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK) -#define PXP_PS_SCALE_RSVD2_MASK (0x80000000U) -#define PXP_PS_SCALE_RSVD2_SHIFT (31U) -#define PXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK) -/*! @} */ - -/*! @name PS_OFFSET - PS Scale Offset Register */ -/*! @{ */ -#define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU) -#define PXP_PS_OFFSET_XOFFSET_SHIFT (0U) -#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK) -#define PXP_PS_OFFSET_RSVD1_MASK (0xF000U) -#define PXP_PS_OFFSET_RSVD1_SHIFT (12U) -#define PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD1_SHIFT)) & PXP_PS_OFFSET_RSVD1_MASK) -#define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U) -#define PXP_PS_OFFSET_YOFFSET_SHIFT (16U) -#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK) -#define PXP_PS_OFFSET_RSVD2_MASK (0xF0000000U) -#define PXP_PS_OFFSET_RSVD2_SHIFT (28U) -#define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK) -/*! @} */ - -/*! @name PS_CLRKEYLOW - PS Color Key Low */ -/*! @{ */ -#define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) -#define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U) -#define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK) -#define PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) -#define PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U) -#define PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK) -/*! @} */ - -/*! @name PS_CLRKEYHIGH - PS Color Key High */ -/*! @{ */ -#define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) -#define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U) -#define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK) -#define PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) -#define PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U) -#define PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK) -/*! @} */ - -/*! @name AS_CTRL - Alpha Surface Control */ -/*! @{ */ -#define PXP_AS_CTRL_RSVD0_MASK (0x1U) -#define PXP_AS_CTRL_RSVD0_SHIFT (0U) -#define PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK) -#define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U) -#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U) -#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK) -#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) -#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) -#define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK) -#define PXP_AS_CTRL_FORMAT_MASK (0xF0U) -#define PXP_AS_CTRL_FORMAT_SHIFT (4U) -#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK) -#define PXP_AS_CTRL_ALPHA_MASK (0xFF00U) -#define PXP_AS_CTRL_ALPHA_SHIFT (8U) -#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK) -#define PXP_AS_CTRL_ROP_MASK (0xF0000U) -#define PXP_AS_CTRL_ROP_SHIFT (16U) -#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK) -#define PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) -#define PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U) -#define PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK) -#define PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U) -#define PXP_AS_CTRL_RSVD1_SHIFT (21U) -#define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK) -/*! @} */ - -/*! @name AS_BUF - Alpha Surface Buffer Pointer */ -/*! @{ */ -#define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU) -#define PXP_AS_BUF_ADDR_SHIFT (0U) -#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK) -/*! @} */ - -/*! @name AS_PITCH - Alpha Surface Pitch */ -/*! @{ */ -#define PXP_AS_PITCH_PITCH_MASK (0xFFFFU) -#define PXP_AS_PITCH_PITCH_SHIFT (0U) -#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK) -#define PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U) -#define PXP_AS_PITCH_RSVD_SHIFT (16U) -#define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK) -/*! @} */ - -/*! @name AS_CLRKEYLOW - Overlay Color Key Low */ -/*! @{ */ -#define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) -#define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U) -#define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK) -#define PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) -#define PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U) -#define PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK) -/*! @} */ - -/*! @name AS_CLRKEYHIGH - Overlay Color Key High */ -/*! @{ */ -#define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) -#define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) -#define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK) -#define PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) -#define PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) -#define PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK) -/*! @} */ - -/*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */ -/*! @{ */ -#define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU) -#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U) -#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK) -#define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U) -#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U) -#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK) -#define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U) -#define PXP_CSC1_COEF0_C0_SHIFT (18U) -#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK) -#define PXP_CSC1_COEF0_RSVD1_MASK (0x20000000U) -#define PXP_CSC1_COEF0_RSVD1_SHIFT (29U) -#define PXP_CSC1_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_RSVD1_SHIFT)) & PXP_CSC1_COEF0_RSVD1_MASK) -#define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U) -#define PXP_CSC1_COEF0_BYPASS_SHIFT (30U) -#define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK) -#define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U) -#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U) -#define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK) -/*! @} */ - -/*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */ -/*! @{ */ -#define PXP_CSC1_COEF1_C4_MASK (0x7FFU) -#define PXP_CSC1_COEF1_C4_SHIFT (0U) -#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK) -#define PXP_CSC1_COEF1_RSVD0_MASK (0xF800U) -#define PXP_CSC1_COEF1_RSVD0_SHIFT (11U) -#define PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD0_SHIFT)) & PXP_CSC1_COEF1_RSVD0_MASK) -#define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U) -#define PXP_CSC1_COEF1_C1_SHIFT (16U) -#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK) -#define PXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U) -#define PXP_CSC1_COEF1_RSVD1_SHIFT (27U) -#define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK) -/*! @} */ - -/*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */ -/*! @{ */ -#define PXP_CSC1_COEF2_C3_MASK (0x7FFU) -#define PXP_CSC1_COEF2_C3_SHIFT (0U) -#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK) -#define PXP_CSC1_COEF2_RSVD0_MASK (0xF800U) -#define PXP_CSC1_COEF2_RSVD0_SHIFT (11U) -#define PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD0_SHIFT)) & PXP_CSC1_COEF2_RSVD0_MASK) -#define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U) -#define PXP_CSC1_COEF2_C2_SHIFT (16U) -#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK) -#define PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U) -#define PXP_CSC1_COEF2_RSVD1_SHIFT (27U) -#define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK) -/*! @} */ - -/*! @name POWER - PXP Power Control Register */ -/*! @{ */ -#define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U) -#define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U) -#define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK) -#define PXP_POWER_CTRL_MASK (0xFFFFF000U) -#define PXP_POWER_CTRL_SHIFT (12U) -#define PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK) -/*! @} */ - -/*! @name NEXT - Next Frame Pointer */ -/*! @{ */ -#define PXP_NEXT_ENABLED_MASK (0x1U) -#define PXP_NEXT_ENABLED_SHIFT (0U) -#define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK) -#define PXP_NEXT_RSVD_MASK (0x2U) -#define PXP_NEXT_RSVD_SHIFT (1U) -#define PXP_NEXT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_RSVD_SHIFT)) & PXP_NEXT_RSVD_MASK) -#define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU) -#define PXP_NEXT_POINTER_SHIFT (2U) -#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK) -/*! @} */ - -/*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */ -/*! @{ */ -#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U) -#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U) -#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK) -#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U) -#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U) -#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK) -#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U) -#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U) -#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK) -#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U) -#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U) -#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK) -#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U) -#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U) -#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK) -#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U) -#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U) -#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK) -#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U) -#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U) -#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK) -#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U) -#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U) -#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK) -#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U) -#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U) -#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK) -#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U) -#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U) -#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK) -#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U) -#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U) -#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PXP_Register_Masks */ - - -/* PXP - Peripheral instance base addresses */ -/** Peripheral PXP base address */ -#define PXP_BASE (0x402B4000u) -/** Peripheral PXP base pointer */ -#define PXP ((PXP_Type *)PXP_BASE) -/** Array initializer of PXP peripheral base addresses */ -#define PXP_BASE_ADDRS { PXP_BASE } -/** Array initializer of PXP peripheral base pointers */ -#define PXP_BASE_PTRS { PXP } -/** Interrupt vectors for the PXP peripheral type */ -#define PXP_IRQ0_IRQS { PXP_IRQn } - -/*! - * @} - */ /* end of group PXP_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ROMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer - * @{ - */ - -/** ROMC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[212]; - __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ - __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ - uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ - __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ - __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_1[200]; - __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ -} ROMC_Type; - -/* ---------------------------------------------------------------------------- - -- ROMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ROMC_Register_Masks ROMC Register Masks - * @{ - */ - -/*! @name ROMPATCHD - ROMC Data Registers */ -/*! @{ */ -#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) -#define ROMC_ROMPATCHD_DATAX_SHIFT (0U) -#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) -/*! @} */ - -/* The count of ROMC_ROMPATCHD */ -#define ROMC_ROMPATCHD_COUNT (8U) - -/*! @name ROMPATCHCNTL - ROMC Control Register */ -/*! @{ */ -#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) -#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) -#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) -#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) -#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) -#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) -/*! @} */ - -/*! @name ROMPATCHENL - ROMC Enable Register Low */ -/*! @{ */ -#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) -#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) -#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) -/*! @} */ - -/*! @name ROMPATCHA - ROMC Address Registers */ -/*! @{ */ -#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) -#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) -#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) -#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) -#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) -#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) -/*! @} */ - -/* The count of ROMC_ROMPATCHA */ -#define ROMC_ROMPATCHA_COUNT (16U) - -/*! @name ROMPATCHSR - ROMC Status Register */ -/*! @{ */ -#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) -#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) -#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) -#define ROMC_ROMPATCHSR_SW_MASK (0x20000U) -#define ROMC_ROMPATCHSR_SW_SHIFT (17U) -#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ROMC_Register_Masks */ - - -/* ROMC - Peripheral instance base addresses */ -/** Peripheral ROMC base address */ -#define ROMC_BASE (0x40180000u) -/** Peripheral ROMC base pointer */ -#define ROMC ((ROMC_Type *)ROMC_BASE) -/** Array initializer of ROMC peripheral base addresses */ -#define ROMC_BASE_ADDRS { ROMC_BASE } -/** Array initializer of ROMC peripheral base pointers */ -#define ROMC_BASE_PTRS { ROMC } - -/*! - * @} - */ /* end of group ROMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTWDOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer - * @{ - */ - -/** RTWDOG - Register Layout Typedef */ -typedef struct { - __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ - __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ - __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ - __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ -} RTWDOG_Type; - -/* ---------------------------------------------------------------------------- - -- RTWDOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks - * @{ - */ - -/*! @name CS - Watchdog Control and Status Register */ -/*! @{ */ -#define RTWDOG_CS_STOP_MASK (0x1U) -#define RTWDOG_CS_STOP_SHIFT (0U) -#define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) -#define RTWDOG_CS_WAIT_MASK (0x2U) -#define RTWDOG_CS_WAIT_SHIFT (1U) -#define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) -#define RTWDOG_CS_DBG_MASK (0x4U) -#define RTWDOG_CS_DBG_SHIFT (2U) -#define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) -#define RTWDOG_CS_TST_MASK (0x18U) -#define RTWDOG_CS_TST_SHIFT (3U) -#define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) -#define RTWDOG_CS_UPDATE_MASK (0x20U) -#define RTWDOG_CS_UPDATE_SHIFT (5U) -#define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) -#define RTWDOG_CS_INT_MASK (0x40U) -#define RTWDOG_CS_INT_SHIFT (6U) -#define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) -#define RTWDOG_CS_EN_MASK (0x80U) -#define RTWDOG_CS_EN_SHIFT (7U) -#define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) -#define RTWDOG_CS_CLK_MASK (0x300U) -#define RTWDOG_CS_CLK_SHIFT (8U) -#define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) -#define RTWDOG_CS_RCS_MASK (0x400U) -#define RTWDOG_CS_RCS_SHIFT (10U) -#define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) -#define RTWDOG_CS_ULK_MASK (0x800U) -#define RTWDOG_CS_ULK_SHIFT (11U) -#define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) -#define RTWDOG_CS_PRES_MASK (0x1000U) -#define RTWDOG_CS_PRES_SHIFT (12U) -#define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) -#define RTWDOG_CS_CMD32EN_MASK (0x2000U) -#define RTWDOG_CS_CMD32EN_SHIFT (13U) -#define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) -#define RTWDOG_CS_FLG_MASK (0x4000U) -#define RTWDOG_CS_FLG_SHIFT (14U) -#define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) -#define RTWDOG_CS_WIN_MASK (0x8000U) -#define RTWDOG_CS_WIN_SHIFT (15U) -#define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) -/*! @} */ - -/*! @name CNT - Watchdog Counter Register */ -/*! @{ */ -#define RTWDOG_CNT_CNTLOW_MASK (0xFFU) -#define RTWDOG_CNT_CNTLOW_SHIFT (0U) -#define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) -#define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) -#define RTWDOG_CNT_CNTHIGH_SHIFT (8U) -#define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) -/*! @} */ - -/*! @name TOVAL - Watchdog Timeout Value Register */ -/*! @{ */ -#define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) -#define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) -#define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) -#define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) -#define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) -#define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) -/*! @} */ - -/*! @name WIN - Watchdog Window Register */ -/*! @{ */ -#define RTWDOG_WIN_WINLOW_MASK (0xFFU) -#define RTWDOG_WIN_WINLOW_SHIFT (0U) -#define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) -#define RTWDOG_WIN_WINHIGH_MASK (0xFF00U) -#define RTWDOG_WIN_WINHIGH_SHIFT (8U) -#define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RTWDOG_Register_Masks */ - - -/* RTWDOG - Peripheral instance base addresses */ -/** Peripheral RTWDOG base address */ -#define RTWDOG_BASE (0x400BC000u) -/** Peripheral RTWDOG base pointer */ -#define RTWDOG ((RTWDOG_Type *)RTWDOG_BASE) -/** Array initializer of RTWDOG peripheral base addresses */ -#define RTWDOG_BASE_ADDRS { RTWDOG_BASE } -/** Array initializer of RTWDOG peripheral base pointers */ -#define RTWDOG_BASE_PTRS { RTWDOG } -/** Interrupt vectors for the RTWDOG peripheral type */ -#define RTWDOG_IRQS { RTWDOG_IRQn } -/* Extra definition */ -#define RTWDOG_UPDATE_KEY (0xD928C520U) -#define RTWDOG_REFRESH_KEY (0xB480A602U) - - -/*! - * @} - */ /* end of group RTWDOG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SEMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SEMC_Peripheral_Access_Layer SEMC Peripheral Access Layer - * @{ - */ - -/** SEMC - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCR; /**< Module Control Register, offset: 0x0 */ - __IO uint32_t IOCR; /**< IO Mux Control Register, offset: 0x4 */ - __IO uint32_t BMCR0; /**< Master Bus (AXI) Control Register 0, offset: 0x8 */ - __IO uint32_t BMCR1; /**< Master Bus (AXI) Control Register 1, offset: 0xC */ - __IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device), array offset: 0x10, array step: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x38 */ - __IO uint32_t INTR; /**< Interrupt Enable Register, offset: 0x3C */ - __IO uint32_t SDRAMCR0; /**< SDRAM control register 0, offset: 0x40 */ - __IO uint32_t SDRAMCR1; /**< SDRAM control register 1, offset: 0x44 */ - __IO uint32_t SDRAMCR2; /**< SDRAM control register 2, offset: 0x48 */ - __IO uint32_t SDRAMCR3; /**< SDRAM control register 3, offset: 0x4C */ - __IO uint32_t NANDCR0; /**< NAND control register 0, offset: 0x50 */ - __IO uint32_t NANDCR1; /**< NAND control register 1, offset: 0x54 */ - __IO uint32_t NANDCR2; /**< NAND control register 2, offset: 0x58 */ - __IO uint32_t NANDCR3; /**< NAND control register 3, offset: 0x5C */ - __IO uint32_t NORCR0; /**< NOR control register 0, offset: 0x60 */ - __IO uint32_t NORCR1; /**< NOR control register 1, offset: 0x64 */ - __IO uint32_t NORCR2; /**< NOR control register 2, offset: 0x68 */ - uint32_t NORCR3; /**< NOR control register 3, offset: 0x6C */ - __IO uint32_t SRAMCR0; /**< SRAM control register 0, offset: 0x70 */ - __IO uint32_t SRAMCR1; /**< SRAM control register 1, offset: 0x74 */ - __IO uint32_t SRAMCR2; /**< SRAM control register 2, offset: 0x78 */ - uint32_t SRAMCR3; /**< SRAM control register 3, offset: 0x7C */ - __IO uint32_t DBICR0; /**< DBI-B control register 0, offset: 0x80 */ - __IO uint32_t DBICR1; /**< DBI-B control register 1, offset: 0x84 */ - uint8_t RESERVED_1[8]; - __IO uint32_t IPCR0; /**< IP Command control register 0, offset: 0x90 */ - __IO uint32_t IPCR1; /**< IP Command control register 1, offset: 0x94 */ - __IO uint32_t IPCR2; /**< IP Command control register 2, offset: 0x98 */ - __IO uint32_t IPCMD; /**< IP Command register, offset: 0x9C */ - __IO uint32_t IPTXDAT; /**< TX DATA register (for IP Command), offset: 0xA0 */ - uint8_t RESERVED_2[12]; - __I uint32_t IPRXDAT; /**< RX DATA register (for IP Command), offset: 0xB0 */ - uint8_t RESERVED_3[12]; - __I uint32_t STS0; /**< Status register 0, offset: 0xC0 */ - uint32_t STS1; /**< Status register 1, offset: 0xC4 */ - __I uint32_t STS2; /**< Status register 2, offset: 0xC8 */ - uint32_t STS3; /**< Status register 3, offset: 0xCC */ - uint32_t STS4; /**< Status register 4, offset: 0xD0 */ - uint32_t STS5; /**< Status register 5, offset: 0xD4 */ - uint32_t STS6; /**< Status register 6, offset: 0xD8 */ - uint32_t STS7; /**< Status register 7, offset: 0xDC */ - uint32_t STS8; /**< Status register 8, offset: 0xE0 */ - uint32_t STS9; /**< Status register 9, offset: 0xE4 */ - uint32_t STS10; /**< Status register 10, offset: 0xE8 */ - uint32_t STS11; /**< Status register 11, offset: 0xEC */ - __I uint32_t STS12; /**< Status register 12, offset: 0xF0 */ - uint32_t STS13; /**< Status register 13, offset: 0xF4 */ - uint32_t STS14; /**< Status register 14, offset: 0xF8 */ - uint32_t STS15; /**< Status register 15, offset: 0xFC */ -} SEMC_Type; - -/* ---------------------------------------------------------------------------- - -- SEMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SEMC_Register_Masks SEMC Register Masks - * @{ - */ - -/*! @name MCR - Module Control Register */ -/*! @{ */ -#define SEMC_MCR_SWRST_MASK (0x1U) -#define SEMC_MCR_SWRST_SHIFT (0U) -#define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) -#define SEMC_MCR_MDIS_MASK (0x2U) -#define SEMC_MCR_MDIS_SHIFT (1U) -#define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) -#define SEMC_MCR_DQSMD_MASK (0x4U) -#define SEMC_MCR_DQSMD_SHIFT (2U) -#define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) -#define SEMC_MCR_WPOL0_MASK (0x40U) -#define SEMC_MCR_WPOL0_SHIFT (6U) -#define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) -#define SEMC_MCR_WPOL1_MASK (0x80U) -#define SEMC_MCR_WPOL1_SHIFT (7U) -#define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) -#define SEMC_MCR_CTO_MASK (0xFF0000U) -#define SEMC_MCR_CTO_SHIFT (16U) -#define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) -#define SEMC_MCR_BTO_MASK (0x1F000000U) -#define SEMC_MCR_BTO_SHIFT (24U) -#define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) -/*! @} */ - -/*! @name IOCR - IO Mux Control Register */ -/*! @{ */ -#define SEMC_IOCR_MUX_A8_MASK (0x7U) -#define SEMC_IOCR_MUX_A8_SHIFT (0U) -#define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) -#define SEMC_IOCR_MUX_CSX0_MASK (0x38U) -#define SEMC_IOCR_MUX_CSX0_SHIFT (3U) -#define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) -#define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U) -#define SEMC_IOCR_MUX_CSX1_SHIFT (6U) -#define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) -#define SEMC_IOCR_MUX_CSX2_MASK (0xE00U) -#define SEMC_IOCR_MUX_CSX2_SHIFT (9U) -#define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) -#define SEMC_IOCR_MUX_CSX3_MASK (0x7000U) -#define SEMC_IOCR_MUX_CSX3_SHIFT (12U) -#define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) -#define SEMC_IOCR_MUX_RDY_MASK (0x38000U) -#define SEMC_IOCR_MUX_RDY_SHIFT (15U) -#define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) -/*! @} */ - -/*! @name BMCR0 - Master Bus (AXI) Control Register 0 */ -/*! @{ */ -#define SEMC_BMCR0_WQOS_MASK (0xFU) -#define SEMC_BMCR0_WQOS_SHIFT (0U) -#define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) -#define SEMC_BMCR0_WAGE_MASK (0xF0U) -#define SEMC_BMCR0_WAGE_SHIFT (4U) -#define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK) -#define SEMC_BMCR0_WSH_MASK (0xFF00U) -#define SEMC_BMCR0_WSH_SHIFT (8U) -#define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK) -#define SEMC_BMCR0_WRWS_MASK (0xFF0000U) -#define SEMC_BMCR0_WRWS_SHIFT (16U) -#define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) -/*! @} */ - -/*! @name BMCR1 - Master Bus (AXI) Control Register 1 */ -/*! @{ */ -#define SEMC_BMCR1_WQOS_MASK (0xFU) -#define SEMC_BMCR1_WQOS_SHIFT (0U) -#define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) -#define SEMC_BMCR1_WAGE_MASK (0xF0U) -#define SEMC_BMCR1_WAGE_SHIFT (4U) -#define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK) -#define SEMC_BMCR1_WPH_MASK (0xFF00U) -#define SEMC_BMCR1_WPH_SHIFT (8U) -#define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK) -#define SEMC_BMCR1_WRWS_MASK (0xFF0000U) -#define SEMC_BMCR1_WRWS_SHIFT (16U) -#define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK) -#define SEMC_BMCR1_WBR_MASK (0xFF000000U) -#define SEMC_BMCR1_WBR_SHIFT (24U) -#define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) -/*! @} */ - -/*! @name BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) */ -/*! @{ */ -#define SEMC_BR_VLD_MASK (0x1U) -#define SEMC_BR_VLD_SHIFT (0U) -#define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) -#define SEMC_BR_MS_MASK (0x3EU) -#define SEMC_BR_MS_SHIFT (1U) -#define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) -#define SEMC_BR_BA_MASK (0xFFFFF000U) -#define SEMC_BR_BA_SHIFT (12U) -#define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) -/*! @} */ - -/* The count of SEMC_BR */ -#define SEMC_BR_COUNT (9U) - -/*! @name INTEN - Interrupt Enable Register */ -/*! @{ */ -#define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) -#define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) -#define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) -#define SEMC_INTEN_IPCMDERREN_MASK (0x2U) -#define SEMC_INTEN_IPCMDERREN_SHIFT (1U) -#define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) -#define SEMC_INTEN_AXICMDERREN_MASK (0x4U) -#define SEMC_INTEN_AXICMDERREN_SHIFT (2U) -#define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) -#define SEMC_INTEN_AXIBUSERREN_MASK (0x8U) -#define SEMC_INTEN_AXIBUSERREN_SHIFT (3U) -#define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) -#define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) -#define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) -#define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) -#define SEMC_INTEN_NDNOPENDEN_MASK (0x20U) -#define SEMC_INTEN_NDNOPENDEN_SHIFT (5U) -#define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) -/*! @} */ - -/*! @name INTR - Interrupt Enable Register */ -/*! @{ */ -#define SEMC_INTR_IPCMDDONE_MASK (0x1U) -#define SEMC_INTR_IPCMDDONE_SHIFT (0U) -#define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) -#define SEMC_INTR_IPCMDERR_MASK (0x2U) -#define SEMC_INTR_IPCMDERR_SHIFT (1U) -#define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) -#define SEMC_INTR_AXICMDERR_MASK (0x4U) -#define SEMC_INTR_AXICMDERR_SHIFT (2U) -#define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) -#define SEMC_INTR_AXIBUSERR_MASK (0x8U) -#define SEMC_INTR_AXIBUSERR_SHIFT (3U) -#define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) -#define SEMC_INTR_NDPAGEEND_MASK (0x10U) -#define SEMC_INTR_NDPAGEEND_SHIFT (4U) -#define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) -#define SEMC_INTR_NDNOPEND_MASK (0x20U) -#define SEMC_INTR_NDNOPEND_SHIFT (5U) -#define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) -/*! @} */ - -/*! @name SDRAMCR0 - SDRAM control register 0 */ -/*! @{ */ -#define SEMC_SDRAMCR0_PS_MASK (0x1U) -#define SEMC_SDRAMCR0_PS_SHIFT (0U) -#define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) -#define SEMC_SDRAMCR0_BL_MASK (0x70U) -#define SEMC_SDRAMCR0_BL_SHIFT (4U) -#define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) -#define SEMC_SDRAMCR0_COL_MASK (0x300U) -#define SEMC_SDRAMCR0_COL_SHIFT (8U) -#define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) -#define SEMC_SDRAMCR0_CL_MASK (0xC00U) -#define SEMC_SDRAMCR0_CL_SHIFT (10U) -#define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) -/*! @} */ - -/*! @name SDRAMCR1 - SDRAM control register 1 */ -/*! @{ */ -#define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU) -#define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U) -#define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) -#define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U) -#define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U) -#define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK) -#define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U) -#define SEMC_SDRAMCR1_RFRC_SHIFT (8U) -#define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK) -#define SEMC_SDRAMCR1_WRC_MASK (0xE000U) -#define SEMC_SDRAMCR1_WRC_SHIFT (13U) -#define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK) -#define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U) -#define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U) -#define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK) -#define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U) -#define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U) -#define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) -/*! @} */ - -/*! @name SDRAMCR2 - SDRAM control register 2 */ -/*! @{ */ -#define SEMC_SDRAMCR2_SRRC_MASK (0xFFU) -#define SEMC_SDRAMCR2_SRRC_SHIFT (0U) -#define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) -#define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U) -#define SEMC_SDRAMCR2_REF2REF_SHIFT (8U) -#define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK) -#define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U) -#define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U) -#define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) -#define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U) -#define SEMC_SDRAMCR2_ITO_SHIFT (24U) -#define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) -/*! @} */ - -/*! @name SDRAMCR3 - SDRAM control register 3 */ -/*! @{ */ -#define SEMC_SDRAMCR3_REN_MASK (0x1U) -#define SEMC_SDRAMCR3_REN_SHIFT (0U) -#define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) -#define SEMC_SDRAMCR3_REBL_MASK (0xEU) -#define SEMC_SDRAMCR3_REBL_SHIFT (1U) -#define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) -#define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) -#define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) -#define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) -#define SEMC_SDRAMCR3_RT_MASK (0xFF0000U) -#define SEMC_SDRAMCR3_RT_SHIFT (16U) -#define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) -#define SEMC_SDRAMCR3_UT_MASK (0xFF000000U) -#define SEMC_SDRAMCR3_UT_SHIFT (24U) -#define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) -/*! @} */ - -/*! @name NANDCR0 - NAND control register 0 */ -/*! @{ */ -#define SEMC_NANDCR0_PS_MASK (0x1U) -#define SEMC_NANDCR0_PS_SHIFT (0U) -#define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) -#define SEMC_NANDCR0_BL_MASK (0x70U) -#define SEMC_NANDCR0_BL_SHIFT (4U) -#define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) -#define SEMC_NANDCR0_EDO_MASK (0x80U) -#define SEMC_NANDCR0_EDO_SHIFT (7U) -#define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) -#define SEMC_NANDCR0_COL_MASK (0x700U) -#define SEMC_NANDCR0_COL_SHIFT (8U) -#define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) -/*! @} */ - -/*! @name NANDCR1 - NAND control register 1 */ -/*! @{ */ -#define SEMC_NANDCR1_CES_MASK (0xFU) -#define SEMC_NANDCR1_CES_SHIFT (0U) -#define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) -#define SEMC_NANDCR1_CEH_MASK (0xF0U) -#define SEMC_NANDCR1_CEH_SHIFT (4U) -#define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK) -#define SEMC_NANDCR1_WEL_MASK (0xF00U) -#define SEMC_NANDCR1_WEL_SHIFT (8U) -#define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK) -#define SEMC_NANDCR1_WEH_MASK (0xF000U) -#define SEMC_NANDCR1_WEH_SHIFT (12U) -#define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK) -#define SEMC_NANDCR1_REL_MASK (0xF0000U) -#define SEMC_NANDCR1_REL_SHIFT (16U) -#define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK) -#define SEMC_NANDCR1_REH_MASK (0xF00000U) -#define SEMC_NANDCR1_REH_SHIFT (20U) -#define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK) -#define SEMC_NANDCR1_TA_MASK (0xF000000U) -#define SEMC_NANDCR1_TA_SHIFT (24U) -#define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK) -#define SEMC_NANDCR1_CEITV_MASK (0xF0000000U) -#define SEMC_NANDCR1_CEITV_SHIFT (28U) -#define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) -/*! @} */ - -/*! @name NANDCR2 - NAND control register 2 */ -/*! @{ */ -#define SEMC_NANDCR2_TWHR_MASK (0x3FU) -#define SEMC_NANDCR2_TWHR_SHIFT (0U) -#define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) -#define SEMC_NANDCR2_TRHW_MASK (0xFC0U) -#define SEMC_NANDCR2_TRHW_SHIFT (6U) -#define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK) -#define SEMC_NANDCR2_TADL_MASK (0x3F000U) -#define SEMC_NANDCR2_TADL_SHIFT (12U) -#define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK) -#define SEMC_NANDCR2_TRR_MASK (0xFC0000U) -#define SEMC_NANDCR2_TRR_SHIFT (18U) -#define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK) -#define SEMC_NANDCR2_TWB_MASK (0x3F000000U) -#define SEMC_NANDCR2_TWB_SHIFT (24U) -#define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) -/*! @} */ - -/*! @name NANDCR3 - NAND control register 3 */ -/*! @{ */ -#define SEMC_NANDCR3_NDOPT1_MASK (0x1U) -#define SEMC_NANDCR3_NDOPT1_SHIFT (0U) -#define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) -#define SEMC_NANDCR3_NDOPT2_MASK (0x2U) -#define SEMC_NANDCR3_NDOPT2_SHIFT (1U) -#define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK) -#define SEMC_NANDCR3_NDOPT3_MASK (0x4U) -#define SEMC_NANDCR3_NDOPT3_SHIFT (2U) -#define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) -/*! @} */ - -/*! @name NORCR0 - NOR control register 0 */ -/*! @{ */ -#define SEMC_NORCR0_PS_MASK (0x1U) -#define SEMC_NORCR0_PS_SHIFT (0U) -#define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) -#define SEMC_NORCR0_BL_MASK (0x70U) -#define SEMC_NORCR0_BL_SHIFT (4U) -#define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) -#define SEMC_NORCR0_AM_MASK (0x300U) -#define SEMC_NORCR0_AM_SHIFT (8U) -#define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) -#define SEMC_NORCR0_ADVP_MASK (0x400U) -#define SEMC_NORCR0_ADVP_SHIFT (10U) -#define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) -#define SEMC_NORCR0_COL_MASK (0xF000U) -#define SEMC_NORCR0_COL_SHIFT (12U) -#define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) -/*! @} */ - -/*! @name NORCR1 - NOR control register 1 */ -/*! @{ */ -#define SEMC_NORCR1_CES_MASK (0xFU) -#define SEMC_NORCR1_CES_SHIFT (0U) -#define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) -#define SEMC_NORCR1_CEH_MASK (0xF0U) -#define SEMC_NORCR1_CEH_SHIFT (4U) -#define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK) -#define SEMC_NORCR1_AS_MASK (0xF00U) -#define SEMC_NORCR1_AS_SHIFT (8U) -#define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK) -#define SEMC_NORCR1_AH_MASK (0xF000U) -#define SEMC_NORCR1_AH_SHIFT (12U) -#define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK) -#define SEMC_NORCR1_WEL_MASK (0xF0000U) -#define SEMC_NORCR1_WEL_SHIFT (16U) -#define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK) -#define SEMC_NORCR1_WEH_MASK (0xF00000U) -#define SEMC_NORCR1_WEH_SHIFT (20U) -#define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK) -#define SEMC_NORCR1_REL_MASK (0xF000000U) -#define SEMC_NORCR1_REL_SHIFT (24U) -#define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK) -#define SEMC_NORCR1_REH_MASK (0xF0000000U) -#define SEMC_NORCR1_REH_SHIFT (28U) -#define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) -/*! @} */ - -/*! @name NORCR2 - NOR control register 2 */ -/*! @{ */ -#define SEMC_NORCR2_WDS_MASK (0xFU) -#define SEMC_NORCR2_WDS_SHIFT (0U) -#define SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK) -#define SEMC_NORCR2_WDH_MASK (0xF0U) -#define SEMC_NORCR2_WDH_SHIFT (4U) -#define SEMC_NORCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK) -#define SEMC_NORCR2_TA_MASK (0xF00U) -#define SEMC_NORCR2_TA_SHIFT (8U) -#define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK) -#define SEMC_NORCR2_AWDH_MASK (0xF000U) -#define SEMC_NORCR2_AWDH_SHIFT (12U) -#define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK) -#define SEMC_NORCR2_LC_MASK (0xF0000U) -#define SEMC_NORCR2_LC_SHIFT (16U) -#define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK) -#define SEMC_NORCR2_RD_MASK (0xF00000U) -#define SEMC_NORCR2_RD_SHIFT (20U) -#define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK) -#define SEMC_NORCR2_CEITV_MASK (0xF000000U) -#define SEMC_NORCR2_CEITV_SHIFT (24U) -#define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) -/*! @} */ - -/*! @name SRAMCR0 - SRAM control register 0 */ -/*! @{ */ -#define SEMC_SRAMCR0_PS_MASK (0x1U) -#define SEMC_SRAMCR0_PS_SHIFT (0U) -#define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) -#define SEMC_SRAMCR0_BL_MASK (0x70U) -#define SEMC_SRAMCR0_BL_SHIFT (4U) -#define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) -#define SEMC_SRAMCR0_AM_MASK (0x300U) -#define SEMC_SRAMCR0_AM_SHIFT (8U) -#define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) -#define SEMC_SRAMCR0_ADVP_MASK (0x400U) -#define SEMC_SRAMCR0_ADVP_SHIFT (10U) -#define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) -#define SEMC_SRAMCR0_COL_MASK (0xF000U) -#define SEMC_SRAMCR0_COL_SHIFT (12U) -#define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) -/*! @} */ - -/*! @name SRAMCR1 - SRAM control register 1 */ -/*! @{ */ -#define SEMC_SRAMCR1_CES_MASK (0xFU) -#define SEMC_SRAMCR1_CES_SHIFT (0U) -#define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) -#define SEMC_SRAMCR1_CEH_MASK (0xF0U) -#define SEMC_SRAMCR1_CEH_SHIFT (4U) -#define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK) -#define SEMC_SRAMCR1_AS_MASK (0xF00U) -#define SEMC_SRAMCR1_AS_SHIFT (8U) -#define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK) -#define SEMC_SRAMCR1_AH_MASK (0xF000U) -#define SEMC_SRAMCR1_AH_SHIFT (12U) -#define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK) -#define SEMC_SRAMCR1_WEL_MASK (0xF0000U) -#define SEMC_SRAMCR1_WEL_SHIFT (16U) -#define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK) -#define SEMC_SRAMCR1_WEH_MASK (0xF00000U) -#define SEMC_SRAMCR1_WEH_SHIFT (20U) -#define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK) -#define SEMC_SRAMCR1_REL_MASK (0xF000000U) -#define SEMC_SRAMCR1_REL_SHIFT (24U) -#define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK) -#define SEMC_SRAMCR1_REH_MASK (0xF0000000U) -#define SEMC_SRAMCR1_REH_SHIFT (28U) -#define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) -/*! @} */ - -/*! @name SRAMCR2 - SRAM control register 2 */ -/*! @{ */ -#define SEMC_SRAMCR2_WDS_MASK (0xFU) -#define SEMC_SRAMCR2_WDS_SHIFT (0U) -#define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) -#define SEMC_SRAMCR2_WDH_MASK (0xF0U) -#define SEMC_SRAMCR2_WDH_SHIFT (4U) -#define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK) -#define SEMC_SRAMCR2_TA_MASK (0xF00U) -#define SEMC_SRAMCR2_TA_SHIFT (8U) -#define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK) -#define SEMC_SRAMCR2_AWDH_MASK (0xF000U) -#define SEMC_SRAMCR2_AWDH_SHIFT (12U) -#define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK) -#define SEMC_SRAMCR2_LC_MASK (0xF0000U) -#define SEMC_SRAMCR2_LC_SHIFT (16U) -#define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK) -#define SEMC_SRAMCR2_RD_MASK (0xF00000U) -#define SEMC_SRAMCR2_RD_SHIFT (20U) -#define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK) -#define SEMC_SRAMCR2_CEITV_MASK (0xF000000U) -#define SEMC_SRAMCR2_CEITV_SHIFT (24U) -#define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) -/*! @} */ - -/*! @name DBICR0 - DBI-B control register 0 */ -/*! @{ */ -#define SEMC_DBICR0_PS_MASK (0x1U) -#define SEMC_DBICR0_PS_SHIFT (0U) -#define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) -#define SEMC_DBICR0_BL_MASK (0x70U) -#define SEMC_DBICR0_BL_SHIFT (4U) -#define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) -#define SEMC_DBICR0_COL_MASK (0xF000U) -#define SEMC_DBICR0_COL_SHIFT (12U) -#define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) -/*! @} */ - -/*! @name DBICR1 - DBI-B control register 1 */ -/*! @{ */ -#define SEMC_DBICR1_CES_MASK (0xFU) -#define SEMC_DBICR1_CES_SHIFT (0U) -#define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) -#define SEMC_DBICR1_CEH_MASK (0xF0U) -#define SEMC_DBICR1_CEH_SHIFT (4U) -#define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK) -#define SEMC_DBICR1_WEL_MASK (0xF00U) -#define SEMC_DBICR1_WEL_SHIFT (8U) -#define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK) -#define SEMC_DBICR1_WEH_MASK (0xF000U) -#define SEMC_DBICR1_WEH_SHIFT (12U) -#define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK) -#define SEMC_DBICR1_REL_MASK (0xF0000U) -#define SEMC_DBICR1_REL_SHIFT (16U) -#define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK) -#define SEMC_DBICR1_REH_MASK (0xF00000U) -#define SEMC_DBICR1_REH_SHIFT (20U) -#define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK) -#define SEMC_DBICR1_CEITV_MASK (0xF000000U) -#define SEMC_DBICR1_CEITV_SHIFT (24U) -#define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK) -#define SEMC_DBICR1_REL2_MASK (0x30000000U) -#define SEMC_DBICR1_REL2_SHIFT (28U) -#define SEMC_DBICR1_REL2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK) -#define SEMC_DBICR1_REH2_MASK (0xC0000000U) -#define SEMC_DBICR1_REH2_SHIFT (30U) -#define SEMC_DBICR1_REH2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK) -/*! @} */ - -/*! @name IPCR0 - IP Command control register 0 */ -/*! @{ */ -#define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU) -#define SEMC_IPCR0_SA_SHIFT (0U) -#define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) -/*! @} */ - -/*! @name IPCR1 - IP Command control register 1 */ -/*! @{ */ -#define SEMC_IPCR1_DATSZ_MASK (0x7U) -#define SEMC_IPCR1_DATSZ_SHIFT (0U) -#define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) -/*! @} */ - -/*! @name IPCR2 - IP Command control register 2 */ -/*! @{ */ -#define SEMC_IPCR2_BM0_MASK (0x1U) -#define SEMC_IPCR2_BM0_SHIFT (0U) -#define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) -#define SEMC_IPCR2_BM1_MASK (0x2U) -#define SEMC_IPCR2_BM1_SHIFT (1U) -#define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) -#define SEMC_IPCR2_BM2_MASK (0x4U) -#define SEMC_IPCR2_BM2_SHIFT (2U) -#define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) -#define SEMC_IPCR2_BM3_MASK (0x8U) -#define SEMC_IPCR2_BM3_SHIFT (3U) -#define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) -/*! @} */ - -/*! @name IPCMD - IP Command register */ -/*! @{ */ -#define SEMC_IPCMD_CMD_MASK (0xFFFFU) -#define SEMC_IPCMD_CMD_SHIFT (0U) -#define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) -#define SEMC_IPCMD_KEY_MASK (0xFFFF0000U) -#define SEMC_IPCMD_KEY_SHIFT (16U) -#define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) -/*! @} */ - -/*! @name IPTXDAT - TX DATA register (for IP Command) */ -/*! @{ */ -#define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU) -#define SEMC_IPTXDAT_DAT_SHIFT (0U) -#define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK) -/*! @} */ - -/*! @name IPRXDAT - RX DATA register (for IP Command) */ -/*! @{ */ -#define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU) -#define SEMC_IPRXDAT_DAT_SHIFT (0U) -#define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK) -/*! @} */ - -/*! @name STS0 - Status register 0 */ -/*! @{ */ -#define SEMC_STS0_IDLE_MASK (0x1U) -#define SEMC_STS0_IDLE_SHIFT (0U) -#define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) -#define SEMC_STS0_NARDY_MASK (0x2U) -#define SEMC_STS0_NARDY_SHIFT (1U) -#define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) -/*! @} */ - -/*! @name STS2 - Status register 2 */ -/*! @{ */ -#define SEMC_STS2_NDWRPEND_MASK (0x8U) -#define SEMC_STS2_NDWRPEND_SHIFT (3U) -#define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) -/*! @} */ - -/*! @name STS12 - Status register 12 */ -/*! @{ */ -#define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU) -#define SEMC_STS12_NDADDR_SHIFT (0U) -#define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SEMC_Register_Masks */ - - -/* SEMC - Peripheral instance base addresses */ -/** Peripheral SEMC base address */ -#define SEMC_BASE (0x402F0000u) -/** Peripheral SEMC base pointer */ -#define SEMC ((SEMC_Type *)SEMC_BASE) -/** Array initializer of SEMC peripheral base addresses */ -#define SEMC_BASE_ADDRS { SEMC_BASE } -/** Array initializer of SEMC peripheral base pointers */ -#define SEMC_BASE_PTRS { SEMC } -/** Interrupt vectors for the SEMC peripheral type */ -#define SEMC_IRQS { SEMC_IRQn } - -/*! - * @} - */ /* end of group SEMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SNVS Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer - * @{ - */ - -/** SNVS - Register Layout Typedef */ -typedef struct { - __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ - __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */ - __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */ - __IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */ - __IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */ - __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ - __IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */ - __IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */ - __I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */ - __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */ - __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */ - __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ - __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ - __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ - __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ - __IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */ - __IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */ - uint8_t RESERVED_0[4]; - __IO uint32_t LPTDCR; /**< SNVS_LP Tamper Detectors Configuration Register, offset: 0x48 */ - __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ - __IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */ - __IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */ - __IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */ - __I uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ - __I uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ - __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */ - __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */ - __IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */ - uint8_t RESERVED_1[4]; - __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ - uint8_t RESERVED_2[96]; - __IO uint32_t LPGPR[8]; /**< SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_3[2776]; - __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ - __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ -} SNVS_Type; - -/* ---------------------------------------------------------------------------- - -- SNVS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SNVS_Register_Masks SNVS Register Masks - * @{ - */ - -/*! @name HPLR - SNVS_HP Lock Register */ -/*! @{ */ -#define SNVS_HPLR_ZMK_WSL_MASK (0x1U) -#define SNVS_HPLR_ZMK_WSL_SHIFT (0U) -#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) -#define SNVS_HPLR_ZMK_RSL_MASK (0x2U) -#define SNVS_HPLR_ZMK_RSL_SHIFT (1U) -#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) -#define SNVS_HPLR_SRTC_SL_MASK (0x4U) -#define SNVS_HPLR_SRTC_SL_SHIFT (2U) -#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) -#define SNVS_HPLR_LPCALB_SL_MASK (0x8U) -#define SNVS_HPLR_LPCALB_SL_SHIFT (3U) -#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) -#define SNVS_HPLR_MC_SL_MASK (0x10U) -#define SNVS_HPLR_MC_SL_SHIFT (4U) -#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) -#define SNVS_HPLR_GPR_SL_MASK (0x20U) -#define SNVS_HPLR_GPR_SL_SHIFT (5U) -#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) -#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U) -#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U) -#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) -#define SNVS_HPLR_LPTDCR_SL_MASK (0x100U) -#define SNVS_HPLR_LPTDCR_SL_SHIFT (8U) -#define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK) -#define SNVS_HPLR_MKS_SL_MASK (0x200U) -#define SNVS_HPLR_MKS_SL_SHIFT (9U) -#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) -#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U) -#define SNVS_HPLR_HPSVCR_L_SHIFT (16U) -#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) -#define SNVS_HPLR_HPSICR_L_MASK (0x20000U) -#define SNVS_HPLR_HPSICR_L_SHIFT (17U) -#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) -#define SNVS_HPLR_HAC_L_MASK (0x40000U) -#define SNVS_HPLR_HAC_L_SHIFT (18U) -#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) -/*! @} */ - -/*! @name HPCOMR - SNVS_HP Command Register */ -/*! @{ */ -#define SNVS_HPCOMR_SSM_ST_MASK (0x1U) -#define SNVS_HPCOMR_SSM_ST_SHIFT (0U) -#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) -#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) -#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) -#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) -#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) -#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) -#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) -#define SNVS_HPCOMR_LP_SWR_MASK (0x10U) -#define SNVS_HPCOMR_LP_SWR_SHIFT (4U) -#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) -#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) -#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) -#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) -#define SNVS_HPCOMR_SW_SV_MASK (0x100U) -#define SNVS_HPCOMR_SW_SV_SHIFT (8U) -#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK) -#define SNVS_HPCOMR_SW_FSV_MASK (0x200U) -#define SNVS_HPCOMR_SW_FSV_SHIFT (9U) -#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK) -#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U) -#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U) -#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) -#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) -#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) -#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) -#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) -#define SNVS_HPCOMR_MKS_EN_SHIFT (13U) -#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) -#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) -#define SNVS_HPCOMR_HAC_EN_SHIFT (16U) -#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) -#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) -#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) -#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) -#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) -#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) -#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) -#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) -#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U) -#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK) -#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) -#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) -#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) -/*! @} */ - -/*! @name HPCR - SNVS_HP Control Register */ -/*! @{ */ -#define SNVS_HPCR_RTC_EN_MASK (0x1U) -#define SNVS_HPCR_RTC_EN_SHIFT (0U) -#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) -#define SNVS_HPCR_HPTA_EN_MASK (0x2U) -#define SNVS_HPCR_HPTA_EN_SHIFT (1U) -#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) -#define SNVS_HPCR_DIS_PI_MASK (0x4U) -#define SNVS_HPCR_DIS_PI_SHIFT (2U) -#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) -#define SNVS_HPCR_PI_EN_MASK (0x8U) -#define SNVS_HPCR_PI_EN_SHIFT (3U) -#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) -#define SNVS_HPCR_PI_FREQ_MASK (0xF0U) -#define SNVS_HPCR_PI_FREQ_SHIFT (4U) -#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) -#define SNVS_HPCR_HPCALB_EN_MASK (0x100U) -#define SNVS_HPCR_HPCALB_EN_SHIFT (8U) -#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) -#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) -#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) -#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) -#define SNVS_HPCR_HP_TS_MASK (0x10000U) -#define SNVS_HPCR_HP_TS_SHIFT (16U) -#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) -#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) -#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) -#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) -#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) -#define SNVS_HPCR_BTN_MASK_SHIFT (27U) -#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) -/*! @} */ - -/*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ -/*! @{ */ -#define SNVS_HPSICR_SV0_EN_MASK (0x1U) -#define SNVS_HPSICR_SV0_EN_SHIFT (0U) -#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) -#define SNVS_HPSICR_SV1_EN_MASK (0x2U) -#define SNVS_HPSICR_SV1_EN_SHIFT (1U) -#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK) -#define SNVS_HPSICR_SV2_EN_MASK (0x4U) -#define SNVS_HPSICR_SV2_EN_SHIFT (2U) -#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK) -#define SNVS_HPSICR_SV3_EN_MASK (0x8U) -#define SNVS_HPSICR_SV3_EN_SHIFT (3U) -#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK) -#define SNVS_HPSICR_SV4_EN_MASK (0x10U) -#define SNVS_HPSICR_SV4_EN_SHIFT (4U) -#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK) -#define SNVS_HPSICR_SV5_EN_MASK (0x20U) -#define SNVS_HPSICR_SV5_EN_SHIFT (5U) -#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK) -#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) -#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) -#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) -/*! @} */ - -/*! @name HPSVCR - SNVS_HP Security Violation Control Register */ -/*! @{ */ -#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) -#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) -#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) -#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U) -#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U) -#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK) -#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U) -#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U) -#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK) -#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U) -#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U) -#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK) -#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U) -#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U) -#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK) -#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U) -#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U) -#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK) -#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) -#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) -#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) -/*! @} */ - -/*! @name HPSR - SNVS_HP Status Register */ -/*! @{ */ -#define SNVS_HPSR_HPTA_MASK (0x1U) -#define SNVS_HPSR_HPTA_SHIFT (0U) -#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) -#define SNVS_HPSR_PI_MASK (0x2U) -#define SNVS_HPSR_PI_SHIFT (1U) -#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) -#define SNVS_HPSR_LPDIS_MASK (0x10U) -#define SNVS_HPSR_LPDIS_SHIFT (4U) -#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK) -#define SNVS_HPSR_BTN_MASK (0x40U) -#define SNVS_HPSR_BTN_SHIFT (6U) -#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) -#define SNVS_HPSR_BI_MASK (0x80U) -#define SNVS_HPSR_BI_SHIFT (7U) -#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) -#define SNVS_HPSR_SSM_STATE_MASK (0xF00U) -#define SNVS_HPSR_SSM_STATE_SHIFT (8U) -#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) -#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U) -#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U) -#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK) -#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U) -#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U) -#define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK) -#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) -#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) -#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) -#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) -#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) -#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) -/*! @} */ - -/*! @name HPSVSR - SNVS_HP Security Violation Status Register */ -/*! @{ */ -#define SNVS_HPSVSR_SV0_MASK (0x1U) -#define SNVS_HPSVSR_SV0_SHIFT (0U) -#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) -#define SNVS_HPSVSR_SV1_MASK (0x2U) -#define SNVS_HPSVSR_SV1_SHIFT (1U) -#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK) -#define SNVS_HPSVSR_SV2_MASK (0x4U) -#define SNVS_HPSVSR_SV2_SHIFT (2U) -#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK) -#define SNVS_HPSVSR_SV3_MASK (0x8U) -#define SNVS_HPSVSR_SV3_SHIFT (3U) -#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK) -#define SNVS_HPSVSR_SV4_MASK (0x10U) -#define SNVS_HPSVSR_SV4_SHIFT (4U) -#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK) -#define SNVS_HPSVSR_SV5_MASK (0x20U) -#define SNVS_HPSVSR_SV5_SHIFT (5U) -#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK) -#define SNVS_HPSVSR_SW_SV_MASK (0x2000U) -#define SNVS_HPSVSR_SW_SV_SHIFT (13U) -#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK) -#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U) -#define SNVS_HPSVSR_SW_FSV_SHIFT (14U) -#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK) -#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U) -#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U) -#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK) -#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U) -#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U) -#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) -#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) -#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) -#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) -#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) -#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) -#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) -/*! @} */ - -/*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ -/*! @{ */ -#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) -#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) -#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) -/*! @} */ - -/*! @name HPHACR - SNVS_HP High Assurance Counter Register */ -/*! @{ */ -#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) -#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) -#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) -/*! @} */ - -/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ -/*! @{ */ -#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) -#define SNVS_HPRTCMR_RTC_SHIFT (0U) -#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) -/*! @} */ - -/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ -/*! @{ */ -#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) -#define SNVS_HPRTCLR_RTC_SHIFT (0U) -#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) -/*! @} */ - -/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ -/*! @{ */ -#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) -#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) -#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) -/*! @} */ - -/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ -/*! @{ */ -#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) -#define SNVS_HPTALR_HPTA_LS_SHIFT (0U) -#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) -/*! @} */ - -/*! @name LPLR - SNVS_LP Lock Register */ -/*! @{ */ -#define SNVS_LPLR_ZMK_WHL_MASK (0x1U) -#define SNVS_LPLR_ZMK_WHL_SHIFT (0U) -#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) -#define SNVS_LPLR_ZMK_RHL_MASK (0x2U) -#define SNVS_LPLR_ZMK_RHL_SHIFT (1U) -#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) -#define SNVS_LPLR_SRTC_HL_MASK (0x4U) -#define SNVS_LPLR_SRTC_HL_SHIFT (2U) -#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) -#define SNVS_LPLR_LPCALB_HL_MASK (0x8U) -#define SNVS_LPLR_LPCALB_HL_SHIFT (3U) -#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) -#define SNVS_LPLR_MC_HL_MASK (0x10U) -#define SNVS_LPLR_MC_HL_SHIFT (4U) -#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) -#define SNVS_LPLR_GPR_HL_MASK (0x20U) -#define SNVS_LPLR_GPR_HL_SHIFT (5U) -#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) -#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U) -#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U) -#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) -#define SNVS_LPLR_LPTDCR_HL_MASK (0x100U) -#define SNVS_LPLR_LPTDCR_HL_SHIFT (8U) -#define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK) -#define SNVS_LPLR_MKS_HL_MASK (0x200U) -#define SNVS_LPLR_MKS_HL_SHIFT (9U) -#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) -/*! @} */ - -/*! @name LPCR - SNVS_LP Control Register */ -/*! @{ */ -#define SNVS_LPCR_SRTC_ENV_MASK (0x1U) -#define SNVS_LPCR_SRTC_ENV_SHIFT (0U) -#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) -#define SNVS_LPCR_LPTA_EN_MASK (0x2U) -#define SNVS_LPCR_LPTA_EN_SHIFT (1U) -#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) -#define SNVS_LPCR_MC_ENV_MASK (0x4U) -#define SNVS_LPCR_MC_ENV_SHIFT (2U) -#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) -#define SNVS_LPCR_LPWUI_EN_MASK (0x8U) -#define SNVS_LPCR_LPWUI_EN_SHIFT (3U) -#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) -#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) -#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) -#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) -#define SNVS_LPCR_DP_EN_MASK (0x20U) -#define SNVS_LPCR_DP_EN_SHIFT (5U) -#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) -#define SNVS_LPCR_TOP_MASK (0x40U) -#define SNVS_LPCR_TOP_SHIFT (6U) -#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) -#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) -#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) -#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) -#define SNVS_LPCR_LPCALB_EN_MASK (0x100U) -#define SNVS_LPCR_LPCALB_EN_SHIFT (8U) -#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) -#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) -#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U) -#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) -#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) -#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) -#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) -#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) -#define SNVS_LPCR_DEBOUNCE_SHIFT (18U) -#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) -#define SNVS_LPCR_ON_TIME_MASK (0x300000U) -#define SNVS_LPCR_ON_TIME_SHIFT (20U) -#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) -#define SNVS_LPCR_PK_EN_MASK (0x400000U) -#define SNVS_LPCR_PK_EN_SHIFT (22U) -#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) -#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) -#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) -#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) -#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) -#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) -#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) -/*! @} */ - -/*! @name LPMKCR - SNVS_LP Master Key Control Register */ -/*! @{ */ -#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) -#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) -#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) -#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) -#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) -#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) -#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) -#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) -#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) -#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) -#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) -#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) -#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) -#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) -#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) -/*! @} */ - -/*! @name LPSVCR - SNVS_LP Security Violation Control Register */ -/*! @{ */ -#define SNVS_LPSVCR_SV0_EN_MASK (0x1U) -#define SNVS_LPSVCR_SV0_EN_SHIFT (0U) -#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) -#define SNVS_LPSVCR_SV1_EN_MASK (0x2U) -#define SNVS_LPSVCR_SV1_EN_SHIFT (1U) -#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK) -#define SNVS_LPSVCR_SV2_EN_MASK (0x4U) -#define SNVS_LPSVCR_SV2_EN_SHIFT (2U) -#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK) -#define SNVS_LPSVCR_SV3_EN_MASK (0x8U) -#define SNVS_LPSVCR_SV3_EN_SHIFT (3U) -#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK) -#define SNVS_LPSVCR_SV4_EN_MASK (0x10U) -#define SNVS_LPSVCR_SV4_EN_SHIFT (4U) -#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK) -#define SNVS_LPSVCR_SV5_EN_MASK (0x20U) -#define SNVS_LPSVCR_SV5_EN_SHIFT (5U) -#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) -/*! @} */ - -/*! @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */ -/*! @{ */ -#define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U) -#define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U) -#define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK) -#define SNVS_LPTDCR_MCR_EN_MASK (0x4U) -#define SNVS_LPTDCR_MCR_EN_SHIFT (2U) -#define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK) -#define SNVS_LPTDCR_ET1_EN_MASK (0x200U) -#define SNVS_LPTDCR_ET1_EN_SHIFT (9U) -#define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK) -#define SNVS_LPTDCR_ET1P_MASK (0x800U) -#define SNVS_LPTDCR_ET1P_SHIFT (11U) -#define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK) -#define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U) -#define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U) -#define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK) -#define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U) -#define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U) -#define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK) -#define SNVS_LPTDCR_OSCB_MASK (0x10000000U) -#define SNVS_LPTDCR_OSCB_SHIFT (28U) -#define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK) -/*! @} */ - -/*! @name LPSR - SNVS_LP Status Register */ -/*! @{ */ -#define SNVS_LPSR_LPTA_MASK (0x1U) -#define SNVS_LPSR_LPTA_SHIFT (0U) -#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) -#define SNVS_LPSR_SRTCR_MASK (0x2U) -#define SNVS_LPSR_SRTCR_SHIFT (1U) -#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) -#define SNVS_LPSR_MCR_MASK (0x4U) -#define SNVS_LPSR_MCR_SHIFT (2U) -#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) -#define SNVS_LPSR_PGD_MASK (0x8U) -#define SNVS_LPSR_PGD_SHIFT (3U) -#define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK) -#define SNVS_LPSR_ET1D_MASK (0x200U) -#define SNVS_LPSR_ET1D_SHIFT (9U) -#define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK) -#define SNVS_LPSR_ESVD_MASK (0x10000U) -#define SNVS_LPSR_ESVD_SHIFT (16U) -#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) -#define SNVS_LPSR_EO_MASK (0x20000U) -#define SNVS_LPSR_EO_SHIFT (17U) -#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) -#define SNVS_LPSR_SPO_MASK (0x40000U) -#define SNVS_LPSR_SPO_SHIFT (18U) -#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) -#define SNVS_LPSR_SED_MASK (0x100000U) -#define SNVS_LPSR_SED_SHIFT (20U) -#define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK) -#define SNVS_LPSR_LPNS_MASK (0x40000000U) -#define SNVS_LPSR_LPNS_SHIFT (30U) -#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) -#define SNVS_LPSR_LPS_MASK (0x80000000U) -#define SNVS_LPSR_LPS_SHIFT (31U) -#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) -/*! @} */ - -/*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ -/*! @{ */ -#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) -#define SNVS_LPSRTCMR_SRTC_SHIFT (0U) -#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) -/*! @} */ - -/*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ -/*! @{ */ -#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) -#define SNVS_LPSRTCLR_SRTC_SHIFT (0U) -#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) -/*! @} */ - -/*! @name LPTAR - SNVS_LP Time Alarm Register */ -/*! @{ */ -#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) -#define SNVS_LPTAR_LPTA_SHIFT (0U) -#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) -/*! @} */ - -/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ -/*! @{ */ -#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) -#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) -#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) -#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) -#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) -#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) -/*! @} */ - -/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ -/*! @{ */ -#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) -#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) -#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) -/*! @} */ - -/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ -/*! @{ */ -#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) -#define SNVS_LPPGDR_PGD_SHIFT (0U) -#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) -/*! @} */ - -/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ -/*! @{ */ -#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) -#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) -#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) -/*! @} */ - -/*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ -/*! @{ */ -#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) -#define SNVS_LPZMKR_ZMK_SHIFT (0U) -#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) -/*! @} */ - -/* The count of SNVS_LPZMKR */ -#define SNVS_LPZMKR_COUNT (8U) - -/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ -/*! @{ */ -#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) -#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) -#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) -/*! @} */ - -/* The count of SNVS_LPGPR_ALIAS */ -#define SNVS_LPGPR_ALIAS_COUNT (4U) - -/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */ -/*! @{ */ -#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) -#define SNVS_LPGPR_GPR_SHIFT (0U) -#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) -/*! @} */ - -/* The count of SNVS_LPGPR */ -#define SNVS_LPGPR_COUNT (8U) - -/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ -/*! @{ */ -#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) -#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) -#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) -#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) -#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) -#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) -#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) -#define SNVS_HPVIDR1_IP_ID_SHIFT (16U) -#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) -/*! @} */ - -/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ -/*! @{ */ -#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) -#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) -#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) -#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) -#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) -#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) -#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) -#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) -#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) -#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) -#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) -#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SNVS_Register_Masks */ - - -/* SNVS - Peripheral instance base addresses */ -/** Peripheral SNVS base address */ -#define SNVS_BASE (0x400D4000u) -/** Peripheral SNVS base pointer */ -#define SNVS ((SNVS_Type *)SNVS_BASE) -/** Array initializer of SNVS peripheral base addresses */ -#define SNVS_BASE_ADDRS { SNVS_BASE } -/** Array initializer of SNVS peripheral base pointers */ -#define SNVS_BASE_PTRS { SNVS } -/** Interrupt vectors for the SNVS peripheral type */ -#define SNVS_IRQS { SNVS_LP_WRAPPER_IRQn } -#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn } -#define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn } - -/*! - * @} - */ /* end of group SNVS_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPDIF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer - * @{ - */ - -/** SPDIF - Register Layout Typedef */ -typedef struct { - __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ - __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ - __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ - __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ - union { /* offset: 0x10 */ - __O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ - __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ - }; - __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ - __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ - __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ - __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ - __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ - __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ - __O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ - __O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ - __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ - __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ - uint8_t RESERVED_0[8]; - __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ - uint8_t RESERVED_1[8]; - __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ -} SPDIF_Type; - -/* ---------------------------------------------------------------------------- - -- SPDIF Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPDIF_Register_Masks SPDIF Register Masks - * @{ - */ - -/*! @name SCR - SPDIF Configuration Register */ -/*! @{ */ -#define SPDIF_SCR_USRC_SEL_MASK (0x3U) -#define SPDIF_SCR_USRC_SEL_SHIFT (0U) -#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) -#define SPDIF_SCR_TXSEL_MASK (0x1CU) -#define SPDIF_SCR_TXSEL_SHIFT (2U) -#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) -#define SPDIF_SCR_VALCTRL_MASK (0x20U) -#define SPDIF_SCR_VALCTRL_SHIFT (5U) -#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) -#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) -#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) -#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) -#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) -#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) -#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) -#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) -#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) -#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) -#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) -#define SPDIF_SCR_SOFT_RESET_SHIFT (12U) -#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) -#define SPDIF_SCR_LOW_POWER_MASK (0x2000U) -#define SPDIF_SCR_LOW_POWER_SHIFT (13U) -#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) -#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) -#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) -#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) -#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) -#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) -#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) -#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) -#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) -#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) -#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) -#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) -#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) -#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) -#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) -#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) -#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) -#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) -#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) -#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) -#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) -#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) -/*! @} */ - -/*! @name SRCD - CDText Control Register */ -/*! @{ */ -#define SPDIF_SRCD_USYNCMODE_MASK (0x2U) -#define SPDIF_SRCD_USYNCMODE_SHIFT (1U) -#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) -/*! @} */ - -/*! @name SRPC - PhaseConfig Register */ -/*! @{ */ -#define SPDIF_SRPC_GAINSEL_MASK (0x38U) -#define SPDIF_SRPC_GAINSEL_SHIFT (3U) -#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) -#define SPDIF_SRPC_LOCK_MASK (0x40U) -#define SPDIF_SRPC_LOCK_SHIFT (6U) -#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) -#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) -#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) -#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) -/*! @} */ - -/*! @name SIE - InterruptEn Register */ -/*! @{ */ -#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) -#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) -#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) -#define SPDIF_SIE_TXEM_MASK (0x2U) -#define SPDIF_SIE_TXEM_SHIFT (1U) -#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) -#define SPDIF_SIE_LOCKLOSS_MASK (0x4U) -#define SPDIF_SIE_LOCKLOSS_SHIFT (2U) -#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) -#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) -#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) -#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) -#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) -#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) -#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) -#define SPDIF_SIE_UQERR_MASK (0x20U) -#define SPDIF_SIE_UQERR_SHIFT (5U) -#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) -#define SPDIF_SIE_UQSYNC_MASK (0x40U) -#define SPDIF_SIE_UQSYNC_SHIFT (6U) -#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) -#define SPDIF_SIE_QRXOV_MASK (0x80U) -#define SPDIF_SIE_QRXOV_SHIFT (7U) -#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) -#define SPDIF_SIE_QRXFUL_MASK (0x100U) -#define SPDIF_SIE_QRXFUL_SHIFT (8U) -#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) -#define SPDIF_SIE_URXOV_MASK (0x200U) -#define SPDIF_SIE_URXOV_SHIFT (9U) -#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) -#define SPDIF_SIE_URXFUL_MASK (0x400U) -#define SPDIF_SIE_URXFUL_SHIFT (10U) -#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) -#define SPDIF_SIE_BITERR_MASK (0x4000U) -#define SPDIF_SIE_BITERR_SHIFT (14U) -#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) -#define SPDIF_SIE_SYMERR_MASK (0x8000U) -#define SPDIF_SIE_SYMERR_SHIFT (15U) -#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) -#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) -#define SPDIF_SIE_VALNOGOOD_SHIFT (16U) -#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) -#define SPDIF_SIE_CNEW_MASK (0x20000U) -#define SPDIF_SIE_CNEW_SHIFT (17U) -#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) -#define SPDIF_SIE_TXRESYN_MASK (0x40000U) -#define SPDIF_SIE_TXRESYN_SHIFT (18U) -#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) -#define SPDIF_SIE_TXUNOV_MASK (0x80000U) -#define SPDIF_SIE_TXUNOV_SHIFT (19U) -#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) -#define SPDIF_SIE_LOCK_MASK (0x100000U) -#define SPDIF_SIE_LOCK_SHIFT (20U) -#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) -/*! @} */ - -/*! @name SIC - InterruptClear Register */ -/*! @{ */ -#define SPDIF_SIC_LOCKLOSS_MASK (0x4U) -#define SPDIF_SIC_LOCKLOSS_SHIFT (2U) -#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) -#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) -#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) -#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) -#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) -#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) -#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) -#define SPDIF_SIC_UQERR_MASK (0x20U) -#define SPDIF_SIC_UQERR_SHIFT (5U) -#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) -#define SPDIF_SIC_UQSYNC_MASK (0x40U) -#define SPDIF_SIC_UQSYNC_SHIFT (6U) -#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) -#define SPDIF_SIC_QRXOV_MASK (0x80U) -#define SPDIF_SIC_QRXOV_SHIFT (7U) -#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) -#define SPDIF_SIC_URXOV_MASK (0x200U) -#define SPDIF_SIC_URXOV_SHIFT (9U) -#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) -#define SPDIF_SIC_BITERR_MASK (0x4000U) -#define SPDIF_SIC_BITERR_SHIFT (14U) -#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) -#define SPDIF_SIC_SYMERR_MASK (0x8000U) -#define SPDIF_SIC_SYMERR_SHIFT (15U) -#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) -#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) -#define SPDIF_SIC_VALNOGOOD_SHIFT (16U) -#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) -#define SPDIF_SIC_CNEW_MASK (0x20000U) -#define SPDIF_SIC_CNEW_SHIFT (17U) -#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) -#define SPDIF_SIC_TXRESYN_MASK (0x40000U) -#define SPDIF_SIC_TXRESYN_SHIFT (18U) -#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) -#define SPDIF_SIC_TXUNOV_MASK (0x80000U) -#define SPDIF_SIC_TXUNOV_SHIFT (19U) -#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) -#define SPDIF_SIC_LOCK_MASK (0x100000U) -#define SPDIF_SIC_LOCK_SHIFT (20U) -#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) -/*! @} */ - -/*! @name SIS - InterruptStat Register */ -/*! @{ */ -#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) -#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) -#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) -#define SPDIF_SIS_TXEM_MASK (0x2U) -#define SPDIF_SIS_TXEM_SHIFT (1U) -#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) -#define SPDIF_SIS_LOCKLOSS_MASK (0x4U) -#define SPDIF_SIS_LOCKLOSS_SHIFT (2U) -#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) -#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) -#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) -#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) -#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) -#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) -#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) -#define SPDIF_SIS_UQERR_MASK (0x20U) -#define SPDIF_SIS_UQERR_SHIFT (5U) -#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) -#define SPDIF_SIS_UQSYNC_MASK (0x40U) -#define SPDIF_SIS_UQSYNC_SHIFT (6U) -#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) -#define SPDIF_SIS_QRXOV_MASK (0x80U) -#define SPDIF_SIS_QRXOV_SHIFT (7U) -#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) -#define SPDIF_SIS_QRXFUL_MASK (0x100U) -#define SPDIF_SIS_QRXFUL_SHIFT (8U) -#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) -#define SPDIF_SIS_URXOV_MASK (0x200U) -#define SPDIF_SIS_URXOV_SHIFT (9U) -#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) -#define SPDIF_SIS_URXFUL_MASK (0x400U) -#define SPDIF_SIS_URXFUL_SHIFT (10U) -#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) -#define SPDIF_SIS_BITERR_MASK (0x4000U) -#define SPDIF_SIS_BITERR_SHIFT (14U) -#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) -#define SPDIF_SIS_SYMERR_MASK (0x8000U) -#define SPDIF_SIS_SYMERR_SHIFT (15U) -#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) -#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) -#define SPDIF_SIS_VALNOGOOD_SHIFT (16U) -#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) -#define SPDIF_SIS_CNEW_MASK (0x20000U) -#define SPDIF_SIS_CNEW_SHIFT (17U) -#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) -#define SPDIF_SIS_TXRESYN_MASK (0x40000U) -#define SPDIF_SIS_TXRESYN_SHIFT (18U) -#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) -#define SPDIF_SIS_TXUNOV_MASK (0x80000U) -#define SPDIF_SIS_TXUNOV_SHIFT (19U) -#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) -#define SPDIF_SIS_LOCK_MASK (0x100000U) -#define SPDIF_SIS_LOCK_SHIFT (20U) -#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) -/*! @} */ - -/*! @name SRL - SPDIFRxLeft Register */ -/*! @{ */ -#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) -#define SPDIF_SRL_RXDATALEFT_SHIFT (0U) -#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) -/*! @} */ - -/*! @name SRR - SPDIFRxRight Register */ -/*! @{ */ -#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) -#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) -#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) -/*! @} */ - -/*! @name SRCSH - SPDIFRxCChannel_h Register */ -/*! @{ */ -#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) -#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) -#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) -/*! @} */ - -/*! @name SRCSL - SPDIFRxCChannel_l Register */ -/*! @{ */ -#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) -#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) -#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) -/*! @} */ - -/*! @name SRU - UchannelRx Register */ -/*! @{ */ -#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) -#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) -#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) -/*! @} */ - -/*! @name SRQ - QchannelRx Register */ -/*! @{ */ -#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) -#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) -#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) -/*! @} */ - -/*! @name STL - SPDIFTxLeft Register */ -/*! @{ */ -#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) -#define SPDIF_STL_TXDATALEFT_SHIFT (0U) -#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) -/*! @} */ - -/*! @name STR - SPDIFTxRight Register */ -/*! @{ */ -#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) -#define SPDIF_STR_TXDATARIGHT_SHIFT (0U) -#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) -/*! @} */ - -/*! @name STCSCH - SPDIFTxCChannelCons_h Register */ -/*! @{ */ -#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) -#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) -#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) -/*! @} */ - -/*! @name STCSCL - SPDIFTxCChannelCons_l Register */ -/*! @{ */ -#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) -#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) -#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) -/*! @} */ - -/*! @name SRFM - FreqMeas Register */ -/*! @{ */ -#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) -#define SPDIF_SRFM_FREQMEAS_SHIFT (0U) -#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) -/*! @} */ - -/*! @name STC - SPDIFTxClk Register */ -/*! @{ */ -#define SPDIF_STC_TXCLK_DF_MASK (0x7FU) -#define SPDIF_STC_TXCLK_DF_SHIFT (0U) -#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) -#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) -#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) -#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) -#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) -#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) -#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) -#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) -#define SPDIF_STC_SYSCLK_DF_SHIFT (11U) -#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPDIF_Register_Masks */ - - -/* SPDIF - Peripheral instance base addresses */ -/** Peripheral SPDIF base address */ -#define SPDIF_BASE (0x40380000u) -/** Peripheral SPDIF base pointer */ -#define SPDIF ((SPDIF_Type *)SPDIF_BASE) -/** Array initializer of SPDIF peripheral base addresses */ -#define SPDIF_BASE_ADDRS { SPDIF_BASE } -/** Array initializer of SPDIF peripheral base pointers */ -#define SPDIF_BASE_PTRS { SPDIF } -/** Interrupt vectors for the SPDIF peripheral type */ -#define SPDIF_IRQS { SPDIF_IRQn } - -/*! - * @} - */ /* end of group SPDIF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer - * @{ - */ - -/** SRC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ - __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x4 */ - __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x8 */ - uint8_t RESERVED_0[16]; - __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x1C */ - __IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4 */ -} SRC_Type; - -/* ---------------------------------------------------------------------------- - -- SRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SRC_Register_Masks SRC Register Masks - * @{ - */ - -/*! @name SCR - SRC Control Register */ -/*! @{ */ -#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) -#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) -#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) -#define SRC_SCR_CORE0_RST_MASK (0x2000U) -#define SRC_SCR_CORE0_RST_SHIFT (13U) -#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK) -#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U) -#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U) -#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK) -#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U) -#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U) -#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK) -#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) -#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) -#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) -/*! @} */ - -/*! @name SBMR1 - SRC Boot Mode Register 1 */ -/*! @{ */ -#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) -#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) -#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) -#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) -#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U) -#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) -#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) -#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U) -#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) -#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) -#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) -#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) -/*! @} */ - -/*! @name SRSR - SRC Reset Status Register */ -/*! @{ */ -#define SRC_SRSR_IPP_RESET_B_MASK (0x1U) -#define SRC_SRSR_IPP_RESET_B_SHIFT (0U) -#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) -#define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U) -#define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U) -#define SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK) -#define SRC_SRSR_CSU_RESET_B_MASK (0x4U) -#define SRC_SRSR_CSU_RESET_B_SHIFT (2U) -#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) -#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) -#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) -#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) -#define SRC_SRSR_WDOG_RST_B_MASK (0x10U) -#define SRC_SRSR_WDOG_RST_B_SHIFT (4U) -#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK) -#define SRC_SRSR_JTAG_RST_B_MASK (0x20U) -#define SRC_SRSR_JTAG_RST_B_SHIFT (5U) -#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) -#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) -#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) -#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) -#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) -#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) -#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) -#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) -#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) -#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) -/*! @} */ - -/*! @name SBMR2 - SRC Boot Mode Register 2 */ -/*! @{ */ -#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) -#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) -#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) -#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) -#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) -#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) -#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) -#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) -#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) -#define SRC_SBMR2_BMOD_MASK (0x3000000U) -#define SRC_SBMR2_BMOD_SHIFT (24U) -#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) -/*! @} */ - -/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ -/*! @{ */ -#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) -#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) -#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) -#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) -#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) -#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) -/*! @} */ - -/* The count of SRC_GPR */ -#define SRC_GPR_COUNT (10U) - - -/*! - * @} - */ /* end of group SRC_Register_Masks */ - - -/* SRC - Peripheral instance base addresses */ -/** Peripheral SRC base address */ -#define SRC_BASE (0x400F8000u) -/** Peripheral SRC base pointer */ -#define SRC ((SRC_Type *)SRC_BASE) -/** Array initializer of SRC peripheral base addresses */ -#define SRC_BASE_ADDRS { SRC_BASE } -/** Array initializer of SRC peripheral base pointers */ -#define SRC_BASE_PTRS { SRC } -/** Interrupt vectors for the SRC peripheral type */ -#define SRC_IRQS { SRC_IRQn } -/* Backward compatibility */ -#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK -#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT -#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x) -#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK -#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT -#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x) -#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK -#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT -#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x) -#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK -#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT -#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x) -#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK -#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT -#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x) -/* Extra definition */ -#define SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK \ - | SRC_SRSR_JTAG_SW_RST_MASK \ - | SRC_SRSR_JTAG_RST_B_MASK \ - | SRC_SRSR_WDOG_RST_B_MASK \ - | SRC_SRSR_IPP_USER_RESET_B_MASK \ - | SRC_SRSR_CSU_RESET_B_MASK \ - | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK \ - | SRC_SRSR_IPP_RESET_B_MASK) - - -/*! - * @} - */ /* end of group SRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TEMPMON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer - * @{ - */ - -/** TEMPMON - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[384]; - __IO uint32_t TEMPSENSE0; /**< Tempsensor Control Register 0, offset: 0x180 */ - __IO uint32_t TEMPSENSE0_SET; /**< Tempsensor Control Register 0, offset: 0x184 */ - __IO uint32_t TEMPSENSE0_CLR; /**< Tempsensor Control Register 0, offset: 0x188 */ - __IO uint32_t TEMPSENSE0_TOG; /**< Tempsensor Control Register 0, offset: 0x18C */ - __IO uint32_t TEMPSENSE1; /**< Tempsensor Control Register 1, offset: 0x190 */ - __IO uint32_t TEMPSENSE1_SET; /**< Tempsensor Control Register 1, offset: 0x194 */ - __IO uint32_t TEMPSENSE1_CLR; /**< Tempsensor Control Register 1, offset: 0x198 */ - __IO uint32_t TEMPSENSE1_TOG; /**< Tempsensor Control Register 1, offset: 0x19C */ - uint8_t RESERVED_1[240]; - __IO uint32_t TEMPSENSE2; /**< Tempsensor Control Register 2, offset: 0x290 */ - __IO uint32_t TEMPSENSE2_SET; /**< Tempsensor Control Register 2, offset: 0x294 */ - __IO uint32_t TEMPSENSE2_CLR; /**< Tempsensor Control Register 2, offset: 0x298 */ - __IO uint32_t TEMPSENSE2_TOG; /**< Tempsensor Control Register 2, offset: 0x29C */ -} TEMPMON_Type; - -/* ---------------------------------------------------------------------------- - -- TEMPMON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks - * @{ - */ - -/*! @name TEMPSENSE0 - Tempsensor Control Register 0 */ -/*! @{ */ -#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U) -#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U) -#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK) -#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U) -#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U) -#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK) -#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U) -#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U) -#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK) -#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U) -#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U) -#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) -#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U) -#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U) -#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) -/*! @} */ - -/*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */ -/*! @{ */ -#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U) -#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U) -#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK) -#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U) -#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U) -#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK) -#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) -#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U) -#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK) -#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U) -#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U) -#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK) -#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U) -#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U) -#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) -/*! @} */ - -/*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */ -/*! @{ */ -#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U) -#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U) -#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK) -#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U) -#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U) -#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK) -#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) -#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U) -#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK) -#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U) -#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U) -#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK) -#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U) -#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U) -#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) -/*! @} */ - -/*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */ -/*! @{ */ -#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U) -#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U) -#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK) -#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U) -#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U) -#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK) -#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U) -#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U) -#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK) -#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U) -#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U) -#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK) -#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U) -#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U) -#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) -/*! @} */ - -/*! @name TEMPSENSE1 - Tempsensor Control Register 1 */ -/*! @{ */ -#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) -#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) -#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) -/*! @} */ - -/*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */ -/*! @{ */ -#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) -#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) -#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) -/*! @} */ - -/*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */ -/*! @{ */ -#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) -#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) -#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) -/*! @} */ - -/*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */ -/*! @{ */ -#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) -#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) -#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) -/*! @} */ - -/*! @name TEMPSENSE2 - Tempsensor Control Register 2 */ -/*! @{ */ -#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU) -#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U) -#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) -#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U) -#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U) -#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) -/*! @} */ - -/*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */ -/*! @{ */ -#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU) -#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U) -#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) -#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U) -#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U) -#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) -/*! @} */ - -/*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */ -/*! @{ */ -#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU) -#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U) -#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) -#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U) -#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U) -#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) -/*! @} */ - -/*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */ -/*! @{ */ -#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU) -#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U) -#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) -#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U) -#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U) -#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group TEMPMON_Register_Masks */ - - -/* TEMPMON - Peripheral instance base addresses */ -/** Peripheral TEMPMON base address */ -#define TEMPMON_BASE (0x400D8000u) -/** Peripheral TEMPMON base pointer */ -#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE) -/** Array initializer of TEMPMON peripheral base addresses */ -#define TEMPMON_BASE_ADDRS { TEMPMON_BASE } -/** Array initializer of TEMPMON peripheral base pointers */ -#define TEMPMON_BASE_PTRS { TEMPMON } - -/*! - * @} - */ /* end of group TEMPMON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TMR Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer - * @{ - */ - -/** TMR - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x20 */ - __IO uint16_t COMP1; /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */ - __IO uint16_t COMP2; /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */ - __IO uint16_t CAPT; /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */ - __IO uint16_t LOAD; /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */ - __IO uint16_t HOLD; /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */ - __IO uint16_t CNTR; /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */ - __IO uint16_t CTRL; /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */ - __IO uint16_t SCTRL; /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */ - __IO uint16_t CMPLD1; /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */ - __IO uint16_t CMPLD2; /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */ - __IO uint16_t CSCTRL; /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */ - __IO uint16_t FILT; /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */ - __IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */ - uint8_t RESERVED_0[4]; - __IO uint16_t ENBL; /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances */ - } CHANNEL[4]; -} TMR_Type; - -/* ---------------------------------------------------------------------------- - -- TMR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TMR_Register_Masks TMR Register Masks - * @{ - */ - -/*! @name COMP1 - Timer Channel Compare Register 1 */ -/*! @{ */ -#define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU) -#define TMR_COMP1_COMPARISON_1_SHIFT (0U) -#define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK) -/*! @} */ - -/* The count of TMR_COMP1 */ -#define TMR_COMP1_COUNT (4U) - -/*! @name COMP2 - Timer Channel Compare Register 2 */ -/*! @{ */ -#define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU) -#define TMR_COMP2_COMPARISON_2_SHIFT (0U) -#define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK) -/*! @} */ - -/* The count of TMR_COMP2 */ -#define TMR_COMP2_COUNT (4U) - -/*! @name CAPT - Timer Channel Capture Register */ -/*! @{ */ -#define TMR_CAPT_CAPTURE_MASK (0xFFFFU) -#define TMR_CAPT_CAPTURE_SHIFT (0U) -#define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK) -/*! @} */ - -/* The count of TMR_CAPT */ -#define TMR_CAPT_COUNT (4U) - -/*! @name LOAD - Timer Channel Load Register */ -/*! @{ */ -#define TMR_LOAD_LOAD_MASK (0xFFFFU) -#define TMR_LOAD_LOAD_SHIFT (0U) -#define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK) -/*! @} */ - -/* The count of TMR_LOAD */ -#define TMR_LOAD_COUNT (4U) - -/*! @name HOLD - Timer Channel Hold Register */ -/*! @{ */ -#define TMR_HOLD_HOLD_MASK (0xFFFFU) -#define TMR_HOLD_HOLD_SHIFT (0U) -#define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK) -/*! @} */ - -/* The count of TMR_HOLD */ -#define TMR_HOLD_COUNT (4U) - -/*! @name CNTR - Timer Channel Counter Register */ -/*! @{ */ -#define TMR_CNTR_COUNTER_MASK (0xFFFFU) -#define TMR_CNTR_COUNTER_SHIFT (0U) -#define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK) -/*! @} */ - -/* The count of TMR_CNTR */ -#define TMR_CNTR_COUNT (4U) - -/*! @name CTRL - Timer Channel Control Register */ -/*! @{ */ -#define TMR_CTRL_OUTMODE_MASK (0x7U) -#define TMR_CTRL_OUTMODE_SHIFT (0U) -#define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK) -#define TMR_CTRL_COINIT_MASK (0x8U) -#define TMR_CTRL_COINIT_SHIFT (3U) -#define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK) -#define TMR_CTRL_DIR_MASK (0x10U) -#define TMR_CTRL_DIR_SHIFT (4U) -#define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK) -#define TMR_CTRL_LENGTH_MASK (0x20U) -#define TMR_CTRL_LENGTH_SHIFT (5U) -#define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK) -#define TMR_CTRL_ONCE_MASK (0x40U) -#define TMR_CTRL_ONCE_SHIFT (6U) -#define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK) -#define TMR_CTRL_SCS_MASK (0x180U) -#define TMR_CTRL_SCS_SHIFT (7U) -#define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK) -#define TMR_CTRL_PCS_MASK (0x1E00U) -#define TMR_CTRL_PCS_SHIFT (9U) -#define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK) -#define TMR_CTRL_CM_MASK (0xE000U) -#define TMR_CTRL_CM_SHIFT (13U) -#define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK) -/*! @} */ - -/* The count of TMR_CTRL */ -#define TMR_CTRL_COUNT (4U) - -/*! @name SCTRL - Timer Channel Status and Control Register */ -/*! @{ */ -#define TMR_SCTRL_OEN_MASK (0x1U) -#define TMR_SCTRL_OEN_SHIFT (0U) -#define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK) -#define TMR_SCTRL_OPS_MASK (0x2U) -#define TMR_SCTRL_OPS_SHIFT (1U) -#define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK) -#define TMR_SCTRL_FORCE_MASK (0x4U) -#define TMR_SCTRL_FORCE_SHIFT (2U) -#define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK) -#define TMR_SCTRL_VAL_MASK (0x8U) -#define TMR_SCTRL_VAL_SHIFT (3U) -#define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK) -#define TMR_SCTRL_EEOF_MASK (0x10U) -#define TMR_SCTRL_EEOF_SHIFT (4U) -#define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK) -#define TMR_SCTRL_MSTR_MASK (0x20U) -#define TMR_SCTRL_MSTR_SHIFT (5U) -#define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK) -#define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U) -#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U) -#define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK) -#define TMR_SCTRL_INPUT_MASK (0x100U) -#define TMR_SCTRL_INPUT_SHIFT (8U) -#define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK) -#define TMR_SCTRL_IPS_MASK (0x200U) -#define TMR_SCTRL_IPS_SHIFT (9U) -#define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK) -#define TMR_SCTRL_IEFIE_MASK (0x400U) -#define TMR_SCTRL_IEFIE_SHIFT (10U) -#define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK) -#define TMR_SCTRL_IEF_MASK (0x800U) -#define TMR_SCTRL_IEF_SHIFT (11U) -#define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK) -#define TMR_SCTRL_TOFIE_MASK (0x1000U) -#define TMR_SCTRL_TOFIE_SHIFT (12U) -#define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK) -#define TMR_SCTRL_TOF_MASK (0x2000U) -#define TMR_SCTRL_TOF_SHIFT (13U) -#define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK) -#define TMR_SCTRL_TCFIE_MASK (0x4000U) -#define TMR_SCTRL_TCFIE_SHIFT (14U) -#define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK) -#define TMR_SCTRL_TCF_MASK (0x8000U) -#define TMR_SCTRL_TCF_SHIFT (15U) -#define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK) -/*! @} */ - -/* The count of TMR_SCTRL */ -#define TMR_SCTRL_COUNT (4U) - -/*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */ -/*! @{ */ -#define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU) -#define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U) -#define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK) -/*! @} */ - -/* The count of TMR_CMPLD1 */ -#define TMR_CMPLD1_COUNT (4U) - -/*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */ -/*! @{ */ -#define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU) -#define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U) -#define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK) -/*! @} */ - -/* The count of TMR_CMPLD2 */ -#define TMR_CMPLD2_COUNT (4U) - -/*! @name CSCTRL - Timer Channel Comparator Status and Control Register */ -/*! @{ */ -#define TMR_CSCTRL_CL1_MASK (0x3U) -#define TMR_CSCTRL_CL1_SHIFT (0U) -#define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK) -#define TMR_CSCTRL_CL2_MASK (0xCU) -#define TMR_CSCTRL_CL2_SHIFT (2U) -#define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK) -#define TMR_CSCTRL_TCF1_MASK (0x10U) -#define TMR_CSCTRL_TCF1_SHIFT (4U) -#define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK) -#define TMR_CSCTRL_TCF2_MASK (0x20U) -#define TMR_CSCTRL_TCF2_SHIFT (5U) -#define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK) -#define TMR_CSCTRL_TCF1EN_MASK (0x40U) -#define TMR_CSCTRL_TCF1EN_SHIFT (6U) -#define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK) -#define TMR_CSCTRL_TCF2EN_MASK (0x80U) -#define TMR_CSCTRL_TCF2EN_SHIFT (7U) -#define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK) -#define TMR_CSCTRL_UP_MASK (0x200U) -#define TMR_CSCTRL_UP_SHIFT (9U) -#define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK) -#define TMR_CSCTRL_TCI_MASK (0x400U) -#define TMR_CSCTRL_TCI_SHIFT (10U) -#define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK) -#define TMR_CSCTRL_ROC_MASK (0x800U) -#define TMR_CSCTRL_ROC_SHIFT (11U) -#define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK) -#define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U) -#define TMR_CSCTRL_ALT_LOAD_SHIFT (12U) -#define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK) -#define TMR_CSCTRL_FAULT_MASK (0x2000U) -#define TMR_CSCTRL_FAULT_SHIFT (13U) -#define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK) -#define TMR_CSCTRL_DBG_EN_MASK (0xC000U) -#define TMR_CSCTRL_DBG_EN_SHIFT (14U) -#define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK) -/*! @} */ - -/* The count of TMR_CSCTRL */ -#define TMR_CSCTRL_COUNT (4U) - -/*! @name FILT - Timer Channel Input Filter Register */ -/*! @{ */ -#define TMR_FILT_FILT_PER_MASK (0xFFU) -#define TMR_FILT_FILT_PER_SHIFT (0U) -#define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK) -#define TMR_FILT_FILT_CNT_MASK (0x700U) -#define TMR_FILT_FILT_CNT_SHIFT (8U) -#define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK) -/*! @} */ - -/* The count of TMR_FILT */ -#define TMR_FILT_COUNT (4U) - -/*! @name DMA - Timer Channel DMA Enable Register */ -/*! @{ */ -#define TMR_DMA_IEFDE_MASK (0x1U) -#define TMR_DMA_IEFDE_SHIFT (0U) -#define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK) -#define TMR_DMA_CMPLD1DE_MASK (0x2U) -#define TMR_DMA_CMPLD1DE_SHIFT (1U) -#define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK) -#define TMR_DMA_CMPLD2DE_MASK (0x4U) -#define TMR_DMA_CMPLD2DE_SHIFT (2U) -#define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK) -/*! @} */ - -/* The count of TMR_DMA */ -#define TMR_DMA_COUNT (4U) - -/*! @name ENBL - Timer Channel Enable Register */ -/*! @{ */ -#define TMR_ENBL_ENBL_MASK (0xFU) -#define TMR_ENBL_ENBL_SHIFT (0U) -#define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK) -/*! @} */ - -/* The count of TMR_ENBL */ -#define TMR_ENBL_COUNT (4U) - - -/*! - * @} - */ /* end of group TMR_Register_Masks */ - - -/* TMR - Peripheral instance base addresses */ -/** Peripheral TMR1 base address */ -#define TMR1_BASE (0x401DC000u) -/** Peripheral TMR1 base pointer */ -#define TMR1 ((TMR_Type *)TMR1_BASE) -/** Peripheral TMR2 base address */ -#define TMR2_BASE (0x401E0000u) -/** Peripheral TMR2 base pointer */ -#define TMR2 ((TMR_Type *)TMR2_BASE) -/** Peripheral TMR3 base address */ -#define TMR3_BASE (0x401E4000u) -/** Peripheral TMR3 base pointer */ -#define TMR3 ((TMR_Type *)TMR3_BASE) -/** Peripheral TMR4 base address */ -#define TMR4_BASE (0x401E8000u) -/** Peripheral TMR4 base pointer */ -#define TMR4 ((TMR_Type *)TMR4_BASE) -/** Array initializer of TMR peripheral base addresses */ -#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE } -/** Array initializer of TMR peripheral base pointers */ -#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 } -/** Interrupt vectors for the TMR peripheral type */ -#define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn } - -/*! - * @} - */ /* end of group TMR_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TRNG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer - * @{ - */ - -/** TRNG - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */ - __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */ - __IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */ - union { /* offset: 0xC */ - __IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */ - __I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */ - }; - __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */ - union { /* offset: 0x14 */ - __IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */ - __I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */ - }; - __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */ - union { /* offset: 0x1C */ - __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */ - __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */ - }; - union { /* offset: 0x20 */ - __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */ - __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */ - }; - union { /* offset: 0x24 */ - __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */ - __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */ - }; - union { /* offset: 0x28 */ - __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */ - __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */ - }; - union { /* offset: 0x2C */ - __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */ - __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */ - }; - union { /* offset: 0x30 */ - __I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */ - __IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */ - }; - union { /* offset: 0x34 */ - __I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */ - __IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */ - }; - union { /* offset: 0x38 */ - __I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */ - __IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */ - }; - __I uint32_t STATUS; /**< Status Register, offset: 0x3C */ - __I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */ - __I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */ - __I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */ - __I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */ - __I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */ - __I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */ - __I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */ - __I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */ - __I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */ - __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */ - __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */ - __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ - __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ - uint8_t RESERVED_0[64]; - __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */ - __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */ -} TRNG_Type; - -/* ---------------------------------------------------------------------------- - -- TRNG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TRNG_Register_Masks TRNG Register Masks - * @{ - */ - -/*! @name MCTL - Miscellaneous Control Register */ -/*! @{ */ -#define TRNG_MCTL_SAMP_MODE_MASK (0x3U) -#define TRNG_MCTL_SAMP_MODE_SHIFT (0U) -#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) -#define TRNG_MCTL_OSC_DIV_MASK (0xCU) -#define TRNG_MCTL_OSC_DIV_SHIFT (2U) -#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) -#define TRNG_MCTL_UNUSED4_MASK (0x10U) -#define TRNG_MCTL_UNUSED4_SHIFT (4U) -#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK) -#define TRNG_MCTL_UNUSED5_MASK (0x20U) -#define TRNG_MCTL_UNUSED5_SHIFT (5U) -#define TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK) -#define TRNG_MCTL_RST_DEF_MASK (0x40U) -#define TRNG_MCTL_RST_DEF_SHIFT (6U) -#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) -#define TRNG_MCTL_FOR_SCLK_MASK (0x80U) -#define TRNG_MCTL_FOR_SCLK_SHIFT (7U) -#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK) -#define TRNG_MCTL_FCT_FAIL_MASK (0x100U) -#define TRNG_MCTL_FCT_FAIL_SHIFT (8U) -#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) -#define TRNG_MCTL_FCT_VAL_MASK (0x200U) -#define TRNG_MCTL_FCT_VAL_SHIFT (9U) -#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) -#define TRNG_MCTL_ENT_VAL_MASK (0x400U) -#define TRNG_MCTL_ENT_VAL_SHIFT (10U) -#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) -#define TRNG_MCTL_TST_OUT_MASK (0x800U) -#define TRNG_MCTL_TST_OUT_SHIFT (11U) -#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK) -#define TRNG_MCTL_ERR_MASK (0x1000U) -#define TRNG_MCTL_ERR_SHIFT (12U) -#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) -#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) -#define TRNG_MCTL_TSTOP_OK_SHIFT (13U) -#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) -#define TRNG_MCTL_LRUN_CONT_MASK (0x4000U) -#define TRNG_MCTL_LRUN_CONT_SHIFT (14U) -#define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK) -#define TRNG_MCTL_PRGM_MASK (0x10000U) -#define TRNG_MCTL_PRGM_SHIFT (16U) -#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) -/*! @} */ - -/*! @name SCMISC - Statistical Check Miscellaneous Register */ -/*! @{ */ -#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) -#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) -#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) -#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) -#define TRNG_SCMISC_RTY_CT_SHIFT (16U) -#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) -/*! @} */ - -/*! @name PKRRNG - Poker Range Register */ -/*! @{ */ -#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) -#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) -#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) -/*! @} */ - -/*! @name PKRMAX - Poker Maximum Limit Register */ -/*! @{ */ -#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) -#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) -#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) -/*! @} */ - -/*! @name PKRSQ - Poker Square Calculation Result Register */ -/*! @{ */ -#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) -#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) -#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) -/*! @} */ - -/*! @name SDCTL - Seed Control Register */ -/*! @{ */ -#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) -#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) -#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) -#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) -#define TRNG_SDCTL_ENT_DLY_SHIFT (16U) -#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) -/*! @} */ - -/*! @name SBLIM - Sparse Bit Limit Register */ -/*! @{ */ -#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) -#define TRNG_SBLIM_SB_LIM_SHIFT (0U) -#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) -/*! @} */ - -/*! @name TOTSAM - Total Samples Register */ -/*! @{ */ -#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) -#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) -#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) -/*! @} */ - -/*! @name FRQMIN - Frequency Count Minimum Limit Register */ -/*! @{ */ -#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) -#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) -#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) -/*! @} */ - -/*! @name FRQCNT - Frequency Count Register */ -/*! @{ */ -#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) -#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) -#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) -/*! @} */ - -/*! @name FRQMAX - Frequency Count Maximum Limit Register */ -/*! @{ */ -#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) -#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) -#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) -/*! @} */ - -/*! @name SCMC - Statistical Check Monobit Count Register */ -/*! @{ */ -#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) -#define TRNG_SCMC_MONO_CT_SHIFT (0U) -#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) -/*! @} */ - -/*! @name SCML - Statistical Check Monobit Limit Register */ -/*! @{ */ -#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) -#define TRNG_SCML_MONO_MAX_SHIFT (0U) -#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) -#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) -#define TRNG_SCML_MONO_RNG_SHIFT (16U) -#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) -/*! @} */ - -/*! @name SCR1C - Statistical Check Run Length 1 Count Register */ -/*! @{ */ -#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) -#define TRNG_SCR1C_R1_0_CT_SHIFT (0U) -#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) -#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) -#define TRNG_SCR1C_R1_1_CT_SHIFT (16U) -#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) -/*! @} */ - -/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ -/*! @{ */ -#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) -#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) -#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) -#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) -#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) -#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) -/*! @} */ - -/*! @name SCR2C - Statistical Check Run Length 2 Count Register */ -/*! @{ */ -#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) -#define TRNG_SCR2C_R2_0_CT_SHIFT (0U) -#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) -#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) -#define TRNG_SCR2C_R2_1_CT_SHIFT (16U) -#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) -/*! @} */ - -/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ -/*! @{ */ -#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) -#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) -#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) -#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) -#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) -#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) -/*! @} */ - -/*! @name SCR3C - Statistical Check Run Length 3 Count Register */ -/*! @{ */ -#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) -#define TRNG_SCR3C_R3_0_CT_SHIFT (0U) -#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) -#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) -#define TRNG_SCR3C_R3_1_CT_SHIFT (16U) -#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) -/*! @} */ - -/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ -/*! @{ */ -#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) -#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) -#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) -#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) -#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) -#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) -/*! @} */ - -/*! @name SCR4C - Statistical Check Run Length 4 Count Register */ -/*! @{ */ -#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) -#define TRNG_SCR4C_R4_0_CT_SHIFT (0U) -#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) -#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) -#define TRNG_SCR4C_R4_1_CT_SHIFT (16U) -#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) -/*! @} */ - -/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ -/*! @{ */ -#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) -#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) -#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) -#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) -#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) -#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) -/*! @} */ - -/*! @name SCR5C - Statistical Check Run Length 5 Count Register */ -/*! @{ */ -#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) -#define TRNG_SCR5C_R5_0_CT_SHIFT (0U) -#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) -#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) -#define TRNG_SCR5C_R5_1_CT_SHIFT (16U) -#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) -/*! @} */ - -/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ -/*! @{ */ -#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) -#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) -#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) -#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) -#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) -#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) -/*! @} */ - -/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ -/*! @{ */ -#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) -#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) -#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) -#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) -#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) -#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) -/*! @} */ - -/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ -/*! @{ */ -#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) -#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) -#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) -#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) -#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) -#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) -/*! @} */ - -/*! @name STATUS - Status Register */ -/*! @{ */ -#define TRNG_STATUS_TF1BR0_MASK (0x1U) -#define TRNG_STATUS_TF1BR0_SHIFT (0U) -#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) -#define TRNG_STATUS_TF1BR1_MASK (0x2U) -#define TRNG_STATUS_TF1BR1_SHIFT (1U) -#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) -#define TRNG_STATUS_TF2BR0_MASK (0x4U) -#define TRNG_STATUS_TF2BR0_SHIFT (2U) -#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) -#define TRNG_STATUS_TF2BR1_MASK (0x8U) -#define TRNG_STATUS_TF2BR1_SHIFT (3U) -#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) -#define TRNG_STATUS_TF3BR0_MASK (0x10U) -#define TRNG_STATUS_TF3BR0_SHIFT (4U) -#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) -#define TRNG_STATUS_TF3BR1_MASK (0x20U) -#define TRNG_STATUS_TF3BR1_SHIFT (5U) -#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) -#define TRNG_STATUS_TF4BR0_MASK (0x40U) -#define TRNG_STATUS_TF4BR0_SHIFT (6U) -#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK) -#define TRNG_STATUS_TF4BR1_MASK (0x80U) -#define TRNG_STATUS_TF4BR1_SHIFT (7U) -#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK) -#define TRNG_STATUS_TF5BR0_MASK (0x100U) -#define TRNG_STATUS_TF5BR0_SHIFT (8U) -#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK) -#define TRNG_STATUS_TF5BR1_MASK (0x200U) -#define TRNG_STATUS_TF5BR1_SHIFT (9U) -#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK) -#define TRNG_STATUS_TF6PBR0_MASK (0x400U) -#define TRNG_STATUS_TF6PBR0_SHIFT (10U) -#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK) -#define TRNG_STATUS_TF6PBR1_MASK (0x800U) -#define TRNG_STATUS_TF6PBR1_SHIFT (11U) -#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK) -#define TRNG_STATUS_TFSB_MASK (0x1000U) -#define TRNG_STATUS_TFSB_SHIFT (12U) -#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK) -#define TRNG_STATUS_TFLR_MASK (0x2000U) -#define TRNG_STATUS_TFLR_SHIFT (13U) -#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) -#define TRNG_STATUS_TFP_MASK (0x4000U) -#define TRNG_STATUS_TFP_SHIFT (14U) -#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK) -#define TRNG_STATUS_TFMB_MASK (0x8000U) -#define TRNG_STATUS_TFMB_SHIFT (15U) -#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) -#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) -#define TRNG_STATUS_RETRY_CT_SHIFT (16U) -#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) -/*! @} */ - -/*! @name ENT - Entropy Read Register */ -/*! @{ */ -#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) -#define TRNG_ENT_ENT_SHIFT (0U) -#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) -/*! @} */ - -/* The count of TRNG_ENT */ -#define TRNG_ENT_COUNT (16U) - -/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ -/*! @{ */ -#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) -#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) -#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) -#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) -/*! @} */ - -/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ -/*! @{ */ -#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) -#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) -#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) -#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) -/*! @} */ - -/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ -/*! @{ */ -#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) -#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) -#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) -#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) -/*! @} */ - -/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ -/*! @{ */ -#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) -#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) -#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) -#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) -/*! @} */ - -/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ -/*! @{ */ -#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) -#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) -#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) -#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) -#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) -/*! @} */ - -/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ -/*! @{ */ -#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) -#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) -#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) -#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) -#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) -/*! @} */ - -/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ -/*! @{ */ -#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) -#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) -#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) -#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) -#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) -/*! @} */ - -/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ -/*! @{ */ -#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) -#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) -#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) -#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) -#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) -#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) -/*! @} */ - -/*! @name SEC_CFG - Security Configuration Register */ -/*! @{ */ -#define TRNG_SEC_CFG_UNUSED0_MASK (0x1U) -#define TRNG_SEC_CFG_UNUSED0_SHIFT (0U) -#define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK) -#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) -#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) -#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) -#define TRNG_SEC_CFG_UNUSED2_MASK (0x4U) -#define TRNG_SEC_CFG_UNUSED2_SHIFT (2U) -#define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK) -/*! @} */ - -/*! @name INT_CTRL - Interrupt Control Register */ -/*! @{ */ -#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) -#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) -#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) -#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) -#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) -#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) -#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) -#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) -#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) -#define TRNG_INT_CTRL_UNUSED_SHIFT (3U) -#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) -/*! @} */ - -/*! @name INT_MASK - Mask Register */ -/*! @{ */ -#define TRNG_INT_MASK_HW_ERR_MASK (0x1U) -#define TRNG_INT_MASK_HW_ERR_SHIFT (0U) -#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) -#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) -#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) -#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) -#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) -#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt Status Register */ -/*! @{ */ -#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) -#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) -#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) -#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) -#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) -#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) -#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) -#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) -#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) -/*! @} */ - -/*! @name VID1 - Version ID Register (MS) */ -/*! @{ */ -#define TRNG_VID1_MIN_REV_MASK (0xFFU) -#define TRNG_VID1_MIN_REV_SHIFT (0U) -#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) -#define TRNG_VID1_MAJ_REV_MASK (0xFF00U) -#define TRNG_VID1_MAJ_REV_SHIFT (8U) -#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) -#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) -#define TRNG_VID1_IP_ID_SHIFT (16U) -#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) -/*! @} */ - -/*! @name VID2 - Version ID Register (LS) */ -/*! @{ */ -#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) -#define TRNG_VID2_CONFIG_OPT_SHIFT (0U) -#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) -#define TRNG_VID2_ECO_REV_MASK (0xFF00U) -#define TRNG_VID2_ECO_REV_SHIFT (8U) -#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) -#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) -#define TRNG_VID2_INTG_OPT_SHIFT (16U) -#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) -#define TRNG_VID2_ERA_MASK (0xFF000000U) -#define TRNG_VID2_ERA_SHIFT (24U) -#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group TRNG_Register_Masks */ - - -/* TRNG - Peripheral instance base addresses */ -/** Peripheral TRNG base address */ -#define TRNG_BASE (0x400CC000u) -/** Peripheral TRNG base pointer */ -#define TRNG ((TRNG_Type *)TRNG_BASE) -/** Array initializer of TRNG peripheral base addresses */ -#define TRNG_BASE_ADDRS { TRNG_BASE } -/** Array initializer of TRNG peripheral base pointers */ -#define TRNG_BASE_PTRS { TRNG } -/** Interrupt vectors for the TRNG peripheral type */ -#define TRNG_IRQS { TRNG_IRQn } - -/*! - * @} - */ /* end of group TRNG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TSC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TSC_Peripheral_Access_Layer TSC Peripheral Access Layer - * @{ - */ - -/** TSC - Register Layout Typedef */ -typedef struct { - __IO uint32_t BASIC_SETTING; /**< , offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t PRE_CHARGE_TIME; /**< , offset: 0x10 */ - uint8_t RESERVED_1[12]; - __IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */ - uint8_t RESERVED_2[12]; - __I uint32_t MEASEURE_VALUE; /**< Measure Value, offset: 0x30 */ - uint8_t RESERVED_3[12]; - __IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0x40 */ - uint8_t RESERVED_4[12]; - __IO uint32_t INT_SIG_EN; /**< Interrupt Signal Enable, offset: 0x50 */ - uint8_t RESERVED_5[12]; - __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ - uint8_t RESERVED_6[12]; - __IO uint32_t DEBUG_MODE; /**< , offset: 0x70 */ - uint8_t RESERVED_7[12]; - __IO uint32_t DEBUG_MODE2; /**< , offset: 0x80 */ -} TSC_Type; - -/* ---------------------------------------------------------------------------- - -- TSC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup TSC_Register_Masks TSC Register Masks - * @{ - */ - -/*! @name BASIC_SETTING - */ -/*! @{ */ -#define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U) -#define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U) -#define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK) -#define TSC_BASIC_SETTING_4_5_WIRE_MASK (0x10U) -#define TSC_BASIC_SETTING_4_5_WIRE_SHIFT (4U) -#define TSC_BASIC_SETTING_4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING_4_5_WIRE_MASK) -#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U) -#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U) -#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK) -/*! @} */ - -/*! @name PRE_CHARGE_TIME - */ -/*! @{ */ -#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) -#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U) -#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK) -/*! @} */ - -/*! @name FLOW_CONTROL - Flow Control */ -/*! @{ */ -#define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U) -#define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U) -#define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK) -#define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U) -#define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U) -#define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK) -#define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U) -#define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U) -#define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK) -#define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U) -#define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U) -#define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK) -#define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U) -#define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U) -#define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK) -/*! @} */ - -/*! @name MEASEURE_VALUE - Measure Value */ -/*! @{ */ -#define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU) -#define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U) -#define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) -#define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U) -#define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U) -#define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK) -/*! @} */ - -/*! @name INT_EN - Interrupt Enable */ -/*! @{ */ -#define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U) -#define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U) -#define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK) -#define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U) -#define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U) -#define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK) -#define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U) -#define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U) -#define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK) -/*! @} */ - -/*! @name INT_SIG_EN - Interrupt Signal Enable */ -/*! @{ */ -#define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U) -#define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U) -#define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK) -#define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U) -#define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U) -#define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK) -#define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U) -#define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U) -#define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK) -#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U) -#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U) -#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK) -/*! @} */ - -/*! @name INT_STATUS - Intterrupt Status */ -/*! @{ */ -#define TSC_INT_STATUS_MEASURE_MASK (0x1U) -#define TSC_INT_STATUS_MEASURE_SHIFT (0U) -#define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK) -#define TSC_INT_STATUS_DETECT_MASK (0x10U) -#define TSC_INT_STATUS_DETECT_SHIFT (4U) -#define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK) -#define TSC_INT_STATUS_VALID_MASK (0x100U) -#define TSC_INT_STATUS_VALID_SHIFT (8U) -#define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK) -#define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U) -#define TSC_INT_STATUS_IDLE_SW_SHIFT (12U) -#define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK) -/*! @} */ - -/*! @name DEBUG_MODE - */ -/*! @{ */ -#define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU) -#define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U) -#define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK) -#define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U) -#define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U) -#define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK) -#define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U) -#define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U) -#define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK) -#define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U) -#define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U) -#define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK) -#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U) -#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U) -#define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK) -#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U) -#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U) -#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK) -#define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U) -#define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U) -#define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK) -/*! @} */ - -/*! @name DEBUG_MODE2 - */ -/*! @{ */ -#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U) -#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U) -#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK) -#define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U) -#define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U) -#define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK) -#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U) -#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U) -#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK) -#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U) -#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U) -#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK) -#define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U) -#define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U) -#define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK) -#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U) -#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U) -#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK) -#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U) -#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U) -#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK) -#define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U) -#define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U) -#define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK) -#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U) -#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U) -#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK) -#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U) -#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U) -#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK) -#define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U) -#define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U) -#define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK) -#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U) -#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U) -#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK) -#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U) -#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U) -#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK) -#define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U) -#define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U) -#define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK) -#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U) -#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U) -#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK) -#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U) -#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U) -#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK) -#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U) -#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U) -#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK) -#define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U) -#define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U) -#define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK) -#define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U) -#define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U) -#define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK) -#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U) -#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U) -#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK) -#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U) -#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U) -#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK) -#define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U) -#define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U) -#define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group TSC_Register_Masks */ - - -/* TSC - Peripheral instance base addresses */ -/** Peripheral TSC base address */ -#define TSC_BASE (0x400E0000u) -/** Peripheral TSC base pointer */ -#define TSC ((TSC_Type *)TSC_BASE) -/** Array initializer of TSC peripheral base addresses */ -#define TSC_BASE_ADDRS { TSC_BASE } -/** Array initializer of TSC peripheral base pointers */ -#define TSC_BASE_PTRS { TSC } -/** Interrupt vectors for the TSC peripheral type */ -#define TSC_IRQS { TSC_DIG_IRQn } -/* Backward compatibility */ -#define TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_4_5_WIRE_MASK -#define TSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_4_5_WIRE_SHIFT -#define TSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_4_5_WIRE(x) - - -/*! - * @} - */ /* end of group TSC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __I uint32_t ID; /**< Identification register, offset: 0x0 */ - __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ - __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ - __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ - __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ - __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ - uint8_t RESERVED_0[104]; - __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ - __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ - __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ - __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ - __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ - uint8_t RESERVED_1[108]; - __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ - uint8_t RESERVED_2[1]; - __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ - __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ - __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ - uint8_t RESERVED_3[20]; - __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ - uint8_t RESERVED_4[2]; - __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ - uint8_t RESERVED_5[24]; - __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ - __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ - __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ - __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ - uint8_t RESERVED_6[4]; - union { /* offset: 0x154 */ - __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ - __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ - }; - union { /* offset: 0x158 */ - __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ - __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ - }; - uint8_t RESERVED_7[4]; - __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ - __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ - uint8_t RESERVED_8[16]; - __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ - __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ - __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ - __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ - uint8_t RESERVED_9[28]; - __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ - __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ - __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ - __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ - __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ - __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ - __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ - __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ - __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name ID - Identification register */ -/*! @{ */ -#define USB_ID_ID_MASK (0x3FU) -#define USB_ID_ID_SHIFT (0U) -#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) -#define USB_ID_NID_MASK (0x3F00U) -#define USB_ID_NID_SHIFT (8U) -#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) -#define USB_ID_REVISION_MASK (0xFF0000U) -#define USB_ID_REVISION_SHIFT (16U) -#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) -/*! @} */ - -/*! @name HWGENERAL - Hardware General */ -/*! @{ */ -#define USB_HWGENERAL_PHYW_MASK (0x30U) -#define USB_HWGENERAL_PHYW_SHIFT (4U) -#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) -#define USB_HWGENERAL_PHYM_MASK (0x1C0U) -#define USB_HWGENERAL_PHYM_SHIFT (6U) -#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) -#define USB_HWGENERAL_SM_MASK (0x600U) -#define USB_HWGENERAL_SM_SHIFT (9U) -#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) -/*! @} */ - -/*! @name HWHOST - Host Hardware Parameters */ -/*! @{ */ -#define USB_HWHOST_HC_MASK (0x1U) -#define USB_HWHOST_HC_SHIFT (0U) -#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) -#define USB_HWHOST_NPORT_MASK (0xEU) -#define USB_HWHOST_NPORT_SHIFT (1U) -#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) -/*! @} */ - -/*! @name HWDEVICE - Device Hardware Parameters */ -/*! @{ */ -#define USB_HWDEVICE_DC_MASK (0x1U) -#define USB_HWDEVICE_DC_SHIFT (0U) -#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) -#define USB_HWDEVICE_DEVEP_MASK (0x3EU) -#define USB_HWDEVICE_DEVEP_SHIFT (1U) -#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) -/*! @} */ - -/*! @name HWTXBUF - TX Buffer Hardware Parameters */ -/*! @{ */ -#define USB_HWTXBUF_TXBURST_MASK (0xFFU) -#define USB_HWTXBUF_TXBURST_SHIFT (0U) -#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) -#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) -#define USB_HWTXBUF_TXCHANADD_SHIFT (16U) -#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) -/*! @} */ - -/*! @name HWRXBUF - RX Buffer Hardware Parameters */ -/*! @{ */ -#define USB_HWRXBUF_RXBURST_MASK (0xFFU) -#define USB_HWRXBUF_RXBURST_SHIFT (0U) -#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) -#define USB_HWRXBUF_RXADD_MASK (0xFF00U) -#define USB_HWRXBUF_RXADD_SHIFT (8U) -#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) -/*! @} */ - -/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ -/*! @{ */ -#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) -#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) -/*! @} */ - -/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ -/*! @{ */ -#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) -#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) -#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) -#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) -#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) -#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) -#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) -#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) -/*! @} */ - -/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ -/*! @{ */ -#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) -#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) -/*! @} */ - -/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ -/*! @{ */ -#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) -#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) -#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) -#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) -#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) -#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) -#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) -#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) -/*! @} */ - -/*! @name SBUSCFG - System Bus Config */ -/*! @{ */ -#define USB_SBUSCFG_AHBBRST_MASK (0x7U) -#define USB_SBUSCFG_AHBBRST_SHIFT (0U) -#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) -/*! @} */ - -/*! @name CAPLENGTH - Capability Registers Length */ -/*! @{ */ -#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) -#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) -#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) -/*! @} */ - -/*! @name HCIVERSION - Host Controller Interface Version */ -/*! @{ */ -#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) -#define USB_HCIVERSION_HCIVERSION_SHIFT (0U) -#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) -/*! @} */ - -/*! @name HCSPARAMS - Host Controller Structural Parameters */ -/*! @{ */ -#define USB_HCSPARAMS_N_PORTS_MASK (0xFU) -#define USB_HCSPARAMS_N_PORTS_SHIFT (0U) -#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) -#define USB_HCSPARAMS_PPC_MASK (0x10U) -#define USB_HCSPARAMS_PPC_SHIFT (4U) -#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) -#define USB_HCSPARAMS_N_PCC_MASK (0xF00U) -#define USB_HCSPARAMS_N_PCC_SHIFT (8U) -#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) -#define USB_HCSPARAMS_N_CC_MASK (0xF000U) -#define USB_HCSPARAMS_N_CC_SHIFT (12U) -#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) -#define USB_HCSPARAMS_PI_MASK (0x10000U) -#define USB_HCSPARAMS_PI_SHIFT (16U) -#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) -#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) -#define USB_HCSPARAMS_N_PTT_SHIFT (20U) -#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) -#define USB_HCSPARAMS_N_TT_MASK (0xF000000U) -#define USB_HCSPARAMS_N_TT_SHIFT (24U) -#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) -/*! @} */ - -/*! @name HCCPARAMS - Host Controller Capability Parameters */ -/*! @{ */ -#define USB_HCCPARAMS_ADC_MASK (0x1U) -#define USB_HCCPARAMS_ADC_SHIFT (0U) -#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) -#define USB_HCCPARAMS_PFL_MASK (0x2U) -#define USB_HCCPARAMS_PFL_SHIFT (1U) -#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) -#define USB_HCCPARAMS_ASP_MASK (0x4U) -#define USB_HCCPARAMS_ASP_SHIFT (2U) -#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) -#define USB_HCCPARAMS_IST_MASK (0xF0U) -#define USB_HCCPARAMS_IST_SHIFT (4U) -#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) -#define USB_HCCPARAMS_EECP_MASK (0xFF00U) -#define USB_HCCPARAMS_EECP_SHIFT (8U) -#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) -/*! @} */ - -/*! @name DCIVERSION - Device Controller Interface Version */ -/*! @{ */ -#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) -#define USB_DCIVERSION_DCIVERSION_SHIFT (0U) -#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) -/*! @} */ - -/*! @name DCCPARAMS - Device Controller Capability Parameters */ -/*! @{ */ -#define USB_DCCPARAMS_DEN_MASK (0x1FU) -#define USB_DCCPARAMS_DEN_SHIFT (0U) -#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) -#define USB_DCCPARAMS_DC_MASK (0x80U) -#define USB_DCCPARAMS_DC_SHIFT (7U) -#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) -#define USB_DCCPARAMS_HC_MASK (0x100U) -#define USB_DCCPARAMS_HC_SHIFT (8U) -#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) -/*! @} */ - -/*! @name USBCMD - USB Command Register */ -/*! @{ */ -#define USB_USBCMD_RS_MASK (0x1U) -#define USB_USBCMD_RS_SHIFT (0U) -#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) -#define USB_USBCMD_RST_MASK (0x2U) -#define USB_USBCMD_RST_SHIFT (1U) -#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) -#define USB_USBCMD_FS_1_MASK (0xCU) -#define USB_USBCMD_FS_1_SHIFT (2U) -#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) -#define USB_USBCMD_PSE_MASK (0x10U) -#define USB_USBCMD_PSE_SHIFT (4U) -#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) -#define USB_USBCMD_ASE_MASK (0x20U) -#define USB_USBCMD_ASE_SHIFT (5U) -#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) -#define USB_USBCMD_IAA_MASK (0x40U) -#define USB_USBCMD_IAA_SHIFT (6U) -#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) -#define USB_USBCMD_ASP_MASK (0x300U) -#define USB_USBCMD_ASP_SHIFT (8U) -#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) -#define USB_USBCMD_ASPE_MASK (0x800U) -#define USB_USBCMD_ASPE_SHIFT (11U) -#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) -#define USB_USBCMD_ATDTW_MASK (0x1000U) -#define USB_USBCMD_ATDTW_SHIFT (12U) -#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) -#define USB_USBCMD_SUTW_MASK (0x2000U) -#define USB_USBCMD_SUTW_SHIFT (13U) -#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) -#define USB_USBCMD_FS_2_MASK (0x8000U) -#define USB_USBCMD_FS_2_SHIFT (15U) -#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) -#define USB_USBCMD_ITC_MASK (0xFF0000U) -#define USB_USBCMD_ITC_SHIFT (16U) -#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) -/*! @} */ - -/*! @name USBSTS - USB Status Register */ -/*! @{ */ -#define USB_USBSTS_UI_MASK (0x1U) -#define USB_USBSTS_UI_SHIFT (0U) -#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) -#define USB_USBSTS_UEI_MASK (0x2U) -#define USB_USBSTS_UEI_SHIFT (1U) -#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) -#define USB_USBSTS_PCI_MASK (0x4U) -#define USB_USBSTS_PCI_SHIFT (2U) -#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) -#define USB_USBSTS_FRI_MASK (0x8U) -#define USB_USBSTS_FRI_SHIFT (3U) -#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) -#define USB_USBSTS_SEI_MASK (0x10U) -#define USB_USBSTS_SEI_SHIFT (4U) -#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) -#define USB_USBSTS_AAI_MASK (0x20U) -#define USB_USBSTS_AAI_SHIFT (5U) -#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) -#define USB_USBSTS_URI_MASK (0x40U) -#define USB_USBSTS_URI_SHIFT (6U) -#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) -#define USB_USBSTS_SRI_MASK (0x80U) -#define USB_USBSTS_SRI_SHIFT (7U) -#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) -#define USB_USBSTS_SLI_MASK (0x100U) -#define USB_USBSTS_SLI_SHIFT (8U) -#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) -#define USB_USBSTS_ULPII_MASK (0x400U) -#define USB_USBSTS_ULPII_SHIFT (10U) -#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) -#define USB_USBSTS_HCH_MASK (0x1000U) -#define USB_USBSTS_HCH_SHIFT (12U) -#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) -#define USB_USBSTS_RCL_MASK (0x2000U) -#define USB_USBSTS_RCL_SHIFT (13U) -#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) -#define USB_USBSTS_PS_MASK (0x4000U) -#define USB_USBSTS_PS_SHIFT (14U) -#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) -#define USB_USBSTS_AS_MASK (0x8000U) -#define USB_USBSTS_AS_SHIFT (15U) -#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) -#define USB_USBSTS_NAKI_MASK (0x10000U) -#define USB_USBSTS_NAKI_SHIFT (16U) -#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) -#define USB_USBSTS_TI0_MASK (0x1000000U) -#define USB_USBSTS_TI0_SHIFT (24U) -#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) -#define USB_USBSTS_TI1_MASK (0x2000000U) -#define USB_USBSTS_TI1_SHIFT (25U) -#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) -/*! @} */ - -/*! @name USBINTR - Interrupt Enable Register */ -/*! @{ */ -#define USB_USBINTR_UE_MASK (0x1U) -#define USB_USBINTR_UE_SHIFT (0U) -#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) -#define USB_USBINTR_UEE_MASK (0x2U) -#define USB_USBINTR_UEE_SHIFT (1U) -#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) -#define USB_USBINTR_PCE_MASK (0x4U) -#define USB_USBINTR_PCE_SHIFT (2U) -#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) -#define USB_USBINTR_FRE_MASK (0x8U) -#define USB_USBINTR_FRE_SHIFT (3U) -#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) -#define USB_USBINTR_SEE_MASK (0x10U) -#define USB_USBINTR_SEE_SHIFT (4U) -#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) -#define USB_USBINTR_AAE_MASK (0x20U) -#define USB_USBINTR_AAE_SHIFT (5U) -#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) -#define USB_USBINTR_URE_MASK (0x40U) -#define USB_USBINTR_URE_SHIFT (6U) -#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) -#define USB_USBINTR_SRE_MASK (0x80U) -#define USB_USBINTR_SRE_SHIFT (7U) -#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) -#define USB_USBINTR_SLE_MASK (0x100U) -#define USB_USBINTR_SLE_SHIFT (8U) -#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) -#define USB_USBINTR_ULPIE_MASK (0x400U) -#define USB_USBINTR_ULPIE_SHIFT (10U) -#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) -#define USB_USBINTR_NAKE_MASK (0x10000U) -#define USB_USBINTR_NAKE_SHIFT (16U) -#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) -#define USB_USBINTR_UAIE_MASK (0x40000U) -#define USB_USBINTR_UAIE_SHIFT (18U) -#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) -#define USB_USBINTR_UPIE_MASK (0x80000U) -#define USB_USBINTR_UPIE_SHIFT (19U) -#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) -#define USB_USBINTR_TIE0_MASK (0x1000000U) -#define USB_USBINTR_TIE0_SHIFT (24U) -#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) -#define USB_USBINTR_TIE1_MASK (0x2000000U) -#define USB_USBINTR_TIE1_SHIFT (25U) -#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) -/*! @} */ - -/*! @name FRINDEX - USB Frame Index */ -/*! @{ */ -#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) -#define USB_FRINDEX_FRINDEX_SHIFT (0U) -#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) -/*! @} */ - -/*! @name DEVICEADDR - Device Address */ -/*! @{ */ -#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) -#define USB_DEVICEADDR_USBADRA_SHIFT (24U) -#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) -#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) -#define USB_DEVICEADDR_USBADR_SHIFT (25U) -#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) -/*! @} */ - -/*! @name PERIODICLISTBASE - Frame List Base Address */ -/*! @{ */ -#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) -#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) -#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) -/*! @} */ - -/*! @name ASYNCLISTADDR - Next Asynch. Address */ -/*! @{ */ -#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) -#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) -#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) -/*! @} */ - -/*! @name ENDPTLISTADDR - Endpoint List Address */ -/*! @{ */ -#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) -#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) -#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) -/*! @} */ - -/*! @name BURSTSIZE - Programmable Burst Size */ -/*! @{ */ -#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) -#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) -#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) -#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) -#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) -#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) -/*! @} */ - -/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ -/*! @{ */ -#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) -#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) -#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) -#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) -#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) -#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) -#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) -#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) -#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) -/*! @} */ - -/*! @name ENDPTNAK - Endpoint NAK */ -/*! @{ */ -#define USB_ENDPTNAK_EPRN_MASK (0xFFU) -#define USB_ENDPTNAK_EPRN_SHIFT (0U) -#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) -#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) -#define USB_ENDPTNAK_EPTN_SHIFT (16U) -#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) -/*! @} */ - -/*! @name ENDPTNAKEN - Endpoint NAK Enable */ -/*! @{ */ -#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) -#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) -#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) -#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) -#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) -#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) -/*! @} */ - -/*! @name CONFIGFLAG - Configure Flag Register */ -/*! @{ */ -#define USB_CONFIGFLAG_CF_MASK (0x1U) -#define USB_CONFIGFLAG_CF_SHIFT (0U) -#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) -/*! @} */ - -/*! @name PORTSC1 - Port Status & Control */ -/*! @{ */ -#define USB_PORTSC1_CCS_MASK (0x1U) -#define USB_PORTSC1_CCS_SHIFT (0U) -#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) -#define USB_PORTSC1_CSC_MASK (0x2U) -#define USB_PORTSC1_CSC_SHIFT (1U) -#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) -#define USB_PORTSC1_PE_MASK (0x4U) -#define USB_PORTSC1_PE_SHIFT (2U) -#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) -#define USB_PORTSC1_PEC_MASK (0x8U) -#define USB_PORTSC1_PEC_SHIFT (3U) -#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) -#define USB_PORTSC1_OCA_MASK (0x10U) -#define USB_PORTSC1_OCA_SHIFT (4U) -#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) -#define USB_PORTSC1_OCC_MASK (0x20U) -#define USB_PORTSC1_OCC_SHIFT (5U) -#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) -#define USB_PORTSC1_FPR_MASK (0x40U) -#define USB_PORTSC1_FPR_SHIFT (6U) -#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) -#define USB_PORTSC1_SUSP_MASK (0x80U) -#define USB_PORTSC1_SUSP_SHIFT (7U) -#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) -#define USB_PORTSC1_PR_MASK (0x100U) -#define USB_PORTSC1_PR_SHIFT (8U) -#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) -#define USB_PORTSC1_HSP_MASK (0x200U) -#define USB_PORTSC1_HSP_SHIFT (9U) -#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) -#define USB_PORTSC1_LS_MASK (0xC00U) -#define USB_PORTSC1_LS_SHIFT (10U) -#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) -#define USB_PORTSC1_PP_MASK (0x1000U) -#define USB_PORTSC1_PP_SHIFT (12U) -#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) -#define USB_PORTSC1_PO_MASK (0x2000U) -#define USB_PORTSC1_PO_SHIFT (13U) -#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) -#define USB_PORTSC1_PIC_MASK (0xC000U) -#define USB_PORTSC1_PIC_SHIFT (14U) -#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) -#define USB_PORTSC1_PTC_MASK (0xF0000U) -#define USB_PORTSC1_PTC_SHIFT (16U) -#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) -#define USB_PORTSC1_WKCN_MASK (0x100000U) -#define USB_PORTSC1_WKCN_SHIFT (20U) -#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) -#define USB_PORTSC1_WKDC_MASK (0x200000U) -#define USB_PORTSC1_WKDC_SHIFT (21U) -#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) -#define USB_PORTSC1_WKOC_MASK (0x400000U) -#define USB_PORTSC1_WKOC_SHIFT (22U) -#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) -#define USB_PORTSC1_PHCD_MASK (0x800000U) -#define USB_PORTSC1_PHCD_SHIFT (23U) -#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) -#define USB_PORTSC1_PFSC_MASK (0x1000000U) -#define USB_PORTSC1_PFSC_SHIFT (24U) -#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) -#define USB_PORTSC1_PTS_2_MASK (0x2000000U) -#define USB_PORTSC1_PTS_2_SHIFT (25U) -#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) -#define USB_PORTSC1_PSPD_MASK (0xC000000U) -#define USB_PORTSC1_PSPD_SHIFT (26U) -#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) -#define USB_PORTSC1_PTW_MASK (0x10000000U) -#define USB_PORTSC1_PTW_SHIFT (28U) -#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) -#define USB_PORTSC1_STS_MASK (0x20000000U) -#define USB_PORTSC1_STS_SHIFT (29U) -#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) -#define USB_PORTSC1_PTS_1_MASK (0xC0000000U) -#define USB_PORTSC1_PTS_1_SHIFT (30U) -#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) -/*! @} */ - -/*! @name OTGSC - On-The-Go Status & control */ -/*! @{ */ -#define USB_OTGSC_VD_MASK (0x1U) -#define USB_OTGSC_VD_SHIFT (0U) -#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) -#define USB_OTGSC_VC_MASK (0x2U) -#define USB_OTGSC_VC_SHIFT (1U) -#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) -#define USB_OTGSC_OT_MASK (0x8U) -#define USB_OTGSC_OT_SHIFT (3U) -#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) -#define USB_OTGSC_DP_MASK (0x10U) -#define USB_OTGSC_DP_SHIFT (4U) -#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) -#define USB_OTGSC_IDPU_MASK (0x20U) -#define USB_OTGSC_IDPU_SHIFT (5U) -#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) -#define USB_OTGSC_ID_MASK (0x100U) -#define USB_OTGSC_ID_SHIFT (8U) -#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) -#define USB_OTGSC_AVV_MASK (0x200U) -#define USB_OTGSC_AVV_SHIFT (9U) -#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) -#define USB_OTGSC_ASV_MASK (0x400U) -#define USB_OTGSC_ASV_SHIFT (10U) -#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) -#define USB_OTGSC_BSV_MASK (0x800U) -#define USB_OTGSC_BSV_SHIFT (11U) -#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) -#define USB_OTGSC_BSE_MASK (0x1000U) -#define USB_OTGSC_BSE_SHIFT (12U) -#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) -#define USB_OTGSC_TOG_1MS_MASK (0x2000U) -#define USB_OTGSC_TOG_1MS_SHIFT (13U) -#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) -#define USB_OTGSC_DPS_MASK (0x4000U) -#define USB_OTGSC_DPS_SHIFT (14U) -#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) -#define USB_OTGSC_IDIS_MASK (0x10000U) -#define USB_OTGSC_IDIS_SHIFT (16U) -#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) -#define USB_OTGSC_AVVIS_MASK (0x20000U) -#define USB_OTGSC_AVVIS_SHIFT (17U) -#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) -#define USB_OTGSC_ASVIS_MASK (0x40000U) -#define USB_OTGSC_ASVIS_SHIFT (18U) -#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) -#define USB_OTGSC_BSVIS_MASK (0x80000U) -#define USB_OTGSC_BSVIS_SHIFT (19U) -#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) -#define USB_OTGSC_BSEIS_MASK (0x100000U) -#define USB_OTGSC_BSEIS_SHIFT (20U) -#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) -#define USB_OTGSC_STATUS_1MS_MASK (0x200000U) -#define USB_OTGSC_STATUS_1MS_SHIFT (21U) -#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) -#define USB_OTGSC_DPIS_MASK (0x400000U) -#define USB_OTGSC_DPIS_SHIFT (22U) -#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) -#define USB_OTGSC_IDIE_MASK (0x1000000U) -#define USB_OTGSC_IDIE_SHIFT (24U) -#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) -#define USB_OTGSC_AVVIE_MASK (0x2000000U) -#define USB_OTGSC_AVVIE_SHIFT (25U) -#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) -#define USB_OTGSC_ASVIE_MASK (0x4000000U) -#define USB_OTGSC_ASVIE_SHIFT (26U) -#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) -#define USB_OTGSC_BSVIE_MASK (0x8000000U) -#define USB_OTGSC_BSVIE_SHIFT (27U) -#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) -#define USB_OTGSC_BSEIE_MASK (0x10000000U) -#define USB_OTGSC_BSEIE_SHIFT (28U) -#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) -#define USB_OTGSC_EN_1MS_MASK (0x20000000U) -#define USB_OTGSC_EN_1MS_SHIFT (29U) -#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) -#define USB_OTGSC_DPIE_MASK (0x40000000U) -#define USB_OTGSC_DPIE_SHIFT (30U) -#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) -/*! @} */ - -/*! @name USBMODE - USB Device Mode */ -/*! @{ */ -#define USB_USBMODE_CM_MASK (0x3U) -#define USB_USBMODE_CM_SHIFT (0U) -#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) -#define USB_USBMODE_ES_MASK (0x4U) -#define USB_USBMODE_ES_SHIFT (2U) -#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) -#define USB_USBMODE_SLOM_MASK (0x8U) -#define USB_USBMODE_SLOM_SHIFT (3U) -#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) -#define USB_USBMODE_SDIS_MASK (0x10U) -#define USB_USBMODE_SDIS_SHIFT (4U) -#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) -/*! @} */ - -/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ -/*! @{ */ -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) -/*! @} */ - -/*! @name ENDPTPRIME - Endpoint Prime */ -/*! @{ */ -#define USB_ENDPTPRIME_PERB_MASK (0xFFU) -#define USB_ENDPTPRIME_PERB_SHIFT (0U) -#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) -#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) -#define USB_ENDPTPRIME_PETB_SHIFT (16U) -#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) -/*! @} */ - -/*! @name ENDPTFLUSH - Endpoint Flush */ -/*! @{ */ -#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) -#define USB_ENDPTFLUSH_FERB_SHIFT (0U) -#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) -#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) -#define USB_ENDPTFLUSH_FETB_SHIFT (16U) -#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) -/*! @} */ - -/*! @name ENDPTSTAT - Endpoint Status */ -/*! @{ */ -#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) -#define USB_ENDPTSTAT_ERBR_SHIFT (0U) -#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) -#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) -#define USB_ENDPTSTAT_ETBR_SHIFT (16U) -#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) -/*! @} */ - -/*! @name ENDPTCOMPLETE - Endpoint Complete */ -/*! @{ */ -#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) -#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) -#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) -#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) -#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) -#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) -/*! @} */ - -/*! @name ENDPTCTRL0 - Endpoint Control0 */ -/*! @{ */ -#define USB_ENDPTCTRL0_RXS_MASK (0x1U) -#define USB_ENDPTCTRL0_RXS_SHIFT (0U) -#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) -#define USB_ENDPTCTRL0_RXT_MASK (0xCU) -#define USB_ENDPTCTRL0_RXT_SHIFT (2U) -#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) -#define USB_ENDPTCTRL0_RXE_MASK (0x80U) -#define USB_ENDPTCTRL0_RXE_SHIFT (7U) -#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) -#define USB_ENDPTCTRL0_TXS_MASK (0x10000U) -#define USB_ENDPTCTRL0_TXS_SHIFT (16U) -#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) -#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) -#define USB_ENDPTCTRL0_TXT_SHIFT (18U) -#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) -#define USB_ENDPTCTRL0_TXE_MASK (0x800000U) -#define USB_ENDPTCTRL0_TXE_SHIFT (23U) -#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) -/*! @} */ - -/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ -/*! @{ */ -#define USB_ENDPTCTRL_RXS_MASK (0x1U) -#define USB_ENDPTCTRL_RXS_SHIFT (0U) -#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) -#define USB_ENDPTCTRL_RXD_MASK (0x2U) -#define USB_ENDPTCTRL_RXD_SHIFT (1U) -#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) -#define USB_ENDPTCTRL_RXT_MASK (0xCU) -#define USB_ENDPTCTRL_RXT_SHIFT (2U) -#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) -#define USB_ENDPTCTRL_RXI_MASK (0x20U) -#define USB_ENDPTCTRL_RXI_SHIFT (5U) -#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) -#define USB_ENDPTCTRL_RXR_MASK (0x40U) -#define USB_ENDPTCTRL_RXR_SHIFT (6U) -#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) -#define USB_ENDPTCTRL_RXE_MASK (0x80U) -#define USB_ENDPTCTRL_RXE_SHIFT (7U) -#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) -#define USB_ENDPTCTRL_TXS_MASK (0x10000U) -#define USB_ENDPTCTRL_TXS_SHIFT (16U) -#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) -#define USB_ENDPTCTRL_TXD_MASK (0x20000U) -#define USB_ENDPTCTRL_TXD_SHIFT (17U) -#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) -#define USB_ENDPTCTRL_TXT_MASK (0xC0000U) -#define USB_ENDPTCTRL_TXT_SHIFT (18U) -#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) -#define USB_ENDPTCTRL_TXI_MASK (0x200000U) -#define USB_ENDPTCTRL_TXI_SHIFT (21U) -#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) -#define USB_ENDPTCTRL_TXR_MASK (0x400000U) -#define USB_ENDPTCTRL_TXR_SHIFT (22U) -#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) -#define USB_ENDPTCTRL_TXE_MASK (0x800000U) -#define USB_ENDPTCTRL_TXE_SHIFT (23U) -#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) -/*! @} */ - -/* The count of USB_ENDPTCTRL */ -#define USB_ENDPTCTRL_COUNT (7U) - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -/** Peripheral USB1 base address */ -#define USB1_BASE (0x402E0000u) -/** Peripheral USB1 base pointer */ -#define USB1 ((USB_Type *)USB1_BASE) -/** Peripheral USB2 base address */ -#define USB2_BASE (0x402E0200u) -/** Peripheral USB2 base pointer */ -#define USB2 ((USB_Type *)USB2_BASE) -/** Array initializer of USB peripheral base addresses */ -#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE } -/** Array initializer of USB peripheral base pointers */ -#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 } -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn } -/* Backward compatibility */ -#define GPTIMER0CTL GPTIMER0CTRL -#define GPTIMER1CTL GPTIMER1CTRL -#define USB_SBUSCFG SBUSCFG -#define EPLISTADDR ENDPTLISTADDR -#define EPSETUPSR ENDPTSETUPSTAT -#define EPPRIME ENDPTPRIME -#define EPFLUSH ENDPTFLUSH -#define EPSR ENDPTSTAT -#define EPCOMPLETE ENDPTCOMPLETE -#define EPCR ENDPTCTRL -#define EPCR0 ENDPTCTRL0 -#define USBHS_ID_ID_MASK USB_ID_ID_MASK -#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT -#define USBHS_ID_ID(x) USB_ID_ID(x) -#define USBHS_ID_NID_MASK USB_ID_NID_MASK -#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT -#define USBHS_ID_NID(x) USB_ID_NID(x) -#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK -#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT -#define USBHS_ID_REVISION(x) USB_ID_REVISION(x) -#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK -#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT -#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x) -#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK -#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT -#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x) -#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK -#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT -#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x) -#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK -#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT -#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x) -#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK -#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT -#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x) -#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK -#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT -#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x) -#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK -#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT -#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x) -#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK -#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT -#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x) -#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK -#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT -#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x) -#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK -#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT -#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x) -#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK -#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT -#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x) -#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK -#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT -#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x) -#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK -#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT -#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x) -#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK -#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT -#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x) -#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK -#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT -#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x) -#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK -#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT -#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x) -#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK -#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT -#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x) -#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK -#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT -#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x) -#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK -#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT -#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x) -#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK -#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT -#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x) -#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK -#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT -#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x) -#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK -#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT -#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x) -#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x) -#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK -#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT -#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x) -#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK -#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT -#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x) -#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK -#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT -#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x) -#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK -#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT -#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x) -#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK -#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT -#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x) -#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK -#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT -#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x) -#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK -#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT -#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x) -#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK -#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT -#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x) -#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK -#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT -#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x) -#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK -#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT -#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x) -#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK -#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT -#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x) -#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK -#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT -#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x) -#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK -#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT -#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x) -#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK -#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT -#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x) -#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK -#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT -#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x) -#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK -#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT -#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x) -#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK -#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT -#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x) -#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK -#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT -#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x) -#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK -#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT -#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x) -#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK -#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT -#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x) -#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK -#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT -#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x) -#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK -#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT -#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x) -#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK -#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT -#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x) -#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK -#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT -#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x) -#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK -#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT -#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x) -#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK -#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT -#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x) -#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK -#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT -#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x) -#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK -#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT -#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x) -#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK -#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT -#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x) -#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK -#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT -#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x) -#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK -#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT -#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x) -#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK -#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT -#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x) -#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK -#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT -#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x) -#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK -#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT -#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x) -#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK -#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT -#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x) -#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK -#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT -#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x) -#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK -#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT -#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x) -#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK -#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT -#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x) -#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK -#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT -#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x) -#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK -#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT -#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x) -#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK -#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT -#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x) -#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK -#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT -#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x) -#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK -#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT -#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x) -#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK -#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT -#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x) -#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK -#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT -#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x) -#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK -#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT -#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x) -#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK -#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT -#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x) -#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK -#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT -#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x) -#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK -#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT -#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x) -#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK -#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT -#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x) -#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK -#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT -#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x) -#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK -#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT -#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x) -#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK -#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT -#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x) -#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK -#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT -#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x) -#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK -#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT -#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x) -#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK -#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT -#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x) -#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK -#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT -#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x) -#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK -#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT -#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x) -#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK -#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT -#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x) -#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK -#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT -#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x) -#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK -#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT -#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x) -#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK -#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT -#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x) -#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK -#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT -#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x) -#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK -#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT -#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x) -#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK -#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT -#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x) -#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK -#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT -#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x) -#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK -#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT -#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x) -#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK -#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT -#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x) -#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK -#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT -#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x) -#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK -#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT -#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x) -#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK -#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT -#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x) -#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK -#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT -#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x) -#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK -#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT -#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x) -#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK -#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT -#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x) -#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK -#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT -#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x) -#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK -#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT -#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x) -#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK -#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT -#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x) -#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK -#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT -#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x) -#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK -#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT -#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x) -#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK -#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT -#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x) -#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK -#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT -#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x) -#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK -#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT -#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x) -#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK -#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT -#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x) -#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK -#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT -#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x) -#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK -#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT -#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x) -#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK -#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT -#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x) -#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK -#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT -#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x) -#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK -#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT -#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x) -#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK -#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT -#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x) -#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK -#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT -#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x) -#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK -#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT -#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x) -#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK -#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT -#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x) -#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK -#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT -#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x) -#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK -#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT -#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x) -#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK -#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT -#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x) -#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK -#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT -#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x) -#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK -#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT -#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x) -#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK -#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT -#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x) -#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK -#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT -#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x) -#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK -#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT -#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x) -#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK -#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT -#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x) -#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK -#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT -#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x) -#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK -#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT -#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x) -#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK -#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT -#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x) -#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK -#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT -#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x) -#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK -#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT -#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x) -#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK -#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT -#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x) -#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK -#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT -#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x) -#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK -#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT -#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x) -#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK -#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT -#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x) -#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK -#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT -#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x) -#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK -#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT -#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x) -#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK -#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT -#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x) -#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK -#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT -#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x) -#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK -#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT -#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x) -#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK -#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT -#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x) -#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK -#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT -#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x) -#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK -#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT -#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x) -#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK -#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT -#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x) -#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK -#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT -#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x) -#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK -#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT -#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x) -#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK -#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT -#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x) -#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK -#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT -#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x) -#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK -#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT -#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x) -#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK -#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT -#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x) -#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK -#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT -#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x) -#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK -#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT -#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x) -#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK -#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT -#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x) -#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK -#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT -#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x) -#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK -#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT -#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x) -#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK -#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT -#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x) -#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK -#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT -#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x) -#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK -#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT -#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) -#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK -#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT -#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x) -#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK -#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT -#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x) -#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK -#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT -#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x) -#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK -#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT -#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x) -#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK -#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT -#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x) -#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK -#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT -#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x) -#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK -#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT -#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x) -#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK -#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT -#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x) -#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK -#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT -#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x) -#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK -#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT -#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x) -#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK -#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT -#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x) -#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK -#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT -#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x) -#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK -#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT -#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x) -#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK -#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT -#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x) -#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK -#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT -#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x) -#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK -#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT -#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x) -#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK -#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT -#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x) -#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK -#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT -#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x) -#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK -#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT -#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x) -#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK -#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT -#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x) -#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK -#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT -#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x) -#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK -#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT -#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x) -#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK -#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT -#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x) -#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK -#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT -#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x) -#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK -#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT -#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x) -#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK -#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT -#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x) -#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT -#define USBHS_Type USB_Type -#define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE } -#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn } -#define USBHS_IRQHandler USB_OTG1_IRQHandler - - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBNC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer - * @{ - */ - -/** USBNC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t USB_OTGn_CTRL; /**< USB OTG1 Control Register..USB OTG2 Control Register, offset: 0x800 */ - uint8_t RESERVED_1[20]; - __IO uint32_t USB_OTGn_PHY_CTRL_0; /**< OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register, offset: 0x818 */ -} USBNC_Type; - -/* ---------------------------------------------------------------------------- - -- USBNC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBNC_Register_Masks USBNC Register Masks - * @{ - */ - -/*! @name USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register */ -/*! @{ */ -#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) -#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) -#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) -#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U) -#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U) -#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK) -#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U) -#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U) -#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK) -#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U) -#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U) -#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK) -#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U) -#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U) -#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK) -#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U) -#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U) -#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK) -#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U) -#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U) -#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK) -#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U) -#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U) -#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK) -#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U) -#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U) -#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK) -#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) -#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) -#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) -/*! @} */ - -/*! @name USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register */ -/*! @{ */ -#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U) -#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U) -#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBNC_Register_Masks */ - - -/* USBNC - Peripheral instance base addresses */ -/** Peripheral USBNC1 base address */ -#define USBNC1_BASE (0x402E0000u) -/** Peripheral USBNC1 base pointer */ -#define USBNC1 ((USBNC_Type *)USBNC1_BASE) -/** Peripheral USBNC2 base address */ -#define USBNC2_BASE (0x402E0004u) -/** Peripheral USBNC2 base pointer */ -#define USBNC2 ((USBNC_Type *)USBNC2_BASE) -/** Array initializer of USBNC peripheral base addresses */ -#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE } -/** Array initializer of USBNC peripheral base pointers */ -#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 } - -/*! - * @} - */ /* end of group USBNC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBPHY Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer - * @{ - */ - -/** USBPHY - Register Layout Typedef */ -typedef struct { - __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ - __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ - __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ - __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ - __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ - __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ - __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ - __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ - __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ - __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ - __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ - __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ - __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ - __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ - __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ - __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ - __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ - uint8_t RESERVED_0[12]; - __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */ - __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ - __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ - __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ - __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ - uint8_t RESERVED_1[12]; - __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ - __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ - __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ - __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ - __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ -} USBPHY_Type; - -/* ---------------------------------------------------------------------------- - -- USBPHY Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Register_Masks USBPHY Register Masks - * @{ - */ - -/*! @name PWD - USB PHY Power-Down Register */ -/*! @{ */ -#define USBPHY_PWD_RSVD0_MASK (0x3FFU) -#define USBPHY_PWD_RSVD0_SHIFT (0U) -#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK) -#define USBPHY_PWD_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TXPWDFS_SHIFT (10U) -#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) -#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) -#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) -#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) -#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) -#define USBPHY_PWD_RSVD1_MASK (0x1E000U) -#define USBPHY_PWD_RSVD1_SHIFT (13U) -#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK) -#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_RXPWDENV_SHIFT (17U) -#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) -#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) -#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) -#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) -#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) -#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_RXPWDRX_SHIFT (20U) -#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) -#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U) -#define USBPHY_PWD_RSVD2_SHIFT (21U) -#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK) -/*! @} */ - -/*! @name PWD_SET - USB PHY Power-Down Register */ -/*! @{ */ -#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU) -#define USBPHY_PWD_SET_RSVD0_SHIFT (0U) -#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK) -#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) -#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) -#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) -#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) -#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) -#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) -#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U) -#define USBPHY_PWD_SET_RSVD1_SHIFT (13U) -#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK) -#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) -#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) -#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) -#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) -#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) -#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) -#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) -#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) -#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U) -#define USBPHY_PWD_SET_RSVD2_SHIFT (21U) -#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK) -/*! @} */ - -/*! @name PWD_CLR - USB PHY Power-Down Register */ -/*! @{ */ -#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU) -#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U) -#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK) -#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) -#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) -#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) -#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) -#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) -#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) -#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U) -#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U) -#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK) -#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) -#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) -#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) -#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) -#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) -#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) -#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) -#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) -#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U) -#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U) -#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK) -/*! @} */ - -/*! @name PWD_TOG - USB PHY Power-Down Register */ -/*! @{ */ -#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU) -#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U) -#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK) -#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) -#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) -#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) -#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) -#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) -#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) -#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) -#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) -#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) -#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U) -#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U) -#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK) -#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) -#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) -#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) -#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) -#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) -#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) -#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) -#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) -#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) -#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) -#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) -#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) -#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U) -#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U) -#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK) -/*! @} */ - -/*! @name TX - USB PHY Transmitter Control Register */ -/*! @{ */ -#define USBPHY_TX_D_CAL_MASK (0xFU) -#define USBPHY_TX_D_CAL_SHIFT (0U) -#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) -#define USBPHY_TX_RSVD0_MASK (0xF0U) -#define USBPHY_TX_RSVD0_SHIFT (4U) -#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK) -#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) -#define USBPHY_TX_TXCAL45DN_SHIFT (8U) -#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) -#define USBPHY_TX_RSVD1_MASK (0xF000U) -#define USBPHY_TX_RSVD1_SHIFT (12U) -#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK) -#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) -#define USBPHY_TX_RSVD2_MASK (0x3F00000U) -#define USBPHY_TX_RSVD2_SHIFT (20U) -#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK) -#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) -#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U) -#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK) -#define USBPHY_TX_RSVD5_MASK (0xE0000000U) -#define USBPHY_TX_RSVD5_SHIFT (29U) -#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK) -/*! @} */ - -/*! @name TX_SET - USB PHY Transmitter Control Register */ -/*! @{ */ -#define USBPHY_TX_SET_D_CAL_MASK (0xFU) -#define USBPHY_TX_SET_D_CAL_SHIFT (0U) -#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) -#define USBPHY_TX_SET_RSVD0_MASK (0xF0U) -#define USBPHY_TX_SET_RSVD0_SHIFT (4U) -#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK) -#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) -#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) -#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) -#define USBPHY_TX_SET_RSVD1_MASK (0xF000U) -#define USBPHY_TX_SET_RSVD1_SHIFT (12U) -#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK) -#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) -#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U) -#define USBPHY_TX_SET_RSVD2_SHIFT (20U) -#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK) -#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) -#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U) -#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK) -#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U) -#define USBPHY_TX_SET_RSVD5_SHIFT (29U) -#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK) -/*! @} */ - -/*! @name TX_CLR - USB PHY Transmitter Control Register */ -/*! @{ */ -#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) -#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) -#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) -#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U) -#define USBPHY_TX_CLR_RSVD0_SHIFT (4U) -#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK) -#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) -#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) -#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) -#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U) -#define USBPHY_TX_CLR_RSVD1_SHIFT (12U) -#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK) -#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) -#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U) -#define USBPHY_TX_CLR_RSVD2_SHIFT (20U) -#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK) -#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) -#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U) -#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK) -#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U) -#define USBPHY_TX_CLR_RSVD5_SHIFT (29U) -#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK) -/*! @} */ - -/*! @name TX_TOG - USB PHY Transmitter Control Register */ -/*! @{ */ -#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) -#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) -#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) -#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U) -#define USBPHY_TX_TOG_RSVD0_SHIFT (4U) -#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK) -#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) -#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) -#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) -#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U) -#define USBPHY_TX_TOG_RSVD1_SHIFT (12U) -#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK) -#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) -#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) -#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) -#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U) -#define USBPHY_TX_TOG_RSVD2_SHIFT (20U) -#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK) -#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) -#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U) -#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK) -#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U) -#define USBPHY_TX_TOG_RSVD5_SHIFT (29U) -#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK) -/*! @} */ - -/*! @name RX - USB PHY Receiver Control Register */ -/*! @{ */ -#define USBPHY_RX_ENVADJ_MASK (0x7U) -#define USBPHY_RX_ENVADJ_SHIFT (0U) -#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) -#define USBPHY_RX_RSVD0_MASK (0x8U) -#define USBPHY_RX_RSVD0_SHIFT (3U) -#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK) -#define USBPHY_RX_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_DISCONADJ_SHIFT (4U) -#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) -#define USBPHY_RX_RSVD1_MASK (0x3FFF80U) -#define USBPHY_RX_RSVD1_SHIFT (7U) -#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK) -#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_RXDBYPASS_SHIFT (22U) -#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) -#define USBPHY_RX_RSVD2_MASK (0xFF800000U) -#define USBPHY_RX_RSVD2_SHIFT (23U) -#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK) -/*! @} */ - -/*! @name RX_SET - USB PHY Receiver Control Register */ -/*! @{ */ -#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) -#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) -#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) -#define USBPHY_RX_SET_RSVD0_MASK (0x8U) -#define USBPHY_RX_SET_RSVD0_SHIFT (3U) -#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK) -#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) -#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) -#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U) -#define USBPHY_RX_SET_RSVD1_SHIFT (7U) -#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK) -#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) -#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) -#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U) -#define USBPHY_RX_SET_RSVD2_SHIFT (23U) -#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK) -/*! @} */ - -/*! @name RX_CLR - USB PHY Receiver Control Register */ -/*! @{ */ -#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) -#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) -#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) -#define USBPHY_RX_CLR_RSVD0_MASK (0x8U) -#define USBPHY_RX_CLR_RSVD0_SHIFT (3U) -#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK) -#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) -#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) -#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U) -#define USBPHY_RX_CLR_RSVD1_SHIFT (7U) -#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK) -#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) -#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) -#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U) -#define USBPHY_RX_CLR_RSVD2_SHIFT (23U) -#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK) -/*! @} */ - -/*! @name RX_TOG - USB PHY Receiver Control Register */ -/*! @{ */ -#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) -#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) -#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) -#define USBPHY_RX_TOG_RSVD0_MASK (0x8U) -#define USBPHY_RX_TOG_RSVD0_SHIFT (3U) -#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK) -#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) -#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) -#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) -#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U) -#define USBPHY_RX_TOG_RSVD1_SHIFT (7U) -#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK) -#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) -#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) -#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) -#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U) -#define USBPHY_RX_TOG_RSVD2_SHIFT (23U) -#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK) -/*! @} */ - -/*! @name CTRL - USB PHY General Control Register */ -/*! @{ */ -#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) -#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) -#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) -#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) -#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) -#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) -#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) -#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) -#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) -#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) -#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) -#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) -#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) -#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) -#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) -#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) -#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) -#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) -#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) -#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) -#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) -#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) -#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) -#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) -#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) -#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) -#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U) -#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U) -#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) -#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U) -#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U) -#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK) -#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) -#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_RSVD1_MASK (0x6000000U) -#define USBPHY_CTRL_RSVD1_SHIFT (25U) -#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK) -#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) -#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) -#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) -#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_SET - USB PHY General Control Register */ -/*! @{ */ -#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) -#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) -#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) -#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) -#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) -#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) -#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) -#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) -#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) -#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) -#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) -#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) -#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) -#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) -#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) -#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) -#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) -#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) -#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) -#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) -#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) -#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U) -#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U) -#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) -#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U) -#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U) -#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK) -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) -#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U) -#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U) -#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK) -#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) -#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) -#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_CLR - USB PHY General Control Register */ -/*! @{ */ -#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) -#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) -#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) -#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) -#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) -#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) -#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) -#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) -#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) -#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) -#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) -#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) -#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) -#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) -#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) -#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) -#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) -#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) -#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) -#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U) -#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U) -#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) -#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U) -#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U) -#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK) -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U) -#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U) -#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) -#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) -#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) -/*! @} */ - -/*! @name CTRL_TOG - USB PHY General Control Register */ -/*! @{ */ -#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) -#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) -#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) -#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) -#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) -#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) -#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) -#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) -#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) -#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) -#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) -#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) -#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) -#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) -#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) -#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) -#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) -#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) -#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) -#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) -#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) -#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) -#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) -#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) -#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) -#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) -#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U) -#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U) -#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) -#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U) -#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U) -#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK) -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U) -#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U) -#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) -#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) -#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) -#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) -#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) -#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) -#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) -/*! @} */ - -/*! @name STATUS - USB PHY Status Register */ -/*! @{ */ -#define USBPHY_STATUS_RSVD0_MASK (0x7U) -#define USBPHY_STATUS_RSVD0_SHIFT (0U) -#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) -#define USBPHY_STATUS_RSVD1_MASK (0x30U) -#define USBPHY_STATUS_RSVD1_SHIFT (4U) -#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK) -#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) -#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) -#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) -#define USBPHY_STATUS_RSVD2_MASK (0x80U) -#define USBPHY_STATUS_RSVD2_SHIFT (7U) -#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK) -#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) -#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) -#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) -#define USBPHY_STATUS_RSVD3_MASK (0x200U) -#define USBPHY_STATUS_RSVD3_SHIFT (9U) -#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK) -#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) -#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) -#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) -#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U) -#define USBPHY_STATUS_RSVD4_SHIFT (11U) -#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK) -/*! @} */ - -/*! @name DEBUG - USB PHY Debug Register */ -/*! @{ */ -#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG_RSVD0_MASK (0xC0U) -#define USBPHY_DEBUG_RSVD0_SHIFT (6U) -#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK) -#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG_RSVD1_MASK (0xE000U) -#define USBPHY_DEBUG_RSVD1_SHIFT (13U) -#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK) -#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U) -#define USBPHY_DEBUG_RSVD2_SHIFT (21U) -#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK) -#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK) -#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U) -#define USBPHY_DEBUG_RSVD3_SHIFT (31U) -#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK) -/*! @} */ - -/*! @name DEBUG_SET - USB PHY Debug Register */ -/*! @{ */ -#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U) -#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U) -#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK) -#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U) -#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U) -#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK) -#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U) -#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U) -#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK) -#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK) -#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U) -#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U) -#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK) -/*! @} */ - -/*! @name DEBUG_CLR - USB PHY Debug Register */ -/*! @{ */ -#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U) -#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U) -#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK) -#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U) -#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U) -#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK) -#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U) -#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U) -#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK) -#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK) -#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U) -#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U) -#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK) -/*! @} */ - -/*! @name DEBUG_TOG - USB PHY Debug Register */ -/*! @{ */ -#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U) -#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U) -#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK) -#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U) -#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U) -#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK) -#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U) -#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U) -#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK) -#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK) -#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U) -#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U) -#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK) -/*! @} */ - -/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U) -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U) -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) -/*! @} */ - -/*! @name DEBUG1 - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU) -#define USBPHY_DEBUG1_RSVD0_SHIFT (0U) -#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK) -#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) -#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U) -#define USBPHY_DEBUG1_RSVD1_SHIFT (15U) -#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK) -/*! @} */ - -/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU) -#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U) -#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK) -#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) -#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U) -#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U) -#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK) -/*! @} */ - -/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU) -#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U) -#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK) -#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) -#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U) -#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U) -#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK) -/*! @} */ - -/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU) -#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U) -#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK) -#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) -#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U) -#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U) -#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK) -/*! @} */ - -/*! @name VERSION - UTMI RTL Version */ -/*! @{ */ -#define USBPHY_VERSION_STEP_MASK (0xFFFFU) -#define USBPHY_VERSION_STEP_SHIFT (0U) -#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) -#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) -#define USBPHY_VERSION_MINOR_SHIFT (16U) -#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) -#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) -#define USBPHY_VERSION_MAJOR_SHIFT (24U) -#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USBPHY_Register_Masks */ - - -/* USBPHY - Peripheral instance base addresses */ -/** Peripheral USBPHY1 base address */ -#define USBPHY1_BASE (0x400D9000u) -/** Peripheral USBPHY1 base pointer */ -#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) -/** Peripheral USBPHY2 base address */ -#define USBPHY2_BASE (0x400DA000u) -/** Peripheral USBPHY2 base pointer */ -#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) -/** Array initializer of USBPHY peripheral base addresses */ -#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE } -/** Array initializer of USBPHY peripheral base pointers */ -#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 } -/** Interrupt vectors for the USBPHY peripheral type */ -#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn } -/* Backward compatibility */ -#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK -#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT -#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) -#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK -#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT -#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) - - -/*! - * @} - */ /* end of group USBPHY_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB_ANALOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer - * @{ - */ - -/** USB_ANALOG - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[416]; - struct { /* offset: 0x1A0, array step: 0x60 */ - __IO uint32_t VBUS_DETECT; /**< USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60 */ - __IO uint32_t VBUS_DETECT_SET; /**< USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60 */ - __IO uint32_t VBUS_DETECT_CLR; /**< USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60 */ - __IO uint32_t VBUS_DETECT_TOG; /**< USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60 */ - __IO uint32_t CHRG_DETECT; /**< USB Charger Detect Register, array offset: 0x1B0, array step: 0x60 */ - __IO uint32_t CHRG_DETECT_SET; /**< USB Charger Detect Register, array offset: 0x1B4, array step: 0x60 */ - __IO uint32_t CHRG_DETECT_CLR; /**< USB Charger Detect Register, array offset: 0x1B8, array step: 0x60 */ - __IO uint32_t CHRG_DETECT_TOG; /**< USB Charger Detect Register, array offset: 0x1BC, array step: 0x60 */ - __I uint32_t VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60 */ - uint8_t RESERVED_0[12]; - __I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60 */ - uint8_t RESERVED_1[28]; - __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */ - __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */ - __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */ - __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */ - } INSTANCE[2]; - __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */ -} USB_ANALOG_Type; - -/* ---------------------------------------------------------------------------- - -- USB_ANALOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks - * @{ - */ - -/*! @name VBUS_DETECT - USB VBUS Detect Register */ -/*! @{ */ -#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) -#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) -#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) -#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) -#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) -#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) -#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK) -#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) -#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) -#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) -/*! @} */ - -/* The count of USB_ANALOG_VBUS_DETECT */ -#define USB_ANALOG_VBUS_DETECT_COUNT (2U) - -/*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ -/*! @{ */ -#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) -#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) -#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) -#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) -#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) -#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) -#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) -#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) -#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) -#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) -/*! @} */ - -/* The count of USB_ANALOG_VBUS_DETECT_SET */ -#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U) - -/*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ -/*! @{ */ -#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) -#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) -#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) -#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) -#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) -#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) -#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) -#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) -#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) -#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) -/*! @} */ - -/* The count of USB_ANALOG_VBUS_DETECT_CLR */ -#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U) - -/*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ -/*! @{ */ -#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) -#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) -#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) -#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) -#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) -#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) -#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) -#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) -#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) -#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) -/*! @} */ - -/* The count of USB_ANALOG_VBUS_DETECT_TOG */ -#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U) - -/*! @name CHRG_DETECT - USB Charger Detect Register */ -/*! @{ */ -#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) -#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) -#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) -#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) -#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) -#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK) -#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) -#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) -#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) -/*! @} */ - -/* The count of USB_ANALOG_CHRG_DETECT */ -#define USB_ANALOG_CHRG_DETECT_COUNT (2U) - -/*! @name CHRG_DETECT_SET - USB Charger Detect Register */ -/*! @{ */ -#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) -#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) -#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) -#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) -#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) -#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK) -#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) -#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) -#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) -/*! @} */ - -/* The count of USB_ANALOG_CHRG_DETECT_SET */ -#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U) - -/*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ -/*! @{ */ -#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) -#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) -#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) -#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) -#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) -#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) -#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) -#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) -#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) -/*! @} */ - -/* The count of USB_ANALOG_CHRG_DETECT_CLR */ -#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U) - -/*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ -/*! @{ */ -#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) -#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) -#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) -#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) -#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) -#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) -#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) -#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) -#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) -/*! @} */ - -/* The count of USB_ANALOG_CHRG_DETECT_TOG */ -#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U) - -/*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ -/*! @{ */ -#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) -#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) -#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) -#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U) -#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U) -#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK) -#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U) -#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U) -#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK) -#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) -#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) -#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) -/*! @} */ - -/* The count of USB_ANALOG_VBUS_DETECT_STAT */ -#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U) - -/*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ -/*! @{ */ -#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) -#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) -#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) -#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U) -#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U) -#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK) -#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U) -#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U) -#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK) -#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) -#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) -#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) -/*! @} */ - -/* The count of USB_ANALOG_CHRG_DETECT_STAT */ -#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U) - -/*! @name MISC - USB Misc Register */ -/*! @{ */ -#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) -#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) -#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) -#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U) -#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U) -#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK) -#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) -#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) -#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) -/*! @} */ - -/* The count of USB_ANALOG_MISC */ -#define USB_ANALOG_MISC_COUNT (2U) - -/*! @name MISC_SET - USB Misc Register */ -/*! @{ */ -#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) -#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) -#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) -#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U) -#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U) -#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK) -#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) -#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) -#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) -/*! @} */ - -/* The count of USB_ANALOG_MISC_SET */ -#define USB_ANALOG_MISC_SET_COUNT (2U) - -/*! @name MISC_CLR - USB Misc Register */ -/*! @{ */ -#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) -#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) -#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) -#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U) -#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U) -#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK) -#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) -#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) -#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) -/*! @} */ - -/* The count of USB_ANALOG_MISC_CLR */ -#define USB_ANALOG_MISC_CLR_COUNT (2U) - -/*! @name MISC_TOG - USB Misc Register */ -/*! @{ */ -#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) -#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) -#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) -#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U) -#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U) -#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK) -#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) -#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) -#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) -/*! @} */ - -/* The count of USB_ANALOG_MISC_TOG */ -#define USB_ANALOG_MISC_TOG_COUNT (2U) - -/*! @name DIGPROG - Chip Silicon Version */ -/*! @{ */ -#define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU) -#define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U) -#define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_ANALOG_Register_Masks */ - - -/* USB_ANALOG - Peripheral instance base addresses */ -/** Peripheral USB_ANALOG base address */ -#define USB_ANALOG_BASE (0x400D8000u) -/** Peripheral USB_ANALOG base pointer */ -#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) -/** Array initializer of USB_ANALOG peripheral base addresses */ -#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } -/** Array initializer of USB_ANALOG peripheral base pointers */ -#define USB_ANALOG_BASE_PTRS { USB_ANALOG } - -/*! - * @} - */ /* end of group USB_ANALOG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USDHC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer - * @{ - */ - -/** USDHC - Register Layout Typedef */ -typedef struct { - __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ - __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ - __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ - __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ - __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ - __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ - __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ - __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ - __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ - __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ - __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ - __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ - __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ - __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ - __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ - __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ - __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ - __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ - __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ - uint8_t RESERVED_0[4]; - __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ - __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ - __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ - uint8_t RESERVED_1[4]; - __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ - __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ - __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ - uint8_t RESERVED_2[84]; - __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ - __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ - __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ - __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ -} USDHC_Type; - -/* ---------------------------------------------------------------------------- - -- USDHC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USDHC_Register_Masks USDHC Register Masks - * @{ - */ - -/*! @name DS_ADDR - DMA System Address */ -/*! @{ */ -#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) -#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) -#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) -/*! @} */ - -/*! @name BLK_ATT - Block Attributes */ -/*! @{ */ -#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) -#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) -#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) -#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) -#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) -#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) -/*! @} */ - -/*! @name CMD_ARG - Command Argument */ -/*! @{ */ -#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) -#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) -#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) -/*! @} */ - -/*! @name CMD_XFR_TYP - Command Transfer Type */ -/*! @{ */ -#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) -#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) -#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) -#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) -#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) -#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) -#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) -#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) -#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) -#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) -#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) -#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) -#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) -#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) -#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) -#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) -#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) -#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) -/*! @} */ - -/*! @name CMD_RSP0 - Command Response0 */ -/*! @{ */ -#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) -#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) -#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) -/*! @} */ - -/*! @name CMD_RSP1 - Command Response1 */ -/*! @{ */ -#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) -#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) -#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) -/*! @} */ - -/*! @name CMD_RSP2 - Command Response2 */ -/*! @{ */ -#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) -#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) -#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) -/*! @} */ - -/*! @name CMD_RSP3 - Command Response3 */ -/*! @{ */ -#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) -#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) -#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) -/*! @} */ - -/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ -/*! @{ */ -#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) -#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) -#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) -/*! @} */ - -/*! @name PRES_STATE - Present State */ -/*! @{ */ -#define USDHC_PRES_STATE_CIHB_MASK (0x1U) -#define USDHC_PRES_STATE_CIHB_SHIFT (0U) -#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) -#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) -#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) -#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) -#define USDHC_PRES_STATE_DLA_MASK (0x4U) -#define USDHC_PRES_STATE_DLA_SHIFT (2U) -#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) -#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) -#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) -#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) -#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) -#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) -#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) -#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) -#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) -#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) -#define USDHC_PRES_STATE_PEROFF_MASK (0x40U) -#define USDHC_PRES_STATE_PEROFF_SHIFT (6U) -#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) -#define USDHC_PRES_STATE_SDOFF_MASK (0x80U) -#define USDHC_PRES_STATE_SDOFF_SHIFT (7U) -#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) -#define USDHC_PRES_STATE_WTA_MASK (0x100U) -#define USDHC_PRES_STATE_WTA_SHIFT (8U) -#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) -#define USDHC_PRES_STATE_RTA_MASK (0x200U) -#define USDHC_PRES_STATE_RTA_SHIFT (9U) -#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) -#define USDHC_PRES_STATE_BWEN_MASK (0x400U) -#define USDHC_PRES_STATE_BWEN_SHIFT (10U) -#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) -#define USDHC_PRES_STATE_BREN_MASK (0x800U) -#define USDHC_PRES_STATE_BREN_SHIFT (11U) -#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) -#define USDHC_PRES_STATE_RTR_MASK (0x1000U) -#define USDHC_PRES_STATE_RTR_SHIFT (12U) -#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) -#define USDHC_PRES_STATE_TSCD_MASK (0x8000U) -#define USDHC_PRES_STATE_TSCD_SHIFT (15U) -#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) -#define USDHC_PRES_STATE_CINST_MASK (0x10000U) -#define USDHC_PRES_STATE_CINST_SHIFT (16U) -#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) -#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) -#define USDHC_PRES_STATE_CDPL_SHIFT (18U) -#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) -#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) -#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) -#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) -#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) -#define USDHC_PRES_STATE_CLSL_SHIFT (23U) -#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) -#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) -#define USDHC_PRES_STATE_DLSL_SHIFT (24U) -#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) -/*! @} */ - -/*! @name PROT_CTRL - Protocol Control */ -/*! @{ */ -#define USDHC_PROT_CTRL_LCTL_MASK (0x1U) -#define USDHC_PROT_CTRL_LCTL_SHIFT (0U) -#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) -#define USDHC_PROT_CTRL_DTW_MASK (0x6U) -#define USDHC_PROT_CTRL_DTW_SHIFT (1U) -#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) -#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) -#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) -#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) -#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) -#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) -#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) -#define USDHC_PROT_CTRL_CDTL_MASK (0x40U) -#define USDHC_PROT_CTRL_CDTL_SHIFT (6U) -#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) -#define USDHC_PROT_CTRL_CDSS_MASK (0x80U) -#define USDHC_PROT_CTRL_CDSS_SHIFT (7U) -#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) -#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) -#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) -#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) -#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) -#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) -#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) -#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) -#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) -#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) -#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) -#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) -#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) -#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) -#define USDHC_PROT_CTRL_IABG_SHIFT (19U) -#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) -#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) -#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) -#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) -#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) -#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) -#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) -#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) -#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) -#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) -#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) -#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) -#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) -#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) -#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) -#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) -#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) -#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) -#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) -/*! @} */ - -/*! @name SYS_CTRL - System Control */ -/*! @{ */ -#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) -#define USDHC_SYS_CTRL_DVS_SHIFT (4U) -#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) -#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) -#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) -#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) -#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) -#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) -#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) -#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) -#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) -#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) -#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) -#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) -#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) -#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) -#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) -#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) -#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) -#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) -#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) -#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) -#define USDHC_SYS_CTRL_INITA_SHIFT (27U) -#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) -#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) -#define USDHC_SYS_CTRL_RSTT_SHIFT (28U) -#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) -/*! @} */ - -/*! @name INT_STATUS - Interrupt Status */ -/*! @{ */ -#define USDHC_INT_STATUS_CC_MASK (0x1U) -#define USDHC_INT_STATUS_CC_SHIFT (0U) -#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) -#define USDHC_INT_STATUS_TC_MASK (0x2U) -#define USDHC_INT_STATUS_TC_SHIFT (1U) -#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) -#define USDHC_INT_STATUS_BGE_MASK (0x4U) -#define USDHC_INT_STATUS_BGE_SHIFT (2U) -#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) -#define USDHC_INT_STATUS_DINT_MASK (0x8U) -#define USDHC_INT_STATUS_DINT_SHIFT (3U) -#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) -#define USDHC_INT_STATUS_BWR_MASK (0x10U) -#define USDHC_INT_STATUS_BWR_SHIFT (4U) -#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) -#define USDHC_INT_STATUS_BRR_MASK (0x20U) -#define USDHC_INT_STATUS_BRR_SHIFT (5U) -#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) -#define USDHC_INT_STATUS_CINS_MASK (0x40U) -#define USDHC_INT_STATUS_CINS_SHIFT (6U) -#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) -#define USDHC_INT_STATUS_CRM_MASK (0x80U) -#define USDHC_INT_STATUS_CRM_SHIFT (7U) -#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) -#define USDHC_INT_STATUS_CINT_MASK (0x100U) -#define USDHC_INT_STATUS_CINT_SHIFT (8U) -#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) -#define USDHC_INT_STATUS_RTE_MASK (0x1000U) -#define USDHC_INT_STATUS_RTE_SHIFT (12U) -#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) -#define USDHC_INT_STATUS_TP_MASK (0x4000U) -#define USDHC_INT_STATUS_TP_SHIFT (14U) -#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) -#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) -#define USDHC_INT_STATUS_CTOE_SHIFT (16U) -#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) -#define USDHC_INT_STATUS_CCE_MASK (0x20000U) -#define USDHC_INT_STATUS_CCE_SHIFT (17U) -#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) -#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) -#define USDHC_INT_STATUS_CEBE_SHIFT (18U) -#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) -#define USDHC_INT_STATUS_CIE_MASK (0x80000U) -#define USDHC_INT_STATUS_CIE_SHIFT (19U) -#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) -#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) -#define USDHC_INT_STATUS_DTOE_SHIFT (20U) -#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) -#define USDHC_INT_STATUS_DCE_MASK (0x200000U) -#define USDHC_INT_STATUS_DCE_SHIFT (21U) -#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) -#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) -#define USDHC_INT_STATUS_DEBE_SHIFT (22U) -#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) -#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) -#define USDHC_INT_STATUS_AC12E_SHIFT (24U) -#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) -#define USDHC_INT_STATUS_TNE_MASK (0x4000000U) -#define USDHC_INT_STATUS_TNE_SHIFT (26U) -#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) -#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) -#define USDHC_INT_STATUS_DMAE_SHIFT (28U) -#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) -/*! @} */ - -/*! @name INT_STATUS_EN - Interrupt Status Enable */ -/*! @{ */ -#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) -#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) -#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) -#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) -#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) -#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) -#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) -#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) -#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) -#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) -#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) -#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) -#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) -#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) -#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) -#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) -#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) -#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) -#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) -#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) -#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) -#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) -#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) -#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) -#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) -#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) -#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) -#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) -#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) -#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) -#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) -#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) -#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) -#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) -#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) -#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) -#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) -#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) -#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) -#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) -#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) -#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) -#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) -#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) -#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) -#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) -#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) -#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) -#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) -#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) -#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) -#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) -#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) -#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) -#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) -#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) -#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) -#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) -#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) -#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) -#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) -#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) -#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) -/*! @} */ - -/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ -/*! @{ */ -#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) -#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) -#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) -#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) -#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) -#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) -#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) -#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) -#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) -#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) -#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) -#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) -#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) -#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) -#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) -#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) -#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) -#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) -#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) -#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) -#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) -#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) -#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) -#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) -#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) -#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) -#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) -#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) -#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) -#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) -#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) -#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) -#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) -#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) -#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) -#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) -#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) -#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) -#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) -#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) -#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) -#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) -#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) -#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) -#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) -#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) -#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) -#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) -#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) -/*! @} */ - -/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ -/*! @{ */ -#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) -#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) -#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) -#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) -#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) -#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) -#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) -#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) -#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) -/*! @} */ - -/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ -/*! @{ */ -#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) -#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) -#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) -#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) -#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) -#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) -#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) -#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) -#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) -#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) -#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) -#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) -#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) -#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) -#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) -#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) -#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) -#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) -#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) -#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) -#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) -#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) -#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) -#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) -#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) -#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) -#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) -#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) -#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) -#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) -#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) -#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) -#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) -#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) -#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) -#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) -#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) -#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) -#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) -#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) -#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) -#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) -/*! @} */ - -/*! @name WTMK_LVL - Watermark Level */ -/*! @{ */ -#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) -#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) -#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) -#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) -#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) -#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) -#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) -#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) -#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) -#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) -#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) -#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) -/*! @} */ - -/*! @name MIX_CTRL - Mixer Control */ -/*! @{ */ -#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) -#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) -#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) -#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) -#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) -#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) -#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) -#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) -#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) -#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) -#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) -#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) -#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) -#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) -#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) -#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) -#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) -#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) -#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) -#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) -#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) -#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) -#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) -#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) -#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) -#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) -#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) -#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) -#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) -#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) -#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) -#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) -#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) -#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) -#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) -#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) -/*! @} */ - -/*! @name FORCE_EVENT - Force Event */ -/*! @{ */ -#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) -#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) -#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) -#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) -#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) -#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) -#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) -#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) -#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) -#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) -#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) -#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) -#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) -#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) -#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) -#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) -#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) -#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) -#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) -#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) -#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) -#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) -#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) -#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) -#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) -#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) -#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) -#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) -#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) -#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) -#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) -#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) -#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) -#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) -#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) -#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) -#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) -#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) -#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) -#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) -#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) -#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) -#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) -#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) -#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) -#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) -#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) -/*! @} */ - -/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ -/*! @{ */ -#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) -#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) -#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) -#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) -#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) -#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) -#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) -#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) -#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) -/*! @} */ - -/*! @name ADMA_SYS_ADDR - ADMA System Address */ -/*! @{ */ -#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) -#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) -#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) -/*! @} */ - -/*! @name DLL_CTRL - DLL (Delay Line) Control */ -/*! @{ */ -#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) -#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) -#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) -#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) -#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) -#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) -#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) -#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) -#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) -#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) -#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) -#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) -#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) -/*! @} */ - -/*! @name DLL_STATUS - DLL Status */ -/*! @{ */ -#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) -#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) -#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) -#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) -#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) -#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) -#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) -#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) -#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) -#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) -#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) -#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) -/*! @} */ - -/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ -/*! @{ */ -#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) -#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) -#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) -#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) -#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) -#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) -#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) -#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) -#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) -#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) -#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) -#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) -#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) -#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) -#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) -#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) -#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) -#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) -#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) -#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) -#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) -#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) -#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) -#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) -/*! @} */ - -/*! @name VEND_SPEC - Vendor Specific Register */ -/*! @{ */ -#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) -#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) -#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) -#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) -#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) -#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) -#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) -#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) -#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) -#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) -#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) -#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) -#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) -#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) -#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) -#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) -#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) -#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) -/*! @} */ - -/*! @name MMC_BOOT - MMC Boot Register */ -/*! @{ */ -#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) -#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) -#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) -#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) -#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) -#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) -#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) -#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) -#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) -#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) -#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) -#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) -#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) -#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) -#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) -#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) -#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) -#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) -#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) -#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) -#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) -/*! @} */ - -/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ -/*! @{ */ -#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) -#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) -#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) -#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) -#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) -#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) -#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) -#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) -#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) -#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) -#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) -#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) -#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) -#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) -#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) -#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U) -#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U) -#define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK) -#define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U) -#define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U) -#define USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK) -/*! @} */ - -/*! @name TUNING_CTRL - Tuning Control Register */ -/*! @{ */ -#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) -#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) -#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) -#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) -#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) -#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) -#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) -#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) -#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) -#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) -#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) -#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) -#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) -#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) -#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USDHC_Register_Masks */ - - -/* USDHC - Peripheral instance base addresses */ -/** Peripheral USDHC1 base address */ -#define USDHC1_BASE (0x402C0000u) -/** Peripheral USDHC1 base pointer */ -#define USDHC1 ((USDHC_Type *)USDHC1_BASE) -/** Peripheral USDHC2 base address */ -#define USDHC2_BASE (0x402C4000u) -/** Peripheral USDHC2 base pointer */ -#define USDHC2 ((USDHC_Type *)USDHC2_BASE) -/** Array initializer of USDHC peripheral base addresses */ -#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE } -/** Array initializer of USDHC peripheral base pointers */ -#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 } -/** Interrupt vectors for the USDHC peripheral type */ -#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn } - -/*! - * @} - */ /* end of group USDHC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WDOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer - * @{ - */ - -/** WDOG - Register Layout Typedef */ -typedef struct { - __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ - __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ - __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ - __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ - __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ -} WDOG_Type; - -/* ---------------------------------------------------------------------------- - -- WDOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WDOG_Register_Masks WDOG Register Masks - * @{ - */ - -/*! @name WCR - Watchdog Control Register */ -/*! @{ */ -#define WDOG_WCR_WDZST_MASK (0x1U) -#define WDOG_WCR_WDZST_SHIFT (0U) -#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) -#define WDOG_WCR_WDBG_MASK (0x2U) -#define WDOG_WCR_WDBG_SHIFT (1U) -#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) -#define WDOG_WCR_WDE_MASK (0x4U) -#define WDOG_WCR_WDE_SHIFT (2U) -#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) -#define WDOG_WCR_WDT_MASK (0x8U) -#define WDOG_WCR_WDT_SHIFT (3U) -#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) -#define WDOG_WCR_SRS_MASK (0x10U) -#define WDOG_WCR_SRS_SHIFT (4U) -#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) -#define WDOG_WCR_WDA_MASK (0x20U) -#define WDOG_WCR_WDA_SHIFT (5U) -#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) -#define WDOG_WCR_SRE_MASK (0x40U) -#define WDOG_WCR_SRE_SHIFT (6U) -#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) -#define WDOG_WCR_WDW_MASK (0x80U) -#define WDOG_WCR_WDW_SHIFT (7U) -#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) -#define WDOG_WCR_WT_MASK (0xFF00U) -#define WDOG_WCR_WT_SHIFT (8U) -#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) -/*! @} */ - -/*! @name WSR - Watchdog Service Register */ -/*! @{ */ -#define WDOG_WSR_WSR_MASK (0xFFFFU) -#define WDOG_WSR_WSR_SHIFT (0U) -#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) -/*! @} */ - -/*! @name WRSR - Watchdog Reset Status Register */ -/*! @{ */ -#define WDOG_WRSR_SFTW_MASK (0x1U) -#define WDOG_WRSR_SFTW_SHIFT (0U) -#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) -#define WDOG_WRSR_TOUT_MASK (0x2U) -#define WDOG_WRSR_TOUT_SHIFT (1U) -#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) -#define WDOG_WRSR_POR_MASK (0x10U) -#define WDOG_WRSR_POR_SHIFT (4U) -#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) -/*! @} */ - -/*! @name WICR - Watchdog Interrupt Control Register */ -/*! @{ */ -#define WDOG_WICR_WICT_MASK (0xFFU) -#define WDOG_WICR_WICT_SHIFT (0U) -#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) -#define WDOG_WICR_WTIS_MASK (0x4000U) -#define WDOG_WICR_WTIS_SHIFT (14U) -#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) -#define WDOG_WICR_WIE_MASK (0x8000U) -#define WDOG_WICR_WIE_SHIFT (15U) -#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) -/*! @} */ - -/*! @name WMCR - Watchdog Miscellaneous Control Register */ -/*! @{ */ -#define WDOG_WMCR_PDE_MASK (0x1U) -#define WDOG_WMCR_PDE_SHIFT (0U) -#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WDOG_Register_Masks */ - - -/* WDOG - Peripheral instance base addresses */ -/** Peripheral WDOG1 base address */ -#define WDOG1_BASE (0x400B8000u) -/** Peripheral WDOG1 base pointer */ -#define WDOG1 ((WDOG_Type *)WDOG1_BASE) -/** Peripheral WDOG2 base address */ -#define WDOG2_BASE (0x400D0000u) -/** Peripheral WDOG2 base pointer */ -#define WDOG2 ((WDOG_Type *)WDOG2_BASE) -/** Array initializer of WDOG peripheral base addresses */ -#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE } -/** Array initializer of WDOG peripheral base pointers */ -#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 } -/** Interrupt vectors for the WDOG peripheral type */ -#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn } - -/*! - * @} - */ /* end of group WDOG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XBARA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer - * @{ - */ - -/** XBARA - Register Layout Typedef */ -typedef struct { - __IO uint16_t SEL0; /**< Crossbar A Select Register 0, offset: 0x0 */ - __IO uint16_t SEL1; /**< Crossbar A Select Register 1, offset: 0x2 */ - __IO uint16_t SEL2; /**< Crossbar A Select Register 2, offset: 0x4 */ - __IO uint16_t SEL3; /**< Crossbar A Select Register 3, offset: 0x6 */ - __IO uint16_t SEL4; /**< Crossbar A Select Register 4, offset: 0x8 */ - __IO uint16_t SEL5; /**< Crossbar A Select Register 5, offset: 0xA */ - __IO uint16_t SEL6; /**< Crossbar A Select Register 6, offset: 0xC */ - __IO uint16_t SEL7; /**< Crossbar A Select Register 7, offset: 0xE */ - __IO uint16_t SEL8; /**< Crossbar A Select Register 8, offset: 0x10 */ - __IO uint16_t SEL9; /**< Crossbar A Select Register 9, offset: 0x12 */ - __IO uint16_t SEL10; /**< Crossbar A Select Register 10, offset: 0x14 */ - __IO uint16_t SEL11; /**< Crossbar A Select Register 11, offset: 0x16 */ - __IO uint16_t SEL12; /**< Crossbar A Select Register 12, offset: 0x18 */ - __IO uint16_t SEL13; /**< Crossbar A Select Register 13, offset: 0x1A */ - __IO uint16_t SEL14; /**< Crossbar A Select Register 14, offset: 0x1C */ - __IO uint16_t SEL15; /**< Crossbar A Select Register 15, offset: 0x1E */ - __IO uint16_t SEL16; /**< Crossbar A Select Register 16, offset: 0x20 */ - __IO uint16_t SEL17; /**< Crossbar A Select Register 17, offset: 0x22 */ - __IO uint16_t SEL18; /**< Crossbar A Select Register 18, offset: 0x24 */ - __IO uint16_t SEL19; /**< Crossbar A Select Register 19, offset: 0x26 */ - __IO uint16_t SEL20; /**< Crossbar A Select Register 20, offset: 0x28 */ - __IO uint16_t SEL21; /**< Crossbar A Select Register 21, offset: 0x2A */ - __IO uint16_t SEL22; /**< Crossbar A Select Register 22, offset: 0x2C */ - __IO uint16_t SEL23; /**< Crossbar A Select Register 23, offset: 0x2E */ - __IO uint16_t SEL24; /**< Crossbar A Select Register 24, offset: 0x30 */ - __IO uint16_t SEL25; /**< Crossbar A Select Register 25, offset: 0x32 */ - __IO uint16_t SEL26; /**< Crossbar A Select Register 26, offset: 0x34 */ - __IO uint16_t SEL27; /**< Crossbar A Select Register 27, offset: 0x36 */ - __IO uint16_t SEL28; /**< Crossbar A Select Register 28, offset: 0x38 */ - __IO uint16_t SEL29; /**< Crossbar A Select Register 29, offset: 0x3A */ - __IO uint16_t SEL30; /**< Crossbar A Select Register 30, offset: 0x3C */ - __IO uint16_t SEL31; /**< Crossbar A Select Register 31, offset: 0x3E */ - __IO uint16_t SEL32; /**< Crossbar A Select Register 32, offset: 0x40 */ - __IO uint16_t SEL33; /**< Crossbar A Select Register 33, offset: 0x42 */ - __IO uint16_t SEL34; /**< Crossbar A Select Register 34, offset: 0x44 */ - __IO uint16_t SEL35; /**< Crossbar A Select Register 35, offset: 0x46 */ - __IO uint16_t SEL36; /**< Crossbar A Select Register 36, offset: 0x48 */ - __IO uint16_t SEL37; /**< Crossbar A Select Register 37, offset: 0x4A */ - __IO uint16_t SEL38; /**< Crossbar A Select Register 38, offset: 0x4C */ - __IO uint16_t SEL39; /**< Crossbar A Select Register 39, offset: 0x4E */ - __IO uint16_t SEL40; /**< Crossbar A Select Register 40, offset: 0x50 */ - __IO uint16_t SEL41; /**< Crossbar A Select Register 41, offset: 0x52 */ - __IO uint16_t SEL42; /**< Crossbar A Select Register 42, offset: 0x54 */ - __IO uint16_t SEL43; /**< Crossbar A Select Register 43, offset: 0x56 */ - __IO uint16_t SEL44; /**< Crossbar A Select Register 44, offset: 0x58 */ - __IO uint16_t SEL45; /**< Crossbar A Select Register 45, offset: 0x5A */ - __IO uint16_t SEL46; /**< Crossbar A Select Register 46, offset: 0x5C */ - __IO uint16_t SEL47; /**< Crossbar A Select Register 47, offset: 0x5E */ - __IO uint16_t SEL48; /**< Crossbar A Select Register 48, offset: 0x60 */ - __IO uint16_t SEL49; /**< Crossbar A Select Register 49, offset: 0x62 */ - __IO uint16_t SEL50; /**< Crossbar A Select Register 50, offset: 0x64 */ - __IO uint16_t SEL51; /**< Crossbar A Select Register 51, offset: 0x66 */ - __IO uint16_t SEL52; /**< Crossbar A Select Register 52, offset: 0x68 */ - __IO uint16_t SEL53; /**< Crossbar A Select Register 53, offset: 0x6A */ - __IO uint16_t SEL54; /**< Crossbar A Select Register 54, offset: 0x6C */ - __IO uint16_t SEL55; /**< Crossbar A Select Register 55, offset: 0x6E */ - __IO uint16_t SEL56; /**< Crossbar A Select Register 56, offset: 0x70 */ - __IO uint16_t SEL57; /**< Crossbar A Select Register 57, offset: 0x72 */ - __IO uint16_t SEL58; /**< Crossbar A Select Register 58, offset: 0x74 */ - __IO uint16_t SEL59; /**< Crossbar A Select Register 59, offset: 0x76 */ - __IO uint16_t SEL60; /**< Crossbar A Select Register 60, offset: 0x78 */ - __IO uint16_t SEL61; /**< Crossbar A Select Register 61, offset: 0x7A */ - __IO uint16_t SEL62; /**< Crossbar A Select Register 62, offset: 0x7C */ - __IO uint16_t SEL63; /**< Crossbar A Select Register 63, offset: 0x7E */ - __IO uint16_t SEL64; /**< Crossbar A Select Register 64, offset: 0x80 */ - __IO uint16_t SEL65; /**< Crossbar A Select Register 65, offset: 0x82 */ - __IO uint16_t CTRL0; /**< Crossbar A Control Register 0, offset: 0x84 */ - __IO uint16_t CTRL1; /**< Crossbar A Control Register 1, offset: 0x86 */ -} XBARA_Type; - -/* ---------------------------------------------------------------------------- - -- XBARA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XBARA_Register_Masks XBARA Register Masks - * @{ - */ - -/*! @name SEL0 - Crossbar A Select Register 0 */ -/*! @{ */ -#define XBARA_SEL0_SEL0_MASK (0x7FU) -#define XBARA_SEL0_SEL0_SHIFT (0U) -#define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK) -#define XBARA_SEL0_SEL1_MASK (0x7F00U) -#define XBARA_SEL0_SEL1_SHIFT (8U) -#define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK) -/*! @} */ - -/*! @name SEL1 - Crossbar A Select Register 1 */ -/*! @{ */ -#define XBARA_SEL1_SEL2_MASK (0x7FU) -#define XBARA_SEL1_SEL2_SHIFT (0U) -#define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK) -#define XBARA_SEL1_SEL3_MASK (0x7F00U) -#define XBARA_SEL1_SEL3_SHIFT (8U) -#define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK) -/*! @} */ - -/*! @name SEL2 - Crossbar A Select Register 2 */ -/*! @{ */ -#define XBARA_SEL2_SEL4_MASK (0x7FU) -#define XBARA_SEL2_SEL4_SHIFT (0U) -#define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK) -#define XBARA_SEL2_SEL5_MASK (0x7F00U) -#define XBARA_SEL2_SEL5_SHIFT (8U) -#define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK) -/*! @} */ - -/*! @name SEL3 - Crossbar A Select Register 3 */ -/*! @{ */ -#define XBARA_SEL3_SEL6_MASK (0x7FU) -#define XBARA_SEL3_SEL6_SHIFT (0U) -#define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK) -#define XBARA_SEL3_SEL7_MASK (0x7F00U) -#define XBARA_SEL3_SEL7_SHIFT (8U) -#define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK) -/*! @} */ - -/*! @name SEL4 - Crossbar A Select Register 4 */ -/*! @{ */ -#define XBARA_SEL4_SEL8_MASK (0x7FU) -#define XBARA_SEL4_SEL8_SHIFT (0U) -#define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK) -#define XBARA_SEL4_SEL9_MASK (0x7F00U) -#define XBARA_SEL4_SEL9_SHIFT (8U) -#define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK) -/*! @} */ - -/*! @name SEL5 - Crossbar A Select Register 5 */ -/*! @{ */ -#define XBARA_SEL5_SEL10_MASK (0x7FU) -#define XBARA_SEL5_SEL10_SHIFT (0U) -#define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK) -#define XBARA_SEL5_SEL11_MASK (0x7F00U) -#define XBARA_SEL5_SEL11_SHIFT (8U) -#define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK) -/*! @} */ - -/*! @name SEL6 - Crossbar A Select Register 6 */ -/*! @{ */ -#define XBARA_SEL6_SEL12_MASK (0x7FU) -#define XBARA_SEL6_SEL12_SHIFT (0U) -#define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK) -#define XBARA_SEL6_SEL13_MASK (0x7F00U) -#define XBARA_SEL6_SEL13_SHIFT (8U) -#define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK) -/*! @} */ - -/*! @name SEL7 - Crossbar A Select Register 7 */ -/*! @{ */ -#define XBARA_SEL7_SEL14_MASK (0x7FU) -#define XBARA_SEL7_SEL14_SHIFT (0U) -#define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK) -#define XBARA_SEL7_SEL15_MASK (0x7F00U) -#define XBARA_SEL7_SEL15_SHIFT (8U) -#define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK) -/*! @} */ - -/*! @name SEL8 - Crossbar A Select Register 8 */ -/*! @{ */ -#define XBARA_SEL8_SEL16_MASK (0x7FU) -#define XBARA_SEL8_SEL16_SHIFT (0U) -#define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK) -#define XBARA_SEL8_SEL17_MASK (0x7F00U) -#define XBARA_SEL8_SEL17_SHIFT (8U) -#define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK) -/*! @} */ - -/*! @name SEL9 - Crossbar A Select Register 9 */ -/*! @{ */ -#define XBARA_SEL9_SEL18_MASK (0x7FU) -#define XBARA_SEL9_SEL18_SHIFT (0U) -#define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK) -#define XBARA_SEL9_SEL19_MASK (0x7F00U) -#define XBARA_SEL9_SEL19_SHIFT (8U) -#define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK) -/*! @} */ - -/*! @name SEL10 - Crossbar A Select Register 10 */ -/*! @{ */ -#define XBARA_SEL10_SEL20_MASK (0x7FU) -#define XBARA_SEL10_SEL20_SHIFT (0U) -#define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK) -#define XBARA_SEL10_SEL21_MASK (0x7F00U) -#define XBARA_SEL10_SEL21_SHIFT (8U) -#define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK) -/*! @} */ - -/*! @name SEL11 - Crossbar A Select Register 11 */ -/*! @{ */ -#define XBARA_SEL11_SEL22_MASK (0x7FU) -#define XBARA_SEL11_SEL22_SHIFT (0U) -#define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK) -#define XBARA_SEL11_SEL23_MASK (0x7F00U) -#define XBARA_SEL11_SEL23_SHIFT (8U) -#define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK) -/*! @} */ - -/*! @name SEL12 - Crossbar A Select Register 12 */ -/*! @{ */ -#define XBARA_SEL12_SEL24_MASK (0x7FU) -#define XBARA_SEL12_SEL24_SHIFT (0U) -#define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK) -#define XBARA_SEL12_SEL25_MASK (0x7F00U) -#define XBARA_SEL12_SEL25_SHIFT (8U) -#define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK) -/*! @} */ - -/*! @name SEL13 - Crossbar A Select Register 13 */ -/*! @{ */ -#define XBARA_SEL13_SEL26_MASK (0x7FU) -#define XBARA_SEL13_SEL26_SHIFT (0U) -#define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK) -#define XBARA_SEL13_SEL27_MASK (0x7F00U) -#define XBARA_SEL13_SEL27_SHIFT (8U) -#define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK) -/*! @} */ - -/*! @name SEL14 - Crossbar A Select Register 14 */ -/*! @{ */ -#define XBARA_SEL14_SEL28_MASK (0x7FU) -#define XBARA_SEL14_SEL28_SHIFT (0U) -#define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK) -#define XBARA_SEL14_SEL29_MASK (0x7F00U) -#define XBARA_SEL14_SEL29_SHIFT (8U) -#define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK) -/*! @} */ - -/*! @name SEL15 - Crossbar A Select Register 15 */ -/*! @{ */ -#define XBARA_SEL15_SEL30_MASK (0x7FU) -#define XBARA_SEL15_SEL30_SHIFT (0U) -#define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK) -#define XBARA_SEL15_SEL31_MASK (0x7F00U) -#define XBARA_SEL15_SEL31_SHIFT (8U) -#define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK) -/*! @} */ - -/*! @name SEL16 - Crossbar A Select Register 16 */ -/*! @{ */ -#define XBARA_SEL16_SEL32_MASK (0x7FU) -#define XBARA_SEL16_SEL32_SHIFT (0U) -#define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK) -#define XBARA_SEL16_SEL33_MASK (0x7F00U) -#define XBARA_SEL16_SEL33_SHIFT (8U) -#define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK) -/*! @} */ - -/*! @name SEL17 - Crossbar A Select Register 17 */ -/*! @{ */ -#define XBARA_SEL17_SEL34_MASK (0x7FU) -#define XBARA_SEL17_SEL34_SHIFT (0U) -#define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK) -#define XBARA_SEL17_SEL35_MASK (0x7F00U) -#define XBARA_SEL17_SEL35_SHIFT (8U) -#define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK) -/*! @} */ - -/*! @name SEL18 - Crossbar A Select Register 18 */ -/*! @{ */ -#define XBARA_SEL18_SEL36_MASK (0x7FU) -#define XBARA_SEL18_SEL36_SHIFT (0U) -#define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK) -#define XBARA_SEL18_SEL37_MASK (0x7F00U) -#define XBARA_SEL18_SEL37_SHIFT (8U) -#define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK) -/*! @} */ - -/*! @name SEL19 - Crossbar A Select Register 19 */ -/*! @{ */ -#define XBARA_SEL19_SEL38_MASK (0x7FU) -#define XBARA_SEL19_SEL38_SHIFT (0U) -#define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK) -#define XBARA_SEL19_SEL39_MASK (0x7F00U) -#define XBARA_SEL19_SEL39_SHIFT (8U) -#define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK) -/*! @} */ - -/*! @name SEL20 - Crossbar A Select Register 20 */ -/*! @{ */ -#define XBARA_SEL20_SEL40_MASK (0x7FU) -#define XBARA_SEL20_SEL40_SHIFT (0U) -#define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK) -#define XBARA_SEL20_SEL41_MASK (0x7F00U) -#define XBARA_SEL20_SEL41_SHIFT (8U) -#define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK) -/*! @} */ - -/*! @name SEL21 - Crossbar A Select Register 21 */ -/*! @{ */ -#define XBARA_SEL21_SEL42_MASK (0x7FU) -#define XBARA_SEL21_SEL42_SHIFT (0U) -#define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK) -#define XBARA_SEL21_SEL43_MASK (0x7F00U) -#define XBARA_SEL21_SEL43_SHIFT (8U) -#define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK) -/*! @} */ - -/*! @name SEL22 - Crossbar A Select Register 22 */ -/*! @{ */ -#define XBARA_SEL22_SEL44_MASK (0x7FU) -#define XBARA_SEL22_SEL44_SHIFT (0U) -#define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK) -#define XBARA_SEL22_SEL45_MASK (0x7F00U) -#define XBARA_SEL22_SEL45_SHIFT (8U) -#define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK) -/*! @} */ - -/*! @name SEL23 - Crossbar A Select Register 23 */ -/*! @{ */ -#define XBARA_SEL23_SEL46_MASK (0x7FU) -#define XBARA_SEL23_SEL46_SHIFT (0U) -#define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK) -#define XBARA_SEL23_SEL47_MASK (0x7F00U) -#define XBARA_SEL23_SEL47_SHIFT (8U) -#define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK) -/*! @} */ - -/*! @name SEL24 - Crossbar A Select Register 24 */ -/*! @{ */ -#define XBARA_SEL24_SEL48_MASK (0x7FU) -#define XBARA_SEL24_SEL48_SHIFT (0U) -#define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK) -#define XBARA_SEL24_SEL49_MASK (0x7F00U) -#define XBARA_SEL24_SEL49_SHIFT (8U) -#define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK) -/*! @} */ - -/*! @name SEL25 - Crossbar A Select Register 25 */ -/*! @{ */ -#define XBARA_SEL25_SEL50_MASK (0x7FU) -#define XBARA_SEL25_SEL50_SHIFT (0U) -#define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK) -#define XBARA_SEL25_SEL51_MASK (0x7F00U) -#define XBARA_SEL25_SEL51_SHIFT (8U) -#define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK) -/*! @} */ - -/*! @name SEL26 - Crossbar A Select Register 26 */ -/*! @{ */ -#define XBARA_SEL26_SEL52_MASK (0x7FU) -#define XBARA_SEL26_SEL52_SHIFT (0U) -#define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK) -#define XBARA_SEL26_SEL53_MASK (0x7F00U) -#define XBARA_SEL26_SEL53_SHIFT (8U) -#define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK) -/*! @} */ - -/*! @name SEL27 - Crossbar A Select Register 27 */ -/*! @{ */ -#define XBARA_SEL27_SEL54_MASK (0x7FU) -#define XBARA_SEL27_SEL54_SHIFT (0U) -#define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK) -#define XBARA_SEL27_SEL55_MASK (0x7F00U) -#define XBARA_SEL27_SEL55_SHIFT (8U) -#define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK) -/*! @} */ - -/*! @name SEL28 - Crossbar A Select Register 28 */ -/*! @{ */ -#define XBARA_SEL28_SEL56_MASK (0x7FU) -#define XBARA_SEL28_SEL56_SHIFT (0U) -#define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK) -#define XBARA_SEL28_SEL57_MASK (0x7F00U) -#define XBARA_SEL28_SEL57_SHIFT (8U) -#define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK) -/*! @} */ - -/*! @name SEL29 - Crossbar A Select Register 29 */ -/*! @{ */ -#define XBARA_SEL29_SEL58_MASK (0x7FU) -#define XBARA_SEL29_SEL58_SHIFT (0U) -#define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK) -#define XBARA_SEL29_SEL59_MASK (0x7F00U) -#define XBARA_SEL29_SEL59_SHIFT (8U) -#define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK) -/*! @} */ - -/*! @name SEL30 - Crossbar A Select Register 30 */ -/*! @{ */ -#define XBARA_SEL30_SEL60_MASK (0x7FU) -#define XBARA_SEL30_SEL60_SHIFT (0U) -#define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK) -#define XBARA_SEL30_SEL61_MASK (0x7F00U) -#define XBARA_SEL30_SEL61_SHIFT (8U) -#define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK) -/*! @} */ - -/*! @name SEL31 - Crossbar A Select Register 31 */ -/*! @{ */ -#define XBARA_SEL31_SEL62_MASK (0x7FU) -#define XBARA_SEL31_SEL62_SHIFT (0U) -#define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK) -#define XBARA_SEL31_SEL63_MASK (0x7F00U) -#define XBARA_SEL31_SEL63_SHIFT (8U) -#define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK) -/*! @} */ - -/*! @name SEL32 - Crossbar A Select Register 32 */ -/*! @{ */ -#define XBARA_SEL32_SEL64_MASK (0x7FU) -#define XBARA_SEL32_SEL64_SHIFT (0U) -#define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK) -#define XBARA_SEL32_SEL65_MASK (0x7F00U) -#define XBARA_SEL32_SEL65_SHIFT (8U) -#define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK) -/*! @} */ - -/*! @name SEL33 - Crossbar A Select Register 33 */ -/*! @{ */ -#define XBARA_SEL33_SEL66_MASK (0x7FU) -#define XBARA_SEL33_SEL66_SHIFT (0U) -#define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK) -#define XBARA_SEL33_SEL67_MASK (0x7F00U) -#define XBARA_SEL33_SEL67_SHIFT (8U) -#define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK) -/*! @} */ - -/*! @name SEL34 - Crossbar A Select Register 34 */ -/*! @{ */ -#define XBARA_SEL34_SEL68_MASK (0x7FU) -#define XBARA_SEL34_SEL68_SHIFT (0U) -#define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK) -#define XBARA_SEL34_SEL69_MASK (0x7F00U) -#define XBARA_SEL34_SEL69_SHIFT (8U) -#define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK) -/*! @} */ - -/*! @name SEL35 - Crossbar A Select Register 35 */ -/*! @{ */ -#define XBARA_SEL35_SEL70_MASK (0x7FU) -#define XBARA_SEL35_SEL70_SHIFT (0U) -#define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK) -#define XBARA_SEL35_SEL71_MASK (0x7F00U) -#define XBARA_SEL35_SEL71_SHIFT (8U) -#define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK) -/*! @} */ - -/*! @name SEL36 - Crossbar A Select Register 36 */ -/*! @{ */ -#define XBARA_SEL36_SEL72_MASK (0x7FU) -#define XBARA_SEL36_SEL72_SHIFT (0U) -#define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK) -#define XBARA_SEL36_SEL73_MASK (0x7F00U) -#define XBARA_SEL36_SEL73_SHIFT (8U) -#define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK) -/*! @} */ - -/*! @name SEL37 - Crossbar A Select Register 37 */ -/*! @{ */ -#define XBARA_SEL37_SEL74_MASK (0x7FU) -#define XBARA_SEL37_SEL74_SHIFT (0U) -#define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK) -#define XBARA_SEL37_SEL75_MASK (0x7F00U) -#define XBARA_SEL37_SEL75_SHIFT (8U) -#define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK) -/*! @} */ - -/*! @name SEL38 - Crossbar A Select Register 38 */ -/*! @{ */ -#define XBARA_SEL38_SEL76_MASK (0x7FU) -#define XBARA_SEL38_SEL76_SHIFT (0U) -#define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK) -#define XBARA_SEL38_SEL77_MASK (0x7F00U) -#define XBARA_SEL38_SEL77_SHIFT (8U) -#define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK) -/*! @} */ - -/*! @name SEL39 - Crossbar A Select Register 39 */ -/*! @{ */ -#define XBARA_SEL39_SEL78_MASK (0x7FU) -#define XBARA_SEL39_SEL78_SHIFT (0U) -#define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK) -#define XBARA_SEL39_SEL79_MASK (0x7F00U) -#define XBARA_SEL39_SEL79_SHIFT (8U) -#define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK) -/*! @} */ - -/*! @name SEL40 - Crossbar A Select Register 40 */ -/*! @{ */ -#define XBARA_SEL40_SEL80_MASK (0x7FU) -#define XBARA_SEL40_SEL80_SHIFT (0U) -#define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK) -#define XBARA_SEL40_SEL81_MASK (0x7F00U) -#define XBARA_SEL40_SEL81_SHIFT (8U) -#define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK) -/*! @} */ - -/*! @name SEL41 - Crossbar A Select Register 41 */ -/*! @{ */ -#define XBARA_SEL41_SEL82_MASK (0x7FU) -#define XBARA_SEL41_SEL82_SHIFT (0U) -#define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK) -#define XBARA_SEL41_SEL83_MASK (0x7F00U) -#define XBARA_SEL41_SEL83_SHIFT (8U) -#define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK) -/*! @} */ - -/*! @name SEL42 - Crossbar A Select Register 42 */ -/*! @{ */ -#define XBARA_SEL42_SEL84_MASK (0x7FU) -#define XBARA_SEL42_SEL84_SHIFT (0U) -#define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK) -#define XBARA_SEL42_SEL85_MASK (0x7F00U) -#define XBARA_SEL42_SEL85_SHIFT (8U) -#define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK) -/*! @} */ - -/*! @name SEL43 - Crossbar A Select Register 43 */ -/*! @{ */ -#define XBARA_SEL43_SEL86_MASK (0x7FU) -#define XBARA_SEL43_SEL86_SHIFT (0U) -#define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK) -#define XBARA_SEL43_SEL87_MASK (0x7F00U) -#define XBARA_SEL43_SEL87_SHIFT (8U) -#define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK) -/*! @} */ - -/*! @name SEL44 - Crossbar A Select Register 44 */ -/*! @{ */ -#define XBARA_SEL44_SEL88_MASK (0x7FU) -#define XBARA_SEL44_SEL88_SHIFT (0U) -#define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK) -#define XBARA_SEL44_SEL89_MASK (0x7F00U) -#define XBARA_SEL44_SEL89_SHIFT (8U) -#define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK) -/*! @} */ - -/*! @name SEL45 - Crossbar A Select Register 45 */ -/*! @{ */ -#define XBARA_SEL45_SEL90_MASK (0x7FU) -#define XBARA_SEL45_SEL90_SHIFT (0U) -#define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK) -#define XBARA_SEL45_SEL91_MASK (0x7F00U) -#define XBARA_SEL45_SEL91_SHIFT (8U) -#define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK) -/*! @} */ - -/*! @name SEL46 - Crossbar A Select Register 46 */ -/*! @{ */ -#define XBARA_SEL46_SEL92_MASK (0x7FU) -#define XBARA_SEL46_SEL92_SHIFT (0U) -#define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK) -#define XBARA_SEL46_SEL93_MASK (0x7F00U) -#define XBARA_SEL46_SEL93_SHIFT (8U) -#define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK) -/*! @} */ - -/*! @name SEL47 - Crossbar A Select Register 47 */ -/*! @{ */ -#define XBARA_SEL47_SEL94_MASK (0x7FU) -#define XBARA_SEL47_SEL94_SHIFT (0U) -#define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK) -#define XBARA_SEL47_SEL95_MASK (0x7F00U) -#define XBARA_SEL47_SEL95_SHIFT (8U) -#define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK) -/*! @} */ - -/*! @name SEL48 - Crossbar A Select Register 48 */ -/*! @{ */ -#define XBARA_SEL48_SEL96_MASK (0x7FU) -#define XBARA_SEL48_SEL96_SHIFT (0U) -#define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK) -#define XBARA_SEL48_SEL97_MASK (0x7F00U) -#define XBARA_SEL48_SEL97_SHIFT (8U) -#define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK) -/*! @} */ - -/*! @name SEL49 - Crossbar A Select Register 49 */ -/*! @{ */ -#define XBARA_SEL49_SEL98_MASK (0x7FU) -#define XBARA_SEL49_SEL98_SHIFT (0U) -#define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK) -#define XBARA_SEL49_SEL99_MASK (0x7F00U) -#define XBARA_SEL49_SEL99_SHIFT (8U) -#define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK) -/*! @} */ - -/*! @name SEL50 - Crossbar A Select Register 50 */ -/*! @{ */ -#define XBARA_SEL50_SEL100_MASK (0x7FU) -#define XBARA_SEL50_SEL100_SHIFT (0U) -#define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK) -#define XBARA_SEL50_SEL101_MASK (0x7F00U) -#define XBARA_SEL50_SEL101_SHIFT (8U) -#define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK) -/*! @} */ - -/*! @name SEL51 - Crossbar A Select Register 51 */ -/*! @{ */ -#define XBARA_SEL51_SEL102_MASK (0x7FU) -#define XBARA_SEL51_SEL102_SHIFT (0U) -#define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK) -#define XBARA_SEL51_SEL103_MASK (0x7F00U) -#define XBARA_SEL51_SEL103_SHIFT (8U) -#define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK) -/*! @} */ - -/*! @name SEL52 - Crossbar A Select Register 52 */ -/*! @{ */ -#define XBARA_SEL52_SEL104_MASK (0x7FU) -#define XBARA_SEL52_SEL104_SHIFT (0U) -#define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK) -#define XBARA_SEL52_SEL105_MASK (0x7F00U) -#define XBARA_SEL52_SEL105_SHIFT (8U) -#define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK) -/*! @} */ - -/*! @name SEL53 - Crossbar A Select Register 53 */ -/*! @{ */ -#define XBARA_SEL53_SEL106_MASK (0x7FU) -#define XBARA_SEL53_SEL106_SHIFT (0U) -#define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK) -#define XBARA_SEL53_SEL107_MASK (0x7F00U) -#define XBARA_SEL53_SEL107_SHIFT (8U) -#define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK) -/*! @} */ - -/*! @name SEL54 - Crossbar A Select Register 54 */ -/*! @{ */ -#define XBARA_SEL54_SEL108_MASK (0x7FU) -#define XBARA_SEL54_SEL108_SHIFT (0U) -#define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK) -#define XBARA_SEL54_SEL109_MASK (0x7F00U) -#define XBARA_SEL54_SEL109_SHIFT (8U) -#define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK) -/*! @} */ - -/*! @name SEL55 - Crossbar A Select Register 55 */ -/*! @{ */ -#define XBARA_SEL55_SEL110_MASK (0x7FU) -#define XBARA_SEL55_SEL110_SHIFT (0U) -#define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK) -#define XBARA_SEL55_SEL111_MASK (0x7F00U) -#define XBARA_SEL55_SEL111_SHIFT (8U) -#define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK) -/*! @} */ - -/*! @name SEL56 - Crossbar A Select Register 56 */ -/*! @{ */ -#define XBARA_SEL56_SEL112_MASK (0x7FU) -#define XBARA_SEL56_SEL112_SHIFT (0U) -#define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK) -#define XBARA_SEL56_SEL113_MASK (0x7F00U) -#define XBARA_SEL56_SEL113_SHIFT (8U) -#define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK) -/*! @} */ - -/*! @name SEL57 - Crossbar A Select Register 57 */ -/*! @{ */ -#define XBARA_SEL57_SEL114_MASK (0x7FU) -#define XBARA_SEL57_SEL114_SHIFT (0U) -#define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK) -#define XBARA_SEL57_SEL115_MASK (0x7F00U) -#define XBARA_SEL57_SEL115_SHIFT (8U) -#define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK) -/*! @} */ - -/*! @name SEL58 - Crossbar A Select Register 58 */ -/*! @{ */ -#define XBARA_SEL58_SEL116_MASK (0x7FU) -#define XBARA_SEL58_SEL116_SHIFT (0U) -#define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK) -#define XBARA_SEL58_SEL117_MASK (0x7F00U) -#define XBARA_SEL58_SEL117_SHIFT (8U) -#define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK) -/*! @} */ - -/*! @name SEL59 - Crossbar A Select Register 59 */ -/*! @{ */ -#define XBARA_SEL59_SEL118_MASK (0x7FU) -#define XBARA_SEL59_SEL118_SHIFT (0U) -#define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK) -#define XBARA_SEL59_SEL119_MASK (0x7F00U) -#define XBARA_SEL59_SEL119_SHIFT (8U) -#define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK) -/*! @} */ - -/*! @name SEL60 - Crossbar A Select Register 60 */ -/*! @{ */ -#define XBARA_SEL60_SEL120_MASK (0x7FU) -#define XBARA_SEL60_SEL120_SHIFT (0U) -#define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK) -#define XBARA_SEL60_SEL121_MASK (0x7F00U) -#define XBARA_SEL60_SEL121_SHIFT (8U) -#define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK) -/*! @} */ - -/*! @name SEL61 - Crossbar A Select Register 61 */ -/*! @{ */ -#define XBARA_SEL61_SEL122_MASK (0x7FU) -#define XBARA_SEL61_SEL122_SHIFT (0U) -#define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK) -#define XBARA_SEL61_SEL123_MASK (0x7F00U) -#define XBARA_SEL61_SEL123_SHIFT (8U) -#define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK) -/*! @} */ - -/*! @name SEL62 - Crossbar A Select Register 62 */ -/*! @{ */ -#define XBARA_SEL62_SEL124_MASK (0x7FU) -#define XBARA_SEL62_SEL124_SHIFT (0U) -#define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK) -#define XBARA_SEL62_SEL125_MASK (0x7F00U) -#define XBARA_SEL62_SEL125_SHIFT (8U) -#define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK) -/*! @} */ - -/*! @name SEL63 - Crossbar A Select Register 63 */ -/*! @{ */ -#define XBARA_SEL63_SEL126_MASK (0x7FU) -#define XBARA_SEL63_SEL126_SHIFT (0U) -#define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK) -#define XBARA_SEL63_SEL127_MASK (0x7F00U) -#define XBARA_SEL63_SEL127_SHIFT (8U) -#define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK) -/*! @} */ - -/*! @name SEL64 - Crossbar A Select Register 64 */ -/*! @{ */ -#define XBARA_SEL64_SEL128_MASK (0x7FU) -#define XBARA_SEL64_SEL128_SHIFT (0U) -#define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK) -#define XBARA_SEL64_SEL129_MASK (0x7F00U) -#define XBARA_SEL64_SEL129_SHIFT (8U) -#define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK) -/*! @} */ - -/*! @name SEL65 - Crossbar A Select Register 65 */ -/*! @{ */ -#define XBARA_SEL65_SEL130_MASK (0x7FU) -#define XBARA_SEL65_SEL130_SHIFT (0U) -#define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK) -#define XBARA_SEL65_SEL131_MASK (0x7F00U) -#define XBARA_SEL65_SEL131_SHIFT (8U) -#define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK) -/*! @} */ - -/*! @name CTRL0 - Crossbar A Control Register 0 */ -/*! @{ */ -#define XBARA_CTRL0_DEN0_MASK (0x1U) -#define XBARA_CTRL0_DEN0_SHIFT (0U) -#define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK) -#define XBARA_CTRL0_IEN0_MASK (0x2U) -#define XBARA_CTRL0_IEN0_SHIFT (1U) -#define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK) -#define XBARA_CTRL0_EDGE0_MASK (0xCU) -#define XBARA_CTRL0_EDGE0_SHIFT (2U) -#define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK) -#define XBARA_CTRL0_STS0_MASK (0x10U) -#define XBARA_CTRL0_STS0_SHIFT (4U) -#define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK) -#define XBARA_CTRL0_DEN1_MASK (0x100U) -#define XBARA_CTRL0_DEN1_SHIFT (8U) -#define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK) -#define XBARA_CTRL0_IEN1_MASK (0x200U) -#define XBARA_CTRL0_IEN1_SHIFT (9U) -#define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK) -#define XBARA_CTRL0_EDGE1_MASK (0xC00U) -#define XBARA_CTRL0_EDGE1_SHIFT (10U) -#define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK) -#define XBARA_CTRL0_STS1_MASK (0x1000U) -#define XBARA_CTRL0_STS1_SHIFT (12U) -#define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK) -/*! @} */ - -/*! @name CTRL1 - Crossbar A Control Register 1 */ -/*! @{ */ -#define XBARA_CTRL1_DEN2_MASK (0x1U) -#define XBARA_CTRL1_DEN2_SHIFT (0U) -#define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK) -#define XBARA_CTRL1_IEN2_MASK (0x2U) -#define XBARA_CTRL1_IEN2_SHIFT (1U) -#define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK) -#define XBARA_CTRL1_EDGE2_MASK (0xCU) -#define XBARA_CTRL1_EDGE2_SHIFT (2U) -#define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK) -#define XBARA_CTRL1_STS2_MASK (0x10U) -#define XBARA_CTRL1_STS2_SHIFT (4U) -#define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK) -#define XBARA_CTRL1_DEN3_MASK (0x100U) -#define XBARA_CTRL1_DEN3_SHIFT (8U) -#define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK) -#define XBARA_CTRL1_IEN3_MASK (0x200U) -#define XBARA_CTRL1_IEN3_SHIFT (9U) -#define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK) -#define XBARA_CTRL1_EDGE3_MASK (0xC00U) -#define XBARA_CTRL1_EDGE3_SHIFT (10U) -#define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK) -#define XBARA_CTRL1_STS3_MASK (0x1000U) -#define XBARA_CTRL1_STS3_SHIFT (12U) -#define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group XBARA_Register_Masks */ - - -/* XBARA - Peripheral instance base addresses */ -/** Peripheral XBARA1 base address */ -#define XBARA1_BASE (0x403BC000u) -/** Peripheral XBARA1 base pointer */ -#define XBARA1 ((XBARA_Type *)XBARA1_BASE) -/** Array initializer of XBARA peripheral base addresses */ -#define XBARA_BASE_ADDRS { XBARA1_BASE } -/** Array initializer of XBARA peripheral base pointers */ -#define XBARA_BASE_PTRS { XBARA1 } - -/*! - * @} - */ /* end of group XBARA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XBARB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer - * @{ - */ - -/** XBARB - Register Layout Typedef */ -typedef struct { - __IO uint16_t SEL0; /**< Crossbar B Select Register 0, offset: 0x0 */ - __IO uint16_t SEL1; /**< Crossbar B Select Register 1, offset: 0x2 */ - __IO uint16_t SEL2; /**< Crossbar B Select Register 2, offset: 0x4 */ - __IO uint16_t SEL3; /**< Crossbar B Select Register 3, offset: 0x6 */ - __IO uint16_t SEL4; /**< Crossbar B Select Register 4, offset: 0x8 */ - __IO uint16_t SEL5; /**< Crossbar B Select Register 5, offset: 0xA */ - __IO uint16_t SEL6; /**< Crossbar B Select Register 6, offset: 0xC */ - __IO uint16_t SEL7; /**< Crossbar B Select Register 7, offset: 0xE */ -} XBARB_Type; - -/* ---------------------------------------------------------------------------- - -- XBARB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XBARB_Register_Masks XBARB Register Masks - * @{ - */ - -/*! @name SEL0 - Crossbar B Select Register 0 */ -/*! @{ */ -#define XBARB_SEL0_SEL0_MASK (0x3FU) -#define XBARB_SEL0_SEL0_SHIFT (0U) -#define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK) -#define XBARB_SEL0_SEL1_MASK (0x3F00U) -#define XBARB_SEL0_SEL1_SHIFT (8U) -#define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK) -/*! @} */ - -/*! @name SEL1 - Crossbar B Select Register 1 */ -/*! @{ */ -#define XBARB_SEL1_SEL2_MASK (0x3FU) -#define XBARB_SEL1_SEL2_SHIFT (0U) -#define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK) -#define XBARB_SEL1_SEL3_MASK (0x3F00U) -#define XBARB_SEL1_SEL3_SHIFT (8U) -#define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK) -/*! @} */ - -/*! @name SEL2 - Crossbar B Select Register 2 */ -/*! @{ */ -#define XBARB_SEL2_SEL4_MASK (0x3FU) -#define XBARB_SEL2_SEL4_SHIFT (0U) -#define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK) -#define XBARB_SEL2_SEL5_MASK (0x3F00U) -#define XBARB_SEL2_SEL5_SHIFT (8U) -#define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK) -/*! @} */ - -/*! @name SEL3 - Crossbar B Select Register 3 */ -/*! @{ */ -#define XBARB_SEL3_SEL6_MASK (0x3FU) -#define XBARB_SEL3_SEL6_SHIFT (0U) -#define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK) -#define XBARB_SEL3_SEL7_MASK (0x3F00U) -#define XBARB_SEL3_SEL7_SHIFT (8U) -#define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK) -/*! @} */ - -/*! @name SEL4 - Crossbar B Select Register 4 */ -/*! @{ */ -#define XBARB_SEL4_SEL8_MASK (0x3FU) -#define XBARB_SEL4_SEL8_SHIFT (0U) -#define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK) -#define XBARB_SEL4_SEL9_MASK (0x3F00U) -#define XBARB_SEL4_SEL9_SHIFT (8U) -#define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK) -/*! @} */ - -/*! @name SEL5 - Crossbar B Select Register 5 */ -/*! @{ */ -#define XBARB_SEL5_SEL10_MASK (0x3FU) -#define XBARB_SEL5_SEL10_SHIFT (0U) -#define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK) -#define XBARB_SEL5_SEL11_MASK (0x3F00U) -#define XBARB_SEL5_SEL11_SHIFT (8U) -#define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK) -/*! @} */ - -/*! @name SEL6 - Crossbar B Select Register 6 */ -/*! @{ */ -#define XBARB_SEL6_SEL12_MASK (0x3FU) -#define XBARB_SEL6_SEL12_SHIFT (0U) -#define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK) -#define XBARB_SEL6_SEL13_MASK (0x3F00U) -#define XBARB_SEL6_SEL13_SHIFT (8U) -#define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK) -/*! @} */ - -/*! @name SEL7 - Crossbar B Select Register 7 */ -/*! @{ */ -#define XBARB_SEL7_SEL14_MASK (0x3FU) -#define XBARB_SEL7_SEL14_SHIFT (0U) -#define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK) -#define XBARB_SEL7_SEL15_MASK (0x3F00U) -#define XBARB_SEL7_SEL15_SHIFT (8U) -#define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group XBARB_Register_Masks */ - - -/* XBARB - Peripheral instance base addresses */ -/** Peripheral XBARB2 base address */ -#define XBARB2_BASE (0x403C0000u) -/** Peripheral XBARB2 base pointer */ -#define XBARB2 ((XBARB_Type *)XBARB2_BASE) -/** Peripheral XBARB3 base address */ -#define XBARB3_BASE (0x403C4000u) -/** Peripheral XBARB3 base pointer */ -#define XBARB3 ((XBARB_Type *)XBARB3_BASE) -/** Array initializer of XBARB peripheral base addresses */ -#define XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE } -/** Array initializer of XBARB peripheral base pointers */ -#define XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 } - -/*! - * @} - */ /* end of group XBARB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- XTALOSC24M Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer - * @{ - */ - -/** XTALOSC24M - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[336]; - __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ - __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ - __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ - __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ - uint8_t RESERVED_1[272]; - __IO uint32_t LOWPWR_CTRL; /**< XTAL OSC (LP) Control Register, offset: 0x270 */ - __IO uint32_t LOWPWR_CTRL_SET; /**< XTAL OSC (LP) Control Register, offset: 0x274 */ - __IO uint32_t LOWPWR_CTRL_CLR; /**< XTAL OSC (LP) Control Register, offset: 0x278 */ - __IO uint32_t LOWPWR_CTRL_TOG; /**< XTAL OSC (LP) Control Register, offset: 0x27C */ - uint8_t RESERVED_2[32]; - __IO uint32_t OSC_CONFIG0; /**< XTAL OSC Configuration 0 Register, offset: 0x2A0 */ - __IO uint32_t OSC_CONFIG0_SET; /**< XTAL OSC Configuration 0 Register, offset: 0x2A4 */ - __IO uint32_t OSC_CONFIG0_CLR; /**< XTAL OSC Configuration 0 Register, offset: 0x2A8 */ - __IO uint32_t OSC_CONFIG0_TOG; /**< XTAL OSC Configuration 0 Register, offset: 0x2AC */ - __IO uint32_t OSC_CONFIG1; /**< XTAL OSC Configuration 1 Register, offset: 0x2B0 */ - __IO uint32_t OSC_CONFIG1_SET; /**< XTAL OSC Configuration 1 Register, offset: 0x2B4 */ - __IO uint32_t OSC_CONFIG1_CLR; /**< XTAL OSC Configuration 1 Register, offset: 0x2B8 */ - __IO uint32_t OSC_CONFIG1_TOG; /**< XTAL OSC Configuration 1 Register, offset: 0x2BC */ - __IO uint32_t OSC_CONFIG2; /**< XTAL OSC Configuration 2 Register, offset: 0x2C0 */ - __IO uint32_t OSC_CONFIG2_SET; /**< XTAL OSC Configuration 2 Register, offset: 0x2C4 */ - __IO uint32_t OSC_CONFIG2_CLR; /**< XTAL OSC Configuration 2 Register, offset: 0x2C8 */ - __IO uint32_t OSC_CONFIG2_TOG; /**< XTAL OSC Configuration 2 Register, offset: 0x2CC */ -} XTALOSC24M_Type; - -/* ---------------------------------------------------------------------------- - -- XTALOSC24M Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks - * @{ - */ - -/*! @name MISC0 - Miscellaneous Register 0 */ -/*! @{ */ -#define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U) -#define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U) -#define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK) -#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) -#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) -#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK) -#define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U) -#define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U) -#define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK) -#define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U) -#define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U) -#define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK) -#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) -#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U) -#define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK) -#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) -#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) -#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK) -#define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U) -#define XTALOSC24M_MISC0_OSC_I_SHIFT (13U) -#define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK) -#define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U) -#define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U) -#define XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK) -#define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U) -#define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U) -#define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK) -#define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U) -#define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U) -#define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK) -#define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) -#define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U) -#define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK) -#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) -#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) -#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK) -#define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U) -#define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U) -#define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK) -#define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) -#define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U) -#define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK) -/*! @} */ - -/*! @name MISC0_SET - Miscellaneous Register 0 */ -/*! @{ */ -#define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U) -#define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U) -#define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK) -#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) -#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) -#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK) -#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) -#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) -#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK) -#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) -#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) -#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK) -#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) -#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) -#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK) -#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) -#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) -#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK) -#define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U) -#define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U) -#define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK) -#define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U) -#define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U) -#define XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK) -#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) -#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) -#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK) -#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) -#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) -#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK) -#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) -#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) -#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK) -#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) -#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) -#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK) -#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) -#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) -#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK) -#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) -#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) -#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK) -/*! @} */ - -/*! @name MISC0_CLR - Miscellaneous Register 0 */ -/*! @{ */ -#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U) -#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U) -#define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK) -#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) -#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) -#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) -#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) -#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) -#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK) -#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) -#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) -#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK) -#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) -#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) -#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK) -#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) -#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) -#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK) -#define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U) -#define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U) -#define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK) -#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) -#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U) -#define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK) -#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) -#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) -#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK) -#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) -#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) -#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK) -#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) -#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) -#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK) -#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) -#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) -#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK) -#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) -#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) -#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK) -#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) -#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) -#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK) -/*! @} */ - -/*! @name MISC0_TOG - Miscellaneous Register 0 */ -/*! @{ */ -#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U) -#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U) -#define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK) -#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) -#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) -#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) -#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) -#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) -#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK) -#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) -#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) -#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK) -#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) -#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) -#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK) -#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) -#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) -#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK) -#define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U) -#define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U) -#define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK) -#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) -#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U) -#define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK) -#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) -#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) -#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK) -#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) -#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) -#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK) -#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) -#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) -#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK) -#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) -#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) -#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK) -#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) -#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) -#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK) -#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) -#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) -#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK) -/*! @} */ - -/*! @name LOWPWR_CTRL - XTAL OSC (LP) Control Register */ -/*! @{ */ -#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U) -#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U) -#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U) -#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U) -#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) -#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) -#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U) -#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK) -#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U) -#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U) -#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK) -#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U) -#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U) -#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK) -#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U) -#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U) -#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U) -#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U) -#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U) -#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U) -#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U) -#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U) -#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U) -#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U) -#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U) -#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U) -#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK) -#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U) -#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U) -#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) -#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U) -#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U) -#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U) -#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U) -#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK) -/*! @} */ - -/*! @name LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register */ -/*! @{ */ -#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U) -#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U) -#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U) -#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U) -#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U) -#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U) -#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U) -#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U) -#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U) -#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U) -#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U) -#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U) -#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U) -#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U) -#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) -#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U) -#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U) -#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U) -#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U) -#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U) -#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U) -#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U) -#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U) -#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U) -#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U) -#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U) -#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U) -#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U) -#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK) -/*! @} */ - -/*! @name LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register */ -/*! @{ */ -#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U) -#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK) -/*! @} */ - -/*! @name LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register */ -/*! @{ */ -#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK) -#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U) -#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK) -/*! @} */ - -/*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */ -/*! @{ */ -#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U) -#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U) -#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK) -#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U) -#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U) -#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK) -#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U) -#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U) -#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK) -#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U) -#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U) -#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK) -#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U) -#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U) -#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK) -#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U) -#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U) -#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK) -#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U) -#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U) -#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK) -#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U) -#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U) -#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) -/*! @} */ - -/*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */ -/*! @{ */ -#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U) -#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U) -#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK) -#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U) -#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U) -#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK) -#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U) -#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U) -#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK) -#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U) -#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U) -#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK) -#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U) -#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U) -#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK) -#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U) -#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U) -#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK) -#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U) -#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U) -#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK) -#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U) -#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U) -#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) -/*! @} */ - -/*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */ -/*! @{ */ -#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U) -#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U) -#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK) -#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U) -#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U) -#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK) -#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U) -#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U) -#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK) -#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U) -#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U) -#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK) -#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U) -#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U) -#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK) -#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U) -#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U) -#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK) -#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U) -#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U) -#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK) -#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U) -#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U) -#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) -/*! @} */ - -/*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */ -/*! @{ */ -#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U) -#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U) -#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK) -#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U) -#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U) -#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK) -#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U) -#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U) -#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK) -#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U) -#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U) -#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK) -#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U) -#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U) -#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK) -#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U) -#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U) -#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK) -#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U) -#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U) -#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK) -#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U) -#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U) -#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) -/*! @} */ - -/*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */ -/*! @{ */ -#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU) -#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U) -#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) -#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U) -#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U) -#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) -/*! @} */ - -/*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */ -/*! @{ */ -#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU) -#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U) -#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) -#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U) -#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U) -#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) -/*! @} */ - -/*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */ -/*! @{ */ -#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU) -#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U) -#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) -#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U) -#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U) -#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) -/*! @} */ - -/*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */ -/*! @{ */ -#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU) -#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U) -#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) -#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U) -#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U) -#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) -/*! @} */ - -/*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */ -/*! @{ */ -#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU) -#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U) -#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) -#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) -#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U) -#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK) -#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U) -#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U) -#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK) -#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U) -#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U) -#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK) -/*! @} */ - -/*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */ -/*! @{ */ -#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU) -#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U) -#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) -#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U) -#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U) -#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK) -#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U) -#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U) -#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK) -#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U) -#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U) -#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK) -/*! @} */ - -/*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */ -/*! @{ */ -#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU) -#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U) -#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) -#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U) -#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U) -#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK) -#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U) -#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U) -#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK) -#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U) -#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U) -#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK) -/*! @} */ - -/*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */ -/*! @{ */ -#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU) -#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U) -#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) -#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U) -#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U) -#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK) -#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U) -#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U) -#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK) -#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U) -#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U) -#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group XTALOSC24M_Register_Masks */ - - -/* XTALOSC24M - Peripheral instance base addresses */ -/** Peripheral XTALOSC24M base address */ -#define XTALOSC24M_BASE (0x400D8000u) -/** Peripheral XTALOSC24M base pointer */ -#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) -/** Array initializer of XTALOSC24M peripheral base addresses */ -#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE } -/** Array initializer of XTALOSC24M peripheral base pointers */ -#define XTALOSC24M_BASE_PTRS { XTALOSC24M } - -/*! - * @} - */ /* end of group XTALOSC24M_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -/* No SDK compatibility issues. */ - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _MIMXRT1052_H_ */ - diff --git a/bsp/imxrt1052-evk/Libraries/MIMXRT1052_features.h b/bsp/imxrt1052-evk/Libraries/MIMXRT1052_features.h deleted file mode 100644 index 765ebaddda..0000000000 --- a/bsp/imxrt1052-evk/Libraries/MIMXRT1052_features.h +++ /dev/null @@ -1,615 +0,0 @@ -/* -** ################################################################### -** Version: rev. 0.1, 2017-01-10 -** Build: b180509 -** -** Abstract: -** Chip specific module features. -** -** The Clear BSD License -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without -** modification, are permitted (subject to the limitations in the -** disclaimer below) provided that the following conditions are met: -** -** * Redistributions of source code must retain the above copyright -** notice, this list of conditions and the following disclaimer. -** -** * Redistributions in binary form must reproduce the above copyright -** notice, this list of conditions and the following disclaimer in the -** documentation and/or other materials provided with the distribution. -** -** * Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from -** this software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 0.1 (2017-01-10) -** Initial version. -** -** ################################################################### -*/ - -#ifndef _MIMXRT1052_FEATURES_H_ -#define _MIMXRT1052_FEATURES_H_ - -/* SOC module features */ - -/* @brief ADC availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC_COUNT (2) -/* @brief AIPSTZ availability on the SoC. */ -#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4) -/* @brief AOI availability on the SoC. */ -#define FSL_FEATURE_SOC_AOI_COUNT (2) -/* @brief CCM availability on the SoC. */ -#define FSL_FEATURE_SOC_CCM_COUNT (1) -/* @brief CCM_ANALOG availability on the SoC. */ -#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) -/* @brief CMP availability on the SoC. */ -#define FSL_FEATURE_SOC_CMP_COUNT (4) -/* @brief CSI availability on the SoC. */ -#define FSL_FEATURE_SOC_CSI_COUNT (1) -/* @brief DCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_DCDC_COUNT (1) -/* @brief DCP availability on the SoC. */ -#define FSL_FEATURE_SOC_DCP_COUNT (1) -/* @brief DMAMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) -/* @brief EDMA availability on the SoC. */ -#define FSL_FEATURE_SOC_EDMA_COUNT (1) -/* @brief ENC availability on the SoC. */ -#define FSL_FEATURE_SOC_ENC_COUNT (4) -/* @brief ENET availability on the SoC. */ -#define FSL_FEATURE_SOC_ENET_COUNT (1) -/* @brief EWM availability on the SoC. */ -#define FSL_FEATURE_SOC_EWM_COUNT (1) -/* @brief FLEXCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) -/* @brief FLEXIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXIO_COUNT (2) -/* @brief FLEXRAM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1) -/* @brief FLEXSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) -/* @brief GPC availability on the SoC. */ -#define FSL_FEATURE_SOC_GPC_COUNT (1) -/* @brief GPT availability on the SoC. */ -#define FSL_FEATURE_SOC_GPT_COUNT (2) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (3) -/* @brief IGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_IGPIO_COUNT (5) -/* @brief IOMUXC availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_COUNT (1) -/* @brief IOMUXC_GPR availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) -/* @brief IOMUXC_SNVS availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) -/* @brief KPP availability on the SoC. */ -#define FSL_FEATURE_SOC_KPP_COUNT (1) -/* @brief LCDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_LCDIF_COUNT (1) -/* @brief LPI2C availability on the SoC. */ -#define FSL_FEATURE_SOC_LPI2C_COUNT (4) -/* @brief LPSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSPI_COUNT (4) -/* @brief LPUART availability on the SoC. */ -#define FSL_FEATURE_SOC_LPUART_COUNT (8) -/* @brief OCOTP availability on the SoC. */ -#define FSL_FEATURE_SOC_OCOTP_COUNT (1) -/* @brief PIT availability on the SoC. */ -#define FSL_FEATURE_SOC_PIT_COUNT (1) -/* @brief PMU availability on the SoC. */ -#define FSL_FEATURE_SOC_PMU_COUNT (1) -/* @brief PWM availability on the SoC. */ -#define FSL_FEATURE_SOC_PWM_COUNT (4) -/* @brief PXP availability on the SoC. */ -#define FSL_FEATURE_SOC_PXP_COUNT (1) -/* @brief ROMC availability on the SoC. */ -#define FSL_FEATURE_SOC_ROMC_COUNT (1) -/* @brief SEMC availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMC_COUNT (1) -/* @brief SNVS availability on the SoC. */ -#define FSL_FEATURE_SOC_SNVS_COUNT (1) -/* @brief SPDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_SPDIF_COUNT (1) -/* @brief SRC availability on the SoC. */ -#define FSL_FEATURE_SOC_SRC_COUNT (1) -/* @brief TEMPMON availability on the SoC. */ -#define FSL_FEATURE_SOC_TEMPMON_COUNT (1) -/* @brief TMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TMR_COUNT (4) -/* @brief TRNG availability on the SoC. */ -#define FSL_FEATURE_SOC_TRNG_COUNT (1) -/* @brief TSC availability on the SoC. */ -#define FSL_FEATURE_SOC_TSC_COUNT (1) -/* @brief USBHS availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHS_COUNT (2) -/* @brief USBNC availability on the SoC. */ -#define FSL_FEATURE_SOC_USBNC_COUNT (2) -/* @brief USBPHY availability on the SoC. */ -#define FSL_FEATURE_SOC_USBPHY_COUNT (2) -/* @brief USDHC availability on the SoC. */ -#define FSL_FEATURE_SOC_USDHC_COUNT (2) -/* @brief WDOG availability on the SoC. */ -#define FSL_FEATURE_SOC_WDOG_COUNT (2) -/* @brief XBARA availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARA_COUNT (1) -/* @brief XBARB availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARB_COUNT (2) -/* @brief XTALOSC24M availability on the SoC. */ -#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) - -/* ADC module features */ - -/* @brief Remove Hardware Trigger feature. */ -#define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0) -/* @brief Remove ALT Clock selection feature. */ -#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1) - -/* ADC_ETC module features */ - -/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */ -#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1) - -/* AOI module features */ - -/* @brief Maximum value of input mux. */ -#define FSL_FEATURE_AOI_MODULE_INPUTS (4) -/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ -#define FSL_FEATURE_AOI_EVENT_COUNT (4) - -/* FLEXCAN module features */ - -/* @brief Message buffer size */ -#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64) -/* @brief Has doze mode support (register bit field MCR[DOZE]). */ -#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) -/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ -#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) -/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ -#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) -/* @brief Has extended bit timing register (register CBT). */ -#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) -/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ -#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) -/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ -#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) -/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ -#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) -/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ -#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0) -/* @brief Has extra MB interrupt or common one. */ -#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1) - -/* CMP module features */ - -/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ -#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) -/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ -#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) -/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ -#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) -/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ -#define FSL_FEATURE_CMP_HAS_DMA (1) -/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ -#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) -/* @brief Has DAC Test function in CMP (register DACTEST). */ -#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) - -/* EDMA module features */ - -/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32) -/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) -/* @brief Has DMA_Error interrupt vector. */ -#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) -/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) - -/* DMAMUX module features */ - -/* @brief Number of DMA channels (related to number of register CHCFGn). */ -#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32) -/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ -#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) -/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ -#define FSL_FEATURE_DMAMUX_HAS_A_ON (1) - -/* ENET module features */ - -/* @brief Support Interrupt Coalesce */ -#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) -/* @brief Queue Size. */ -#define FSL_FEATURE_ENET_QUEUE (1) -/* @brief Has AVB Support. */ -#define FSL_FEATURE_ENET_HAS_AVB (0) -/* @brief Has Timer Pulse Width control. */ -#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1) -/* @brief Has Extend MDIO Support. */ -#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) -/* @brief Has Additional 1588 Timer Channel Interrupt. */ -#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) - -/* FLEXIO module features */ - -/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ -#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) -/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ -#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) -/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ -#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) -/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ -#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) -/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ -#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) -/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ -#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) -/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ -#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) -/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ -#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) -/* @brief Reset value of the FLEXIO_VERID register */ -#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) -/* @brief Reset value of the FLEXIO_PARAM register */ -#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404) - -/* FLEXRAM module features */ - -/* @brief Bank size */ -#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024) -/* @brief Total Bank numbers */ -#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16) - -/* FLEXSPI module features */ - -/* @brief FlexSPI AHB buffer count */ -#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4) -/* @brief FlexSPI has no data learn. */ -#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1) - -/* GPC module features */ - -/* @brief Has DVFS0 Change Request. */ -#define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0) -/* @brief Has GPC interrupt/event masking. */ -#define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0) -/* @brief Has L2 cache power control. */ -#define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0) -/* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */ -#define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1) -/* @brief Has VADC power control. */ -#define FSL_FEATURE_GPC_HAS_CNTR_VADC (0) -/* @brief Has Display power control. */ -#define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0) -/* @brief Supports IRQ 0-31. */ -#define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1) - -/* IGPIO module features */ - -/* @brief Has data register set DR_SET. */ -#define FSL_FEATURE_IGPIO_HAS_DR_SET (1) -/* @brief Has data register clear DR_CLEAR. */ -#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1) -/* @brief Has data register toggle DR_TOGGLE. */ -#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1) - -/* LCDIF module features */ - -/* @brief LCDIF does not support alpha support. */ -#define FSL_FEATURE_LCDIF_HAS_NO_AS (1) -/* @brief LCDIF does not support output reset pin to LCD panel. */ -#define FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN (1) -/* @brief LCDIF supports LUT. */ -#define FSL_FEATURE_LCDIF_HAS_LUT (1) - -/* LPI2C module features */ - -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) - -/* LPSPI module features */ - -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) - -/* LPUART module features */ - -/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ -#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) -/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) -/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (1) -/* @brief Has 32-bit register MODIR */ -#define FSL_FEATURE_LPUART_HAS_MODIR (1) -/* @brief Hardware flow control (RTS, CTS) is supported. */ -#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) -/* @brief Infrared (modulation) is supported. */ -#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) -/* @brief 2 bits long stop bit is available. */ -#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) -/* @brief If 10-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) -/* @brief If 7-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) -/* @brief Baud rate fine adjustment is available. */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) -/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) -/* @brief Peripheral type. */ -#define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) -/* @brief Maximal data width without parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) -/* @brief Maximal data width with parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) -/* @brief Supports two match addresses to filter incoming frames. */ -#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) -/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) -/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ -#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) -/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) -/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ -#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) -/* @brief Has improved smart card (ISO7816 protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) -/* @brief Has local operation network (CEA709.1-B protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) -/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ -#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) -/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ -#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) -/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ -#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has separate RX and TX interrupts. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) -/* @brief Has LPAURT_PARAM. */ -#define FSL_FEATURE_LPUART_HAS_PARAM (1) -/* @brief Has LPUART_VERID. */ -#define FSL_FEATURE_LPUART_HAS_VERID (1) -/* @brief Has LPUART_GLOBAL. */ -#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) -/* @brief Has LPUART_PINCFG. */ -#define FSL_FEATURE_LPUART_HAS_PINCFG (1) - -/* interrupt module features */ - -/* @brief Lowest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) -/* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (159) - -/* OCOTP module features */ - -/* No feature definitions */ - -/* PIT module features */ - -/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ -#define FSL_FEATURE_PIT_TIMER_COUNT (4) -/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ -#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) -/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ -#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) -/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ -#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) -/* @brief Has timer enable control. */ -#define FSL_FEATURE_PIT_HAS_MDIS (1) - -/* PMU module features */ - -/* @brief PMU supports lower power control. */ -#define FSL_FEATURE_PMU_HAS_LOWPWR_CTRL (0) - -/* PWM module features */ - -/* @brief Number of each EflexPWM module channels (outputs). */ -#define FSL_FEATURE_PWM_CHANNEL_COUNT (12U) -/* @brief Number of EflexPWM module A channels (outputs). */ -#define FSL_FEATURE_PWM_CHANNELA_COUNT (4U) -/* @brief Number of EflexPWM module B channels (outputs). */ -#define FSL_FEATURE_PWM_CHANNELB_COUNT (4U) -/* @brief Number of EflexPWM module X channels (outputs). */ -#define FSL_FEATURE_PWM_CHANNELX_COUNT (4U) -/* @brief Number of each EflexPWM module compare channels interrupts. */ -#define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U) -/* @brief Number of each EflexPWM module reload channels interrupts. */ -#define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U) -/* @brief Number of each EflexPWM module capture channels interrupts. */ -#define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U) -/* @brief Number of each EflexPWM module reload error channels interrupts. */ -#define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U) -/* @brief Number of each EflexPWM module fault channels interrupts. */ -#define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U) -/* @brief Number of submodules in each EflexPWM module. */ -#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) - -/* PXP module features */ - -/* @brief PXP module has dither engine. */ -#define FSL_FEATURE_PXP_HAS_DITHER (0) -/* @brief PXP module supports repeat run */ -#define FSL_FEATURE_PXP_HAS_EN_REPEAT (1) -/* @brief PXP doesn't have CSC */ -#define FSL_FEATURE_PXP_HAS_NO_CSC2 (1) -/* @brief PXP doesn't have LUT */ -#define FSL_FEATURE_PXP_HAS_NO_LUT (1) - -/* RTWDOG module features */ - -/* @brief Watchdog is available. */ -#define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1) -/* @brief RTWDOG_CNT can be 32-bit written. */ -#define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1) - -/* SAI module features */ - -/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ -#define FSL_FEATURE_SAI_FIFO_COUNT (32) -/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ -#define FSL_FEATURE_SAI_CHANNEL_COUNT (4) -/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ -#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) -/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ -#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) -/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ -#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) -/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ -#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) -/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ -#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) -/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ -#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) -/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ -#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) -/* @brief Interrupt source number */ -#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) -/* @brief Has register of MCR. */ -#define FSL_FEATURE_SAI_HAS_MCR (0) -/* @brief Has register of MDR */ -#define FSL_FEATURE_SAI_HAS_MDR (0) - -/* SNVS module features */ - -/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ -#define FSL_FEATURE_SNVS_HAS_SRTC (1) - -/* SRC module features */ - -/* @brief There is MASK_WDOG3_RST bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1) -/* @brief There is MIX_RST_STRCH bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0) -/* @brief There is DBG_RST_MSK_PG bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1) -/* @brief There is WDOG3_RST_OPTN bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0) -/* @brief There is CORES_DBG_RST bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0) -/* @brief There is MTSR bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_MTSR (0) -/* @brief There is CORE0_DBG_RST bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1) -/* @brief There is CORE0_RST bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) -/* @brief There is LOCKUP_RST bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0) -/* @brief There is SWRC bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) -/* @brief There is EIM_RST bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0) -/* @brief There is LUEN bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_SCR_LUEN (0) -/* @brief There is no WRBC bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1) -/* @brief There is no WRE bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1) -/* @brief There is SISR register. */ -#define FSL_FEATURE_SRC_HAS_SISR (0) -/* @brief There is RESET_OUT bit in SRSR register. */ -#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0) -/* @brief There is WDOG3_RST_B bit in SRSR register. */ -#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1) -/* @brief There is SW bit in SRSR register. */ -#define FSL_FEATURE_SRC_HAS_SRSR_SW (0) -/* @brief There is IPP_USER_RESET_B bit in SRSR register. */ -#define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1) -/* @brief There is SNVS bit in SRSR register. */ -#define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0) -/* @brief There is CSU_RESET_B bit in SRSR register. */ -#define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1) -/* @brief There is LOCKUP bit in SRSR register. */ -#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (0) -/* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */ -#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (1) -/* @brief There is POR bit in SRSR register. */ -#define FSL_FEATURE_SRC_HAS_SRSR_POR (0) -/* @brief There is IPP_RESET_B bit in SRSR register. */ -#define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1) -/* @brief There is no WBI bit in SCR register. */ -#define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1) - -/* SCB module features */ - -/* @brief L1 ICACHE line size in byte. */ -#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) -/* @brief L1 DCACHE line size in byte. */ -#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) - -/* TRNG module features */ - -/* @brief TRNG has no TRNG_ACC bitfield. */ -#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) - -/* USBHS module features */ - -/* @brief EHCI module instance count */ -#define FSL_FEATURE_USBHS_EHCI_COUNT (2) -/* @brief Number of endpoints supported */ -#define FSL_FEATURE_USBHS_ENDPT_COUNT (8) - -/* USDHC module features */ - -/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ -#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) -/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ -#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) -/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ -#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) -/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ -#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) - -/* XBARA module features */ - -/* @brief DMA_CH_MUX_REQ_30. */ -#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 (1) -/* @brief DMA_CH_MUX_REQ_31. */ -#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 (1) -/* @brief DMA_CH_MUX_REQ_94. */ -#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 (1) -/* @brief DMA_CH_MUX_REQ_95. */ -#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 (1) - -#endif /* _MIMXRT1052_FEATURES_H_ */ - diff --git a/bsp/imxrt1052-evk/Libraries/SConscript b/bsp/imxrt1052-evk/Libraries/SConscript deleted file mode 100644 index d9d84e78b2..0000000000 --- a/bsp/imxrt1052-evk/Libraries/SConscript +++ /dev/null @@ -1,27 +0,0 @@ -# RT-Thread building script for component - -Import('rtconfig') -Import('RTT_ROOT') -from building import * - -cwd = GetCurrentDir() -src = Glob('drivers/*.c') - -SrcRemove(src, 'drivers/dataqueue.c') -src += Glob('common/chip/*.c') -src += [cwd + '/system_MIMXRT1052.c'] - -CPPPATH = [ cwd, cwd + '/drivers', cwd + '/utilities', cwd + '/CMSIS/Include'] -CPPDEFINES = ['CPU_MIMXRT1052DVL6B', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1'] - -# add for startup script -if rtconfig.CROSS_TOOL == 'gcc': - src += [cwd + '/gcc/startup_MIMXRT1052.S'] -elif rtconfig.CROSS_TOOL == 'keil': - src += [cwd + '/arm/startup_MIMXRT1052.s'] -elif rtconfig.CROSS_TOOL == 'iar': - src += [cwd + '/iar/startup_MIMXRT1052.s'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) - -Return('group') diff --git a/bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf b/bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf deleted file mode 100644 index 8fdb2c4cd2..0000000000 --- a/bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf +++ /dev/null @@ -1,127 +0,0 @@ -#! armcc -E -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#define m_flash_config_start 0x60000000 -#define m_flash_config_size 0x00001000 - -#define m_ivt_start 0x60001000 -#define m_ivt_size 0x00001000 - -#define m_text_start 0x60002000 -#define m_text_size 0x1F7FE000 - -#define m_data_start 0x20000000 -#define m_data_size 0x00020000 - -#define m_ncache_start 0x81E00000 -#define m_ncache_size 0x00200000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x1000 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#include "../../rtconfig.h" - -#if (defined(BOARD_USING_HYPERFLASH)) -LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region -{ - RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address - { - * (.boot_hdr.conf, +FIRST) - } -} - -LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region -{ - RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address - { - * (.boot_hdr.ivt, +FIRST) - * (.boot_hdr.boot_data) - * (.boot_hdr.dcd_data) - } -} -#endif - -#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) - -; load region size_region -LR_IROM1 m_text_start m_text_size -{ - ER_IROM1 m_text_start m_text_size ; load address = execution address - { - * (RESET,+FIRST) - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data - { - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up - ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down - RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} - - ; ncache RW data - RW_m_ncache m_ncache_start m_ncache_size - { - * (NonCacheable.init) - * (NonCacheable) - } -} - - diff --git a/bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_ram.scf b/bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_ram.scf deleted file mode 100644 index bc175605d0..0000000000 --- a/bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_ram.scf +++ /dev/null @@ -1,92 +0,0 @@ -#! armcc -E -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#define m_interrupts_start 0x00000000 -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x00000400 -#define m_text_size 0x0001FC00 - -#define m_data_start 0x20000000 -#define m_data_size 0x00020000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -LR_m_text m_text_start m_text_size { ; load region size_region - ER_m_text m_text_start m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - * (NonCacheable.init) - * (NonCacheable) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } -} - -LR_m_interrupts m_interrupts_start m_interrupts_size { - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) - } -} - - diff --git a/bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_sdram.scf b/bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_sdram.scf deleted file mode 100644 index 30b771d212..0000000000 --- a/bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_sdram.scf +++ /dev/null @@ -1,99 +0,0 @@ -#! armcc -E -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#define m_interrupts_start 0x00000000 -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x00000400 -#define m_text_size 0x0001FC00 - -#define m_data_start 0x80000000 -#define m_data_size 0x01E00000 - -#define m_ncache_start 0x81E00000 -#define m_ncache_size 0x00200000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -LR_m_text m_text_start m_text_size { ; load region size_region - ER_m_text m_text_start m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - *(m_usb_dma_init_data) - *(m_usb_dma_noninit_data) - } - RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data - * (NonCacheable.init) - * (NonCacheable) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } -} - -LR_m_interrupts m_interrupts_start m_interrupts_size { - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) - } -} - - diff --git a/bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_sdram_txt.scf b/bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_sdram_txt.scf deleted file mode 100644 index cc86f22cb8..0000000000 --- a/bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_sdram_txt.scf +++ /dev/null @@ -1,99 +0,0 @@ -#! armcc -E -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#define m_interrupts_start 0x80000000 -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x80000400 -#define m_text_size 0x001FFC00 - -#define m_data_start 0x20200000 -#define m_data_size 0x00040000 - -#define m_ncache_start 0x81E00000 -#define m_ncache_size 0x00200000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -LR_m_text m_text_start m_text_size { ; load region size_region - ER_m_text m_text_start m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - *(m_usb_dma_init_data) - *(m_usb_dma_noninit_data) - } - RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data - * (NonCacheable.init) - * (NonCacheable) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } -} - -LR_m_interrupts m_interrupts_start m_interrupts_size { - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) - } -} - - diff --git a/bsp/imxrt1052-evk/Libraries/arm/evkmimxrt1050_flexspi_nor.ini b/bsp/imxrt1052-evk/Libraries/arm/evkmimxrt1050_flexspi_nor.ini deleted file mode 100644 index 1e21d31013..0000000000 --- a/bsp/imxrt1052-evk/Libraries/arm/evkmimxrt1050_flexspi_nor.ini +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -FUNC void Setup (void) { - - SP = _RDWORD(0x60002000); // Setup Stack Pointer - PC = _RDWORD(0x60002004); // Setup Program Counter - _WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register -} - -FUNC void OnResetExec (void) { // executes upon software RESET - Setup(); // Setup for Running -} - -LOAD %L INCREMENTAL // Download - -Setup(); // Setup for Running - -// g, main diff --git a/bsp/imxrt1052-evk/Libraries/arm/startup_MIMXRT1052.s b/bsp/imxrt1052-evk/Libraries/arm/startup_MIMXRT1052.s deleted file mode 100644 index 22cd46e7ba..0000000000 --- a/bsp/imxrt1052-evk/Libraries/arm/startup_MIMXRT1052.s +++ /dev/null @@ -1,1044 +0,0 @@ -; * --------------------------------------------------------------------------------------- -; * @file: startup_MIMXRT1052.s -; * @purpose: CMSIS Cortex-M7 Core Device Startup File -; * MIMXRT1052 -; * @version: 0.1 -; * @date: 2017-1-10 -; * @build: b170927 -; * --------------------------------------------------------------------------------------- -; * -; * Copyright 1997-2016 Freescale Semiconductor, Inc. -; * Copyright 2016-2017 NXP -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: -; * -; * 1. Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * 2. Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * 3. Neither the name of the copyright holder nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD MemManage_Handler ;MPU Fault Handler - DCD BusFault_Handler ;Bus Fault Handler - DCD UsageFault_Handler ;Usage Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD DebugMon_Handler ;Debug Monitor Handler - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_DMA16_IRQHandler ;DMA channel 0/16 transfer complete - DCD DMA1_DMA17_IRQHandler ;DMA channel 1/17 transfer complete - DCD DMA2_DMA18_IRQHandler ;DMA channel 2/18 transfer complete - DCD DMA3_DMA19_IRQHandler ;DMA channel 3/19 transfer complete - DCD DMA4_DMA20_IRQHandler ;DMA channel 4/20 transfer complete - DCD DMA5_DMA21_IRQHandler ;DMA channel 5/21 transfer complete - DCD DMA6_DMA22_IRQHandler ;DMA channel 6/22 transfer complete - DCD DMA7_DMA23_IRQHandler ;DMA channel 7/23 transfer complete - DCD DMA8_DMA24_IRQHandler ;DMA channel 8/24 transfer complete - DCD DMA9_DMA25_IRQHandler ;DMA channel 9/25 transfer complete - DCD DMA10_DMA26_IRQHandler ;DMA channel 10/26 transfer complete - DCD DMA11_DMA27_IRQHandler ;DMA channel 11/27 transfer complete - DCD DMA12_DMA28_IRQHandler ;DMA channel 12/28 transfer complete - DCD DMA13_DMA29_IRQHandler ;DMA channel 13/29 transfer complete - DCD DMA14_DMA30_IRQHandler ;DMA channel 14/30 transfer complete - DCD DMA15_DMA31_IRQHandler ;DMA channel 15/31 transfer complete - DCD DMA_ERROR_IRQHandler ;DMA error interrupt channels 0-15 / 16-31 - DCD CTI0_ERROR_IRQHandler ;CTI0_Error - DCD CTI1_ERROR_IRQHandler ;CTI1_Error - DCD CORE_IRQHandler ;CorePlatform exception IRQ - DCD LPUART1_IRQHandler ;LPUART1 TX interrupt and RX interrupt - DCD LPUART2_IRQHandler ;LPUART2 TX interrupt and RX interrupt - DCD LPUART3_IRQHandler ;LPUART3 TX interrupt and RX interrupt - DCD LPUART4_IRQHandler ;LPUART4 TX interrupt and RX interrupt - DCD LPUART5_IRQHandler ;LPUART5 TX interrupt and RX interrupt - DCD LPUART6_IRQHandler ;LPUART6 TX interrupt and RX interrupt - DCD LPUART7_IRQHandler ;LPUART7 TX interrupt and RX interrupt - DCD LPUART8_IRQHandler ;LPUART8 TX interrupt and RX interrupt - DCD LPI2C1_IRQHandler ;LPI2C1 interrupt - DCD LPI2C2_IRQHandler ;LPI2C2 interrupt - DCD LPI2C3_IRQHandler ;LPI2C3 interrupt - DCD LPI2C4_IRQHandler ;LPI2C4 interrupt - DCD LPSPI1_IRQHandler ;LPSPI1 single interrupt vector for all sources - DCD LPSPI2_IRQHandler ;LPSPI2 single interrupt vector for all sources - DCD LPSPI3_IRQHandler ;LPSPI3 single interrupt vector for all sources - DCD LPSPI4_IRQHandler ;LPSPI4 single interrupt vector for all sources - DCD CAN1_IRQHandler ;CAN1 interrupt - DCD CAN2_IRQHandler ;CAN2 interrupt - DCD FLEXRAM_IRQHandler ;FlexRAM address out of range Or access hit IRQ - DCD KPP_IRQHandler ;Keypad nterrupt - DCD TSC_DIG_IRQHandler ;TSC interrupt - DCD GPR_IRQ_IRQHandler ;GPR interrupt - DCD LCDIF_IRQHandler ;LCDIF interrupt - DCD CSI_IRQHandler ;CSI interrupt - DCD PXP_IRQHandler ;PXP interrupt - DCD WDOG2_IRQHandler ;WDOG2 interrupt - DCD SNVS_HP_WRAPPER_IRQHandler ;SRTC Consolidated Interrupt. Non TZ - DCD SNVS_HP_WRAPPER_TZ_IRQHandler ;SRTC Security Interrupt. TZ - DCD SNVS_LP_WRAPPER_IRQHandler ;ON-OFF button press shorter than 5 secs (pulse event) - DCD CSU_IRQHandler ;CSU interrupt - DCD DCP_IRQHandler ;DCP_IRQ interrupt - DCD DCP_VMI_IRQHandler ;DCP_VMI_IRQ interrupt - DCD Reserved68_IRQHandler ;Reserved interrupt - DCD TRNG_IRQHandler ;TRNG interrupt - DCD SJC_IRQHandler ;SJC interrupt - DCD BEE_IRQHandler ;BEE interrupt - DCD SAI1_IRQHandler ;SAI1 interrupt - DCD SAI2_IRQHandler ;SAI1 interrupt - DCD SAI3_RX_IRQHandler ;SAI3 interrupt - DCD SAI3_TX_IRQHandler ;SAI3 interrupt - DCD SPDIF_IRQHandler ;SPDIF interrupt - DCD ANATOP_EVENT0_IRQHandler ;ANATOP interrupt - DCD ANATOP_EVENT1_IRQHandler ;ANATOP interrupt - DCD ANATOP_TAMP_LOW_HIGH_IRQHandler ;ANATOP interrupt - DCD ANATOP_TEMP_PANIC_IRQHandler ;ANATOP interrupt - DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt - DCD USB_PHY2_IRQHandler ;USBPHY (UTMI0), Interrupt - DCD ADC1_IRQHandler ;ADC1 interrupt - DCD ADC2_IRQHandler ;ADC2 interrupt - DCD DCDC_IRQHandler ;DCDC interrupt - DCD Reserved86_IRQHandler ;Reserved interrupt - DCD Reserved87_IRQHandler ;Reserved interrupt - DCD GPIO1_INT0_IRQHandler ;Active HIGH Interrupt from INT0 from GPIO - DCD GPIO1_INT1_IRQHandler ;Active HIGH Interrupt from INT1 from GPIO - DCD GPIO1_INT2_IRQHandler ;Active HIGH Interrupt from INT2 from GPIO - DCD GPIO1_INT3_IRQHandler ;Active HIGH Interrupt from INT3 from GPIO - DCD GPIO1_INT4_IRQHandler ;Active HIGH Interrupt from INT4 from GPIO - DCD GPIO1_INT5_IRQHandler ;Active HIGH Interrupt from INT5 from GPIO - DCD GPIO1_INT6_IRQHandler ;Active HIGH Interrupt from INT6 from GPIO - DCD GPIO1_INT7_IRQHandler ;Active HIGH Interrupt from INT7 from GPIO - DCD GPIO1_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO1 signal 0 throughout 15 - DCD GPIO1_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO1 signal 16 throughout 31 - DCD GPIO2_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO2 signal 0 throughout 15 - DCD GPIO2_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO2 signal 16 throughout 31 - DCD GPIO3_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO3 signal 0 throughout 15 - DCD GPIO3_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO3 signal 16 throughout 31 - DCD GPIO4_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO4 signal 0 throughout 15 - DCD GPIO4_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO4 signal 16 throughout 31 - DCD GPIO5_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO5 signal 0 throughout 15 - DCD GPIO5_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO5 signal 16 throughout 31 - DCD FLEXIO1_IRQHandler ;FLEXIO1 interrupt - DCD FLEXIO2_IRQHandler ;FLEXIO2 interrupt - DCD WDOG1_IRQHandler ;WDOG1 interrupt - DCD RTWDOG_IRQHandler ;RTWDOG interrupt - DCD EWM_IRQHandler ;EWM interrupt - DCD CCM_1_IRQHandler ;CCM IRQ1 interrupt - DCD CCM_2_IRQHandler ;CCM IRQ2 interrupt - DCD GPC_IRQHandler ;GPC interrupt - DCD SRC_IRQHandler ;SRC interrupt - DCD Reserved115_IRQHandler ;Reserved interrupt - DCD GPT1_IRQHandler ;GPT1 interrupt - DCD GPT2_IRQHandler ;GPT2 interrupt - DCD PWM1_0_IRQHandler ;PWM1 capture 0, compare 0, or reload 0 interrupt - DCD PWM1_1_IRQHandler ;PWM1 capture 1, compare 1, or reload 0 interrupt - DCD PWM1_2_IRQHandler ;PWM1 capture 2, compare 2, or reload 0 interrupt - DCD PWM1_3_IRQHandler ;PWM1 capture 3, compare 3, or reload 0 interrupt - DCD PWM1_FAULT_IRQHandler ;PWM1 fault or reload error interrupt - DCD Reserved123_IRQHandler ;Reserved interrupt - DCD FLEXSPI_IRQHandler ;FlexSPI0 interrupt - DCD SEMC_IRQHandler ;Reserved interrupt - DCD USDHC1_IRQHandler ;USDHC1 interrupt - DCD USDHC2_IRQHandler ;USDHC2 interrupt - DCD USB_OTG2_IRQHandler ;USBO2 USB OTG2 - DCD USB_OTG1_IRQHandler ;USBO2 USB OTG1 - DCD ENET_IRQHandler ;ENET interrupt - DCD ENET_1588_Timer_IRQHandler ;ENET_1588_Timer interrupt - DCD XBAR1_IRQ_0_1_IRQHandler ;XBAR1 interrupt - DCD XBAR1_IRQ_2_3_IRQHandler ;XBAR1 interrupt - DCD ADC_ETC_IRQ0_IRQHandler ;ADCETC IRQ0 interrupt - DCD ADC_ETC_IRQ1_IRQHandler ;ADCETC IRQ1 interrupt - DCD ADC_ETC_IRQ2_IRQHandler ;ADCETC IRQ2 interrupt - DCD ADC_ETC_ERROR_IRQ_IRQHandler ;ADCETC Error IRQ interrupt - DCD PIT_IRQHandler ;PIT interrupt - DCD ACMP1_IRQHandler ;ACMP interrupt - DCD ACMP2_IRQHandler ;ACMP interrupt - DCD ACMP3_IRQHandler ;ACMP interrupt - DCD ACMP4_IRQHandler ;ACMP interrupt - DCD Reserved143_IRQHandler ;Reserved interrupt - DCD Reserved144_IRQHandler ;Reserved interrupt - DCD ENC1_IRQHandler ;ENC1 interrupt - DCD ENC2_IRQHandler ;ENC2 interrupt - DCD ENC3_IRQHandler ;ENC3 interrupt - DCD ENC4_IRQHandler ;ENC4 interrupt - DCD TMR1_IRQHandler ;TMR1 interrupt - DCD TMR2_IRQHandler ;TMR2 interrupt - DCD TMR3_IRQHandler ;TMR3 interrupt - DCD TMR4_IRQHandler ;TMR4 interrupt - DCD PWM2_0_IRQHandler ;PWM2 capture 0, compare 0, or reload 0 interrupt - DCD PWM2_1_IRQHandler ;PWM2 capture 1, compare 1, or reload 0 interrupt - DCD PWM2_2_IRQHandler ;PWM2 capture 2, compare 2, or reload 0 interrupt - DCD PWM2_3_IRQHandler ;PWM2 capture 3, compare 3, or reload 0 interrupt - DCD PWM2_FAULT_IRQHandler ;PWM2 fault or reload error interrupt - DCD PWM3_0_IRQHandler ;PWM3 capture 0, compare 0, or reload 0 interrupt - DCD PWM3_1_IRQHandler ;PWM3 capture 1, compare 1, or reload 0 interrupt - DCD PWM3_2_IRQHandler ;PWM3 capture 2, compare 2, or reload 0 interrupt - DCD PWM3_3_IRQHandler ;PWM3 capture 3, compare 3, or reload 0 interrupt - DCD PWM3_FAULT_IRQHandler ;PWM3 fault or reload error interrupt - DCD PWM4_0_IRQHandler ;PWM4 capture 0, compare 0, or reload 0 interrupt - DCD PWM4_1_IRQHandler ;PWM4 capture 1, compare 1, or reload 0 interrupt - DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt - DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt - DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt - DCD Reserved168_IRQHandler ;Reserved interrupt - DCD Reserved169_IRQHandler ;Reserved interrupt - DCD Reserved170_IRQHandler ;Reserved interrupt - DCD Reserved171_IRQHandler ;Reserved interrupt - DCD Reserved172_IRQHandler ;Reserved interrupt - DCD Reserved173_IRQHandler ;Reserved interrupt - DCD SJC_ARM_DEBUG_IRQHandler ;SJC ARM debug interrupt - DCD NMI_WAKEUP_IRQHandler ;NMI wake up - DCD DefaultISR ;176 - DCD DefaultISR ;177 - DCD DefaultISR ;178 - DCD DefaultISR ;179 - DCD DefaultISR ;180 - DCD DefaultISR ;181 - DCD DefaultISR ;182 - DCD DefaultISR ;183 - DCD DefaultISR ;184 - DCD DefaultISR ;185 - DCD DefaultISR ;186 - DCD DefaultISR ;187 - DCD DefaultISR ;188 - DCD DefaultISR ;189 - DCD DefaultISR ;190 - DCD DefaultISR ;191 - DCD DefaultISR ;192 - DCD DefaultISR ;193 - DCD DefaultISR ;194 - DCD DefaultISR ;195 - DCD DefaultISR ;196 - DCD DefaultISR ;197 - DCD DefaultISR ;198 - DCD DefaultISR ;199 - DCD DefaultISR ;200 - DCD DefaultISR ;201 - DCD DefaultISR ;202 - DCD DefaultISR ;203 - DCD DefaultISR ;204 - DCD DefaultISR ;205 - DCD DefaultISR ;206 - DCD DefaultISR ;207 - DCD DefaultISR ;208 - DCD DefaultISR ;209 - DCD DefaultISR ;210 - DCD DefaultISR ;211 - DCD DefaultISR ;212 - DCD DefaultISR ;213 - DCD DefaultISR ;214 - DCD DefaultISR ;215 - DCD DefaultISR ;216 - DCD DefaultISR ;217 - DCD DefaultISR ;218 - DCD DefaultISR ;219 - DCD DefaultISR ;220 - DCD DefaultISR ;221 - DCD DefaultISR ;222 - DCD DefaultISR ;223 - DCD DefaultISR ;224 - DCD DefaultISR ;225 - DCD DefaultISR ;226 - DCD DefaultISR ;227 - DCD DefaultISR ;228 - DCD DefaultISR ;229 - DCD DefaultISR ;230 - DCD DefaultISR ;231 - DCD DefaultISR ;232 - DCD DefaultISR ;233 - DCD DefaultISR ;234 - DCD DefaultISR ;235 - DCD DefaultISR ;236 - DCD DefaultISR ;237 - DCD DefaultISR ;238 - DCD DefaultISR ;239 - DCD DefaultISR ;240 - DCD DefaultISR ;241 - DCD DefaultISR ;242 - DCD DefaultISR ;243 - DCD DefaultISR ;244 - DCD DefaultISR ;245 - DCD DefaultISR ;246 - DCD DefaultISR ;247 - DCD DefaultISR ;248 - DCD DefaultISR ;249 - DCD DefaultISR ;250 - DCD DefaultISR ;251 - DCD DefaultISR ;252 - DCD DefaultISR ;253 - DCD DefaultISR ;254 - DCD 0xFFFFFFFF ; Reserved for user TRIM value -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__Vectors - STR R1, [R0] - LDR R2, [R1] - MSR MSP, R2 - LDR R0, =SystemInit - BLX R0 - CPSIE i ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -DMA0_DMA16_IRQHandler\ - PROC - EXPORT DMA0_DMA16_IRQHandler [WEAK] - LDR R0, =DMA0_DMA16_DriverIRQHandler - BX R0 - ENDP - -DMA1_DMA17_IRQHandler\ - PROC - EXPORT DMA1_DMA17_IRQHandler [WEAK] - LDR R0, =DMA1_DMA17_DriverIRQHandler - BX R0 - ENDP - -DMA2_DMA18_IRQHandler\ - PROC - EXPORT DMA2_DMA18_IRQHandler [WEAK] - LDR R0, =DMA2_DMA18_DriverIRQHandler - BX R0 - ENDP - -DMA3_DMA19_IRQHandler\ - PROC - EXPORT DMA3_DMA19_IRQHandler [WEAK] - LDR R0, =DMA3_DMA19_DriverIRQHandler - BX R0 - ENDP - -DMA4_DMA20_IRQHandler\ - PROC - EXPORT DMA4_DMA20_IRQHandler [WEAK] - LDR R0, =DMA4_DMA20_DriverIRQHandler - BX R0 - ENDP - -DMA5_DMA21_IRQHandler\ - PROC - EXPORT DMA5_DMA21_IRQHandler [WEAK] - LDR R0, =DMA5_DMA21_DriverIRQHandler - BX R0 - ENDP - -DMA6_DMA22_IRQHandler\ - PROC - EXPORT DMA6_DMA22_IRQHandler [WEAK] - LDR R0, =DMA6_DMA22_DriverIRQHandler - BX R0 - ENDP - -DMA7_DMA23_IRQHandler\ - PROC - EXPORT DMA7_DMA23_IRQHandler [WEAK] - LDR R0, =DMA7_DMA23_DriverIRQHandler - BX R0 - ENDP - -DMA8_DMA24_IRQHandler\ - PROC - EXPORT DMA8_DMA24_IRQHandler [WEAK] - LDR R0, =DMA8_DMA24_DriverIRQHandler - BX R0 - ENDP - -DMA9_DMA25_IRQHandler\ - PROC - EXPORT DMA9_DMA25_IRQHandler [WEAK] - LDR R0, =DMA9_DMA25_DriverIRQHandler - BX R0 - ENDP - -DMA10_DMA26_IRQHandler\ - PROC - EXPORT DMA10_DMA26_IRQHandler [WEAK] - LDR R0, =DMA10_DMA26_DriverIRQHandler - BX R0 - ENDP - -DMA11_DMA27_IRQHandler\ - PROC - EXPORT DMA11_DMA27_IRQHandler [WEAK] - LDR R0, =DMA11_DMA27_DriverIRQHandler - BX R0 - ENDP - -DMA12_DMA28_IRQHandler\ - PROC - EXPORT DMA12_DMA28_IRQHandler [WEAK] - LDR R0, =DMA12_DMA28_DriverIRQHandler - BX R0 - ENDP - -DMA13_DMA29_IRQHandler\ - PROC - EXPORT DMA13_DMA29_IRQHandler [WEAK] - LDR R0, =DMA13_DMA29_DriverIRQHandler - BX R0 - ENDP - -DMA14_DMA30_IRQHandler\ - PROC - EXPORT DMA14_DMA30_IRQHandler [WEAK] - LDR R0, =DMA14_DMA30_DriverIRQHandler - BX R0 - ENDP - -DMA15_DMA31_IRQHandler\ - PROC - EXPORT DMA15_DMA31_IRQHandler [WEAK] - LDR R0, =DMA15_DMA31_DriverIRQHandler - BX R0 - ENDP - -DMA_ERROR_IRQHandler\ - PROC - EXPORT DMA_ERROR_IRQHandler [WEAK] - LDR R0, =DMA_ERROR_DriverIRQHandler - BX R0 - ENDP - -LPUART1_IRQHandler\ - PROC - EXPORT LPUART1_IRQHandler [WEAK] - LDR R0, =LPUART1_DriverIRQHandler - BX R0 - ENDP - -LPUART2_IRQHandler\ - PROC - EXPORT LPUART2_IRQHandler [WEAK] - LDR R0, =LPUART2_DriverIRQHandler - BX R0 - ENDP - -LPUART3_IRQHandler\ - PROC - EXPORT LPUART3_IRQHandler [WEAK] - LDR R0, =LPUART3_DriverIRQHandler - BX R0 - ENDP - -LPUART4_IRQHandler\ - PROC - EXPORT LPUART4_IRQHandler [WEAK] - LDR R0, =LPUART4_DriverIRQHandler - BX R0 - ENDP - -LPUART5_IRQHandler\ - PROC - EXPORT LPUART5_IRQHandler [WEAK] - LDR R0, =LPUART5_DriverIRQHandler - BX R0 - ENDP - -LPUART6_IRQHandler\ - PROC - EXPORT LPUART6_IRQHandler [WEAK] - LDR R0, =LPUART6_DriverIRQHandler - BX R0 - ENDP - -LPUART7_IRQHandler\ - PROC - EXPORT LPUART7_IRQHandler [WEAK] - LDR R0, =LPUART7_DriverIRQHandler - BX R0 - ENDP - -LPUART8_IRQHandler\ - PROC - EXPORT LPUART8_IRQHandler [WEAK] - LDR R0, =LPUART8_DriverIRQHandler - BX R0 - ENDP - -LPI2C1_IRQHandler\ - PROC - EXPORT LPI2C1_IRQHandler [WEAK] - LDR R0, =LPI2C1_DriverIRQHandler - BX R0 - ENDP - -LPI2C2_IRQHandler\ - PROC - EXPORT LPI2C2_IRQHandler [WEAK] - LDR R0, =LPI2C2_DriverIRQHandler - BX R0 - ENDP - -LPI2C3_IRQHandler\ - PROC - EXPORT LPI2C3_IRQHandler [WEAK] - LDR R0, =LPI2C3_DriverIRQHandler - BX R0 - ENDP - -LPI2C4_IRQHandler\ - PROC - EXPORT LPI2C4_IRQHandler [WEAK] - LDR R0, =LPI2C4_DriverIRQHandler - BX R0 - ENDP - -LPSPI1_IRQHandler\ - PROC - EXPORT LPSPI1_IRQHandler [WEAK] - LDR R0, =LPSPI1_DriverIRQHandler - BX R0 - ENDP - -LPSPI2_IRQHandler\ - PROC - EXPORT LPSPI2_IRQHandler [WEAK] - LDR R0, =LPSPI2_DriverIRQHandler - BX R0 - ENDP - -LPSPI3_IRQHandler\ - PROC - EXPORT LPSPI3_IRQHandler [WEAK] - LDR R0, =LPSPI3_DriverIRQHandler - BX R0 - ENDP - -LPSPI4_IRQHandler\ - PROC - EXPORT LPSPI4_IRQHandler [WEAK] - LDR R0, =LPSPI4_DriverIRQHandler - BX R0 - ENDP - -CAN1_IRQHandler\ - PROC - EXPORT CAN1_IRQHandler [WEAK] - LDR R0, =CAN1_DriverIRQHandler - BX R0 - ENDP - -CAN2_IRQHandler\ - PROC - EXPORT CAN2_IRQHandler [WEAK] - LDR R0, =CAN2_DriverIRQHandler - BX R0 - ENDP - -SAI1_IRQHandler\ - PROC - EXPORT SAI1_IRQHandler [WEAK] - LDR R0, =SAI1_DriverIRQHandler - BX R0 - ENDP - -SAI2_IRQHandler\ - PROC - EXPORT SAI2_IRQHandler [WEAK] - LDR R0, =SAI2_DriverIRQHandler - BX R0 - ENDP - -SAI3_RX_IRQHandler\ - PROC - EXPORT SAI3_RX_IRQHandler [WEAK] - LDR R0, =SAI3_RX_DriverIRQHandler - BX R0 - ENDP - -SAI3_TX_IRQHandler\ - PROC - EXPORT SAI3_TX_IRQHandler [WEAK] - LDR R0, =SAI3_TX_DriverIRQHandler - BX R0 - ENDP - -SPDIF_IRQHandler\ - PROC - EXPORT SPDIF_IRQHandler [WEAK] - LDR R0, =SPDIF_DriverIRQHandler - BX R0 - ENDP - -FLEXIO1_IRQHandler\ - PROC - EXPORT FLEXIO1_IRQHandler [WEAK] - LDR R0, =FLEXIO1_DriverIRQHandler - BX R0 - ENDP - -FLEXIO2_IRQHandler\ - PROC - EXPORT FLEXIO2_IRQHandler [WEAK] - LDR R0, =FLEXIO2_DriverIRQHandler - BX R0 - ENDP - -FLEXSPI_IRQHandler\ - PROC - EXPORT FLEXSPI_IRQHandler [WEAK] - LDR R0, =FLEXSPI_DriverIRQHandler - BX R0 - ENDP - -USDHC1_IRQHandler\ - PROC - EXPORT USDHC1_IRQHandler [WEAK] - LDR R0, =USDHC1_DriverIRQHandler - BX R0 - ENDP - -USDHC2_IRQHandler\ - PROC - EXPORT USDHC2_IRQHandler [WEAK] - LDR R0, =USDHC2_DriverIRQHandler - BX R0 - ENDP - -ENET_IRQHandler\ - PROC - EXPORT ENET_IRQHandler [WEAK] - LDR R0, =ENET_DriverIRQHandler - BX R0 - ENDP - -ENET_1588_Timer_IRQHandler\ - PROC - EXPORT ENET_1588_Timer_IRQHandler [WEAK] - LDR R0, =ENET_1588_Timer_DriverIRQHandler - BX R0 - ENDP - -Default_Handler\ - PROC - EXPORT DMA0_DMA16_DriverIRQHandler [WEAK] - EXPORT DMA1_DMA17_DriverIRQHandler [WEAK] - EXPORT DMA2_DMA18_DriverIRQHandler [WEAK] - EXPORT DMA3_DMA19_DriverIRQHandler [WEAK] - EXPORT DMA4_DMA20_DriverIRQHandler [WEAK] - EXPORT DMA5_DMA21_DriverIRQHandler [WEAK] - EXPORT DMA6_DMA22_DriverIRQHandler [WEAK] - EXPORT DMA7_DMA23_DriverIRQHandler [WEAK] - EXPORT DMA8_DMA24_DriverIRQHandler [WEAK] - EXPORT DMA9_DMA25_DriverIRQHandler [WEAK] - EXPORT DMA10_DMA26_DriverIRQHandler [WEAK] - EXPORT DMA11_DMA27_DriverIRQHandler [WEAK] - EXPORT DMA12_DMA28_DriverIRQHandler [WEAK] - EXPORT DMA13_DMA29_DriverIRQHandler [WEAK] - EXPORT DMA14_DMA30_DriverIRQHandler [WEAK] - EXPORT DMA15_DMA31_DriverIRQHandler [WEAK] - EXPORT DMA_ERROR_DriverIRQHandler [WEAK] - EXPORT CTI0_ERROR_IRQHandler [WEAK] - EXPORT CTI1_ERROR_IRQHandler [WEAK] - EXPORT CORE_IRQHandler [WEAK] - EXPORT LPUART1_DriverIRQHandler [WEAK] - EXPORT LPUART2_DriverIRQHandler [WEAK] - EXPORT LPUART3_DriverIRQHandler [WEAK] - EXPORT LPUART4_DriverIRQHandler [WEAK] - EXPORT LPUART5_DriverIRQHandler [WEAK] - EXPORT LPUART6_DriverIRQHandler [WEAK] - EXPORT LPUART7_DriverIRQHandler [WEAK] - EXPORT LPUART8_DriverIRQHandler [WEAK] - EXPORT LPI2C1_DriverIRQHandler [WEAK] - EXPORT LPI2C2_DriverIRQHandler [WEAK] - EXPORT LPI2C3_DriverIRQHandler [WEAK] - EXPORT LPI2C4_DriverIRQHandler [WEAK] - EXPORT LPSPI1_DriverIRQHandler [WEAK] - EXPORT LPSPI2_DriverIRQHandler [WEAK] - EXPORT LPSPI3_DriverIRQHandler [WEAK] - EXPORT LPSPI4_DriverIRQHandler [WEAK] - EXPORT CAN1_DriverIRQHandler [WEAK] - EXPORT CAN2_DriverIRQHandler [WEAK] - EXPORT FLEXRAM_IRQHandler [WEAK] - EXPORT KPP_IRQHandler [WEAK] - EXPORT TSC_DIG_IRQHandler [WEAK] - EXPORT GPR_IRQ_IRQHandler [WEAK] - EXPORT LCDIF_IRQHandler [WEAK] - EXPORT CSI_IRQHandler [WEAK] - EXPORT PXP_IRQHandler [WEAK] - EXPORT WDOG2_IRQHandler [WEAK] - EXPORT SNVS_HP_WRAPPER_IRQHandler [WEAK] - EXPORT SNVS_HP_WRAPPER_TZ_IRQHandler [WEAK] - EXPORT SNVS_LP_WRAPPER_IRQHandler [WEAK] - EXPORT CSU_IRQHandler [WEAK] - EXPORT DCP_IRQHandler [WEAK] - EXPORT DCP_VMI_IRQHandler [WEAK] - EXPORT Reserved68_IRQHandler [WEAK] - EXPORT TRNG_IRQHandler [WEAK] - EXPORT SJC_IRQHandler [WEAK] - EXPORT BEE_IRQHandler [WEAK] - EXPORT SAI1_DriverIRQHandler [WEAK] - EXPORT SAI2_DriverIRQHandler [WEAK] - EXPORT SAI3_RX_DriverIRQHandler [WEAK] - EXPORT SAI3_TX_DriverIRQHandler [WEAK] - EXPORT SPDIF_DriverIRQHandler [WEAK] - EXPORT ANATOP_EVENT0_IRQHandler [WEAK] - EXPORT ANATOP_EVENT1_IRQHandler [WEAK] - EXPORT ANATOP_TAMP_LOW_HIGH_IRQHandler [WEAK] - EXPORT ANATOP_TEMP_PANIC_IRQHandler [WEAK] - EXPORT USB_PHY1_IRQHandler [WEAK] - EXPORT USB_PHY2_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT ADC2_IRQHandler [WEAK] - EXPORT DCDC_IRQHandler [WEAK] - EXPORT Reserved86_IRQHandler [WEAK] - EXPORT Reserved87_IRQHandler [WEAK] - EXPORT GPIO1_INT0_IRQHandler [WEAK] - EXPORT GPIO1_INT1_IRQHandler [WEAK] - EXPORT GPIO1_INT2_IRQHandler [WEAK] - EXPORT GPIO1_INT3_IRQHandler [WEAK] - EXPORT GPIO1_INT4_IRQHandler [WEAK] - EXPORT GPIO1_INT5_IRQHandler [WEAK] - EXPORT GPIO1_INT6_IRQHandler [WEAK] - EXPORT GPIO1_INT7_IRQHandler [WEAK] - EXPORT GPIO1_Combined_0_15_IRQHandler [WEAK] - EXPORT GPIO1_Combined_16_31_IRQHandler [WEAK] - EXPORT GPIO2_Combined_0_15_IRQHandler [WEAK] - EXPORT GPIO2_Combined_16_31_IRQHandler [WEAK] - EXPORT GPIO3_Combined_0_15_IRQHandler [WEAK] - EXPORT GPIO3_Combined_16_31_IRQHandler [WEAK] - EXPORT GPIO4_Combined_0_15_IRQHandler [WEAK] - EXPORT GPIO4_Combined_16_31_IRQHandler [WEAK] - EXPORT GPIO5_Combined_0_15_IRQHandler [WEAK] - EXPORT GPIO5_Combined_16_31_IRQHandler [WEAK] - EXPORT FLEXIO1_DriverIRQHandler [WEAK] - EXPORT FLEXIO2_DriverIRQHandler [WEAK] - EXPORT WDOG1_IRQHandler [WEAK] - EXPORT RTWDOG_IRQHandler [WEAK] - EXPORT EWM_IRQHandler [WEAK] - EXPORT CCM_1_IRQHandler [WEAK] - EXPORT CCM_2_IRQHandler [WEAK] - EXPORT GPC_IRQHandler [WEAK] - EXPORT SRC_IRQHandler [WEAK] - EXPORT Reserved115_IRQHandler [WEAK] - EXPORT GPT1_IRQHandler [WEAK] - EXPORT GPT2_IRQHandler [WEAK] - EXPORT PWM1_0_IRQHandler [WEAK] - EXPORT PWM1_1_IRQHandler [WEAK] - EXPORT PWM1_2_IRQHandler [WEAK] - EXPORT PWM1_3_IRQHandler [WEAK] - EXPORT PWM1_FAULT_IRQHandler [WEAK] - EXPORT Reserved123_IRQHandler [WEAK] - EXPORT FLEXSPI_DriverIRQHandler [WEAK] - EXPORT SEMC_IRQHandler [WEAK] - EXPORT USDHC1_DriverIRQHandler [WEAK] - EXPORT USDHC2_DriverIRQHandler [WEAK] - EXPORT USB_OTG2_IRQHandler [WEAK] - EXPORT USB_OTG1_IRQHandler [WEAK] - EXPORT ENET_DriverIRQHandler [WEAK] - EXPORT ENET_1588_Timer_DriverIRQHandler [WEAK] - EXPORT XBAR1_IRQ_0_1_IRQHandler [WEAK] - EXPORT XBAR1_IRQ_2_3_IRQHandler [WEAK] - EXPORT ADC_ETC_IRQ0_IRQHandler [WEAK] - EXPORT ADC_ETC_IRQ1_IRQHandler [WEAK] - EXPORT ADC_ETC_IRQ2_IRQHandler [WEAK] - EXPORT ADC_ETC_ERROR_IRQ_IRQHandler [WEAK] - EXPORT PIT_IRQHandler [WEAK] - EXPORT ACMP1_IRQHandler [WEAK] - EXPORT ACMP2_IRQHandler [WEAK] - EXPORT ACMP3_IRQHandler [WEAK] - EXPORT ACMP4_IRQHandler [WEAK] - EXPORT Reserved143_IRQHandler [WEAK] - EXPORT Reserved144_IRQHandler [WEAK] - EXPORT ENC1_IRQHandler [WEAK] - EXPORT ENC2_IRQHandler [WEAK] - EXPORT ENC3_IRQHandler [WEAK] - EXPORT ENC4_IRQHandler [WEAK] - EXPORT TMR1_IRQHandler [WEAK] - EXPORT TMR2_IRQHandler [WEAK] - EXPORT TMR3_IRQHandler [WEAK] - EXPORT TMR4_IRQHandler [WEAK] - EXPORT PWM2_0_IRQHandler [WEAK] - EXPORT PWM2_1_IRQHandler [WEAK] - EXPORT PWM2_2_IRQHandler [WEAK] - EXPORT PWM2_3_IRQHandler [WEAK] - EXPORT PWM2_FAULT_IRQHandler [WEAK] - EXPORT PWM3_0_IRQHandler [WEAK] - EXPORT PWM3_1_IRQHandler [WEAK] - EXPORT PWM3_2_IRQHandler [WEAK] - EXPORT PWM3_3_IRQHandler [WEAK] - EXPORT PWM3_FAULT_IRQHandler [WEAK] - EXPORT PWM4_0_IRQHandler [WEAK] - EXPORT PWM4_1_IRQHandler [WEAK] - EXPORT PWM4_2_IRQHandler [WEAK] - EXPORT PWM4_3_IRQHandler [WEAK] - EXPORT PWM4_FAULT_IRQHandler [WEAK] - EXPORT Reserved168_IRQHandler [WEAK] - EXPORT Reserved169_IRQHandler [WEAK] - EXPORT Reserved170_IRQHandler [WEAK] - EXPORT Reserved171_IRQHandler [WEAK] - EXPORT Reserved172_IRQHandler [WEAK] - EXPORT Reserved173_IRQHandler [WEAK] - EXPORT SJC_ARM_DEBUG_IRQHandler [WEAK] - EXPORT NMI_WAKEUP_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] -DMA0_DMA16_DriverIRQHandler -DMA1_DMA17_DriverIRQHandler -DMA2_DMA18_DriverIRQHandler -DMA3_DMA19_DriverIRQHandler -DMA4_DMA20_DriverIRQHandler -DMA5_DMA21_DriverIRQHandler -DMA6_DMA22_DriverIRQHandler -DMA7_DMA23_DriverIRQHandler -DMA8_DMA24_DriverIRQHandler -DMA9_DMA25_DriverIRQHandler -DMA10_DMA26_DriverIRQHandler -DMA11_DMA27_DriverIRQHandler -DMA12_DMA28_DriverIRQHandler -DMA13_DMA29_DriverIRQHandler -DMA14_DMA30_DriverIRQHandler -DMA15_DMA31_DriverIRQHandler -DMA_ERROR_DriverIRQHandler -CTI0_ERROR_IRQHandler -CTI1_ERROR_IRQHandler -CORE_IRQHandler -LPUART1_DriverIRQHandler -LPUART2_DriverIRQHandler -LPUART3_DriverIRQHandler -LPUART4_DriverIRQHandler -LPUART5_DriverIRQHandler -LPUART6_DriverIRQHandler -LPUART7_DriverIRQHandler -LPUART8_DriverIRQHandler -LPI2C1_DriverIRQHandler -LPI2C2_DriverIRQHandler -LPI2C3_DriverIRQHandler -LPI2C4_DriverIRQHandler -LPSPI1_DriverIRQHandler -LPSPI2_DriverIRQHandler -LPSPI3_DriverIRQHandler -LPSPI4_DriverIRQHandler -CAN1_DriverIRQHandler -CAN2_DriverIRQHandler -FLEXRAM_IRQHandler -KPP_IRQHandler -TSC_DIG_IRQHandler -GPR_IRQ_IRQHandler -LCDIF_IRQHandler -CSI_IRQHandler -PXP_IRQHandler -WDOG2_IRQHandler -SNVS_HP_WRAPPER_IRQHandler -SNVS_HP_WRAPPER_TZ_IRQHandler -SNVS_LP_WRAPPER_IRQHandler -CSU_IRQHandler -DCP_IRQHandler -DCP_VMI_IRQHandler -Reserved68_IRQHandler -TRNG_IRQHandler -SJC_IRQHandler -BEE_IRQHandler -SAI1_DriverIRQHandler -SAI2_DriverIRQHandler -SAI3_RX_DriverIRQHandler -SAI3_TX_DriverIRQHandler -SPDIF_DriverIRQHandler -ANATOP_EVENT0_IRQHandler -ANATOP_EVENT1_IRQHandler -ANATOP_TAMP_LOW_HIGH_IRQHandler -ANATOP_TEMP_PANIC_IRQHandler -USB_PHY1_IRQHandler -USB_PHY2_IRQHandler -ADC1_IRQHandler -ADC2_IRQHandler -DCDC_IRQHandler -Reserved86_IRQHandler -Reserved87_IRQHandler -GPIO1_INT0_IRQHandler -GPIO1_INT1_IRQHandler -GPIO1_INT2_IRQHandler -GPIO1_INT3_IRQHandler -GPIO1_INT4_IRQHandler -GPIO1_INT5_IRQHandler -GPIO1_INT6_IRQHandler -GPIO1_INT7_IRQHandler -GPIO1_Combined_0_15_IRQHandler -GPIO1_Combined_16_31_IRQHandler -GPIO2_Combined_0_15_IRQHandler -GPIO2_Combined_16_31_IRQHandler -GPIO3_Combined_0_15_IRQHandler -GPIO3_Combined_16_31_IRQHandler -GPIO4_Combined_0_15_IRQHandler -GPIO4_Combined_16_31_IRQHandler -GPIO5_Combined_0_15_IRQHandler -GPIO5_Combined_16_31_IRQHandler -FLEXIO1_DriverIRQHandler -FLEXIO2_DriverIRQHandler -WDOG1_IRQHandler -RTWDOG_IRQHandler -EWM_IRQHandler -CCM_1_IRQHandler -CCM_2_IRQHandler -GPC_IRQHandler -SRC_IRQHandler -Reserved115_IRQHandler -GPT1_IRQHandler -GPT2_IRQHandler -PWM1_0_IRQHandler -PWM1_1_IRQHandler -PWM1_2_IRQHandler -PWM1_3_IRQHandler -PWM1_FAULT_IRQHandler -Reserved123_IRQHandler -FLEXSPI_DriverIRQHandler -SEMC_IRQHandler -USDHC1_DriverIRQHandler -USDHC2_DriverIRQHandler -USB_OTG2_IRQHandler -USB_OTG1_IRQHandler -ENET_DriverIRQHandler -ENET_1588_Timer_DriverIRQHandler -XBAR1_IRQ_0_1_IRQHandler -XBAR1_IRQ_2_3_IRQHandler -ADC_ETC_IRQ0_IRQHandler -ADC_ETC_IRQ1_IRQHandler -ADC_ETC_IRQ2_IRQHandler -ADC_ETC_ERROR_IRQ_IRQHandler -PIT_IRQHandler -ACMP1_IRQHandler -ACMP2_IRQHandler -ACMP3_IRQHandler -ACMP4_IRQHandler -Reserved143_IRQHandler -Reserved144_IRQHandler -ENC1_IRQHandler -ENC2_IRQHandler -ENC3_IRQHandler -ENC4_IRQHandler -TMR1_IRQHandler -TMR2_IRQHandler -TMR3_IRQHandler -TMR4_IRQHandler -PWM2_0_IRQHandler -PWM2_1_IRQHandler -PWM2_2_IRQHandler -PWM2_3_IRQHandler -PWM2_FAULT_IRQHandler -PWM3_0_IRQHandler -PWM3_1_IRQHandler -PWM3_2_IRQHandler -PWM3_3_IRQHandler -PWM3_FAULT_IRQHandler -PWM4_0_IRQHandler -PWM4_1_IRQHandler -PWM4_2_IRQHandler -PWM4_3_IRQHandler -PWM4_FAULT_IRQHandler -Reserved168_IRQHandler -Reserved169_IRQHandler -Reserved170_IRQHandler -Reserved171_IRQHandler -Reserved172_IRQHandler -Reserved173_IRQHandler -SJC_ARM_DEBUG_IRQHandler -NMI_WAKEUP_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - ENDP - ALIGN - - - END diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.c deleted file mode 100644 index d3cdb6f645..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_adc.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for ADC module. - * - * @param base ADC peripheral base address - */ -static uint32_t ADC_GetInstance(ADC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to ADC bases for each instance. */ -static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS; - -/*! @brief Pointers to ADC clocks for each instance. */ -static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t ADC_GetInstance(ADC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++) - { - if (s_adcBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_adcBases)); - - return instance; -} - -void ADC_Init(ADC_Type *base, const adc_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32; - - /* Enable the clock. */ - CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]); - /* ADCx_CFG */ - tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */ - tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) | - ADC_CFG_ADICLK(config->clockSource) | ADC_CFG_ADIV(config->clockDriver) | ADC_CFG_MODE(config->resolution); - if (config->enableOverWrite) - { - tmp32 |= ADC_CFG_OVWREN_MASK; - } - if (config->enableLongSample) - { - tmp32 |= ADC_CFG_ADLSMP_MASK; - } - if (config->enableLowPower) - { - tmp32 |= ADC_CFG_ADLPC_MASK; - } - if (config->enableHighSpeed) - { - tmp32 |= ADC_CFG_ADHSC_MASK; - } - base->CFG = tmp32; - - /* ADCx_GC */ - tmp32 = base->GC & ~(ADC_GC_ADCO_MASK | ADC_GC_ADACKEN_MASK); - if (config->enableContinuousConversion) - { - tmp32 |= ADC_GC_ADCO_MASK; - } - if (config->enableAsynchronousClockOutput) - { - tmp32 |= ADC_GC_ADACKEN_MASK; - } - base->GC = tmp32; -} - -void ADC_Deinit(ADC_Type *base) -{ - /* Disable the clock. */ - CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]); -} - -void ADC_GetDefaultConfig(adc_config_t *config) -{ - assert(NULL != config); - - config->enableAsynchronousClockOutput = true; - config->enableOverWrite = false; - config->enableContinuousConversion = false; - config->enableHighSpeed = false; - config->enableLowPower = false; - config->enableLongSample = false; - config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0; - config->samplePeriodMode = kADC_SamplePeriod2or12Clocks; - config->clockSource = kADC_ClockSourceAD; - config->clockDriver = kADC_ClockDriver1; - config->resolution = kADC_Resolution12Bit; -} - -void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config) -{ - assert(NULL != config); - assert(channelGroup < ADC_HC_COUNT); - - uint32_t tmp32; - - tmp32 = ADC_HC_ADCH(config->channelNumber); - if (config->enableInterruptOnConversionCompleted) - { - tmp32 |= ADC_HC_AIEN_MASK; - } - base->HC[channelGroup] = tmp32; -} - -/* - *To complete calibration, the user must follow the below procedure: - * 1. Configure ADC_CFG with actual operating values for maximum accuracy. - * 2. Configure the ADC_GC values along with CAL bit. - * 3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC. - * 4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status. - */ -status_t ADC_DoAutoCalibration(ADC_Type *base) -{ - status_t status = kStatus_Success; -#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) - bool bHWTrigger = false; - - /* The calibration would be failed when in hardwar mode. - * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/ - if (0U != (ADC_CFG_ADTRG_MASK & base->CFG)) - { - bHWTrigger = true; - ADC_EnableHardwareTrigger(base, false); - } -#endif - - /* Clear the CALF and launch the calibration. */ - base->GS = ADC_GS_CALF_MASK; /* Clear the CALF. */ - base->GC |= ADC_GC_CAL_MASK; /* Launch the calibration. */ - - /* Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC. */ - while (0U != (base->GC & ADC_GC_CAL_MASK)) - { - /* Check the CALF when the calibration is active. */ - if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag)) - { - status = kStatus_Fail; - break; - } - } - - /* When CAL bit becomes '0' then check the CALF status and COCO[0] bit status. */ - if (0U == ADC_GetChannelStatusFlags(base, 0U)) /* Check the COCO[0] bit status. */ - { - status = kStatus_Fail; - } - if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag)) /* Check the CALF status. */ - { - status = kStatus_Fail; - } - - /* Clear conversion done flag. */ - ADC_GetChannelConversionValue(base, 0U); - -#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) - /* Restore original trigger mode. */ - if (true == bHWTrigger) - { - ADC_EnableHardwareTrigger(base, true); - } -#endif - - return status; -} - -void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32; - - tmp32 = ADC_OFS_OFS(config->offsetValue); - if (config->enableSigned) - { - tmp32 |= ADC_OFS_SIGN_MASK; - } - base->OFS = tmp32; -} - -void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config) -{ - uint32_t tmp32; - - tmp32 = base->GC & ~(ADC_GC_ACFE_MASK | ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK); - if (NULL == config) /* Pass "NULL" to disable the feature. */ - { - base->GC = tmp32; - return; - } - /* Enable the feature. */ - tmp32 |= ADC_GC_ACFE_MASK; - - /* Select the hardware compare working mode. */ - switch (config->hardwareCompareMode) - { - case kADC_HardwareCompareMode0: - break; - case kADC_HardwareCompareMode1: - tmp32 |= ADC_GC_ACFGT_MASK; - break; - case kADC_HardwareCompareMode2: - tmp32 |= ADC_GC_ACREN_MASK; - break; - case kADC_HardwareCompareMode3: - tmp32 |= ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK; - break; - default: - break; - } - base->GC = tmp32; - - /* Load the compare values. */ - tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2); - base->CV = tmp32; -} - -void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode) -{ - uint32_t tmp32; - - if (mode == kADC_HardwareAverageDiasable) - { - base->GC &= ~ADC_GC_AVGE_MASK; - } - else - { - tmp32 = base->CFG & ~ADC_CFG_AVGS_MASK; - tmp32 |= ADC_CFG_AVGS(mode); - base->CFG = tmp32; - base->GC |= ADC_GC_AVGE_MASK; /* Enable the hardware compare. */ - } -} - -void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) -{ - uint32_t tmp32 = 0; - - if (0U != (mask & kADC_CalibrationFailedFlag)) - { - tmp32 |= ADC_GS_CALF_MASK; - } - if (0U != (mask & kADC_ConversionActiveFlag)) - { - tmp32 |= ADC_GS_ADACT_MASK; - } - base->GS = tmp32; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.h deleted file mode 100644 index 8b46fb1ba5..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.h +++ /dev/null @@ -1,446 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_ADC_H_ -#define _FSL_ADC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup adc_12b1msps_sar - * @{ - */ - -/******************************************************************************* -* Definitions -******************************************************************************/ -/*! @brief ADC driver version */ -#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - -/*! - * @brief Converter's status flags. - */ -typedef enum _adc_status_flags -{ - kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */ - kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */ - kADC_AsynchronousWakeupInterruptFlag = - ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occured, support w1c. */ -} adc_status_flags_t; - -/*! - * @brief Reference voltage source. - */ -typedef enum _adc_reference_voltage_source -{ - kADC_ReferenceVoltageSourceAlt0 = 0U, /*!< For external pins pair of VrefH and VrefL. */ -} adc_reference_voltage_source_t; - -/*! - * @brief Sample time duration. - */ -typedef enum _adc_sample_period_mode -{ - /* This group of enumeration is for internal use which is related to register setting. */ - kADC_SamplePeriod2or12Clocks = 0U, /*!< Long sample 12 clocks or short sample 2 clocks. */ - kADC_SamplePeriod4or16Clocks = 1U, /*!< Long sample 16 clocks or short sample 4 clocks. */ - kADC_SamplePeriod6or20Clocks = 2U, /*!< Long sample 20 clocks or short sample 6 clocks. */ - kADC_SamplePeriod8or24Clocks = 3U, /*!< Long sample 24 clocks or short sample 8 clocks. */ - /* This group of enumeration is for a public user. */ - /* For long sample mode. */ - kADC_SamplePeriodLong12Clcoks = kADC_SamplePeriod2or12Clocks, /*!< Long sample 12 clocks. */ - kADC_SamplePeriodLong16Clcoks = kADC_SamplePeriod4or16Clocks, /*!< Long sample 16 clocks. */ - kADC_SamplePeriodLong20Clcoks = kADC_SamplePeriod6or20Clocks, /*!< Long sample 20 clocks. */ - kADC_SamplePeriodLong24Clcoks = kADC_SamplePeriod8or24Clocks, /*!< Long sample 24 clocks. */ - /* For short sample mode. */ - kADC_SamplePeriodShort2Clocks = kADC_SamplePeriod2or12Clocks, /*!< Short sample 2 clocks. */ - kADC_SamplePeriodShort4Clocks = kADC_SamplePeriod4or16Clocks, /*!< Short sample 4 clocks. */ - kADC_SamplePeriodShort6Clocks = kADC_SamplePeriod6or20Clocks, /*!< Short sample 6 clocks. */ - kADC_SamplePeriodShort8Clocks = kADC_SamplePeriod8or24Clocks, /*!< Short sample 8 clocks. */ -} adc_sample_period_mode_t; - -/*! - * @brief Clock source. - */ -typedef enum _adc_clock_source -{ - kADC_ClockSourceIPG = 0U, /*!< Select IPG clock to generate ADCK. */ - kADC_ClockSourceIPGDiv2 = 1U, /*!< Select IPG clock divided by 2 to generate ADCK. */ -#if !(defined(FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) && FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) - kADC_ClockSourceALT = 2U, /*!< Select alternate clock to generate ADCK. */ -#endif - kADC_ClockSourceAD = 3U, /*!< Select Asynchronous clock to generate ADCK. */ -} adc_clock_source_t; - -/*! - * @brief Clock divider for the converter. - */ -typedef enum _adc_clock_drvier -{ - kADC_ClockDriver1 = 0U, /*!< For divider 1 from the input clock to the module. */ - kADC_ClockDriver2 = 1U, /*!< For divider 2 from the input clock to the module. */ - kADC_ClockDriver4 = 2U, /*!< For divider 4 from the input clock to the module. */ - kADC_ClockDriver8 = 3U, /*!< For divider 8 from the input clock to the module. */ -} adc_clock_driver_t; - -/*! - * @brief Converter's resolution. - */ -typedef enum _adc_resolution -{ - kADC_Resolution8Bit = 0U, /*!< Single End 8-bit resolution. */ - kADC_Resolution10Bit = 1U, /*!< Single End 10-bit resolution. */ - kADC_Resolution12Bit = 2U, /*!< Single End 12-bit resolution. */ -} adc_resolution_t; - -/*! - * @brief Converter hardware compare mode. - */ -typedef enum _adc_hardware_compare_mode -{ - kADC_HardwareCompareMode0 = 0U, /*!< Compare true if the result is less than the value1. */ - kADC_HardwareCompareMode1 = 1U, /*!< Compare true if the result is greater than or equal to value1. */ - kADC_HardwareCompareMode2 = 2U, /*!< Value1 <= Value2, compare true if the result is less than value1 Or - the result is Greater than value2. - Value1 > Value2, compare true if the result is less than value1 And the - result is greater than value2*/ - kADC_HardwareCompareMode3 = 3U, /*!< Value1 <= Value2, compare true if the result is greater than or equal - to value1 And the result is less than or equal to value2. - Value1 > Value2, compare true if the result is greater than or equal to - value1 Or the result is less than or equal to value2. */ -} adc_hardware_compare_mode_t; - -/*! - * @brief Converter hardware average mode. - */ -typedef enum _adc_hardware_average_mode -{ - kADC_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */ - kADC_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */ - kADC_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */ - kADC_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */ - kADC_HardwareAverageDiasable = 4U, /*!< Disable the hardware average function. */ -} adc_hardware_average_mode_t; - -/*! - * @brief Converter configuration. - */ -typedef struct _adc_config -{ - bool enableOverWrite; /*!< Enable the overwriting. */ - bool enableContinuousConversion; /*!< Enable the continuous conversion mode. */ - bool enableHighSpeed; /*!< Enable the high-speed mode. */ - bool enableLowPower; /*!< Enable the low power mode. */ - bool enableLongSample; /*!< Enable the long sample mode. */ - bool enableAsynchronousClockOutput; /*!< Enable the asynchronous clock output. */ - adc_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ - adc_sample_period_mode_t samplePeriodMode; /*!< Select the sample period in long sample mode or short mode. */ - adc_clock_source_t clockSource; /*!< Select the input clock source to generate the internal clock ADCK. */ - adc_clock_driver_t clockDriver; /*!< Select the divide ratio used by the ADC to generate the internal clock ADCK. */ - adc_resolution_t resolution; /*!< Select the ADC resolution mode. */ -} adc_config_t; - -/*! - * @brief Converter Offset configuration. - */ -typedef struct _adc_offest_config -{ - bool enableSigned; /*!< if false,The offset value is added with the raw result. - if true,The offset value is subtracted from the raw converted value. */ - uint32_t offsetValue; /*!< User configurable offset value(0-4095). */ -} adc_offest_config_t; - -/*! - * @brief ADC hardware compare configuration. - * - * In kADC_HardwareCompareMode0, compare true if the result is less than the value1. - * In kADC_HardwareCompareMode1, compare true if the result is greater than or equal to value1. - * In kADC_HardwareCompareMode2, Value1 <= Value2, compare true if the result is less than value1 Or the result is - * Greater than value2. - * Value1 > Value2, compare true if the result is less than value1 And the result is - * Greater than value2. - * In kADC_HardwareCompareMode3, Value1 <= Value2, compare true if the result is greater than or equal to value1 And the - * result is less than or equal to value2. - * Value1 > Value2, compare true if the result is greater than or equal to value1 Or the - * result is less than or equal to value2. - */ -typedef struct _adc_hardware_compare_config -{ - adc_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode. - See "adc_hardware_compare_mode_t". */ - uint16_t value1; /*!< Setting value1(0-4095) for hardware compare mode. */ - uint16_t value2; /*!< Setting value2(0-4095) for hardware compare mode. */ -} adc_hardware_compare_config_t; - -/*! - * @brief ADC channel conversion configuration. - */ -typedef struct _adc_channel_config -{ - uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31. - See channel connection information for each chip in Reference - Manual document. */ - bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */ -} adc_channel_config_t; -/******************************************************************************* -* API -******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initialize the ADC module. - * - * @param base ADC peripheral base address. - * @param config Pointer to "adc_config_t" structure. - */ -void ADC_Init(ADC_Type *base, const adc_config_t *config); - -/*! - * @brief De-initializes the ADC module. - * - * @param base ADC peripheral base address. - */ -void ADC_Deinit(ADC_Type *base); - -/*! - * @brief Gets an available pre-defined settings for the converter's configuration. - * - * This function initializes the converter configuration structure with available settings. The default values are: - * @code - * config->enableAsynchronousClockOutput = true; - * config->enableOverWrite = false; - * config->enableContinuousConversion = false; - * config->enableHighSpeed = false; - * config->enableLowPower = false; - * config->enableLongSample = false; - * config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0; - * config->samplePeriodMode = kADC_SamplePeriod2or12Clocks; - * config->clockSource = kADC_ClockSourceAD; - * config->clockDriver = kADC_ClockDriver1; - * config->resolution = kADC_Resolution12Bit; - * @endcode - * @param base ADC peripheral base address. - * @param config Pointer to the configuration structure. - */ -void ADC_GetDefaultConfig(adc_config_t *config); - -/*! - * @brief Configures the conversion channel. - * - * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API - * configures the channel while the external trigger source helps to trigger the conversion. - * - * Note that the "Channel Group" has a detailed description. - * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one - * group of status and control registers, one for each conversion. The channel group parameter indicates which group of - * registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B - * registers. The - * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of - * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and - * hardware - * trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for - * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual - * about the - * number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used - * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion. - * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and - * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a - * conversion aborts the current conversion. - * - * @param base ADC peripheral base address. - * @param channelGroup Channel group index. - * @param config Pointer to the "adc_channel_config_t" structure for the conversion channel. - */ -void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config); - -/*! - * @brief Gets the conversion value. - * - * @param base ADC peripheral base address. - * @param channelGroup Channel group index. - * - * @return Conversion value. - */ -static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup) -{ - assert(channelGroup < ADC_R_COUNT); - - return base->R[channelGroup]; -} - -/*! - * @brief Gets the status flags of channel. - * - * A conversion is completed when the result of the conversion is transferred into the data - * result registers. (provided the compare function & hardware averaging is disabled), this is - * indicated by the setting of COCOn. If hardware averaging is enabled, COCOn sets only, - * if the last of the selected number of conversions is complete. If the compare function is - * enabled, COCOn sets and conversion result data is transferred only if the compare - * condition is true. If both hardware averaging and compare functions are enabled, then - * COCOn sets only if the last of the selected number of conversions is complete and the - * compare condition is true. - * - * @param base ADC peripheral base address. - * @param channelGroup Channel group index. - * - * @return Status flags of channel.return 0 means COCO flag is 0,return 1 means COCOflag is 1. - */ -static inline uint32_t ADC_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup) -{ - assert(channelGroup < ADC_HC_COUNT); - - /* If flag is set,return 1,otherwise, return 0. */ - return (((base->HS) & (1U << channelGroup)) >> channelGroup); -} - -/*! - * @brief Automates the hardware calibration. - * - * This auto calibration helps to adjust the plus/minus side gain automatically. - * Execute the calibration before using the converter. Note that the software trigger should be used - * during calibration. - * - * @param base ADC peripheral base address. - * - * @return Execution status. - * @retval kStatus_Success Calibration is done successfully. - * @retval kStatus_Fail Calibration has failed. - */ -status_t ADC_DoAutoCalibration(ADC_Type *base); - -/*! - * @brief Set user defined offset. - * - * @param base ADC peripheral base address. - * @param config Pointer to "adc_offest_config_t" structure. - */ -void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config); - -/*! - * @brief Enables generating the DMA trigger when the conversion is complete. - * - * @param base ADC peripheral base address. - * @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled. - */ -static inline void ADC_EnableDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->GC |= ADC_GC_DMAEN_MASK; - } - else - { - base->GC &= ~ADC_GC_DMAEN_MASK; - } -} - -/*! - * @brief Enables the hardware trigger mode. - * - * @param base ADC peripheral base address. - * @param enable Switcher of the trigger mode. "true" means hardware tirgger mode,"false" means software mode. - */ -#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) -static inline void ADC_EnableHardwareTrigger(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= ADC_CFG_ADTRG_MASK; - } - else - { - base->CFG &= ~ADC_CFG_ADTRG_MASK; - } -} -#endif - -/*! - * @brief Configures the hardware compare mode. - * - * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the - * result - * in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate - * reference - * manual for more information. - * - * @param base ADC peripheral base address. - * @param Pointer to "adc_hardware_compare_config_t" structure. - * - */ -void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config); - -/*! - * @brief Configures the hardware average mode. - * - * The hardware average mode provides a way to process the conversion result automatically by using hardware. The - * multiple - * conversion results are accumulated and averaged internally making them easier to read. - * - * @param base ADC peripheral base address. - * @param mode Setting the hardware average mode. See "adc_hardware_average_mode_t". - */ -void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode); - -/*! - * @brief Gets the converter's status flags. - * - * @param base ADC peripheral base address. - * - * @return Flags' mask if indicated flags are asserted. See "adc_status_flags_t". - */ -static inline uint32_t ADC_GetStatusFlags(ADC_Type *base) -{ - return base->GS; -} - -/*! - * @brief Clears the converter's status falgs. - * - * @param base ADC peripheral base address. - * @param mask Mask value for the cleared flags. See "adc_status_flags_t". - */ -void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask); - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_ADC_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_adc_etc.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_adc_etc.c deleted file mode 100644 index f17dcc3ba7..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_adc_etc.c +++ /dev/null @@ -1,365 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_adc_etc.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.adc_etc" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -#if defined(ADC_ETC_CLOCKS) -/*! - * @brief Get instance number for ADC_ETC module. - * - * @param base ADC_ETC peripheral base address - */ -static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to ADC_ETC bases for each instance. */ -static ADC_ETC_Type *const s_adcetcBases[] = ADC_ETC_BASE_PTRS; - -/*! @brief Pointers to ADC_ETC clocks for each instance. */ -static const clock_ip_name_t s_adcetcClocks[] = ADC_ETC_CLOCKS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base) -{ - uint32_t instance = 0U; - uint32_t adcetcArrayCount = (sizeof(s_adcetcBases) / sizeof(s_adcetcBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < adcetcArrayCount; instance++) - { - if (s_adcetcBases[instance] == base) - { - break; - } - } - - return instance; -} -#endif /* ADC_ETC_CLOCKS */ - -void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(ADC_ETC_CLOCKS) - /* Open clock gate. */ - CLOCK_EnableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]); -#endif /* ADC_ETC_CLOCKS */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Disable software reset. */ - ADC_ETC_DoSoftwareReset(base, false); - - /* Set ADC_ETC_CTRL register. */ - tmp32 = ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(config->TSC0triggerPriority) | - ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(config->TSC1triggerPriority) | - ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask) -#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL - | ADC_ETC_CTRL_DMA_MODE_SEL(config->dmaMode) -#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ - ; - if (config->enableTSCBypass) - { - tmp32 |= ADC_ETC_CTRL_TSC_BYPASS_MASK; - } - if (config->enableTSC0Trigger) - { - tmp32 |= ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK; - } - if (config->enableTSC1Trigger) - { - tmp32 |= ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK; - } - base->CTRL = tmp32; -} - -void ADC_ETC_Deinit(ADC_ETC_Type *base) -{ - /* Do software reset to clear all logical. */ - ADC_ETC_DoSoftwareReset(base, true); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -#if defined(ADC_ETC_CLOCKS) - /* Close clock gate. */ - CLOCK_DisableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]); -#endif /* ADC_ETC_CLOCKS */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config) -{ - config->enableTSCBypass = true; - config->enableTSC0Trigger = false; - config->enableTSC1Trigger = false; -#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL - config->dmaMode = kADC_ETC_TrigDMAWithLatchedSignal; -#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ - config->TSC0triggerPriority = 0U; - config->TSC1triggerPriority = 0U; - config->clockPreDivider = 0U; - config->XBARtriggerMask = 0U; -} - -void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config) -{ - assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT); - assert(ADC_ETC_TRIGn_COUNTER_COUNT > triggerGroup); - - uint32_t tmp32; - - /* Set ADC_ETC_TRGn_CTRL register. */ - tmp32 = ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(config->triggerChainLength) | - ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(config->triggerPriority); - if (config->enableSyncMode) - { - tmp32 |= ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK; - } - if (config->enableSWTriggerMode) - { - tmp32 |= ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK; - } - base->TRIG[triggerGroup].TRIGn_CTRL = tmp32; - - /* Set ADC_ETC_TRGn_COUNTER register. */ - tmp32 = ADC_ETC_TRIGn_COUNTER_INIT_DELAY(config->initialDelay) | - ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(config->sampleIntervalDelay); - base->TRIG[triggerGroup].TRIGn_COUNTER = tmp32; -} - -void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base, - uint32_t triggerGroup, - uint32_t chainGroup, - const adc_etc_trigger_chain_config_t *config) -{ - assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT); - - uint32_t tmp; - uint32_t tmp32; - uint8_t mRemainder = chainGroup % 2U; - - /* Set ADC_ETC_TRIGn_CHAINm register. */ - tmp = ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(config->ADCHCRegisterSelect) | - ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(config->ADCChannelSelect) | - ADC_ETC_TRIGn_CHAIN_1_0_IE0(config->InterruptEnable); - if (config->enableB2BMode) - { - tmp |= ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK; - } - switch (chainGroup / 2U) - { - case 0U: /* Configurate trigger chain0 and chain 1. */ - tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_1_0; - if (mRemainder == 0U) /* Chain 0. */ - { - tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK | - ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK); - tmp32 |= tmp; - } - else /* Chain 1. */ - { - tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK | - ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK); - tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT); - } - base->TRIG[triggerGroup].TRIGn_CHAIN_1_0 = tmp32; - break; - case 1U: /* Configurate trigger chain2 and chain 3. */ - tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_3_2; - if (mRemainder == 0U) /* Chain 2. */ - { - tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK | - ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK); - tmp32 |= tmp; - } - else /* Chain 3. */ - { - tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK | - ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK); - tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT); - } - base->TRIG[triggerGroup].TRIGn_CHAIN_3_2 = tmp32; - break; - case 2U: /* Configurate trigger chain4 and chain 5. */ - tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_5_4; - if (mRemainder == 0U) /* Chain 4. */ - { - tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK | - ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK); - tmp32 |= tmp; - } - else /* Chain 5. */ - { - tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK | - ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK); - tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT); - } - base->TRIG[triggerGroup].TRIGn_CHAIN_5_4 = tmp32; - break; - case 3U: /* Configurate trigger chain6 and chain 7. */ - tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_7_6; - if (mRemainder == 0U) /* Chain 6. */ - { - tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK | - ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK); - tmp32 |= tmp; - } - else /* Chain 7. */ - { - tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK | - ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK); - tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT); - } - base->TRIG[triggerGroup].TRIGn_CHAIN_7_6 = tmp32; - break; - default: - break; - } -} - -uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex) -{ - uint32_t tmp32 = 0U; - - if (((base->DONE0_1_IRQ) & (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << sourceIndex)) != 0U) - { - tmp32 |= kADC_ETC_Done0StatusFlagMask; /* Customized DONE0 status flags mask, which is defined in fsl_adc_etc.h - file. */ - } - if (((base->DONE0_1_IRQ) & (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << sourceIndex)) != 0U) - { - tmp32 |= kADC_ETC_Done1StatusFlagMask; /* Customized DONE1 status flags mask, which is defined in fsl_adc_etc.h - file. */ - } - if (((base->DONE2_ERR_IRQ) & (ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK << sourceIndex)) != 0U) - { - tmp32 |= kADC_ETC_Done2StatusFlagMask; /* Customized DONE2 status flags mask, which is defined in fsl_adc_etc.h - file. */ - } - if (((base->DONE2_ERR_IRQ) & (ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK << sourceIndex)) != 0U) - { - tmp32 |= kADC_ETC_ErrorStatusFlagMask; /* Customized ERROR status flags mask, which is defined in fsl_adc_etc.h - file. */ - } - return tmp32; -} - -void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask) -{ - if (0U != (mask & kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */ - { - base->DONE0_1_IRQ = (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << sourceIndex); - } - if (0U != (mask & kADC_ETC_Done1StatusFlagMask)) /* Write 1 to clear DONE1 status flags. */ - { - base->DONE0_1_IRQ = (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << sourceIndex); - } - if (0U != (mask & kADC_ETC_Done2StatusFlagMask)) /* Write 1 to clear DONE2 status flags. */ - { - base->DONE2_ERR_IRQ = (ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK << sourceIndex); - } - if (0U != (mask & kADC_ETC_ErrorStatusFlagMask)) /* Write 1 to clear ERROR status flags. */ - { - base->DONE2_ERR_IRQ = (ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK << sourceIndex); - } -} - -uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup) -{ - assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT); - - uint32_t mADCResult; - uint8_t mRemainder = chainGroup % 2U; - - switch (chainGroup / 2U) - { - case 0U: - if (0U == mRemainder) - { - mADCResult = ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_1_0); - } - else - { - mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_1_0) >> ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT; - } - break; - case 1U: - if (0U == mRemainder) - { - mADCResult = ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_3_2); - } - else - { - mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_3_2) >> ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT; - } - break; - case 2U: - if (0U == mRemainder) - { - mADCResult = ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_5_4); - } - else - { - mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_5_4) >> ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT; - } - break; - case 3U: - if (0U == mRemainder) - { - mADCResult = ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_7_6); - } - else - { - mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_7_6) >> ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT; - } - break; - default: - return 0U; - } - return mADCResult; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_adc_etc.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_adc_etc.h deleted file mode 100644 index 06cb5675b0..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_adc_etc.h +++ /dev/null @@ -1,342 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_ADC_ETC_H_ -#define _FSL_ADC_ETC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup adc_etc - * @{ - */ - -/******************************************************************************* -* Definitions -******************************************************************************/ -/*! @brief ADC_ETC driver version */ -#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ -/*! @brief The mask of status flags cleared by writing 1. */ -#define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U - -/*! -* @brief ADC_ETC customized status flags mask. -*/ -enum _adc_etc_status_flag_mask -{ - kADC_ETC_Done0StatusFlagMask = 1U, - kADC_ETC_Done1StatusFlagMask = 2U, - kADC_ETC_Done2StatusFlagMask = 4U, - kADC_ETC_ErrorStatusFlagMask = 8U, -}; - -/*! -* @brief External triggers sources. -*/ -typedef enum _adc_etc_external_trigger_source -{ - /* External XBAR sources. Support HW or SW mode. */ - kADC_ETC_Trg0TriggerSource = 0U, /* External XBAR trigger0 source. */ - kADC_ETC_Trg1TriggerSource = 1U, /* External XBAR trigger1 source. */ - kADC_ETC_Trg2TriggerSource = 2U, /* External XBAR trigger2 source. */ - kADC_ETC_Trg3TriggerSource = 3U, /* External XBAR trigger3 source. */ - kADC_ETC_Trg4TriggerSource = 4U, /* External XBAR trigger4 source. */ - kADC_ETC_Trg5TriggerSource = 5U, /* External XBAR trigger5 source. */ - kADC_ETC_Trg6TriggerSource = 6U, /* External XBAR trigger6 source. */ - kADC_ETC_Trg7TriggerSource = 7U, /* External XBAR trigger7 source. */ - /* External TSC sources. Only support HW mode. */ - kADC_ETC_TSC0TriggerSource = 8U, /* External TSC trigger0 source. */ - kADC_ETC_TSC1TriggerSource = 9U, /* External TSC trigger1 source. */ -} adc_etc_external_trigger_source_t; - -/*! -* @brief Interrupt enable/disable mask. -*/ -typedef enum _adc_etc_interrupt_enable -{ - kADC_ETC_InterruptDisable = 0U, /* Disable the ADC_ETC interrupt. */ - kADC_ETC_Done0InterruptEnable = 1U, /* Enable the DONE0 interrupt when ADC conversions complete. */ - kADC_ETC_Done1InterruptEnable = 2U, /* Enable the DONE1 interrupt when ADC conversions complete. */ - kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */ -} adc_etc_interrupt_enable_t; - -#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL -/*! -* @brief DMA mode selection. -*/ -typedef enum _adc_etc_dma_mode_selection -{ - kADC_ETC_TrigDMAWithLatchedSignal = 0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */ - kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */ -} adc_etc_dma_mode_selection_t; -#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ - -/*! - * @brief ADC_ETC configuration. - */ -typedef struct _adc_etc_config -{ - bool enableTSCBypass; /* If bypass TSC, TSC would trigger ADC directly. - Otherwise TSC would trigger ADC through ADC_ETC. */ - bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */ - bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/ -#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL - adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */ -#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ - uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */ - uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */ - uint32_t clockPreDivider; /* Pre-divider for trig delay and interval. Available range is 0-255. - Clock would be divided by (clockPreDivider+1). */ - uint32_t XBARtriggerMask; /* Enable the corresponding trigger source. Available range is trigger0:0x01 to - trigger7:0x80 - For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is - enabled. */ -} adc_etc_config_t; - -/*! -* @brief ADC_ETC trigger chain configuration. -*/ -typedef struct _adc_etc_trigger_chain_config -{ - bool enableB2BMode; /* Enable ADC_ETC BackToBack mode. when not enabled B2B mode, - wait until interval delay is reached. */ - uint32_t ADCHCRegisterSelect; /* Select relevant ADC_HCx register to trigger. 1U : HC0, 2U: HC1, 4U: HC2 ... */ - uint32_t ADCChannelSelect; /* Select ADC sample channel. */ - adc_etc_interrupt_enable_t InterruptEnable; /* Enable/disable Interrupt. */ -} adc_etc_trigger_chain_config_t; - -/*! -* @brief ADC_ETC trigger configuration. -*/ -typedef struct _adc_etc_trigger_config -{ - bool enableSyncMode; /* Enable the sync Mode, In SyncMode ADC1 and ADC2 are controlled by the same trigger source. - In AsyncMode ADC1 and ADC2 are controlled by separate trigger source. */ - bool enableSWTriggerMode; /* Enable the sofware trigger mode. */ - uint32_t triggerChainLength; /* TRIG chain length to the ADC. 0: Trig length is 1. ... 7: Trig length is 8. */ - uint32_t triggerPriority; /* External trigger priority, 7 is highest, 0 is lowest. */ - uint32_t sampleIntervalDelay; /* Set sampling interval delay. */ - uint32_t initialDelay; /* Set trigger initial delay. */ -} adc_etc_trigger_config_t; - -/******************************************************************************* -* API -******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization - * @{ - */ - -/*! -* @brief Initialize the ADC_ETC module. -* -* @param base ADC_ETC peripheral base address. -* @param config Pointer to "adc_etc_config_t" structure. -*/ -void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config); - -/*! -* @brief De-Initialize the ADC_ETC module. -* -* @param base ADC_ETC peripheral base address. -*/ -void ADC_ETC_Deinit(ADC_ETC_Type *base); - -/*! -* @brief Gets an available pre-defined settings for the ADC_ETC's configuration. -* This function initializes the ADC_ETC's configuration structure with available settings. The default values are: -* @code -* config->enableTSCBypass = true; -* config->enableTSC0Trigger = false; -* config->enableTSC1Trigger = false; -* config->TSC0triggerPriority = 0U; -* config->TSC1triggerPriority = 0U; -* config->clockPreDivider = 0U; -* config->XBARtriggerMask = 0U; -* @endCode -* -* @param config Pointer to "adc_etc_config_t" structure. -*/ -void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config); - -/*! -* @brief Set the external XBAR trigger configuration. -* -* @param base ADC_ETC peripheral base address. -* @param triggerGroup Trigger group index. -* @param config Pointer to "adc_etc_trigger_config_t" structure. -*/ -void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config); - -/*! -* @brief Set the external XBAR trigger chain configuration. -* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be -* configurated. -* -* @param base ADC_ETC peripheral base address. -* @param triggerGroup Trigger group index. Available number is 0~7. -* @param chainGroup Trigger chain group index. Available number is 0~7. -* @param config Pointer to "adc_etc_trigger_chain_config_t" structure. -*/ -void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base, - uint32_t triggerGroup, - uint32_t chainGroup, - const adc_etc_trigger_chain_config_t *config); - -/*! -* @brief Gets the interrupt status flags of external XBAR and TSC triggers. -* -* @param base ADC_ETC peripheral base address. -* @param sourceIndex trigger source index. -* -* @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". -*/ -uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex); - -/*! -* @brief Clears the ADC_ETC's interrupt status falgs. -* -* @param base ADC_ETC peripheral base address. -* @param sourceIndex trigger source index. -* @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". -*/ -void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, - adc_etc_external_trigger_source_t sourceIndex, - uint32_t mask); - -/*! -* @brief Enable the DMA corresponding to each trigger source. -* -* @param base ADC_ETC peripheral base address. -* @param triggerGroup Trigger group index. Available number is 0~7. -*/ -static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup) -{ - /* Avoid clearing status flags at the same time. */ - base->DMA_CTRL = - (base->DMA_CTRL | (ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << triggerGroup)) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK; -} - -/*! -* @brief Disable the DMA corresponding to each trigger sources. -* -* @param base ADC_ETC peripheral base address. -* @param triggerGroup Trigger group index. Available number is 0~7. -*/ -static inline void ADC_ETC_DisableDMA(ADC_ETC_Type *base, uint32_t triggerGroup) -{ - /* Avoid clearing status flags at the same time. */ - base->DMA_CTRL = - (base->DMA_CTRL & ~(ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << triggerGroup)) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK; -} - -/*! - * @brief Get the DMA request status falgs. Only external XBAR sources support DMA request. - * - * @param base ADC_ETC peripheral base address. - * @return Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to - * trigger7:0x80. - */ -static inline uint32_t ADC_ETC_GetDMAStatusFlags(ADC_ETC_Type *base) -{ - return (((base->DMA_CTRL) & ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) >> ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT); -} - -/*! - * @brief Clear the DMA request status falgs. Only external XBAR sources support DMA request. - * - * @param base ADC_ETC peripheral base address. - * @param mask Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to - * trigger7:0x80. - */ -static inline void ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type *base, uint32_t mask) -{ - base->DMA_CTRL = ((base->DMA_CTRL) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) | (mask << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT); -} - -/*! -* @brief When enable ,all logical will be reset. -* -* @param base ADC_ETC peripheral base address. -* @param enable Enable/Disable the software reset. -*/ -static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_ETC_CTRL_SOFTRST_MASK; - } - else - { - base->CTRL &= ~ADC_ETC_CTRL_SOFTRST_MASK; - } -} - -/*! -* @brief Do software trigger corresponding to each XBAR trigger sources. -* Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode, -* trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources -* can only work in hardware trigger mode. -* -* @param base ADC_ETC peripheral base address. -* @param triggerGroup Trigger group index. Available number is 0~7. -*/ -static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t triggerGroup) -{ - assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT); - - base->TRIG[triggerGroup].TRIGn_CTRL |= ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK; -} - -/*! -* @brief Get ADC conversion result from external XBAR sources. -* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would -* return Trigger0 source's chain1 conversion result. -* -* @param base ADC_ETC peripheral base address. -* @param triggerGroup Trigger group index. Available number is 0~7. -* @param chainGroup Trigger chain group index. Available number is 0~7. -* @return ADC conversion result value. -*/ -uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup); - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_ADC_ETC_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_aipstz.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_aipstz.c deleted file mode 100644 index 91c091c75e..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_aipstz.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_aipstz.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.aipstz" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig) -{ - uint32_t mask = ((uint32_t)master >> 8) - 1; - uint32_t shift = (uint32_t)master & 0xFF; - base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift); -} - -void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl) -{ - volatile uint32_t *reg = (uint32_t *)((uint32_t)base + ((uint32_t)peripheral >> 16)); - uint32_t mask = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1; - uint32_t shift = (uint32_t)peripheral & 0xFF; - - *reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift); -} - - diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_aipstz.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_aipstz.h deleted file mode 100644 index 9d46f2e6a5..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_aipstz.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_AIPSTZ_H_ -#define _FSL_AIPSTZ_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup aipstz - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_AIPSTZ_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief List of AIPSTZ privilege configuration.*/ -typedef enum _aipstz_master_privilege_level { - kAIPSTZ_MasterBufferedWriteEnable = (1U << 3), /*!< Write accesses from this master are allowed to be buffered. */ - kAIPSTZ_MasterTrustedForReadEnable = (1U << 2), /*!< This master is trusted for read accesses. */ - kAIPSTZ_MasterTrustedForWriteEnable = (1U << 1), /*!< This master is trusted for write accesses. */ - kAIPSTZ_MasterForceUserModeEnable = 1U /*!< Accesses from this master are forced to user-mode. */ -} aipstz_master_privilege_level_t; - -/*! @brief List of AIPSTZ masters. Organized by width for the 8-15 bits and shift for lower 8 bits.*/ -typedef enum _aipstz_master { - kAIPSTZ_Master0 = (0x400U | 28U), - kAIPSTZ_Master1 = (0x400U | 24U), - kAIPSTZ_Master2 = (0x400U | 20U), - kAIPSTZ_Master3 = (0x400U | 16U), - kAIPSTZ_Master5 = (0x400U | 8U) -} aipstz_master_t; - -/*! @brief List of AIPSTZ peripheral access control configuration.*/ -typedef enum _aipstz_peripheral_access_control { - kAIPSTZ_PeripheralAllowUntrustedMaster = 1U, - kAIPSTZ_PeripheralWriteProtected = (1U << 1), - kAIPSTZ_PeripheralRequireSupervisor = (1U << 2), - kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3) -} aipstz_peripheral_access_control_t; - -/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and shift for lower 8 bits.*/ -typedef enum _aipstz_peripheral { - kAIPSTZ_Peripheral0 = ((0x40 << 16) | (4 << 8) | 28), - kAIPSTZ_Peripheral1 = ((0x40 << 16) | (4 << 8) | 24), - kAIPSTZ_Peripheral2 = ((0x40 << 16) | (4 << 8) | 20), - kAIPSTZ_Peripheral3 = ((0x40 << 16) | (4 << 8) | 16), - kAIPSTZ_Peripheral4 = ((0x40 << 16) | (4 << 8) | 12), - kAIPSTZ_Peripheral5 = ((0x40 << 16) | (4 << 8) | 8), - kAIPSTZ_Peripheral6 = ((0x40 << 16) | (4 << 8) | 4), - kAIPSTZ_Peripheral7 = ((0x40 << 16) | (4 << 8) | 0), - kAIPSTZ_Peripheral8 = ((0x44 << 16) | (4 << 8) | 28), - kAIPSTZ_Peripheral9 = ((0x44 << 16) | (4 << 8) | 24), - kAIPSTZ_Peripheral10 = ((0x44 << 16) | (4 << 8) | 20), - kAIPSTZ_Peripheral11 = ((0x44 << 16) | (4 << 8) | 16), - kAIPSTZ_Peripheral12 = ((0x44 << 16) | (4 << 8) | 12), - kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) | 8), - kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) | 4), - kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) | 0), - kAIPSTZ_Peripheral16 = ((0x48 << 16) | (4 << 8) | 28), - kAIPSTZ_Peripheral17 = ((0x48 << 16) | (4 << 8) | 24), - kAIPSTZ_Peripheral18 = ((0x48 << 16) | (4 << 8) | 20), - kAIPSTZ_Peripheral19 = ((0x48 << 16) | (4 << 8) | 16), - kAIPSTZ_Peripheral20 = ((0x48 << 16) | (4 << 8) | 12), - kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) | 8), - kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) | 4), - kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) | 0), - kAIPSTZ_Peripheral24 = ((0x4C << 16) | (4 << 8) | 28), - kAIPSTZ_Peripheral25 = ((0x4C << 16) | (4 << 8) | 24), - kAIPSTZ_Peripheral26 = ((0x4C << 16) | (4 << 8) | 20), - kAIPSTZ_Peripheral27 = ((0x4C << 16) | (4 << 8) | 16), - kAIPSTZ_Peripheral28 = ((0x4C << 16) | (4 << 8) | 12), - kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) | 8), - kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) | 4), - kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) | 0), - kAIPSTZ_Peripheral32 = ((0x50 << 16) | (4 << 8) | 28), - kAIPSTZ_Peripheral33 = ((0x50 << 16) | (4 << 8) | 24) -} aipstz_peripheral_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Configure the privilege level for master. - * - * @param base AIPSTZ peripheral base pointer - * @param master Masters for AIPSTZ. - * @param privilegeConfig Configuration is ORed from @aipstz_master_privilege_level_t. - */ -void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig); - -/*! - * @brief Configure the access for peripheral. - * - * @param base AIPSTZ peripheral base pointer - * @param master Peripheral for AIPSTZ. - * @param accessControl Configuration is ORed from @aipstz_peripheral_access_control_t. - */ -void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_AIPSTZ_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.c deleted file mode 100644 index c20f13c928..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_aoi.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.aoi" -#endif - - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to aoi bases for each instance. */ -static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to aoi clocks for each instance. */ -static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for AOI module. - * - * @param base AOI peripheral base address - * - * @return The AOI instance - */ -static uint32_t AOI_GetInstance(AOI_Type *base); -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t AOI_GetInstance(AOI_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_aoiBases); instance++) - { - if (s_aoiBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_aoiBases)); - - return instance; -} - -void AOI_Init(AOI_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock gate from clock manager. */ - CLOCK_EnableClock(s_aoiClocks[AOI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void AOI_Deinit(AOI_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock gate from clock manager */ - CLOCK_DisableClock(s_aoiClocks[AOI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config) -{ - assert(event < FSL_FEATURE_AOI_EVENT_COUNT); - assert(config != NULL); - - uint16_t value = 0; - /* Read BFCRT01 register at event index. */ - value = base->BFCRT[event].BFCRT01; - - config->PT0AC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_AC_MASK) >> AOI_BFCRT01_PT0_AC_SHIFT); - config->PT0BC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_BC_MASK) >> AOI_BFCRT01_PT0_BC_SHIFT); - config->PT0CC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_CC_MASK) >> AOI_BFCRT01_PT0_CC_SHIFT); - config->PT0DC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_DC_MASK) >> AOI_BFCRT01_PT0_DC_SHIFT); - - config->PT1AC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_AC_MASK) >> AOI_BFCRT01_PT1_AC_SHIFT); - config->PT1BC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_BC_MASK) >> AOI_BFCRT01_PT1_BC_SHIFT); - config->PT1CC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_CC_MASK) >> AOI_BFCRT01_PT1_CC_SHIFT); - config->PT1DC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_DC_MASK) >> AOI_BFCRT01_PT1_DC_SHIFT); - - /* Read BFCRT23 register at event index. */ - value = 0; - value = base->BFCRT[event].BFCRT23; - - config->PT2AC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_AC_MASK) >> AOI_BFCRT23_PT2_AC_SHIFT); - config->PT2BC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_BC_MASK) >> AOI_BFCRT23_PT2_BC_SHIFT); - config->PT2CC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_CC_MASK) >> AOI_BFCRT23_PT2_CC_SHIFT); - config->PT2DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_DC_MASK) >> AOI_BFCRT23_PT2_DC_SHIFT); - - config->PT3AC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_AC_MASK) >> AOI_BFCRT23_PT3_AC_SHIFT); - config->PT3BC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_BC_MASK) >> AOI_BFCRT23_PT3_BC_SHIFT); - config->PT3CC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_CC_MASK) >> AOI_BFCRT23_PT3_CC_SHIFT); - config->PT3DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT); -} - -void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig) -{ - assert(eventConfig != NULL); - assert(event < FSL_FEATURE_AOI_EVENT_COUNT); - - uint16_t value = 0; - /* Calculate value to configure product term 0, 1 */ - value = AOI_BFCRT01_PT0_AC(eventConfig->PT0AC) | AOI_BFCRT01_PT0_BC(eventConfig->PT0BC) | - AOI_BFCRT01_PT0_CC(eventConfig->PT0CC) | AOI_BFCRT01_PT0_DC(eventConfig->PT0DC) | - AOI_BFCRT01_PT1_AC(eventConfig->PT1AC) | AOI_BFCRT01_PT1_BC(eventConfig->PT1BC) | - AOI_BFCRT01_PT1_CC(eventConfig->PT1CC) | AOI_BFCRT01_PT1_DC(eventConfig->PT1DC); - /* Write value to register */ - base->BFCRT[event].BFCRT01 = value; - - /* Reset and calculate value to configure product term 2, 3 */ - value = 0; - value = AOI_BFCRT23_PT2_AC(eventConfig->PT2AC) | AOI_BFCRT23_PT2_BC(eventConfig->PT2BC) | - AOI_BFCRT23_PT2_CC(eventConfig->PT2CC) | AOI_BFCRT23_PT2_DC(eventConfig->PT2DC) | - AOI_BFCRT23_PT3_AC(eventConfig->PT3AC) | AOI_BFCRT23_PT3_BC(eventConfig->PT3BC) | - AOI_BFCRT23_PT3_CC(eventConfig->PT3CC) | AOI_BFCRT23_PT3_DC(eventConfig->PT3DC); - /* Write value to register */ - base->BFCRT[event].BFCRT23 = value; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.h deleted file mode 100644 index 47dbd9b9ca..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_AOI_H_ -#define _FSL_AOI_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup aoi - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#ifndef AOI -#define AOI AOI0 /*!< AOI peripheral address */ -#endif - -/*! @name Driver version */ -/*@{*/ -#define FSL_AOI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ -/*@}*/ - -/*! - * @brief AOI input configurations. - * - * The selection item represents the Boolean evaluations. -*/ -typedef enum _aoi_input_config -{ - kAOI_LogicZero = 0x0U, /*!< Forces the input to logical zero. */ - kAOI_InputSignal = 0x1U, /*!< Passes the input signal. */ - kAOI_InvInputSignal = 0x2U, /*!< Inverts the input signal. */ - kAOI_LogicOne = 0x3U /*!< Forces the input to logical one. */ -} aoi_input_config_t; - -/*! - * @brief AOI event indexes, where an event is the collection of the four product - * terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D). - */ -typedef enum _aoi_event -{ - kAOI_Event0 = 0x0U, /*!< Event 0 index */ - kAOI_Event1 = 0x1U, /*!< Event 1 index */ - kAOI_Event2 = 0x2U, /*!< Event 2 index */ - kAOI_Event3 = 0x3U /*!< Event 3 index */ -} aoi_event_t; - -/*! - * @brief AOI event configuration structure - * - * Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make - * whole event configuration. - */ -typedef struct _aoi_event_config -{ - aoi_input_config_t PT0AC; /*!< Product term 0 input A */ - aoi_input_config_t PT0BC; /*!< Product term 0 input B */ - aoi_input_config_t PT0CC; /*!< Product term 0 input C */ - aoi_input_config_t PT0DC; /*!< Product term 0 input D */ - aoi_input_config_t PT1AC; /*!< Product term 1 input A */ - aoi_input_config_t PT1BC; /*!< Product term 1 input B */ - aoi_input_config_t PT1CC; /*!< Product term 1 input C */ - aoi_input_config_t PT1DC; /*!< Product term 1 input D */ - aoi_input_config_t PT2AC; /*!< Product term 2 input A */ - aoi_input_config_t PT2BC; /*!< Product term 2 input B */ - aoi_input_config_t PT2CC; /*!< Product term 2 input C */ - aoi_input_config_t PT2DC; /*!< Product term 2 input D */ - aoi_input_config_t PT3AC; /*!< Product term 3 input A */ - aoi_input_config_t PT3BC; /*!< Product term 3 input B */ - aoi_input_config_t PT3CC; /*!< Product term 3 input C */ - aoi_input_config_t PT3DC; /*!< Product term 3 input D */ -} aoi_event_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @name AOI Initialization - * @{ - */ - -/*! - * @brief Initializes an AOI instance for operation. - * - * This function un-gates the AOI clock. - * - * @param base AOI peripheral address. - */ -void AOI_Init(AOI_Type *base); - -/*! - * @brief Deinitializes an AOI instance for operation. - * - * This function shutdowns AOI module. - * - * @param base AOI peripheral address. - */ -void AOI_Deinit(AOI_Type *base); - -/*@}*/ - -/*! - * @name AOI Get Set Operation - * @{ - */ - -/*! - * @brief Gets the Boolean evaluation associated. - * - * This function returns the Boolean evaluation associated. - * - * Example: - @code - aoi_event_config_t demoEventLogicStruct; - - AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct); - @endcode - * - * @param base AOI peripheral address. - * @param event Index of the event which will be set of type aoi_event_t. - * @param config Selected input configuration . - */ -void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config); - -/*! - * @brief Configures an AOI event. - * - * This function configures an AOI event according - * to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) - * of all product terms (0, 1, 2, and 3) of a desired event. - * - * Example: - @code - aoi_event_config_t demoEventLogicStruct; - - demoEventLogicStruct.PT0AC = kAOI_InvInputSignal; - demoEventLogicStruct.PT0BC = kAOI_InputSignal; - demoEventLogicStruct.PT0CC = kAOI_LogicOne; - demoEventLogicStruct.PT0DC = kAOI_LogicOne; - - demoEventLogicStruct.PT1AC = kAOI_LogicZero; - demoEventLogicStruct.PT1BC = kAOI_LogicOne; - demoEventLogicStruct.PT1CC = kAOI_LogicOne; - demoEventLogicStruct.PT1DC = kAOI_LogicOne; - - demoEventLogicStruct.PT2AC = kAOI_LogicZero; - demoEventLogicStruct.PT2BC = kAOI_LogicOne; - demoEventLogicStruct.PT2CC = kAOI_LogicOne; - demoEventLogicStruct.PT2DC = kAOI_LogicOne; - - demoEventLogicStruct.PT3AC = kAOI_LogicZero; - demoEventLogicStruct.PT3BC = kAOI_LogicOne; - demoEventLogicStruct.PT3CC = kAOI_LogicOne; - demoEventLogicStruct.PT3DC = kAOI_LogicOne; - - AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct); - @endcode - * - * @param base AOI peripheral address. - * @param event Event which will be configured of type aoi_event_t. - * @param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for - * filling out the members of this structure and passing the pointer to this function. - */ -void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*@}*/ - -/*!* @} */ - -#endif /* _FSL_AOI_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.c deleted file mode 100644 index 15a804b0c5..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_bee.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.bee" -#endif - - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -static void aligned_memcpy(void *dst, const void *src, size_t size) -{ - register uint32_t *to32 = (uint32_t *)(uintptr_t)dst; - register const uint32_t *from32 = (const uint32_t *)(uintptr_t)src; - - while (size >= sizeof(uint32_t)) - { - *to32 = *from32; - size -= sizeof(uint32_t); - to32++; - from32++; - } -} - -void BEE_Init(BEE_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Bee); -#endif - - base->CTRL = BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK; -} - -void BEE_Deinit(BEE_Type *base) -{ - base->CTRL &= - ~(BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK | BEE_CTRL_KEY_VALID_MASK); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Bee); -#endif -} - -void BEE_GetDefaultConfig(bee_region_config_t *config) -{ - assert(config); - - config->mode = kBEE_AesEcbMode; - config->regionBot = 0U; - config->regionTop = 0U; - config->addrOffset = 0xF0000000U; - config->regionEn = kBEE_RegionDisabled; -} - -status_t BEE_SetRegionConfig(BEE_Type *base, bee_region_t region, const bee_region_config_t *config) -{ - IOMUXC_GPR_Type *iomuxc = IOMUXC_GPR; - bool reenable = false; - - /* Wait until BEE is in idle state */ - while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag)) - { - } - - /* Disable BEE before region configuration in case it is enabled. */ - if ((base->CTRL >> BEE_CTRL_BEE_ENABLE_SHIFT) & 1) - { - BEE_Disable(base); - reenable = true; - } - - if (region == kBEE_Region0) - { - /* Region 0 config */ - iomuxc->GPR18 = config->regionBot; - iomuxc->GPR19 = config->regionTop; - - base->CTRL |= BEE_CTRL_CTRL_AES_MODE_R0(config->mode); - base->ADDR_OFFSET0 = BEE_ADDR_OFFSET0_ADDR_OFFSET0(config->addrOffset); - } - - else if (region == kBEE_Region1) - { - /* Region 1 config */ - iomuxc->GPR20 = config->regionBot; - iomuxc->GPR21 = config->regionTop; - - base->CTRL |= BEE_CTRL_CTRL_AES_MODE_R1(config->mode); - base->ADDR_OFFSET1 = BEE_ADDR_OFFSET1_ADDR_OFFSET0(config->addrOffset); - base->REGION1_BOT = BEE_REGION1_BOT_REGION1_BOT(config->regionBot); - base->REGION1_TOP = BEE_REGION1_TOP_REGION1_TOP(config->regionTop); - } - - else - { - return kStatus_InvalidArgument; - } - - /* Enable/disable region if desired */ - if (config->regionEn == kBEE_RegionEnabled) - { - iomuxc->GPR11 |= IOMUXC_GPR_GPR11_BEE_DE_RX_EN(1 << region); - } - else - { - iomuxc->GPR11 &= ~IOMUXC_GPR_GPR11_BEE_DE_RX_EN(1 << region); - } - - /* Reenable BEE if it was enabled before. */ - if (reenable) - { - BEE_Enable(base); - } - - return kStatus_Success; -} - -status_t BEE_SetRegionKey( - BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize, const uint8_t *nonce, size_t nonceSize) -{ - bool reenable = false; - - /* Key must be 32-bit aligned */ - if (((uintptr_t)key & 0x3u) || (keySize != 16)) - { - return kStatus_InvalidArgument; - } - - /* Wait until BEE is in idle state */ - while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag)) - { - } - - /* Disable BEE before region configuration in case it is enabled. */ - if ((base->CTRL >> BEE_CTRL_BEE_ENABLE_SHIFT) & 1) - { - BEE_Disable(base); - reenable = true; - } - - if (region == kBEE_Region0) - { - base->CTRL &= ~BEE_CTRL_KEY_REGION_SEL_MASK; - - if (nonce) - { - if (nonceSize != 16) - { - return kStatus_InvalidArgument; - } - memcpy((uint32_t *)&base->CTR_NONCE0_W0, nonce, nonceSize); - } - } - - else if (region == kBEE_Region1) - { - base->CTRL |= BEE_CTRL_KEY_REGION_SEL_MASK; - - if (nonce) - { - if (nonceSize != 16) - { - return kStatus_InvalidArgument; - } - memcpy((uint32_t *)&base->CTR_NONCE1_W0, nonce, nonceSize); - } - } - - else - { - return kStatus_InvalidArgument; - } - - /* Try to load key. If BEE key selection fuse is programmed to use OTMP key on this device, this operation should - * fail. */ - aligned_memcpy((uint32_t *)&base->AES_KEY0_W0, key, keySize); - if (memcmp((uint32_t *)&base->AES_KEY0_W0, key, keySize) != 0) - { - return kStatus_Fail; - } - - /* Reenable BEE if it was enabled before. */ - if (reenable) - { - BEE_Enable(base); - } - - return kStatus_Success; -} - -uint32_t BEE_GetStatusFlags(BEE_Type *base) -{ - return base->STATUS; -} - -void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask) -{ - /* w1c */ - base->STATUS |= mask; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.h deleted file mode 100644 index 1eb6ae1ed6..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_BEE_H_ -#define _FSL_BEE_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief BEE driver version. Version 2.0.0. - * - * Current version: 2.0.0 - * - * Change log: - * - Version 2.0.0 - * - Initial version - */ -#define FSL_BEE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -typedef enum _bee_aes_mode -{ - kBEE_AesEcbMode = 0U, /*!< AES ECB Mode */ - kBEE_AesCtrMode = 1U /*!< AES CTR Mode */ -} bee_aes_mode_t; - -typedef enum _bee_region -{ - kBEE_Region0 = 0U, /*!< BEE region 0 */ - kBEE_Region1 = 1U /*!< BEE region 1 */ -} bee_region_t; - -typedef enum _bee_region_enable -{ - kBEE_RegionDisabled = 0U, /*!< BEE region disabled */ - kBEE_RegionEnabled = 1U /*!< BEE region enabled */ -} bee_region_enable_t; - -typedef enum _bee_status_flags -{ - kBEE_DisableAbortFlag = 1U, /*!< Disable abort flag. */ - kBEE_Reg0ReadSecViolation = 2U, /*!< Region-0 read channel security violation */ - kBEE_ReadIllegalAccess = 4U, /*!< Read channel illegal access detected */ - kBEE_Reg1ReadSecViolation = 8U, /*!< Region-1 read channel security violation */ - kBEE_Reg0AccessViolation = 16U, /*!< Protected region-0 access violation */ - kBEE_Reg1AccessViolation = 32U, /*!< Protected region-1 access violation */ - kBEE_IdleFlag = BEE_STATUS_BEE_IDLE_MASK /*!< Idle flag */ -} bee_status_flags_t; - -/*! @brief BEE region configuration structure. */ -typedef struct _bee_region_config -{ - bee_aes_mode_t mode; /*!< AES mode used for encryption/decryption */ - uint32_t regionBot; /*!< Region bottom address */ - uint32_t regionTop; /*!< Region top address */ - uint32_t addrOffset; /*!< Region address offset */ - bee_region_enable_t regionEn; /*!< Region enable/disable */ -} bee_region_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Resets BEE module to factory default values. - * - * This function performs hardware reset of BEE module. Attributes and keys from software for both regions are cleared. - * - * @param base BEE peripheral address. - */ -void BEE_Init(BEE_Type *base); - -/*! - * @brief Resets BEE module, clears keys for both regions and disables clock to the BEE. - * - * This function performs hardware reset of BEE module and disables clocks. Attributes and keys from software for both - * regions are cleared. - * - * @param base BEE peripheral address. - */ -void BEE_Deinit(BEE_Type *base); - -/*! - * @brief Enables BEE decryption. - * - * This function enables decryption using BEE. - * - * @param base BEE peripheral address. - */ -static inline void BEE_Enable(BEE_Type *base) -{ - base->CTRL |= BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_KEY_VALID_MASK; -} - -/*! - * @brief Disables BEE decryption. - * - * This function disables decryption using BEE. - * - * @param base BEE peripheral address. - */ -static inline void BEE_Disable(BEE_Type *base) -{ - base->CTRL &= ~BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_KEY_VALID_MASK; -} - -/*! - * @brief Loads default values to the BEE region configuration structure. - * - * Loads default values to the BEE region configuration structure. The default values are as follows: - * @code - * config->mode = kBEE_AesCbcMode; - * config->regionBot = 0U; - * config->regionTop = 0U; - * config->addrOffset = 0xF0000000U; - * config->regionEn = kBEE_RegionDisabled; - * @endcode - * - * @param config Configuration structure for BEE region. - */ -void BEE_GetDefaultConfig(bee_region_config_t *config); - -/*! - * @brief Sets BEE region configuration. - * - * This function sets BEE region settings accorging to given configuration structure. - * - * @param base BEE peripheral address. - * @param region Selection of the BEE region to be configured. - * @param config Configuration structure for BEE region. - */ -status_t BEE_SetRegionConfig(BEE_Type *base, bee_region_t region, const bee_region_config_t *config); - -/*! - * @brief Loads the AES key and nonce for selected region into BEE key registers. - * - * This function loads given AES key and nonce(only AES CTR mode) to BEE register for the given region. - * - * Please note, that eFuse BEE_KEYx_SEL must be set accordingly to be able to load and use key loaded in BEE registers. - * Otherwise, key cannot loaded and BEE will use key from OTPMK or SW_GP2. - * - * @param base BEE peripheral address. - * @param region Selection of the BEE region to be configured. - * @param key AES key. - * @param keySize Size of AES key. - * @param nonce AES nonce. - * @param nonceSize Size of AES nonce. - */ -status_t BEE_SetRegionKey( - BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize, const uint8_t *nonce, size_t nonceSize); - -/*! - * @brief Gets the BEE status flags. - * - * This function returns status of BEE peripheral. - * - * @param base BEE peripheral address. - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::bee_status_flags_t - */ -uint32_t BEE_GetStatusFlags(BEE_Type *base); - -/*! - * @brief Clears the BEE status flags. - * - * @param base BEE peripheral base address. - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::bee_status_flags_t - */ -void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask); - -/*! - * @brief Computes offset to be set for specifed memory location. - * - * This function calculates offset that must be set for BEE region to access physical memory location. - * - * @param addressMemory Address of physical memory location. - */ -static inline uint32_t BEE_GetOffset(uint32_t addressMemory) -{ - return (addressMemory >> 16); -} - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_BEE_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_cache.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_cache.c deleted file mode 100644 index 595fefe733..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_cache.c +++ /dev/null @@ -1,470 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_cache.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.cache_armv7_m7" -#endif - -#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT -#define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU -#define L2CACHE_8WAYS_MASK 0xFFU -#define L2CACHE_16WAYS_MASK 0xFFFFU -#define L2CACHE_SMALLWAYS_NUM 8U -#define L2CACHE_1KBCOVERTOB 1024U -#define L2CACHE_SAMLLWAYS_SIZE 16U -#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/ -/******************************************************************************* -* Prototypes -******************************************************************************/ -/*! - * @brief Set for all ways and waiting for the operation finished. - * This is provided for all the background operations. - * - * @param auxCtlReg The auxiliary control register. - * @param regAddr The register address to be operated. - */ -static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr); - -/*! - * @brief Invalidates the Level 2 cache line by physical address. - * This function invalidates a cache line by physcial address. - * - * @param address The physical addderss of the cache. - * The format of the address shall be : - * bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0 - * Tag | index | 0 - * Note: the physical address shall be aligned to the line size - 32B (256 bit). - * so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero. - * If the input address is not aligned, it will be changed to 32-byte aligned address. - * The n is varies according to the index width. - * @return The actual 32-byte aligned physical address be operated. - */ -static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address); - -/*! - * @brief Cleans the Level 2 cache line based on the physical address. - * This function cleans a cache line based on a physcial address. - * - * @param address The physical addderss of the cache. - * The format of the address shall be : - * bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0 - * Tag | index | 0 - * Note: the physical address shall be aligned to the line size - 32B (256 bit). - * so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero. - * If the input address is not aligned, it will be changed to 32-byte aligned address. - * The n is varies according to the index width. - * @return The actual 32-byte aligned physical address be operated. - */ -static uint32_t L2CACHE_CleanLineByAddr(uint32_t address); - -/*! - * @brief Cleans and invalidates the Level 2 cache line based on the physical address. - * This function cleans and invalidates a cache line based on a physcial address. - * - * @param address The physical addderss of the cache. - * The format of the address shall be : - * bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0 - * Tag | index | 0 - * Note: the physical address shall be aligned to the line size - 32B (256 bit). - * so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero. - * If the input address is not aligned, it will be changed to 32-byte aligned address. - * The n is varies according to the index width. - * @return The actual 32-byte aligned physical address be operated. - */ -static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address); - -/*! - * @brief Gets the number of the Level 2 cache and the way size. - * This function cleans and invalidates a cache line based on a physcial address. - * - * @param num_ways The number of the cache way. - * @param size_way The way size. - */ -static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way); -/******************************************************************************* - * Code - ******************************************************************************/ -static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr) -{ - uint16_t mask = L2CACHE_8WAYS_MASK; - uint32_t timeout = L2CACHE_OPERATION_TIMEOUT; - - /* Check the ways used at first. */ - if (auxCtlReg & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) - { - mask = L2CACHE_16WAYS_MASK; - } - - /* Set the opeartion for all ways/entries of the cache. */ - *(uint32_t *)regAddr = mask; - /* Waiting for until the operation is complete. */ - while ((*(volatile uint32_t *)regAddr & mask) && timeout) - { - __ASM("nop"); - timeout--; - } -} - -static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address) -{ - /* Align the address first. */ - address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1); - /* Invalidate the cache line by physical address. */ - L2CACHEC->REG7_INV_PA = address; - - return address; -} - -static uint32_t L2CACHE_CleanLineByAddr(uint32_t address) -{ - /* Align the address first. */ - address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1); - /* Invalidate the cache line by physical address. */ - L2CACHEC->REG7_CLEAN_PA = address; - - return address; -} - -static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address) -{ - /* Align the address first. */ - address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1); - /* Clean and invalidate the cache line by physical address. */ - L2CACHEC->REG7_CLEAN_INV_PA = address; - - return address; -} - -static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way) -{ - assert(num_ways); - assert(size_way); - - uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> - L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT; - uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >> - L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT; - - *num_ways = (number + 1) * L2CACHE_SMALLWAYS_NUM; - if (!size) - { - /* 0 internally mapped to the same size as 1 - 16KB.*/ - size += 1; - } - *size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB; -} - -void L2CACHE_Init(l2cache_config_t *config) -{ - assert (config); - - uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */ - uint8_t count; - uint32_t auxReg = 0; - - /*The aux register must be configured when the cachec is disabled - * So disable first if the cache controller is enabled. - */ - if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK) - { - L2CACHE_Disable(); - } - - /* Unlock all entries. */ - if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) - { - waysNum = 0xFFFFU; - } - - for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count ++) - { - L2CACHE_LockdownByWayEnable(count, waysNum, false); - } - - /* Set the ways and way-size etc. */ - auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) | - L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | - L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) | - L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) | - L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) | - L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) | - L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | - L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc); - L2CACHEC->REG1_AUX_CONTROL = auxReg; - - /* Set the tag/data ram latency. */ - if (config->lateConfig) - { - uint32_t data = 0; - /* Tag latency. */ - data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)| - L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)| - L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate)| - L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); - L2CACHEC->REG1_TAG_RAM_CONTROL = data; - /* Data latency. */ - data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)| - L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)| - L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate)| - L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); - L2CACHEC->REG1_DATA_RAM_CONTROL = data; - } -} - -void L2CACHE_GetDefaultConfig(l2cache_config_t *config) -{ - assert(config); - uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> - L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT; - uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >> - L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT; - - /* Get the default value */ - config->wayNum = (l2cache_way_num_t)number; - config->waySize = (l2cache_way_size)size; - config->repacePolicy = kL2CACHE_Roundrobin; - config->lateConfig = NULL; - config->istrPrefetchEnable = false; - config->dataPrefetchEnable = false; - config->nsLockdownEnable = false; - config->writeAlloc = kL2CACHE_UseAwcache; -} - -void L2CACHE_Enable(void) -{ - /* Invalidate first. */ - L2CACHE_Invalidate(); - /* Enable the level 2 cache controller. */ - L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK; -} - -void L2CACHE_Disable(void) -{ - /* First CleanInvalidate all enties in the cache. */ - L2CACHE_CleanInvalidate(); - /* Disable the level 2 cache controller. */ - L2CACHEC->REG1_CONTROL &= ~L2CACHEC_REG1_CONTROL_CE_MASK; - /* DSB - data sync barrier.*/ - __DSB(); -} - -void L2CACHE_Invalidate(void) -{ - /* Invalidate all entries in cache. */ - L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_INV_WAY); - /* Cache sync. */ - L2CACHEC->REG7_CACHE_SYNC = 0; -} - -void L2CACHE_Clean(void) -{ - /* Clean all entries of the cache. */ - L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_WAY); - /* Cache sync. */ - L2CACHEC->REG7_CACHE_SYNC = 0; -} - -void L2CACHE_CleanInvalidate(void) -{ - /* Clean all entries of the cache. */ - L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_INV_WAY); - /* Cache sync. */ - L2CACHEC->REG7_CACHE_SYNC = 0; -} - -void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) -{ - uint32_t endAddr = address + size_byte; - - /* Invalidate addresses in the range. */ - while (address < endAddr) - { - address = L2CACHE_InvalidateLineByAddr(address); - /* Update the size. */ - address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE; - } - - /* Cache sync. */ - L2CACHEC->REG7_CACHE_SYNC = 0; -} - -void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte) -{ - uint32_t num_ways = 0; - uint32_t size_way = 0; - uint32_t endAddr = address + size_byte; - - /* Get the number and size of the cache way. */ - L2CACHE_GetWayNumSize(&num_ways, &size_way); - - /* Check if the clean size is over the cache size. */ - if ((endAddr - address) > num_ways * size_way) - { - L2CACHE_Clean(); - return; - } - - /* Clean addresses in the range. */ - while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr) - { - /* Clean the address in the range. */ - address = L2CACHE_CleanLineByAddr(address); - address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE; - } - - L2CACHEC->REG7_CACHE_SYNC = 0; -} - -void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) -{ - uint32_t num_ways = 0; - uint32_t size_way = 0; - uint32_t endAddr = address + size_byte; - - /* Get the number and size of the cache way. */ - L2CACHE_GetWayNumSize(&num_ways, &size_way); - - /* Check if the clean size is over the cache size. */ - if ((endAddr - address) > num_ways * size_way) - { - L2CACHE_CleanInvalidate(); - return; - } - - /* Clean addresses in the range. */ - while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr) - { - /* Clean the address in the range. */ - address = L2CACHE_CleanInvalidateLineByAddr(address); - address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE; - } - - L2CACHEC->REG7_CACHE_SYNC = 0; -} - -void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) -{ - uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> - L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT; - num_ways = (num_ways + 1) * L2CACHE_SMALLWAYS_NUM; - - assert(mask < (1U << num_ways)); - assert(masterId < L2CACHE_LOCKDOWN_REGNUM); - - uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; - uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; - - if (enable) - { - /* Data lockdown. */ - L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; - /* Instruction lockdown. */ - L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; - } - else - { - /* Data lockdown. */ - L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; - /* Instruction lockdown. */ - L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; - } -} -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ - -void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte) -{ -#if (__DCACHE_PRESENT == 1U) - uint32_t addr = address & (uint32_t)~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1); - int32_t size = size_byte + address - addr; - uint32_t linesize = 32U; - - __DSB(); - while (size > 0) - { - SCB->ICIMVAU = addr; - addr += linesize; - size -= linesize; - } - __DSB(); - __ISB(); -#endif -} - -void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) -{ -#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT -#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT - L2CACHE_InvalidateByRange(address, size_byte); -#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ - - L1CACHE_InvalidateICacheByRange(address, size_byte); -} - -void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) -{ -#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT -#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT - L2CACHE_InvalidateByRange(address, size_byte); -#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ - L1CACHE_InvalidateDCacheByRange(address, size_byte); -} - -void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) -{ - L1CACHE_CleanDCacheByRange(address, size_byte); -#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT -#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT - L2CACHE_CleanByRange(address, size_byte); -#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ -} - -void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) -{ - L1CACHE_CleanInvalidateDCacheByRange(address, size_byte); -#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT -#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT - L2CACHE_CleanInvalidateByRange(address, size_byte); -#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_cache.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_cache.h deleted file mode 100644 index a041ea2a34..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_cache.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_CACHE_H_ -#define _FSL_CACHE_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cache - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief cache driver version 2.0.1. */ -#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT -#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT -#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0 -#endif -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ -/******************************************************************************* - * Definitions - ******************************************************************************/ -#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT - -/*! @brief Number of level 2 cache controller ways. */ -typedef enum _l2cache_way_num -{ - kL2CACHE_8ways = 0, /*!< 8 ways. */ -#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY - kL2CACHE_16ways /*!< 16 ways. */ -#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */ -} l2cache_way_num_t; - -/*! @brief Level 2 cache controller way size. */ -typedef enum _l2cache_way_size -{ - kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */ - kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */ - kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */ - kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */ - kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */ - kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */ -} l2cache_way_size; - -/*! @brief Level 2 cache controller replacement policy. */ -typedef enum _l2cache_replacement -{ - kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */ - kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */ -} l2cache_replacement_t; - -/*! @brief Level 2 cache controller force write allocate options. */ -typedef enum _l2cache_writealloc -{ - kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */ - kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */ - kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */ -} l2cache_writealloc_t; - -/*! @brief Level 2 cache controller tag/data ram latency. */ -typedef enum _l2cache_latency -{ - kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */ - kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */ - kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */ - kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */ - kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */ - kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */ - kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */ - kL2CACHE_8CycleLate /*!< 8 cycle of latency. */ -} l2cache_latency_t; - -/*! @brief Level 2 cache controller tag/data ram latency configure structure. */ -typedef struct _l2cache_latency_config -{ - l2cache_latency_t tagWriteLate; /*!< Tag write latency. */ - l2cache_latency_t tagReadLate; /*!< Tag Read latency. */ - l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */ - l2cache_latency_t dataWriteLate; /*!< Data write latency. */ - l2cache_latency_t dataReadLate; /*!< Data Read latency. */ - l2cache_latency_t dataSetupLate; /*!< Data setup latency. */ -} L2cache_latency_config_t; - -/*! @brief Level 2 cache controller configure structure. */ -typedef struct _l2cache_config -{ - /* ------------------------ l2 cachec basic settings ---------------------------- */ - l2cache_way_num_t wayNum; /*!< The number of ways. */ - l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */ - l2cache_replacement_t repacePolicy;/*!< Replacemnet policy. */ - /* ------------------------ tag/data ram latency settings ----------------------- */ - L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ - /* ------------------------ Prefetch enable settings ---------------------------- */ - bool istrPrefetchEnable; /*!< Instruction prefetch enable. */ - bool dataPrefetchEnable; /*!< Data prefetch enable. */ - /* ------------------------ Non-secure access settings -------------------------- */ - bool nsLockdownEnable; /*!< None-secure lockdown enable. */ - /* ------------------------ other settings -------------------------------------- */ - l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */ -} l2cache_config_t; -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Control for cortex-m7 L1 cache - *@{ - */ - -/*! - * @brief Enables cortex-m7 L1 instruction cache. - * - */ -static inline void L1CACHE_EnableICache(void) -{ - SCB_EnableICache(); -} - -/*! - * @brief Disables cortex-m7 L1 instruction cache. - * - */ -static inline void L1CACHE_DisableICache(void) -{ - SCB_DisableICache(); -} - -/*! - * @brief Invalidate cortex-m7 L1 instruction cache. - * - */ -static inline void L1CACHE_InvalidateICache(void) -{ - SCB_InvalidateICache(); -} - -/*! - * @brief Invalidate cortex-m7 L1 instruction cache by range. - * - * @param address The start address of the memory to be invalidated. - * @param size_byte The memory size. - * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. - * The startAddr here will be forced to align to L1 I-cache line size if - * startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte); - -/*! - * @brief Enables cortex-m7 L1 data cache. - * - */ -static inline void L1CACHE_EnableDCache(void) -{ - SCB_EnableDCache(); -} - -/*! - * @brief Disables cortex-m7 L1 data cache. - * - */ -static inline void L1CACHE_DisableDCache(void) -{ - SCB_DisableDCache(); -} - -/*! - * @brief Invalidates cortex-m7 L1 data cache. - * - */ -static inline void L1CACHE_InvalidateDCache(void) -{ - SCB_InvalidateDCache(); -} - -/*! - * @brief Cleans cortex-m7 L1 data cache. - * - */ -static inline void L1CACHE_CleanDCache(void) -{ - SCB_CleanDCache(); -} - -/*! - * @brief Cleans and Invalidates cortex-m7 L1 data cache. - * - */ -static inline void L1CACHE_CleanInvalidateDCache(void) -{ - SCB_CleanInvalidateDCache(); -} - -/*! - * @brief Invalidates cortex-m7 L1 data cache by range. - * - * @param address The start address of the memory to be invalidated. - * @param size_byte The memory size. - * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. - * The startAddr here will be forced to align to L1 D-cache line size if - * startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte) -{ - uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); - uint32_t size = size_byte + address - startAddr; - - SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size); -} - -/*! - * @brief Cleans cortex-m7 L1 data cache by range. - * - * @param address The start address of the memory to be cleaned. - * @param size_byte The memory size. - * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. - * The startAddr here will be forced to align to L1 D-cache line size if - * startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte) -{ - uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); - uint32_t size = size_byte + address - startAddr; - - SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size); -} - -/*! - * @brief Cleans and Invalidates cortex-m7 L1 data cache by range. - * - * @param address The start address of the memory to be clean and invalidated. - * @param size_byte The memory size. - * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. - * The startAddr here will be forced to align to L1 D-cache line size if - * startAddr is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte) -{ - uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); - uint32_t size = size_byte + address - startAddr; - - SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size); -} -/*@}*/ - -#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT -/*! - * @name Control for L2 pl310 cache - *@{ - */ - -/*! - * @brief Initializes the level 2 cache controller module. - * - * @param config Pointer to configuration structure. See "l2cache_config_t". - */ -void L2CACHE_Init(l2cache_config_t *config); - -/*! - * @brief Gets an available default settings for the cache controller. - * - * This function initializes the cache controller configuration structure with default settings. - * The default values are: - * @code - * config->waysNum = kL2CACHE_8ways; - * config->waySize = kL2CACHE_32KbSize; - * config->repacePolicy = kL2CACHE_Roundrobin; - * config->lateConfig = NULL; - * config->istrPrefetchEnable = false; - * config->dataPrefetchEnable = false; - * config->nsLockdownEnable = false; - * config->writeAlloc = kL2CACHE_UseAwcache; - * @endcode - * @param config Pointer to the configuration structure. - */ -void L2CACHE_GetDefaultConfig(l2cache_config_t *config); - -/*! - * @brief Enables the level 2 cache controller. - * This function enables the cache controller. Must be written using a secure access. - * If write with a Non-secure access will cause a DECERR response. - * - */ -void L2CACHE_Enable(void); - -/*! - * @brief Disables the level 2 cache controller. - * This function disables the cache controller. Must be written using a secure access. - * If write with a Non-secure access will cause a DECERR response. - * - */ -void L2CACHE_Disable(void); - -/*! - * @brief Invalidates the Level 2 cache. - * This function invalidates all entries in cache. - * - */ -void L2CACHE_Invalidate(void); - -/*! - * @brief Invalidates the Level 2 cache lines in the range of two physical addresses. - * This function invalidates all cache lines between two physical addresses. - * - * @param address The start address of the memory to be invalidated. - * @param size_byte The memory size. - * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. - * The startAddr here will be forced to align to L2 line size if startAddr - * is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); - -/*! - * @brief Cleans the level 2 cache controller. - * This function cleans all entries in the level 2 cache controller. - * - */ -void L2CACHE_Clean(void); - -/*! - * @brief Cleans the Level 2 cache lines in the range of two physical addresses. - * This function cleans all cache lines between two physical addresses. - * - * @param address The start address of the memory to be cleaned. - * @param size_byte The memory size. - * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. - * The startAddr here will be forced to align to L2 line size if startAddr - * is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte); - -/*! - * @brief Cleans and invalidates the level 2 cache controller. - * This function cleans and invalidates all entries in the level 2 cache controller. - * - */ -void L2CACHE_CleanInvalidate(void); - -/*! - * @brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses. - * This function cleans and invalidates all cache lines between two physical addresses. - * - * @param address The start address of the memory to be cleaned and invalidated. - * @param size_byte The memory size. - * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. - * The startAddr here will be forced to align to L2 line size if startAddr - * is not aligned. For the size_byte, application should make sure the - * alignment or make sure the right operation order if the size_byte is not aligned. - */ -void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); - -/*! - * @brief Enables or disables to lock down the data and instruction by way. - * This function locks down the cached instruction/data by way and prevent the adresses from - * being allocated and prevent dara from being evicted out of the level 2 cache. - * But the normal cache maintenance operations that invalidate, clean or clean - * and validate cache contents affect the locked-down cache lines as normal. - * - * @param masterId The master id, range from 0 ~ 7. - * @param mask The ways to be enabled or disabled to lockdown. - * each bit in value is related to each way of the cache. for example: - * value: bit 0 ------ way 0. - * value: bit 1 ------ way 1. - * -------------------------- - * value: bit 15 ------ way 15. - * Note: please make sure the value setting is align with your supported ways. - * @param enable True enable the lockdown, false to disable the lockdown. - */ -void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable); - -/*@}*/ -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ - -/*! - * @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310) - * Mainly used for many drivers for easy cache operation. - *@{ - */ - -/*! - * @brief Invalidates all instruction caches by range. - * - * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. - * - * @param address The physical address. - * @param size_byte size of the memory to be invalidated. - * @note address and size should be aligned to cache line size - * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced - * to align to the cache line size if startAddr is not aligned. For the size_byte, application should - * make sure the alignment or make sure the right operation order if the size_byte is not aligned. - */ -void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); - -/*! - * @brief Invalidates all data caches by range. - * - * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. - * - * @param address The physical address. - * @param size_byte size of the memory to be invalidated. - * @note address and size should be aligned to cache line size - * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced - * to align to the cache line size if startAddr is not aligned. For the size_byte, application should - * make sure the alignment or make sure the right operation order if the size_byte is not aligned. - */ -void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); - -/*! - * @brief Cleans all data caches by range. - * - * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. - * - * @param address The physical address. - * @param size_byte size of the memory to be cleaned. - * @note address and size should be aligned to cache line size - * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced - * to align to the cache line size if startAddr is not aligned. For the size_byte, application should - * make sure the alignment or make sure the right operation order if the size_byte is not aligned. - */ -void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte); - -/*! - * @brief Cleans and Invalidates all data caches by range. - * - * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. - * - * @param address The physical address. - * @param size_byte size of the memory to be cleaned and invalidated. - * @note address and size should be aligned to cache line size - * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced - * to align to the cache line size if startAddr is not aligned. For the size_byte, application should - * make sure the alignment or make sure the right operation order if the size_byte is not aligned. - */ -void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); - -/*@}*/ - - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CACHE_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_clock.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_clock.c deleted file mode 100644 index fba76beac2..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_clock.c +++ /dev/null @@ -1,917 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_clock.h" -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.clock" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* External XTAL (OSC) clock frequency. */ -uint32_t g_xtalFreq; -/* External RTC XTAL clock frequency. */ -uint32_t g_rtcXtalFreq; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the periph clock frequency. - * - * @return Periph clock frequency in Hz. - */ -static uint32_t CLOCK_GetPeriphClkFreq(void); - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t CLOCK_GetPeriphClkFreq(void) -{ - uint32_t freq; - - /* Periph_clk2_clk ---> Periph_clk */ - if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) - { - switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) - { - /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ - case CCM_CBCMR_PERIPH_CLK2_SEL(0U): - freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); - break; - - /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ - case CCM_CBCMR_PERIPH_CLK2_SEL(1U): - freq = CLOCK_GetOscFreq(); - break; - - case CCM_CBCMR_PERIPH_CLK2_SEL(2U): - freq = CLOCK_GetPllFreq(kCLOCK_PllSys); - break; - - case CCM_CBCMR_PERIPH_CLK2_SEL(3U): - default: - freq = 0U; - break; - } - - freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); - } - /* Pre_Periph_clk ---> Periph_clk */ - else - { - switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) - { - /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */ - case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): - freq = CLOCK_GetPllFreq(kCLOCK_PllSys); - break; - - /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */ - case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): - freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); - break; - - /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */ - case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): - freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); - break; - - /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */ - case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): - freq = CLOCK_GetPllFreq(kCLOCK_PllArm) / - (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); - break; - - default: - freq = 0U; - break; - } - } - - return freq; -} - -void CLOCK_InitExternalClk(bool bypassXtalOsc) -{ - /* This device does not support bypass XTAL OSC. */ - assert(!bypassXtalOsc); - - CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power up */ - while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0) - { - } - CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; /* detect freq */ - while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) == 0) - { - } - CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; -} - -void CLOCK_DeinitExternalClk(void) -{ - CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */ -} - -void CLOCK_SwitchOsc(clock_osc_t osc) -{ - if (osc == kCLOCK_RcOsc) - XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; - else - XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; -} - -void CLOCK_InitRcOsc24M(void) -{ - XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; -} - -void CLOCK_DeinitRcOsc24M(void) -{ - XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; -} - -uint32_t CLOCK_GetFreq(clock_name_t name) -{ - uint32_t freq; - - switch (name) - { - case kCLOCK_CpuClk: - /* Periph_clk ---> AHB Clock */ - case kCLOCK_AhbClk: - /* Periph_clk ---> AHB Clock */ - freq = - CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); - break; - - case kCLOCK_SemcClk: - /* SEMC alternative clock ---> SEMC Clock */ - if (CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK) - { - /* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */ - if (CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) - { - freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); - } - /* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */ - else - { - freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); - } - } - /* Periph_clk ---> SEMC Clock */ - else - { - freq = CLOCK_GetPeriphClkFreq(); - } - - freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U); - break; - - case kCLOCK_IpgClk: - /* Periph_clk ---> AHB Clock ---> IPG Clock */ - freq = - CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); - freq /= (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); - break; - - case kCLOCK_OscClk: - freq = CLOCK_GetOscFreq(); - break; - case kCLOCK_RtcClk: - freq = CLOCK_GetRtcFreq(); - break; - case kCLOCK_ArmPllClk: - freq = CLOCK_GetPllFreq(kCLOCK_PllArm); - break; - case kCLOCK_Usb1PllClk: - freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); - break; - case kCLOCK_Usb1PllPfd0Clk: - freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd0); - break; - case kCLOCK_Usb1PllPfd1Clk: - freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); - break; - case kCLOCK_Usb1PllPfd2Clk: - freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2); - break; - case kCLOCK_Usb1PllPfd3Clk: - freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3); - break; - case kCLOCK_Usb2PllClk: - freq = CLOCK_GetPllFreq(kCLOCK_PllUsb2); - break; - case kCLOCK_SysPllClk: - freq = CLOCK_GetPllFreq(kCLOCK_PllSys); - break; - case kCLOCK_SysPllPfd0Clk: - freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); - break; - case kCLOCK_SysPllPfd1Clk: - freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd1); - break; - case kCLOCK_SysPllPfd2Clk: - freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); - break; - case kCLOCK_SysPllPfd3Clk: - freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3); - break; - case kCLOCK_EnetPll0Clk: - freq = CLOCK_GetPllFreq(kCLOCK_PllEnet); - break; - case kCLOCK_EnetPll1Clk: - freq = CLOCK_GetPllFreq(kCLOCK_PllEnet25M); - break; - case kCLOCK_AudioPllClk: - freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); - break; - case kCLOCK_VideoPllClk: - freq = CLOCK_GetPllFreq(kCLOCK_PllVideo); - break; - default: - freq = 0U; - break; - } - - return freq; -} - -bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) -{ - CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; - USB1->USBCMD |= USBHS_USBCMD_RST_MASK; - for (volatile uint32_t i = 0; i < 400000; - i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ - { - __ASM("nop"); - } - PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | - (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); - return true; -} - -bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) -{ - CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; - USB2->USBCMD |= USBHS_USBCMD_RST_MASK; - for (volatile uint32_t i = 0; i < 400000; - i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ - { - __ASM("nop"); - } - PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | - (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); - return true; -} - -bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) -{ - const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; - if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) - { - CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; - } - else - { - CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); - } - USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ - USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; - - USBPHY1->PWD = 0; - USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | - USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; - return true; -} - -void CLOCK_DisableUsbhs0PhyPllClock(void) -{ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; - USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ -} - -void CLOCK_InitArmPll(const clock_arm_pll_config_t *config) -{ - /* Bypass PLL first */ - CCM_ANALOG->PLL_ARM = (CCM_ANALOG->PLL_ARM & (~CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_ARM_BYPASS_MASK | CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(config->src); - - CCM_ANALOG->PLL_ARM = - (CCM_ANALOG->PLL_ARM & (~(CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK | CCM_ANALOG_PLL_ARM_POWERDOWN_MASK))) | - CCM_ANALOG_PLL_ARM_ENABLE_MASK | CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider); - - while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0) - { - } - - /* Disable Bypass */ - CCM_ANALOG->PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK; -} - -void CLOCK_DeinitArmPll(void) -{ - CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK; -} - -void CLOCK_InitSysPll(const clock_sys_pll_config_t *config) -{ - /* Bypass PLL first */ - CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_SYS_BYPASS_MASK | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(config->src); - - CCM_ANALOG->PLL_SYS = - (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) | - CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); - - while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0) - { - } - - /* Disable Bypass */ - CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK; -} - -void CLOCK_DeinitSysPll(void) -{ - CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK; -} - -void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config) -{ - /* Bypass PLL first */ - CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src); - - CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) | - CCM_ANALOG_PLL_USB1_ENABLE_MASK | CCM_ANALOG_PLL_USB1_POWER_MASK | - CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); - - while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) - { - } - - /* Disable Bypass */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; -} - -void CLOCK_DeinitUsb1Pll(void) -{ - CCM_ANALOG->PLL_USB1 = 0U; -} - -void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config) -{ - /* Bypass PLL first */ - CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_USB2_BYPASS_MASK | CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(config->src); - - CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)) | - CCM_ANALOG_PLL_USB2_ENABLE_MASK | CCM_ANALOG_PLL_USB2_POWER_MASK | - CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider); - - while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) - { - } - - /* Disable Bypass */ - CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_BYPASS_MASK; -} - -void CLOCK_DeinitUsb2Pll(void) -{ - CCM_ANALOG->PLL_USB2 = 0U; -} - -void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) -{ - uint32_t pllAudio; - uint32_t misc2 = 0; - - /* Bypass PLL first */ - CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src); - - CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator); - CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator); - - /* - * Set post divider: - * - * ------------------------------------------------------------------------ - * | config->postDivider | PLL_AUDIO[POST_DIV_SELECT] | MISC2[AUDIO_DIV] | - * ------------------------------------------------------------------------ - * | 1 | 2 | 0 | - * ------------------------------------------------------------------------ - * | 2 | 1 | 0 | - * ------------------------------------------------------------------------ - * | 4 | 2 | 3 | - * ------------------------------------------------------------------------ - * | 8 | 1 | 3 | - * ------------------------------------------------------------------------ - * | 16 | 0 | 3 | - * ------------------------------------------------------------------------ - */ - pllAudio = - (CCM_ANALOG->PLL_AUDIO & (~(CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK))) | - CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider); - - switch (config->postDivider) - { - case 16: - pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0); - misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - break; - - case 8: - pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); - misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - break; - - case 4: - pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); - misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - break; - - case 2: - pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); - break; - - default: - pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); - break; - } - - CCM_ANALOG->MISC2 = - (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) | misc2; - - CCM_ANALOG->PLL_AUDIO = pllAudio; - - while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) - { - } - - /* Disable Bypass */ - CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; -} - -void CLOCK_DeinitAudioPll(void) -{ - CCM_ANALOG->PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; -} - -void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) -{ - uint32_t pllVideo; - uint32_t misc2 = 0; - - /* Bypass PLL first */ - CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(config->src); - - CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator); - CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator); - - /* - * Set post divider: - * - * ------------------------------------------------------------------------ - * | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] | - * ------------------------------------------------------------------------ - * | 1 | 2 | 0 | - * ------------------------------------------------------------------------ - * | 2 | 1 | 0 | - * ------------------------------------------------------------------------ - * | 4 | 2 | 3 | - * ------------------------------------------------------------------------ - * | 8 | 1 | 3 | - * ------------------------------------------------------------------------ - * | 16 | 0 | 3 | - * ------------------------------------------------------------------------ - */ - pllVideo = - (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | - CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider); - - switch (config->postDivider) - { - case 16: - pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0); - misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); - break; - - case 8: - pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); - misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); - break; - - case 4: - pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); - misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); - break; - - case 2: - pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); - break; - - default: - pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); - break; - } - - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK) | misc2; - - CCM_ANALOG->PLL_VIDEO = pllVideo; - - while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) - { - } - - /* Disable Bypass */ - CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; -} - -void CLOCK_DeinitVideoPll(void) -{ - CCM_ANALOG->PLL_VIDEO = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; -} - -void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config) -{ - uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider); - - CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(config->src); - - if (config->enableClkOutput) - { - enet_pll |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; - } - - if (config->enableClkOutput25M) - { - enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - } - - CCM_ANALOG->PLL_ENET = - (CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | - enet_pll; - - /* Wait for stable */ - while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) - { - } - - /* Disable Bypass */ - CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK; -} - -void CLOCK_DeinitEnetPll(void) -{ - CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; -} - -uint32_t CLOCK_GetPllFreq(clock_pll_t pll) -{ - uint32_t freq; - uint32_t divSelect; - uint64_t freqTmp; - - const uint32_t enetRefClkFreq[] = { - 25000000U, /* 25M */ - 50000000U, /* 50M */ - 100000000U, /* 100M */ - 125000000U /* 125M */ - }; - - /* check if PLL is enabled */ - if (!CLOCK_IsPllEnabled(CCM_ANALOG, pll)) - { - return 0U; - } - - /* get pll reference clock */ - freq = CLOCK_GetPllBypassRefClk(CCM_ANALOG, pll); - - /* check if pll is bypassed */ - if (CLOCK_IsPllBypassed(CCM_ANALOG, pll)) - { - return freq; - } - - switch (pll) - { - case kCLOCK_PllArm: - freq = ((freq * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> - CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> - 1U); - break; - case kCLOCK_PllSys: - /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ - freqTmp = - ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); - - if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) - { - freq *= 22U; - } - else - { - freq *= 20U; - } - - freq += (uint32_t)freqTmp; - break; - - case kCLOCK_PllUsb1: - freq = (freq * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); - break; - - case kCLOCK_PllAudio: - /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ - divSelect = - (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; - - freqTmp = - ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); - - freq = freq * divSelect + (uint32_t)freqTmp; - - /* AUDIO PLL output = PLL output frequency / POSTDIV. */ - - /* - * Post divider: - * - * PLL_AUDIO[POST_DIV_SELECT]: - * 0x00: 4 - * 0x01: 2 - * 0x02: 1 - * - * MISC2[AUDO_DIV]: - * 0x00: 1 - * 0x01: 2 - * 0x02: 1 - * 0x03: 4 - */ - switch (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) - { - case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0U): - freq = freq >> 2U; - break; - - case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1U): - freq = freq >> 1U; - break; - - default: - break; - } - - switch (CCM_ANALOG->MISC2 & (CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)) - { - case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): - freq >>= 2U; - break; - - case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): - freq >>= 1U; - break; - - default: - break; - } - break; - - case kCLOCK_PllVideo: - /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ - divSelect = - (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; - - freqTmp = - ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); - - freq = freq * divSelect + (uint32_t)freqTmp; - - /* VIDEO PLL output = PLL output frequency / POSTDIV. */ - - /* - * Post divider: - * - * PLL_VIDEO[POST_DIV_SELECT]: - * 0x00: 4 - * 0x01: 2 - * 0x02: 1 - * - * MISC2[VIDEO_DIV]: - * 0x00: 1 - * 0x01: 2 - * 0x02: 1 - * 0x03: 4 - */ - switch (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) - { - case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0U): - freq = freq >> 2U; - break; - - case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1U): - freq = freq >> 1U; - break; - - default: - break; - } - - switch (CCM_ANALOG->MISC2 & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) - { - case CCM_ANALOG_MISC2_VIDEO_DIV(3): - freq >>= 2U; - break; - - case CCM_ANALOG_MISC2_VIDEO_DIV(1): - freq >>= 1U; - break; - - default: - break; - } - break; - case kCLOCK_PllEnet: - divSelect = - (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT; - freq = enetRefClkFreq[divSelect]; - break; - - case kCLOCK_PllEnet25M: - /* ref_enetpll1 if fixed at 25MHz. */ - freq = 25000000UL; - break; - - case kCLOCK_PllUsb2: - freq = (freq * ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) ? 22U : 20U)); - break; - default: - freq = 0U; - break; - } - - return freq; -} - -void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac) -{ - uint32_t pfdIndex = (uint32_t)pfd; - uint32_t pfd528; - - pfd528 = CCM_ANALOG->PFD_528 & - ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex)); - - /* Disable the clock output first. */ - CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfdIndex)); - - /* Set the new value and enable output. */ - CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); -} - -void CLOCK_DeinitSysPfd(clock_pfd_t pfd) -{ - CCM_ANALOG->PFD_528 |= CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfd); -} - -void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac) -{ - uint32_t pfdIndex = (uint32_t)pfd; - uint32_t pfd480; - - pfd480 = CCM_ANALOG->PFD_480 & - ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex)); - - /* Disable the clock output first. */ - CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfdIndex)); - - /* Set the new value and enable output. */ - CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); -} - -void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd) -{ - CCM_ANALOG->PFD_480 |= CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfd); -} - -uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd) -{ - uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys); - - switch (pfd) - { - case kCLOCK_Pfd0: - freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT); - break; - - case kCLOCK_Pfd1: - freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT); - break; - - case kCLOCK_Pfd2: - freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT); - break; - - case kCLOCK_Pfd3: - freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT); - break; - - default: - freq = 0U; - break; - } - freq *= 18U; - - return freq; -} - -uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd) -{ - uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); - - switch (pfd) - { - case kCLOCK_Pfd0: - freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT); - break; - - case kCLOCK_Pfd1: - freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT); - break; - - case kCLOCK_Pfd2: - freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT); - break; - - case kCLOCK_Pfd3: - freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT); - break; - - default: - freq = 0U; - break; - } - freq *= 18U; - - return freq; -} - -bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) -{ - const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; - CLOCK_InitUsb2Pll(&g_ccmConfigUsbPll); - USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ - USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; - - USBPHY2->PWD = 0; - USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | - USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; - - return true; -} - -void CLOCK_DisableUsbhs1PhyPllClock(void) -{ - CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; - USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_clock.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_clock.h deleted file mode 100644 index 52fd227e2e..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_clock.h +++ /dev/null @@ -1,1466 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_CLOCK_H_ -#define _FSL_CLOCK_H_ - -#include "fsl_common.h" - -/*! @addtogroup clock */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Configurations - ******************************************************************************/ - -/*! @brief Configure whether driver controls clock - * - * When set to 0, peripheral drivers will enable clock in initialize function - * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could contol the clock out of - * the driver. - * - * @note All drivers share this feature switcher. If it is set to 1, application - * should handle clock enable and disable for all drivers. - */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) -#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CLOCK driver version 2.1.2. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) - -/* analog pll definition */ -#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) - -/*@}*/ -#define CCM_TUPLE(reg, shift, mask, busyShift) \ - ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | \ - ((busyShift) << 26U)) -#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU)))) -#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) -#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) -#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) - -#define CCM_NO_BUSY_WAIT (0x20U) - -/*! - * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields. - */ -#define CCM_ANALOG_TUPLE(reg, shift) ((((uint32_t)(&((CCM_ANALOG_Type *)0U)->reg) & 0xFFFU) << 16U) | (shift)) -#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU) -#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \ - (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off))) -#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U) - -/*! - * @brief clock1PN frequency. - */ -#define CLKPN_FREQ 0U - -/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency. - * - * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the - * function CLOCK_SetXtalFreq to set the value in to clock driver. For example, - * if XTAL is 24MHz, - * @code - * CLOCK_InitExternalClk(false); // Setup the 24M OSC/SYSOSC - * CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver. - * @endcode - */ -extern uint32_t g_xtalFreq; - -/*! @brief External RTC XTAL (32K OSC) clock frequency. - * - * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the - * function CLOCK_SetRtcXtalFreq to set the value in to clock driver. - */ -extern uint32_t g_rtcXtalFreq; - -/* For compatible with other platforms */ -#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq -#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq - -/*! @brief Clock ip name array for ADC. */ -#define ADC_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \ - } - -/*! @brief Clock ip name array for AOI. */ -#define AOI_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \ - } - -/*! @brief Clock ip name array for BEE. */ -#define BEE_CLOCKS \ - { \ - kCLOCK_Bee \ - } - -/*! @brief Clock ip name array for CMP. */ -#define CMP_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \ - } - -/*! @brief Clock ip name array for CSI. */ -#define CSI_CLOCKS \ - { \ - kCLOCK_Csi \ - } - -/*! @brief Clock ip name array for DCDC. */ -#define DCDC_CLOCKS \ - { \ - kCLOCK_Dcdc \ - } - -/*! @brief Clock ip name array for DCP. */ -#define DCP_CLOCKS \ - { \ - kCLOCK_Dcp \ - } - -/*! @brief Clock ip name array for DMAMUX_CLOCKS. */ -#define DMAMUX_CLOCKS \ - { \ - kCLOCK_Dma \ - } - -/*! @brief Clock ip name array for DMA. */ -#define EDMA_CLOCKS \ - { \ - kCLOCK_Dma \ - } - -/*! @brief Clock ip name array for ENC. */ -#define ENC_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \ - } - -/*! @brief Clock ip name array for ENET. */ -#define ENET_CLOCKS \ - { \ - kCLOCK_Enet \ - } - -/*! @brief Clock ip name array for EWM. */ -#define EWM_CLOCKS \ - { \ - kCLOCK_Ewm0 \ - } - -/*! @brief Clock ip name array for FLEXCAN. */ -#define FLEXCAN_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \ - } - -/*! @brief Clock ip name array for FLEXCAN Peripheral clock. */ -#define FLEXCAN_PERIPH_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \ - } - -/*! @brief Clock ip name array for FLEXIO. */ -#define FLEXIO_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ - } - -/*! @brief Clock ip name array for FLEXRAM. */ -#define FLEXRAM_CLOCKS \ - { \ - kCLOCK_FlexRam \ - } - -/*! @brief Clock ip name array for FLEXSPI. */ -#define FLEXSPI_CLOCKS \ - { \ - kCLOCK_FlexSpi \ - } - -/*! @brief Clock ip name array for FLEXSPI EXSC. */ -#define FLEXSPI_EXSC_CLOCKS \ - { \ - kCLOCK_FlexSpiExsc \ - } - -/*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ - } - -/*! @brief Clock ip name array for GPT. */ -#define GPT_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ - } - -/*! @brief Clock ip name array for KPP. */ -#define KPP_CLOCKS \ - { \ - kCLOCK_Kpp \ - } - -/*! @brief Clock ip name array for LCDIF. */ -#define LCDIF_CLOCKS \ - { \ - kCLOCK_Lcd \ - } - -/*! @brief Clock ip name array for LCDIF PIXEL. */ -#define LCDIF_PERIPH_CLOCKS \ - { \ - kCLOCK_LcdPixel \ - } - -/*! @brief Clock ip name array for LPI2C. */ -#define LPI2C_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \ - } - -/*! @brief Clock ip name array for LPSPI. */ -#define LPSPI_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \ - } - -/*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ - kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \ - } - -/*! @brief Clock ip name array for MQS. */ -#define MQS_CLOCKS \ - { \ - kCLOCK_Mqs \ - } - -/*! @brief Clock ip name array for OCRAM EXSC. */ -#define OCRAM_EXSC_CLOCKS \ - { \ - kCLOCK_OcramExsc \ - } - -/*! @brief Clock ip name array for PIT. */ -#define PIT_CLOCKS \ - { \ - kCLOCK_Pit \ - } - -/*! @brief Clock ip name array for PWM. */ -#define PWM_CLOCKS \ - { \ - { \ - kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid \ - } \ - , {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \ - {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \ - { \ - kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \ - } \ - } - -/*! @brief Clock ip name array for PXP. */ -#define PXP_CLOCKS \ - { \ - kCLOCK_Pxp \ - } - -/*! @brief Clock ip name array for RTWDOG. */ -#define RTWDOG_CLOCKS \ - { \ - kCLOCK_Wdog3 \ - } - -/*! @brief Clock ip name array for SAI. */ -#define SAI_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \ - } - -/*! @brief Clock ip name array for SEMC. */ -#define SEMC_CLOCKS \ - { \ - kCLOCK_Semc \ - } - -/*! @brief Clock ip name array for SEMC EXSC. */ -#define SEMC_EXSC_CLOCKS \ - { \ - kCLOCK_SemcExsc \ - } - -/*! @brief Clock ip name array for QTIMER. */ -#define TMR_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ - } - -/*! @brief Clock ip name array for TRNG. */ -#define TRNG_CLOCKS \ - { \ - kCLOCK_Trng \ - } - -/*! @brief Clock ip name array for TSC. */ -#define TSC_CLOCKS \ - { \ - kCLOCK_Tsc \ - } - -/*! @brief Clock ip name array for WDOG. */ -#define WDOG_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \ - } - -/*! @brief Clock ip name array for USDHC. */ -#define USDHC_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ - } - -/*! @brief Clock ip name array for SPDIF. */ -#define SPDIF_CLOCKS \ - { \ - kCLOCK_Spdif \ - } - -/*! @brief Clock ip name array for XBARA. */ -#define XBARA_CLOCKS \ - { \ - kCLOCK_Xbar1 \ - } - -/*! @brief Clock ip name array for XBARB. */ -#define XBARB_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \ - } - -/*! @brief Clock name used to get clock frequency. */ -typedef enum _clock_name -{ - kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ - kCLOCK_AhbClk = 0x1U, /*!< AHB clock */ - kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */ - kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ - - kCLOCK_OscClk = 0x4U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ - kCLOCK_RtcClk = 0x5U, /*!< RTC clock. (RTCCLK) */ - - kCLOCK_ArmPllClk = 0x6U, /*!< ARMPLLCLK. */ - - kCLOCK_Usb1PllClk = 0x7U, /*!< USB1PLLCLK. */ - kCLOCK_Usb1PllPfd0Clk = 0x8U, /*!< USB1PLLPDF0CLK. */ - kCLOCK_Usb1PllPfd1Clk = 0x9U, /*!< USB1PLLPFD1CLK. */ - kCLOCK_Usb1PllPfd2Clk = 0xAU, /*!< USB1PLLPFD2CLK. */ - kCLOCK_Usb1PllPfd3Clk = 0xBU, /*!< USB1PLLPFD3CLK. */ - - kCLOCK_Usb2PllClk = 0xCU, /*!< USB2PLLCLK. */ - - kCLOCK_SysPllClk = 0xDU, /*!< SYSPLLCLK. */ - kCLOCK_SysPllPfd0Clk = 0xEU, /*!< SYSPLLPDF0CLK. */ - kCLOCK_SysPllPfd1Clk = 0xFU, /*!< SYSPLLPFD1CLK. */ - kCLOCK_SysPllPfd2Clk = 0x10U, /*!< SYSPLLPFD2CLK. */ - kCLOCK_SysPllPfd3Clk = 0x11U, /*!< SYSPLLPFD3CLK. */ - - kCLOCK_EnetPll0Clk = 0x12U, /*!< Enet PLLCLK ref_enetpll0. */ - kCLOCK_EnetPll1Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll1. */ - - kCLOCK_AudioPllClk = 0x14U, /*!< Audio PLLCLK. */ - kCLOCK_VideoPllClk = 0x15U, /*!< Video PLLCLK. */ -} clock_name_t; - -#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */ -#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */ - -/*! - * @brief CCM CCGR gate control for each module independently. - */ -typedef enum _clock_ip_name -{ - kCLOCK_IpInvalid = -1, - - /* CCM CCGR0 */ - kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */ - kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */ - kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */ - kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */ - kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */ - kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */ - kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */ - kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */ - kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */ - kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */ - kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */ - kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */ - kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */ - kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */ - kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */ - kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */ - - /* CCM CCGR1 */ - kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */ - kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */ - kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */ - kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */ - kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */ - kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */ - kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */ - kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */ - kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */ - kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */ - kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */ - kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */ - kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */ - kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */ - kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */ - kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */ - - /* CCM CCGR2 */ - kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */ - kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */ - kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */ - kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */ - kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */ - kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */ - kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */ - kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */ - kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */ - kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */ - kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */ - kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */ - kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */ - kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */ - kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */ - kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */ - - /* CCM CCGR3 */ - kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */ - kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */ - kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */ - kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */ - kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */ - kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */ - kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */ - kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */ - kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */ - kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */ - kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */ - kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */ - kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */ - kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */ - kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */ - kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */ - - /* CCM CCGR4 */ - kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */ - kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */ - kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */ - kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */ - kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */ - kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */ - kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */ - kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */ - kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */ - kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */ - kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */ - kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */ - kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */ - kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */ - kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */ - - /* CCM CCGR5 */ - kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */ - kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */ - kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */ - kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */ - kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */ - kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */ - kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */ - kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */ - kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */ - kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */ - kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */ - kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */ - kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */ - kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */ - kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */ - kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */ - - /* CCM CCGR6 */ - kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */ - kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */ - kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */ - kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */ - kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */ - kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */ - kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */ - kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */ - kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */ - kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */ - kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */ - kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */ - kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */ - kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */ - kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */ - kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */ - -} clock_ip_name_t; - -/*! @brief OSC 24M sorce select */ -typedef enum _clock_osc -{ - kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ - kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ -} clock_osc_t; - -/*! @brief Clock gate value */ -typedef enum _clock_gate_value -{ - kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ - kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ - kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ -} clock_gate_value_t; - -/*! @brief System clock mode */ -typedef enum _clock_mode_t -{ - kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ - kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ - kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ -} clock_mode_t; - -/*! - * @brief MUX control names for clock mux setting. - * - * These constants define the mux control names for clock mux setting.\n - * - 0:7: REG offset to CCM_BASE in bytes. - * - 8:15: Root clock setting bit field shift. - * - 16:31: Root clock setting bit field width. - */ -typedef enum _clock_mux -{ - kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR, - CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, - CCM_CCSR_PLL3_SW_CLK_SEL_MASK, - CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */ - - kCLOCK_PeriphMux = CCM_TUPLE(CBCDR, - CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, - CCM_CBCDR_PERIPH_CLK_SEL_MASK, - CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ - kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR, - CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT, - CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK, - CCM_NO_BUSY_WAIT), /*!< semc mux name */ - kCLOCK_SemcMux = CCM_TUPLE( - CBCDR, CCM_CBCDR_SEMC_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< semc mux name */ - - kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR, - CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, - CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, - CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ - kCLOCK_TraceMux = CCM_TUPLE( - CBCMR, CCM_CBCMR_TRACE_CLK_SEL_SHIFT, CCM_CBCMR_TRACE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< trace mux name */ - kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR, - CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, - CCM_CBCMR_PERIPH_CLK2_SEL_MASK, - CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ - kCLOCK_LpspiMux = CCM_TUPLE( - CBCMR, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi mux name */ - - kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1, - CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT, - CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK, - CCM_NO_BUSY_WAIT), /*!< flexspi mux name */ - kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1, - CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT, - CCM_CSCMR1_USDHC2_CLK_SEL_MASK, - CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */ - kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1, - CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, - CCM_CSCMR1_USDHC1_CLK_SEL_MASK, - CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */ - kCLOCK_Sai3Mux = CCM_TUPLE( - CSCMR1, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ - kCLOCK_Sai2Mux = CCM_TUPLE( - CSCMR1, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ - kCLOCK_Sai1Mux = CCM_TUPLE( - CSCMR1, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ - kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1, - CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, - CCM_CSCMR1_PERCLK_CLK_SEL_MASK, - CCM_NO_BUSY_WAIT), /*!< perclk mux name */ - - kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2, - CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT, - CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK, - CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */ - kCLOCK_CanMux = CCM_TUPLE( - CSCMR2, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< can mux name */ - - kCLOCK_UartMux = CCM_TUPLE( - CSCDR1, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< uart mux name */ - - kCLOCK_SpdifMux = CCM_TUPLE( - CDCDR, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< spdif mux name */ - kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR, - CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT, - CCM_CDCDR_FLEXIO1_CLK_SEL_MASK, - CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */ - - kCLOCK_Lpi2cMux = CCM_TUPLE( - CSCDR2, CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, CCM_CSCDR2_LPI2C_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */ - kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2, - CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT, - CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK, - CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */ - - kCLOCK_CsiMux = CCM_TUPLE( - CSCDR3, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< csi mux name */ -} clock_mux_t; - -/*! - * @brief DIV control names for clock div setting. - * - * These constants define div control names for clock div setting.\n - * - 0:7: REG offset to CCM_BASE in bytes. - * - 8:15: Root clock setting bit field shift. - * - 16:31: Root clock setting bit field width. - */ -typedef enum _clock_div -{ - kCLOCK_ArmDiv = CCM_TUPLE( - CACRR, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ - - kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR, - CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, - CCM_CBCDR_PERIPH_CLK2_PODF_MASK, - CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ - kCLOCK_SemcDiv = CCM_TUPLE(CBCDR, - CCM_CBCDR_SEMC_PODF_SHIFT, - CCM_CBCDR_SEMC_PODF_MASK, - CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */ - kCLOCK_AhbDiv = CCM_TUPLE( - CBCDR, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ - kCLOCK_IpgDiv = - CCM_TUPLE(CBCDR, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ - - kCLOCK_LpspiDiv = CCM_TUPLE( - CBCMR, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */ - kCLOCK_LcdifDiv = CCM_TUPLE( - CBCMR, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */ - - kCLOCK_FlexspiDiv = CCM_TUPLE( - CSCMR1, CCM_CSCMR1_FLEXSPI_PODF_SHIFT, CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexspi div name */ - kCLOCK_PerclkDiv = CCM_TUPLE( - CSCMR1, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< perclk div name */ - - kCLOCK_CanDiv = CCM_TUPLE( - CSCMR2, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< can div name */ - - kCLOCK_TraceDiv = CCM_TUPLE( - CSCDR1, CCM_CSCDR1_TRACE_PODF_SHIFT, CCM_CSCDR1_TRACE_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< trace div name */ - kCLOCK_Usdhc2Div = CCM_TUPLE( - CSCDR1, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */ - kCLOCK_Usdhc1Div = CCM_TUPLE( - CSCDR1, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */ - kCLOCK_UartDiv = CCM_TUPLE( - CSCDR1, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< uart div name */ - - kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR, - CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT, - CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK, - CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */ - kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR, - CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, - CCM_CS1CDR_SAI3_CLK_PRED_MASK, - CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ - kCLOCK_Sai3Div = CCM_TUPLE( - CS1CDR, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 div name */ - kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR, - CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT, - CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK, - CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ - kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR, - CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, - CCM_CS1CDR_SAI1_CLK_PRED_MASK, - CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ - kCLOCK_Sai1Div = CCM_TUPLE( - CS1CDR, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 div name */ - - kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR, - CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, - CCM_CS2CDR_SAI2_CLK_PRED_MASK, - CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ - kCLOCK_Sai2Div = CCM_TUPLE( - CS2CDR, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 div name */ - - kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR, - CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, - CCM_CDCDR_SPDIF0_CLK_PRED_MASK, - CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ - kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR, - CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, - CCM_CDCDR_SPDIF0_CLK_PODF_MASK, - CCM_NO_BUSY_WAIT), /*!< spdif div name */ - kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR, - CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT, - CCM_CDCDR_FLEXIO1_CLK_PRED_MASK, - CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */ - kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR, - CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT, - CCM_CDCDR_FLEXIO1_CLK_PODF_MASK, - CCM_NO_BUSY_WAIT), /*!< flexio1 div name */ - - kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2, - CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT, - CCM_CSCDR2_LPI2C_CLK_PODF_MASK, - CCM_NO_BUSY_WAIT), /*!< lpi2c div name */ - kCLOCK_LcdifPreDiv = CCM_TUPLE( - CSCDR2, CCM_CSCDR2_LCDIF_PRED_SHIFT, CCM_CSCDR2_LCDIF_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */ - - kCLOCK_CsiDiv = - CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */ -} clock_div_t; - -/*! @brief USB clock source definition. */ -typedef enum _clock_usb_src -{ - kCLOCK_Usb480M = 0, /*!< Use 480M. */ - kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not - care the clock source. */ -} clock_usb_src_t; - -/*! @brief Source of the USB HS PHY. */ -typedef enum _clock_usb_phy_src -{ - kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ -} clock_usb_phy_src_t; - -/*!@brief PLL clock source, bypass cloco source also */ -enum _clock_pll_clk_src -{ - kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */ - kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */ -}; - -/*! @brief PLL configuration for ARM */ -typedef struct _clock_arm_pll_config -{ - uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */ - uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ -} clock_arm_pll_config_t; - -/*! @brief PLL configuration for USB */ -typedef struct _clock_usb_pll_config -{ - uint8_t loopDivider; /*!< PLL loop divider. - 0 - Fout=Fref*20; - 1 - Fout=Fref*22 */ - uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ - -} clock_usb_pll_config_t; - -/*! @brief PLL configuration for System */ -typedef struct _clock_sys_pll_config -{ - uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). - 0 - Fout=Fref*20; - 1 - Fout=Fref*22 */ - uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ - uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ - uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ - -} clock_sys_pll_config_t; - -/*! @brief PLL configuration for AUDIO and VIDEO */ -typedef struct _clock_audio_pll_config -{ - uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ - uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ - uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ - uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ - uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ -} clock_audio_pll_config_t; - -/*! @brief PLL configuration for AUDIO and VIDEO */ -typedef struct _clock_video_pll_config -{ - uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ - uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ - uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ - uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ - uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ - -} clock_video_pll_config_t; - -/*! @brief PLL configuration for ENET */ -typedef struct _clock_enet_pll_config -{ - bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ - - bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ - uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock. - b00 25MHz - b01 50MHz - b10 100MHz (not 50% duty cycle) - b11 125MHz */ - uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ - -} clock_enet_pll_config_t; - -/*! @brief PLL name */ -typedef enum _clock_pll -{ - kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */ - kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */ - kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */ - kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */ - kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */ - - kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */ - - kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */ - - kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */ - -} clock_pll_t; - -/*! @brief PLL PFD name */ -typedef enum _clock_pfd -{ - kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ - kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ - kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ - kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ -} clock_pfd_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief Set CCM MUX node to certain value. - * - * @param mux Which mux node to set, see \ref clock_mux_t. - * @param value Clock mux value to set, different mux has different value range. - */ -static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value) -{ - uint32_t busyShift; - - busyShift = CCM_TUPLE_BUSY_SHIFT(mux); - CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | - (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); - - assert(busyShift <= CCM_NO_BUSY_WAIT); - - /* Clock switch need Handshake? */ - if (CCM_NO_BUSY_WAIT != busyShift) - { - /* Wait until CCM internal handshake finish. */ - while (CCM->CDHIPR & (1U << busyShift)) - { - } - } -} - -/*! - * @brief Get CCM MUX value. - * - * @param mux Which mux node to get, see \ref clock_mux_t. - * @return Clock mux value. - */ -static inline uint32_t CLOCK_GetMux(clock_mux_t mux) -{ - return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux); -} - -/*! - * @brief Set CCM DIV node to certain value. - * - * @param divider Which div node to set, see \ref clock_div_t. - * @param value Clock div value to set, different divider has different value range. - */ -static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) -{ - uint32_t busyShift; - - busyShift = CCM_TUPLE_BUSY_SHIFT(divider); - CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | - (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); - - assert(busyShift <= CCM_NO_BUSY_WAIT); - - /* Clock switch need Handshake? */ - if (CCM_NO_BUSY_WAIT != busyShift) - { - /* Wait until CCM internal handshake finish. */ - while (CCM->CDHIPR & (1U << busyShift)) - { - } - } -} - -/*! - * @brief Get CCM DIV node value. - * - * @param divider Which div node to get, see \ref clock_div_t. - */ -static inline uint32_t CLOCK_GetDiv(clock_div_t divider) -{ - return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider)); -} - -/*! - * @brief Control the clock gate for specific IP. - * - * @param name Which clock to enable, see \ref clock_ip_name_t. - * @param value Clock gate value to set, see \ref clock_gate_value_t. - */ -static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) -{ - uint32_t index = ((uint32_t)name) >> 8U; - uint32_t shift = ((uint32_t)name) & 0x1FU; - volatile uint32_t *reg; - - assert(index <= 6); - - reg = ((volatile uint32_t *)&CCM->CCGR0) + index; - *reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift); -} - -/*! - * @brief Enable the clock for specific IP. - * - * @param name Which clock to enable, see \ref clock_ip_name_t. - */ -static inline void CLOCK_EnableClock(clock_ip_name_t name) -{ - CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait); -} - -/*! - * @brief Disable the clock for specific IP. - * - * @param name Which clock to disable, see \ref clock_ip_name_t. - */ -static inline void CLOCK_DisableClock(clock_ip_name_t name) -{ - CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded); -} - -/*! - * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal. - * - * @param mode Which mode to enter, see \ref clock_mode_t. - */ -static inline void CLOCK_SetMode(clock_mode_t mode) -{ - CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode); -} - -/*! - * @brief Gets the OSC clock frequency. - * - * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, - * otherwise internal 24MHz RC OSC frequency will be returned. - * - * @param osc OSC type to get frequency. - * - * @return Clock frequency; If the clock is invalid, returns 0. - */ -static inline uint32_t CLOCK_GetOscFreq(void) -{ - return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq; -} - -/*! - * @brief Gets the clock frequency for a specific clock name. - * - * This function checks the current clock configurations and then calculates - * the clock frequency for a specific clock name defined in clock_name_t. - * - * @param clockName Clock names defined in clock_name_t - * @return Clock frequency value in hertz - */ -uint32_t CLOCK_GetFreq(clock_name_t name); - -/*! - * @brief Get the CCM CPU/core/system frequency. - * - * @return Clock frequency; If the clock is invalid, returns 0. - */ -static inline uint32_t CLOCK_GetCpuClkFreq(void) -{ - return CLOCK_GetFreq(kCLOCK_CpuClk); -} - -/*! - * @name OSC operations - * @{ - */ - -/*! - * @brief Initialize the external 24MHz clock. - * - * This function supports two modes: - * 1. Use external crystal oscillator. - * 2. Bypass the external crystal oscillator, using input source clock directly. - * - * After this function, please call @ref CLOCK_SetXtal0Freq to inform clock driver - * the external clock frequency. - * - * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator. - * @note This device does not support bypass external crystal oscillator, so - * the input parameter should always be false. - */ -void CLOCK_InitExternalClk(bool bypassXtalOsc); - -/*! - * @brief Deinitialize the external 24MHz clock. - * - * This function disables the external 24MHz clock. - * - * After this function, please call @ref CLOCK_SetXtal0Freq to set external clock - * frequency to 0. - */ -void CLOCK_DeinitExternalClk(void); - -/*! - * @brief Switch the OSC. - * - * This function switches the OSC source for SoC. - * - * @param osc OSC source to switch to. - */ -void CLOCK_SwitchOsc(clock_osc_t osc); - -/*! - * @brief Gets the RTC clock frequency. - * - * @return Clock frequency; If the clock is invalid, returns 0. - */ -static inline uint32_t CLOCK_GetRtcFreq(void) -{ - return 32768U; -} - -/*! - * @brief Set the XTAL (24M OSC) frequency based on board setting. - * - * @param freq The XTAL input clock frequency in Hz. - */ -static inline void CLOCK_SetXtalFreq(uint32_t freq) -{ - g_xtalFreq = freq; -} - -/*! - * @brief Set the RTC XTAL (32K OSC) frequency based on board setting. - * - * @param freq The RTC XTAL input clock frequency in Hz. - */ -static inline void CLOCK_SetRtcXtalFreq(uint32_t freq) -{ - g_rtcXtalFreq = freq; -} - -/*! - * @brief Initialize the RC oscillator 24MHz clock. - */ -void CLOCK_InitRcOsc24M(void); - -/*! - * @brief Power down the RCOSC 24M clock. - */ -void CLOCK_DeinitRcOsc24M(void); -/* @} */ - - -/*! @brief Enable USB HS clock. - * - * This function only enables the access to USB HS prepheral, upper layer - * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY - * clock to use USB HS. - * - * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. - * @param freq USB HS does not care about the clock source, so this parameter is ignored. - * @retval true The clock is set successfully. - * @retval false The clock source is invalid to get proper USB HS clock. - */ -bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); - -/*! @brief Enable USB HS clock. - * - * This function only enables the access to USB HS prepheral, upper layer - * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY - * clock to use USB HS. - * - * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. - * @param freq USB HS does not care about the clock source, so this parameter is ignored. - * @retval true The clock is set successfully. - * @retval false The clock source is invalid to get proper USB HS clock. - */ -bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); - -/*! @brief Disable USB HS PHY PLL clock. - * - * This function disables USB HS PHY PLL clock. - */ -void CLOCK_DisableUsbhs1PhyPllClock(void); - -/* @} */ - -/*! - * @name PLL/PFD operations - * @{ - */ -/*! - * @brief PLL bypass setting - * - * @param base CCM_ANALOG base pointer. - * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) - * @param bypass Bypass the PLL. - * - true: Bypass the PLL. - * - false:Not bypass the PLL. - */ -static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass) -{ - if (bypass) - { - CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; - } - else - { - CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; - } -} - -/*! - * @brief Check if PLL is bypassed - * - * @param base CCM_ANALOG base pointer. - * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) - * @return PLL bypass status. - * - true: The PLL is bypassed. - * - false: The PLL is not bypassed. - */ -static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll) -{ - return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_PLL_BYPASS_SHIFT)); -} - -/*! - * @brief Check if PLL is enabled - * - * @param base CCM_ANALOG base pointer. - * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) - * @return PLL bypass status. - * - true: The PLL is enabled. - * - false: The PLL is not enabled. - */ -static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll) -{ - return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_TUPLE_SHIFT(pll))); -} - -/*! - * @brief PLL bypass clock source setting. - * Note: change the bypass clock source also change the pll reference clock source. - * - * @param base CCM_ANALOG base pointer. - * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) - * @param src Bypass clock source, reference _clock_pll_bypass_clk_src. - */ -static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src) -{ - CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src; -} - -/*! - * @brief Get PLL bypass clock value, it is PLL reference clock actually. - * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 - * will be returned. - * @param base CCM_ANALOG base pointer. - * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) - * @retval bypass reference clock frequency value. - */ -static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll) -{ - return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >> - CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == kCLOCK_PllClkSrc24M) ? - CLOCK_GetOscFreq() : - CLKPN_FREQ; -} - -/*! - * @brief Initialize the ARM PLL. - * - * This function initialize the ARM PLL with specific settings - * - * @param config configuration to set to PLL. - */ -void CLOCK_InitArmPll(const clock_arm_pll_config_t *config); - -/*! - * @brief De-initialize the ARM PLL. - */ -void CLOCK_DeinitArmPll(void); - -/*! - * @brief Initialize the System PLL. - * - * This function initializes the System PLL with specific settings - * - * @param config Configuration to set to PLL. - */ -void CLOCK_InitSysPll(const clock_sys_pll_config_t *config); - -/*! - * @brief De-initialize the System PLL. - */ -void CLOCK_DeinitSysPll(void); - -/*! - * @brief Initialize the USB1 PLL. - * - * This function initializes the USB1 PLL with specific settings - * - * @param config Configuration to set to PLL. - */ -void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config); - -/*! - * @brief Deinitialize the USB1 PLL. - */ -void CLOCK_DeinitUsb1Pll(void); - -/*! - * @brief Initialize the USB2 PLL. - * - * This function initializes the USB2 PLL with specific settings - * - * @param config Configuration to set to PLL. - */ -void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config); - -/*! - * @brief Deinitialize the USB2 PLL. - */ -void CLOCK_DeinitUsb2Pll(void); - -/*! - * @brief Initializes the Audio PLL. - * - * This function initializes the Audio PLL with specific settings - * - * @param config Configuration to set to PLL. - */ -void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); - -/*! - * @brief De-initialize the Audio PLL. - */ -void CLOCK_DeinitAudioPll(void); - -/*! - * @brief Initialize the video PLL. - * - * This function configures the Video PLL with specific settings - * - * @param config configuration to set to PLL. - */ -void CLOCK_InitVideoPll(const clock_video_pll_config_t *config); - -/*! - * @brief De-initialize the Video PLL. - */ -void CLOCK_DeinitVideoPll(void); -/*! - * @brief Initialize the ENET PLL. - * - * This function initializes the ENET PLL with specific settings. - * - * @param config Configuration to set to PLL. - */ -void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config); - -/*! - * @brief Deinitialize the ENET PLL. - * - * This function disables the ENET PLL. - */ -void CLOCK_DeinitEnetPll(void); - -/*! - * @brief Get current PLL output frequency. - * - * This function get current output frequency of specific PLL - * - * @param pll pll name to get frequency. - * @return The PLL output frequency in hertz. - */ -uint32_t CLOCK_GetPllFreq(clock_pll_t pll); - -/*! - * @brief Initialize the System PLL PFD. - * - * This function initializes the System PLL PFD. During new value setting, - * the clock output is disabled to prevent glitch. - * - * @param pfd Which PFD clock to enable. - * @param pfdFrac The PFD FRAC value. - * @note It is recommended that PFD settings are kept between 12-35. - */ -void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac); - -/*! - * @brief De-initialize the System PLL PFD. - * - * This function disables the System PLL PFD. - * - * @param pfd Which PFD clock to disable. - */ -void CLOCK_DeinitSysPfd(clock_pfd_t pfd); - -/*! - * @brief Initialize the USB1 PLL PFD. - * - * This function initializes the USB1 PLL PFD. During new value setting, - * the clock output is disabled to prevent glitch. - * - * @param pfd Which PFD clock to enable. - * @param pfdFrac The PFD FRAC value. - * @note It is recommended that PFD settings are kept between 12-35. - */ -void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac); - -/*! - * @brief De-initialize the USB1 PLL PFD. - * - * This function disables the USB1 PLL PFD. - * - * @param pfd Which PFD clock to disable. - */ -void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd); - -/*! - * @brief Get current System PLL PFD output frequency. - * - * This function get current output frequency of specific System PLL PFD - * - * @param pfd pfd name to get frequency. - * @return The PFD output frequency in hertz. - */ -uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd); - -/*! - * @brief Get current USB1 PLL PFD output frequency. - * - * This function get current output frequency of specific USB1 PLL PFD - * - * @param pfd pfd name to get frequency. - * @return The PFD output frequency in hertz. - */ -uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd); - -/*! @brief Enable USB HS PHY PLL clock. - * - * This function enables the internal 480MHz USB PHY PLL clock. - * - * @param src USB HS PHY PLL clock source. - * @param freq The frequency specified by src. - * @retval true The clock is set successfully. - * @retval false The clock source is invalid to get proper USB HS clock. - */ -bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); - -/*! @brief Disable USB HS PHY PLL clock. - * - * This function disables USB HS PHY PLL clock. - */ -void CLOCK_DisableUsbhs0PhyPllClock(void); - -/*! @brief Enable USB HS PHY PLL clock. - * - * This function enables the internal 480MHz USB PHY PLL clock. - * - * @param src USB HS PHY PLL clock source. - * @param freq The frequency specified by src. - * @retval true The clock is set successfully. - * @retval false The clock source is invalid to get proper USB HS clock. - */ -bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); - -/*! @brief Disable USB HS PHY PLL clock. - * - * This function disables USB HS PHY PLL clock. - */ -void CLOCK_DisableUsbhs1PhyPllClock(void); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_CLOCK_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_cmp.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_cmp.c deleted file mode 100644 index 98039cd6f9..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_cmp.c +++ /dev/null @@ -1,295 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_cmp.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.cmp" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for CMP module. - * - * @param base CMP peripheral base address - */ -static uint32_t CMP_GetInstance(CMP_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to CMP bases for each instance. */ -static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to CMP clocks for each instance. */ -static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Codes - ******************************************************************************/ -static uint32_t CMP_GetInstance(CMP_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_cmpBases); instance++) - { - if (s_cmpBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_cmpBases)); - - return instance; -} - -void CMP_Init(CMP_Type *base, const cmp_config_t *config) -{ - assert(NULL != config); - - uint8_t tmp8; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Configure. */ - CMP_Enable(base, false); /* Disable the CMP module during configuring. */ - /* CMPx_CR1. */ - tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK); - if (config->enableHighSpeed) - { - tmp8 |= CMP_CR1_PMODE_MASK; - } - if (config->enableInvertOutput) - { - tmp8 |= CMP_CR1_INV_MASK; - } - if (config->useUnfilteredOutput) - { - tmp8 |= CMP_CR1_COS_MASK; - } - if (config->enablePinOut) - { - tmp8 |= CMP_CR1_OPE_MASK; - } -#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE - if (config->enableTriggerMode) - { - tmp8 |= CMP_CR1_TRIGM_MASK; - } - else - { - tmp8 &= ~CMP_CR1_TRIGM_MASK; - } -#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ - base->CR1 = tmp8; - - /* CMPx_CR0. */ - tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK; - tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode); - base->CR0 = tmp8; - - CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */ -} - -void CMP_Deinit(CMP_Type *base) -{ - /* Disable the CMP module. */ - CMP_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void CMP_GetDefaultConfig(cmp_config_t *config) -{ - assert(NULL != config); - - config->enableCmp = true; /* Enable the CMP module after initialization. */ - config->hysteresisMode = kCMP_HysteresisLevel0; - config->enableHighSpeed = false; - config->enableInvertOutput = false; - config->useUnfilteredOutput = false; - config->enablePinOut = false; -#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE - config->enableTriggerMode = false; -#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ -} - -void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel) -{ - uint8_t tmp8 = base->MUXCR; - - tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK); - tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel); - base->MUXCR = tmp8; -} - -#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA -void CMP_EnableDMA(CMP_Type *base, bool enable) -{ - uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ - - if (enable) - { - tmp8 |= CMP_SCR_DMAEN_MASK; - } - else - { - tmp8 &= ~CMP_SCR_DMAEN_MASK; - } - base->SCR = tmp8; -} -#endif /* FSL_FEATURE_CMP_HAS_DMA */ - -void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) -{ - assert(NULL != config); - - uint8_t tmp8; - -#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT - /* Choose the clock source for sampling. */ - if (config->enableSample) - { - base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ - } - else - { - base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */ - } -#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ - /* Set the filter count. */ - tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK; - tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount); - base->CR0 = tmp8; - /* Set the filter period. It is used as the divider to bus clock. */ - base->FPR = CMP_FPR_FILT_PER(config->filterPeriod); -} - -void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) -{ - uint8_t tmp8 = 0U; - - if (NULL == config) - { - /* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/ - base->DACCR = 0U; - return; - } - /* CMPx_DACCR. */ - tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */ - if (kCMP_VrefSourceVin2 == config->referenceVoltageSource) - { - tmp8 |= CMP_DACCR_VRSEL_MASK; - } - tmp8 |= CMP_DACCR_VOSEL(config->DACValue); - - base->DACCR = tmp8; -} - -void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) -{ - uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ - - if (0U != (kCMP_OutputRisingInterruptEnable & mask)) - { - tmp8 |= CMP_SCR_IER_MASK; - } - if (0U != (kCMP_OutputFallingInterruptEnable & mask)) - { - tmp8 |= CMP_SCR_IEF_MASK; - } - base->SCR = tmp8; -} - -void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) -{ - uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ - - if (0U != (kCMP_OutputRisingInterruptEnable & mask)) - { - tmp8 &= ~CMP_SCR_IER_MASK; - } - if (0U != (kCMP_OutputFallingInterruptEnable & mask)) - { - tmp8 &= ~CMP_SCR_IEF_MASK; - } - base->SCR = tmp8; -} - -uint32_t CMP_GetStatusFlags(CMP_Type *base) -{ - uint32_t ret32 = 0U; - - if (0U != (CMP_SCR_CFR_MASK & base->SCR)) - { - ret32 |= kCMP_OutputRisingEventFlag; - } - if (0U != (CMP_SCR_CFF_MASK & base->SCR)) - { - ret32 |= kCMP_OutputFallingEventFlag; - } - if (0U != (CMP_SCR_COUT_MASK & base->SCR)) - { - ret32 |= kCMP_OutputAssertEventFlag; - } - return ret32; -} - -void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask) -{ - uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ - - if (0U != (kCMP_OutputRisingEventFlag & mask)) - { - tmp8 |= CMP_SCR_CFR_MASK; - } - if (0U != (kCMP_OutputFallingEventFlag & mask)) - { - tmp8 |= CMP_SCR_CFF_MASK; - } - base->SCR = tmp8; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_cmp.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_cmp.h deleted file mode 100644 index e228413f0c..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_cmp.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_CMP_H_ -#define _FSL_CMP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup cmp - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CMP driver version 2.0.0. */ -#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! -* @brief Interrupt enable/disable mask. -*/ -enum _cmp_interrupt_enable -{ - kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */ - kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */ -}; - -/*! - * @brief Status flags' mask. - */ -enum _cmp_status_flags -{ - kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ - kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ - kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */ -}; - -/*! - * @brief CMP Hysteresis mode. - */ -typedef enum _cmp_hysteresis_mode -{ - kCMP_HysteresisLevel0 = 0U, /*!< Hysteresis level 0. */ - kCMP_HysteresisLevel1 = 1U, /*!< Hysteresis level 1. */ - kCMP_HysteresisLevel2 = 2U, /*!< Hysteresis level 2. */ - kCMP_HysteresisLevel3 = 3U, /*!< Hysteresis level 3. */ -} cmp_hysteresis_mode_t; - -/*! - * @brief CMP Voltage Reference source. - */ -typedef enum _cmp_reference_voltage_source -{ - kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as a resistor ladder network supply reference Vin. */ - kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as a resistor ladder network supply reference Vin. */ -} cmp_reference_voltage_source_t; - -/*! - * @brief Configures the comparator. - */ -typedef struct _cmp_config -{ - bool enableCmp; /*!< Enable the CMP module. */ - cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */ - bool enableHighSpeed; /*!< Enable High-speed (HS) comparison mode. */ - bool enableInvertOutput; /*!< Enable the inverted comparator output. */ - bool useUnfilteredOutput; /*!< Set the compare output(COUT) to equal COUTA(true) or COUT(false). */ - bool enablePinOut; /*!< The comparator output is available on the associated pin. */ -#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE - bool enableTriggerMode; /*!< Enable the trigger mode. */ -#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ -} cmp_config_t; - -/*! - * @brief Configures the filter. - */ -typedef struct _cmp_filter_config -{ -#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT - bool enableSample; /*!< Using the external SAMPLE as a sampling clock input or using a divided bus clock. */ -#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ - uint8_t filterCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter.*/ - uint8_t filterPeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. */ -} cmp_filter_config_t; - -/*! - * @brief Configures the internal DAC. - */ -typedef struct _cmp_dac_config -{ - cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */ - uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/ -} cmp_dac_config_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @name Initialization - * @{ - */ - -/*! - * @brief Initializes the CMP. - * - * This function initializes the CMP module. The operations included are as follows. - * - Enabling the clock for CMP module. - * - Configuring the comparator. - * - Enabling the CMP module. - * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for - * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP. - * - * @param base CMP peripheral base address. - * @param config Pointer to the configuration structure. - */ -void CMP_Init(CMP_Type *base, const cmp_config_t *config); - -/*! - * @brief De-initializes the CMP module. - * - * This function de-initializes the CMP module. The operations included are as follows. - * - Disabling the CMP module. - * - Disabling the clock for CMP module. - * - * This function disables the clock for the CMP. - * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the - * clock for the CMP, ensure that all the CMP instances are not used. - * - * @param base CMP peripheral base address. - */ -void CMP_Deinit(CMP_Type *base); - -/*! - * @brief Enables/disables the CMP module. - * - * @param base CMP peripheral base address. - * @param enable Enables or disables the module. - */ -static inline void CMP_Enable(CMP_Type *base, bool enable) -{ - if (enable) - { - base->CR1 |= CMP_CR1_EN_MASK; - } - else - { - base->CR1 &= ~CMP_CR1_EN_MASK; - } -} - -/*! -* @brief Initializes the CMP user configuration structure. -* -* This function initializes the user configuration structure to these default values. -* @code -* config->enableCmp = true; -* config->hysteresisMode = kCMP_HysteresisLevel0; -* config->enableHighSpeed = false; -* config->enableInvertOutput = false; -* config->useUnfilteredOutput = false; -* config->enablePinOut = false; -* config->enableTriggerMode = false; -* @endcode -* @param config Pointer to the configuration structure. -*/ -void CMP_GetDefaultConfig(cmp_config_t *config); - -/*! - * @brief Sets the input channels for the comparator. - * - * This function sets the input channels for the comparator. - * Note that two input channels cannot be set the same way in the application. When the user selects the same input - * from the analog mux to the positive and negative port, the comparator is disabled automatically. - * - * @param base CMP peripheral base address. - * @param positiveChannel Positive side input channel number. Available range is 0-7. - * @param negativeChannel Negative side input channel number. Available range is 0-7. - */ -void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel); - -/* @} */ - -/*! - * @name Advanced Features - * @{ - */ - -#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA -/*! - * @brief Enables/disables the DMA request for rising/falling events. - * - * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of - * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP - * if the DMA is disabled. - * - * @param base CMP peripheral base address. - * @param enable Enables or disables the feature. - */ -void CMP_EnableDMA(CMP_Type *base, bool enable); -#endif /* FSL_FEATURE_CMP_HAS_DMA */ - -#if defined(FSL_FEATURE_CMP_HAS_WINDOW_MODE) && FSL_FEATURE_CMP_HAS_WINDOW_MODE -/*! - * @brief Enables/disables the window mode. - * - * @param base CMP peripheral base address. - * @param enable Enables or disables the feature. - */ -static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable) -{ - if (enable) - { - base->CR1 |= CMP_CR1_WE_MASK; - } - else - { - base->CR1 &= ~CMP_CR1_WE_MASK; - } -} -#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */ - -#if defined(FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE) && FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE -/*! - * @brief Enables/disables the pass through mode. - * - * @param base CMP peripheral base address. - * @param enable Enables or disables the feature. - */ -static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable) -{ - if (enable) - { - base->MUXCR |= CMP_MUXCR_PSTM_MASK; - } - else - { - base->MUXCR &= ~CMP_MUXCR_PSTM_MASK; - } -} -#endif /* FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE */ - -/*! - * @brief Configures the filter. - * - * @param base CMP peripheral base address. - * @param config Pointer to the configuration structure. - */ -void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config); - -/*! - * @brief Configures the internal DAC. - * - * @param base CMP peripheral base address. - * @param config Pointer to the configuration structure. "NULL" disables the feature. - */ -void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config); - -/*! - * @brief Enables the interrupts. - * - * @param base CMP peripheral base address. - * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". - */ -void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask); - -/*! - * @brief Disables the interrupts. - * - * @param base CMP peripheral base address. - * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". - */ -void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Results - * @{ - */ - -/*! - * @brief Gets the status flags. - * - * @param base CMP peripheral base address. - * - * @return Mask value for the asserted flags. See "_cmp_status_flags". - */ -uint32_t CMP_GetStatusFlags(CMP_Type *base); - -/*! - * @brief Clears the status flags. - * - * @param base CMP peripheral base address. - * @param mask Mask value for the flags. See "_cmp_status_flags". - */ -void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask); - -/* @} */ -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_CMP_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_common.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_common.c deleted file mode 100644 index 903faf52b6..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_common.c +++ /dev/null @@ -1,192 +0,0 @@ -/* -* The Clear BSD License -* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP -* All rights reserved. -* -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted (subject to the limitations in the disclaimer below) provided -* that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_common.h" -#define SDK_MEM_MAGIC_NUMBER 12345U - -typedef struct _mem_align_control_block -{ - uint16_t identifier; /*!< Identifier for the memory control block. */ - uint16_t offset; /*!< offset from aligned adress to real address */ -} mem_align_cb_t; - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common" -#endif - - -#ifndef __GIC_PRIO_BITS -#if defined(ENABLE_RAM_VECTOR_TABLE) -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) -{ -/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) - extern uint32_t Image$$VECTOR_ROM$$Base[]; - extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; - -#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) -#elif defined(__ICCARM__) - extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; -#elif defined(__GNUC__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; - extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; - uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) */ - uint32_t n; - uint32_t ret; - uint32_t irqMaskValue; - - irqMaskValue = DisableGlobalIRQ(); - if (SCB->VTOR != (uint32_t)__VECTOR_RAM) - { - /* Copy the vector table from ROM to RAM */ - for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) - { - __VECTOR_RAM[n] = __VECTOR_TABLE[n]; - } - /* Point the VTOR to the position of vector table */ - SCB->VTOR = (uint32_t)__VECTOR_RAM; - } - - ret = __VECTOR_RAM[irq + 16]; - /* make sure the __VECTOR_RAM is noncachable */ - __VECTOR_RAM[irq + 16] = irqHandler; - - EnableGlobalIRQ(irqMaskValue); - -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif - - return ret; -} -#endif /* ENABLE_RAM_VECTOR_TABLE. */ -#endif /* __GIC_PRIO_BITS. */ - -#ifndef QN908XC_SERIES -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - -#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1)) - { - SYSCON->STARTERP1 = 1u << intNumber; - } -#else - { - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1u << intNumber; - } -#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */ - EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ -#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1)) - { - SYSCON->STARTERP1 &= ~(1u << intNumber); - } -#else - { - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERCLR[index] = 1u << intNumber; - } -#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */ -} -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -#endif /* QN908XC_SERIES */ - -void *SDK_Malloc(size_t size, size_t alignbytes) -{ - mem_align_cb_t *p_cb = NULL; - uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); - void *p_align_addr, *p_addr = malloc(alignedsize); - - if (!p_addr) - { - return NULL; - } - - p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); - - p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4); - p_cb->identifier = SDK_MEM_MAGIC_NUMBER; - p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; - - return (void *)p_align_addr; -} - -void SDK_Free(void *ptr) -{ - mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4); - - if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) - { - return; - } - - free((void *)((uint32_t)ptr - p_cb->offset)); -} - diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_common.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_common.h deleted file mode 100644 index a53dbc2713..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_common.h +++ /dev/null @@ -1,576 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ - -#include -#include -#include -#include -#include - -#if defined(__ICCARM__) -#include -#endif - -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) - -/*! @brief Construct the version number for drivers. */ -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) - -/*! @name Driver version */ -/*@{*/ -/*! @brief common driver version 2.0.0. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console base on LPC_USART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console base on SWO. */ - -/*! @brief Status group numbers. */ -enum _status_groups -{ - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ - kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ - kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ - kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ - kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ - kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ - kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ - kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ - kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ - kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ - kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ - kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ - kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ - kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ - kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ - kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ - kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ - kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ - kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ - kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ - kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */ - kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ - kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ - kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ - kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ - kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ -}; - -/*! @brief Generic status return codes. */ -enum _generic_status -{ - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), - kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - -/* - * Macro guard for whether to use default weak IRQ implementation in drivers - */ -#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 -#endif - -/*! @name Min/max macros */ -/* @{ */ -#if !defined(MIN) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#endif -/* @} */ - -/*! @brief Computes the number of elements in an array. */ -#if !defined(ARRAY_SIZE) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ -#if !defined(UINT16_MAX) -#define UINT16_MAX ((uint16_t)-1) -#endif - -#if !defined(UINT32_MAX) -#define UINT32_MAX ((uint32_t)-1) -#endif -/* @} */ - -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) -/* @} */ - -/*! @name Alignment variable definition macros */ -/* @{ */ -#if (defined(__ICCARM__)) -/** - * Workaround to disable MISRA C message suppress warnings for IAR compiler. - * http://supp.iar.com/Support/?note=24725 - */ -_Pragma("diag_suppress=Pm120") -#define SDK_PRAGMA(x) _Pragma(#x) - _Pragma("diag_error=Pm120") -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var -#endif -#elif defined(__ARMCC_VERSION) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var -#endif -#elif defined(__GNUC__) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) -#endif -#else -#error Toolchain not supported -#define SDK_ALIGN(var, alignbytes) var -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) var -#endif -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) var -#endif -#endif - -/*! Macro to change a value to a given size aligned value */ -#define SDK_SIZEALIGN(var, alignbytes) \ - ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) -/* @} */ - -/*! @name Non-cacheable region definition macros */ -/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or - * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, - * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables - * will be initialized to zero in system startup. - */ -/* @{ */ -#if (defined(__ICCARM__)) -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) -#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#endif -#elif(defined(__ARMCC_VERSION)) -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) __align(alignbytes) var -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var -#endif -#elif(defined(__GNUC__)) -/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" - * in your projects to make sure the non-cacheable section variables will be initialized in system startup. - */ -#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) -#endif -#else -#error Toolchain not supported. -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var -#endif -/* @} */ - -/*! @name Time sensitive region */ -/* @{ */ -#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" -#elif(defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func -#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func -#elif(defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func -#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ -#else -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#elif(defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#elif(defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#else -#error Toolchain not supported. -#endif -#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ -/* @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) - extern "C" -{ -#endif - - /*! - * @brief Enable specific interrupt. - * - * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt enabled successfully - * @retval kStatus_Fail Failed to enable the interrupt - */ - static inline status_t EnableIRQ(IRQn_Type interrupt) - { - if (NotAvail_IRQn == interrupt) - { - return kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - return kStatus_Fail; - } -#endif - -#if defined(__GIC_PRIO_BITS) - GIC_EnableIRQ(interrupt); -#else - NVIC_EnableIRQ(interrupt); -#endif - return kStatus_Success; - } - - /*! - * @brief Disable specific interrupt. - * - * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt disabled successfully - * @retval kStatus_Fail Failed to disable the interrupt - */ - static inline status_t DisableIRQ(IRQn_Type interrupt) - { - if (NotAvail_IRQn == interrupt) - { - return kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - return kStatus_Fail; - } -#endif - -#if defined(__GIC_PRIO_BITS) - GIC_DisableIRQ(interrupt); -#else - NVIC_DisableIRQ(interrupt); -#endif - return kStatus_Success; - } - - /*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ - static inline uint32_t DisableGlobalIRQ(void) - { -#if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - - __disable_irq(); - - return cpsr; -#else - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -#endif - } - - /*! - * @brief Enaable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ - static inline void EnableGlobalIRQ(uint32_t primask) - { -#if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); -#else - __set_PRIMASK(primask); -#endif - } - -#if defined(ENABLE_RAM_VECTOR_TABLE) - /*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ - uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); -#endif /* ENABLE_RAM_VECTOR_TABLE. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - /*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). - * - * @param interrupt The IRQ number. - */ - void EnableDeepSleepIRQ(IRQn_Type interrupt); - - /*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). - * - * @param interrupt The IRQ number. - */ - void DisableDeepSleepIRQ(IRQn_Type interrupt); -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - - /*! - * @brief Allocate memory with given alignment and aligned size. - * - * This is provided to support the dynamically allocated memory - * used in cache-able region. - * @param size The length required to malloc. - * @param alignbytes The alignment size. - * @retval The allocated memory. - */ - void *SDK_Malloc(size_t size, size_t alignbytes); - - /*! - * @brief Free memory. - * - * @param ptr The memory to be release. - */ - void SDK_Free(void *ptr); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_csi.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_csi.c deleted file mode 100644 index df993d29dc..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_csi.c +++ /dev/null @@ -1,694 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2017, NXP Semiconductors, Inc. - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_csi.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.csi" -#endif - - -/* Two frame buffer loaded to CSI register at most. */ -#define CSI_MAX_ACTIVE_FRAME_NUM 2 - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance from the base address - * - * @param base CSI peripheral base address - * - * @return The CSI module instance - */ -static uint32_t CSI_GetInstance(CSI_Type *base); - -/*! - * @brief Get the delta value of two index in queue. - * - * @param startIdx Start index. - * @param endIdx End index. - * - * @return The delta between startIdx and endIdx in queue. - */ -static uint32_t CSI_TransferGetQueueDelta(uint32_t startIdx, uint32_t endIdx); - -/*! - * @brief Increase a index value in queue. - * - * This function increases the index value in the queue, if the index is out of - * the queue range, it is reset to 0. - * - * @param idx The index value to increase. - * - * @return The index value after increase. - */ -static uint32_t CSI_TransferIncreaseQueueIdx(uint32_t idx); - -/*! - * @brief Get the empty frame buffer count in queue. - * - * @param base CSI peripheral base address - * @param handle Pointer to CSI driver handle. - * - * @return Number of the empty frame buffer count in queue. - */ -static uint32_t CSI_TransferGetEmptyBufferCount(CSI_Type *base, csi_handle_t *handle); - -/*! - * @brief Load one empty frame buffer in queue to CSI module. - * - * Load one empty frame in queue to CSI module, this function could only be called - * when there is empty frame buffer in queue. - * - * @param base CSI peripheral base address - * @param handle Pointer to CSI driver handle. - */ -static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle); - -/* Typedef for interrupt handler. */ -typedef void (*csi_isr_t)(CSI_Type *base, csi_handle_t *handle); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to CSI bases for each instance. */ -static CSI_Type *const s_csiBases[] = CSI_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to CSI clocks for each CSI submodule. */ -static const clock_ip_name_t s_csiClocks[] = CSI_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* Array for the CSI driver handle. */ -static csi_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)]; - -/* Array of CSI IRQ number. */ -static const IRQn_Type s_csiIRQ[] = CSI_IRQS; - -/* CSI ISR for transactional APIs. */ -static csi_isr_t s_csiIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t CSI_GetInstance(CSI_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_csiBases); instance++) - { - if (s_csiBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_csiBases)); - - return instance; -} - -static uint32_t CSI_TransferGetQueueDelta(uint32_t startIdx, uint32_t endIdx) -{ - if (endIdx >= startIdx) - { - return endIdx - startIdx; - } - else - { - return startIdx + CSI_DRIVER_ACTUAL_QUEUE_SIZE - endIdx; - } -} - -static uint32_t CSI_TransferIncreaseQueueIdx(uint32_t idx) -{ - uint32_t ret; - - /* - * Here not use the method: - * ret = (idx+1) % CSI_DRIVER_ACTUAL_QUEUE_SIZE; - * - * Because the mod function might be slow. - */ - - ret = idx + 1; - - if (ret >= CSI_DRIVER_ACTUAL_QUEUE_SIZE) - { - ret = 0; - } - - return ret; -} - -static uint32_t CSI_TransferGetEmptyBufferCount(CSI_Type *base, csi_handle_t *handle) -{ - return CSI_TransferGetQueueDelta(handle->queueDrvReadIdx, handle->queueUserWriteIdx); -} - -static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle) -{ - /* Load the frame buffer address to CSI register. */ - CSI_SetRxBufferAddr(base, handle->nextBufferIdx, handle->frameBufferQueue[handle->queueDrvReadIdx]); - - handle->queueDrvReadIdx = CSI_TransferIncreaseQueueIdx(handle->queueDrvReadIdx); - handle->activeBufferNum++; - - /* There are two CSI buffers, so could use XOR to get the next index. */ - handle->nextBufferIdx ^= 1U; -} - -status_t CSI_Init(CSI_Type *base, const csi_config_t *config) -{ - assert(config); - uint32_t reg; - uint32_t imgWidth_Bytes; - - imgWidth_Bytes = config->width * config->bytesPerPixel; - - /* The image width and frame buffer pitch should be multiple of 8-bytes. */ - if ((imgWidth_Bytes & 0x07) | ((uint32_t)config->linePitch_Bytes & 0x07)) - { - return kStatus_InvalidArgument; - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - uint32_t instance = CSI_GetInstance(base); - CLOCK_EnableClock(s_csiClocks[instance]); -#endif - - CSI_Reset(base); - - /* Configure CSICR1. CSICR1 has been reset to the default value, so could write it directly. */ - reg = ((uint32_t)config->workMode) | config->polarityFlags | CSI_CSICR1_FCC_MASK; - - if (config->useExtVsync) - { - reg |= CSI_CSICR1_EXT_VSYNC_MASK; - } - - base->CSICR1 = reg; - - /* - * Generally, CSIIMAG_PARA[IMAGE_WIDTH] indicates how many data bus cycles per line. - * One special case is when receiving 24-bit pixels through 8-bit data bus, and - * CSICR3[ZERO_PACK_EN] is enabled, in this case, the CSIIMAG_PARA[IMAGE_WIDTH] - * should be set to the pixel number per line. - * - * Currently the CSI driver only support 8-bit data bus, so generally the - * CSIIMAG_PARA[IMAGE_WIDTH] is bytes number per line. When the CSICR3[ZERO_PACK_EN] - * is enabled, CSIIMAG_PARA[IMAGE_WIDTH] is pixel number per line. - * - * NOTE: The CSIIMAG_PARA[IMAGE_WIDTH] setting code should be updated if the - * driver is upgraded to support other data bus width. - */ - if (4U == config->bytesPerPixel) - { - /* Enable zero pack. */ - base->CSICR3 |= CSI_CSICR3_ZERO_PACK_EN_MASK; - /* Image parameter. */ - base->CSIIMAG_PARA = ((uint32_t)(config->width) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT) | - ((uint32_t)(config->height) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT); - } - else - { - /* Image parameter. */ - base->CSIIMAG_PARA = ((uint32_t)(imgWidth_Bytes) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT) | - ((uint32_t)(config->height) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT); - } - - /* The CSI frame buffer bus is 8-byte width. */ - base->CSIFBUF_PARA = (uint32_t)((config->linePitch_Bytes - imgWidth_Bytes) / 8U) - << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT; - - /* Enable auto ECC. */ - base->CSICR3 |= CSI_CSICR3_ECC_AUTO_EN_MASK; - - /* - * For better performance. - * The DMA burst size could be set to 16 * 8 byte, 8 * 8 byte, or 4 * 8 byte, - * choose the best burst size based on bytes per line. - */ - if (!(imgWidth_Bytes % (8 * 16))) - { - base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(3U); - base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((2U << CSI_CSICR3_RxFF_LEVEL_SHIFT)); - } - else if (!(imgWidth_Bytes % (8 * 8))) - { - base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(2U); - base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((1U << CSI_CSICR3_RxFF_LEVEL_SHIFT)); - } - else - { - base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(1U); - base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((0U << CSI_CSICR3_RxFF_LEVEL_SHIFT)); - } - - CSI_ReflashFifoDma(base, kCSI_RxFifo); - - return kStatus_Success; -} - -void CSI_Deinit(CSI_Type *base) -{ - /* Disable transfer first. */ - CSI_Stop(base); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - uint32_t instance = CSI_GetInstance(base); - CLOCK_DisableClock(s_csiClocks[instance]); -#endif -} - -void CSI_Reset(CSI_Type *base) -{ - uint32_t csisr; - - /* Disable transfer first. */ - CSI_Stop(base); - - /* Disable DMA request. */ - base->CSICR3 = 0U; - - /* Reset the fame count. */ - base->CSICR3 |= CSI_CSICR3_FRMCNT_RST_MASK; - while (base->CSICR3 & CSI_CSICR3_FRMCNT_RST_MASK) - { - } - - /* Clear the RX FIFO. */ - CSI_ClearFifo(base, kCSI_AllFifo); - - /* Reflash DMA. */ - CSI_ReflashFifoDma(base, kCSI_AllFifo); - - /* Clear the status. */ - csisr = base->CSISR; - base->CSISR = csisr; - - /* Set the control registers to default value. */ - base->CSICR1 = CSI_CSICR1_HSYNC_POL_MASK | CSI_CSICR1_EXT_VSYNC_MASK; - base->CSICR2 = 0U; - base->CSICR3 = 0U; -#if defined(CSI_CSICR18_CSI_LCDIF_BUFFER_LINES) - base->CSICR18 = CSI_CSICR18_AHB_HPROT(0x0DU) | CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(0x02U); -#else - base->CSICR18 = CSI_CSICR18_AHB_HPROT(0x0DU); -#endif - base->CSIFBUF_PARA = 0U; - base->CSIIMAG_PARA = 0U; -} - -void CSI_GetDefaultConfig(csi_config_t *config) -{ - assert(config); - - config->width = 320U; - config->height = 240U; - config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge; - config->bytesPerPixel = 2U; - config->linePitch_Bytes = 320U * 2U; - config->workMode = kCSI_GatedClockMode; - config->dataBus = kCSI_DataBus8Bit; - config->useExtVsync = true; -} - -void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr) -{ - if (index) - { - base->CSIDMASA_FB2 = addr; - } - else - { - base->CSIDMASA_FB1 = addr; - } -} - -void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo) -{ - uint32_t cr1; - uint32_t mask = 0U; - - /* The FIFO could only be cleared when CSICR1[FCC] = 0, so first clear the FCC. */ - cr1 = base->CSICR1; - base->CSICR1 = (cr1 & ~CSI_CSICR1_FCC_MASK); - - if ((uint32_t)fifo & (uint32_t)kCSI_RxFifo) - { - mask |= CSI_CSICR1_CLR_RXFIFO_MASK; - } - - if ((uint32_t)fifo & (uint32_t)kCSI_StatFifo) - { - mask |= CSI_CSICR1_CLR_STATFIFO_MASK; - } - - base->CSICR1 = (cr1 & ~CSI_CSICR1_FCC_MASK) | mask; - - /* Wait clear completed. */ - while (base->CSICR1 & mask) - { - } - - /* Recover the FCC. */ - base->CSICR1 = cr1; -} - -void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo) -{ - uint32_t cr3 = 0U; - - if ((uint32_t)fifo & (uint32_t)kCSI_RxFifo) - { - cr3 |= CSI_CSICR3_DMA_REFLASH_RFF_MASK; - } - - if ((uint32_t)fifo & (uint32_t)kCSI_StatFifo) - { - cr3 |= CSI_CSICR3_DMA_REFLASH_SFF_MASK; - } - - base->CSICR3 |= cr3; - - /* Wait clear completed. */ - while (base->CSICR3 & cr3) - { - } -} - -void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable) -{ - uint32_t cr3 = 0U; - - if ((uint32_t)fifo & (uint32_t)kCSI_RxFifo) - { - cr3 |= CSI_CSICR3_DMA_REQ_EN_RFF_MASK; - } - - if ((uint32_t)fifo & (uint32_t)kCSI_StatFifo) - { - cr3 |= CSI_CSICR3_DMA_REQ_EN_SFF_MASK; - } - - if (enable) - { - base->CSICR3 |= cr3; - } - else - { - base->CSICR3 &= ~cr3; - } -} - -void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask) -{ - base->CSICR1 |= (mask & CSI_CSICR1_INT_EN_MASK); - base->CSICR3 |= (mask & CSI_CSICR3_INT_EN_MASK); - base->CSICR18 |= ((mask & CSI_CSICR18_INT_EN_MASK) >> 6U); -} - -void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask) -{ - base->CSICR1 &= ~(mask & CSI_CSICR1_INT_EN_MASK); - base->CSICR3 &= ~(mask & CSI_CSICR3_INT_EN_MASK); - base->CSICR18 &= ~((mask & CSI_CSICR18_INT_EN_MASK) >> 6U); -} - -status_t CSI_TransferCreateHandle(CSI_Type *base, - csi_handle_t *handle, - csi_transfer_callback_t callback, - void *userData) -{ - assert(handle); - uint32_t instance; - - memset(handle, 0, sizeof(*handle)); - - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - - /* Get instance from peripheral base address. */ - instance = CSI_GetInstance(base); - - /* Save the handle in global variables to support the double weak mechanism. */ - s_csiHandle[instance] = handle; - - s_csiIsr = CSI_TransferHandleIRQ; - - /* Enable interrupt. */ - EnableIRQ(s_csiIRQ[instance]); - - return kStatus_Success; -} - -status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle) -{ - assert(handle); - - uint32_t emptyBufferCount; - - emptyBufferCount = CSI_TransferGetEmptyBufferCount(base, handle); - - if (emptyBufferCount < 2U) - { - return kStatus_CSI_NoEmptyBuffer; - } - - handle->nextBufferIdx = 0U; - handle->activeBufferNum = 0U; - - /* Write to memory from second completed frame. */ - base->CSICR18 = (base->CSICR18 & ~CSI_CSICR18_MASK_OPTION_MASK) | CSI_CSICR18_MASK_OPTION(2); - - /* Load the frame buffer to CSI register, there are at least two empty buffers. */ - CSI_TransferLoadBufferToDevice(base, handle); - CSI_TransferLoadBufferToDevice(base, handle); - - /* After reflash DMA, the CSI saves frame to frame buffer 0. */ - CSI_ReflashFifoDma(base, kCSI_RxFifo); - - handle->transferStarted = true; - handle->transferOnGoing = true; - - CSI_EnableInterrupts(base, kCSI_RxBuffer1DmaDoneInterruptEnable | kCSI_RxBuffer0DmaDoneInterruptEnable); - - CSI_Start(base); - - return kStatus_Success; -} - -status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle) -{ - assert(handle); - - CSI_Stop(base); - CSI_DisableInterrupts(base, kCSI_RxBuffer1DmaDoneInterruptEnable | kCSI_RxBuffer0DmaDoneInterruptEnable); - - handle->transferStarted = false; - handle->transferOnGoing = false; - - /* Stoped, reset the state flags. */ - handle->queueDrvReadIdx = handle->queueDrvWriteIdx; - handle->activeBufferNum = 0U; - - return kStatus_Success; -} - -status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t frameBuffer) -{ - uint32_t csicr1; - - if (CSI_DRIVER_QUEUE_SIZE == CSI_TransferGetQueueDelta(handle->queueUserReadIdx, handle->queueUserWriteIdx)) - { - return kStatus_CSI_QueueFull; - } - - /* Disable the interrupt to protect the index information in handle. */ - csicr1 = base->CSICR1; - - base->CSICR1 = (csicr1 & ~(CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK | CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)); - - /* Save the empty frame buffer address to queue. */ - handle->frameBufferQueue[handle->queueUserWriteIdx] = frameBuffer; - handle->queueUserWriteIdx = CSI_TransferIncreaseQueueIdx(handle->queueUserWriteIdx); - - base->CSICR1 = csicr1; - - if (handle->transferStarted) - { - /* - * If user has started transfer using @ref CSI_TransferStart, and the CSI is - * stopped due to no empty frame buffer in queue, then start the CSI. - */ - if ((!handle->transferOnGoing) && (CSI_TransferGetEmptyBufferCount(base, handle) >= 2U)) - { - handle->transferOnGoing = true; - handle->nextBufferIdx = 0U; - - /* Load the frame buffers to CSI module. */ - CSI_TransferLoadBufferToDevice(base, handle); - CSI_TransferLoadBufferToDevice(base, handle); - CSI_ReflashFifoDma(base, kCSI_RxFifo); - CSI_Start(base); - } - } - - return kStatus_Success; -} - -status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t *frameBuffer) -{ - uint32_t csicr1; - - /* No full frame buffer. */ - if (handle->queueUserReadIdx == handle->queueDrvWriteIdx) - { - return kStatus_CSI_NoFullBuffer; - } - - /* Disable the interrupt to protect the index information in handle. */ - csicr1 = base->CSICR1; - - base->CSICR1 = (csicr1 & ~(CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK | CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)); - - *frameBuffer = handle->frameBufferQueue[handle->queueUserReadIdx]; - - handle->queueUserReadIdx = CSI_TransferIncreaseQueueIdx(handle->queueUserReadIdx); - - base->CSICR1 = csicr1; - - return kStatus_Success; -} - -void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle) -{ - uint32_t queueDrvWriteIdx; - uint32_t csisr = base->CSISR; - - /* Clear the error flags. */ - base->CSISR = csisr; - - /* - * If both frame buffer 0 and frame buffer 1 flags assert, driver does not - * know which frame buffer ready just now, so reset the CSI transfer to - * start from frame buffer 0. - */ - if ((csisr & (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK)) == - (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK)) - { - CSI_Stop(base); - - /* Reset the active buffers. */ - if (1 <= handle->activeBufferNum) - { - queueDrvWriteIdx = handle->queueDrvWriteIdx; - - base->CSIDMASA_FB1 = handle->frameBufferQueue[queueDrvWriteIdx]; - - if (2U == handle->activeBufferNum) - { - queueDrvWriteIdx = CSI_TransferIncreaseQueueIdx(queueDrvWriteIdx); - base->CSIDMASA_FB2 = handle->frameBufferQueue[queueDrvWriteIdx]; - handle->nextBufferIdx = 0U; - } - else - { - handle->nextBufferIdx = 1U; - } - } - CSI_ReflashFifoDma(base, kCSI_RxFifo); - CSI_Start(base); - } - else if (csisr & (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK)) - { - handle->queueDrvWriteIdx = CSI_TransferIncreaseQueueIdx(handle->queueDrvWriteIdx); - - handle->activeBufferNum--; - - if (handle->callback) - { - handle->callback(base, handle, kStatus_CSI_FrameDone, handle->userData); - } - - /* No frame buffer to save incoming data, then stop the CSI module. */ - if (!(handle->activeBufferNum)) - { - CSI_Stop(base); - handle->transferOnGoing = false; - } - else - { - if (CSI_TransferGetEmptyBufferCount(base, handle)) - { - CSI_TransferLoadBufferToDevice(base, handle); - } - } - } - else - { - } -} - -#if defined(CSI) -void CSI_DriverIRQHandler(void) -{ - s_csiIsr(CSI, s_csiHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CSI0) -void CSI0_DriverIRQHandler(void) -{ - s_csiIsr(CSI, s_csiHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_csi.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_csi.h deleted file mode 100644 index 96230c8318..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_csi.h +++ /dev/null @@ -1,562 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2017, NXP Semiconductors, Inc. - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_CSI_H_ -#define _FSL_CSI_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup csi_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_CSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief Size of the frame buffer queue used in CSI transactional function. */ -#ifndef CSI_DRIVER_QUEUE_SIZE -#define CSI_DRIVER_QUEUE_SIZE 4U -#endif - -/* - * There is one empty room in queue, used to distinguish whether the queue - * is full or empty. When header equals tail, the queue is empty; when header - * equals tail + 1, the queue is full. - */ -#define CSI_DRIVER_ACTUAL_QUEUE_SIZE (CSI_DRIVER_QUEUE_SIZE + 1U) - -/* - * The interrupt enable bits are in registers CSICR1[16:31], CSICR3[0:7], - * and CSICR18[2:9]. So merge them into an uint32_t value, place CSICR18 control - * bits to [8:15]. - */ -#define CSI_CSICR1_INT_EN_MASK 0xFFFF0000U -#define CSI_CSICR3_INT_EN_MASK 0x000000FFU -#define CSI_CSICR18_INT_EN_MASK 0x0000FF00U - -#if ((~CSI_CSICR1_INT_EN_MASK) & \ - (CSI_CSICR1_EOF_INT_EN_MASK | CSI_CSICR1_COF_INT_EN_MASK | CSI_CSICR1_SF_OR_INTEN_MASK | \ - CSI_CSICR1_RF_OR_INTEN_MASK | CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK | CSI_CSICR1_STATFF_INTEN_MASK | \ - CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK | CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK | CSI_CSICR1_RXFF_INTEN_MASK | \ - CSI_CSICR1_SOF_INTEN_MASK)) -#error CSI_CSICR1_INT_EN_MASK could not cover all interrupt bits in CSICR1. -#endif - -#if ((~CSI_CSICR3_INT_EN_MASK) & (CSI_CSICR3_ECC_INT_EN_MASK | CSI_CSICR3_HRESP_ERR_EN_MASK)) -#error CSI_CSICR3_INT_EN_MASK could not cover all interrupt bits in CSICR3. -#endif - -#if ((~CSI_CSICR18_INT_EN_MASK) & ((CSI_CSICR18_FIELD0_DONE_IE_MASK | CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK | CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) << 6U)) -#error CSI_CSICR18_INT_EN_MASK could not cover all interrupt bits in CSICR18. -#endif - -/*! @brief Error codes for the CSI driver. */ -enum _csi_status -{ - kStatus_CSI_NoEmptyBuffer = MAKE_STATUS(kStatusGroup_CSI, 0), /*!< No empty frame buffer in queue to load to CSI. */ - kStatus_CSI_NoFullBuffer = MAKE_STATUS(kStatusGroup_CSI, 1), /*!< No full frame buffer in queue to read out. */ - kStatus_CSI_QueueFull = MAKE_STATUS(kStatusGroup_CSI, 2), /*!< Queue is full, no room to save new empty buffer. */ - kStatus_CSI_FrameDone = MAKE_STATUS(kStatusGroup_CSI, 3), /*!< New frame received and saved to queue. */ -}; - -/*! - * @brief CSI work mode. - * - * The CCIR656 interlace mode is not supported currently. - */ -typedef enum _csi_work_mode -{ - kCSI_GatedClockMode = CSI_CSICR1_GCLK_MODE(1U), /*!< HSYNC, VSYNC, and PIXCLK signals are used. */ - kCSI_NonGatedClockMode = 0U, /*!< VSYNC, and PIXCLK signals are used. */ - kCSI_CCIR656ProgressiveMode = CSI_CSICR1_CCIR_EN(1U), /*!< CCIR656 progressive mode. */ -} csi_work_mode_t; - -/*! - * @brief CSI data bus witdh. - * - * Currently only support 8-bit width. - */ -typedef enum _csi_data_bus -{ - kCSI_DataBus8Bit, /*!< 8-bit data bus. */ -} csi_data_bus_t; - -/*! @brief CSI signal polarity. */ -enum _csi_polarity_flags -{ - kCSI_HsyncActiveLow = 0U, /*!< HSYNC is active low. */ - kCSI_HsyncActiveHigh = CSI_CSICR1_HSYNC_POL_MASK, /*!< HSYNC is active high. */ - kCSI_DataLatchOnRisingEdge = CSI_CSICR1_REDGE_MASK, /*!< Pixel data latched at rising edge of pixel clock. */ - kCSI_DataLatchOnFallingEdge = 0U, /*!< Pixel data latched at falling edge of pixel clock. */ - kCSI_VsyncActiveHigh = 0U, /*!< VSYNC is active high. */ - kCSI_VsyncActiveLow = CSI_CSICR1_SOF_POL_MASK, /*!< VSYNC is active low. */ -}; - -/*! @brief Configuration to initialize the CSI module. */ -typedef struct _csi_config -{ - uint16_t width; /*!< Pixels of the input frame. */ - uint16_t height; /*!< Lines of the input frame. */ - uint32_t polarityFlags; /*!< Timing signal polarity flags, OR'ed value of @ref _csi_polarity_flags. */ - uint8_t bytesPerPixel; /*!< Bytes per pixel, valid values are: - - 2: Used for RGB565, YUV422, and so on. - - 3: Used for packed RGB888, packed YUV444, and so on. - - 4: Used for XRGB8888, XYUV444, and so on. - */ - uint16_t linePitch_Bytes; /*!< Frame buffer line pitch, must be 8-byte aligned. */ - csi_work_mode_t workMode; /*!< CSI work mode. */ - csi_data_bus_t dataBus; /*!< Data bus width. */ - bool useExtVsync; /*!< In CCIR656 progressive mode, set true to use external VSYNC signal, set false - to use internal VSYNC signal decoded from SOF. */ -} csi_config_t; - -/*! @brief The CSI FIFO, used for FIFO operation. */ -typedef enum _csi_fifo -{ - kCSI_RxFifo = (1U << 0U), /*!< RXFIFO. */ - kCSI_StatFifo = (1U << 1U), /*!< STAT FIFO. */ - kCSI_AllFifo = 0x01 | 0x02, /*!< Both RXFIFO and STAT FIFO. */ -} csi_fifo_t; - -/*! @brief CSI feature interrupt source. */ -enum _csi_interrupt_enable -{ - kCSI_EndOfFrameInterruptEnable = CSI_CSICR1_EOF_INT_EN_MASK, /*!< End of frame interrupt enable. */ - kCSI_ChangeOfFieldInterruptEnable = CSI_CSICR1_COF_INT_EN_MASK, /*!< Change of field interrupt enable. */ - kCSI_StatFifoOverrunInterruptEnable = CSI_CSICR1_SF_OR_INTEN_MASK, /*!< STAT FIFO overrun interrupt enable. */ - kCSI_RxFifoOverrunInterruptEnable = CSI_CSICR1_RF_OR_INTEN_MASK, /*!< RXFIFO overrun interrupt enable. */ - kCSI_StatFifoDmaDoneInterruptEnable = - CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK, /*!< STAT FIFO DMA done interrupt enable. */ - kCSI_StatFifoFullInterruptEnable = CSI_CSICR1_STATFF_INTEN_MASK, /*!< STAT FIFO full interrupt enable. */ - kCSI_RxBuffer1DmaDoneInterruptEnable = - CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK, /*!< RX frame buffer 1 DMA transfer done. */ - kCSI_RxBuffer0DmaDoneInterruptEnable = - CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK, /*!< RX frame buffer 0 DMA transfer done. */ - kCSI_RxFifoFullInterruptEnable = CSI_CSICR1_RXFF_INTEN_MASK, /*!< RXFIFO full interrupt enable. */ - kCSI_StartOfFrameInterruptEnable = CSI_CSICR1_SOF_INTEN_MASK, /*!< Start of frame (SOF) interrupt enable. */ - - kCSI_EccErrorInterruptEnable = CSI_CSICR3_ECC_INT_EN_MASK, /*!< ECC error detection interrupt enable. */ - kCSI_AhbResErrorInterruptEnable = CSI_CSICR3_HRESP_ERR_EN_MASK, /*!< AHB response Error interrupt enable. */ - - kCSI_BaseAddrChangeErrorInterruptEnable = CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK << 6U, /*!< The DMA output buffer base address - changes before DMA completed. */ - kCSI_Field0DoneInterruptEnable = CSI_CSICR18_FIELD0_DONE_IE_MASK << 6U, /*!< Field 0 done interrupt enable. */ - kCSI_Field1DoneInterruptEnable = CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK << 6U, /*!< Field 1 done interrupt enable. */ -}; - -/*! - * @brief CSI status flags. - * - * The following status register flags can be cleared: - * - kCSI_EccErrorFlag - * - kCSI_AhbResErrorFlag - * - kCSI_ChangeOfFieldFlag - * - kCSI_StartOfFrameFlag - * - kCSI_EndOfFrameFlag - * - kCSI_RxBuffer1DmaDoneFlag - * - kCSI_RxBuffer0DmaDoneFlag - * - kCSI_StatFifoDmaDoneFlag - * - kCSI_StatFifoOverrunFlag - * - kCSI_RxFifoOverrunFlag - * - kCSI_Field0DoneFlag - * - kCSI_Field1DoneFlag - * - kCSI_BaseAddrChangeErrorFlag - */ -enum _csi_flags -{ - kCSI_RxFifoDataReadyFlag = CSI_CSISR_DRDY_MASK, /*!< RXFIFO data ready. */ - kCSI_EccErrorFlag = CSI_CSISR_ECC_INT_MASK, /*!< ECC error detected. */ - kCSI_AhbResErrorFlag = CSI_CSISR_HRESP_ERR_INT_MASK, /*!< Hresponse (AHB bus response) Error. */ - kCSI_ChangeOfFieldFlag = CSI_CSISR_COF_INT_MASK, /*!< Change of field. */ - kCSI_Field0PresentFlag = CSI_CSISR_F1_INT_MASK, /*!< Field 0 present in CCIR mode. */ - kCSI_Field1PresentFlag = CSI_CSISR_F2_INT_MASK, /*!< Field 1 present in CCIR mode. */ - kCSI_StartOfFrameFlag = CSI_CSISR_SOF_INT_MASK, /*!< Start of frame (SOF) detected. */ - kCSI_EndOfFrameFlag = CSI_CSISR_EOF_INT_MASK, /*!< End of frame (EOF) detected. */ - kCSI_RxFifoFullFlag = CSI_CSISR_RxFF_INT_MASK, /*!< RXFIFO full (Number of data reaches trigger level). */ - kCSI_RxBuffer1DmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_FB2_MASK, /*!< RX frame buffer 1 DMA transfer done. */ - kCSI_RxBuffer0DmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_FB1_MASK, /*!< RX frame buffer 0 DMA transfer done. */ - kCSI_StatFifoFullFlag = CSI_CSISR_STATFF_INT_MASK, /*!< STAT FIFO full (Reach trigger level). */ - kCSI_StatFifoDmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_SFF_MASK, /*!< STAT FIFO DMA transfer done. */ - kCSI_StatFifoOverrunFlag = CSI_CSISR_SF_OR_INT_MASK, /*!< STAT FIFO overrun. */ - kCSI_RxFifoOverrunFlag = CSI_CSISR_RF_OR_INT_MASK, /*!< RXFIFO overrun. */ - kCSI_Field0DoneFlag = CSI_CSISR_DMA_FIELD0_DONE_MASK, /*!< Field 0 transfer done. */ - kCSI_Field1DoneFlag = CSI_CSISR_DMA_FIELD1_DONE_MASK, /*!< Field 1 transfer done. */ - kCSI_BaseAddrChangeErrorFlag = CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK, /*!< The DMA output buffer base address - changes before DMA completed. */ -}; - -/* Forward declaration of the handle typedef. */ -typedef struct _csi_handle csi_handle_t; - -/*! - * @brief CSI transfer callback function. - * - * When a new frame is received and saved to the frame buffer queue, the callback - * is called and the pass the status @ref kStatus_CSI_FrameDone to upper layer. - */ -typedef void (*csi_transfer_callback_t)(CSI_Type *base, csi_handle_t *handle, status_t status, void *userData); - -/*! - * @brief CSI handle structure. - * - * Please see the user guide for the details of the CSI driver queue mechanism. - */ -struct _csi_handle -{ - uint32_t frameBufferQueue[CSI_DRIVER_ACTUAL_QUEUE_SIZE]; /*!< Frame buffer queue. */ - - volatile uint8_t queueUserReadIdx; /*!< Application gets full-filled frame buffer from this index. */ - volatile uint8_t queueUserWriteIdx; /*!< Application puts empty frame buffer to this index. */ - volatile uint8_t queueDrvReadIdx; /*!< Driver gets empty frame buffer from this index. */ - volatile uint8_t queueDrvWriteIdx; /*!< Driver puts the full-filled frame buffer to this index. */ - - volatile uint8_t activeBufferNum; /*!< How many frame buffers are in progres currently. */ - volatile uint8_t nextBufferIdx; /*!< The CSI frame buffer index to use for next frame. */ - - volatile bool transferStarted; /*!< User has called @ref CSI_TransferStart to start frame receiving. */ - volatile bool transferOnGoing; /*!< CSI is working and receiving incoming frames. */ - - csi_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< CSI callback function parameter.*/ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initialize the CSI. - * - * This function enables the CSI peripheral clock, and resets the CSI registers. - * - * @param base CSI peripheral base address. - * @param config Pointer to the configuration structure. - * - * @retval kStatus_Success Initialize successfully. - * @retval kStatus_InvalidArgument Initialize failed because of invalid argument. - */ -status_t CSI_Init(CSI_Type *base, const csi_config_t *config); - -/*! - * @brief De-initialize the CSI. - * - * This function disables the CSI peripheral clock. - * - * @param base CSI peripheral base address. - */ -void CSI_Deinit(CSI_Type *base); - -/*! - * @brief Reset the CSI. - * - * This function resets the CSI peripheral registers to default status. - * - * @param base CSI peripheral base address. - */ -void CSI_Reset(CSI_Type *base); - -/*! - * @brief Get the default configuration for to initialize the CSI. - * - * The default configuration value is: - * - * @code - config->width = 320U; - config->height = 240U; - config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge; - config->bytesPerPixel = 2U; - config->linePitch_Bytes = 320U * 2U; - config->workMode = kCSI_GatedClockMode; - config->dataBus = kCSI_DataBus8Bit; - config->useExtVsync = true; - @endcode - * - * @param config Pointer to the CSI configuration. - */ -void CSI_GetDefaultConfig(csi_config_t *config); - -/* @} */ - -/*! - * @name Module operation - * @{ - */ - -/*! - * @brief Clear the CSI FIFO. - * - * This function clears the CSI FIFO. - * - * @param base CSI peripheral base address. - * @param fifo The FIFO to clear. - */ -void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo); - -/*! - * @brief Reflash the CSI FIFO DMA. - * - * This function reflashes the CSI FIFO DMA. - * - * For RXFIFO, there are two frame buffers. When the CSI module started, it saves - * the frames to frame buffer 0 then frame buffer 1, the two buffers will be - * written by turns. After reflash DMA using this function, the CSI is reset to - * save frame to buffer 0. - * - * @param base CSI peripheral base address. - * @param fifo The FIFO DMA to reflash. - */ -void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo); - -/*! - * @brief Enable or disable the CSI FIFO DMA request. - * - * @param base CSI peripheral base address. - * @param fifo The FIFO DMA reques to enable or disable. - * @param enable True to enable, false to disable. - */ -void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable); - -/*! - * @brief Start to receive data. - * - * @param base CSI peripheral base address. - */ -static inline void CSI_Start(CSI_Type *base) -{ - CSI_EnableFifoDmaRequest(base, kCSI_RxFifo, true); - base->CSICR18 |= CSI_CSICR18_CSI_ENABLE_MASK; -} - -/*! - * @brief Stop to receiving data. - * - * @param base CSI peripheral base address. - */ -static inline void CSI_Stop(CSI_Type *base) -{ - base->CSICR18 &= ~CSI_CSICR18_CSI_ENABLE_MASK; - CSI_EnableFifoDmaRequest(base, kCSI_RxFifo, false); -} - -/*! - * @brief Set the RX frame buffer address. - * - * @param base CSI peripheral base address. - * @param index Buffer index. - * @param addr Frame buffer address to set. - */ -void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr); -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables CSI interrupt requests. - * - * @param base CSI peripheral base address. - * @param mask The interrupts to enable, pass in as OR'ed value of @ref _csi_interrupt_enable. - */ -void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask); - -/*! - * @brief Disable CSI interrupt requests. - * - * @param base CSI peripheral base address. - * @param mask The interrupts to disable, pass in as OR'ed value of @ref _csi_interrupt_enable. - */ -void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the CSI status flags. - * - * @param base CSI peripheral base address. - * @return status flag, it is OR'ed value of @ref _csi_flags. - */ -static inline uint32_t CSI_GetStatusFlags(CSI_Type *base) -{ - return base->CSISR; -} - -/*! - * @brief Clears the CSI status flag. - * - * The flags to clear are passed in as OR'ed value of @ref _csi_flags. The following - * flags are cleared automatically by hardware: - * - * - @ref kCSI_RxFifoFullFlag, - * - @ref kCSI_StatFifoFullFlag, - * - @ref kCSI_Field0PresentFlag, - * - @ref kCSI_Field1PresentFlag, - * - @ref kCSI_RxFifoDataReadyFlag, - * - * @param base CSI peripheral base address. - * @param statusMask The status flags mask, OR'ed value of @ref _csi_flags. - */ -static inline void CSI_ClearStatusFlags(CSI_Type *base, uint32_t statusMask) -{ - base->CSISR = statusMask; -} -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the CSI handle. - * - * This function initializes CSI handle, it should be called before any other - * CSI transactional functions. - * - * @param base CSI peripheral base address. - * @param handle Pointer to the handle structure. - * @param callback Callback function for CSI transfer. - * @param userData Callback function parameter. - * - * @retval kStatus_Success Handle created successfully. - */ -status_t CSI_TransferCreateHandle(CSI_Type *base, - csi_handle_t *handle, - csi_transfer_callback_t callback, - void *userData); - -/*! - * @brief Start the transfer using transactional functions. - * - * When the empty frame buffers have been submit to CSI driver using function - * @ref CSI_TransferSubmitEmptyBuffer, user could call this function to start - * the transfer. The incoming frame will be saved to the empty frame buffer, - * and user could be optionally notified through callback function. - * - * @param base CSI peripheral base address. - * @param handle Pointer to the handle structure. - * - * @retval kStatus_Success Started successfully. - * @retval kStatus_CSI_NoEmptyBuffer Could not start because no empty frame buffer in queue. - */ -status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle); - -/*! - * @brief Stop the transfer using transactional functions. - * - * The driver does not clean the full frame buffers in queue. In other words, after - * calling this function, user still could get the full frame buffers in queue - * using function @ref CSI_TransferGetFullBuffer. - * - * @param base CSI peripheral base address. - * @param handle Pointer to the handle structure. - * - * @retval kStatus_Success Stoped successfully. - */ -status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle); - -/*! - * @brief Submit empty frame buffer to queue. - * - * This function could be called before @ref CSI_TransferStart or after @ref - * CSI_TransferStart. If there is no room in queue to store the empty frame - * buffer, this function returns error. - * - * @param base CSI peripheral base address. - * @param handle Pointer to the handle structure. - * @param frameBuffer Empty frame buffer to submit. - * - * @retval kStatus_Success Started successfully. - * @retval kStatus_CSI_QueueFull Could not submit because there is no room in queue. - */ -status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t frameBuffer); - -/*! - * @brief Get one full frame buffer from queue. - * - * After the transfer started using function @ref CSI_TransferStart, the incoming - * frames will be saved to the empty frame buffers in queue. This function gets - * the full-filled frame buffer from the queue. If there is no full frame buffer - * in queue, this function returns error. - * - * @param base CSI peripheral base address. - * @param handle Pointer to the handle structure. - * @param frameBuffer Full frame buffer. - * - * @retval kStatus_Success Started successfully. - * @retval kStatus_CSI_NoFullBuffer There is no full frame buffer in queue. - */ -status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t *frameBuffer); - -/*! - * @brief CSI IRQ handle function. - * - * This function handles the CSI IRQ request to work with CSI driver transactional - * APIs. - * - * @param base CSI peripheral base address. - * @param handle CSI handle pointer. - */ -void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle); -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CSI_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_dcdc.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_dcdc.c deleted file mode 100644 index 5e0e3a97b4..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_dcdc.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2017, NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dcdc.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.dcdc_1" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for DCDC module. - * - * @param base DCDC peripheral base address - */ -static uint32_t DCDC_GetInstance(DCDC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to DCDC bases for each instance. */ -static DCDC_Type *const s_dcdcBases[] = DCDC_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to DCDC clocks for each instance. */ -static const clock_ip_name_t s_dcdcClocks[] = DCDC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t DCDC_GetInstance(DCDC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dcdcBases); instance++) - { - if (s_dcdcBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_dcdcBases)); - - return instance; -} - -void DCDC_Init(DCDC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(s_dcdcClocks[DCDC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void DCDC_Deinit(DCDC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_dcdcClocks[DCDC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource) -{ - uint32_t tmp32; - - /* Configure the DCDC_REG0 register. */ - tmp32 = base->REG0 & - ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | - DCDC_REG0_PWD_OSC_INT_MASK); - switch (clockSource) - { - case kDCDC_ClockInternalOsc: - tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; - break; - case kDCDC_ClockExternalOsc: - /* Choose the external clock and disable the internal clock. */ - tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK; - break; - case kDCDC_ClockAutoSwitch: - /* Set to switch from internal ring osc to xtal 24M if auto mode is enabled. */ - tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK; - break; - default: - break; - } - base->REG0 = tmp32; -} - -void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config) -{ - assert(NULL != config); - - config->enableXtalokDetection = false; - config->powerDownOverVoltageDetection = true; - config->powerDownLowVlotageDetection = false; - config->powerDownOverCurrentDetection = true; - config->powerDownPeakCurrentDetection = true; - config->powerDownZeroCrossDetection = true; - config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; - config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; -} - -void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32; - /* Configure the DCDC_REG0 register. */ - tmp32 = base->REG0 & - ~(DCDC_REG0_XTALOK_DISABLE_MASK | DCDC_REG0_PWD_HIGH_VOLT_DET_MASK | DCDC_REG0_PWD_CMP_BATT_DET_MASK | - DCDC_REG0_PWD_OVERCUR_DET_MASK | DCDC_REG0_PWD_CUR_SNS_CMP_MASK | DCDC_REG0_PWD_ZCD_MASK | - DCDC_REG0_CUR_SNS_THRSH_MASK | DCDC_REG0_OVERCUR_TRIG_ADJ_MASK); - - tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold) | - DCDC_REG0_OVERCUR_TRIG_ADJ(config->OverCurrentThreshold); - if (false == config->enableXtalokDetection) - { - tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; - } - if (config->powerDownOverVoltageDetection) - { - tmp32 |= DCDC_REG0_PWD_HIGH_VOLT_DET_MASK; - } - if (config->powerDownLowVlotageDetection) - { - tmp32 |= DCDC_REG0_PWD_CMP_BATT_DET_MASK; - } - if (config->powerDownOverCurrentDetection) - { - tmp32 |= DCDC_REG0_PWD_OVERCUR_DET_MASK; - } - if (config->powerDownPeakCurrentDetection) - { - tmp32 |= DCDC_REG0_PWD_CUR_SNS_CMP_MASK; - } - if (config->powerDownZeroCrossDetection) - { - tmp32 |= DCDC_REG0_PWD_ZCD_MASK; - } - base->REG0 = tmp32; -} - -void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config) -{ - assert(NULL != config); - - config->enableOverloadDetection = true; - config->enableAdjustHystereticValue = false; - config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; - config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; -} - -void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32; - /* Configure the DCDC_REG0 register. */ - tmp32 = base->REG0 & - ~(DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK | DCDC_REG0_LP_HIGH_HYS_MASK | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK | - DCDC_REG0_LP_OVERLOAD_THRSH_MASK); - tmp32 |= DCDC_REG0_LP_OVERLOAD_FREQ_SEL(config->countChargingTimePeriod) | - DCDC_REG0_LP_OVERLOAD_THRSH(config->countChargingTimeThreshold); - if (config->enableOverloadDetection) - { - tmp32 |= DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK; - } - if (config->enableAdjustHystereticValue) - { - tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK; - } - base->REG0 = tmp32; -} - -uint32_t DCDC_GetstatusFlags(DCDC_Type *base) -{ - uint32_t tmp32 = 0U; - - if (DCDC_REG0_STS_DC_OK_MASK == (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) - { - tmp32 |= kDCDC_LockedOKStatus; - } - - return tmp32; -} - -void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable) -{ - if (enable) - { - base->REG0 |= DCDC_REG0_CURRENT_ALERT_RESET_MASK; - } - else - { - base->REG0 &= ~DCDC_REG0_CURRENT_ALERT_RESET_MASK; - } -} - -void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config) -{ - assert(NULL != config); - - config->enableCommonHysteresis = false; - config->enableCommonThresholdDetection = false; - config->enableInvertHysteresisSign = false; - config->enableRCThresholdDetection = false; - config->enableRCScaleCircuit = 0U; - config->complementFeedForwardStep = 0U; - config->controlParameterMagnitude = 2U; - config->integralProportionalRatio = 2U; -} - -void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32; - - /* Configure the DCDC_REG1 register. */ - tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_HYST_MASK | DCDC_REG1_LOOPCTRL_HST_THRESH_MASK); - if (config->enableCommonHysteresis) - { - tmp32 |= DCDC_REG1_LOOPCTRL_EN_HYST_MASK; - } - if (config->enableCommonThresholdDetection) - { - tmp32 |= DCDC_REG1_LOOPCTRL_HST_THRESH_MASK; - } - base->REG1 = tmp32; - - /* configure the DCDC_REG2 register. */ - tmp32 = base->REG2 & - ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK | - DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK | DCDC_REG2_LOOPCTRL_DC_R_MASK | - DCDC_REG2_LOOPCTRL_DC_C_MASK); - tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) | - DCDC_REG2_LOOPCTRL_DC_R(config->controlParameterMagnitude) | - DCDC_REG2_LOOPCTRL_DC_C(config->integralProportionalRatio) | - DCDC_REG2_LOOPCTRL_EN_RCSCALE(config->enableRCScaleCircuit); - if (config->enableInvertHysteresisSign) - { - tmp32 |= DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK; - } - if (config->enableRCThresholdDetection) - { - tmp32 |= DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK; - } - base->REG2 = tmp32; -} - -void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32; - - tmp32 = base->REG3 & ~DCDC_REG3_MINPWR_DC_HALFCLK_MASK; - if (config->enableUseHalfFreqForContinuous) - { - tmp32 |= DCDC_REG3_MINPWR_DC_HALFCLK_MASK; - } - base->REG3 = tmp32; -} - -void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby) -{ - uint32_t tmp32; - - /* Unlock the step for the output. */ - base->REG3 &= ~DCDC_REG3_DISABLE_STEP_MASK; - - /* Configure the DCDC_REG3 register. */ - tmp32 = base->REG3 & ~(DCDC_REG3_TARGET_LP_MASK | DCDC_REG3_TRG_MASK); - - tmp32 |= DCDC_REG3_TARGET_LP(VDDStandby) | DCDC_REG3_TRG(VDDRun); - base->REG3 = tmp32; - - /* DCDC_STS_DC_OK bit will be de-asserted after target register changes. After output voltage settling to new - * target value, DCDC_STS_DC_OK will be asserted. */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) - { - } -} - -void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32; - - /* Configure the DCDC_REG1 register. */ - tmp32 = base->REG1 & ~(DCDC_REG1_REG_FBK_SEL_MASK | DCDC_REG1_REG_RLOAD_SW_MASK); - tmp32 |= DCDC_REG1_REG_FBK_SEL(config->feedbackPoint); - if (config->enableLoadResistor) - { - tmp32 |= DCDC_REG1_REG_RLOAD_SW_MASK; - } - base->REG1 = tmp32; -} - -void DCDC_BootIntoDCM(DCDC_Type *base) -{ - base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); - base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x4U) | - DCDC_REG2_DCM_SET_CTRL_MASK; -} - -void DCDC_BootIntoCCM(DCDC_Type *base) -{ - base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; - base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U); -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_dcdc.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_dcdc.h deleted file mode 100644 index 647d3a8589..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_dcdc.h +++ /dev/null @@ -1,490 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2017, NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_DCDC_H__ -#define __FSL_DCDC_H__ - -#include "fsl_common.h" - -/*! - * @addtogroup dcdc - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief DCDC driver version. */ -#define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - /*! - * @brief DCDC status flags. - */ -enum _dcdc_status_flags_t -{ - kDCDC_LockedOKStatus = (1U << 0U), /*!< Indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling. */ -}; - -/*! -* @brief The current bias of low power comparator. -*/ -typedef enum _dcdc_comparator_current_bias -{ - kDCDC_ComparatorCurrentBias50nA = 0U, /*!< The current bias of low power comparator is 50nA. */ - kDCDC_ComparatorCurrentBias100nA = 1U, /*!< The current bias of low power comparator is 100nA. */ - kDCDC_ComparatorCurrentBias200nA = 2U, /*!< The current bias of low power comparator is 200nA. */ - kDCDC_ComparatorCurrentBias400nA = 3U, /*!< The current bias of low power comparator is 400nA. */ -} dcdc_comparator_current_bias_t; - -/*! -* @brief The threshold of over current detection. -*/ -typedef enum _dcdc_over_current_threshold -{ - kDCDC_OverCurrentThresholdAlt0 = 0U, /*!< 1A in the run mode, 0.25A in the power save mode. */ - kDCDC_OverCurrentThresholdAlt1 = 1U, /*!< 2A in the run mode, 0.25A in the power save mode. */ - kDCDC_OverCurrentThresholdAlt2 = 2U, /*!< 1A in the run mode, 0.2A in the power save mode. */ - kDCDC_OverCurrentThresholdAlt3 = 3U, /*!< 2A in the run mode, 0.2A in the power save mode. */ -} dcdc_over_current_threshold_t; - -/*! -* @brief The threshold if peak current detection. -*/ -typedef enum _dcdc_peak_current_threshold -{ - kDCDC_PeakCurrentThresholdAlt0 = 0U, /*!< 150mA peak current threshold. */ - kDCDC_PeakCurrentThresholdAlt1 = 1U, /*!< 250mA peak current threshold. */ - kDCDC_PeakCurrentThresholdAlt2 = 2U, /*!< 350mA peak current threshold. */ - kDCDC_PeakCurrentThresholdAlt3 = 3U, /*!< 450mA peak current threshold. */ - kDCDC_PeakCurrentThresholdAlt4 = 4U, /*!< 550mA peak current threshold. */ - kDCDC_PeakCurrentThresholdAlt5 = 5U, /*!< 650mA peak current threshold. */ -} dcdc_peak_current_threshold_t; - -/*! -* @brief The period of counting the charging times in power save mode. -*/ -typedef enum _dcdc_count_charging_time_period -{ - kDCDC_CountChargingTimePeriod8Cycle = 0U, /*!< Eight 32k cycle. */ - kDCDC_CountChargingTimePeriod16Cycle = 1U, /*!< Sixteen 32k cycle. */ -} dcdc_count_charging_time_period_t; - -/*! -* @brief The threshold of the counting number of charging times -*/ -typedef enum _dcdc_count_charging_time_threshold -{ - kDCDC_CountChargingTimeThreshold32 = 0U, /*!< 0x0: 32. */ - kDCDC_CountChargingTimeThreshold64 = 1U, /*!< 0x1: 64. */ - kDCDC_CountChargingTimeThreshold16 = 2U, /*!< 0x2: 16. */ - kDCDC_CountChargingTimeThreshold8 = 3U, /*!< 0x3: 8. */ -} dcdc_count_charging_time_threshold_t; - -/*! - * @brief Oscillator clock option. - */ -typedef enum _dcdc_clock_source -{ - kDCDC_ClockAutoSwitch = 0U, /*!< Automatic clock switch from internal oscillator to external clock. */ - kDCDC_ClockInternalOsc = 1U, /*!< Use internal oscillator. */ - kDCDC_ClockExternalOsc = 2U, /*!< Use external 24M crystal oscillator. */ -} dcdc_clock_source_t; - -/*! -* @brief Configuration for DCDC detection. -*/ -typedef struct _dcdc_detection_config -{ - bool enableXtalokDetection; /*!< Enable xtalok detection circuit. */ - bool powerDownOverVoltageDetection; /*!< Power down over-voltage detection comparator. */ - bool powerDownLowVlotageDetection; /*!< Power down low-voltage detection comparator. */ - bool powerDownOverCurrentDetection; /*!< Power down over-current detection. */ - bool powerDownPeakCurrentDetection; /*!< Power down peak-current detection. */ - bool powerDownZeroCrossDetection; /*!< Power down the zero cross detection function for discontinuous conductor - mode. */ - dcdc_over_current_threshold_t OverCurrentThreshold; /*!< The threshold of over current detection. */ - dcdc_peak_current_threshold_t PeakCurrentThreshold; /*!< The threshold of peak current detection. */ -} dcdc_detection_config_t; - -/*! -* @brief Configuration for the loop control. -*/ -typedef struct _dcdc_loop_control_config -{ - bool enableCommonHysteresis; /*!< Enable hysteresis in switching converter common mode analog comparators. - This feature will improve transient supply ripple and efficiency. */ - bool enableCommonThresholdDetection; /*!< Increase the threshold detection for common mode analog comparator. */ - bool enableInvertHysteresisSign; /*!< Invert the sign of the hysteresis in DC-DC analog comparators. */ - bool enableRCThresholdDetection; /*!< Increase the threshold detection for RC scale circuit. */ - uint32_t enableRCScaleCircuit; /*!< Available range is 0~7. Enable analog circuit of DC-DC converter to respond - faster under transient load conditions. */ - uint32_t complementFeedForwardStep; /*!< Available range is 0~7. Two's complement feed forward step in duty cycle in - the switching DC-DC converter. Each time this field makes a transition from - 0x0, the loop filter of the DC-DC converter is stepped once by a value - proportional to the change. This can be used to force a certain control loop - behavior, such as improving response under known heavy load transients. */ - uint32_t controlParameterMagnitude; /*!< Available range is 0~15. Magnitude of proportional control parameter in the - switching DC-DC converter control loop. */ - uint32_t integralProportionalRatio; /*!< Available range is 0~3.Ratio of integral control parameter to proportional - control parameter in the switching DC-DC converter, and can be used to - optimize efficiency and loop response. */ -} dcdc_loop_control_config_t; -/*! -* @brief Configuration for DCDC low power. -*/ -typedef struct _dcdc_low_power_config -{ - bool enableOverloadDetection; /*!< Enable the overload detection in power save mode, if current is larger than the - overloading threshold (typical value is 50 mA), DCDC will switch to the run mode - automatically. */ - bool enableAdjustHystereticValue; /*!< Adjust hysteretic value in low power from 12.5mV to 25mV. */ - dcdc_count_charging_time_period_t - countChargingTimePeriod; /*!< The period of counting the charging times in power save mode. */ - dcdc_count_charging_time_threshold_t - countChargingTimeThreshold; /*!< the threshold of the counting number of charging times during - the period that lp_overload_freq_sel sets in power save mode. */ -} dcdc_low_power_config_t; - -/*! -* @brief Configuration for DCDC internal regulator. -*/ -typedef struct _dcdc_internal_regulator_config -{ - bool enableLoadResistor; /*!< control the load resistor of the internal regulator of DCDC, the load resistor is - connected as default "true", and need set to "false" to disconnect the load - resistor. */ - uint32_t feedbackPoint; /*!< Available range is 0~3. Select the feedback point of the internal regulator. */ -} dcdc_internal_regulator_config_t; - -/*! - * @brief Configuration for min power setting. - */ -typedef struct _dcdc_min_power_config -{ - bool enableUseHalfFreqForContinuous; /*!< Set DCDC clock to half frequency for the continuous mode. */ -} dcdc_min_power_config_t; -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! -* @brief Enable the access to DCDC registers. -* -* @param base DCDC peripheral base address. -*/ -void DCDC_Init(DCDC_Type *base); - -/*! -* @brief Disable the access to DCDC registers. -* -* @param base DCDC peripheral base address. -*/ -void DCDC_Deinit(DCDC_Type *base); - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! -* @brief Get DCDC status flags. -* -* @param base peripheral base address. -* @return Mask of asserted status flags. See to "_dcdc_status_flags_t". -*/ -uint32_t DCDC_GetstatusFlags(DCDC_Type *base); - -/* @} */ - -/*! - * @name Misc control. - * @{ - */ - -/*! - * @brief Enable the output range comparator. - * - * The output range comparator is disabled by default. - * - * @param base DCDC peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable) -{ - if (enable) - { - base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK; - } - else - { - base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; - } -} - -/*! -* @brief Configure the DCDC clock source. -* -* @param base DCDC peripheral base address. -* @param clockSource Clock source for DCDC. See to "dcdc_clock_source_t". -*/ -void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource); - -/*! -* @brief Get the default setting for detection configuration. -* -* The default configuration are set according to responding registers' setting when powered on. -* They are: -* @code -* config->enableXtalokDetection = false; -* config->powerDownOverVoltageDetection = true; -* config->powerDownLowVlotageDetection = false; -* config->powerDownOverCurrentDetection = true; -* config->powerDownPeakCurrentDetection = true; -* config->powerDownZeroCrossDetection = true; -* config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; -* config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; -* @endcode -* -* @param config Pointer to configuration structure. See to "dcdc_detection_config_t" -*/ -void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config); - -/*! -* @breif Configure the DCDC detection. -* -* @param base DCDC peripheral base address. -* @param config Pointer to configuration structure. See to "dcdc_detection_config_t" -*/ -void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config); - -/*! -* @brief Get the default setting for low power configuration. -* -* The default configuration are set according to responding registers' setting when powered on. -* They are: -* @code -* config->enableOverloadDetection = true; -* config->enableAdjustHystereticValue = false; -* config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; -* config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; -* @endcode -* -* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t" -*/ -void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config); - -/*! -* @brief Configure the DCDC low power. -* -* @param base DCDC peripheral base address. -* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t". -*/ -void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config); - -/*! -* @brief Reset current alert signal. Alert signal is generate by peak current detection. -* -* @param base DCDC peripheral base address. -* @param enable Switcher to reset signal. True means reset signal. False means don't reset signal. -*/ -void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable); - -/*! -* @brief Set the bangap trim value to trim bandgap voltage. -* -* @param base DCDC peripheral base address. -* @param TrimValue The bangap trim value. Available range is 0U-31U. -*/ -static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue) -{ - base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; - base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); -} - -/*! -* @brief Get the default setting for loop control configuration. -* -* The default configuration are set according to responding registers' setting when powered on. -* They are: -* @code -* config->enableCommonHysteresis = false; -* config->enableCommonThresholdDetection = false; -* config->enableInvertHysteresisSign = false; -* config->enableRCThresholdDetection = false; -* config->enableRCScaleCircuit = 0U; -* config->complementFeedForwardStep = 0U; -* config->controlParameterMagnitude = 2U; -* config->integralProportionalRatio = 2U; -* @endcode -* -* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t" -*/ -void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config); - -/*! -* @brief Configure the DCDC loop control. -* -* @param base DCDC peripheral base address. -* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t". -*/ -void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config); - -/*! - * @brief Configure for the min power. - * - * @param base DCDC peripheral base address. - * @param config Pointer to configuration structure. See to "dcdc_min_power_config_t". - */ -void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config); - -/*! -* @brief Set the current bias of low power comparator. -* -* @param base DCDC peripheral base address. -* @param biasVaule The current bias of low power comparator. Refer to "dcdc_comparator_current_bias_t". -*/ -static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasVaule) -{ - base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK; - base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasVaule); -} - -static inline void DCDC_LockTargetVoltage(DCDC_Type *base) -{ - base->REG3 |= DCDC_REG3_DISABLE_STEP_MASK; -} - -/*! -* @brief Adjust the target voltage of VDD_SOC in run mode and low power mode. -* -* This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is -* stabled. -* Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch -* back to run mode if it detects the current loading is larger than about 50 mA(typical value). -* -* @param base DCDC peripheral base address. -* @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V. -* @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V. -*/ -void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby); - -/*! -* @brief Configure the DCDC internal regulator. -* -* @param base DCDC peripheral base address. -* @param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t". -*/ -void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config); - -/*! -* @brief Ajust delay to reduce ground noise. -* -* @param base DCDC peripheral base address. -* @param enable Enable the feature or not. -*/ -static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable) -{ - if (enable) - { - base->REG3 |= DCDC_REG3_MISC_DELAY_TIMING_MASK; - } - else - { - base->REG3 &= ~DCDC_REG3_MISC_DELAY_TIMING_MASK; - } -} - -/*! -* @brief Enable/Disable to improve the transition from heavy load to light load. It is valid while zero -* cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from DCM. -* -* @param base DCDC peripheral base address. -* @param enable Enable the feature or not. -*/ -static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable) -{ - if (enable) - { - base->REG2 |= DCDC_REG2_DCM_SET_CTRL_MASK; - } - else - { - base->REG2 &= ~DCDC_REG2_DCM_SET_CTRL_MASK; - } -} - -/* @} */ - -/*! - * @name Application guideline. - * @{ - */ - -/*! -* @brief Boot DCDC into DCM(discontinous conduction mode). -* -* pwd_zcd=0x0; -* pwd_cmp_offset=0x0; -* dcdc_loopctrl_en_rcscale=0x3 or 0x5; -* DCM_set_ctrl=1'b1; -* -* @param base DCDC peripheral base address. -*/ -void DCDC_BootIntoDCM(DCDC_Type *base); - -/*! -* @brief Boot DCDC into CCM(continous conduction mode). -* -* pwd_zcd=0x1; -* pwd_cmp_offset=0x0; -* dcdc_loopctrl_en_rcscale=0x3; -* -* @param base DCDC peripheral base address. -*/ -void DCDC_BootIntoCCM(DCDC_Type *base); - -#if defined(__cplusplus) -} -#endif - -#endif /* __FSL_DCDC_H__ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_dcp.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_dcp.c deleted file mode 100644 index fdc13fa0fc..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_dcp.c +++ /dev/null @@ -1,1129 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dcp.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.dcp" -#endif - - -/*! Compile time sizeof() check */ -#define BUILD_ASSURE(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) - -#define dcp_memcpy memcpy - -/*! Internal states of the HASH creation process */ -typedef enum _dcp_hash_algo_state -{ - kDCP_StateHashInit = 1u, /*!< Init state. */ - kDCP_StateHashUpdate, /*!< Update state. */ -} dcp_hash_algo_state_t; - -/*! multiple of 64-byte block represented as byte array of 32-bit words */ -typedef union _dcp_hash_block -{ - uint32_t w[DCP_HASH_BLOCK_SIZE / 4]; /*!< array of 32-bit words */ - uint8_t b[DCP_HASH_BLOCK_SIZE]; /*!< byte array */ -} dcp_hash_block_t; - -/*! internal dcp_hash context structure */ -typedef struct _dcp_hash_ctx_internal -{ - dcp_hash_block_t blk; /*!< memory buffer. only full blocks are written to DCP during hash updates */ - size_t blksz; /*!< number of valid bytes in memory buffer */ - dcp_hash_algo_t algo; /*!< selected algorithm from the set of supported algorithms */ - dcp_hash_algo_state_t state; /*!< finite machine state of the hash software process */ - uint32_t fullMessageSize; /*!< track message size */ - uint32_t ctrl0; /*!< HASH_INIT and HASH_TERM flags */ - uint32_t runningHash[9]; /*!< running hash. up to SHA-256 plus size, that is 36 bytes. */ - dcp_handle_t *handle; -} dcp_hash_ctx_internal_t; - -/*!< SHA-1/SHA-2 digest length in bytes */ -enum _dcp_hash_digest_len -{ - kDCP_OutLenSha1 = 20u, - kDCP_OutLenSha256 = 32u, - kDCP_OutLenCrc32 = 4u, -}; - -enum _dcp_work_packet_bit_definitions -{ - kDCP_CONTROL0_DECR_SEMAPHOR = 1u << 1, /* DECR_SEMAPHOR */ - kDCP_CONTROL0_ENABLE_HASH = 1u << 6, /* ENABLE_HASH */ - kDCP_CONTROL0_HASH_INIT = 1u << 12, /* HASH_INIT */ - kDCP_CONTROL0_HASH_TERM = 1u << 13, /* HASH_TERM */ - kDCP_CONTROL1_HASH_SELECT_SHA256 = 2u << 16, - kDCP_CONTROL1_HASH_SELECT_SHA1 = 0u << 16, - kDCP_CONTROL1_HASH_SELECT_CRC32 = 1u << 16, -}; - -/*! 64-byte block represented as byte array of 16 32-bit words */ -typedef union _dcp_sha_block -{ - uint32_t w[64 / 4]; /*!< array of 32-bit words */ - uint8_t b[64]; /*!< byte array */ -} dcp_sha_block_t; - -#if defined(DCP_HASH_CAVP_COMPATIBLE) -/* result of sha1 hash for message with zero size */ -static uint8_t s_nullSha1[] = {0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d, 0x32, 0x55, - 0xbf, 0xef, 0x95, 0x60, 0x18, 0x90, 0xaf, 0xd8, 0x07, 0x09}; -/* result of sha256 hash for message with zero size */ -static uint8_t s_nullSha256[] = {0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14, 0x9a, 0xfb, 0xf4, - 0xc8, 0x99, 0x6f, 0xb9, 0x24, 0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, - 0x93, 0x4c, 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55}; -#endif /* DCP_HASH_CAVP_COMPATIBLE */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -static dcp_context_t s_dcpContextSwitchingBuffer; - -/******************************************************************************* - * Code - ******************************************************************************/ - -static void dcp_reverse_and_copy(uint8_t *src, uint8_t *dest, size_t src_len) -{ - for (int i = 0; i < src_len; i++) - { - dest[i] = src[src_len - 1 - i]; - } -} - -static status_t dcp_get_channel_status(DCP_Type *base, dcp_channel_t channel) -{ - uint32_t statReg = 0; - uint32_t semaReg = 0; - status_t status = kStatus_Fail; - - switch (channel) - { - case kDCP_Channel0: - statReg = base->CH0STAT; - semaReg = base->CH0SEMA; - break; - - case kDCP_Channel1: - statReg = base->CH1STAT; - semaReg = base->CH1SEMA; - break; - - case kDCP_Channel2: - statReg = base->CH2STAT; - semaReg = base->CH2SEMA; - break; - - case kDCP_Channel3: - statReg = base->CH3STAT; - semaReg = base->CH3SEMA; - break; - - default: - break; - } - - if (!((semaReg & DCP_CH0SEMA_VALUE_MASK) || (statReg & DCP_CH0STAT_ERROR_CODE_MASK))) - { - status = kStatus_Success; - } - - return status; -} - -static void dcp_clear_status(DCP_Type *base) -{ - volatile uint32_t *dcpStatClrPtr = &base->STAT + 2u; - *dcpStatClrPtr = 0xFFu; -} - -static void dcp_clear_channel_status(DCP_Type *base, uint32_t mask) -{ - volatile uint32_t *chStatClrPtr; - - if (mask & kDCP_Channel0) - { - chStatClrPtr = &base->CH0STAT + 2u; - *chStatClrPtr = 0xFFu; - } - if (mask & kDCP_Channel1) - { - chStatClrPtr = &base->CH1STAT + 2u; - *chStatClrPtr = 0xFFu; - } - if (mask & kDCP_Channel2) - { - chStatClrPtr = &base->CH2STAT + 2u; - *chStatClrPtr = 0xFFu; - } - if (mask & kDCP_Channel3) - { - chStatClrPtr = &base->CH3STAT + 2u; - *chStatClrPtr = 0xFFu; - } -} - -static status_t dcp_aes_set_sram_based_key(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key) -{ - base->KEY = DCP_KEY_INDEX(handle->keySlot) | DCP_KEY_SUBWORD(0); - /* move the key by 32-bit words */ - int i = 0; - size_t keySize = 16u; - while (keySize) - { - keySize -= sizeof(uint32_t); - base->KEYDATA = ((uint32_t *)(uintptr_t)key)[i]; - i++; - } - return kStatus_Success; -} - -static status_t dcp_schedule_work(DCP_Type *base, dcp_handle_t *handle, dcp_work_packet_t *dcpPacket) -{ - status_t status; - - /* check if our channel is active */ - if ((base->STAT & (uint32_t)handle->channel) != handle->channel) - { - /* disable global interrupt */ - uint32_t currPriMask = DisableGlobalIRQ(); - - /* re-check if our channel is still available */ - if ((base->STAT & (uint32_t)handle->channel) == 0) - { - volatile uint32_t *cmdptr = NULL; - volatile uint32_t *chsema = NULL; - - switch (handle->channel) - { - case kDCP_Channel0: - cmdptr = &base->CH0CMDPTR; - chsema = &base->CH0SEMA; - break; - - case kDCP_Channel1: - cmdptr = &base->CH1CMDPTR; - chsema = &base->CH1SEMA; - break; - - case kDCP_Channel2: - cmdptr = &base->CH2CMDPTR; - chsema = &base->CH2SEMA; - break; - - case kDCP_Channel3: - cmdptr = &base->CH3CMDPTR; - chsema = &base->CH3SEMA; - break; - - default: - break; - } - - if (cmdptr && chsema) - { - /* set out packet to DCP CMDPTR */ - *cmdptr = (uint32_t)dcpPacket; - - /* set the channel semaphore */ - *chsema = 1u; - } - - status = kStatus_Success; - } - - else - { - status = kStatus_DCP_Again; - } - /* global interrupt enable */ - EnableGlobalIRQ(currPriMask); - } - - else - { - return kStatus_DCP_Again; - } - - return status; -} - -status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key, size_t keySize) -{ - status_t status = kStatus_Fail; - - if ((kDCP_OtpKey == handle->keySlot) || (kDCP_OtpUniqueKey == handle->keySlot)) - { - /* for AES OTP and unique key, check and return read from fuses status */ - if ((base->STAT & DCP_STAT_OTP_KEY_READY_MASK) == DCP_STAT_OTP_KEY_READY_MASK) - { - status = kStatus_Success; - } - } - else - { - /* only work with aligned key[] */ - if (0x3U & (uintptr_t)key) - { - return kStatus_InvalidArgument; - } - - /* keySize must be 16. */ - if (keySize != 16U) - { - return kStatus_InvalidArgument; - } - - /* move the key by 32-bit words */ - int i = 0; - while (keySize) - { - keySize -= sizeof(uint32_t); - handle->keyWord[i] = ((uint32_t *)(uintptr_t)key)[i]; - i++; - } - - if (kDCP_PayloadKey != handle->keySlot) - { - /* move the key by 32-bit words to DCP SRAM-based key storage */ - status = dcp_aes_set_sram_based_key(base, handle, key); - } - else - { - /* for PAYLOAD_KEY, just return Ok status now */ - status = kStatus_Success; - } - } - - return status; -} - -status_t DCP_AES_EncryptEcb( - DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size) -{ - status_t completionStatus = kStatus_Fail; - dcp_work_packet_t dcpWork = {0}; - - do - { - completionStatus = DCP_AES_EncryptEcbNonBlocking(base, handle, &dcpWork, plaintext, ciphertext, size); - } while (completionStatus == kStatus_DCP_Again); - - if (completionStatus != kStatus_Success) - { - return completionStatus; - } - - return DCP_WaitForChannelComplete(base, handle); -} - -status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base, - dcp_handle_t *handle, - dcp_work_packet_t *dcpPacket, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size) -{ - /* Size must be 16-byte multiple */ - if ((size < 16u) || (size % 16u)) - { - return kStatus_InvalidArgument; - } - - dcpPacket->control0 = 0x122u; /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */ - dcpPacket->sourceBufferAddress = (uint32_t)plaintext; - dcpPacket->destinationBufferAddress = (uint32_t)ciphertext; - dcpPacket->bufferSize = (uint32_t)size; - - if (handle->keySlot == kDCP_OtpKey) - { - dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ - dcpPacket->control1 = (0xFFu << 8); /* KEY_SELECT = OTP_KEY */ - } - else if (handle->keySlot == kDCP_OtpUniqueKey) - { - dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ - dcpPacket->control1 = (0xFEu << 8); /* KEY_SELECT = UNIQUE_KEY */ - } - else if (handle->keySlot == kDCP_PayloadKey) - { - /* ECB does not have IV, so we can point payload directly to keyWord[] stored in handle. */ - dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0]; - dcpPacket->control0 |= (1u << 11); /* PAYLOAD_KEY */ - } - else - { - dcpPacket->control1 = (handle->keySlot << 8); /* KEY_SELECT = keySlot */ - } - - return dcp_schedule_work(base, handle, dcpPacket); -} - -status_t DCP_AES_DecryptEcb( - DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size) -{ - status_t completionStatus = kStatus_Fail; - dcp_work_packet_t dcpWork = {0}; - - do - { - completionStatus = DCP_AES_DecryptEcbNonBlocking(base, handle, &dcpWork, ciphertext, plaintext, size); - } while (completionStatus == kStatus_DCP_Again); - - if (completionStatus != kStatus_Success) - { - return completionStatus; - } - - return DCP_WaitForChannelComplete(base, handle); -} - -status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base, - dcp_handle_t *handle, - dcp_work_packet_t *dcpPacket, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size) -{ - /* Size must be 16-byte multiple */ - if ((size < 16u) || (size % 16u)) - { - return kStatus_InvalidArgument; - } - - dcpPacket->control0 = 0x22u; /* ENABLE_CIPHER | DECR_SEMAPHORE */ - dcpPacket->sourceBufferAddress = (uint32_t)ciphertext; - dcpPacket->destinationBufferAddress = (uint32_t)plaintext; - dcpPacket->bufferSize = (uint32_t)size; - - if (handle->keySlot == kDCP_OtpKey) - { - dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ - dcpPacket->control1 = (0xFFu << 8); /* KEY_SELECT = OTP_KEY */ - } - else if (handle->keySlot == kDCP_OtpUniqueKey) - { - dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ - dcpPacket->control1 = (0xFEu << 8); /* KEY_SELECT = UNIQUE_KEY */ - } - else if (handle->keySlot == kDCP_PayloadKey) - { - /* ECB does not have IV, so we can point payload directly to keyWord[] stored in handle. */ - dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0]; - dcpPacket->control0 |= (1u << 11); /* PAYLOAD_KEY */ - } - else - { - dcpPacket->control1 = (handle->keySlot << 8); /* KEY_SELECT = keySlot */ - } - - return dcp_schedule_work(base, handle, dcpPacket); -} - -status_t DCP_AES_EncryptCbc(DCP_Type *base, - dcp_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]) -{ - status_t completionStatus = kStatus_Fail; - dcp_work_packet_t dcpWork = {0}; - - do - { - completionStatus = DCP_AES_EncryptCbcNonBlocking(base, handle, &dcpWork, plaintext, ciphertext, size, iv); - } while (completionStatus == kStatus_DCP_Again); - - if (completionStatus != kStatus_Success) - { - return completionStatus; - } - - return DCP_WaitForChannelComplete(base, handle); -} - -status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base, - dcp_handle_t *handle, - dcp_work_packet_t *dcpPacket, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t *iv) -{ - /* Size must be 16-byte multiple */ - if ((size < 16u) || (size % 16u)) - { - return kStatus_InvalidArgument; - } - - dcpPacket->control0 = 0x322u; /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */ - dcpPacket->control1 = 0x10u; /* CBC */ - dcpPacket->sourceBufferAddress = (uint32_t)plaintext; - dcpPacket->destinationBufferAddress = (uint32_t)ciphertext; - dcpPacket->bufferSize = (uint32_t)size; - - if (handle->keySlot == kDCP_OtpKey) - { - dcpPacket->payloadPointer = (uint32_t)iv; - dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ - dcpPacket->control1 |= (0xFFu << 8); /* KEY_SELECT = OTP_KEY */ - } - else if (handle->keySlot == kDCP_OtpUniqueKey) - { - dcpPacket->payloadPointer = (uint32_t)iv; - dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ - dcpPacket->control1 |= (0xFEu << 8); /* KEY_SELECT = UNIQUE_KEY */ - } - else if (handle->keySlot == kDCP_PayloadKey) - { - /* In this case payload must contain key & iv in one array. */ - /* Copy iv into handle right behind the keyWord[] so we can point payload to keyWord[]. */ - dcp_memcpy(handle->iv, iv, 16); - dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0]; - dcpPacket->control0 |= (1u << 11); /* PAYLOAD_KEY */ - } - else - { - dcpPacket->payloadPointer = (uint32_t)iv; - dcpPacket->control1 |= ((uint32_t)handle->keySlot << 8); /* KEY_SELECT = keySlot */ - } - - return dcp_schedule_work(base, handle, dcpPacket); -} - -status_t DCP_AES_DecryptCbc(DCP_Type *base, - dcp_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]) -{ - status_t completionStatus = kStatus_Fail; - dcp_work_packet_t dcpWork = {0}; - - do - { - completionStatus = DCP_AES_DecryptCbcNonBlocking(base, handle, &dcpWork, ciphertext, plaintext, size, iv); - } while (completionStatus == kStatus_DCP_Again); - - if (completionStatus != kStatus_Success) - { - return completionStatus; - } - - return DCP_WaitForChannelComplete(base, handle); -} - -status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base, - dcp_handle_t *handle, - dcp_work_packet_t *dcpPacket, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t *iv) -{ - /* Size must be 16-byte multiple */ - if ((size < 16u) || (size % 16u)) - { - return kStatus_InvalidArgument; - } - - dcpPacket->control0 = 0x222u; /* CIPHER_INIT | ENABLE_CIPHER | DECR_SEMAPHORE */ - dcpPacket->control1 = 0x10u; /* CBC */ - dcpPacket->sourceBufferAddress = (uint32_t)ciphertext; - dcpPacket->destinationBufferAddress = (uint32_t)plaintext; - dcpPacket->bufferSize = (uint32_t)size; - - if (handle->keySlot == kDCP_OtpKey) - { - dcpPacket->payloadPointer = (uint32_t)iv; - dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ - dcpPacket->control1 |= (0xFFu << 8); /* OTP_KEY */ - } - else if (handle->keySlot == kDCP_OtpUniqueKey) - { - dcpPacket->payloadPointer = (uint32_t)iv; - dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ - dcpPacket->control1 |= (0xFEu << 8); /* UNIQUE_KEY */ - } - else if (handle->keySlot == kDCP_PayloadKey) - { - /* in this case payload must contain KEY + IV together */ - /* copy iv into handle struct so we can point payload directly to keyWord[]. */ - dcp_memcpy(handle->iv, iv, 16); - dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0]; - dcpPacket->control0 |= (1u << 11); /* PAYLOAD_KEY */ - } - else - { - dcpPacket->payloadPointer = (uint32_t)iv; - dcpPacket->control1 |= ((uint32_t)handle->keySlot << 8); /* KEY_SELECT */ - } - - return dcp_schedule_work(base, handle, dcpPacket); -} - -void DCP_GetDefaultConfig(dcp_config_t *config) -{ - /* ENABLE_CONTEXT_CACHING is disabled by default as the DCP Hash driver uses - * dcp_hash_save_running_hash() and dcp_hash_restore_running_hash() to support - * Hash context switch (different messages interleaved) on the same channel. - */ - dcp_config_t userConfig = { - true, false, true, kDCP_chEnableAll, kDCP_chIntDisable, - }; - - *config = userConfig; -} - -void DCP_Init(DCP_Type *base, const dcp_config_t *config) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Dcp); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - base->CTRL = 0xF0800000u; /* reset value */ - base->CTRL = 0x30800000u; /* default value */ - - dcp_clear_status(base); - dcp_clear_channel_status(base, kDCP_Channel0 | kDCP_Channel1 | kDCP_Channel2 | kDCP_Channel3); - - base->CTRL = DCP_CTRL_GATHER_RESIDUAL_WRITES(config->gatherResidualWrites) | - DCP_CTRL_ENABLE_CONTEXT_CACHING(config->enableContextCaching) | - DCP_CTRL_ENABLE_CONTEXT_SWITCHING(config->enableContextSwitching) | - DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(config->enableChannelInterrupt); - - /* enable DCP channels */ - base->CHANNELCTRL = DCP_CHANNELCTRL_ENABLE_CHANNEL(config->enableChannel); - - /* use context switching buffer */ - base->CONTEXT = (uint32_t)&s_dcpContextSwitchingBuffer; -} - -void DCP_Deinit(DCP_Type *base) -{ - base->CTRL = 0xF0800000u; /* reset value */ - memset(&s_dcpContextSwitchingBuffer, 0, sizeof(s_dcpContextSwitchingBuffer)); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Dcp); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle) -{ - /* wait if our channel is still active */ - while ((base->STAT & (uint32_t)handle->channel) == handle->channel) - { - } - - if (dcp_get_channel_status(base, handle->channel) != kStatus_Success) - { - dcp_clear_status(base); - dcp_clear_channel_status(base, handle->channel); - return kStatus_Fail; - } - - return kStatus_Success; -} - -/*! - * @brief Check validity of algoritm. - * - * This function checks the validity of input argument. - * - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t dcp_hash_check_input_alg(dcp_hash_algo_t algo) -{ - if ((algo != kDCP_Sha256) && (algo != kDCP_Sha1) && (algo != kDCP_Crc32)) - { - return kStatus_InvalidArgument; - } - return kStatus_Success; -} - -/*! - * @brief Check validity of input arguments. - * - * This function checks the validity of input arguments. - * - * @param base DCP peripheral base address. - * @param ctx Memory buffer given by user application where the DCP_HASH_Init/DCP_HASH_Update/DCP_HASH_Finish store - * context. - * @param algo Tested algorithm value. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t dcp_hash_check_input_args(DCP_Type *base, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo) -{ - /* Check validity of input algorithm */ - if (kStatus_Success != dcp_hash_check_input_alg(algo)) - { - return kStatus_InvalidArgument; - } - - if ((NULL == ctx) || (NULL == base)) - { - return kStatus_InvalidArgument; - } - - return kStatus_Success; -} - -/*! - * @brief Check validity of internal software context. - * - * This function checks if the internal context structure looks correct. - * - * @param ctxInternal Internal context. - * @param message Input message address. - * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. - */ -static status_t dcp_hash_check_context(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *message) -{ - if ((NULL == message) || (NULL == ctxInternal) || (kStatus_Success != dcp_hash_check_input_alg(ctxInternal->algo))) - { - return kStatus_InvalidArgument; - } - return kStatus_Success; -} - -/*! - * @brief Initialize the SHA engine for new hash. - * - * This function sets kDCP_CONTROL0_HASH_INIT for control0 in work packet to start a new hash. - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - */ -static status_t dcp_hash_engine_init(DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal) -{ - status_t status; - - status = kStatus_InvalidArgument; - - if ((kDCP_Sha256 == ctxInternal->algo) || (kDCP_Sha1 == ctxInternal->algo) || (kDCP_Crc32 == ctxInternal->algo)) - { - ctxInternal->ctrl0 = kDCP_CONTROL0_HASH_INIT; - status = kStatus_Success; - } - - return status; -} - -static status_t dcp_hash_update_non_blocking( - DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal, dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size) -{ - dcpPacket->control0 = ctxInternal->ctrl0 | kDCP_CONTROL0_ENABLE_HASH | kDCP_CONTROL0_DECR_SEMAPHOR; - if (ctxInternal->algo == kDCP_Sha256) - { - dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_SHA256; - } - else if (ctxInternal->algo == kDCP_Sha1) - { - dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_SHA1; - } - else if (ctxInternal->algo == kDCP_Crc32) - { - dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_CRC32; - } - else - { - return kStatus_Fail; - } - dcpPacket->sourceBufferAddress = (uint32_t)msg; - dcpPacket->destinationBufferAddress = 0; - dcpPacket->bufferSize = size; - dcpPacket->payloadPointer = (uint32_t)ctxInternal->runningHash; - - return dcp_schedule_work(base, ctxInternal->handle, dcpPacket); -} - -static status_t dcp_hash_update(DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *msg, size_t size) -{ - status_t completionStatus = kStatus_Fail; - dcp_work_packet_t dcpWork = {0}; - - do - { - completionStatus = dcp_hash_update_non_blocking(base, ctxInternal, &dcpWork, msg, size); - } while (completionStatus == kStatus_DCP_Again); - - completionStatus = DCP_WaitForChannelComplete(base, ctxInternal->handle); - - ctxInternal->ctrl0 = 0; /* clear kDCP_CONTROL0_HASH_INIT and kDCP_CONTROL0_HASH_TERM flags */ - return (completionStatus); -} - -/*! - * @brief Adds message to current hash. - * - * This function merges the message to fill the internal buffer, empties the internal buffer if - * it becomes full, then process all remaining message data. - * - * - * @param base DCP peripheral base address. - * @param ctxInternal Internal context. - * @param message Input message. - * @param messageSize Size of input message in bytes. - * @return kStatus_Success. - */ -static status_t dcp_hash_process_message_data(DCP_Type *base, - dcp_hash_ctx_internal_t *ctxInternal, - const uint8_t *message, - size_t messageSize) -{ - status_t status = kStatus_Fail; - - /* if there is partially filled internal buffer, fill it to full block */ - if (ctxInternal->blksz > 0) - { - size_t toCopy = DCP_HASH_BLOCK_SIZE - ctxInternal->blksz; - dcp_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); - message += toCopy; - messageSize -= toCopy; - - /* process full internal block */ - status = dcp_hash_update(base, ctxInternal, &ctxInternal->blk.b[0], DCP_HASH_BLOCK_SIZE); - if (kStatus_Success != status) - { - return status; - } - } - - /* process all full blocks in message[] */ - uint32_t fullBlocksSize = ((messageSize >> 6) << 6); /* (X / 64) * 64 */ - if (fullBlocksSize > 0) - { - status = dcp_hash_update(base, ctxInternal, message, fullBlocksSize); - if (kStatus_Success != status) - { - return status; - } - message += fullBlocksSize; - messageSize -= fullBlocksSize; - } - - /* copy last incomplete message bytes into internal block */ - dcp_memcpy(&ctxInternal->blk.b[0], message, messageSize); - ctxInternal->blksz = messageSize; - - return status; -} - -/*! - * @brief Finalize the running hash to make digest. - * - * This function empties the internal buffer, adds padding bits, and generates final digest. - * - * @param base SHA peripheral base address. - * @param ctxInternal Internal context. - * @return kStatus_Success. - */ -static status_t dcp_hash_finalize(DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal) -{ - status_t status; - - ctxInternal->ctrl0 |= kDCP_CONTROL0_HASH_TERM; - status = dcp_hash_update(base, ctxInternal, &ctxInternal->blk.b[0], ctxInternal->blksz); - - return status; -} - -static void dcp_hash_save_running_hash(dcp_hash_ctx_internal_t *ctxInternal) -{ - uint32_t *srcAddr = NULL; - - switch (ctxInternal->handle->channel) - { - case kDCP_Channel0: - srcAddr = &s_dcpContextSwitchingBuffer.x[43]; - break; - - case kDCP_Channel1: - srcAddr = &s_dcpContextSwitchingBuffer.x[30]; - break; - - case kDCP_Channel2: - srcAddr = &s_dcpContextSwitchingBuffer.x[17]; - break; - - case kDCP_Channel3: - srcAddr = &s_dcpContextSwitchingBuffer.x[4]; - break; - - default: - break; - } - if (srcAddr) - { - dcp_memcpy(ctxInternal->runningHash, srcAddr, sizeof(ctxInternal->runningHash)); - } -} - -static void dcp_hash_restore_running_hash(dcp_hash_ctx_internal_t *ctxInternal) -{ - uint32_t *destAddr = NULL; - - switch (ctxInternal->handle->channel) - { - case kDCP_Channel0: - destAddr = &s_dcpContextSwitchingBuffer.x[43]; - break; - - case kDCP_Channel1: - destAddr = &s_dcpContextSwitchingBuffer.x[30]; - break; - - case kDCP_Channel2: - destAddr = &s_dcpContextSwitchingBuffer.x[17]; - break; - - case kDCP_Channel3: - destAddr = &s_dcpContextSwitchingBuffer.x[4]; - break; - - default: - break; - } - if (destAddr) - { - dcp_memcpy(destAddr, ctxInternal->runningHash, sizeof(ctxInternal->runningHash)); - } -} - -status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo) -{ - status_t status; - - dcp_hash_ctx_internal_t *ctxInternal; - /* compile time check for the correct structure size */ - BUILD_ASSURE(sizeof(dcp_hash_ctx_t) >= sizeof(dcp_hash_ctx_internal_t), dcp_hash_ctx_t_size); - uint32_t i; - - status = dcp_hash_check_input_args(base, ctx, algo); - if (status != kStatus_Success) - { - return status; - } - - /* set algorithm in context struct for later use */ - ctxInternal = (dcp_hash_ctx_internal_t *)ctx; - ctxInternal->algo = algo; - ctxInternal->blksz = 0u; - for (i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) - { - ctxInternal->blk.w[0] = 0u; - } - ctxInternal->state = kDCP_StateHashInit; - ctxInternal->fullMessageSize = 0; - ctxInternal->handle = handle; - return status; -} - -status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) -{ - bool isUpdateState; - status_t status; - dcp_hash_ctx_internal_t *ctxInternal; - size_t blockSize; - - if (inputSize == 0) - { - return kStatus_Success; - } - - ctxInternal = (dcp_hash_ctx_internal_t *)ctx; - status = dcp_hash_check_context(ctxInternal, input); - if (kStatus_Success != status) - { - return status; - } - - ctxInternal->fullMessageSize += inputSize; - blockSize = DCP_HASH_BLOCK_SIZE; - /* if we are still less than DCP_HASH_BLOCK_SIZE bytes, keep only in context */ - if ((ctxInternal->blksz + inputSize) <= blockSize) - { - dcp_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); - ctxInternal->blksz += inputSize; - return status; - } - else - { - isUpdateState = ctxInternal->state == kDCP_StateHashUpdate; - if (!isUpdateState) - { - /* start NEW hash */ - status = dcp_hash_engine_init(base, ctxInternal); - if (status != kStatus_Success) - { - return status; - } - ctxInternal->state = kDCP_StateHashUpdate; - } - else - { - dcp_hash_restore_running_hash(ctxInternal); - } - } - - /* process input data */ - status = dcp_hash_process_message_data(base, ctxInternal, input, inputSize); - dcp_hash_save_running_hash(ctxInternal); - return status; -} - -status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize) -{ - size_t algOutSize = 0; - status_t status; - dcp_hash_ctx_internal_t *ctxInternal; - - ctxInternal = (dcp_hash_ctx_internal_t *)ctx; - status = dcp_hash_check_context(ctxInternal, output); - if (kStatus_Success != status) - { - return status; - } - - if (ctxInternal->state == kDCP_StateHashInit) - { - status = dcp_hash_engine_init(base, ctxInternal); - if (status != kStatus_Success) - { - return status; - } - } - else - { - dcp_hash_restore_running_hash(ctxInternal); - } - - size_t outSize = 0u; - - /* compute algorithm output length */ - switch (ctxInternal->algo) - { - case kDCP_Sha256: - outSize = kDCP_OutLenSha256; - break; - case kDCP_Sha1: - outSize = kDCP_OutLenSha1; - break; - case kDCP_Crc32: - outSize = kDCP_OutLenCrc32; - break; - default: - break; - } - algOutSize = outSize; - -#if defined(DCP_HASH_CAVP_COMPATIBLE) - if (ctxInternal->fullMessageSize == 0) - { - switch (ctxInternal->algo) - { - case kDCP_Sha256: - dcp_memcpy(&output[0], &s_nullSha256, 32); - break; - case kDCP_Sha1: - dcp_memcpy(&output[0], &s_nullSha1, 20); - break; - default: - break; - } - - return kStatus_Success; - } -#endif /* DCP_HASH_CAVP_COMPATIBLE */ - - /* flush message last incomplete block, if there is any, and add padding bits */ - status = dcp_hash_finalize(base, ctxInternal); - - if (outputSize) - { - if (algOutSize < *outputSize) - { - *outputSize = algOutSize; - } - else - { - algOutSize = *outputSize; - } - } - - /* Reverse and copy result to output[] */ - dcp_reverse_and_copy((uint8_t *)ctxInternal->runningHash, &output[0], algOutSize); - - memset(ctx, 0, sizeof(dcp_hash_ctx_t)); - return status; -} - -status_t DCP_HASH(DCP_Type *base, - dcp_handle_t *handle, - dcp_hash_algo_t algo, - const uint8_t *input, - size_t inputSize, - uint8_t *output, - size_t *outputSize) -{ - dcp_hash_ctx_t hashCtx; - status_t status; - - status = DCP_HASH_Init(base, handle, &hashCtx, algo); - if (status != kStatus_Success) - { - return status; - } - - status = DCP_HASH_Update(base, &hashCtx, input, inputSize); - if (status != kStatus_Success) - { - return status; - } - - status = DCP_HASH_Finish(base, &hashCtx, output, outputSize); - - return status; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_dcp.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_dcp.h deleted file mode 100644 index 15694703a6..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_dcp.h +++ /dev/null @@ -1,557 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_DCP_H_ -#define _FSL_DCP_H_ - -#include "fsl_common.h" - -/*! @brief DCP status return codes. */ -enum _dcp_status -{ - kStatus_DCP_Again = MAKE_STATUS(kStatusGroup_DCP, 0), /*!< Non-blocking function shall be called again. */ -}; - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! - * @addtogroup dcp_driver - * @{ - */ -/*! @name Driver version */ -/*@{*/ -/*! @brief DCP driver version. Version 2.0.0. - * - * Current version: 2.0.0 - * - * Change log: - * - Version 2.0.0 - * - Initial version - */ -#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief DCP channel enable. - * - */ -typedef enum _dcp_ch_enable -{ - kDCP_chDisable = 0U, /*!< DCP channel disable */ - kDCP_ch0Enable = 1U, /*!< DCP channel 0 enable */ - kDCP_ch1Enable = 2U, /*!< DCP channel 1 enable */ - kDCP_ch2Enable = 4U, /*!< DCP channel 2 enable */ - kDCP_ch3Enable = 8U, /*!< DCP channel 3 enable */ - kDCP_chEnableAll = 15U, /*!< DCP channel enable all */ -} _dcp_ch_enable_t; - -/*! @brief DCP interrupt enable. - * - */ -typedef enum _dcp_ch_int_enable -{ - kDCP_chIntDisable = 0U, /*!< DCP interrupts disable */ - kDCP_ch0IntEnable = 1U, /*!< DCP channel 0 interrupt enable */ - kDCP_ch1IntEnable = 2U, /*!< DCP channel 1 interrupt enable */ - kDCP_ch2IntEnable = 4U, /*!< DCP channel 2 interrupt enable */ - kDCP_ch3IntEnable = 8U, /*!< DCP channel 3 interrupt enable */ -} _dcp_ch_int_enable_t; - -/*! @brief DCP channel selection. - * - */ -typedef enum _dcp_channel -{ - kDCP_Channel0 = (1u << 16), /*!< DCP channel 0. */ - kDCP_Channel1 = (1u << 17), /*!< DCP channel 1. */ - kDCP_Channel2 = (1u << 18), /*!< DCP channel 2. */ - kDCP_Channel3 = (1u << 19), /*!< DCP channel 3. */ -} dcp_channel_t; - -/*! @brief DCP key slot selection. - * - */ -typedef enum _dcp_key_slot -{ - kDCP_KeySlot0 = 0U, /*!< DCP key slot 0. */ - kDCP_KeySlot1 = 1U, /*!< DCP key slot 1. */ - kDCP_KeySlot2 = 2U, /*!< DCP key slot 2.*/ - kDCP_KeySlot3 = 3U, /*!< DCP key slot 3. */ - kDCP_OtpKey = 4U, /*!< DCP OTP key. */ - kDCP_OtpUniqueKey = 5U, /*!< DCP unique OTP key. */ - kDCP_PayloadKey = 6U, /*!< DCP payload key. */ -} dcp_key_slot_t; - -/*! @brief DCP's work packet. */ -typedef struct _dcp_work_packet -{ - uint32_t nextCmdAddress; - uint32_t control0; - uint32_t control1; - uint32_t sourceBufferAddress; - uint32_t destinationBufferAddress; - uint32_t bufferSize; - uint32_t payloadPointer; - uint32_t status; -} dcp_work_packet_t; - -/*! @brief Specify DCP's key resource and DCP channel. */ -typedef struct _dcp_handle -{ - dcp_channel_t channel; /*!< Specify DCP channel. */ - dcp_key_slot_t keySlot; /*!< For operations with key (such as AES encryption/decryption), specify DCP key slot. */ - uint32_t keyWord[4]; - uint32_t iv[4]; -} dcp_handle_t; - -/*! @brief DCP's context buffer, used by DCP for context switching between channels. */ -typedef struct _dcp_context -{ - uint32_t x[208 / sizeof(uint32_t)]; -} dcp_context_t; - -/*! @brief DCP's configuration structure. */ -typedef struct _dcp_config -{ - bool gatherResidualWrites; /*!< Enable the ragged writes to the unaligned buffers. */ - bool enableContextCaching; /*!< Enable the caching of contexts between the operations. */ - bool enableContextSwitching; /*!< Enable automatic context switching for the channels. */ - uint8_t enableChannel; /*!< DCP channel enable. */ - uint8_t enableChannelInterrupt; /*!< Per-channel interrupt enable. */ -} dcp_config_t; - -/*! @} */ - -/******************************************************************************* - * AES Definitions - *******************************************************************************/ - -/*! - * @addtogroup dcp_driver_aes - * @{ - */ - -/*! AES block size in bytes */ -#define DCP_AES_BLOCK_SIZE 16 - -/*! - *@} - */ /* end of dcp_driver_aes */ - -/******************************************************************************* - * HASH Definitions - ******************************************************************************/ -/*! - * @addtogroup dcp_driver_hash - * @{ - */ - -/* DCP cannot correctly compute hash for message with zero size. When enabled, driver bypases DCP and returns correct - * hash value. If you are sure, that the driver will never be called with zero sized message, you can disable this - * feature to reduce code size */ -#define DCP_HASH_CAVP_COMPATIBLE - -/*! @brief Supported cryptographic block cipher functions for HASH creation */ -typedef enum _dcp_hash_algo_t -{ - kDCP_Sha1, /*!< SHA_1 */ - kDCP_Sha256, /*!< SHA_256 */ - kDCP_Crc32, /*!< CRC_32 */ -} dcp_hash_algo_t; - -/*! @brief DCP HASH Context size. */ -#define DCP_SHA_BLOCK_SIZE 128 /*!< internal buffer block size */ -#define DCP_HASH_BLOCK_SIZE DCP_SHA_BLOCK_SIZE /*!< DCP hash block size */ - -/*! @brief DCP HASH Context size. */ -#define DCP_HASH_CTX_SIZE 58 - -/*! @brief Storage type used to save hash context. */ -typedef struct _dcp_hash_ctx_t -{ - uint32_t x[DCP_HASH_CTX_SIZE]; -} dcp_hash_ctx_t; - -/*! - *@} - */ /* end of dcp_driver_hash */ - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup dcp_driver - * @{ - */ - -/*! - * @brief Enables clock to and enables DCP - * - * Enable DCP clock and configure DCP. - * - * @param base DCP base address - * @param config Pointer to configuration structure. - */ -void DCP_Init(DCP_Type *base, const dcp_config_t *config); - -/*! - * @brief Disable DCP clock - * - * Reset DCP and Disable DCP clock. - * - * @param base DCP base address - */ -void DCP_Deinit(DCP_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the DCP configuration structure to a default value. The default - * values are as follows. - * dcpConfig->gatherResidualWrites = true; - * dcpConfig->enableContextCaching = true; - * dcpConfig->enableContextSwitching = true; - * dcpConfig->enableChannnel = kDCP_chEnableAll; - * dcpConfig->enableChannelInterrupt = kDCP_chIntDisable; - * - * @param[out] config Pointer to configuration structure. - */ -void DCP_GetDefaultConfig(dcp_config_t *config); - -/*! - * @brief Poll and wait on DCP channel. - * - * Polls the specified DCP channel until current it completes activity. - * - * @param base DCP peripheral base address. - * @param handle Specifies DCP channel. - * @return kStatus_Success When data processing completes without error. - * @return kStatus_Fail When error occurs. - */ -status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle); - -/*! - *@} - */ /* end of dcp_driver */ - -/******************************************************************************* - * AES API - ******************************************************************************/ - -/*! - * @addtogroup dcp_driver_aes - * @{ - */ - -/*! - * @brief Set AES key to dcp_handle_t struct and optionally to DCP. - * - * Sets the AES key for encryption/decryption with the dcp_handle_t structure. - * The dcp_handle_t input argument specifies keySlot. - * If the keySlot is kDCP_OtpKey, the function will check the OTP_KEY_READY bit and will return it's ready to use - * status. - * For other keySlot selections, the function will copy and hold the key in dcp_handle_t struct. - * If the keySlot is one of the four DCP SRAM-based keys (one of kDCP_KeySlot0, kDCP_KeySlot1, kDCP_KeySlot2, - * kDCP_KeySlot3), - * this function will also load the supplied key to the specified keySlot in DCP. - * - * @param base DCP peripheral base address. - * @param handle Handle used for the request. - * @param key 0-mod-4 aligned pointer to AES key. - * @param keySize AES key size in bytes. Shall equal 16. - * @return status from set key operation - */ -status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key, size_t keySize); - -/*! - * @brief Encrypts AES on one or multiple 128-bit block(s). - * - * Encrypts AES. - * The source plaintext and destination ciphertext can overlap in system memory. - * - * @param base DCP peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @return Status from encrypt operation - */ -status_t DCP_AES_EncryptEcb( - DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size); - -/*! - * @brief Decrypts AES on one or multiple 128-bit block(s). - * - * Decrypts AES. - * The source ciphertext and destination plaintext can overlap in system memory. - * - * @param base DCP peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input plain text to encrypt - * @param[out] plaintext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @return Status from decrypt operation - */ -status_t DCP_AES_DecryptEcb( - DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size); - -/*! - * @brief Encrypts AES using CBC block mode. - * - * Encrypts AES using CBC block mode. - * The source plaintext and destination ciphertext can overlap in system memory. - * - * @param base DCP peripheral base address - * @param handle Handle used for this request. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from encrypt operation - */ -status_t DCP_AES_EncryptCbc(DCP_Type *base, - dcp_handle_t *handle, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t iv[16]); - -/*! - * @brief Decrypts AES using CBC block mode. - * - * Decrypts AES using CBC block mode. - * The source ciphertext and destination plaintext can overlap in system memory. - * - * @param base DCP peripheral base address - * @param handle Handle used for this request. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return Status from decrypt operation - */ -status_t DCP_AES_DecryptCbc(DCP_Type *base, - dcp_handle_t *handle, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t iv[16]); - -/*! - *@} - */ /* end of dcp_driver_aes */ - -/*! - * @addtogroup dcp_nonblocking_driver_aes - * @{ - */ -/*! -* @brief Encrypts AES using the ECB block mode. -* -* Puts AES ECB encrypt work packet to DCP channel. -* -* @param base DCP peripheral base address -* @param handle Handle used for this request. -* @param[out] dcpPacket Memory for the DCP work packet. -* @param plaintext Input plain text to encrypt. -* @param[out] ciphertext Output cipher text -* @param size Size of input and output data in bytes. Must be multiple of 16 bytes. -* @return kStatus_Success The work packet has been scheduled at DCP channel. -* @return kStatus_DCP_Again The DCP channel is busy processing previous request. -*/ -status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base, - dcp_handle_t *handle, - dcp_work_packet_t *dcpPacket, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size); - -/*! - * @brief Decrypts AES using ECB block mode. - * - * Puts AES ECB decrypt dcpPacket to DCP input job ring. - * - * @param base DCP peripheral base address - * @param handle Handle used for this request. - * @param[out] dcpPacket Memory for the DCP work packet. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @return kStatus_Success The work packet has been scheduled at DCP channel. - * @return kStatus_DCP_Again The DCP channel is busy processing previous request. - */ -status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base, - dcp_handle_t *handle, - dcp_work_packet_t *dcpPacket, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size); - -/*! - * @brief Encrypts AES using CBC block mode. - * - * Puts AES CBC encrypt dcpPacket to DCP input job ring. - * - * @param base DCP peripheral base address - * @param handle Handle used for this request. Specifies jobRing. - * @param[out] dcpPacket Memory for the DCP work packet. - * @param plaintext Input plain text to encrypt - * @param[out] ciphertext Output cipher text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return kStatus_Success The work packet has been scheduled at DCP channel. - * @return kStatus_DCP_Again The DCP channel is busy processing previous request. - */ -status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base, - dcp_handle_t *handle, - dcp_work_packet_t *dcpPacket, - const uint8_t *plaintext, - uint8_t *ciphertext, - size_t size, - const uint8_t *iv); - -/*! - * @brief Decrypts AES using CBC block mode. - * - * Puts AES CBC decrypt dcpPacket to DCP input job ring. - * - * @param base DCP peripheral base address - * @param handle Handle used for this request. Specifies jobRing. - * @param[out] dcpPacket Memory for the DCP work packet. - * @param ciphertext Input cipher text to decrypt - * @param[out] plaintext Output plain text - * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. - * @param iv Input initial vector to combine with the first input block. - * @return kStatus_Success The work packet has been scheduled at DCP channel. - * @return kStatus_DCP_Again The DCP channel is busy processing previous request. - */ -status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base, - dcp_handle_t *handle, - dcp_work_packet_t *dcpPacket, - const uint8_t *ciphertext, - uint8_t *plaintext, - size_t size, - const uint8_t *iv); - -/*! - *@} - */ /* end of dcp_nonblocking_driver_aes */ - -/******************************************************************************* - * HASH API - ******************************************************************************/ - -/*! - * @addtogroup dcp_driver_hash - * @{ - */ -/*! - * @brief Initialize HASH context - * - * This function initializes the HASH. - * - * @param base DCP peripheral base address - * @param handle Specifies the DCP channel used for hashing. - * @param[out] ctx Output hash context - * @param algo Underlaying algorithm to use for hash computation. - * @return Status of initialization - */ -status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo); - -/*! - * @brief Add data to current HASH - * - * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be - * hashed. The functions blocks. If it returns kStatus_Success, the running hash - * has been updated (DCP has processed the input data), so the memory at @ref input pointer - * can be released back to system. The DCP context buffer is updated with the running hash - * and with all necessary information to support possible context switch. - * - * @param base DCP peripheral base address - * @param[in,out] ctx HASH context - * @param input Input data - * @param inputSize Size of input data in bytes - * @return Status of the hash update operation - */ -status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize); - -/*! - * @brief Finalize hashing - * - * Outputs the final hash (computed by DCP_HASH_Update()) and erases the context. - * - * @param[in,out] ctx Input hash context - * @param[out] output Output hash data - * @param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of - * output[] buffer. On function return, it stores the number of updated output bytes. - * @return Status of the hash finish operation - */ -status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize); - -/*! - * @brief Create HASH on given data - * - * Perform the full SHA or CRC32 in one function call. The function is blocking. - * - * @param base DCP peripheral base address - * @param handle Handle used for the request. - * @param algo Underlaying algorithm to use for hash computation. - * @param input Input data - * @param inputSize Size of input data in bytes - * @param[out] output Output hash data - * @param[out] outputSize Output parameter storing the size of the output hash in bytes - * @return Status of the one call hash operation. - */ -status_t DCP_HASH(DCP_Type *base, - dcp_handle_t *handle, - dcp_hash_algo_t algo, - const uint8_t *input, - size_t inputSize, - uint8_t *output, - size_t *outputSize); - -/*! - *@} - */ /* end of dcp_driver_hash */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_DCP_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_dmamux.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_dmamux.c deleted file mode 100644 index 155531de5a..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_dmamux.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_dmamux.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.dmamux" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for DMAMUX. - * - * @param base DMAMUX peripheral base address. - */ -static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map DMAMUX instance number to base pointer. */ -static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map DMAMUX instance number to clock name. */ -static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_dmamuxBases); instance++) - { - if (s_dmamuxBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_dmamuxBases)); - - return instance; -} - -void DMAMUX_Init(DMAMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void DMAMUX_Deinit(DMAMUX_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_dmamux.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_dmamux.h deleted file mode 100644 index 17f32ee2e8..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_dmamux.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_DMAMUX_H_ -#define _FSL_DMAMUX_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dmamux - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DMAMUX driver version 2.0.2. */ -#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name DMAMUX Initialization and de-initialization - * @{ - */ - -/*! - * @brief Initializes the DMAMUX peripheral. - * - * This function ungates the DMAMUX clock. - * - * @param base DMAMUX peripheral base address. - * - */ -void DMAMUX_Init(DMAMUX_Type *base); - -/*! - * @brief Deinitializes the DMAMUX peripheral. - * - * This function gates the DMAMUX clock. - * - * @param base DMAMUX peripheral base address. - */ -void DMAMUX_Deinit(DMAMUX_Type *base); - -/* @} */ -/*! - * @name DMAMUX Channel Operation - * @{ - */ - -/*! - * @brief Enables the DMAMUX channel. - * - * This function enables the DMAMUX channel. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; -} - -/*! - * @brief Disables the DMAMUX channel. - * - * This function disables the DMAMUX channel. - * - * @note The user must disable the DMAMUX channel before configuring it. - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; -} - -/*! - * @brief Configures the DMAMUX channel source. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - * @param source Channel source, which is used to trigger the DMA transfer. - */ -static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); -} - -#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U -/*! - * @brief Enables the DMAMUX period trigger. - * - * This function enables the DMAMUX period trigger feature. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK; -} - -/*! - * @brief Disables the DMAMUX period trigger. - * - * This function disables the DMAMUX period trigger. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - */ -static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK; -} -#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */ - -#if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON) -/*! - * @brief Enables the DMA channel to be always ON. - * - * This function enables the DMAMUX channel always ON feature. - * - * @param base DMAMUX peripheral base address. - * @param channel DMAMUX channel number. - * @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled. - */ -static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - if (enable) - { - base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK; - } - else - { - base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK; - } -} -#endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */ - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /* _FSL_DMAMUX_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_edma.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_edma.c deleted file mode 100644 index 96b0f80022..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_edma.c +++ /dev/null @@ -1,2299 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_edma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.edma" -#endif - - -#define EDMA_TRANSFER_ENABLED_MASK 0x80U - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for EDMA. - * - * @param base EDMA peripheral base address. - */ -static uint32_t EDMA_GetInstance(DMA_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map EDMA instance number to base pointer. */ -static DMA_Type *const s_edmaBases[] = DMA_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map EDMA instance number to clock name. */ -static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Array to map EDMA instance number to IRQ number. */ -static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS; - -/*! @brief Pointers to transfer handle for each EDMA channel. */ -static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL * FSL_FEATURE_SOC_EDMA_COUNT]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t EDMA_GetInstance(DMA_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++) - { - if (s_edmaBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_edmaBases)); - - return instance; -} - -void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - /* Push tcd into hardware TCD register */ - base->TCD[channel].SADDR = tcd->SADDR; - base->TCD[channel].SOFF = tcd->SOFF; - base->TCD[channel].ATTR = tcd->ATTR; - base->TCD[channel].NBYTES_MLNO = tcd->NBYTES; - base->TCD[channel].SLAST = tcd->SLAST; - base->TCD[channel].DADDR = tcd->DADDR; - base->TCD[channel].DOFF = tcd->DOFF; - base->TCD[channel].CITER_ELINKNO = tcd->CITER; - base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA; - /* Clear DONE bit first, otherwise ESG cannot be set */ - base->TCD[channel].CSR = 0; - base->TCD[channel].CSR = tcd->CSR; - base->TCD[channel].BITER_ELINKNO = tcd->BITER; -} - -void EDMA_Init(DMA_Type *base, const edma_config_t *config) -{ - assert(config != NULL); - - uint32_t tmpreg; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate EDMA periphral clock */ - CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Configure EDMA peripheral according to the configuration structure. */ - tmpreg = base->CR; - tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); - tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) | - DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true)); - base->CR = tmpreg; -} - -void EDMA_Deinit(DMA_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate EDMA periphral clock */ - CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void EDMA_GetDefaultConfig(edma_config_t *config) -{ - assert(config != NULL); - - config->enableRoundRobinArbitration = false; - config->enableHaltOnError = true; - config->enableContinuousLinkMode = false; - config->enableDebugMode = false; -} - -void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]); -} - -void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(config != NULL); - assert(((uint32_t)nextTcd & 0x1FU) == 0); - - EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd); -} - -void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(config != NULL); - - uint32_t tmpreg; - - tmpreg = base->TCD[channel].NBYTES_MLOFFYES; - tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); - tmpreg |= - (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | - DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); - base->TCD[channel].NBYTES_MLOFFYES = tmpreg; -} - -void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel); -} - -void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); -} - -void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t tmpreg; - - tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); - base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); -} - -void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - /* Enable error interrupt */ - if (mask & kEDMA_ErrorInterruptEnable) - { - base->EEI |= (0x1U << channel); - } - - /* Enable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK; - } - - /* Enable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; - } -} - -void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - /* Disable error interrupt */ - if (mask & kEDMA_ErrorInterruptEnable) - { - base->EEI &= ~(0x1U << channel); - } - - /* Disable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK; - } - - /* Disable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK; - } -} - -void EDMA_TcdReset(edma_tcd_t *tcd) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - /* Reset channel TCD */ - tcd->SADDR = 0U; - tcd->SOFF = 0U; - tcd->ATTR = 0U; - tcd->NBYTES = 0U; - tcd->SLAST = 0U; - tcd->DADDR = 0U; - tcd->DOFF = 0U; - tcd->CITER = 0U; - tcd->DLAST_SGA = 0U; - /* Enable auto disable request feature */ - tcd->CSR = DMA_CSR_DREQ(true); - tcd->BITER = 0U; -} - -void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - assert(config != NULL); - assert(((uint32_t)nextTcd & 0x1FU) == 0); - - /* source address */ - tcd->SADDR = config->srcAddr; - /* destination address */ - tcd->DADDR = config->destAddr; - /* Source data and destination data transfer size */ - tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize); - /* Source address signed offset */ - tcd->SOFF = config->srcOffset; - /* Destination address signed offset */ - tcd->DOFF = config->destOffset; - /* Minor byte transfer count */ - tcd->NBYTES = config->minorLoopBytes; - /* Current major iteration count */ - tcd->CITER = config->majorLoopCounts; - /* Starting major iteration count */ - tcd->BITER = config->majorLoopCounts; - /* Enable scatter/gather processing */ - if (nextTcd != NULL) - { - tcd->DLAST_SGA = (uint32_t)nextTcd; - /* - Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, - user must call EDMA_TcdReset or EDMA_ResetChannel which will set - DREQ, so must use "|" or "&" rather than "=". - - Clear the DREQ bit because scatter gather has been enabled, so the - previous transfer is not the last transfer, and channel request should - be enabled at the next transfer(the next TCD). - */ - tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; - } -} - -void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - uint32_t tmpreg; - - tmpreg = tcd->NBYTES & - ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); - tmpreg |= - (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | - DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); - tcd->NBYTES = tmpreg; -} - -void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - if (type == kEDMA_MinorLink) /* Minor link config */ - { - uint32_t tmpreg; - - /* Enable minor link */ - tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; - tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; - /* Set likned channel */ - tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK); - tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); - tcd->CITER = tmpreg; - tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK); - tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); - tcd->BITER = tmpreg; - } - else if (type == kEDMA_MajorLink) /* Major link config */ - { - uint32_t tmpreg; - - /* Enable major link */ - tcd->CSR |= DMA_CSR_MAJORELINK_MASK; - /* Set major linked channel */ - tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK); - tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); - } - else /* Link none */ - { - tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK; - tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK; - tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK; - } -} - -void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - uint32_t tmpreg; - - tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); - tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); -} - -void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) -{ - assert(tcd != NULL); - - /* Enable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - tcd->CSR |= DMA_CSR_INTMAJOR_MASK; - } - - /* Enable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - tcd->CSR |= DMA_CSR_INTHALF_MASK; - } -} - -void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) -{ - assert(tcd != NULL); - - /* Disable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) - { - tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK; - } - - /* Disable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) - { - tcd->CSR &= ~DMA_CSR_INTHALF_MASK; - } -} - -uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t remainingCount = 0; - - if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR) - { - remainingCount = 0; - } - else - { - /* Calculate the unfinished bytes */ - if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK) - { - remainingCount = - (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT; - } - else - { - remainingCount = - (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT; - } - } - - return remainingCount; -} - -uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t retval = 0; - - /* Get DONE bit flag */ - retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT); - /* Get ERROR bit flag */ - retval |= (((base->ERR >> channel) & 0x1U) << 1U); - /* Get INT bit flag */ - retval |= (((base->INT >> channel) & 0x1U) << 2U); - - return retval; -} - -void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - /* Clear DONE bit flag */ - if (mask & kEDMA_DoneFlag) - { - base->CDNE = channel; - } - /* Clear ERROR bit flag */ - if (mask & kEDMA_ErrorFlag) - { - base->CERR = channel; - } - /* Clear INT bit flag */ - if (mask & kEDMA_InterruptFlag) - { - base->CINT = channel; - } -} - -static uint8_t Get_StartInstance(void) -{ - static uint8_t StartInstanceNum; - -#if defined(DMA0) - StartInstanceNum = EDMA_GetInstance(DMA0); -#elif defined(DMA1) - StartInstanceNum = EDMA_GetInstance(DMA1); -#elif defined(DMA2) - StartInstanceNum = EDMA_GetInstance(DMA2); -#elif defined(DMA3) - StartInstanceNum = EDMA_GetInstance(DMA3); -#endif - - return StartInstanceNum; -} - -void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) -{ - assert(handle != NULL); - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - - uint32_t edmaInstance; - uint32_t channelIndex; - uint8_t StartInstance; - edma_tcd_t *tcdRegs; - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - handle->base = base; - handle->channel = channel; - /* Get the DMA instance number */ - edmaInstance = EDMA_GetInstance(base); - StartInstance = Get_StartInstance(); - channelIndex = ((edmaInstance - StartInstance) * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel; - s_EDMAHandle[channelIndex] = handle; - - /* Enable NVIC interrupt */ - EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]); - - /* - Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set), - CSR will be 0. Because in order to suit EDMA busy check mechanism in - EDMA_SubmitTransfer, CSR must be set 0. - */ - tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - tcdRegs->SADDR = 0; - tcdRegs->SOFF = 0; - tcdRegs->ATTR = 0; - tcdRegs->NBYTES = 0; - tcdRegs->SLAST = 0; - tcdRegs->DADDR = 0; - tcdRegs->DOFF = 0; - tcdRegs->CITER = 0; - tcdRegs->DLAST_SGA = 0; - tcdRegs->CSR = 0; - tcdRegs->BITER = 0; -} - -void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) -{ - assert(handle != NULL); - assert(((uint32_t)tcdPool & 0x1FU) == 0); - - /* Initialize tcd queue attibute. */ - handle->header = 0; - handle->tail = 0; - handle->tcdUsed = 0; - handle->tcdSize = tcdSize; - handle->flags = 0; - handle->tcdPool = tcdPool; -} - -void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) -{ - assert(handle != NULL); - - handle->callback = callback; - handle->userData = userData; -} - -void EDMA_PrepareTransfer(edma_transfer_config_t *config, - void *srcAddr, - uint32_t srcWidth, - void *destAddr, - uint32_t destWidth, - uint32_t bytesEachRequest, - uint32_t transferBytes, - edma_transfer_type_t type) -{ - assert(config != NULL); - assert(srcAddr != NULL); - assert(destAddr != NULL); - assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U)); - assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U)); - assert(transferBytes % bytesEachRequest == 0); - - config->destAddr = (uint32_t)destAddr; - config->srcAddr = (uint32_t)srcAddr; - config->minorLoopBytes = bytesEachRequest; - config->majorLoopCounts = transferBytes / bytesEachRequest; - switch (srcWidth) - { - case 1U: - config->srcTransferSize = kEDMA_TransferSize1Bytes; - break; - case 2U: - config->srcTransferSize = kEDMA_TransferSize2Bytes; - break; - case 4U: - config->srcTransferSize = kEDMA_TransferSize4Bytes; - break; - case 16U: - config->srcTransferSize = kEDMA_TransferSize16Bytes; - break; - case 32U: - config->srcTransferSize = kEDMA_TransferSize32Bytes; - break; - default: - break; - } - switch (destWidth) - { - case 1U: - config->destTransferSize = kEDMA_TransferSize1Bytes; - break; - case 2U: - config->destTransferSize = kEDMA_TransferSize2Bytes; - break; - case 4U: - config->destTransferSize = kEDMA_TransferSize4Bytes; - break; - case 16U: - config->destTransferSize = kEDMA_TransferSize16Bytes; - break; - case 32U: - config->destTransferSize = kEDMA_TransferSize32Bytes; - break; - default: - break; - } - switch (type) - { - case kEDMA_MemoryToMemory: - config->destOffset = destWidth; - config->srcOffset = srcWidth; - break; - case kEDMA_MemoryToPeripheral: - config->destOffset = 0U; - config->srcOffset = srcWidth; - break; - case kEDMA_PeripheralToMemory: - config->destOffset = destWidth; - config->srcOffset = 0U; - break; - default: - break; - } -} - -status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) -{ - assert(handle != NULL); - assert(config != NULL); - - edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - - if (handle->tcdPool == NULL) - { - /* - Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because - if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit - this check mechanism, EDMA_CreatHandle will clear CSR register. - */ - if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0)) - { - return kStatus_EDMA_Busy; - } - else - { - EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL); - /* Enable auto disable request feature */ - handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK; - /* Enable major interrupt */ - handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK; - - return kStatus_Success; - } - } - else /* Use the TCD queue. */ - { - uint32_t primask; - uint32_t csr; - int8_t currentTcd; - int8_t previousTcd; - int8_t nextTcd; - - /* Check if tcd pool is full. */ - primask = DisableGlobalIRQ(); - if (handle->tcdUsed >= handle->tcdSize) - { - EnableGlobalIRQ(primask); - - return kStatus_EDMA_QueueFull; - } - currentTcd = handle->tail; - handle->tcdUsed++; - /* Calculate index of next TCD */ - nextTcd = currentTcd + 1U; - if (nextTcd == handle->tcdSize) - { - nextTcd = 0U; - } - /* Advance queue tail index */ - handle->tail = nextTcd; - EnableGlobalIRQ(primask); - /* Calculate index of previous TCD */ - previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U; - /* Configure current TCD block. */ - EDMA_TcdReset(&handle->tcdPool[currentTcd]); - EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); - /* Enable major interrupt */ - handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; - /* Link current TCD with next TCD for identification of current TCD */ - handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd]; - /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ - if (currentTcd != previousTcd) - { - /* Enable scatter/gather feature in the previous TCD block. */ - csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; - handle->tcdPool[previousTcd].CSR = csr; - /* - Check if the TCD blcok in the registers is the previous one (points to current TCD block). It - is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to - link the TCD register in case link the current TCD with the dead chain when TCD loading occurs - before link the previous TCD block. - */ - if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) - { - /* Clear the DREQ bits for the dynamic scatter gather */ - tcdRegs->CSR |= DMA_CSR_DREQ_MASK; - /* Enable scatter/gather also in the TCD registers. */ - csr = tcdRegs->CSR | DMA_CSR_ESG_MASK; - /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ - tcdRegs->CSR = csr; - /* - It is very important to check the ESG bit! - Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can - be used to check if the dynamic TCD link operation is successful. If ESG bit is not set - and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and - the current TCD block has been loaded into TCD registers), it means transfer finished - and TCD link operation fail, so must install TCD content into TCD registers and enable - transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic - link succeed. - */ - if (tcdRegs->CSR & DMA_CSR_ESG_MASK) - { - tcdRegs->CSR &= ~DMA_CSR_DREQ_MASK; - return kStatus_Success; - } - /* - Check whether the current TCD block is already loaded in the TCD registers. It is another - condition when ESG bit is not set: it means the dynamic TCD link succeed and the current - TCD block has been loaded into TCD registers. - */ - if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd]) - { - return kStatus_Success; - } - /* - If go to this, means the previous transfer finished, and the DONE bit is set. - So shall configure TCD registers. - */ - } - else if (tcdRegs->DLAST_SGA != 0) - { - /* The current TCD block has been linked successfully. */ - return kStatus_Success; - } - else - { - /* - DLAST_SGA is 0 and it means the first submit transfer, so shall configure - TCD registers. - */ - } - } - /* There is no live chain, TCD block need to be installed in TCD registers. */ - EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); - /* Enable channel request again. */ - if (handle->flags & EDMA_TRANSFER_ENABLED_MASK) - { - handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); - } - - return kStatus_Success; - } -} - -void EDMA_StartTransfer(edma_handle_t *handle) -{ - assert(handle != NULL); - - if (handle->tcdPool == NULL) - { - handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); - } - else /* Use the TCD queue. */ - { - uint32_t primask; - edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - - handle->flags |= EDMA_TRANSFER_ENABLED_MASK; - - /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */ - if (tcdRegs->DLAST_SGA != 0U) - { - primask = DisableGlobalIRQ(); - /* Check if channel request is actually disable. */ - if ((handle->base->ERQ & (1U << handle->channel)) == 0U) - { - /* Check if transfer is paused. */ - if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK)) - { - /* - Re-enable channel request must be as soon as possible, so must put it into - critical section to avoid task switching or interrupt service routine. - */ - handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); - } - } - EnableGlobalIRQ(primask); - } - } -} - -void EDMA_StopTransfer(edma_handle_t *handle) -{ - assert(handle != NULL); - - handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK); - handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); -} - -void EDMA_AbortTransfer(edma_handle_t *handle) -{ - handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); - /* - Clear CSR to release channel. Because if the given channel started transfer, - CSR will be not zero. Because if it is the last transfer, DREQ will be set. - If not, ESG will be set. - */ - handle->base->TCD[handle->channel].CSR = 0; - /* Cancel all next TCD transfer. */ - handle->base->TCD[handle->channel].DLAST_SGA = 0; - - /* Handle the tcd */ - if (handle->tcdPool != NULL) - { - handle->header = 0; - handle->tail = 0; - handle->tcdUsed = 0; - } -} - -void EDMA_HandleIRQ(edma_handle_t *handle) -{ - assert(handle != NULL); - - /* Clear EDMA interrupt flag */ - handle->base->CINT = handle->channel; - if ((handle->tcdPool == NULL) && (handle->callback != NULL)) - { - (handle->callback)(handle, handle->userData, true, 0); - } - else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */ - { - uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA; - uint32_t sga_index; - int32_t tcds_done; - uint8_t new_header; - bool transfer_done; - - /* Check if transfer is already finished. */ - transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0); - /* Get the offset of the next transfer TCD blcoks to be loaded into the eDMA engine. */ - sga -= (uint32_t)handle->tcdPool; - /* Get the index of the next transfer TCD blcoks to be loaded into the eDMA engine. */ - sga_index = sga / sizeof(edma_tcd_t); - /* Adjust header positions. */ - if (transfer_done) - { - /* New header shall point to the next TCD to be loaded (current one is already finished) */ - new_header = sga_index; - } - else - { - /* New header shall point to this descriptor currently loaded (not finished yet) */ - new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U; - } - /* Calculate the number of finished TCDs */ - if (new_header == handle->header) - { - if (handle->tcdUsed == handle->tcdSize) - { - tcds_done = handle->tcdUsed; - } - else - { - /* No TCD in the memory are going to be loaded or internal error occurs. */ - tcds_done = 0; - } - } - else - { - tcds_done = new_header - handle->header; - if (tcds_done < 0) - { - tcds_done += handle->tcdSize; - } - } - /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */ - handle->header = new_header; - /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */ - handle->tcdUsed -= tcds_done; - /* Invoke callback function. */ - if (handle->callback) - { - (handle->callback)(handle, handle->userData, transfer_done, tcds_done); - } - } -} - -/* 8 channels (Shared): kl28 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U - -#if defined(DMA0) -void DMA0_04_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_37_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(DMA1) - -#if defined(DMA0) -void DMA1_04_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_37_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#else -void DMA1_04_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_37_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif -#endif /* 8 channels (Shared) */ - -/* 16 channels (Shared): K32H844P */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U - -void DMA0_08_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_19_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_210_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_311_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_412_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_513_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_614_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_715_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#if defined(DMA1) -void DMA1_08_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[16]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[24]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_19_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[17]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[25]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_210_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[18]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[26]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_311_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[19]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[27]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_412_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[20]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[28]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_513_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[21]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[29]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_614_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[22]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[30]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_715_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[23]); - } - if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[31]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif /* 16 channels (Shared) */ - -/* 32 channels (Shared): k80 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U - -void DMA0_DMA16_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[16]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_DMA17_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[17]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA2_DMA18_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[18]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA3_DMA19_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[19]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA4_DMA20_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[20]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA5_DMA21_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[21]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA6_DMA22_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[22]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA7_DMA23_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[23]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA8_DMA24_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[24]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA9_DMA25_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[25]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA10_DMA26_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[26]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA11_DMA27_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[27]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA12_DMA28_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[28]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA13_DMA29_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[29]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA14_DMA30_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[30]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA15_DMA31_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[31]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* 32 channels (Shared) */ - -/* 32 channels (Shared): MCIMX7U5_M4 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U - -void DMA0_0_4_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[0]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[4]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_1_5_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[1]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[5]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_2_6_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[2]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[6]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_3_7_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[3]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[7]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_8_12_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[8]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[12]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_9_13_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[9]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[13]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_10_14_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[10]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[14]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_11_15_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[11]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[15]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_16_20_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[16]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[20]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_17_21_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[17]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[21]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_18_22_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[18]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[22]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_19_23_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[19]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[23]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_24_28_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[24]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[28]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_25_29_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[25]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[29]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_26_30_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[26]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[30]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA0_27_31_DriverIRQHandler(void) -{ - if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[27]); - } - if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) - { - EDMA_HandleIRQ(s_EDMAHandle[31]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* 32 channels (Shared): MCIMX7U5 */ - -/* 4 channels (No Shared): kv10 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0 - -void DMA0_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA1_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[1]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA2_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[2]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA3_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[3]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -/* 8 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U - -void DMA4_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[4]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA5_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[5]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA6_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[6]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA7_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[7]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */ - -/* 16 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U - -void DMA8_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[8]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA9_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[9]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA10_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[10]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA11_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[11]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA12_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[12]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA13_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[13]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA14_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[14]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA15_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[15]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */ - -/* 32 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U - -void DMA16_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[16]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA17_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[17]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA18_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[18]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA19_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[19]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA20_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[20]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA21_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[21]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA22_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[22]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA23_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[23]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA24_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[24]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA25_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[25]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA26_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[26]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA27_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[27]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA28_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[28]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA29_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[29]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA30_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[30]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void DMA31_DriverIRQHandler(void) -{ - EDMA_HandleIRQ(s_EDMAHandle[31]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */ - -#endif /* 4/8/16/32 channels (No Shared) */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_edma.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_edma.h deleted file mode 100644 index 03bc8db16d..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_edma.h +++ /dev/null @@ -1,957 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_EDMA_H_ -#define _FSL_EDMA_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup edma - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief eDMA driver version */ -#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2. */ -/*@}*/ - -/*! @brief Compute the offset unit from DCHPRI3 */ -#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U))) - -/*! @brief Get the pointer of DCHPRIn */ -#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&((base)->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] - -/*! @brief eDMA transfer configuration */ -typedef enum _edma_transfer_size -{ - kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ - kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ - kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ - kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */ - kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ - kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ -} edma_transfer_size_t; - -/*! @brief eDMA modulo configuration */ -typedef enum _edma_modulo -{ - kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */ - kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */ - kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */ - kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */ - kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */ - kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */ - kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */ - kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */ - kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */ - kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */ - kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1 K bytes. */ - kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2 K bytes. */ - kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4 K bytes. */ - kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8 K bytes. */ - kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16 K bytes. */ - kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32 K bytes. */ - kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64 K bytes. */ - kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128 K bytes. */ - kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256 K bytes. */ - kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512 K bytes. */ - kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1 M bytes. */ - kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2 M bytes. */ - kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4 M bytes. */ - kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8 M bytes. */ - kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16 M bytes. */ - kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32 M bytes. */ - kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64 M bytes. */ - kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128 M bytes. */ - kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256 M bytes. */ - kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512 M bytes. */ - kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1 G bytes. */ - kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2 G bytes. */ -} edma_modulo_t; - -/*! @brief Bandwidth control */ -typedef enum _edma_bandwidth -{ - kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ - kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ - kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */ -} edma_bandwidth_t; - -/*! @brief Channel link type */ -typedef enum _edma_channel_link_type -{ - kEDMA_LinkNone = 0x0U, /*!< No channel link */ - kEDMA_MinorLink, /*!< Channel link after each minor loop */ - kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */ -} edma_channel_link_type_t; - -/*!@brief eDMA channel status flags. */ -enum _edma_channel_status_flags -{ - kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ - kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ - kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ -}; - -/*! @brief eDMA channel error status flags. */ -enum _edma_error_status_flags -{ - kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */ - kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */ - kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ - kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */ - kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */ - kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */ - kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */ - kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/ - kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */ - kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */ - kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */ -#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1 - kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */ -#endif - kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ -}; - -/*! @brief eDMA interrupt source */ -typedef enum _edma_interrupt_enable -{ - kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ - kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ - kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ -} edma_interrupt_enable_t; - -/*! @brief eDMA transfer type */ -typedef enum _edma_transfer_type -{ - kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */ - kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */ - kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */ -} edma_transfer_type_t; - -/*! @brief eDMA transfer status */ -enum _edma_transfer_status -{ - kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */ - kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the - transfer request. */ -}; - -/*! @brief eDMA global configuration structure.*/ -typedef struct _edma_config -{ - bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel - activates again if that channel has a minor loop channel link enabled and - the link channel is itself. */ - bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. - Subsequently, all service requests are ignored until the HALT bit is cleared.*/ - bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method or fixed priority - arbitration is used for channel selection */ - bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of - a new channel. Executing channels are allowed to complete. */ -} edma_config_t; - -/*! - * @brief eDMA transfer configuration - * - * This structure configures the source/destination transfer attribute. - */ -typedef struct _edma_transfer_config -{ - uint32_t srcAddr; /*!< Source data address. */ - uint32_t destAddr; /*!< Destination data address. */ - edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ - edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ - int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to - form the next-state value as each source read is completed. */ - int16_t destOffset; /*!< Sign-extended offset applied to the current destination address to - form the next-state value as each destination write is completed. */ - uint32_t minorLoopBytes; /*!< Bytes to transfer in a minor loop*/ - uint32_t majorLoopCounts; /*!< Major loop iteration count. */ -} edma_transfer_config_t; - -/*! @brief eDMA channel priority configuration */ -typedef struct _edma_channel_Preemption_config -{ - bool enableChannelPreemption; /*!< If true: a channel can be suspended by other channel with higher priority */ - bool enablePreemptAbility; /*!< If true: a channel can suspend other channel with low priority */ - uint8_t channelPriority; /*!< Channel priority */ -} edma_channel_Preemption_config_t; - -/*! @brief eDMA minor offset configuration */ -typedef struct _edma_minor_offset_config -{ - bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */ - bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */ - uint32_t minorOffset; /*!< Offset for a minor loop mapping. */ -} edma_minor_offset_config_t; - -/*! - * @brief eDMA TCD. - * - * This structure is same as TCD register which is described in reference manual, - * and is used to configure the scatter/gather feature as a next hardware TCD. - */ -typedef struct _edma_tcd -{ - __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ - __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ - __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ - __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ - __IO uint32_t SLAST; /*!< SLAST register */ - __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ - __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ - __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ - __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */ - __IO uint16_t CSR; /*!< CSR register, for TCD control status */ - __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ -} edma_tcd_t; - -/*! @brief Callback for eDMA */ -struct _edma_handle; - -/*! @brief Define callback function for eDMA. - * - * This callback function is called in the EDMA interrupt handle. - * In normal mode, run into callback function means the transfer users need is done. - * In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not - * all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber. - * - * @param handle EDMA handle pointer, users shall not touch the values inside. - * @param userData The callback user paramter pointer. Users can use this paramter to involve things users need to - * change in EDMA callback function. - * @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter - * gather mode, this paramter shows is the current transfer block in EDMA regsiter is done. As the - * load of core is different, it will be different if the new tcd loaded into EDMA registers while - * this callback called. If true, it always means new tcd still not loaded into registers, while - * false means new tcd already loaded into registers. - * @param tcds How many tcds are done from the last callback. This parameter only used in scatter gather mode. It - * tells user how many tcds are finished between the last callback and this. - */ -typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); - -/*! @brief eDMA transfer handle structure */ -typedef struct _edma_handle -{ - edma_callback callback; /*!< Callback function for major count exhausted. */ - void *userData; /*!< Callback function parameter. */ - DMA_Type *base; /*!< eDMA peripheral base address. */ - edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ - uint8_t channel; /*!< eDMA channel number. */ - volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */ - volatile int8_t tail; /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */ - volatile int8_t tcdUsed; /*!< The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in - the memory. */ - volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */ - uint8_t flags; /*!< The status of the current channel. */ -} edma_handle_t; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name eDMA initialization and de-initialization - * @{ - */ - -/*! - * @brief Initializes the eDMA peripheral. - * - * This function ungates the eDMA clock and configures the eDMA peripheral according - * to the configuration structure. - * - * @param base eDMA peripheral base address. - * @param config A pointer to the configuration structure, see "edma_config_t". - * @note This function enables the minor loop map feature. - */ -void EDMA_Init(DMA_Type *base, const edma_config_t *config); - -/*! - * @brief Deinitializes the eDMA peripheral. - * - * This function gates the eDMA clock. - * - * @param base eDMA peripheral base address. - */ -void EDMA_Deinit(DMA_Type *base); - -/*! - * @brief Push content of TCD structure into hardware TCD register. - * - * @param base EDMA peripheral base address. - * @param channel EDMA channel number. - * @param tcd Point to TCD structure. - */ -void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd); - -/*! - * @brief Gets the eDMA default configuration structure. - * - * This function sets the configuration structure to default values. - * The default configuration is set to the following values. - * @code - * config.enableContinuousLinkMode = false; - * config.enableHaltOnError = true; - * config.enableRoundRobinArbitration = false; - * config.enableDebugMode = false; - * @endcode - * - * @param config A pointer to the eDMA configuration structure. - */ -void EDMA_GetDefaultConfig(edma_config_t *config); - -/* @} */ -/*! - * @name eDMA Channel Operation - * @{ - */ - -/*! - * @brief Sets all TCD registers to default values. - * - * This function sets TCD registers for this channel to default values. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @note This function must not be called while the channel transfer is ongoing - * or it causes unpredictable results. - * @note This function enables the auto stop request feature. - */ -void EDMA_ResetChannel(DMA_Type *base, uint32_t channel); - -/*! - * @brief Configures the eDMA transfer attribute. - * - * This function configures the transfer attribute, including source address, destination address, - * transfer size, address offset, and so on. It also configures the scatter gather feature if the - * user supplies the TCD address. - * Example: - * @code - * edma_transfer_t config; - * edma_tcd_t tcd; - * config.srcAddr = ..; - * config.destAddr = ..; - * ... - * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); - * @endcode - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param config Pointer to eDMA transfer configuration structure. - * @param nextTcd Point to TCD structure. It can be NULL if users - * do not want to enable scatter/gather feature. - * @note If nextTcd is not NULL, it means scatter gather feature is enabled - * and DREQ bit is cleared in the previous transfer configuration, which - * is set in the eDMA_ResetChannel. - */ -void EDMA_SetTransferConfig(DMA_Type *base, - uint32_t channel, - const edma_transfer_config_t *config, - edma_tcd_t *nextTcd); - -/*! - * @brief Configures the eDMA minor offset feature. - * - * The minor offset means that the signed-extended value is added to the source address or destination - * address after each minor loop. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param config A pointer to the minor offset configuration structure. - */ -void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config); - -/*! - * @brief Configures the eDMA channel preemption feature. - * - * This function configures the channel preemption attribute and the priority of the channel. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number - * @param config A pointer to the channel preemption configuration structure. - */ -static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base, - uint32_t channel, - const edma_channel_Preemption_config_t *config) -{ - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(config != NULL); - - DMA_DCHPRIn(base, channel) = - (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) | - DMA_DCHPRI0_CHPRI(config->channelPriority)); -} - -/*! - * @brief Sets the channel link for the eDMA transfer. - * - * This function configures either the minor link or the major link mode. The minor link means that the channel link is - * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is - * exhausted. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param type A channel link type, which can be one of the following: - * @arg kEDMA_LinkNone - * @arg kEDMA_MinorLink - * @arg kEDMA_MajorLink - * @param linkedChannel The linked channel number. - * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. - */ -void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel); - -/*! - * @brief Sets the bandwidth for the eDMA transfer. - * - * Because the eDMA processes the minor loop, it continuously generates read/write sequences - * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of - * each read/write access to control the bus request bandwidth seen by the crossbar switch. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param bandWidth A bandwidth setting, which can be one of the following: - * @arg kEDMABandwidthStallNone - * @arg kEDMABandwidthStall4Cycle - * @arg kEDMABandwidthStall8Cycle - */ -void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth); - -/*! - * @brief Sets the source modulo and the destination modulo for the eDMA transfer. - * - * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) - * calculation is performed or the original register value. It provides the ability to implement a circular data - * queue easily. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param srcModulo A source modulo value. - * @param destModulo A destination modulo value. - */ -void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo); - -#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT -/*! - * @brief Enables an async request for the eDMA transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param enable The command to enable (true) or disable (false). - */ -static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel); -} -#endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */ - -/*! - * @brief Enables an auto stop request for the eDMA transfer. - * - * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param enable The command to enable (true) or disable (false). - */ -static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); -} - -/*! - * @brief Enables the interrupt source for the eDMA transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param mask The mask of interrupt source to be set. Users need to use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); - -/*! - * @brief Disables the interrupt source for the eDMA transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param mask The mask of the interrupt source to be set. Use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); - -/* @} */ -/*! - * @name eDMA TCD Operation - * @{ - */ - -/*! - * @brief Sets all fields to default values for the TCD structure. - * - * This function sets all fields for this TCD structure to default value. - * - * @param tcd Pointer to the TCD structure. - * @note This function enables the auto stop request feature. - */ -void EDMA_TcdReset(edma_tcd_t *tcd); - -/*! - * @brief Configures the eDMA TCD transfer attribute. - * - * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. - * The STCD is used in the scatter-gather mode. - * This function configures the TCD transfer attribute, including source address, destination address, - * transfer size, address offset, and so on. It also configures the scatter gather feature if the - * user supplies the next TCD address. - * Example: - * @code - * edma_transfer_t config = { - * ... - * } - * edma_tcd_t tcd __aligned(32); - * edma_tcd_t nextTcd __aligned(32); - * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); - * @endcode - * - * @param tcd Pointer to the TCD structure. - * @param config Pointer to eDMA transfer configuration structure. - * @param nextTcd Pointer to the next TCD structure. It can be NULL if users - * do not want to enable scatter/gather feature. - * @note TCD address should be 32 bytes aligned or it causes an eDMA error. - * @note If the nextTcd is not NULL, the scatter gather feature is enabled - * and DREQ bit is cleared in the previous transfer configuration, which - * is set in the EDMA_TcdReset. - */ -void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd); - -/*! - * @brief Configures the eDMA TCD minor offset feature. - * - * A minor offset is a signed-extended value added to the source address or a destination - * address after each minor loop. - * - * @param tcd A point to the TCD structure. - * @param config A pointer to the minor offset configuration structure. - */ -void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config); - -/*! - * @brief Sets the channel link for the eDMA TCD. - * - * This function configures either a minor link or a major link. The minor link means the channel link is - * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is - * exhausted. - * - * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. - * @param tcd Point to the TCD structure. - * @param type Channel link type, it can be one of: - * @arg kEDMA_LinkNone - * @arg kEDMA_MinorLink - * @arg kEDMA_MajorLink - * @param linkedChannel The linked channel number. - */ -void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); - -/*! - * @brief Sets the bandwidth for the eDMA TCD. - * - * Because the eDMA processes the minor loop, it continuously generates read/write sequences - * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of - * each read/write access to control the bus request bandwidth seen by the crossbar switch. - * @param tcd A pointer to the TCD structure. - * @param bandWidth A bandwidth setting, which can be one of the following: - * @arg kEDMABandwidthStallNone - * @arg kEDMABandwidthStall4Cycle - * @arg kEDMABandwidthStall8Cycle - */ -static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); -} - -/*! - * @brief Sets the source modulo and the destination modulo for the eDMA TCD. - * - * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) - * calculation is performed or the original register value. It provides the ability to implement a circular data - * queue easily. - * - * @param tcd A pointer to the TCD structure. - * @param srcModulo A source modulo value. - * @param destModulo A destination modulo value. - */ -void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); - -/*! - * @brief Sets the auto stop request for the eDMA TCD. - * - * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. - * - * @param tcd A pointer to the TCD structure. - * @param enable The command to enable (true) or disable (false). - */ -static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) -{ - assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - - tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); -} - -/*! - * @brief Enables the interrupt source for the eDMA TCD. - * - * @param tcd Point to the TCD structure. - * @param mask The mask of interrupt source to be set. Users need to use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask); - -/*! - * @brief Disables the interrupt source for the eDMA TCD. - * - * @param tcd Point to the TCD structure. - * @param mask The mask of interrupt source to be set. Users need to use - * the defined edma_interrupt_enable_t type. - */ -void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); - -/*! @} */ -/*! - * @name eDMA Channel Transfer Operation - * @{ - */ - -/*! - * @brief Enables the eDMA hardware channel request. - * - * This function enables the hardware channel request. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->SERQ = DMA_SERQ_SERQ(channel); -} - -/*! - * @brief Disables the eDMA hardware channel request. - * - * This function disables the hardware channel request. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->CERQ = DMA_CERQ_CERQ(channel); -} - -/*! - * @brief Starts the eDMA transfer by using the software trigger. - * - * This function starts a minor loop transfer. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) -{ - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - - base->SSRT = DMA_SSRT_SSRT(channel); -} - -/*! @} */ -/*! - * @name eDMA Channel Status Operation - * @{ - */ - -/*! - * @brief Gets the remaining major loop count from the eDMA current channel TCD. - * - * This function checks the TCD (Task Control Descriptor) status for a specified - * eDMA channel and returns the number of major loop count that has not finished. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @return Major loop count which has not been transferred yet for the current TCD. - * @note 1. This function can only be used to get unfinished major loop count of transfer without - * the next TCD, or it might be inaccuracy. - * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while - * the channel is running. - * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO - * register is needed while the eDMA IP does not support getting it while a channel is active. - * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine - * is working with while a channel is running. - * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example - * copied before enabling the channel) is needed. The formula to calculate it is shown below: - * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) - */ -uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel); - -/*! - * @brief Gets the eDMA channel error status flags. - * - * @param base eDMA peripheral base address. - * @return The mask of error status flags. Users need to use the -* _edma_error_status_flags type to decode the return variables. - */ -static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base) -{ - return base->ES; -} - -/*! - * @brief Gets the eDMA channel status flags. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @return The mask of channel status flags. Users need to use the - * _edma_channel_status_flags type to decode the return variables. - */ -uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel); - -/*! - * @brief Clears the eDMA channel status flags. - * - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - * @param mask The mask of channel status to be cleared. Users need to use - * the defined _edma_channel_status_flags type. - */ -void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask); - -/*! @} */ -/*! - * @name eDMA Transactional Operation - */ - -/*! - * @brief Creates the eDMA handle. - * - * This function is called if using the transactional API for eDMA. This function - * initializes the internal state of the eDMA handle. - * - * @param handle eDMA handle pointer. The eDMA handle stores callback function and - * parameters. - * @param base eDMA peripheral base address. - * @param channel eDMA channel number. - */ -void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel); - -/*! - * @brief Installs the TCDs memory pool into the eDMA handle. - * - * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used - * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block - * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. - * Users need to preapre tcd memory and also configure tcds using interface EDMA_SubmitTransfer. - * - * @param handle eDMA handle pointer. - * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. - * @param tcdSize The number of TCD slots. - */ -void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize); - -/*! - * @brief Installs a callback function for the eDMA transfer. - * - * This callback is called in the eDMA IRQ handler. Use the callback to do something after - * the current major loop transfer completes. This function will be called every time one tcd finished transfer. - * - * @param handle eDMA handle pointer. - * @param callback eDMA callback function pointer. - * @param userData A parameter for the callback function. - */ -void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData); - -/*! - * @brief Prepares the eDMA transfer structure. - * - * This function prepares the transfer configuration structure according to the user input. - * - * @param config The user configuration structure of type edma_transfer_t. - * @param srcAddr eDMA transfer source address. - * @param srcWidth eDMA transfer source address width(bytes). - * @param destAddr eDMA transfer destination address. - * @param destWidth eDMA transfer destination address width(bytes). - * @param bytesEachRequest eDMA transfer bytes per channel request. - * @param transferBytes eDMA transfer bytes to be transferred. - * @param type eDMA transfer type. - * @note The data address and the data width must be consistent. For example, if the SRC - * is 4 bytes, the source address must be 4 bytes aligned, or it results in - * source address error (SAE). - */ -void EDMA_PrepareTransfer(edma_transfer_config_t *config, - void *srcAddr, - uint32_t srcWidth, - void *destAddr, - uint32_t destWidth, - uint32_t bytesEachRequest, - uint32_t transferBytes, - edma_transfer_type_t type); - -/*! - * @brief Submits the eDMA transfer request. - * - * This function submits the eDMA transfer request according to the transfer configuration structure. - * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. - * The tcd pools is setup by call function EDMA_InstallTCDMemory before. - * - * @param handle eDMA handle pointer. - * @param config Pointer to eDMA transfer configuration structure. - * @retval kStatus_EDMA_Success It means submit transfer request succeed. - * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. - * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. - */ -status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config); - -/*! - * @brief eDMA starts transfer. - * - * This function enables the channel request. Users can call this function after submitting the transfer request - * or before submitting the transfer request. - * - * @param handle eDMA handle pointer. - */ -void EDMA_StartTransfer(edma_handle_t *handle); - -/*! - * @brief eDMA stops transfer. - * - * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() - * again to resume the transfer. - * - * @param handle eDMA handle pointer. - */ -void EDMA_StopTransfer(edma_handle_t *handle); - -/*! - * @brief eDMA aborts transfer. - * - * This function disables the channel request and clear transfer status bits. - * Users can submit another transfer after calling this API. - * - * @param handle DMA handle pointer. - */ -void EDMA_AbortTransfer(edma_handle_t *handle); - -/*! - * @brief Get unused TCD slot number. - * - * This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0. - * - * @param handle DMA handle pointer. - * @return The unused tcd slot number. - */ -static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle) -{ - return (handle->tcdSize - handle->tcdUsed); -} - -/*! - * @brief Get the next tcd address. - * - * This function gets the next tcd address. If this is last TCD, return 0. - * - * @param handle DMA handle pointer. - * @return The next TCD address. - */ -static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle) -{ - return (handle->base->TCD[handle->channel].DLAST_SGA); -} - -/*! - * @brief eDMA IRQ handler for the current major loop transfer completion. - * - * This function clears the channel major interrupt flag and calls - * the callback function if it is not NULL. - * - * Note: - * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. - * These include the final address adjustments and reloading of the BITER field into the CITER. - * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from - * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). - * - * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. - * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index - * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be - * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have - * been loaded into the eDMA engine at this point already.). - * - * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not - * load a new TCD) from the memory pool to the eDMA engine when major loop completes. - * Therefore, ensure that the header and tcdUsed updated are identical for them. - * tcdUsed are both 0 in this case as no TCD to be loaded. - * - * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for - * further details. - * - * @param handle eDMA handle pointer. - */ -void EDMA_HandleIRQ(edma_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /*_FSL_EDMA_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_elcdif.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_elcdif.c deleted file mode 100644 index 51aabe3b88..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_elcdif.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2017, NXP Semiconductors, Inc. - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_elcdif.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.elcdif" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get instance number for ELCDIF module. - * - * @param base ELCDIF peripheral base address - */ -static uint32_t ELCDIF_GetInstance(LCDIF_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Pointers to ELCDIF bases for each instance. */ -static LCDIF_Type *const s_elcdifBases[] = LCDIF_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to eLCDIF apb_clk for each instance. */ -static const clock_ip_name_t s_elcdifApbClocks[] = LCDIF_CLOCKS; -#if defined(LCDIF_PERIPH_CLOCKS) -/*! @brief Pointers to eLCDIF pix_clk for each instance. */ -static const clock_ip_name_t s_elcdifPixClocks[] = LCDIF_PERIPH_CLOCKS; -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief The control register value to select different pixel format. */ -elcdif_pixel_format_reg_t s_pixelFormatReg[] = { - /* kELCDIF_PixelFormatRAW8 */ - {/* Register CTRL. */ - LCDIF_CTRL_WORD_LENGTH(1U), - /* Register CTRL1. */ - LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)}, - /* kELCDIF_PixelFormatRGB565 */ - {/* Register CTRL. */ - LCDIF_CTRL_WORD_LENGTH(0U), - /* Register CTRL1. */ - LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)}, - /* kELCDIF_PixelFormatRGB666 */ - {/* Register CTRL. */ - LCDIF_CTRL_WORD_LENGTH(3U) | LCDIF_CTRL_DATA_FORMAT_24_BIT(1U), - /* Register CTRL1. */ - LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)}, - /* kELCDIF_PixelFormatXRGB8888 */ - {/* Register CTRL. 24-bit. */ - LCDIF_CTRL_WORD_LENGTH(3U), - /* Register CTRL1. */ - LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)}, - /* kELCDIF_PixelFormatRGB888 */ - {/* Register CTRL. 24-bit. */ - LCDIF_CTRL_WORD_LENGTH(3U), - /* Register CTRL1. */ - LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)}, -}; - -/******************************************************************************* - * Codes - ******************************************************************************/ -static uint32_t ELCDIF_GetInstance(LCDIF_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_elcdifBases); instance++) - { - if (s_elcdifBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_elcdifBases)); - - return instance; -} - -void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config) -{ - assert(config); - assert(config->pixelFormat < ARRAY_SIZE(s_pixelFormatReg)); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - uint32_t instance = ELCDIF_GetInstance(base); - /* Enable the clock. */ - CLOCK_EnableClock(s_elcdifApbClocks[instance]); -#if defined(LCDIF_PERIPH_CLOCKS) - CLOCK_EnableClock(s_elcdifPixClocks[instance]); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset. */ - ELCDIF_Reset(base); - - base->CTRL = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl | (uint32_t)(config->dataBus) | - LCDIF_CTRL_DOTCLK_MODE_MASK | /* RGB mode. */ - LCDIF_CTRL_BYPASS_COUNT_MASK | /* Keep RUN bit set. */ - LCDIF_CTRL_MASTER_MASK; - - base->CTRL1 = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl1; - - base->TRANSFER_COUNT = ((uint32_t)config->panelHeight << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT) | - ((uint32_t)config->panelWidth << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT); - - base->VDCTRL0 = LCDIF_VDCTRL0_ENABLE_PRESENT_MASK | /* Data enable signal. */ - LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK | /* VSYNC period in the unit of display clock. */ - LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK | /* VSYNC pulse width in the unit of display clock. */ - (uint32_t)config->polarityFlags | (uint32_t)config->vsw; - - base->VDCTRL1 = config->vsw + config->panelHeight + config->vfp + config->vbp; - base->VDCTRL2 = ((uint32_t)config->hsw << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT) | - ((uint32_t)(config->hfp + config->hbp + config->panelWidth + config->hsw)) - << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT; - - base->VDCTRL3 = (((uint32_t)config->hbp + config->hsw) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT) | - (((uint32_t)config->vbp + config->vsw) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT); - - base->VDCTRL4 = LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK | - ((uint32_t)config->panelWidth << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT); - - base->CUR_BUF = config->bufferAddr; - base->NEXT_BUF = config->bufferAddr; -} - -void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config) -{ - assert(config); - - config->panelWidth = 480U; - config->panelHeight = 272U; - config->hsw = 41; - config->hfp = 4; - config->hbp = 8; - config->vsw = 10; - config->vfp = 4; - config->vbp = 2; - config->polarityFlags = kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveLow | - kELCDIF_DriveDataOnFallingClkEdge; - config->bufferAddr = 0U; - config->pixelFormat = kELCDIF_PixelFormatRGB888; - config->dataBus = kELCDIF_DataBus24Bit; -} - -void ELCDIF_Deinit(LCDIF_Type *base) -{ - ELCDIF_Reset(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - uint32_t instance = ELCDIF_GetInstance(base); -/* Disable the clock. */ -#if defined(LCDIF_PERIPH_CLOCKS) - CLOCK_DisableClock(s_elcdifPixClocks[instance]); -#endif - CLOCK_DisableClock(s_elcdifApbClocks[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void ELCDIF_RgbModeStop(LCDIF_Type *base) -{ - base->CTRL_CLR = LCDIF_CTRL_DOTCLK_MODE_MASK; - - /* Wait for data transfer finished. */ - while (base->CTRL & LCDIF_CTRL_DOTCLK_MODE_MASK) - { - } -} - -void ELCDIF_Reset(LCDIF_Type *base) -{ - volatile uint32_t i = 0x100; - - /* Disable the clock gate. */ - base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK; - /* Confirm the clock gate is disabled. */ - while (base->CTRL & LCDIF_CTRL_CLKGATE_MASK) - { - } - - /* Reset the block. */ - base->CTRL_SET = LCDIF_CTRL_SFTRST_MASK; - /* Confirm the reset bit is set. */ - while (!(base->CTRL & LCDIF_CTRL_SFTRST_MASK)) - { - } - - /* Delay for the reset. */ - while (i--) - { - } - - /* Bring the module out of reset. */ - base->CTRL_CLR = LCDIF_CTRL_SFTRST_MASK; - /* Disable the clock gate. */ - base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK; -} - -#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS) -void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config) -{ - assert(config); - - base->AS_CTRL = (base->AS_CTRL & ~LCDIF_AS_CTRL_FORMAT_MASK) | LCDIF_AS_CTRL_FORMAT(config->pixelFormat); - base->AS_BUF = config->bufferAddr; - base->AS_NEXT_BUF = config->bufferAddr; -} - -void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config) -{ - assert(config); - uint32_t reg; - - reg = base->AS_CTRL; - reg &= ~(LCDIF_AS_CTRL_ALPHA_INVERT_MASK | LCDIF_AS_CTRL_ROP_MASK | LCDIF_AS_CTRL_ALPHA_MASK | - LCDIF_AS_CTRL_ALPHA_CTRL_MASK); - reg |= (LCDIF_AS_CTRL_ROP(config->ropMode) | LCDIF_AS_CTRL_ALPHA(config->alpha) | - LCDIF_AS_CTRL_ALPHA_CTRL(config->alphaMode)); - - if (config->invertAlpha) - { - reg |= LCDIF_AS_CTRL_ALPHA_INVERT_MASK; - } - - base->AS_CTRL = reg; -} -#endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */ - -#if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT) -status_t ELCDIF_UpdateLut( - LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count) -{ - volatile uint32_t *regLutAddr; - volatile uint32_t *regLutData; - uint32_t i; - - /* Only has 256 entries. */ - if (startIndex + count > ELCDIF_LUT_ENTRY_NUM) - { - return kStatus_InvalidArgument; - } - - if (kELCDIF_Lut0 == lut) - { - regLutAddr = &(base->LUT0_ADDR); - regLutData = &(base->LUT0_DATA); - } - else - { - regLutAddr = &(base->LUT1_ADDR); - regLutData = &(base->LUT1_DATA); - } - - *regLutAddr = startIndex; - - for (i = 0; i < count; i++) - { - *regLutData = lutData[i]; - } - - return kStatus_Success; -} -#endif /* FSL_FEATURE_LCDIF_HAS_LUT */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_elcdif.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_elcdif.h deleted file mode 100644 index 2183c84f7d..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_elcdif.h +++ /dev/null @@ -1,768 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2017, NXP Semiconductors, Inc. - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_ELCDIF_H_ -#define _FSL_ELCDIF_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup elcdif - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief eLCDIF driver version */ -#define FSL_ELCDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ -/*@}*/ - -/* All IRQ flags in CTRL1 register. */ -#define ELCDIF_CTRL1_IRQ_MASK \ - (LCDIF_CTRL1_BM_ERROR_IRQ_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_MASK | \ - LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) - -/* All IRQ enable control bits in CTRL1 register. */ -#define ELCDIF_CTRL1_IRQ_EN_MASK \ - (LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK | \ - LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) - -/* All IRQ flags in AS_CTRL register. */ -#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) -#define ELCDIF_AS_CTRL_IRQ_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) -#else -#define ELCDIF_AS_CTRL_IRQ_MASK 0U -#endif - -/* All IRQ enable control bits in AS_CTRL register. */ -#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) -#define ELCDIF_AS_CTRL_IRQ_EN_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) -#else -#define ELCDIF_AS_CTRL_IRQ_EN_MASK 0U -#endif - -#if ((ELCDIF_CTRL1_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_MASK) || (ELCDIF_AS_CTRL_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_EN_MASK)) -#error Interrupt bits overlap, need to update the interrupt functions. -#endif - -/* LUT memory entery number. */ -#define ELCDIF_LUT_ENTRY_NUM 256 - -/*! - * @brief eLCDIF signal polarity flags - */ -enum _elcdif_polarity_flags -{ - kELCDIF_VsyncActiveLow = 0U, /*!< VSYNC active low. */ - kELCDIF_VsyncActiveHigh = LCDIF_VDCTRL0_VSYNC_POL_MASK, /*!< VSYNC active high. */ - kELCDIF_HsyncActiveLow = 0U, /*!< HSYNC active low. */ - kELCDIF_HsyncActiveHigh = LCDIF_VDCTRL0_HSYNC_POL_MASK, /*!< HSYNC active high. */ - kELCDIF_DataEnableActiveLow = 0U, /*!< Data enable line active low. */ - kELCDIF_DataEnableActiveHigh = LCDIF_VDCTRL0_ENABLE_POL_MASK, /*!< Data enable line active high. */ - kELCDIF_DriveDataOnFallingClkEdge = 0U, /*!< Drive data on falling clock edge, capture data - on rising clock edge. */ - kELCDIF_DriveDataOnRisingClkEdge = LCDIF_VDCTRL0_DOTCLK_POL_MASK, /*!< Drive data on falling - clock edge, capture data - on rising clock edge. */ -}; - -/*! - * @brief The eLCDIF interrupts to enable. - */ -enum _elcdif_interrupt_enable -{ - kELCDIF_BusMasterErrorInterruptEnable = LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK, /*!< Bus master error interrupt. */ - kELCDIF_TxFifoOverflowInterruptEnable = LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK, /*!< TXFIFO overflow interrupt. */ - kELCDIF_TxFifoUnderflowInterruptEnable = LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK, /*!< TXFIFO underflow interrupt. */ - kELCDIF_CurFrameDoneInterruptEnable = - LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK, /*!< Interrupt when hardware enters vertical blanking state. */ - kELCDIF_VsyncEdgeInterruptEnable = - LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */ -#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) - kELCDIF_SciSyncOnInterruptEnable = - LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */ -#endif -}; - -/*! - * @brief The eLCDIF interrupt status flags. - */ -enum _elcdif_interrupt_flags -{ - kELCDIF_BusMasterError = LCDIF_CTRL1_BM_ERROR_IRQ_MASK, /*!< Bus master error interrupt. */ - kELCDIF_TxFifoOverflow = LCDIF_CTRL1_OVERFLOW_IRQ_MASK, /*!< TXFIFO overflow interrupt. */ - kELCDIF_TxFifoUnderflow = LCDIF_CTRL1_UNDERFLOW_IRQ_MASK, /*!< TXFIFO underflow interrupt. */ - kELCDIF_CurFrameDone = - LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK, /*!< Interrupt when hardware enters vertical blanking state. */ - kELCDIF_VsyncEdge = LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */ -#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) - kELCDIF_SciSyncOn = LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */ -#endif -}; - -/*! - * @brief eLCDIF status flags - */ -enum _elcdif_status_flags -{ - kELCDIF_LFifoFull = LCDIF_STAT_LFIFO_FULL_MASK, /*!< LFIFO full. */ - kELCDIF_LFifoEmpty = LCDIF_STAT_LFIFO_EMPTY_MASK, /*!< LFIFO empty. */ - kELCDIF_TxFifoFull = LCDIF_STAT_TXFIFO_FULL_MASK, /*!< TXFIFO full. */ - kELCDIF_TxFifoEmpty = LCDIF_STAT_TXFIFO_EMPTY_MASK, /*!< TXFIFO empty. */ -#if defined(LCDIF_STAT_BUSY_MASK) - kELCDIF_LcdControllerBusy = LCDIF_STAT_BUSY_MASK, /*!< The external LCD controller busy signal. */ -#endif -#if defined(LCDIF_STAT_DVI_CURRENT_FIELD_MASK) - kELCDIF_CurDviField2 = LCDIF_STAT_DVI_CURRENT_FIELD_MASK, /*!< Current DVI filed, if set, then current filed is 2, - otherwise current filed is 1. */ -#endif -}; - -/*! - * @brief The pixel format. - * - * This enumerator should be defined together with the array s_pixelFormatReg. - * To support new pixel format, enhance this enumerator and s_pixelFormatReg. - */ -typedef enum _elcdif_pixel_format -{ - kELCDIF_PixelFormatRAW8 = 0, /*!< RAW 8 bit, four data use 32 bits. */ - kELCDIF_PixelFormatRGB565 = 1, /*!< RGB565, two pixel use 32 bits. */ - kELCDIF_PixelFormatRGB666 = 2, /*!< RGB666 unpacked, one pixel uses 32 bits, high byte unused, - upper 2 bits of other bytes unused. */ - kELCDIF_PixelFormatXRGB8888 = 3, /*!< XRGB8888 unpacked, one pixel uses 32 bits, high byte unused. */ - kELCDIF_PixelFormatRGB888 = 4, /*!< RGB888 packed, one pixel uses 24 bits. */ -} elcdif_pixel_format_t; - -/*! @brief The LCD data bus type. */ -typedef enum _elcdif_lcd_data_bus -{ - kELCDIF_DataBus8Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(1), /*!< 8-bit data bus. */ - kELCDIF_DataBus16Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(0), /*!< 16-bit data bus, support RGB565. */ - kELCDIF_DataBus18Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(2), /*!< 18-bit data bus, support RGB666. */ - kELCDIF_DataBus24Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /*!< 24-bit data bus, support RGB888. */ -} elcdif_lcd_data_bus_t; - -/*! - * @brief The register value when using different pixel format. - * - * These register bits control the pixel format: - * - CTRL[DATA_FORMAT_24_BIT] - * - CTRL[DATA_FORMAT_18_BIT] - * - CTRL[DATA_FORMAT_16_BIT] - * - CTRL[WORD_LENGTH] - * - CTRL1[BYTE_PACKING_FORMAT] - */ -typedef struct _elcdif_pixel_format_reg -{ - uint32_t regCtrl; /*!< Value of register CTRL. */ - uint32_t regCtrl1; /*!< Value of register CTRL1. */ -} elcdif_pixel_format_reg_t; - -/*! - * @brief eLCDIF configure structure for RGB mode (DOTCLK mode). - */ -typedef struct _elcdif_rgb_mode_config -{ - uint16_t panelWidth; /*!< Display panel width, pixels per line. */ - uint16_t panelHeight; /*!< Display panel height, how many lines per panel. */ - uint8_t hsw; /*!< HSYNC pulse width. */ - uint8_t hfp; /*!< Horizontal front porch. */ - uint8_t hbp; /*!< Horizontal back porch. */ - uint8_t vsw; /*!< VSYNC pulse width. */ - uint8_t vfp; /*!< Vrtical front porch. */ - uint8_t vbp; /*!< Vertical back porch. */ - uint32_t polarityFlags; /*!< OR'ed value of @ref _elcdif_polarity_flags, used to contol the signal polarity. */ - uint32_t bufferAddr; /*!< Frame buffer address. */ - elcdif_pixel_format_t pixelFormat; /*!< Pixel format. */ - elcdif_lcd_data_bus_t dataBus; /*!< LCD data bus. */ -} elcdif_rgb_mode_config_t; - -/*! - * @brief eLCDIF alpha surface pixel format. - */ -typedef enum _elcdif_as_pixel_format -{ - kELCDIF_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */ - kELCDIF_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */ - kELCDIF_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */ - kELCDIF_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */ - kELCDIF_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */ - kELCDIF_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */ - kELCDIF_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */ -} elcdif_as_pixel_format_t; - -/*! - * @brief eLCDIF alpha surface buffer configuration. - */ -typedef struct _elcdif_as_buffer_config -{ - uint32_t bufferAddr; /*!< Buffer address. */ - elcdif_as_pixel_format_t pixelFormat; /*!< Pixel format. */ -} elcdif_as_buffer_config_t; - -/*! - * @brief eLCDIF alpha mode during blending. - */ -typedef enum _elcdif_alpha_mode -{ - kELCDIF_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */ - kELCDIF_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */ - kELCDIF_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined - alpha value will be used for blend, for example, pixel alpha set - set to 200, user defined alpha set to 100, then the reault alpha - is 200 * 100 / 255. */ - kELCDIF_AlphaRop /*!< Raster operation. */ -} elcdif_alpha_mode_t; - -/*! - * @brief eLCDIF ROP mode during blending. - * - * Explanation: - * - AS: Alpha surface - * - PS: Process surface - * - nAS: Alpha surface NOT value - * - nPS: Process surface NOT value - */ -typedef enum _elcdif_rop_mode -{ - kELCDIF_RopMaskAs = 0x0, /*!< AS AND PS. */ - kELCDIF_RopMaskNotAs = 0x1, /*!< nAS AND PS. */ - kELCDIF_RopMaskAsNot = 0x2, /*!< AS AND nPS. */ - kELCDIF_RopMergeAs = 0x3, /*!< AS OR PS. */ - kELCDIF_RopMergeNotAs = 0x4, /*!< nAS OR PS. */ - kELCDIF_RopMergeAsNot = 0x5, /*!< AS OR nPS. */ - kELCDIF_RopNotCopyAs = 0x6, /*!< nAS. */ - kELCDIF_RopNot = 0x7, /*!< nPS. */ - kELCDIF_RopNotMaskAs = 0x8, /*!< AS NAND PS. */ - kELCDIF_RopNotMergeAs = 0x9, /*!< AS NOR PS. */ - kELCDIF_RopXorAs = 0xA, /*!< AS XOR PS. */ - kELCDIF_RopNotXorAs = 0xB /*!< AS XNOR PS. */ -} elcdif_rop_mode_t; - -/*! - * @brief eLCDIF alpha surface blending configuration. - */ -typedef struct _elcdif_as_blend_config -{ - uint8_t alpha; /*!< User defined alpha value, only used when @ref alphaMode is @ref kELCDIF_AlphaOverride or @ref - kELCDIF_AlphaRop. */ - bool invertAlpha; /*!< Set true to invert the alpha. */ - elcdif_alpha_mode_t alphaMode; /*!< Alpha mode. */ - elcdif_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kELCDIF_AlphaRop. */ -} elcdif_as_blend_config_t; - -/*! - * @brief eLCDIF LUT - * - * The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits pixel - * before output to external displayer. - * - * There are two 256x24 bits LUT memory in LCDIF, the LSB of frame buffer address - * determins which memory to use. - */ -typedef enum _elcdif_lut -{ - kELCDIF_Lut0 = 0, /*!< LUT 0. */ - kELCDIF_Lut1, /*!< LUT 1. */ -} elcdif_lut_t; - -/******************************************************************************* - * APIs - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name eLCDIF initialization and de-initialization - * @{ - */ - -/*! - * @brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode). - * - * This function ungates the eLCDIF clock and configures the eLCDIF peripheral according - * to the configuration structure. - * - * @param base eLCDIF peripheral base address. - * @param config Pointer to the configuration structure. - */ -void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config); - -/*! - * @brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode. - * - * This function sets the configuration structure to default values. - * The default configuration is set to the following values. - * @code - config->panelWidth = 480U; - config->panelHeight = 272U; - config->hsw = 41; - config->hfp = 4; - config->hbp = 8; - config->vsw = 10; - config->vfp = 4; - config->vbp = 2; - config->polarityFlags = kELCDIF_VsyncActiveLow | - kELCDIF_HsyncActiveLow | - kELCDIF_DataEnableActiveLow | - kELCDIF_DriveDataOnFallingClkEdge; - config->bufferAddr = 0U; - config->pixelFormat = kELCDIF_PixelFormatRGB888; - config->dataBus = kELCDIF_DataBus24Bit; - @code - * - * @param config Pointer to the eLCDIF configuration structure. - */ -void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config); - -/*! - * @brief Deinitializes the eLCDIF peripheral. - * - * @param base eLCDIF peripheral base address. - */ -void ELCDIF_Deinit(LCDIF_Type *base); - -/* @} */ - -/*! - * @name Module operation - * @{ - */ - -/*! - * @brief Start to display in RGB (DOTCLK) mode. - * - * @param base eLCDIF peripheral base address. - */ -static inline void ELCDIF_RgbModeStart(LCDIF_Type *base) -{ - base->CTRL_SET = LCDIF_CTRL_RUN_MASK | LCDIF_CTRL_DOTCLK_MODE_MASK; -} - -/*! - * @brief Stop display in RGB (DOTCLK) mode and wait until finished. - * - * @param base eLCDIF peripheral base address. - */ -void ELCDIF_RgbModeStop(LCDIF_Type *base); - -/*! - * @brief Set the next frame buffer address to display. - * - * @param base eLCDIF peripheral base address. - * @param bufferAddr The frame buffer address to set. - */ -static inline void ELCDIF_SetNextBufferAddr(LCDIF_Type *base, uint32_t bufferAddr) -{ - base->NEXT_BUF = bufferAddr; -} - -/*! - * @brief Reset the eLCDIF peripheral. - * - * @param base eLCDIF peripheral base address. - */ -void ELCDIF_Reset(LCDIF_Type *base); - -#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN) && FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN) -/*! - * @brief Pull up or down the reset pin for the externel LCD controller. - * - * @param base eLCDIF peripheral base address. - * @param pullUp True to pull up reset pin, false to pull down. - */ -static inline void ELCDIF_PullUpResetPin(LCDIF_Type *base, bool pullUp) -{ - if (pullUp) - { - base->CTRL1_SET = LCDIF_CTRL1_RESET_MASK; - } - else - { - base->CTRL1_CLR = LCDIF_CTRL1_RESET_MASK; - } -} -#endif - -/*! - * @brief Enable or disable the hand shake with PXP. - * - * @param base eLCDIF peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void ELCDIF_EnablePxpHandShake(LCDIF_Type *base, bool enable) -{ - if (enable) - { - base->CTRL_SET = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK; - } - else - { - base->CTRL_CLR = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK; - } -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get the CRC value of the frame sent out. - * - * When a frame is sent complete (the interrupt @ref kELCDIF_CurFrameDone assert), this function - * can be used to get the CRC value of the frame sent. - * - * @param base eLCDIF peripheral base address. - * @return The CRC value. - * - * @note The CRC value is dependent on the LCD_DATABUS_WIDTH. - */ -static inline uint32_t ELCDIF_GetCrcValue(LCDIF_Type *base) -{ - return base->CRC_STAT; -} - -/*! - * @brief Get the bus master error virtual address. - * - * When bus master error occurs (the interrupt kELCDIF_BusMasterError assert), this function - * can get the virtual address at which the AXI master received an error - * response from the slave. - * - * @param base eLCDIF peripheral base address. - * @return The error virtual address. - */ -static inline uint32_t ELCDIF_GetBusMasterErrorAddr(LCDIF_Type *base) -{ - return base->BM_ERROR_STAT; -} - -/*! - * @brief Get the eLCDIF status. - * - * The status flags are returned as a mask value, application could check the - * corresponding bit. Example: - * - * @code - uint32_t statusFlags; - statusFlags = ELCDIF_GetStatus(LCDIF); - - // If LFIFO is full. - if (kELCDIF_LFifoFull & statusFlags) - { - // ...; - } - // If TXFIFO is empty. - if (kELCDIF_TxFifoEmpty & statusFlags) - { - // ...; - } - @endcode - * - * @param base eLCDIF peripheral base address. - * @return The mask value of status flags, it is OR'ed value of @ref _elcdif_status_flags. - */ -static inline uint32_t ELCDIF_GetStatus(LCDIF_Type *base) -{ - return base->STAT & (LCDIF_STAT_LFIFO_FULL_MASK | LCDIF_STAT_LFIFO_EMPTY_MASK | LCDIF_STAT_TXFIFO_FULL_MASK | - LCDIF_STAT_TXFIFO_EMPTY_MASK -#if defined(LCDIF_STAT_BUSY_MASK) - | LCDIF_STAT_BUSY_MASK -#endif -#if defined(LCDIF_STAT_DVI_CURRENT_FIELD_MASK) - | LCDIF_STAT_DVI_CURRENT_FIELD_MASK -#endif - ); -} - -/*! - * @brief Get current count in Latency buffer (LFIFO). - * - * @param base eLCDIF peripheral base address. - * @return The LFIFO current count - */ -static inline uint32_t ELCDIF_GetLFifoCount(LCDIF_Type *base) -{ - return (base->STAT & LCDIF_STAT_LFIFO_COUNT_MASK) >> LCDIF_STAT_LFIFO_COUNT_SHIFT; -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables eLCDIF interrupt requests. - * - * @param base eLCDIF peripheral base address. - * @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable. - */ -static inline void ELCDIF_EnableInterrupts(LCDIF_Type *base, uint32_t mask) -{ - base->CTRL1_SET = (mask & ELCDIF_CTRL1_IRQ_EN_MASK); -#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS) - base->AS_CTRL |= (mask & ELCDIF_AS_CTRL_IRQ_EN_MASK); -#endif -} - -/*! - * @brief Disables eLCDIF interrupt requests. - * - * @param base eLCDIF peripheral base address. - * @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable. - */ -static inline void ELCDIF_DisableInterrupts(LCDIF_Type *base, uint32_t mask) -{ - base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_EN_MASK); -#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS) - base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_EN_MASK); -#endif -} - -/*! - * @brief Get eLCDIF interrupt peding status. - * - * @param base eLCDIF peripheral base address. - * @return Interrupt pending status, OR'ed value of _elcdif_interrupt_flags. - */ -static inline uint32_t ELCDIF_GetInterruptStatus(LCDIF_Type *base) -{ - uint32_t flags; - - flags = (base->CTRL1 & ELCDIF_CTRL1_IRQ_MASK); -#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS) - flags |= (base->AS_CTRL & ELCDIF_AS_CTRL_IRQ_MASK); -#endif - - return flags; -} - -/*! - * @brief Clear eLCDIF interrupt peding status. - * - * @param base eLCDIF peripheral base address. - * @param mask of the flags to clear, OR'ed value of _elcdif_interrupt_flags. - */ -static inline void ELCDIF_ClearInterruptStatus(LCDIF_Type *base, uint32_t mask) -{ - base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_MASK); -#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS) - base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_MASK); -#endif -} - -/* @} */ - -#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS) -/*! - * @name Alpha surface - * @{ - */ - -/*! - * @brief Set the configuration for alpha surface buffer. - * - * @param base eLCDIF peripheral base address. - * @param config Pointer to the configuration structure. - */ -void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config); - -/*! - * @brief Set the alpha surface blending configuration. - * - * @param base eLCDIF peripheral base address. - * @param config Pointer to the configuration structure. - */ -void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config); - -/*! - * @brief Set the next alpha surface buffer address. - * - * @param base eLCDIF peripheral base address. - * @param bufferAddr Alpha surface buffer address. - */ -static inline void ELCDIF_SetNextAlphaSurfaceBufferAddr(LCDIF_Type *base, uint32_t bufferAddr) -{ - base->AS_NEXT_BUF = bufferAddr; -} - -/*! - * @brief Set the overlay color key. - * - * If a pixel in the current overlay image with a color that falls in the range - * from the @p colorKeyLow to @p colorKeyHigh range, it will use the process surface - * pixel value for that location. - * - * @param base eLCDIF peripheral base address. - * @param colorKeyLow Color key low range. - * @param colorKeyHigh Color key high range. - * - * @note Colorkey operations are higher priority than alpha or ROP operations - */ -static inline void ELCDIF_SetOverlayColorKey(LCDIF_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh) -{ - base->AS_CLRKEYLOW = colorKeyLow; - base->AS_CLRKEYHIGH = colorKeyHigh; -} - -/*! - * @brief Enable or disable the color key. - * - * @param base eLCDIF peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void ELCDIF_EnableOverlayColorKey(LCDIF_Type *base, bool enable) -{ - if (enable) - { - base->AS_CTRL |= LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK; - } - else - { - base->AS_CTRL &= ~LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK; - } -} - -/*! - * @brief Enable or disable the alpha surface. - * - * @param base eLCDIF peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void ELCDIF_EnableAlphaSurface(LCDIF_Type *base, bool enable) -{ - if (enable) - { - base->AS_CTRL |= LCDIF_AS_CTRL_AS_ENABLE_MASK; - } - else - { - base->AS_CTRL &= ~LCDIF_AS_CTRL_AS_ENABLE_MASK; - } -} - -/*! - * @brief Enable or disable the process surface. - * - * Process surface is the normal frame buffer. The process surface content - * is controlled by @ref ELCDIF_SetNextBufferAddr. - * - * @param base eLCDIF peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void ELCDIF_EnableProcessSurface(LCDIF_Type *base, bool enable) -{ - if (enable) - { - base->AS_CTRL &= ~LCDIF_AS_CTRL_PS_DISABLE_MASK; - } - else - { - base->AS_CTRL |= LCDIF_AS_CTRL_PS_DISABLE_MASK; - } -} - -/* @} */ -#endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */ - -#if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT) -/*! - * @name LUT - * - * The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits pixel - * before output to external displayer. - * - * There are two 256x24 bits LUT memory in LCDIF, the LSB of frame buffer address - * determins which memory to use. - * - * @{ - */ - -/*! - * @brief Enable or disable the LUT. - * - * @param base eLCDIF peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void ELCDIF_EnableLut(LCDIF_Type *base, bool enable) -{ - if (enable) - { - base->LUT_CTRL &= ~LCDIF_LUT_CTRL_LUT_BYPASS_MASK; - } - else - { - base->LUT_CTRL |= LCDIF_LUT_CTRL_LUT_BYPASS_MASK; - } -} - -/*! - * @brief Load the LUT value. - * - * This function loads the LUT value to the specific LUT memory, user can - * specify the start entry index. - * - * @param base eLCDIF peripheral base address. - * @param lut Which LUT to load. - * @param startIndex The start index of the LUT entry to update. - * @param lutData The LUT data to load. - * @param count Count of @p lutData. - * @retval kStatus_Success Initialization success. - * @retval kStatus_InvalidArgument Wrong argument. - */ -status_t ELCDIF_UpdateLut( - LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count); - -/* @} */ -#endif /* FSL_FEATURE_LCDIF_HAS_LUT */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/* @} */ - -#endif /*_FSL_ELCDIF_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_enc.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_enc.c deleted file mode 100644 index 76db836d06..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_enc.c +++ /dev/null @@ -1,489 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_enc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.enc" -#endif - -#define ENC_CTRL_W1C_FLAGS (ENC_CTRL_HIRQ_MASK | ENC_CTRL_XIRQ_MASK | ENC_CTRL_DIRQ_MASK | ENC_CTRL_CMPIRQ_MASK) -#define ENC_CTRL2_W1C_FLAGS (ENC_CTRL2_SABIRQ_MASK | ENC_CTRL2_ROIRQ_MASK | ENC_CTRL2_RUIRQ_MASK) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for ENC module. - * - * @param base ENC peripheral base address - */ -static uint32_t ENC_GetInstance(ENC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to ENC bases for each instance. */ -static ENC_Type *const s_encBases[] = ENC_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to ENC clocks for each instance. */ -static const clock_ip_name_t s_encClocks[] = ENC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t ENC_GetInstance(ENC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_encBases); instance++) - { - if (s_encBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_encBases)); - - return instance; -} - -void ENC_Init(ENC_Type *base, const enc_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp16; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(s_encClocks[ENC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* ENC_CTRL. */ - tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_HIP_MASK | ENC_CTRL_HNE_MASK | ENC_CTRL_REV_MASK | - ENC_CTRL_PH1_MASK | ENC_CTRL_XIP_MASK | ENC_CTRL_XNE_MASK | ENC_CTRL_WDE_MASK)); - /* For HOME trigger. */ - if (kENC_HOMETriggerDisabled != config->HOMETriggerMode) - { - tmp16 |= ENC_CTRL_HIP_MASK; - if (kENC_HOMETriggerOnFallingEdge == config->HOMETriggerMode) - { - tmp16 |= ENC_CTRL_HNE_MASK; - } - } - /* For encoder work mode. */ - if (config->enableReverseDirection) - { - tmp16 |= ENC_CTRL_REV_MASK; - } - if (kENC_DecoderWorkAsSignalPhaseCountMode == config->decoderWorkMode) - { - tmp16 |= ENC_CTRL_PH1_MASK; - } - /* For INDEX trigger. */ - if (kENC_INDEXTriggerDisabled != config->INDEXTriggerMode) - { - tmp16 |= ENC_CTRL_XIP_MASK; - if (kENC_INDEXTriggerOnFallingEdge == config->INDEXTriggerMode) - { - tmp16 |= ENC_CTRL_XNE_MASK; - } - } - /* Watchdog. */ - if (config->enableWatchdog) - { - tmp16 |= ENC_CTRL_WDE_MASK; - base->WTR = config->watchdogTimeoutValue; /* WDOG can be only available when the feature is enabled. */ - } - base->CTRL = tmp16; - - /* ENC_FILT. */ - base->FILT = ENC_FILT_FILT_CNT(config->filterCount) | ENC_FILT_FILT_PER(config->filterSamplePeriod); - - /* ENC_CTRL2. */ - tmp16 = base->CTRL2 & (uint16_t)(~(ENC_CTRL2_W1C_FLAGS | ENC_CTRL2_OUTCTL_MASK | ENC_CTRL2_REVMOD_MASK | - ENC_CTRL2_MOD_MASK | ENC_CTRL2_UPDPOS_MASK | ENC_CTRL2_UPDHLD_MASK)); - if (kENC_POSMATCHOnReadingAnyPositionCounter == config->positionMatchMode) - { - tmp16 |= ENC_CTRL2_OUTCTL_MASK; - } - if (kENC_RevolutionCountOnRollOverModulus == config->revolutionCountCondition) - { - tmp16 |= ENC_CTRL2_REVMOD_MASK; - } - if (config->enableModuloCountMode) - { - tmp16 |= ENC_CTRL2_MOD_MASK; - /* Set modulus value. */ - base->UMOD = (uint16_t)(config->positionModulusValue >> 16U); /* Upper 16 bits. */ - base->LMOD = (uint16_t)(config->positionModulusValue); /* Lower 16 bits. */ - } - if (config->enableTRIGGERClearPositionCounter) - { - tmp16 |= ENC_CTRL2_UPDPOS_MASK; - } - if (config->enableTRIGGERClearHoldPositionCounter) - { - tmp16 |= ENC_CTRL2_UPDHLD_MASK; - } - base->CTRL2 = tmp16; - - /* ENC_UCOMP & ENC_LCOMP. */ - base->UCOMP = (uint16_t)(config->positionCompareValue >> 16U); /* Upper 16 bits. */ - base->LCOMP = (uint16_t)(config->positionCompareValue); /* Lower 16 bits. */ - - /* ENC_UINIT & ENC_LINIT. */ - base->UINIT = (uint16_t)(config->positionInitialValue >> 16U); /* Upper 16 bits. */ - base->LINIT = (uint16_t)(config->positionInitialValue); /* Lower 16 bits. */ -} - -void ENC_Deinit(ENC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(s_encClocks[ENC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void ENC_GetDefaultConfig(enc_config_t *config) -{ - assert(NULL != config); - - config->enableReverseDirection = false; - config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; - config->HOMETriggerMode = kENC_HOMETriggerDisabled; - config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; - config->enableTRIGGERClearPositionCounter = false; - config->enableTRIGGERClearHoldPositionCounter = false; - config->enableWatchdog = false; - config->watchdogTimeoutValue = 0U; - config->filterCount = 0U; - config->filterSamplePeriod = 0U; - config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; - config->positionCompareValue = 0xFFFFFFFFU; - config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; - config->enableModuloCountMode = false; - config->positionModulusValue = 0U; - config->positionInitialValue = 0U; -} - -void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base) -{ - uint16_t tmp16 = base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS); - - tmp16 |= ENC_CTRL_SWIP_MASK; /* Write 1 to trigger the command for loading initial position value. */ - base->CTRL = tmp16; -} - -void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config) -{ - uint16_t tmp16 = 0U; - - if (NULL == config) /* Pass "NULL" to disable the feature. */ - { - base->TST = 0U; - return; - } - tmp16 = ENC_TST_TEN_MASK | ENC_TST_TCE_MASK | ENC_TST_TEST_PERIOD(config->signalPeriod) | - ENC_TST_TEST_COUNT(config->signalCount); - if (kENC_SelfTestDirectionNegative == config->signalDirection) - { - tmp16 |= ENC_TST_QDN_MASK; - } - base->TST = tmp16; -} - -void ENC_EnableWatchdog(ENC_Type *base, bool enable) -{ - uint16_t tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_WDE_MASK)); - - if (enable) - { - tmp16 |= ENC_CTRL_WDE_MASK; - } - base->CTRL = tmp16; -} - -uint32_t ENC_GetStatusFlags(ENC_Type *base) -{ - uint32_t ret32 = 0U; - - /* ENC_CTRL. */ - if (ENC_CTRL_HIRQ_MASK == (ENC_CTRL_HIRQ_MASK & base->CTRL)) - { - ret32 |= kENC_HOMETransitionFlag; - } - if (ENC_CTRL_XIRQ_MASK == (ENC_CTRL_XIRQ_MASK & base->CTRL)) - { - ret32 |= kENC_INDEXPulseFlag; - } - if (ENC_CTRL_DIRQ_MASK == (ENC_CTRL_DIRQ_MASK & base->CTRL)) - { - ret32 |= kENC_WatchdogTimeoutFlag; - } - if (ENC_CTRL_CMPIRQ_MASK == (ENC_CTRL_CMPIRQ_MASK & base->CTRL)) - { - ret32 |= kENC_PositionCompareFlag; - } - - /* ENC_CTRL2. */ - if (ENC_CTRL2_SABIRQ_MASK == (ENC_CTRL2_SABIRQ_MASK & base->CTRL2)) - { - ret32 |= kENC_SimultBothPhaseChangeFlag; - } - if (ENC_CTRL2_ROIRQ_MASK == (ENC_CTRL2_ROIRQ_MASK & base->CTRL2)) - { - ret32 |= kENC_PositionRollOverFlag; - } - if (ENC_CTRL2_RUIRQ_MASK == (ENC_CTRL2_RUIRQ_MASK & base->CTRL2)) - { - ret32 |= kENC_PositionRollUnderFlag; - } - if (ENC_CTRL2_DIR_MASK == (ENC_CTRL2_DIR_MASK & base->CTRL2)) - { - ret32 |= kENC_LastCountDirectionFlag; - } - - return ret32; -} - -void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask) -{ - uint32_t tmp16 = 0U; - - /* ENC_CTRL. */ - if (kENC_HOMETransitionFlag == (kENC_HOMETransitionFlag & mask)) - { - tmp16 |= ENC_CTRL_HIRQ_MASK; - } - if (kENC_INDEXPulseFlag == (kENC_INDEXPulseFlag & mask)) - { - tmp16 |= ENC_CTRL_XIRQ_MASK; - } - if (kENC_WatchdogTimeoutFlag == (kENC_WatchdogTimeoutFlag & mask)) - { - tmp16 |= ENC_CTRL_DIRQ_MASK; - } - if (kENC_PositionCompareFlag == (kENC_PositionCompareFlag & mask)) - { - tmp16 |= ENC_CTRL_CMPIRQ_MASK; - } - if (0U != tmp16) - { - base->CTRL = (base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS)) | tmp16; - } - - /* ENC_CTRL2. */ - tmp16 = 0U; - if (kENC_SimultBothPhaseChangeFlag == (kENC_SimultBothPhaseChangeFlag & mask)) - { - tmp16 |= ENC_CTRL2_SABIRQ_MASK; - } - if (kENC_PositionRollOverFlag == (kENC_PositionRollOverFlag & mask)) - { - tmp16 |= ENC_CTRL2_ROIRQ_MASK; - } - if (kENC_PositionRollUnderFlag == (kENC_PositionRollUnderFlag & mask)) - { - tmp16 |= ENC_CTRL2_RUIRQ_MASK; - } - if (0U != tmp16) - { - base->CTRL2 = (base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) | tmp16; - } -} - -void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask) -{ - uint32_t tmp16 = 0U; - - /* ENC_CTRL. */ - if (kENC_HOMETransitionInterruptEnable == (kENC_HOMETransitionInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_HIE_MASK; - } - if (kENC_INDEXPulseInterruptEnable == (kENC_INDEXPulseInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_XIE_MASK; - } - if (kENC_WatchdogTimeoutInterruptEnable == (kENC_WatchdogTimeoutInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_DIE_MASK; - } - if (kENC_PositionCompareInerruptEnable == (kENC_PositionCompareInerruptEnable & mask)) - { - tmp16 |= ENC_CTRL_CMPIE_MASK; - } - if (tmp16 != 0U) - { - base->CTRL = (base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS)) | tmp16; - } - /* ENC_CTRL2. */ - tmp16 = 0U; - if (kENC_SimultBothPhaseChangeInterruptEnable == (kENC_SimultBothPhaseChangeInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_SABIE_MASK; - } - if (kENC_PositionRollOverInterruptEnable == (kENC_PositionRollOverInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_ROIE_MASK; - } - if (kENC_PositionRollUnderInterruptEnable == (kENC_PositionRollUnderInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_RUIE_MASK; - } - if (tmp16 != 0U) - { - base->CTRL2 = (base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) | tmp16; - } -} - -void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask) -{ - uint16_t tmp16 = 0U; - - /* ENC_CTRL. */ - if (kENC_HOMETransitionInterruptEnable == (kENC_HOMETransitionInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_HIE_MASK; - } - if (kENC_INDEXPulseInterruptEnable == (kENC_INDEXPulseInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_XIE_MASK; - } - if (kENC_WatchdogTimeoutInterruptEnable == (kENC_WatchdogTimeoutInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL_DIE_MASK; - } - if (kENC_PositionCompareInerruptEnable == (kENC_PositionCompareInerruptEnable & mask)) - { - tmp16 |= ENC_CTRL_CMPIE_MASK; - } - if (0U != tmp16) - { - base->CTRL = (uint16_t)(base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS)) & (uint16_t)(~tmp16); - } - /* ENC_CTRL2. */ - tmp16 = 0U; - if (kENC_SimultBothPhaseChangeInterruptEnable == (kENC_SimultBothPhaseChangeInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_SABIE_MASK; - } - if (kENC_PositionRollOverInterruptEnable == (kENC_PositionRollOverInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_ROIE_MASK; - } - if (kENC_PositionRollUnderInterruptEnable == (kENC_PositionRollUnderInterruptEnable & mask)) - { - tmp16 |= ENC_CTRL2_RUIE_MASK; - } - if (tmp16 != 0U) - { - base->CTRL2 = (uint16_t)(base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) & (uint16_t)(~tmp16); - } -} - -uint32_t ENC_GetEnabledInterrupts(ENC_Type *base) -{ - uint32_t ret32 = 0U; - - /* ENC_CTRL. */ - if (ENC_CTRL_HIE_MASK == (ENC_CTRL_HIE_MASK & base->CTRL)) - { - ret32 |= kENC_HOMETransitionInterruptEnable; - } - if (ENC_CTRL_XIE_MASK == (ENC_CTRL_XIE_MASK & base->CTRL)) - { - ret32 |= kENC_INDEXPulseInterruptEnable; - } - if (ENC_CTRL_DIE_MASK == (ENC_CTRL_DIE_MASK & base->CTRL)) - { - ret32 |= kENC_WatchdogTimeoutInterruptEnable; - } - if (ENC_CTRL_CMPIE_MASK == (ENC_CTRL_CMPIE_MASK & base->CTRL)) - { - ret32 |= kENC_PositionCompareInerruptEnable; - } - /* ENC_CTRL2. */ - if (ENC_CTRL2_SABIE_MASK == (ENC_CTRL2_SABIE_MASK & base->CTRL2)) - { - ret32 |= kENC_SimultBothPhaseChangeInterruptEnable; - } - if (ENC_CTRL2_ROIE_MASK == (ENC_CTRL2_ROIE_MASK & base->CTRL2)) - { - ret32 |= kENC_PositionRollOverInterruptEnable; - } - if (ENC_CTRL2_RUIE_MASK == (ENC_CTRL2_RUIE_MASK & base->CTRL2)) - { - ret32 |= kENC_PositionRollUnderInterruptEnable; - } - return ret32; -} - -void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value) -{ - base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */ - base->LINIT = (uint16_t)(value); /* Set lower 16 bits. */ -} - -uint32_t ENC_GetPositionValue(ENC_Type *base) -{ - uint32_t ret32; - - ret32 = base->UPOS; /* Get upper 16 bits and make a snapshot. */ - ret32 <<= 16U; - ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ - - return ret32; -} - -uint32_t ENC_GetHoldPositionValue(ENC_Type *base) -{ - uint32_t ret32; - - ret32 = base->UPOSH; /* Get upper 16 bits and make a snapshot. */ - ret32 <<= 16U; - ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ - - return ret32; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_enc.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_enc.h deleted file mode 100644 index 64c4f402da..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_enc.h +++ /dev/null @@ -1,484 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_ENC_H_ -#define _FSL_ENC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup enc - * @{ - */ -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define FSL_ENC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - -/*! - * @brief Interrupt enable/disable mask. - */ -enum _enc_interrupt_enable -{ - kENC_HOMETransitionInterruptEnable = (1U << 0U), /*!< HOME interrupt enable. */ - kENC_INDEXPulseInterruptEnable = (1U << 1U), /*!< INDEX pulse interrupt enable. */ - kENC_WatchdogTimeoutInterruptEnable = (1U << 2U), /*!< Watchdog timeout interrupt enable. */ - kENC_PositionCompareInerruptEnable = (1U << 3U), /*!< Position compare interrupt enable. */ - kENC_SimultBothPhaseChangeInterruptEnable = - (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt enable. */ - kENC_PositionRollOverInterruptEnable = (1U << 5U), /*!< Roll-over interrupt enable. */ - kENC_PositionRollUnderInterruptEnable = (1U << 6U), /*!< Roll-under interrupt enable. */ -}; - -/*! - * @brief Status flag mask. - * - * These flags indicate the counter's events. - */ -enum _enc_status_flags -{ - kENC_HOMETransitionFlag = (1U << 0U), /*!< HOME signal transition interrupt request. */ - kENC_INDEXPulseFlag = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */ - kENC_WatchdogTimeoutFlag = (1U << 2U), /*!< Watchdog timeout interrupt request. */ - kENC_PositionCompareFlag = (1U << 3U), /*!< Position compare interrupt request. */ - kENC_SimultBothPhaseChangeFlag = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt request. */ - kENC_PositionRollOverFlag = (1U << 5U), /*!< Roll-over interrupt request. */ - kENC_PositionRollUnderFlag = (1U << 6U), /*!< Roll-under interrupt request. */ - kENC_LastCountDirectionFlag = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */ -}; - -/*! - * @brief Signal status flag mask. - * - * These flags indicate the counter's signal. - */ -enum _enc_signal_status_flags -{ - kENC_RawHOMEStatusFlag = ENC_IMR_HOME_MASK, /*!< Raw HOME input. */ - kENC_RawINDEXStatusFlag = ENC_IMR_INDEX_MASK, /*!< Raw INDEX input. */ - kENC_RawPHBStatusFlag = ENC_IMR_PHB_MASK, /*!< Raw PHASEB input. */ - kENC_RawPHAEXStatusFlag = ENC_IMR_PHA_MASK, /*!< Raw PHASEA input. */ - kENC_FilteredHOMEStatusFlag = ENC_IMR_FHOM_MASK, /*!< The filtered version of HOME input. */ - kENC_FilteredINDEXStatusFlag = ENC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */ - kENC_FilteredPHBStatusFlag = ENC_IMR_FPHB_MASK, /*!< The filtered version of PHASEB input. */ - kENC_FilteredPHAStatusFlag = ENC_IMR_FPHA_MASK, /*!< The filtered version of PHASEA input. */ -}; - -/*! - * @brief Define HOME signal's trigger mode. - * - * The ENC would count the trigger from HOME signal line. - */ -typedef enum _enc_home_trigger_mode -{ - kENC_HOMETriggerDisabled = 0U, /*!< HOME signal's trigger is disabled. */ - kENC_HOMETriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ - kENC_HOMETriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ -} enc_home_trigger_mode_t; - -/*! - * @brief Define INDEX signal's trigger mode. - * - * The ENC would count the trigger from INDEX signal line. - */ -typedef enum _enc_index_trigger_mode -{ - kENC_INDEXTriggerDisabled = 0U, /*!< INDEX signal's trigger is disabled. */ - kENC_INDEXTriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ - kENC_INDEXTriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ -} enc_index_trigger_mode_t; - -/*! - * @brief Define type for decoder work mode. - * - * The normal work mode uses the standard quadrature decoder with PHASEA and PHASEB. When in signal phase count mode, - * a positive transition of the PHASEA input generates a count signal while the PHASEB input and the reverse direction - * control the counter direction. If the reverse direction is not enabled, PHASEB = 0 means counting up and PHASEB = 1 - * means counting down. Otherwise, the direction is reversed. - */ -typedef enum _enc_decoder_work_mode -{ - kENC_DecoderWorkAsNormalMode = 0U, /*!< Use standard quadrature decoder with PHASEA and PHASEB. */ - kENC_DecoderWorkAsSignalPhaseCountMode, /*!< PHASEA input generates a count signal while PHASEB input control the - direction. */ -} enc_decoder_work_mode_t; - -/*! - * @brief Define type for the condition of POSMATCH pulses. - */ -typedef enum _enc_position_match_mode -{ - kENC_POSMATCHOnPositionCounterEqualToComapreValue = 0U, /*!< POSMATCH pulses when a match occurs between the - position counters (POS) and the compare value (COMP). */ - kENC_POSMATCHOnReadingAnyPositionCounter, /*!< POSMATCH pulses when any position counter register is read. */ -} enc_position_match_mode_t; - -/*! - * @brief Define type for determining how the revolution counter (REV) is incremented/decremented. - */ -typedef enum _enc_revolution_count_condition -{ - kENC_RevolutionCountOnINDEXPulse = 0U, /*!< Use INDEX pulse to increment/decrement revolution counter. */ - kENC_RevolutionCountOnRollOverModulus, /*!< Use modulus counting roll-over/under to increment/decrement revolution - counter. */ -} enc_revolution_count_condition_t; - -/*! - * @brief Define type for direction of self test generated signal. - */ -typedef enum _enc_self_test_direction -{ - kENC_SelfTestDirectionPositive = 0U, /*!< Self test generates the signal in positive direction. */ - kENC_SelfTestDirectionNegative, /*!< Self test generates the signal in negative direction. */ -} enc_self_test_direction_t; - -/*! - * @brief Define user configuration structure for ENC module. - */ -typedef struct _enc_config -{ - /* Basic counter. */ - bool enableReverseDirection; /*!< Enable reverse direction counting. */ - enc_decoder_work_mode_t decoderWorkMode; /*!< Enable signal phase count mode. */ - - /* Signal detection. */ - enc_home_trigger_mode_t HOMETriggerMode; /*!< Enable HOME to initialize position counters. */ - enc_index_trigger_mode_t INDEXTriggerMode; /*!< Enable INDEX to initialize position counters. */ - bool enableTRIGGERClearPositionCounter; /*!< Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER, or not. */ - bool enableTRIGGERClearHoldPositionCounter; /*!< Enable update of hold registers on rising edge of TRIGGER, or not. - */ - - /* Watchdog. */ - bool enableWatchdog; /*!< Enable the watchdog to detect if the target is moving or not. */ - uint16_t watchdogTimeoutValue; /*!< Watchdog timeout count value. It stores the timeout count for the quadrature - decoder module watchdog timer. This field is only available when - "enableWatchdog" = true. The available value is a 16-bit unsigned number.*/ - - /* Filter for PHASEA, PHASEB, INDEX and HOME. */ - uint16_t filterCount; /*!< Input Filter Sample Count. This value should be chosen to reduce the probability of - noisy samples causing an incorrect transition to be recognized. The value represent the - number of consecutive samples that must agree prior to the input filter accepting an - input transition. A value of 0x0 represents 3 samples. A value of 0x7 represents 10 - samples. The Available range is 0 - 7.*/ - uint16_t filterSamplePeriod; /*!< Input Filter Sample Period. This value should be set such that the sampling period - is larger than the period of the expected noise. This value represents the - sampling period (in IPBus clock cycles) of the decoder input signals. - The available range is 0 - 255. */ - - /* Position compare. */ - enc_position_match_mode_t positionMatchMode; /*!< The condition of POSMATCH pulses. */ - uint32_t positionCompareValue; /*!< Position compare value. The available value is a 32-bit number.*/ - - /* Modulus counting. */ - enc_revolution_count_condition_t revolutionCountCondition; /*!< Revolution Counter Modulus Enable. */ - bool enableModuloCountMode; /*!< Enable Modulo Counting. */ - uint32_t positionModulusValue; /*!< Position modulus value. This value would be available only when - "enableModuloCountMode" = true. The available value is a 32-bit number. */ - uint32_t positionInitialValue; /*!< Position initial value. The available value is a 32-bit number. */ -} enc_config_t; - -/*! - * @brief Define configuration structure for self test module. - * - * The self test module provides a quadrature test signal to the inputs of the quadrature decoder module. - * This is a factory test feature. It is also useful to customers' software development and testing. - */ -typedef struct _enc_self_test_config -{ - enc_self_test_direction_t signalDirection; /*!< Direction of self test generated signal. */ - uint16_t signalCount; /*!< Hold the number of quadrature advances to generate. The available range is 0 - 255.*/ - uint16_t signalPeriod; /*!< Hold the period of quadrature phase in IPBus clock cycles. - The available range is 0 - 31. */ -} enc_self_test_config_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @name Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initialization for the ENC module. - * - * This function is to make the initialization for the ENC module. It should be called firstly before any operation to - * the ENC with the operations like: - * - Enable the clock for ENC module. - * - Configure the ENC's working attributes. - * - * @param base ENC peripheral base address. - * @param config Pointer to configuration structure. See to "enc_config_t". - */ -void ENC_Init(ENC_Type *base, const enc_config_t *config); - -/*! - * @brief De-initialization for the ENC module. - * - * This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with - * the operations like: - * - Disable the clock for ENC module. - * - * @param base ENC peripheral base address. - */ -void ENC_Deinit(ENC_Type *base); - -/*! - * @brief Get an available pre-defined settings for ENC's configuration. - * - * This function initializes the ENC configuration structure with an available settings, the default value are: - * @code - * config->enableReverseDirection = false; - * config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; - * config->HOMETriggerMode = kENC_HOMETriggerDisabled; - * config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; - * config->enableTRIGGERClearPositionCounter = false; - * config->enableTRIGGERClearHoldPositionCounter = false; - * config->enableWatchdog = false; - * config->watchdogTimeoutValue = 0U; - * config->filterCount = 0U; - * config->filterSamplePeriod = 0U; - * config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; - * config->positionCompareValue = 0xFFFFFFFFU; - * config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; - * config->enableModuloCountMode = false; - * config->positionModulusValue = 0U; - * config->positionInitialValue = 0U; - * @endcode - * @param config Pointer to a variable of configuration structure. See to "enc_config_t". - */ -void ENC_GetDefaultConfig(enc_config_t *config); - -/*! - * @brief Load the initial position value to position counter. - * - * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and - * LPOS), so that to provide the consistent operation the position counter registers. - * - * @param base ENC peripheral base address. - */ -void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base); - -/*! - * @brief Enable and configure the self test function. - * - * This function is to enable and configuration the self test function. It controls and sets the frequency of a - * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. - * It is a factory test feature; however, it may be useful to customers' software development and testing. - * - * @param base ENC peripheral base address. - * @param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable. - */ -void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config); - -/*! - * @brief Enable watchdog for ENC module. - * - * @param base ENC peripheral base address - * @param enable Enables or disables the watchdog - */ -void ENC_EnableWatchdog(ENC_Type *base, bool enable); - -/*! - * @brief Set initial position value for ENC module. - * - * @param base ENC peripheral base address - * @param value Positive initial value - */ -void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value); - -/* @} */ - -/*! - * @name Status - * @{ - */ -/*! - * @brief Get the status flags. - * - * @param base ENC peripheral base address. - * - * @return Mask value of status flags. For available mask, see to "_enc_status_flags". - */ -uint32_t ENC_GetStatusFlags(ENC_Type *base); - -/*! - * @brief Clear the status flags. - * - * @param base ENC peripheral base address. - * @param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags". - */ -void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask); - -/*! - * @brief Get the signals' real-time status. - * - * @param base ENC peripheral base address. - * - * @return Mask value of signals' real-time status. For available mask, see to "_enc_signal_status_flags" - */ -static inline uint16_t ENC_GetSignalStatusFlags(ENC_Type *base) -{ - return base->IMR; -} -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enable the interrupts. - * - * @param base ENC peripheral base address. - * @param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable". - */ -void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask); - -/*! - * @brief Disable the interrupts. - * - * @param base ENC peripheral base address. - * @param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable". - */ -void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask); - -/*! - * @brief Get the enabled interrupts' flags. - * - * @param base ENC peripheral base address. - * - * @return Mask value of enabled interrupts. - */ -uint32_t ENC_GetEnabledInterrupts(ENC_Type *base); - -/* @} */ - -/*! - * @name Value Operation - * @{ - */ - -/*! - * @brief Get the current position counter's value. - * - * @param base ENC peripheral base address. - * - * @return Current position counter's value. - */ -uint32_t ENC_GetPositionValue(ENC_Type *base); - -/*! - * @brief Get the hold position counter's value. - * - * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold - * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to - * be attained. - * - * @param base ENC peripheral base address. - * - * @return Hold position counter's value. - */ -uint32_t ENC_GetHoldPositionValue(ENC_Type *base); - -/*! - * @brief Get the position difference counter's value. - * - * @param base ENC peripheral base address. - * - * @return The position difference counter's value. - */ -static inline uint16_t ENC_GetPositionDifferenceValue(ENC_Type *base) -{ - return base->POSD; -} - -/*! - * @brief Get the hold position difference counter's value. - * - * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold - * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to - * be attained. - * - * @param base ENC peripheral base address. - * - * @return Hold position difference counter's value. - */ -static inline uint16_t ENC_GetHoldPositionDifferenceValue(ENC_Type *base) -{ - return base->POSDH; -} - -/*! - * @brief Get the position revolution counter's value. - * - * @param base ENC peripheral base address. - * - * @return The position revolution counter's value. - */ -static inline uint16_t ENC_GetRevolutionValue(ENC_Type *base) -{ - return base->REV; -} -/*! - * @brief Get the hold position revolution counter's value. - * - * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold - * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to - * be attained. - * - * @param base ENC peripheral base address. - * - * @return Hold position revolution counter's value. - */ -static inline uint16_t ENC_GetHoldRevolutionValue(ENC_Type *base) -{ - return base->REVH; -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/* - * @} - */ -#endif /* _FSL_ENC_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.c deleted file mode 100644 index d44b73eb94..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.c +++ /dev/null @@ -1,2975 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_enet.h" -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL -#include "fsl_cache.h" -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.enet" -#endif - -/*! @brief IPv4 PTP message IP version offset. */ -#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU -/*! @brief IPv4 PTP message UDP protocol offset. */ -#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U -/*! @brief IPv4 PTP message UDP port offset. */ -#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U -/*! @brief IPv4 PTP message UDP message type offset. */ -#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU -/*! @brief IPv4 PTP message UDP version offset. */ -#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU -/*! @brief IPv4 PTP message UDP clock id offset. */ -#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU -/*! @brief IPv4 PTP message UDP sequence id offset. */ -#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U -/*! @brief IPv4 PTP message UDP control offset. */ -#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU -/*! @brief IPv6 PTP message UDP protocol offset. */ -#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U -/*! @brief IPv6 PTP message UDP port offset. */ -#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U -/*! @brief IPv6 PTP message UDP message type offset. */ -#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU -/*! @brief IPv6 PTP message UDP version offset. */ -#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU -/*! @brief IPv6 PTP message UDP clock id offset. */ -#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U -/*! @brief IPv6 PTP message UDP sequence id offset. */ -#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU -/*! @brief IPv6 PTP message UDP control offset. */ -#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU -/*! @brief PTPv2 message Ethernet packet type offset. */ -#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU -/*! @brief PTPv2 message Ethernet message type offset. */ -#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU -/*! @brief PTPv2 message Ethernet version type offset. */ -#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU -/*! @brief PTPv2 message Ethernet clock id offset. */ -#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22 -/*! @brief PTPv2 message Ethernet sequence id offset. */ -#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c -/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */ -#define ENET_ETHERNETL2 0x88F7U -/*! @brief Packet type IPv4. */ -#define ENET_IPV4 0x0800U -/*! @brief Packet type IPv6. */ -#define ENET_IPV6 0x86ddU -/*! @brief Packet type VLAN. */ -#define ENET_8021QVLAN 0x8100U -/*! @brief UDP protocol type. */ -#define ENET_UDPVERSION 0x0011U -/*! @brief Packet IP version IPv4. */ -#define ENET_IPV4VERSION 0x0004U -/*! @brief Packet IP version IPv6. */ -#define ENET_IPV6VERSION 0x0006U -/*! @brief Ethernet mac address length. */ -#define ENET_FRAME_MACLEN 6U -/*! @brief Ethernet VLAN header length. */ -#define ENET_FRAME_VLAN_TAGLEN 4U -/*! @brief MDC frequency. */ -#define ENET_MDC_FREQUENCY 2500000U -/*! @brief NanoSecond in one second. */ -#define ENET_NANOSECOND_ONE_SECOND 1000000000U -/*! @brief Define a common clock cycle delays used for time stamp capture. */ -#ifndef ENET_1588TIME_DELAY_COUNT -#define ENET_1588TIME_DELAY_COUNT 10U -#endif - -/*! @brief Defines the macro for converting constants from host byte order to network byte order. */ -#define ENET_HTONS(n) __REV16(n) -#define ENET_HTONL(n) __REV(n) -#define ENET_NTOHS(n) __REV16(n) -#define ENET_NTOHL(n) __REV(n) - -/*! @brief Define the ENET ring/class bumber . */ -enum _enet_ring_number -{ - kENET_Ring0 = 0U, /*!< ENET ring/class 0. */ -#if FSL_FEATURE_ENET_QUEUE > 1 - kENET_Ring1 = 1U, /*!< ENET ring/class 1. */ - kENET_Ring2 = 2U /*!< ENET ring/class 2. */ -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ -}; - -/*! @brief Define interrupt IRQ handler. */ -#if FSL_FEATURE_ENET_QUEUE > 1 -typedef void (*enet_isr_ring_t)(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ -typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle); - -/******************************************************************************* -* Prototypes -******************************************************************************/ - -/*! - * @brief Get the ENET instance from peripheral base address. - * - * @param base ENET peripheral base address. - * @return ENET instance. - */ -uint32_t ENET_GetInstance(ENET_Type *base); -/*! - * @brief Set ENET MAC controller with the configuration. - * - * @param base ENET peripheral base address. - * @param handle The ENET handle pointer. - * @param config ENET Mac configuration. - * @param bufferConfig ENET buffer configuration. - * @param macAddr ENET six-byte mac address. - * @param srcClock_Hz ENET module clock source, normally it's system clock. - */ -static void ENET_SetMacController(ENET_Type *base, - enet_handle_t *handle, - const enet_config_t *config, - const enet_buffer_config_t *bufferConfig, - uint8_t *macAddr, - uint32_t srcClock_Hz); -/*! - * @brief Set ENET handler. - * - * @param base ENET peripheral base address. - * @param handle The ENET handle pointer. - * @param config ENET configuration stucture pointer. - * @param bufferConfig ENET buffer configuration. - */ -static void ENET_SetHandler(ENET_Type *base, - enet_handle_t *handle, - const enet_config_t *config, - const enet_buffer_config_t *bufferConfig); -/*! - * @brief Set ENET MAC transmit buffer descriptors. - * - * @param handle The ENET handle pointer. - * @param config The ENET configuration structure. - * @param bufferConfig The ENET buffer configuration. - */ -static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig); - -/*! - * @brief Set ENET MAC receive buffer descriptors. - * - * @param handle The ENET handle pointer. - * @param config The ENET configuration structure. - * @param bufferConfig The ENET buffer configuration. - */ -static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig); - -/*! - * @brief Updates the ENET read buffer descriptors. - * - * @param base ENET peripheral base address. - * @param handle The ENET handle pointer. - * @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. - * 0 ----- for single ring kinetis platform. - * 0 ~ 2 for mulit-ring supported IMX8qm. - */ -static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); - -/*! - * @brief Activates ENET send for multiple tx rings. - * - * @param base ENET peripheral base address. - * @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. - * 0 ----- for single ring kinetis platform. - * 0 ~ 2 for mulit-ring supported IMX8qm. - * - * @note This must be called after the MAC configuration and - * state are ready. It must be called after the ENET_Init() and - * this should be called when the ENET receive required. - */ -static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId); -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE -/*! - * @brief Parses the ENET frame for time-stamp process of PTP 1588 frame. - * - * @param data The ENET read data for frame parse. - * @param ptpTsData The ENET PTP message and time-stamp data pointer. - * @param isFastEnabled The fast parse flag. - * - true , Fast processing, only check if this is a PTP message. - * - false, Store the PTP message data after check the PTP message. - */ -static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled); - -/*! - * @brief Updates the new PTP 1588 time-stamp to the time-stamp buffer ring. - * - * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. - * @param ptpTimeData The new PTP 1588 time-stamp data pointer. - */ -static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData); - -/*! - * @brief Search up the right PTP 1588 time-stamp from the time-stamp buffer ring. - * - * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. - * @param ptpTimeData The find out right PTP 1588 time-stamp data pointer with the specific PTP message. - */ -static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata); - -/*! - * @brief Store the transmit time-stamp for event PTP frame in the time-stamp buffer ring. - * - * @param base ENET peripheral base address. - * @param handle The ENET handle pointer. - * @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. - * 0 ----- for single ring kinetis platform. - * 0 ~ 2 for mulit-ring supported IMX8qm. - */ -static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); - -/*! - * @brief Store the receive time-stamp for event PTP frame in the time-stamp buffer ring. - * - * @param base ENET peripheral base address. - * @param handle The ENET handle pointer. - * @param ptpTimeData The PTP 1588 time-stamp data pointer. - */ -static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); - -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_AVB -/*! - * @brief Gets the ring index for transmission. - * - * @param base ENET peripheral base address. - * @param data The ENET transmit data. - * @param handle The ENET handle pointer. - * - * @note This must be called after the MAC configuration and - * state are ready. It must be called after the ENET_Init() and - * this should be called when the ENET receive required. - */ -static uint8_t ENET_GetTxRingId(ENET_Type *base, uint8_t *data, enet_handle_t *handle); -#endif /* FSL_FEATURE_ENET_HAS_AVB */ -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Pointers to enet handles for each instance. */ -static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_ENET_COUNT] = {NULL}; - -/*! @brief Pointers to enet clocks for each instance. */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -const clock_ip_name_t s_enetClock[] = ENET_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to enet transmit IRQ number for each instance. */ -static const IRQn_Type s_enetTxIrqId[] = ENET_Transmit_IRQS; -/*! @brief Pointers to enet receive IRQ number for each instance. */ -static const IRQn_Type s_enetRxIrqId[] = ENET_Receive_IRQS; -#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) && ENET_ENHANCEDBUFFERDESCRIPTOR_MODE -/*! @brief Pointers to enet timestamp IRQ number for each instance. */ -static const IRQn_Type s_enetTsIrqId[] = ENET_1588_Timer_IRQS; -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ -/*! @brief Pointers to enet error IRQ number for each instance. */ -static const IRQn_Type s_enetErrIrqId[] = ENET_Error_IRQS; - -/*! @brief Pointers to enet bases for each instance. */ -static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS; - -/* ENET ISR for transactional APIs. */ -#if FSL_FEATURE_ENET_QUEUE > 1 -static enet_isr_ring_t s_enetTxIsr; -static enet_isr_ring_t s_enetRxIsr; -#else -static enet_isr_t s_enetTxIsr; -static enet_isr_t s_enetRxIsr; -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ -static enet_isr_t s_enetErrIsr; -static enet_isr_t s_enetTsIsr; -/******************************************************************************* - * Code - ******************************************************************************/ - -uint32_t ENET_GetInstance(ENET_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_enetBases); instance++) - { - if (s_enetBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_enetBases)); - - return instance; -} - -void ENET_GetDefaultConfig(enet_config_t *config) -{ - /* Checks input parameter. */ - assert(config); - - /* Initializes the MAC configure structure to zero. */ - memset(config, 0, sizeof(enet_config_t)); - - /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB - config->miiMode = kENET_RgmiiMode; -#else - config->miiMode = kENET_RmiiMode; -#endif - config->miiSpeed = kENET_MiiSpeed100M; - config->miiDuplex = kENET_MiiFullDuplex; - - config->ringNum = 1; - - /* Sets the maximum receive frame length. */ - config->rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; -} - -void ENET_Init(ENET_Type *base, - enet_handle_t *handle, - const enet_config_t *config, - const enet_buffer_config_t *bufferConfig, - uint8_t *macAddr, - uint32_t srcClock_Hz) -{ - /* Checks input parameters. */ - assert(handle); - assert(config); - assert(bufferConfig); - assert(macAddr); - assert(config->ringNum <= FSL_FEATURE_ENET_QUEUE); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - uint32_t instance = ENET_GetInstance(base); - - /* Ungate ENET clock. */ - CLOCK_EnableClock(s_enetClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Reset ENET module. */ - ENET_Reset(base); - - /* Initializes the ENET transmit buffer descriptors. */ - ENET_SetTxBufferDescriptors(handle, config, bufferConfig); - - /* Initializes the ENET receive buffer descriptors. */ - ENET_SetRxBufferDescriptors(handle, config, bufferConfig); - - /* Initializes the ENET MAC controller with basic function. */ - ENET_SetMacController(base, handle, config, bufferConfig, macAddr, srcClock_Hz); - - /* Set all buffers or data in handler for data transmit/receive process. */ - ENET_SetHandler(base, handle, config, bufferConfig); -} - -void ENET_Deinit(ENET_Type *base) -{ - /* Disable interrupt. */ - base->EIMR = 0; - - /* Disable ENET. */ - base->ECR &= ~ENET_ECR_ETHEREN_MASK; - - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disables the clock source. */ - CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData) -{ - assert(handle); - - /* Set callback and userData. */ - handle->callback = callback; - handle->userData = userData; -} - -static void ENET_SetHandler(ENET_Type *base, - enet_handle_t *handle, - const enet_config_t *config, - const enet_buffer_config_t *bufferConfig) -{ - uint8_t count; - uint32_t instance = ENET_GetInstance(base); - const enet_buffer_config_t *buffCfg = bufferConfig; - - /* Store transfer parameters in handle pointer. */ - memset(handle, 0, sizeof(enet_handle_t)); - - handle->ringNum = (config->ringNum > FSL_FEATURE_ENET_QUEUE) ? FSL_FEATURE_ENET_QUEUE : config->ringNum; - for (count = 0; count < handle->ringNum; count++) - { - assert(buffCfg->rxBuffSizeAlign * buffCfg->rxBdNumber > config->rxMaxFrameLen); - - handle->rxBdBase[count] = buffCfg->rxBdStartAddrAlign; - handle->rxBdCurrent[count] = buffCfg->rxBdStartAddrAlign; - handle->rxBuffSizeAlign[count] = buffCfg->rxBuffSizeAlign; - handle->txBdBase[count] = buffCfg->txBdStartAddrAlign; - handle->txBdCurrent[count] = buffCfg->txBdStartAddrAlign; - handle->txBuffSizeAlign[count] = buffCfg->txBuffSizeAlign; - buffCfg++; - } - - /* Save the handle pointer in the global variables. */ - s_ENETHandle[instance] = handle; - - /* Set the IRQ handler when the interrupt is enabled. */ - if (config->interrupt & ENET_TX_INTERRUPT) - { - s_enetTxIsr = ENET_TransmitIRQHandler; - EnableIRQ(s_enetTxIrqId[instance]); - } - if (config->interrupt & ENET_RX_INTERRUPT) - { - s_enetRxIsr = ENET_ReceiveIRQHandler; - EnableIRQ(s_enetRxIrqId[instance]); - } - if (config->interrupt & ENET_ERR_INTERRUPT) - { - s_enetErrIsr = ENET_ErrorIRQHandler; - EnableIRQ(s_enetErrIrqId[instance]); - } -} - -static void ENET_SetMacController(ENET_Type *base, - enet_handle_t *handle, - const enet_config_t *config, - const enet_buffer_config_t *bufferConfig, - uint8_t *macAddr, - uint32_t srcClock_Hz) -{ -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB - /* Check the MII mode/speed/duplex setting. */ - if (config->miiSpeed == kENET_MiiSpeed1000M) - { - /* Only RGMII mode has the 1000M bit/s. The 1000M only support full duplex. */ - assert(config->miiMode == kENET_RgmiiMode); - assert(config->miiDuplex == kENET_MiiFullDuplex); - } -#endif /* FSL_FEATURE_ENET_HAS_AVB */ - - uint32_t rcr = 0; - uint32_t tcr = 0; - uint32_t ecr = base->ECR; - uint32_t macSpecialConfig = config->macSpecialConfig; - uint32_t maxFrameLen = config->rxMaxFrameLen; - - /* Maximum frame length check. */ - if ((macSpecialConfig & kENET_ControlVLANTagEnable) && (maxFrameLen <= ENET_FRAME_MAX_FRAMELEN)) - { - maxFrameLen = (ENET_FRAME_MAX_FRAMELEN + ENET_FRAME_VLAN_TAGLEN); -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB - if (macSpecialConfig & kENET_ControlSVLANEnable) - { - /* Double vlan tag (SVLAN) supported. */ - maxFrameLen += ENET_FRAME_VLAN_TAGLEN; - } - ecr |= ((macSpecialConfig & kENET_ControlSVLANEnable) ? (ENET_ECR_SVLANEN_MASK | ENET_ECR_SVLANDBL_MASK) : 0) | - ((macSpecialConfig & kENET_ControlVLANUseSecondTag) ? ENET_ECR_VLANUSE2ND_MASK : 0); -#endif /* FSL_FEATURE_ENET_HAS_AVB */ - } - - /* Configures MAC receive controller with user configure structure. */ - rcr = ((macSpecialConfig & kENET_ControlRxPayloadCheckEnable) ? ENET_RCR_NLC_MASK : 0) | - ((macSpecialConfig & kENET_ControlFlowControlEnable) ? ENET_RCR_CFEN_MASK : 0) | - ((macSpecialConfig & kENET_ControlFlowControlEnable) ? ENET_RCR_FCE_MASK : 0) | - ((macSpecialConfig & kENET_ControlRxPadRemoveEnable) ? ENET_RCR_PADEN_MASK : 0) | - ((macSpecialConfig & kENET_ControlRxBroadCastRejectEnable) ? ENET_RCR_BC_REJ_MASK : 0) | - ((macSpecialConfig & kENET_ControlPromiscuousEnable) ? ENET_RCR_PROM_MASK : 0) | - ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD_MASK; - -/* Set the RGMII or RMII, MII mode and control register. */ -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB - if (config->miiMode == kENET_RgmiiMode) - { - rcr |= ENET_RCR_RGMII_EN_MASK; - rcr &= ~ENET_RCR_MII_MODE_MASK; - } - else - { - rcr &= ~ENET_RCR_RGMII_EN_MASK; -#endif /* FSL_FEATURE_ENET_HAS_AVB */ - rcr |= ENET_RCR_MII_MODE_MASK; - if (config->miiMode == kENET_RmiiMode) - { - rcr |= ENET_RCR_RMII_MODE_MASK; - } -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB - } -#endif /* FSL_FEATURE_ENET_HAS_AVB */ - /* Speed. */ - if (config->miiSpeed == kENET_MiiSpeed10M) - { - rcr |= ENET_RCR_RMII_10T_MASK; - } -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB - if (config->miiSpeed == kENET_MiiSpeed1000M) - { - ecr |= ENET_ECR_SPEED_MASK; - } -#endif /* FSL_FEATURE_ENET_HAS_AVB */ - - /* Receive setting for half duplex. */ - if (config->miiDuplex == kENET_MiiHalfDuplex) - { - rcr |= ENET_RCR_DRT_MASK; - } - /* Sets internal loop only for MII mode. */ - if ((config->macSpecialConfig & kENET_ControlMIILoopEnable) && (config->miiMode != kENET_RmiiMode)) - { - rcr |= ENET_RCR_LOOP_MASK; - rcr &= ~ENET_RCR_DRT_MASK; - } - base->RCR = rcr; - - /* Configures MAC transmit controller: duplex mode, mac address insertion. */ - tcr = base->TCR & ~(ENET_TCR_FDEN_MASK | ENET_TCR_ADDINS_MASK); - tcr |= (config->miiDuplex ? ENET_TCR_FDEN_MASK : 0) | - ((macSpecialConfig & kENET_ControlMacAddrInsert) ? ENET_TCR_ADDINS_MASK : 0); - base->TCR = tcr; - - /* Configures receive and transmit accelerator. */ - base->TACC = config->txAccelerConfig; - base->RACC = config->rxAccelerConfig; - - /* Sets the pause duration and FIFO threshold for the flow control enabled case. */ - if (macSpecialConfig & kENET_ControlFlowControlEnable) - { - uint32_t reemReg; - base->OPD = config->pauseDuration; - reemReg = ENET_RSEM_RX_SECTION_EMPTY(config->rxFifoEmptyThreshold); -#if defined(FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD - reemReg |= ENET_RSEM_STAT_SECTION_EMPTY(config->rxFifoStatEmptyThreshold); -#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ - base->RSEM = reemReg; - } - - /* FIFO threshold setting for store and forward enable/disable case. */ - if (macSpecialConfig & kENET_ControlStoreAndFwdDisable) - { - /* Transmit fifo watermark settings. */ - base->TFWR = config->txFifoWatermark & ENET_TFWR_TFWR_MASK; - /* Receive fifo full threshold settings. */ - base->RSFL = config->rxFifoFullThreshold & ENET_RSFL_RX_SECTION_FULL_MASK; - } - else - { - /* Transmit fifo watermark settings. */ - base->TFWR = ENET_TFWR_STRFWD_MASK; - base->RSFL = 0; - } - - /* Enable store and forward when accelerator is enabled */ - if (config->txAccelerConfig & (kENET_TxAccelIpCheckEnabled | kENET_TxAccelProtoCheckEnabled)) - { - base->TFWR = ENET_TFWR_STRFWD_MASK; - } - if (config->rxAccelerConfig & (kENET_RxAccelIpCheckEnabled | kENET_RxAccelProtoCheckEnabled)) - { - base->RSFL = 0; - } - - /* Initializes the ring 0. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - base->TDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->txBdStartAddrAlign, kMEMORY_Local2DMA); - base->RDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->rxBdStartAddrAlign, kMEMORY_Local2DMA); -#else - base->TDSR = (uint32_t)bufferConfig->txBdStartAddrAlign; - base->RDSR = (uint32_t)bufferConfig->rxBdStartAddrAlign; -#endif - base->MRBR = bufferConfig->rxBuffSizeAlign; - -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB - const enet_buffer_config_t *buffCfg = bufferConfig; - - if (config->ringNum > 1) - { - /* Initializes the ring 1. */ - buffCfg++; -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - base->TDSR1 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->txBdStartAddrAlign, kMEMORY_Local2DMA); - base->RDSR1 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBdStartAddrAlign, kMEMORY_Local2DMA); -#else - base->TDSR1 = (uint32_t)buffCfg->txBdStartAddrAlign; - base->RDSR1 = (uint32_t)buffCfg->rxBdStartAddrAlign; -#endif - base->MRBR1 = buffCfg->rxBuffSizeAlign; - /* Enable the DMAC for ring 1 and with no rx classification set. */ - base->DMACFG[0] = ENET_DMACFG_DMA_CLASS_EN_MASK; - } - if (config->ringNum > 2) - { - /* Initializes the ring 2. */ - buffCfg++; -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - base->TDSR2 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->txBdStartAddrAlign, kMEMORY_Local2DMA); - base->RDSR2 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBdStartAddrAlign, kMEMORY_Local2DMA); -#else - base->TDSR2 = (uint32_t)buffCfg->txBdStartAddrAlign; - base->RDSR2 = (uint32_t)buffCfg->rxBdStartAddrAlign; -#endif - base->MRBR2 = buffCfg->rxBuffSizeAlign; - /* Enable the DMAC for ring 2 and with no rx classification set. */ - base->DMACFG[1] = ENET_DMACFG_DMA_CLASS_EN_MASK; - } - - /* Default the class/ring 1 and 2 are not enabled and the receive classification is disabled - * so we set the default transmit scheme with the round-robin mode. beacuse the legacy bd mode - * only support the round-robin mode. if the avb feature is required, just call the setup avb - * feature API. */ - base->QOS |= ENET_QOS_TX_SCHEME(1); -#endif /* FSL_FEATURE_ENET_HAS_AVB */ - - /* Configures the Mac address. */ - ENET_SetMacAddr(base, macAddr); - - /* Initialize the SMI if uninitialized. */ - if (!ENET_GetSMI(base)) - { - ENET_SetSMI(base, srcClock_Hz, !!(config->macSpecialConfig & kENET_ControlSMIPreambleDisable)); - } - -/* Enables Ethernet interrupt, enables the interrupt coalsecing if it is required. */ -#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE - if (config->intCoalesceCfg) - { - uint32_t intMask = (ENET_EIMR_TXB_MASK | ENET_EIMR_RXB_MASK); - -#if FSL_FEATURE_ENET_QUEUE > 1 - uint8_t queue = 0; - intMask |= ENET_EIMR_TXB2_MASK | ENET_EIMR_RXB2_MASK | ENET_EIMR_TXB1_MASK | ENET_EIMR_RXB1_MASK; -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - - /* Clear all buffer interrupts. */ - base->EIMR &= ~intMask; - -/* Set the interrupt coalescence. */ -#if FSL_FEATURE_ENET_QUEUE > 1 - for (queue = 0; queue < FSL_FEATURE_ENET_QUEUE; queue++) - { - base->TXIC[queue] = ENET_TXIC_ICFT(config->intCoalesceCfg->txCoalesceFrameCount[queue]) | - config->intCoalesceCfg->txCoalesceTimeCount[queue] | ENET_TXIC_ICCS_MASK | - ENET_TXIC_ICEN_MASK; - base->RXIC[queue] = ENET_RXIC_ICFT(config->intCoalesceCfg->rxCoalesceFrameCount[queue]) | - config->intCoalesceCfg->rxCoalesceTimeCount[queue] | ENET_RXIC_ICCS_MASK | - ENET_RXIC_ICEN_MASK; - } -#else - base->TXIC = ENET_TXIC_ICFT(config->intCoalesceCfg->txCoalesceFrameCount[0]) | - config->intCoalesceCfg->txCoalesceTimeCount[0] | ENET_TXIC_ICCS_MASK | ENET_TXIC_ICEN_MASK; - base->RXIC = ENET_RXIC_ICFT(config->intCoalesceCfg->rxCoalesceFrameCount[0]) | - config->intCoalesceCfg->rxCoalesceTimeCount[0] | ENET_RXIC_ICCS_MASK | ENET_RXIC_ICEN_MASK; -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - } -#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ - ENET_EnableInterrupts(base, config->interrupt); - -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* Sets the 1588 enhanced feature. */ - ecr |= ENET_ECR_EN1588_MASK; -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - /* Enables Ethernet module after all configuration except the buffer descriptor active. */ - ecr |= ENET_ECR_ETHEREN_MASK | ENET_ECR_DBSWP_MASK; - base->ECR = ecr; -} - -static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig) -{ - assert(config); - assert(bufferConfig); - - /* Default single ring is supported. */ - uint8_t ringNum; - uint32_t count; - uint32_t txBuffSizeAlign; - uint8_t *txBuffer; - const enet_buffer_config_t *buffCfg = bufferConfig; - - /* Check the input parameters. */ - for (ringNum = 0; ringNum < config->ringNum; ringNum++) - { - if ((buffCfg->txBdStartAddrAlign > 0) && (buffCfg->txBufferAlign > 0)) - { - volatile enet_tx_bd_struct_t *curBuffDescrip = buffCfg->txBdStartAddrAlign; - txBuffSizeAlign = buffCfg->txBuffSizeAlign; -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - txBuffer = (uint8_t *)MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->txBufferAlign, kMEMORY_Local2DMA); -#else - txBuffer = buffCfg->txBufferAlign; -#endif - for (count = 0; count < buffCfg->txBdNumber; count++) - { - /* Set data buffer address. */ - curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffer[count * txBuffSizeAlign]); - /* Initializes data length. */ - curBuffDescrip->length = 0; - /* Sets the crc. */ - curBuffDescrip->control = ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK; - /* Sets the last buffer descriptor with the wrap flag. */ - if (count == buffCfg->txBdNumber - 1) - { - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_WRAP_MASK; - } - -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* Enable transmit interrupt for store the transmit timestamp. */ - curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK; -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB - /* Set the type of the frame when the credit-based scheme is used. */ - curBuffDescrip->controlExtend1 |= ENET_BD_FTYPE(ringNum); -#endif /* FSL_FEATURE_ENET_HAS_AVB */ -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - /* Increase the index. */ - curBuffDescrip++; - } - } - buffCfg++; - } -} - -static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig) -{ - assert(config); - assert(bufferConfig); - - /* Default single ring is supported. */ - uint8_t ringNum; - uint32_t count; - uint32_t rxBuffSizeAlign; - uint8_t *rxBuffer; - const enet_buffer_config_t *buffCfg = bufferConfig; -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - uint32_t mask = (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt); -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - /* Check the input parameters. */ - for (ringNum = 0; ringNum < config->ringNum; ringNum++) - { - assert(buffCfg->rxBuffSizeAlign >= ENET_RX_MIN_BUFFERSIZE); -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE -#if FSL_FEATURE_ENET_QUEUE > 1 - if (ringNum == 1) - { - mask = (kENET_RxFrame1Interrupt | kENET_RxBuffer1Interrupt); - } - else if (ringNum == 2) - { - mask = (kENET_RxFrame2Interrupt | kENET_RxBuffer2Interrupt); - } -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - if ((buffCfg->rxBdStartAddrAlign > 0) && (buffCfg->rxBufferAlign > 0)) - { - volatile enet_rx_bd_struct_t *curBuffDescrip = buffCfg->rxBdStartAddrAlign; - rxBuffSizeAlign = buffCfg->rxBuffSizeAlign; -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - rxBuffer = (uint8_t *)MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBufferAlign, kMEMORY_Local2DMA); -#else - rxBuffer = buffCfg->rxBufferAlign; -#endif - -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Invalidate rx buffers before DMA transfer data into them. */ - DCACHE_InvalidateByRange((uint32_t)rxBuffer, (buffCfg->rxBdNumber * rxBuffSizeAlign)); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - - for (count = 0; count < buffCfg->rxBdNumber; count++) - { - /* Set data buffer and the length. */ - curBuffDescrip->buffer = (uint8_t *)((uint32_t)&rxBuffer[count * rxBuffSizeAlign]); - curBuffDescrip->length = 0; - - /* Initializes the buffer descriptors with empty bit. */ - curBuffDescrip->control = ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; - /* Sets the last buffer descriptor with the wrap flag. */ - if (count == buffCfg->rxBdNumber - 1) - { - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; - } - -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - if (config->interrupt & mask) - { - /* Enable receive interrupt. */ - curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK; - } - else - { - curBuffDescrip->controlExtend1 = 0; - } -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - /* Increase the index. */ - curBuffDescrip++; - } - } - buffCfg++; - } -} - -static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId) -{ - assert(ringId < FSL_FEATURE_ENET_QUEUE); - - switch (ringId) - { - case kENET_Ring0: - base->TDAR = ENET_TDAR_TDAR_MASK; - break; -#if FSL_FEATURE_ENET_QUEUE > 1 - case kENET_Ring1: - base->TDAR1 = ENET_TDAR1_TDAR_MASK; - break; - case kENET_Ring2: - base->TDAR2 = ENET_TDAR2_TDAR_MASK; - break; -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - default: - base->TDAR = ENET_TDAR_TDAR_MASK; - break; - } -} - -void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex) -{ - uint32_t rcr = base->RCR; - uint32_t tcr = base->TCR; - -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB - uint32_t ecr = base->ECR; - - if (kENET_MiiSpeed1000M == speed) - { - assert(duplex == kENET_MiiFullDuplex); - ecr |= ENET_ECR_SPEED_MASK; - } - else - { - ecr &= ~ENET_ECR_SPEED_MASK; - } - - base->ECR = ecr; -#endif /* FSL_FEATURE_ENET_HAS_AVB */ - - /* Sets speed mode. */ - if (kENET_MiiSpeed10M == speed) - { - rcr |= ENET_RCR_RMII_10T_MASK; - } - else - { - rcr &= ~ENET_RCR_RMII_10T_MASK; - } - /* Set duplex mode. */ - if (duplex == kENET_MiiHalfDuplex) - { - rcr |= ENET_RCR_DRT_MASK; - tcr &= ~ENET_TCR_FDEN_MASK; - } - else - { - rcr &= ~ENET_RCR_DRT_MASK; - tcr |= ENET_TCR_FDEN_MASK; - } - - base->RCR = rcr; - base->TCR = tcr; -} - -void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr) -{ - uint32_t address; - - /* Set physical address lower register. */ - address = (uint32_t)(((uint32_t)macAddr[0] << 24U) | ((uint32_t)macAddr[1] << 16U) | ((uint32_t)macAddr[2] << 8U) | - (uint32_t)macAddr[3]); - base->PALR = address; - /* Set physical address high register. */ - address = (uint32_t)(((uint32_t)macAddr[4] << 8U) | ((uint32_t)macAddr[5])); - base->PAUR = address << ENET_PAUR_PADDR2_SHIFT; -} - -void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr) -{ - assert(macAddr); - - uint32_t address; - - /* Get from physical address lower register. */ - address = base->PALR; - macAddr[0] = 0xFFU & (address >> 24U); - macAddr[1] = 0xFFU & (address >> 16U); - macAddr[2] = 0xFFU & (address >> 8U); - macAddr[3] = 0xFFU & address; - - /* Get from physical address high register. */ - address = (base->PAUR & ENET_PAUR_PADDR2_MASK) >> ENET_PAUR_PADDR2_SHIFT; - macAddr[4] = 0xFFU & (address >> 8U); - macAddr[5] = 0xFFU & address; -} - -void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled) -{ - assert(srcClock_Hz); - - uint32_t clkCycle = 0; - uint32_t speed = 0; - uint32_t mscr = 0; - - /* Calculate the MII speed which controls the frequency of the MDC. */ - speed = srcClock_Hz / (2 * ENET_MDC_FREQUENCY); - /* Calculate the hold time on the MDIO output. */ - clkCycle = (10 + ENET_NANOSECOND_ONE_SECOND / srcClock_Hz - 1) / (ENET_NANOSECOND_ONE_SECOND / srcClock_Hz) - 1; - /* Build the configuration for MDC/MDIO control. */ - mscr = ENET_MSCR_MII_SPEED(speed) | ENET_MSCR_HOLDTIME(clkCycle) | (isPreambleDisabled ? ENET_MSCR_DIS_PRE_MASK : 0); - base->MSCR = mscr; -} - -void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data) -{ - uint32_t mmfr = 0; - - /* Build MII write command. */ - mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2) | - (data & 0xFFFF); - base->MMFR = mmfr; -} - -void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation) -{ - uint32_t mmfr = 0; - - /* Build MII read command. */ - mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2); - base->MMFR = mmfr; -} - -#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO -void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) -{ - uint32_t mmfr = 0; - - /* Parse the address from the input register. */ - uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU; - uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU); - - /* Address write firstly. */ - mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | - ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); - base->MMFR = mmfr; - - /* Build MII write command. */ - mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiWriteFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | - ENET_MMFR_TA(2) | ENET_MMFR_DATA(data); - base->MMFR = mmfr; -} - -void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg) -{ - uint32_t mmfr = 0; - - /* Parse the address from the input register. */ - uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU; - uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU); - - /* Address write firstly. */ - mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | - ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); - base->MMFR = mmfr; - - /* Build MII read command. */ - mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiReadFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | - ENET_MMFR_TA(2); - base->MMFR = mmfr; -} -#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ - -void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) -{ - assert(handle); - assert(handle->rxBdCurrent[0]); - assert(eErrorStatic); - - uint16_t control = 0; - volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[0]; - - do - { - /* The last buffer descriptor of a frame. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) - { - control = curBuffDescrip->control; - if (control & ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK) - { - /* The receive truncate error. */ - eErrorStatic->statsRxTruncateErr++; - } - if (control & ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK) - { - /* The receive over run error. */ - eErrorStatic->statsRxOverRunErr++; - } - if (control & ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK) - { - /* The receive length violation error. */ - eErrorStatic->statsRxLenGreaterErr++; - } - if (control & ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK) - { - /* The receive alignment error. */ - eErrorStatic->statsRxAlignErr++; - } - if (control & ENET_BUFFDESCRIPTOR_RX_CRC_MASK) - { - /* The receive CRC error. */ - eErrorStatic->statsRxFcsErr++; - } -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - uint16_t controlExt = curBuffDescrip->controlExtend1; - if (controlExt & ENET_BUFFDESCRIPTOR_RX_MACERR_MASK) - { - /* The MAC error. */ - eErrorStatic->statsRxMacErr++; - } - if (controlExt & ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK) - { - /* The PHY error. */ - eErrorStatic->statsRxPhyErr++; - } - if (controlExt & ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) - { - /* The receive collision error. */ - eErrorStatic->statsRxCollisionErr++; - } -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - break; - } - - /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) - { - curBuffDescrip = handle->rxBdBase[0]; - } - else - { - curBuffDescrip++; - } - - } while (curBuffDescrip != handle->rxBdCurrent[0]); -} - -status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length) -{ - assert(handle); - assert(handle->rxBdCurrent[0]); - assert(length); - - /* Reset the length to zero. */ - *length = 0; - - uint16_t validLastMask = ENET_BUFFDESCRIPTOR_RX_LAST_MASK | ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; - volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[0]; - - /* Check the current buffer descriptor's empty flag. if empty means there is no frame received. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK) - { - return kStatus_ENET_RxFrameEmpty; - } - - do - { - /* Add check for abnormal case. */ - if ((!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK)) && (!curBuffDescrip->length)) - { - return kStatus_ENET_RxFrameError; - } - - /* Find the last buffer descriptor. */ - if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) - { - /* The last buffer descriptor in the frame check the status of the received frame. */ - if ((curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_ERR_MASK) -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - || (curBuffDescrip->controlExtend1 & ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK) -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - ) - { - return kStatus_ENET_RxFrameError; - } - /* FCS is removed by MAC. */ - *length = curBuffDescrip->length; - return kStatus_Success; - } - /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) - { - curBuffDescrip = handle->rxBdBase[0]; - } - else - { - curBuffDescrip++; - } - - } while (curBuffDescrip != handle->rxBdCurrent[0]); - - /* The frame is on processing - set to empty status to make application to receive it next time. */ - return kStatus_ENET_RxFrameEmpty; -} - -status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length) -{ - assert(handle); - assert(handle->rxBdCurrent[0]); - - uint32_t len = 0; - uint32_t offset = 0; - uint16_t control; - bool isLastBuff = false; - volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[0]; - status_t result = kStatus_Success; - uint32_t address; - - /* For data-NULL input, only update the buffer descriptor. */ - if (!data) - { - do - { - /* Update the control flag. */ - control = handle->rxBdCurrent[0]->control; - /* Updates the receive buffer descriptors. */ - ENET_UpdateReadBuffers(base, handle, 0); - - /* Find the last buffer descriptor for the frame. */ - if (control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) - { - break; - } - - } while (handle->rxBdCurrent[0] != curBuffDescrip); - - return result; - } - else - { - /* A frame on one buffer or several receive buffers are both considered. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache invalidate maintain. */ - DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - enet_ptp_time_data_t ptpTimestamp; - bool isPtpEventMessage = false; - /* Parse the PTP message according to the header message. */ - isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - while (!isLastBuff) - { - /* The last buffer descriptor of a frame. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) - { - /* This is a valid frame. */ - isLastBuff = true; - if (length == curBuffDescrip->length) - { - /* Copy the frame to user's buffer without FCS. */ - len = curBuffDescrip->length - offset; - memcpy(data + offset, (void *)address, len); -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* Store the PTP 1588 timestamp for received PTP event frame. */ - if (isPtpEventMessage) - { - /* Set the timestamp to the timestamp ring. */ - ptpTimestamp.timeStamp.nanosecond = curBuffDescrip->timestamp; - result = ENET_StoreRxFrameTime(base, handle, &ptpTimestamp); - } -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - /* Updates the receive buffer descriptors. */ - ENET_UpdateReadBuffers(base, handle, 0); - return result; - } - else - { - /* Updates the receive buffer descriptors. */ - ENET_UpdateReadBuffers(base, handle, 0); - } - } - else - { - /* Store a frame on several buffer descriptors. */ - isLastBuff = false; - /* Length check. */ - if (offset >= length) - { - break; - } - - memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[0]); - offset += handle->rxBuffSizeAlign[0]; - - /* Updates the receive buffer descriptors. */ - ENET_UpdateReadBuffers(base, handle, 0); - } - - /* Get the current buffer descriptor. */ - curBuffDescrip = handle->rxBdCurrent[0]; - /* Add the cache invalidate maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - } - } - - return kStatus_ENET_RxFrameFail; -} - -static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) -{ - assert(handle); - assert(ringId < FSL_FEATURE_ENET_QUEUE); - - /* Clears status. */ - handle->rxBdCurrent[ringId]->control &= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; - /* Sets the receive buffer descriptor with the empty flag. */ - handle->rxBdCurrent[ringId]->control |= ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; - - /* Increase current buffer descriptor to the next one. */ - if (handle->rxBdCurrent[ringId]->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) - { - handle->rxBdCurrent[ringId] = handle->rxBdBase[ringId]; - } - else - { - handle->rxBdCurrent[ringId]++; - } - - /* Actives the receive buffer descriptor. */ - switch (ringId) - { - case kENET_Ring0: - base->RDAR = ENET_RDAR_RDAR_MASK; - break; -#if FSL_FEATURE_ENET_QUEUE > 1 - case kENET_Ring1: - base->RDAR1 = ENET_RDAR1_RDAR_MASK; - break; - case kENET_Ring2: - base->RDAR2 = ENET_RDAR2_RDAR_MASK; - break; -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - default: - base->RDAR = ENET_RDAR_RDAR_MASK; - break; - } -} - -status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length) -{ - assert(handle); - assert(data); - - volatile enet_tx_bd_struct_t *curBuffDescrip; - uint32_t len = 0; - uint32_t sizeleft = 0; - uint32_t address; - - /* Check the frame length. */ - if (length > ENET_FRAME_MAX_FRAMELEN) - { - return kStatus_ENET_TxFrameOverLen; - } - - /* Check if the transmit buffer is ready. */ - curBuffDescrip = handle->txBdCurrent[0]; - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) - { - return kStatus_ENET_TxFrameBusy; - } -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - bool isPtpEventMessage = false; - /* Check PTP message with the PTP header. */ - isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - /* One transmit buffer is enough for one frame. */ - if (handle->txBuffSizeAlign[0] >= length) - { - /* Copy data to the buffer for uDMA transfer. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - memcpy((void *)address, data, length); -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - DCACHE_CleanByRange(address, length); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - /* Set data length. */ - curBuffDescrip->length = length; -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* For enable the timestamp. */ - if (isPtpEventMessage) - { - curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - else - { - curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); - - /* Increase the buffer descriptor address. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdCurrent[0] = handle->txBdBase[0]; - } - else - { - handle->txBdCurrent[0]++; - } - /* Active the transmit buffer descriptor. */ - ENET_ActiveSend(base, 0); - - return kStatus_Success; - } - else - { - /* One frame requires more than one transmit buffers. */ - do - { -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* For enable the timestamp. */ - if (isPtpEventMessage) - { - curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - else - { - curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - /* Increase the buffer descriptor address. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdCurrent[0] = handle->txBdBase[0]; - } - else - { - handle->txBdCurrent[0]++; - } - /* update the size left to be transmit. */ - sizeleft = length - len; -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - if (sizeleft > handle->txBuffSizeAlign[0]) - { - /* Data copy. */ - memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]); -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ - DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - /* Data length update. */ - curBuffDescrip->length = handle->txBuffSizeAlign[0]; - len += handle->txBuffSizeAlign[0]; - /* Sets the control flag. */ - curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; - /* Active the transmit buffer descriptor*/ - ENET_ActiveSend(base, 0); - } - else - { - - memcpy((void *)address, data + len, sizeleft); -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ - DCACHE_CleanByRange(address, sizeleft); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - curBuffDescrip->length = sizeleft; - /* Set Last buffer wrap flag. */ - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; - /* Active the transmit buffer descriptor. */ - ENET_ActiveSend(base, 0); - - return kStatus_Success; - } - - /* Get the current buffer descriptor address. */ - curBuffDescrip = handle->txBdCurrent[0]; - - } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); - - return kStatus_ENET_TxFrameBusy; - } -} - -#if FSL_FEATURE_ENET_QUEUE > 1 -void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle, - enet_data_error_stats_t *eErrorStatic, - uint32_t ringId) -{ - assert(handle); - assert(eErrorStatic); - assert(ringId < FSL_FEATURE_ENET_QUEUE); - - uint16_t control = 0; - volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[ringId]; - - do - { - /* The last buffer descriptor of a frame. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) - { - control = curBuffDescrip->control; - if (control & ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK) - { - /* The receive truncate error. */ - eErrorStatic->statsRxTruncateErr++; - } - if (control & ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK) - { - /* The receive over run error. */ - eErrorStatic->statsRxOverRunErr++; - } - if (control & ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK) - { - /* The receive length violation error. */ - eErrorStatic->statsRxLenGreaterErr++; - } - if (control & ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK) - { - /* The receive alignment error. */ - eErrorStatic->statsRxAlignErr++; - } - if (control & ENET_BUFFDESCRIPTOR_RX_CRC_MASK) - { - /* The receive CRC error. */ - eErrorStatic->statsRxFcsErr++; - } -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - uint16_t controlExt = curBuffDescrip->controlExtend1; - if (controlExt & ENET_BUFFDESCRIPTOR_RX_MACERR_MASK) - { - /* The MAC error. */ - eErrorStatic->statsRxMacErr++; - } - if (controlExt & ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK) - { - /* The PHY error. */ - eErrorStatic->statsRxPhyErr++; - } - if (controlExt & ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) - { - /* The receive collision error. */ - eErrorStatic->statsRxCollisionErr++; - } -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - break; - } - - /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) - { - curBuffDescrip = handle->rxBdBase[ringId]; - } - else - { - curBuffDescrip++; - } - - } while (curBuffDescrip != handle->rxBdCurrent[ringId]); -} - -status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, uint32_t ringId) -{ - assert(handle); - assert(length); - assert(ringId < FSL_FEATURE_ENET_QUEUE); - - /* Reset the length to zero. */ - *length = 0; - uint16_t validLastMask = ENET_BUFFDESCRIPTOR_RX_LAST_MASK | ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; - volatile enet_rx_bd_struct_t *curBuffDescrip; - - curBuffDescrip = handle->rxBdCurrent[ringId]; - /* Check the current buffer descriptor's empty flag. if empty means there is no frame received. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK) - { - return kStatus_ENET_RxFrameEmpty; - } - - do - { - /* Add check for abnormal case. */ - if ((!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK)) && (!curBuffDescrip->length)) - { - return kStatus_ENET_RxFrameError; - } - /* Find the last buffer descriptor. */ - if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) - { - /* The last buffer descriptor in the frame check the status of the received frame. */ - if ((curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_ERR_MASK) -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - || (curBuffDescrip->controlExtend1 & ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK) -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - ) - { - return kStatus_ENET_RxFrameError; - } - /* FCS is removed by MAC. */ - *length = curBuffDescrip->length; - return kStatus_Success; - } - /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) - { - curBuffDescrip = handle->rxBdBase[ringId]; - } - else - { - curBuffDescrip++; - } - } while (curBuffDescrip != handle->rxBdCurrent[ringId]); - - /* The frame is on processing - set to empty status to make application to receive it next time. */ - return kStatus_ENET_RxFrameEmpty; -} - -status_t ENET_ReadFrameMultiRing( - ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId) -{ - assert(handle); - assert(ringId < FSL_FEATURE_ENET_QUEUE); - - uint32_t len = 0; - uint32_t offset = 0; - uint16_t control; - bool isLastBuff = false; - volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[ringId]; - status_t result = kStatus_Success; - uint32_t address; - - /* For data-NULL input, only update the buffer descriptor. */ - if (!data) - { - do - { - /* Update the control flag. */ - control = handle->rxBdCurrent[ringId]->control; - /* Updates the receive buffer descriptors. */ - ENET_UpdateReadBuffers(base, handle, ringId); - - /* Find the last buffer descriptor for the frame. */ - if (control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) - { - break; - } - - } while (handle->rxBdCurrent[ringId] != curBuffDescrip); - - return result; - } - else - { - /* A frame on one buffer or several receive buffers are both considered. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache invalidate maintain. */ - DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - enet_ptp_time_data_t ptpTimestamp; - bool isPtpEventMessage = false; - /* Parse the PTP message according to the header message. */ - isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - while (!isLastBuff) - { - /* The last buffer descriptor of a frame. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) - { - /* This is a valid frame. */ - isLastBuff = true; - if (length == curBuffDescrip->length) - { - /* Copy the frame to user's buffer without FCS. */ - len = curBuffDescrip->length - offset; - memcpy(data + offset, (void *)address, len); -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* Store the PTP 1588 timestamp for received PTP event frame. */ - if (isPtpEventMessage) - { - /* Set the timestamp to the timestamp ring. */ - ptpTimestamp.timeStamp.nanosecond = curBuffDescrip->timestamp; - result = ENET_StoreRxFrameTime(base, handle, &ptpTimestamp); - } -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - /* Updates the receive buffer descriptors. */ - ENET_UpdateReadBuffers(base, handle, ringId); - return result; - } - else - { - /* Updates the receive buffer descriptors. */ - ENET_UpdateReadBuffers(base, handle, ringId); - } - } - else - { - /* Store a frame on several buffer descriptors. */ - isLastBuff = false; - /* Length check. */ - if (offset >= length) - { - break; - } - memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[ringId]); - offset += handle->rxBuffSizeAlign[ringId]; - - - /* Updates the receive buffer descriptors. */ - ENET_UpdateReadBuffers(base, handle, ringId); - } - - /* Get the current buffer descriptor. */ - - curBuffDescrip = handle->rxBdCurrent[ringId]; -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache invalidate maintain. */ - DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - } - } - - return kStatus_ENET_RxFrameFail; -} - - -status_t ENET_SendFrameMultiRing( - ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId) -{ - assert(handle); - assert(data); - assert(ringId < FSL_FEATURE_ENET_QUEUE); - - volatile enet_tx_bd_struct_t *curBuffDescrip; - uint32_t len = 0; - uint32_t sizeleft = 0; - uint32_t address; - - /* Check the frame length. */ - if (length > ENET_FRAME_MAX_FRAMELEN) - { - return kStatus_ENET_TxFrameOverLen; - } - - /* Check if the transmit buffer is ready. */ - curBuffDescrip = handle->txBdCurrent[ringId]; - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) - { - return kStatus_ENET_TxFrameBusy; - } -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - bool isPtpEventMessage = false; - /* Check PTP message with the PTP header. */ - isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - /* One transmit buffer is enough for one frame. */ - if (handle->txBuffSizeAlign[ringId] >= length) - { - /* Copy data to the buffer for uDMA transfer. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - memcpy((void *)address, data, length); - -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ - DCACHE_CleanByRange(address, length); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - - /* Set data length. */ - curBuffDescrip->length = length; -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* For enable the timestamp. */ - if (isPtpEventMessage) - { - curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - else - { - curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); - - /* Increase the buffer descriptor address. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdCurrent[ringId] = handle->txBdBase[ringId]; - } - else - { - handle->txBdCurrent[ringId]++; - } - - /* Active the transmit buffer descriptor. */ - ENET_ActiveSend(base, ringId); - - return kStatus_Success; - } - else - { - /* One frame requires more than one transmit buffers. */ - do - { -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* For enable the timestamp. */ - if (isPtpEventMessage) - { - curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - else - { - curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - /* Increase the buffer descriptor address. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdCurrent[ringId] = handle->txBdBase[ringId]; - } - else - { - handle->txBdCurrent[ringId]++; - } - /* update the size left to be transmit. */ - sizeleft = length - len; -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - if (sizeleft > handle->txBuffSizeAlign[ringId]) - { - /* Data copy. */ - memcpy((void*)address, data + len, handle->txBuffSizeAlign[ringId]); -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ - DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - /* Data length update. */ - curBuffDescrip->length = handle->txBuffSizeAlign[ringId]; - len += handle->txBuffSizeAlign[ringId]; - /* Sets the control flag. */ - curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; - - /* Active the transmit buffer descriptor*/ - ENET_ActiveSend(base, ringId); - } - else - { - - memcpy((void *)address, data + len, sizeleft); -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ - DCACHE_CleanByRange(address, sizeleft); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - curBuffDescrip->length = sizeleft; - /* Set Last buffer wrap flag. */ - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; - - /* Active the transmit buffer descriptor. */ - ENET_ActiveSend(base, ringId); - - return kStatus_Success; - } - - /* Get the current buffer descriptor address. */ - curBuffDescrip = handle->txBdCurrent[ringId]; - } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); - - return kStatus_ENET_TxFrameBusy; - } -} -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - -void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address) -{ - assert(address); - - uint32_t crc = 0xFFFFFFFFU; - uint32_t count1 = 0; - uint32_t count2 = 0; - - /* Calculates the CRC-32 polynomial on the multicast group address. */ - for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) - { - uint8_t c = address[count1]; - for (count2 = 0; count2 < 0x08U; count2++) - { - if ((c ^ crc) & 1U) - { - crc >>= 1U; - c >>= 1U; - crc ^= 0xEDB88320U; - } - else - { - crc >>= 1U; - c >>= 1U; - } - } - } - - /* Enable a multicast group address. */ - if (!((crc >> 0x1FU) & 1U)) - { - base->GALR |= 1U << ((crc >> 0x1AU) & 0x1FU); - } - else - { - base->GAUR |= 1U << ((crc >> 0x1AU) & 0x1FU); - } -} - -void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address) -{ - assert(address); - - uint32_t crc = 0xFFFFFFFFU; - uint32_t count1 = 0; - uint32_t count2 = 0; - - /* Calculates the CRC-32 polynomial on the multicast group address. */ - for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) - { - uint8_t c = address[count1]; - for (count2 = 0; count2 < 0x08U; count2++) - { - if ((c ^ crc) & 1U) - { - crc >>= 1U; - c >>= 1U; - crc ^= 0xEDB88320U; - } - else - { - crc >>= 1U; - c >>= 1U; - } - } - } - - /* Set the hash table. */ - if (!((crc >> 0x1FU) & 1U)) - { - base->GALR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); - } - else - { - base->GAUR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); - } -} - -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE -status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) -{ - assert(handle); - assert(eErrorStatic); - - uint16_t control = 0; - uint16_t controlExt = 0; - - do - { - /* Get the current dirty transmit buffer descriptor. */ - control = handle->txBdDirtyStatic[0]->control; - controlExt = handle->txBdDirtyStatic[0]->controlExtend0; - - /* Get the control status data, If the buffer descriptor has not been processed break out. */ - if (control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) - { - return kStatus_ENET_TxFrameBusy; - } - /* Increase the transmit dirty static pointer. */ - if (handle->txBdDirtyStatic[0]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdDirtyStatic[0] = handle->txBdBase[0]; - } - else - { - handle->txBdDirtyStatic[0]++; - } - - /* If the transmit buffer descriptor is ready and the last buffer descriptor, store packet statistic. */ - if (control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) - { - if (controlExt & ENET_BUFFDESCRIPTOR_TX_ERR_MASK) - { - /* Transmit error. */ - eErrorStatic->statsTxErr++; - } - if (controlExt & ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK) - { - /* Transmit excess collision error. */ - eErrorStatic->statsTxExcessCollisionErr++; - } - if (controlExt & ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK) - { - /* Transmit late collision error. */ - eErrorStatic->statsTxLateCollisionErr++; - } - if (controlExt & ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK) - { - /* Transmit under flow error. */ - eErrorStatic->statsTxUnderFlowErr++; - } - if (controlExt & ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK) - { - /* Transmit over flow error. */ - eErrorStatic->statsTxOverFlowErr++; - } - return kStatus_Success; - } - - } while (handle->txBdDirtyStatic[0] != handle->txBdCurrent[0]); - - return kStatus_ENET_TxFrameFail; -} - -#if FSL_FEATURE_ENET_QUEUE > 1 -status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, - uint32_t ringId) -{ - assert(handle); - assert(eErrorStatic); - assert(ringId < FSL_FEATURE_ENET_QUEUE); - - uint16_t control = 0; - uint16_t controlExt = 0; - - do - { - /* Get the current dirty transmit buffer descriptor. */ - control = handle->txBdDirtyStatic[ringId]->control; - controlExt = handle->txBdDirtyStatic[ringId]->controlExtend0; - /* Get the control status data, If the buffer descriptor has not been processed break out. */ - if (control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) - { - return kStatus_ENET_TxFrameBusy; - } - /* Increase the transmit dirty static pointer. */ - if (handle->txBdDirtyStatic[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdDirtyStatic[ringId] = handle->txBdBase[ringId]; - } - else - { - handle->txBdDirtyStatic[ringId]++; - } - - /* If the transmit buffer descriptor is ready and the last buffer descriptor, store packet statistic. */ - if (control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) - { - if (controlExt & ENET_BUFFDESCRIPTOR_TX_ERR_MASK) - { - /* Transmit error. */ - eErrorStatic->statsTxErr++; - } - if (controlExt & ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK) - { - /* Transmit excess collision error. */ - eErrorStatic->statsTxExcessCollisionErr++; - } - if (controlExt & ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK) - { - /* Transmit late collision error. */ - eErrorStatic->statsTxLateCollisionErr++; - } - if (controlExt & ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK) - { - /* Transmit under flow error. */ - eErrorStatic->statsTxUnderFlowErr++; - } - if (controlExt & ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK) - { - /* Transmit over flow error. */ - eErrorStatic->statsTxOverFlowErr++; - } - return kStatus_Success; - } - - } while (handle->txBdDirtyStatic[ringId] != handle->txBdCurrent[ringId]); - - return kStatus_ENET_TxFrameFail; -} -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - -static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled) -{ - assert(data); - if (!isFastEnabled) - { - assert(ptpTsData); - } - - bool isPtpMsg = false; - const uint8_t *buffer = data; - uint16_t ptpType; - - /* Check for VLAN frame. - * Add Double vlan tag check for receiving extended QIN vlan frame. */ - if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == (ENET_HTONS(ENET_8021QVLAN) -#if defined(FSL_FEATUR_ENET_HAS_AVB) && FSL_FEATURE_HAS_AVB - || ENET_HTONS(ENET_8021QSVLAN) -#endif /* FSL_FEATURE_ENET_HAS_AVB */ - )) - { - buffer += ENET_FRAME_VLAN_TAGLEN; -#if defined(FSL_FEATUR_ENET_HAS_AVB) && FSL_FEATURE_HAS_AVB - if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN) - { - buffer += ENET_FRAME_VLAN_TAGLEN; - } -#endif /* FSL_FEATURE_ENET_HAS_AVB */ - } - - ptpType = *(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET); - switch (ENET_HTONS(ptpType)) - { /* Ethernet layer 2. */ - case ENET_ETHERNETL2: - if ((*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) & 0x0F) <= kENET_PtpEventMsgType) - { - isPtpMsg = true; - if (!isFastEnabled) - { - /* It's a ptpv2 message and store the ptp header information. */ - ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_VERSION_OFFSET)) & 0x0F; - ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET)) & 0x0F; - ptpTsData->sequenceId = ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET)); - memcpy((void *)&ptpTsData->sourcePortId[0], (void *)(buffer + ENET_PTP1588_ETHL2_CLOCKID_OFFSET), - kENET_PtpSrcPortIdLen); - } - } - break; - /* IPV4. */ - case ENET_IPV4: - if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV4VERSION) - { - if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && - (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) - { - /* Set the PTP message flag. */ - isPtpMsg = true; - if (!isFastEnabled) - { - /* It's a IPV4 ptp message and store the ptp header information. */ - ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_VERSION_OFFSET)) & 0x0F; - ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET)) & 0x0F; - ptpTsData->sequenceId = - ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET)); - memcpy((void *)&ptpTsData->sourcePortId[0], - (void *)(buffer + ENET_PTP1588_IPV4_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); - } - } - } - break; - /* IPV6. */ - case ENET_IPV6: - if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV6VERSION) - { - if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && - (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) - { - /* Set the PTP message flag. */ - isPtpMsg = true; - if (!isFastEnabled) - { - /* It's a IPV6 ptp message and store the ptp header information. */ - ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_VERSION_OFFSET)) & 0x0F; - ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET)) & 0x0F; - ptpTsData->sequenceId = - ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET)); - memcpy((void *)&ptpTsData->sourcePortId[0], - (void *)(buffer + ENET_PTP1588_IPV6_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); - } - } - } - break; - default: - break; - } - return isPtpMsg; -} - -void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig) -{ - assert(handle); - assert(ptpConfig); - uint8_t count; - - uint32_t instance = ENET_GetInstance(base); - uint32_t mask = kENET_TxBufferInterrupt; -#if FSL_FEATURE_ENET_QUEUE > 1 - mask |= kENET_TxBuffer1Interrupt | kENET_TxBuffer2Interrupt; -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - - /* Start the 1588 timer. */ - ENET_Ptp1588StartTimer(base, ptpConfig->ptp1588ClockSrc_Hz); - - for (count = 0; count < handle->ringNum; count++) - { - handle->txBdDirtyTime[count] = handle->txBdBase[count]; - handle->txBdDirtyStatic[count] = handle->txBdBase[count]; - } - - /* Setting the receive and transmit state for transaction. */ - handle->rxPtpTsDataRing.ptpTsData = ptpConfig->rxPtpTsData; - handle->rxPtpTsDataRing.size = ptpConfig->ptpTsRxBuffNum; - handle->rxPtpTsDataRing.front = 0; - handle->rxPtpTsDataRing.end = 0; - handle->txPtpTsDataRing.ptpTsData = ptpConfig->txPtpTsData; - handle->txPtpTsDataRing.size = ptpConfig->ptpTsTxBuffNum; - handle->txPtpTsDataRing.front = 0; - handle->txPtpTsDataRing.end = 0; - handle->msTimerSecond = 0; - - /* Set the IRQ handler when the interrupt is enabled. */ - s_enetTxIsr = ENET_TransmitIRQHandler; - s_enetTsIsr = ENET_Ptp1588TimerIRQHandler; - - /* Enables the time stamp interrupt and transmit frame interrupt to - * handle the time-stamp . */ - ENET_EnableInterrupts(base, (ENET_TS_INTERRUPT | ENET_TX_INTERRUPT)); - ENET_DisableInterrupts(base, mask); - - EnableIRQ(s_enetTsIrqId[instance]); - EnableIRQ(s_enetTxIrqId[instance]); -} - -void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc) -{ - /* Restart PTP 1588 timer, master clock. */ - base->ATCR = ENET_ATCR_RESTART_MASK; - - /* Initializes PTP 1588 timer. */ - base->ATINC = ENET_ATINC_INC(ENET_NANOSECOND_ONE_SECOND / ptpClkSrc); - base->ATPER = ENET_NANOSECOND_ONE_SECOND; - /* Sets periodical event and the event signal output assertion and Actives PTP 1588 timer. */ - base->ATCR = ENET_ATCR_PEREN_MASK | ENET_ATCR_PINPER_MASK | ENET_ATCR_EN_MASK; -} - -void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) -{ - assert(handle); - assert(ptpTime); - uint16_t count = ENET_1588TIME_DELAY_COUNT; - uint32_t primask; - - /* Disables the interrupt. */ - primask = DisableGlobalIRQ(); - - /* Get the current PTP time. */ - ptpTime->second = handle->msTimerSecond; - /* Get the nanosecond from the master timer. */ - base->ATCR |= ENET_ATCR_CAPTURE_MASK; - /* Add at least six clock cycle delay to get accurate time. - It's the requirement when the 1588 clock source is slower - than the register clock. - */ - while (count--) - { - __NOP(); - } - /* Get the captured time. */ - ptpTime->nanosecond = base->ATVR; - - /* Enables the interrupt. */ - EnableGlobalIRQ(primask); -} - -void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) -{ - assert(handle); - assert(ptpTime); - - uint32_t primask; - - /* Disables the interrupt. */ - primask = DisableGlobalIRQ(); - - /* Sets PTP timer. */ - handle->msTimerSecond = ptpTime->second; - base->ATVR = ptpTime->nanosecond; - - /* Enables the interrupt. */ - EnableGlobalIRQ(primask); -} - -void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod) -{ - /* Set correction for PTP timer increment. */ - base->ATINC = (base->ATINC & ~ENET_ATINC_INC_CORR_MASK) | (corrIncrease << ENET_ATINC_INC_CORR_SHIFT); - /* Set correction for PTP timer period. */ - base->ATCOR = (base->ATCOR & ~ENET_ATCOR_COR_MASK) | (corrPeriod << ENET_ATCOR_COR_SHIFT); -} - -static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData) -{ - assert(ptpTsDataRing); - assert(ptpTsDataRing->ptpTsData); - assert(ptpTimeData); - - uint16_t usedBuffer = 0; - - /* Check if the buffers ring is full. */ - if (ptpTsDataRing->end >= ptpTsDataRing->front) - { - usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; - } - else - { - usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); - } - - if (usedBuffer == ptpTsDataRing->size) - { - return kStatus_ENET_PtpTsRingFull; - } - - /* Copy the new data into the buffer. */ - memcpy((ptpTsDataRing->ptpTsData + ptpTsDataRing->end), ptpTimeData, sizeof(enet_ptp_time_data_t)); - - /* Increase the buffer pointer to the next empty one. */ - ptpTsDataRing->end = (ptpTsDataRing->end + 1) % ptpTsDataRing->size; - - return kStatus_Success; -} - -static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata) -{ - assert(ptpTsDataRing); - assert(ptpTsDataRing->ptpTsData); - assert(ptpTimedata); - - uint32_t index; - uint32_t size; - uint16_t usedBuffer = 0; - - /* Check the PTP 1588 timestamp ring. */ - if (ptpTsDataRing->front == ptpTsDataRing->end) - { - return kStatus_ENET_PtpTsRingEmpty; - } - - /* Search the element in the ring buffer */ - index = ptpTsDataRing->front; - size = ptpTsDataRing->size; - while (index != ptpTsDataRing->end) - { - if (((ptpTsDataRing->ptpTsData + index)->sequenceId == ptpTimedata->sequenceId) && - (!memcmp(((void *)&(ptpTsDataRing->ptpTsData + index)->sourcePortId[0]), - (void *)&ptpTimedata->sourcePortId[0], kENET_PtpSrcPortIdLen)) && - ((ptpTsDataRing->ptpTsData + index)->version == ptpTimedata->version) && - ((ptpTsDataRing->ptpTsData + index)->messageType == ptpTimedata->messageType)) - { - break; - } - - /* Increase the ptp ring index. */ - index = (index + 1) % size; - } - - if (index == ptpTsDataRing->end) - { - /* Check if buffers is full. */ - if (ptpTsDataRing->end >= ptpTsDataRing->front) - { - usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; - } - else - { - usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); - } - - if (usedBuffer == ptpTsDataRing->size) - { /* Drop one in the front. */ - ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size; - } - return kStatus_ENET_PtpTsRingFull; - } - - /* Get the right timestamp of the required ptp messag. */ - ptpTimedata->timeStamp.second = (ptpTsDataRing->ptpTsData + index)->timeStamp.second; - ptpTimedata->timeStamp.nanosecond = (ptpTsDataRing->ptpTsData + index)->timeStamp.nanosecond; - - /* Increase the index. */ - ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size; - - return kStatus_Success; -} - -static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) -{ - assert(handle); - assert(ptpTimeData); - - bool ptpTimerWrap = false; - enet_ptp_time_t ptpTimer; - uint32_t primask; - - /* Disables the interrupt. */ - primask = DisableGlobalIRQ(); - - /* Get current PTP timer nanosecond value. */ - ENET_Ptp1588GetTimer(base, handle, &ptpTimer); - - /* Get PTP timer wrap event. */ - ptpTimerWrap = base->EIR & kENET_TsTimerInterrupt; - - /* Get transmit time stamp second. */ - if ((ptpTimer.nanosecond > ptpTimeData->timeStamp.nanosecond) || - ((ptpTimer.nanosecond < ptpTimeData->timeStamp.nanosecond) && ptpTimerWrap)) - { - ptpTimeData->timeStamp.second = handle->msTimerSecond; - } - else - { - ptpTimeData->timeStamp.second = handle->msTimerSecond - 1; - } - /* Enable the interrupt. */ - EnableGlobalIRQ(primask); - - /* Store the timestamp to the receive time stamp ring. */ - /* Check if the buffers ring is full. */ - return ENET_Ptp1588UpdateTimeRing(&handle->rxPtpTsDataRing, ptpTimeData); -} - -static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) -{ - assert(handle); - - uint32_t primask; - bool ptpTimerWrap; - bool isPtpEventMessage = false; - enet_ptp_time_data_t ptpTimeData; - volatile enet_tx_bd_struct_t *curBuffDescrip = handle->txBdDirtyTime[ringId]; - uint32_t address; - - /* Get the control status data, If the buffer descriptor has not been processed break out. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) - { - return kStatus_ENET_TxFrameBusy; - } - - /* Parse the PTP message. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimeData, false); - if (isPtpEventMessage) - { - /* Only store tx timestamp for ptp event message. */ - do - { - /* Increase current buffer descriptor to the next one. */ - if (handle->txBdDirtyTime[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdDirtyTime[ringId] = handle->txBdBase[ringId]; - } - else - { - handle->txBdDirtyTime[ringId]++; - } - - /* Do time stamp check on the last buffer descriptor of the frame. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) - { - /* Disables the interrupt. */ - primask = DisableGlobalIRQ(); - - /* Get current PTP timer nanosecond value. */ - ENET_Ptp1588GetTimer(base, handle, &ptpTimeData.timeStamp); - - /* Get PTP timer wrap event. */ - ptpTimerWrap = base->EIR & kENET_TsTimerInterrupt; - - /* Get transmit time stamp second. */ - if ((ptpTimeData.timeStamp.nanosecond > curBuffDescrip->timestamp) || - ((ptpTimeData.timeStamp.nanosecond < curBuffDescrip->timestamp) && ptpTimerWrap)) - { - ptpTimeData.timeStamp.second = handle->msTimerSecond; - } - else - { - ptpTimeData.timeStamp.second = handle->msTimerSecond - 1; - } - - /* Save transmit time stamp nanosecond. */ - ptpTimeData.timeStamp.nanosecond = curBuffDescrip->timestamp; - - /* Enable the interrupt. */ - EnableGlobalIRQ(primask); - - /* Store the timestamp to the transmit timestamp ring. */ - return ENET_Ptp1588UpdateTimeRing(&handle->txPtpTsDataRing, &ptpTimeData); - } - - /* Get the current transmit buffer descriptor. */ - curBuffDescrip = handle->txBdDirtyTime[ringId]; - - /* Get the control status data, If the buffer descriptor has not been processed break out. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) - { - return kStatus_ENET_TxFrameBusy; - } - } while (handle->txBdDirtyTime[ringId] != handle->txBdCurrent[ringId]); - return kStatus_ENET_TxFrameFail; - } - else - { - /* Only increase current buffer descriptor to the next one. */ - if (handle->txBdDirtyTime[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdDirtyTime[ringId] = handle->txBdBase[ringId]; - } - else - { - handle->txBdDirtyTime[ringId]++; - } - } - return kStatus_Success; -} - -status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) -{ - assert(handle); - assert(ptpTimeData); - - return ENET_Ptp1588SearchTimeRing(&handle->txPtpTsDataRing, ptpTimeData); -} - -status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) -{ - assert(handle); - assert(ptpTimeData); - - return ENET_Ptp1588SearchTimeRing(&handle->rxPtpTsDataRing, ptpTimeData); -} - -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB -void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config) -{ - assert(config); - - uint8_t count = 0; - - for (count = 0; count < FSL_FEATURE_ENET_QUEUE - 1; count++) - { - /* Set the AVB receive ring classification match when the match is not 0. */ - if (config->rxClassifyMatch[count]) - { - base->RCMR[count] = (config->rxClassifyMatch[count] & 0xFFFF) | ENET_RCMR_MATCHEN_MASK; - } - /* Set the dma controller for the extended ring. */ - base->DMACFG[count] |= ENET_DMACFG_IDLE_SLOPE(config->idleSlope[count]); - } - - /* Shall use the credit-based scheme for avb. */ - base->QOS &= ~ENET_QOS_TX_SCHEME_MASK; - base->QOS |= ENET_QOS_RX_FLUSH0_MASK; -} -#endif /* FSL_FETAURE_ENET_HAS_AVB */ -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - -#if FSL_FEATURE_ENET_QUEUE > 1 -void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) -#else -void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle) -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ -{ - assert(handle); - uint32_t mask = kENET_TxBufferInterrupt | kENET_TxFrameInterrupt; -#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) || (FSL_FEATURE_ENET_QUEUE > 1) - uint32_t index = 0; -#endif /* ENET_ENHANCEDBUFFERDESCRIPTORMODE || (FSL_FEATURE_ENET_QUEUE > 1) */ - -/* Check if the transmit interrupt happen. */ -#if FSL_FEATURE_ENET_QUEUE > 1 - switch (ringId) - { - case kENET_Ring1: - mask = (kENET_TxFrame1Interrupt | kENET_TxBuffer1Interrupt); - break; - case kENET_Ring2: - mask = (kENET_TxFrame2Interrupt | kENET_TxBuffer2Interrupt); - break; - default: - break; - } - index = ringId; -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - - while (mask & base->EIR) - { -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - if (base->EIR & kENET_TxFrameInterrupt) - { - /* Store the transmit timestamp from the buffer descriptor should be done here. */ - ENET_StoreTxFrameTime(base, handle, index); - } -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - /* Clear the transmit interrupt event. */ - base->EIR = mask; - - /* Callback function. */ - if (handle->callback) - { -#if FSL_FEATURE_ENET_QUEUE > 1 - handle->callback(base, handle, index, kENET_TxEvent, handle->userData); -#else - handle->callback(base, handle, kENET_TxEvent, handle->userData); -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - } - } -} - -#if FSL_FEATURE_ENET_QUEUE > 1 -void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) -#else -void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle) -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ -{ - assert(handle); - uint32_t mask = kENET_RxFrameInterrupt | kENET_RxBufferInterrupt; - -/* Check if the receive interrupt happen. */ -#if FSL_FEATURE_ENET_QUEUE > 1 - switch (ringId) - { - case kENET_Ring1: - mask = (kENET_RxFrame1Interrupt | kENET_RxBuffer1Interrupt); - break; - case kENET_Ring2: - mask = (kENET_RxFrame2Interrupt | kENET_RxBuffer2Interrupt); - break; - default: - break; - } -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - - while (mask & base->EIR) - { - /* Clear the transmit interrupt event. */ - base->EIR = mask; - - /* Callback function. */ - if (handle->callback) - { -#if FSL_FEATURE_ENET_QUEUE > 1 - handle->callback(base, handle, ringId, kENET_RxEvent, handle->userData); -#else - handle->callback(base, handle, kENET_RxEvent, handle->userData); -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - } - } -} - -void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle) -{ - assert(handle); - - uint32_t errMask = kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_PayloadRxInterrupt | - kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt; - - /* Check if the error interrupt happen. */ - if (kENET_WakeupInterrupt & base->EIR) - { - /* Clear the wakeup interrupt. */ - base->EIR = kENET_WakeupInterrupt; - /* wake up and enter the normal mode. */ - ENET_EnableSleepMode(base, false); - /* Callback function. */ - if (handle->callback) - { -#if FSL_FEATURE_ENET_QUEUE > 1 - handle->callback(base, handle, 0, kENET_WakeUpEvent, handle->userData); -#else - handle->callback(base, handle, kENET_WakeUpEvent, handle->userData); -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - } - } - else - { - /* Clear the error interrupt event status. */ - errMask &= base->EIR; - base->EIR = errMask; - /* Callback function. */ - if (handle->callback) - { -#if FSL_FEATURE_ENET_QUEUE > 1 - handle->callback(base, handle, 0, kENET_ErrEvent, handle->userData); -#else - handle->callback(base, handle, kENET_ErrEvent, handle->userData); -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - } - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE -void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle) -{ - assert(handle); - - /* Check if the PTP time stamp interrupt happen. */ - if (kENET_TsTimerInterrupt & base->EIR) - { - /* Clear the time stamp interrupt. */ - base->EIR = kENET_TsTimerInterrupt; - - /* Increase timer second counter. */ - handle->msTimerSecond++; - - /* Callback function. */ - if (handle->callback) - { -#if FSL_FEATURE_ENET_QUEUE > 1 - handle->callback(base, handle, 0, kENET_TimeStampEvent, handle->userData); -#else - handle->callback(base, handle, kENET_TimeStampEvent, handle->userData); -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - } - } - else - { - /* Clear the time stamp interrupt. */ - base->EIR = kENET_TsAvailInterrupt; - /* Callback function. */ - if (handle->callback) - { -#if FSL_FEATURE_ENET_QUEUE > 1 - handle->callback(base, handle, 0, kENET_TimeStampAvailEvent, handle->userData); -#else - handle->callback(base, handle, kENET_TimeStampAvailEvent, handle->userData); -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - } - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - -void ENET_CommonFrame0IRQHandler(ENET_Type *base) -{ - uint32_t event = base->EIR; - uint32_t instance = ENET_GetInstance(base); - - if (event & (kENET_TxBufferInterrupt | kENET_TxFrameInterrupt)) - { -#if FSL_FEATURE_ENET_QUEUE > 1 - s_enetTxIsr(base, s_ENETHandle[instance], 0); -#else - s_enetTxIsr(base, s_ENETHandle[instance]); -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - } - - if (event & (kENET_RxBufferInterrupt | kENET_RxFrameInterrupt)) - { -#if FSL_FEATURE_ENET_QUEUE > 1 - s_enetRxIsr(base, s_ENETHandle[instance], 0); -#else - s_enetRxIsr(base, s_ENETHandle[instance]); -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - } - - if (event & ENET_TS_INTERRUPT) - { - s_enetTsIsr(base, s_ENETHandle[instance]); - } - if (event & ENET_ERR_INTERRUPT) - { - s_enetErrIsr(base, s_ENETHandle[instance]); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#if FSL_FEATURE_ENET_QUEUE > 1 -void ENET_CommonFrame1IRQHandler(ENET_Type *base) -{ - uint32_t event = base->EIR; - uint32_t instance = ENET_GetInstance(base); - - if (event & (kENET_TxBuffer1Interrupt | kENET_TxFrame1Interrupt)) - { - s_enetTxIsr(base, s_ENETHandle[instance], 1); - } - - if (event & (kENET_RxBuffer1Interrupt | kENET_RxFrame1Interrupt)) - { - s_enetRxIsr(base, s_ENETHandle[instance], 1); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void ENET_CommonFrame2IRQHandler(ENET_Type *base) -{ - uint32_t event = base->EIR; - uint32_t instance = ENET_GetInstance(base); - - if (event & (kENET_TxBuffer2Interrupt | kENET_TxFrame2Interrupt)) - { - s_enetTxIsr(base, s_ENETHandle[instance], 2); - } - - if (event & (kENET_RxBuffer2Interrupt | kENET_RxFrame2Interrupt)) - { - s_enetRxIsr(base, s_ENETHandle[instance], 2); - } - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - -#if defined(ENET) -void ENET_Transmit_IRQHandler(void) -{ - s_enetTxIsr(ENET, s_ENETHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void ENET_Receive_IRQHandler(void) -{ - s_enetRxIsr(ENET, s_ENETHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void ENET_Error_IRQHandler(void) -{ - s_enetErrIsr(ENET, s_ENETHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void ENET_1588_Timer_IRQHandler(void) -{ - s_enetTsIsr(ENET, s_ENETHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void ENET_DriverIRQHandler(void) -{ - ENET_CommonFrame0IRQHandler(ENET); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#endif - - -#if defined(ENET1) -void ENET1_DriverIRQHandler(void) -{ - ENET_CommonFrame0IRQHandler(ENET1); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(ENET2) -void ENET2_DriverIRQHandler(void) -{ - ENET_CommonFrame0IRQHandler(ENET2); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - - -#if defined(CONNECTIVITY__ENET0) -void CONNECTIVITY_ENET0_FRAME0_EVENT_INT_DriverIRQHandler(void) -{ - ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET0); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#if FSL_FEATURE_ENET_QUEUE > 1 -void CONNECTIVITY_ENET0_FRAME1_INT_DriverIRQHandler(void) -{ - ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET0); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -void CONNECTIVITY_ENET0_FRAME2_INT_DriverIRQHandler(void) -{ - ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET0); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif -#if defined(CONNECTIVITY__ENET1) -void CONNECTIVITY_ENET1_FRAME0_EVENT_INT_DriverIRQHandler(void) -{ - ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET1); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#if FSL_FEATURE_ENET_QUEUE > 1 -void CONNECTIVITY_ENET1_FRAME1_INT_DriverIRQHandler(void) -{ - ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET1); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -void CONNECTIVITY_ENET1_FRAME2_INT_DriverIRQHandler(void) -{ - ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET1); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif - diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.h deleted file mode 100644 index 3538bca2f2..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.h +++ /dev/null @@ -1,1635 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_ENET_H_ -#define _FSL_ENET_H_ - -#include "fsl_common.h" -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET -#include "fsl_memory.h" -#endif -/*! - * @addtogroup enet - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines the driver version. */ -#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) /*!< Version 2.2.3. */ -/*@}*/ - -/*! @name ENET DESCRIPTOR QUEUE */ -/*@{*/ -/*! @brief Defines the queue number. */ -#ifndef FSL_FEATURE_ENET_QUEUE -#define FSL_FEATURE_ENET_QUEUE 1 /* Singal queue for previous IP. */ -#endif -/*@}*/ - -/*! @name Control and status region bit masks of the receive buffer descriptor. */ -/*@{*/ -#define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK 0x8000U /*!< Empty bit mask. */ -#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK 0x4000U /*!< Software owner one mask. */ -#define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK 0x2000U /*!< Next buffer descriptor is the start address. */ -#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask 0x1000U /*!< Software owner two mask. */ -#define ENET_BUFFDESCRIPTOR_RX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ -#define ENET_BUFFDESCRIPTOR_RX_MISS_MASK 0x0100U /*!< Received because of the promiscuous mode. */ -#define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK 0x0080U /*!< Broadcast packet mask. */ -#define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK 0x0040U /*!< Multicast packet mask. */ -#define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x0020U /*!< Length violation mask. */ -#define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK 0x0010U /*!< Non-octet aligned frame mask. */ -#define ENET_BUFFDESCRIPTOR_RX_CRC_MASK 0x0004U /*!< CRC error mask. */ -#define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK 0x0002U /*!< FIFO overrun mask. */ -#define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK 0x0001U /*!< Frame is truncated mask. */ -/*@}*/ - -/*! @name Control and status bit masks of the transmit buffer descriptor. */ -/*@{*/ -#define ENET_BUFFDESCRIPTOR_TX_READY_MASK 0x8000U /*!< Ready bit mask. */ -#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x4000U /*!< Software owner one mask. */ -#define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK 0x2000U /*!< Wrap buffer descriptor mask. */ -#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x1000U /*!< Software owner two mask. */ -#define ENET_BUFFDESCRIPTOR_TX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ -#define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK 0x0400U /*!< Transmit CRC mask. */ -/*@}*/ - -/* Extended control regions for enhanced buffer descriptors. */ -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE -/*! @name First extended control region bit masks of the receive buffer descriptor. */ -/*@{*/ -#define ENET_BUFFDESCRIPTOR_RX_IPV4_MASK 0x0001U /*!< Ipv4 frame mask. */ -#define ENET_BUFFDESCRIPTOR_RX_IPV6_MASK 0x0002U /*!< Ipv6 frame mask. */ -#define ENET_BUFFDESCRIPTOR_RX_VLAN_MASK 0x0004U /*!< VLAN frame mask. */ -#define ENET_BUFFDESCRIPTOR_RX_PROTOCOLCHECKSUM_MASK 0x0010U /*!< Protocol checksum error mask. */ -#define ENET_BUFFDESCRIPTOR_RX_IPHEADCHECKSUM_MASK 0x0020U /*!< IP header checksum error mask. */ -/*@}*/ - -/*! @name Second extended control region bit masks of the receive buffer descriptor. */ -/*@{*/ -#define ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK 0x0080U /*!< BD interrupt mask. */ -#define ENET_BUFFDESCRIPTOR_RX_UNICAST_MASK 0x0100U /*!< Unicast frame mask. */ -#define ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK 0x0200U /*!< BD collision mask. */ -#define ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK 0x0400U /*!< PHY error mask. */ -#define ENET_BUFFDESCRIPTOR_RX_MACERR_MASK 0x8000U /*!< Mac error mask. */ -/*@}*/ - -/*! @name First extended control region bit masks of the transmit buffer descriptor. */ -/*@{*/ -#define ENET_BUFFDESCRIPTOR_TX_ERR_MASK 0x8000U /*!< Transmit error mask. */ -#define ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK 0x2000U /*!< Underflow error mask. */ -#define ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK 0x1000U /*!< Excess collision error mask. */ -#define ENET_BUFFDESCRIPTOR_TX_FRAMEERR_MASK 0x0800U /*!< Frame error mask. */ -#define ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK 0x0400U /*!< Late collision error mask. */ -#define ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK 0x0200U /*!< Overflow error mask. */ -#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMPERR_MASK 0x0100U /*!< Timestamp error mask. */ -/*@}*/ - -/*! @name Second extended control region bit masks of the transmit buffer descriptor. */ -/*@{*/ -#define ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK 0x4000U /*!< Interrupt mask. */ -#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK 0x2000U /*!< Timestamp flag mask. */ -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB -#define ENET_BUFFDESCRIPTOR_TX_USETXLAUNCHTIME_MASK 0x0100U /*!< Use the transmit launch time. */ -#define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK 0x00F0U /*!< Frame type mask. */ -#define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT 4U /*!< Frame type shift. */ -#define ENET_BD_FTYPE(n) ((n << ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT) & ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK) -#endif /* FSL_FEATURE_ENET_HAS_AVB */ -/*@}*/ -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - -/*! @brief Defines the receive error status flag mask. */ -#define ENET_BUFFDESCRIPTOR_RX_ERR_MASK \ - (ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \ - ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK) -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE -#define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \ - (ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) -#endif - -/*! @name Defines some Ethernet parameters. */ -/*@{*/ -#define ENET_FRAME_MAX_FRAMELEN 1518U /*!< Default maximum Ethernet frame size. */ - -#define ENET_FIFO_MIN_RX_FULL 5U /*!< ENET minimum receive FIFO full. */ -#define ENET_RX_MIN_BUFFERSIZE 256U /*!< ENET minimum buffer size. */ -#define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT) -#if FSL_FEATURE_ENET_QUEUE > 1 -#define ENET_TX_INTERRUPT \ - (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt | kENET_TxFrame1Interrupt | kENET_TxBuffer1Interrupt | \ - kENET_TxFrame2Interrupt | kENET_TxBuffer2Interrupt) -#define ENET_RX_INTERRUPT \ - (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt | kENET_RxFrame1Interrupt | kENET_RxBuffer1Interrupt | \ - kENET_RxFrame2Interrupt | kENET_RxBuffer2Interrupt) -#else -#define ENET_TX_INTERRUPT (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt) -#define ENET_RX_INTERRUPT (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt) -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ -#define ENET_TS_INTERRUPT (kENET_TsTimerInterrupt | kENET_TsAvailInterrupt) -#define ENET_ERR_INTERRUPT \ - (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_LateCollisionInterrupt | \ - kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt) -#define ENET_ERR_INTERRUPT \ - (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_LateCollisionInterrupt | \ - kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt) -/*@}*/ - -/*! @brief Defines the status return codes for transaction. */ -enum _enet_status -{ - kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 0U), /*!< A frame received but data error happen. */ - kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 1U), /*!< Failed to receive a frame. */ - kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 2U), /*!< No frame arrive. */ - kStatus_ENET_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET, 3U), /*!< Tx frame over length. */ - kStatus_ENET_TxFrameBusy = MAKE_STATUS(kStatusGroup_ENET, 4U), /*!< Tx buffer descriptors are under process. */ - kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 5U) /*!< Transmit frame fail. */ -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - , - kStatus_ENET_PtpTsRingFull = MAKE_STATUS(kStatusGroup_ENET, 6U), /*!< Timestamp ring full. */ - kStatus_ENET_PtpTsRingEmpty = MAKE_STATUS(kStatusGroup_ENET, 7U) /*!< Timestamp ring empty. */ -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ -}; - -/*! @brief Defines the MII/RMII/RGMII mode for data interface between the MAC and the PHY. */ -typedef enum _enet_mii_mode -{ - kENET_MiiMode = 0U, /*!< MII mode for data interface. */ - kENET_RmiiMode = 1U, /*!< RMII mode for data interface. */ -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB - kENET_RgmiiMode = 2U /*!< RGMII mode for data interface. */ -#endif /* FSL_FEATURE_ENET_HAS_AVB */ -} enet_mii_mode_t; - -/*! @brief Defines the 10/100/1000 Mbps speed for the MII data interface. - * - * Notice: "kENET_MiiSpeed1000M" only supported when mii mode is "kENET_RgmiiMode". - */ -typedef enum _enet_mii_speed -{ - kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ - kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */ -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB - kENET_MiiSpeed1000M = 2U /*!< Speed 1000M bps. */ -#endif /* FSL_FEATURE_ENET_HAS_AVB */ -} enet_mii_speed_t; - -/*! @brief Defines the half or full duplex for the MII data interface. */ -typedef enum _enet_mii_duplex -{ - kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ - kENET_MiiFullDuplex /*!< Full duplex mode. */ -} enet_mii_duplex_t; - -/*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */ -typedef enum _enet_mii_write -{ - kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */ - kENET_MiiWriteValidFrame /*!< Write frame operation for a valid MII management frame. */ -} enet_mii_write_t; - -/*! @brief Defines the read operation for the MII management frame. */ -typedef enum _enet_mii_read -{ - kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */ - kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */ -} enet_mii_read_t; - -#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO -/*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */ -typedef enum _enet_mii_extend_opcode -{ - kENET_MiiAddrWrite_C45 = 0U, /*!< Address Write operation. */ - kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */ - kENET_MiiReadFrame_C45 = 3U /*!< Read frame operation for a valid MII management frame. */ -} enet_mii_extend_opcode; -#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ - -/*! @brief Defines a special configuration for ENET MAC controller. - * - * These control flags are provided for special user requirements. - * Normally, these control flags are unused for ENET initialization. - * For special requirements, set the flags to - * macSpecialConfig in the enet_config_t. - * The kENET_ControlStoreAndFwdDisable is used to disable the FIFO store - * and forward. FIFO store and forward means that the FIFO read/send is started - * when a complete frame is stored in TX/RX FIFO. If this flag is set, - * configure rxFifoFullThreshold and txFifoWatermark - * in the enet_config_t. - */ -typedef enum _enet_special_control_flag -{ - kENET_ControlFlowControlEnable = 0x0001U, /*!< Enable ENET flow control: pause frame. */ - kENET_ControlRxPayloadCheckEnable = 0x0002U, /*!< Enable ENET receive payload length check. */ - kENET_ControlRxPadRemoveEnable = 0x0004U, /*!< Padding is removed from received frames. */ - kENET_ControlRxBroadCastRejectEnable = 0x0008U, /*!< Enable broadcast frame reject. */ - kENET_ControlMacAddrInsert = 0x0010U, /*!< Enable MAC address insert. */ - kENET_ControlStoreAndFwdDisable = 0x0020U, /*!< Enable FIFO store and forward. */ - kENET_ControlSMIPreambleDisable = 0x0040U, /*!< Enable SMI preamble. */ - kENET_ControlPromiscuousEnable = 0x0080U, /*!< Enable promiscuous mode. */ - kENET_ControlMIILoopEnable = 0x0100U, /*!< Enable ENET MII loop back. */ - kENET_ControlVLANTagEnable = 0x0200U, /*!< Enable normal VLAN (single vlan tag). */ -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB - kENET_ControlSVLANEnable = 0x0400U, /*!< Enable S-VLAN. */ - kENET_ControlVLANUseSecondTag = 0x0800U /*!< Enable extracting the second vlan tag for further processing. */ -#endif /* FSL_FEATURE_ENET_HAS_AVB */ -} enet_special_control_flag_t; - -/*! @brief List of interrupts supported by the peripheral. This - * enumeration uses one-bot encoding to allow a logical OR of multiple - * members. Members usually map to interrupt enable bits in one or more - * peripheral registers. - */ -typedef enum _enet_interrupt_enable -{ - kENET_BabrInterrupt = ENET_EIR_BABR_MASK, /*!< Babbling receive error interrupt source */ - kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */ - kENET_GraceStopInterrupt = ENET_EIR_GRA_MASK, /*!< Graceful stop complete interrupt source */ - kENET_TxFrameInterrupt = ENET_EIR_TXF_MASK, /*!< TX FRAME interrupt source */ - kENET_TxBufferInterrupt = ENET_EIR_TXB_MASK, /*!< TX BUFFER interrupt source */ - kENET_RxFrameInterrupt = ENET_EIR_RXF_MASK, /*!< RX FRAME interrupt source */ - kENET_RxBufferInterrupt = ENET_EIR_RXB_MASK, /*!< RX BUFFER interrupt source */ - kENET_MiiInterrupt = ENET_EIR_MII_MASK, /*!< MII interrupt source */ - kENET_EBusERInterrupt = ENET_EIR_EBERR_MASK, /*!< Ethernet bus error interrupt source */ - kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK, /*!< Late collision interrupt source */ - kENET_RetryLimitInterrupt = ENET_EIR_RL_MASK, /*!< Collision Retry Limit interrupt source */ - kENET_UnderrunInterrupt = ENET_EIR_UN_MASK, /*!< Transmit FIFO underrun interrupt source */ - kENET_PayloadRxInterrupt = ENET_EIR_PLR_MASK, /*!< Payload Receive error interrupt source */ - kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK, /*!< WAKEUP interrupt source */ -#if FSL_FEATURE_ENET_QUEUE > 1 - kENET_RxFlush2Interrupt = ENET_EIR_RXFLUSH_2_MASK, /*!< Rx DMA ring2 flush indication. */ - kENET_RxFlush1Interrupt = ENET_EIR_RXFLUSH_1_MASK, /*!< Rx DMA ring1 flush indication. */ - kENET_RxFlush0Interrupt = ENET_EIR_RXFLUSH_0_MASK, /*!< RX DMA ring0 flush indication. */ - kENET_TxFrame2Interrupt = ENET_EIR_TXF2_MASK, /*!< Tx frame interrupt for Tx ring/class 2. */ - kENET_TxBuffer2Interrupt = ENET_EIR_TXB2_MASK, /*!< Tx buffer interrupt for Tx ring/class 2. */ - kENET_RxFrame2Interrupt = ENET_EIR_RXF2_MASK, /*!< Rx frame interrupt for Rx ring/class 2. */ - kENET_RxBuffer2Interrupt = ENET_EIR_RXB2_MASK, /*!< Rx buffer interrupt for Rx ring/class 2. */ - kENET_TxFrame1Interrupt = ENET_EIR_TXF1_MASK, /*!< Tx frame interrupt for Tx ring/class 1. */ - kENET_TxBuffer1Interrupt = ENET_EIR_TXB1_MASK, /*!< Tx buffer interrupt for Tx ring/class 1. */ - kENET_RxFrame1Interrupt = ENET_EIR_RXF1_MASK, /*!< Rx frame interrupt for Rx ring/class 1. */ - kENET_RxBuffer1Interrupt = ENET_EIR_RXB1_MASK, /*!< Rx buffer interrupt for Rx ring/class 1. */ -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK, /*!< TS AVAIL interrupt source for PTP */ - kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK /*!< TS WRAP interrupt source for PTP */ -} enet_interrupt_enable_t; - -/*! @brief Defines the common interrupt event for callback use. */ -typedef enum _enet_event -{ - kENET_RxEvent, /*!< Receive event. */ - kENET_TxEvent, /*!< Transmit event. */ - kENET_ErrEvent, /*!< Error event: BABR/BABT/EBERR/LC/RL/UN/PLR . */ - kENET_WakeUpEvent, /*!< Wake up from sleep mode event. */ - kENET_TimeStampEvent, /*!< Time stamp event. */ - kENET_TimeStampAvailEvent /*!< Time stamp available event.*/ -} enet_event_t; - -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB -/*! @brief Defines certain idle slope for bandwidth fraction. */ -typedef enum _enet_idle_slope -{ - kENET_IdleSlope1 = 1U, /*!< The bandwidth fraction is about 0.002. */ - kENET_IdleSlope2 = 2U, /*!< The bandwidth fraction is about 0.003. */ - kENET_IdleSlope4 = 4U, /*!< The bandwidth fraction is about 0.008. */ - kENET_IdleSlope8 = 8U, /*!< The bandwidth fraction is about 0.02. */ - kENET_IdleSlope16 = 16U, /*!< The bandwidth fraction is about 0.03. */ - kENET_IdleSlope32 = 32U, /*!< The bandwidth fraction is about 0.06. */ - kENET_IdleSlope64 = 64U, /*!< The bandwidth fraction is about 0.11. */ - kENET_IdleSlope128 = 128U, /*!< The bandwidth fraction is about 0.20. */ - kENET_IdleSlope256 = 256U, /*!< The bandwidth fraction is about 0.33. */ - kENET_IdleSlope384 = 384U, /*!< The bandwidth fraction is about 0.43. */ - kENET_IdleSlope512 = 512U, /*!< The bandwidth fraction is about 0.50. */ - kENET_IdleSlope640 = 640U, /*!< The bandwidth fraction is about 0.56. */ - kENET_IdleSlope768 = 768U, /*!< The bandwidth fraction is about 0.60. */ - kENET_IdleSlope896 = 896U, /*!< The bandwidth fraction is about 0.64. */ - kENET_IdleSlope1024 = 1024U, /*!< The bandwidth fraction is about 0.67. */ - kENET_IdleSlope1152 = 1152U, /*!< The bandwidth fraction is about 0.69. */ - kENET_IdleSlope1280 = 1280U, /*!< The bandwidth fraction is about 0.71. */ - kENET_IdleSlope1408 = 1408U, /*!< The bandwidth fraction is about 0.73. */ - kENET_IdleSlope1536 = 1536U /*!< The bandwidth fraction is about 0.75. */ -} enet_idle_slope_t; -#endif /* FSL_FEATURE_ENET_HAS_AVB */ - -/*! @brief Defines the transmit accelerator configuration. */ -typedef enum _enet_tx_accelerator -{ - kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */ - kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK, /*!< Insert IP header checksum. */ - kENET_TxAccelProtoCheckEnabled = ENET_TACC_PROCHK_MASK /*!< Insert protocol checksum. */ -} enet_tx_accelerator_t; - -/*! @brief Defines the receive accelerator configuration. */ -typedef enum _enet_rx_accelerator -{ - kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK, /*!< Padding removal for short IP frames. */ - kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK, /*!< Discard with wrong IP header checksum. */ - kENET_RxAccelProtoCheckEnabled = ENET_RACC_PRODIS_MASK, /*!< Discard with wrong protocol checksum. */ - kENET_RxAccelMacCheckEnabled = ENET_RACC_LINEDIS_MASK, /*!< Discard with Mac layer errors. */ - kENET_RxAccelisShift16Enabled = ENET_RACC_SHIFT16_MASK /*!< Receive FIFO shift-16. */ -} enet_rx_accelerator_t; - -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE -/*! @brief Defines the ENET PTP message related constant. */ -typedef enum _enet_ptp_event_type -{ - kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ - kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ - kENET_PtpEventPort = 319U, /*!< PTP event port number. */ - kENET_PtpGnrlPort = 320U /*!< PTP general port number. */ -} enet_ptp_event_type_t; - -/*! @brief Defines the IEEE 1588 PTP timer channel numbers. */ -typedef enum _enet_ptp_timer_channel -{ - kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */ - kENET_PtpTimerChannel2, /*!< IEEE 1588 PTP timer Channel 2. */ - kENET_PtpTimerChannel3, /*!< IEEE 1588 PTP timer Channel 3. */ - kENET_PtpTimerChannel4 /*!< IEEE 1588 PTP timer Channel 4. */ -} enet_ptp_timer_channel_t; - -/*! @brief Defines the capture or compare mode for IEEE 1588 PTP timer channels. */ -typedef enum _enet_ptp_timer_channel_mode -{ - kENET_PtpChannelDisable = 0U, /*!< Disable timer channel. */ - kENET_PtpChannelRisingCapture = 1U, /*!< Input capture on rising edge. */ - kENET_PtpChannelFallingCapture = 2U, /*!< Input capture on falling edge. */ - kENET_PtpChannelBothCapture = 3U, /*!< Input capture on both edges. */ - kENET_PtpChannelSoftCompare = 4U, /*!< Output compare software only. */ - kENET_PtpChannelToggleCompare = 5U, /*!< Toggle output on compare. */ - kENET_PtpChannelClearCompare = 6U, /*!< Clear output on compare. */ - kENET_PtpChannelSetCompare = 7U, /*!< Set output on compare. */ - kENET_PtpChannelClearCompareSetOverflow = 10U, /*!< Clear output on compare, set output on overflow. */ - kENET_PtpChannelSetCompareClearOverflow = 11U, /*!< Set output on compare, clear output on overflow. */ - kENET_PtpChannelPulseLowonCompare = 14U, /*!< Pulse output low on compare for one IEEE 1588 clock cycle. */ - kENET_PtpChannelPulseHighonCompare = 15U /*!< Pulse output high on compare for one IEEE 1588 clock cycle. */ -} enet_ptp_timer_channel_mode_t; -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - -/*! @brief Defines the receive buffer descriptor structure for the little endian system.*/ -typedef struct _enet_rx_bd_struct -{ - uint16_t length; /*!< Buffer descriptor data length. */ - uint16_t control; /*!< Buffer descriptor control and status. */ - uint8_t *buffer; /*!< Data buffer pointer. */ -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ - uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ - uint16_t payloadCheckSum; /*!< Internal payload checksum. */ - uint8_t headerLength; /*!< Header length. */ - uint8_t protocolTyte; /*!< Protocol type. */ - uint16_t reserved0; - uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ - uint32_t timestamp; /*!< Timestamp. */ - uint16_t reserved1; - uint16_t reserved2; - uint16_t reserved3; - uint16_t reserved4; -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ -} enet_rx_bd_struct_t; - -/*! @brief Defines the enhanced transmit buffer descriptor structure for the little endian system. */ -typedef struct _enet_tx_bd_struct -{ - uint16_t length; /*!< Buffer descriptor data length. */ - uint16_t control; /*!< Buffer descriptor control and status. */ - uint8_t *buffer; /*!< Data buffer pointer. */ -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ - uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB - int8_t *txLaunchTime; /*!< Transmit launch time. */ -#else - uint16_t reserved0; - uint16_t reserved1; -#endif /* FSL_FEATURE_ENET_HAS_AVB */ - uint16_t reserved2; - uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ - uint32_t timestamp; /*!< Timestamp. */ - uint16_t reserved3; - uint16_t reserved4; - uint16_t reserved5; - uint16_t reserved6; -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ -} enet_tx_bd_struct_t; - -/*! @brief Defines the ENET data error statistic structure. */ -typedef struct _enet_data_error_stats -{ - uint32_t statsRxLenGreaterErr; /*!< Receive length greater than RCR[MAX_FL]. */ - uint32_t statsRxAlignErr; /*!< Receive non-octet alignment/ */ - uint32_t statsRxFcsErr; /*!< Receive CRC error. */ - uint32_t statsRxOverRunErr; /*!< Receive over run. */ - uint32_t statsRxTruncateErr; /*!< Receive truncate. */ -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - uint32_t statsRxProtocolChecksumErr; /*!< Receive protocol checksum error. */ - uint32_t statsRxIpHeadChecksumErr; /*!< Receive IP header checksum error. */ - uint32_t statsRxMacErr; /*!< Receive Mac error. */ - uint32_t statsRxPhyErr; /*!< Receive PHY error. */ - uint32_t statsRxCollisionErr; /*!< Receive collision. */ - uint32_t statsTxErr; /*!< The error happen when transmit the frame. */ - uint32_t statsTxFrameErr; /*!< The transmit frame is error. */ - uint32_t statsTxOverFlowErr; /*!< Transmit overflow. */ - uint32_t statsTxLateCollisionErr; /*!< Transmit late collision. */ - uint32_t statsTxExcessCollisionErr; /*!< Transmit excess collision.*/ - uint32_t statsTxUnderFlowErr; /*!< Transmit under flow error. */ - uint32_t statsTxTsErr; /*!< Transmit time stamp error. */ -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ -} enet_data_error_stats_t; - -/*! @brief Defines the receive buffer descriptor configuration structure. - * - * Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements. - * 1. The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT. - * when the data buffers are in cacheable region when cache is enabled, all those size should be - * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. - * 2. The aligned transmit and receive buffer descriptor start address must be at - * least 64 bit aligned. However, it's recommended to be evenly divisible by ENET_BUFF_ALIGNMENT. - * buffer descriptors should be put in non-cacheable region when cache is enabled. - * 3. The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT. - * Receive buffers should be continuous with the total size equal to "rxBdNumber * rxBuffSizeAlign". - * Transmit buffers should be continuous with the total size equal to "txBdNumber * txBuffSizeAlign". - * when the data buffers are in cacheable region when cache is enabled, all those size should be - * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. - */ -typedef struct _enet_buffer_config -{ - uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ - uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ - uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ - uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ - volatile enet_rx_bd_struct_t - *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */ - volatile enet_tx_bd_struct_t - *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */ - uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ - uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ -} enet_buffer_config_t; - -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE -/*! @brief Defines the ENET PTP time stamp structure. */ -typedef struct _enet_ptp_time -{ - uint64_t second; /*!< Second. */ - uint32_t nanosecond; /*!< Nanosecond. */ -} enet_ptp_time_t; - -/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/ -typedef struct _enet_ptp_time_data -{ - uint8_t version; /*!< PTP version. */ - uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */ - uint16_t sequenceId; /*!< PTP sequence ID. */ - uint8_t messageType; /*!< PTP message type. */ - enet_ptp_time_t timeStamp; /*!< PTP timestamp. */ -} enet_ptp_time_data_t; - -/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/ -typedef struct _enet_ptp_time_data_ring -{ - uint32_t front; /*!< The first index of the ring. */ - uint32_t end; /*!< The end index of the ring. */ - uint32_t size; /*!< The size of the ring. */ - enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */ -} enet_ptp_time_data_ring_t; - -/*! @brief Defines the ENET PTP configuration structure. */ -typedef struct _enet_ptp_config -{ - uint8_t ptpTsRxBuffNum; /*!< Receive 1588 timestamp buffer number*/ - uint8_t ptpTsTxBuffNum; /*!< Transmit 1588 timestamp buffer number*/ - enet_ptp_time_data_t *rxPtpTsData; /*!< The start address of 1588 receive timestamp buffers */ - enet_ptp_time_data_t *txPtpTsData; /*!< The start address of 1588 transmit timestamp buffers */ - enet_ptp_timer_channel_t channel; /*!< Used for ERRATA_2579: the PTP 1588 timer channel for time interrupt. */ - uint32_t ptp1588ClockSrc_Hz; /*!< The clock source of the PTP 1588 timer. */ -} enet_ptp_config_t; -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - -#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE -/*! @brief Defines the interrupt coalescing configure structure. */ -typedef struct _enet_intcoalesce_config -{ - uint8_t txCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing frame count threshold. */ - uint16_t txCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing timer count threshold. */ - uint8_t rxCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing frame count threshold. */ - uint16_t rxCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing timer count threshold. */ -} enet_intcoalesce_config_t; -#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ - -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB -/*! @brief Defines the ENET AVB Configure structure. - * - * This is used for to configure the extended ring 1 and ring 2. - * 1. The classification match format is (CMP3 << 12) | (CMP2 << 8) | (CMP1 << 4) | CMP0. - * composed of four 3-bit compared VLAN priority field cmp0~cmp3, cm0 ~ cmp3 are used in parallel. - * - * If CMP1,2,3 are not unused, please set them to the same value as CMP0. - * 2. The idleSlope is used to calculate the Band Width fraction, BW fraction = 1 / (1 + 512/idleSlope). - * For avb configuration, the BW fraction of Class 1 and Class 2 combined must not exceed 0.75. - */ -typedef struct _enet_avb_config -{ - uint16_t rxClassifyMatch[FSL_FEATURE_ENET_QUEUE - 1]; /*!< The classification match value for the ring. */ - enet_idle_slope_t idleSlope[FSL_FEATURE_ENET_QUEUE - 1]; /*!< The idle slope for certian bandwidth fraction. */ -} enet_avb_config_t; -#endif /* FSL_FEATURE_ENET_HAS_AVB */ - -/*! @brief Defines the basic configuration structure for the ENET device. - * - * Note: - * 1. macSpecialConfig is used for a special control configuration, A logical OR of - * "enet_special_control_flag_t". For a special configuration for MAC, - * set this parameter to 0. - * 2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes: - * 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. - * 2 - 128 bytes written to TX FIFO .... - * 3 - 192 bytes written to TX FIFO .... - * The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO .... - * txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 - * or for larger bus access latency 3 or larger due to contention for the system bus. - * 3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. - * It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. - * If the end of the frame is stored in FIFO and the frame size if smaller than the - * txWatermark, the frame is still transmitted. The rule is the - * same for rxFifoFullThreshold in the receive direction. - * 4. When "kENET_ControlFlowControlEnable" is set in the macSpecialConfig, ensure - * that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold - * are set for flow control enabled case. - * 5. When "kENET_ControlStoreAndFwdDisabled" is set in the macSpecialConfig, ensure - * that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable. - * 6. The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator - * are disabled. The "enet_tx_accelerator_t" and "enet_rx_accelerator_t" are - * recommended to be used to enable the transmit and receive accelerator. - * After the accelerators are enabled, the store and forward feature should be enabled. - * As a result, kENET_ControlStoreAndFwdDisabled should not be set. - * 7. The intCoalesceCfg can be used in the rx or tx enabled cases to decrese the CPU loading. - */ -typedef struct _enet_config -{ - uint32_t macSpecialConfig; /*!< Mac special configuration. A logical OR of "enet_special_control_flag_t". */ - uint32_t interrupt; /*!< Mac interrupt source. A logical OR of "enet_interrupt_enable_t". */ - uint16_t rxMaxFrameLen; /*!< Receive maximum frame length. */ - enet_mii_mode_t miiMode; /*!< MII mode. */ - enet_mii_speed_t miiSpeed; /*!< MII Speed. */ - enet_mii_duplex_t miiDuplex; /*!< MII duplex. */ - uint8_t rxAccelerConfig; /*!< Receive accelerator, A logical OR of "enet_rx_accelerator_t". */ - uint8_t txAccelerConfig; /*!< Transmit accelerator, A logical OR of "enet_rx_accelerator_t". */ - uint16_t pauseDuration; /*!< For flow control enabled case: Pause duration. */ - uint8_t rxFifoEmptyThreshold; /*!< For flow control enabled case: when RX FIFO level reaches this value, - it makes MAC generate XOFF pause frame. */ -#if defined(FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD - uint8_t rxFifoStatEmptyThreshold; /*!< For flow control enabled case: number of frames in the receive FIFO, - independent of size, that can be accept. If the limit is reached, reception - continues and a pause frame is triggered. */ -#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ - uint8_t rxFifoFullThreshold; /*!< For store and forward disable case, the data required in RX FIFO to notify - the MAC receive ready status. */ - uint8_t txFifoWatermark; /*!< For store and forward disable case, the data required in TX FIFO - before a frame transmit start. */ -#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE - enet_intcoalesce_config_t - *intCoalesceCfg; /* If the interrupt coalsecence is not required in the ring n(0,1,2), please set - to NULL. */ -#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ - uint8_t ringNum; /*!< Number of used rings. default with 1 -- single ring. */ -} enet_config_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _enet_handle enet_handle_t; - -/*! @brief ENET callback function. */ -#if FSL_FEATURE_ENET_QUEUE > 1 -typedef void (*enet_callback_t)( - ENET_Type *base, enet_handle_t *handle, uint32_t ringId, enet_event_t event, void *userData); -#else -typedef void (*enet_callback_t)(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData); -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - -/*! @brief Defines the ENET handler structure. */ -struct _enet_handle -{ - volatile enet_rx_bd_struct_t - *rxBdBase[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer descriptor base address pointer. */ - volatile enet_rx_bd_struct_t - *rxBdCurrent[FSL_FEATURE_ENET_QUEUE]; /*!< The current available receive buffer descriptor pointer. */ - volatile enet_tx_bd_struct_t - *txBdBase[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer descriptor base address pointer. */ - volatile enet_tx_bd_struct_t - *txBdCurrent[FSL_FEATURE_ENET_QUEUE]; /*!< The current available transmit buffer descriptor pointer. */ - uint32_t rxBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer size alignment. */ - uint32_t txBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer size alignment. */ - uint8_t ringNum; /*!< Number of used rings. */ - enet_callback_t callback; /*!< Callback function. */ - void *userData; /*!< Callback function parameter.*/ -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - volatile enet_tx_bd_struct_t - *txBdDirtyStatic[FSL_FEATURE_ENET_QUEUE]; /*!< The dirty transmit buffer descriptor for error static update. */ - volatile enet_tx_bd_struct_t - *txBdDirtyTime[FSL_FEATURE_ENET_QUEUE]; /*!< The dirty transmit buffer descriptor for time stamp update. */ - uint64_t msTimerSecond; /*!< The second for Master PTP timer .*/ - enet_ptp_time_data_ring_t rxPtpTsDataRing; /*!< Receive PTP 1588 time stamp data ring buffer. */ - enet_ptp_time_data_ring_t txPtpTsDataRing; /*!< Transmit PTP 1588 time stamp data ring buffer. */ -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and De-initialization - * @{ - */ - -/*! - * @brief Gets the ENET default configuration structure. - * - * The purpose of this API is to get the default ENET MAC controller - * configure structure for ENET_Init(). User may use the initialized - * structure unchanged in ENET_Init(), or modify some fields of the - * structure before calling ENET_Init(). - * Example: - @code - enet_config_t config; - ENET_GetDefaultConfig(&config); - @endcode - * @param config The ENET mac controller configuration structure pointer. - */ -void ENET_GetDefaultConfig(enet_config_t *config); - -/*! - * @brief Initializes the ENET module. - * - * This function ungates the module clock and initializes it with the ENET configuration. - * - * @param base ENET peripheral base address. - * @param handle ENET handler pointer. - * @param config ENET mac configuration structure pointer. - * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig - * can be used directly. It is also possible to verify the Mac configuration using other methods. - * @param bufferConfig ENET buffer configuration structure pointer. - * The buffer configuration should be prepared for ENET Initialization. - * It is the start address of "ringNum" enet_buffer_config structures. - * To support added multi-ring features in some soc and compatible with the previous - * enet driver version. For single ring supported, this bufferConfig is a buffer - * configure structure pointer, for multi-ring supported and used case, this bufferConfig - * pointer should be a buffer configure structure array pointer. - * @param macAddr ENET mac address of Ethernet device. This MAC address should be - * provided. - * @param srcClock_Hz The internal module clock source for MII clock. - * - * @note ENET has two buffer descriptors legacy buffer descriptors and - * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To - * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor - * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() - * to configure the 1588 feature and related buffers after calling ENET_Init(). - */ -void ENET_Init(ENET_Type *base, - enet_handle_t *handle, - const enet_config_t *config, - const enet_buffer_config_t *bufferConfig, - uint8_t *macAddr, - uint32_t srcClock_Hz); -/*! - * @brief Deinitializes the ENET module. - - * This function gates the module clock, clears ENET interrupts, and disables the ENET module. - * - * @param base ENET peripheral base address. - */ -void ENET_Deinit(ENET_Type *base); - -/*! - * @brief Resets the ENET module. - * - * This function restores the ENET module to reset state. - * Note that this function sets all registers to - * reset state. As a result, the ENET module can't work after calling this function. - * - * @param base ENET peripheral base address. - */ -static inline void ENET_Reset(ENET_Type *base) -{ - base->ECR |= ENET_ECR_RESET_MASK; -} - -/* @} */ - -/*! - * @name MII interface operation - * @{ - */ - -/*! - * @brief Sets the ENET MII speed and duplex. - * - * This API is provided to dynamically change the speed and dulpex for MAC. - * - * @param base ENET peripheral base address. - * @param speed The speed of the RMII mode. - * @param duplex The duplex of the RMII mode. - */ -void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex); - -/*! - * @brief Sets the ENET SMI(serial management interface)- MII management interface. - * - * @param base ENET peripheral base address. - * @param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution. - * @param isPreambleDisabled The preamble disable flag. - * - true Enables the preamble. - * - false Disables the preamble. - */ -void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled); - -/*! - * @brief Gets the ENET SMI- MII management interface configuration. - * - * This API is used to get the SMI configuration to check whether the MII management - * interface has been set. - * - * @param base ENET peripheral base address. - * @return The SMI setup status true or false. - */ -static inline bool ENET_GetSMI(ENET_Type *base) -{ - return (0 != (base->MSCR & 0x7E)); -} - -/*! - * @brief Reads data from the PHY register through an SMI interface. - * - * @param base ENET peripheral base address. - * @return The data read from PHY - */ -static inline uint32_t ENET_ReadSMIData(ENET_Type *base) -{ - return (uint32_t)((base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT); -} - -/*! - * @brief Starts an SMI (Serial Management Interface) read command. - * - * Used for standard IEEE802.3 MDIO Clause 22 format. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. Range from 0 ~ 31. - * @param operation The read operation. - */ -void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation); - -/*! - * @brief Starts an SMI write command. - * - * Used for standard IEEE802.3 MDIO Clause 22 format. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. Range from 0 ~ 31. - * @param operation The write operation. - * @param data The data written to PHY. - */ -void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data); - -#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO -/*! - * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI read command. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, - * the phyReg is a 21-bits combination of the devaddr (5 bits device address) - * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. - */ -void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg); - -/*! - * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI write command. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, - * the phyReg is a 21-bits combination of the devaddr (5 bits device address) - * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. - * @param data The data written to PHY. - */ -void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); -#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ - -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB -/*! - * @brief Control the usage of the delayed tx/rx RGMII clock. - * - * @param base ENET peripheral base address. - * @param txEnabled Enable or disable to generate the delayed version of RGMII_TXC. - * @param rxEnabled Enable or disable to use the delayed version of RGMII_RXC. - */ - -static inline void ENET_SetRGMIIClockDelay(ENET_Type *base, bool txEnabled, bool rxEnabled) -{ - uint32_t ecrReg = base->ECR; - - /* Set for transmit clock delay. */ - if (txEnabled) - { - ecrReg |= ENET_ECR_TXC_DLY_MASK; - } - else - { - ecrReg &= ~ENET_ECR_TXC_DLY_MASK; - } - - /* Set for receive clock delay. */ - if (rxEnabled) - { - ecrReg |= ENET_ECR_RXC_DLY_MASK; - } - else - { - ecrReg &= ~ENET_ECR_RXC_DLY_MASK; - } -} -#endif /* FSL_FEATURE_ENET_HAS_AVB */ - /* @} */ - -/*! - * @name MAC Address Filter - * @{ - */ - -/*! - * @brief Sets the ENET module Mac address. - * - * @param base ENET peripheral base address. - * @param macAddr The six-byte Mac address pointer. - * The pointer is allocated by application and input into the API. - */ -void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr); - -/*! - * @brief Gets the ENET module Mac address. - * - * @param base ENET peripheral base address. - * @param macAddr The six-byte Mac address pointer. - * The pointer is allocated by application and input into the API. - */ -void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr); - -/*! - * @brief Adds the ENET device to a multicast group. - * - * @param base ENET peripheral base address. - * @param address The six-byte multicast group address which is provided by application. - */ -void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address); - -/*! - * @brief Moves the ENET device from a multicast group. - * - * @param base ENET peripheral base address. - * @param address The six-byte multicast group address which is provided by application. - */ -void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address); - -/* @} */ - -/*! - * @name Other basic operation - * @{ - */ - -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE -#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB -/*! - * @brief Sets the ENET AVB feature. - * - * ENET AVB feature configuration, set the Receive classification match and transmit - * bandwidth. This API is called when the AVB feature is required. - * - * Note: The AVB frames transmission scheme is credit-based tx scheme and it's only supported - * with the Enhanced buffer descriptors. so the AVB configuration should only done with - * Enhanced buffer descriptor. so when the AVB feature is required, please make sure the - * the "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" is defined. - * - * @param base ENET peripheral base address. - * @param handle ENET handler pointer. - * @param config The ENET AVB feature configuration structure. - */ -void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config); -#endif /* FSL_FEATURE_ENET_HAS_AVB */ -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - -/*! - * @brief Activates ENET read or receive. - * - * This function is to active the enet read process. It is - * used for single descriptor ring/queue. - * - * @param base ENET peripheral base address. - * - * @note This must be called after the MAC configuration and - * state are ready. It must be called after the ENET_Init() and - * ENET_Ptp1588Configure(). This should be called when the ENET receive required. - */ -static inline void ENET_ActiveRead(ENET_Type *base) -{ - base->RDAR = ENET_RDAR_RDAR_MASK; -} - -#if FSL_FEATURE_ENET_QUEUE > 1 -/*! - * @brief Activates ENET read or receive for multiple-queue/ring. - * - * This function is to active the enet read process. It is - * used for extended multiple descriptor rings/queues. - * - * @param base ENET peripheral base address. - * - * @note This must be called after the MAC configuration and - * state are ready. It must be called after the ENET_Init() and - * ENET_Ptp1588Configure(). This should be called when the ENET receive required. - */ -static inline void ENET_ActiveReadMultiRing(ENET_Type *base) -{ - base->RDAR = ENET_RDAR_RDAR_MASK; - base->RDAR1 = ENET_RDAR1_RDAR_MASK; - base->RDAR2 = ENET_RDAR2_RDAR_MASK; -} -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - -/*! - * @brief Enables/disables the MAC to enter sleep mode. - * This function is used to set the MAC enter sleep mode. - * When entering sleep mode, the magic frame wakeup interrupt should be enabled - * to wake up MAC from the sleep mode and reset it to normal mode. - * - * @param base ENET peripheral base address. - * @param enable True enable sleep mode, false disable sleep mode. - */ -static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable) -{ - if (enable) - { - /* When this field is set, MAC enters sleep mode. */ - base->ECR |= ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK; - } - else - { /* MAC exits sleep mode. */ - base->ECR &= ~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK); - } -} - -/*! - * @brief Gets ENET transmit and receive accelerator functions from MAC controller. - * - * @param base ENET peripheral base address. - * @param txAccelOption The transmit accelerator option. The "enet_tx_accelerator_t" is - * recommended to be used to as the mask to get the exact the accelerator option. - * @param rxAccelOption The receive accelerator option. The "enet_rx_accelerator_t" is - * recommended to be used to as the mask to get the exact the accelerator option. - */ -static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption) -{ - assert(txAccelOption); - assert(txAccelOption); - - *txAccelOption = base->TACC; - *rxAccelOption = base->RACC; -} - -/* @} */ - -/*! - * @name Interrupts. - * @{ - */ - -/*! - * @brief Enables the ENET interrupt. - * - * This function enables the ENET interrupt according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. - * For example, to enable the TX frame interrupt and RX frame interrupt, do the following. - * @code - * ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); - * @endcode - * - * @param base ENET peripheral base address. - * @param mask ENET interrupts to enable. This is a logical OR of the - * enumeration :: enet_interrupt_enable_t. - */ -static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask) -{ - base->EIMR |= mask; -} - -/*! - * @brief Disables the ENET interrupt. - * - * This function disables the ENET interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. - * For example, to disable the TX frame interrupt and RX frame interrupt, do the following. - * @code - * ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); - * @endcode - * - * @param base ENET peripheral base address. - * @param mask ENET interrupts to disable. This is a logical OR of the - * enumeration :: enet_interrupt_enable_t. - */ -static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask) -{ - base->EIMR &= ~mask; -} - -/*! - * @brief Gets the ENET interrupt status flag. - * - * @param base ENET peripheral base address. - * @return The event status of the interrupt source. This is the logical OR of members - * of the enumeration :: enet_interrupt_enable_t. - */ -static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base) -{ - return base->EIR; -} - -/*! - * @brief Clears the ENET interrupt events status flag. - * - * This function clears enabled ENET interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See the @ref enet_interrupt_enable_t. - * For example, to clear the TX frame interrupt and RX frame interrupt, do the following. - * @code - * ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); - * @endcode - * - * @param base ENET peripheral base address. - * @param mask ENET interrupt source to be cleared. - * This is the logical OR of members of the enumeration :: enet_interrupt_enable_t. - */ -static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask) -{ - base->EIR = mask; -} -/* @} */ - -/*! - * @name Transactional operation - * @{ - */ - -/*! - * @brief Sets the callback function. - * This API is provided for the application callback required case when ENET - * interrupt is enabled. This API should be called after calling ENET_Init. - * - * @param handle ENET handler pointer. Should be provided by application. - * @param callback The ENET callback function. - * @param userData The callback function parameter. - */ -void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData); - -/*! - * @brief Gets the error statistics of a received frame for ENET single ring. - * - * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). - * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, - * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. - * This is an example. - * @code - * status = ENET_GetRxFrameSize(&g_handle, &length); - * if (status == kStatus_ENET_RxFrameError) - * { - * // Get the error information of the received frame. - * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic); - * // update the receive buffer. - * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); - * } - * @endcode - * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. - * @param eErrorStatic The error statistics structure pointer. - */ -void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); - -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE -/*! - * @brief Gets the ENET transmit frame statistics after the data send for single ring. - * - * This interface gets the error statistics of the transmit frame. - * Because the error information is reported by the uDMA after the data delivery, this interface - * should be called after the data transmit API. It is recommended to call this function on - * transmit interrupt handler. After calling the ENET_SendFrame, the - * transmit interrupt notifies the transmit completion. - * - * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. - * @param eErrorStatic The error statistics structure pointer. - * @return The execute status. - */ -status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - -/*! -* @brief Gets the size of the read frame for single ring. -* -* This function gets a received frame size from the ENET buffer descriptors. -* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. -* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the -* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". -* -* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. -* @param length The length of the valid frame received. -* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. -* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data -* and NULL length to update the receive buffers. -* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame -* should be called with the right data buffer and the captured data length input. -*/ -status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length); - -/*! - * @brief Reads a frame from the ENET device for single ring. - * This function reads a frame (both the data and the length) from the ENET buffer descriptors. - * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. - * This is an example: - * @code - * uint32_t length; - * enet_handle_t g_handle; - * //Get the received frame size firstly. - * status = ENET_GetRxFrameSize(&g_handle, &length); - * if (length != 0) - * { - * //Allocate memory here with the size of "length" - * uint8_t *data = memory allocate interface; - * if (!data) - * { - * ENET_ReadFrame(ENET, &g_handle, NULL, 0); - * //Add the console warning log. - * } - * else - * { - * status = ENET_ReadFrame(ENET, &g_handle, data, length); - * //Call stack input API to deliver the data to stack - * } - * } - * else if (status == kStatus_ENET_RxFrameError) - * { - * //Update the received buffer when a error frame is received. - * ENET_ReadFrame(ENET, &g_handle, NULL, 0); - * } - * @endcode - * @param base ENET peripheral base address. - * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. - * @param data The data buffer provided by user to store the frame which memory size should be at least "length". - * @param length The size of the data buffer which is still the length of the received frame. - * @return The execute status, successful or failure. - */ -status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length); - -/*! - * @brief Transmits an ENET frame for single ring. - * @note The CRC is automatically appended to the data. Input the data - * to send without the CRC. - * - * - * @param base ENET peripheral base address. - * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. - * @param data The data buffer provided by user to be send. - * @param length The length of the data to be send. - * @retval kStatus_Success Send frame succeed. - * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. - * The transmit busy happens when the data send rate is over the MAC capacity. - * The waiting mechanism is recommended to be added after each call return with - * kStatus_ENET_TxFrameBusy. - */ -status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length); - -#if FSL_FEATURE_ENET_QUEUE > 1 -/*! - * @brief Gets the error statistics of received frame for extended multi-ring. - * - * This API must be called after the ENET_GetRxFrameSizeMultiRing and before the ENET_ReadFrameMultiRing(). - * If the ENET_GetRxFrameSizeMultiRing returns kStatus_ENET_RxFrameError, - * the ENET_GetRxErrBeforeReadFrameMultiRing can be used to get the exact error statistics. - * - * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. - * @param eErrorStatic The error statistics structure pointer. - * @param ringId The ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. - */ -void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle, - enet_data_error_stats_t *eErrorStatic, - uint32_t ringId); - -/*! - * @brief Transmits an ENET frame for extended multi-ring. - * @note The CRC is automatically appended to the data. Input the data - * to send without the CRC. - * - * In this API, multiple-ring are mainly used for extended avb frames are supported. - * The transmit scheme for avb frames is the credit-based scheme, the AVB class A, AVB class B - * and the non-AVB frame are transmitted in ring 1, ring 2 and ring 0 independently. - * So application should care about the transmit ring index when use multiple-ring transmission. - * - * @param base ENET peripheral base address. - * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. - * @param data The data buffer provided by user to be send. - * @param length The length of the data to be send. - * @param ringId The ring index for transmission. - * @retval kStatus_Success Send frame succeed. - * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. - * The transmit busy happens when the data send rate is over the MAC capacity. - * The waiting mechanism is recommended to be added after each call return with - * kStatus_ENET_TxFrameBusy. - */ -status_t ENET_SendFrameMultiRing( - ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId); - -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE -/*! - * @brief Gets the ENET transmit frame statistics after the data send for extended multi-ring. - * - * This interface gets the error statistics of the transmit frame. - * Because the error information is reported by the uDMA after the data delivery, this interface - * should be called after the data transmit API and shall be called by transmit interrupt handler. - * After calling the ENET_SendFrame, the transmit interrupt notifies the transmit completion. - * - * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. - * @param eErrorStatic The error statistics structure pointer. - * @param ringId The ring index. - * @return The execute status. - */ -status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, - enet_data_error_stats_t *eErrorStatic, - uint32_t ringId); -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - -/*! -* @brief Gets the size of the read frame for extended mutli-ring. -* -* This function gets a received frame size from the ENET buffer descriptors. -* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. -* After calling ENET_GetRxFrameSizeMultiRing, ENET_ReadFrameMultiRing() should be called to update the -* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". The usage is -* the same to the single ring, refer to ENET_GetRxFrameSize. -* -* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. -* @param length The length of the valid frame received. -* @param ringId The ring index or ring number; -* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrameMultiRing to read frame. -* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrameMultiRing should be called with NULL data -* and NULL length to update the receive buffers. -* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame -* should be called with the right data buffer and the captured data length input. -*/ -status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, uint32_t ringId); - -/*! - * @brief Reads a frame from the ENET device for multi-ring. - * - * This function reads a frame (both the data and the length) from the ENET buffer descriptors. - * The ENET_GetRxFrameSizeMultiRing should be used to get the size of the prepared data buffer. - * This usage is the same as the single ring, refer to ENET_ReadFrame. - - * @param base ENET peripheral base address. - * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. - * @param data The data buffer provided by user to store the frame which memory size should be at least "length". - * @param length The size of the data buffer which is still the length of the received frame. - * @param ringId The ring index or ring number; - * @return The execute status, successful or failure. - */ -status_t ENET_ReadFrameMultiRing( - ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId); - -/*! - * @brief The transmit IRQ handler. - * - * @param base ENET peripheral base address. - * @param handle The ENET handler pointer. - * @param ringId The ring id or ring number. - */ -void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); - -/*! - * @brief The receive IRQ handler. - * - * @param base ENET peripheral base address. - * @param handle The ENET handler pointer. - * @param ringId The ring id or ring number. - */ -void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); - -/*! - * @brief the common IRQ handler for the tx/rx irq handler. - * - * This is used for the combined tx/rx interrupt for multi-ring (frame 1). - * - * @param base ENET peripheral base address. - */ -void ENET_CommonFrame1IRQHandler(ENET_Type *base); - -/*! - * @brief the common IRQ handler for the tx/rx irq handler. - * - * This is used for the combined tx/rx interrupt for multi-ring (frame 2). - * - * @param base ENET peripheral base address. - */ -void ENET_CommonFrame2IRQHandler(ENET_Type *base); -#else -/*! - * @brief The transmit IRQ handler. - * - * @param base ENET peripheral base address. - * @param handle The ENET handler pointer. - */ -void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle); - -/*! - * @brief The receive IRQ handler. - * - * @param base ENET peripheral base address. - * @param handle The ENET handler pointer. - */ -void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle); -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - -/*! - * @brief Some special IRQ handler including the error, mii, wakeup irq handler. - * - * @param base ENET peripheral base address. - * @param handle The ENET handler pointer. - */ -void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle); - -/*! - * @brief the common IRQ handler for the tx/rx/error etc irq handler. - * - * This is used for the combined tx/rx/error interrupt for single/mutli-ring (frame 0). - * - * @param base ENET peripheral base address. - */ -void ENET_CommonFrame0IRQHandler(ENET_Type *base); -/* @} */ - -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE -/*! - * @name ENET PTP 1588 function operation - * @{ - */ - -/*! - * @brief Configures the ENET PTP IEEE 1588 feature with the basic configuration. - * The function sets the clock for PTP 1588 timer and enables - * time stamp interrupts and transmit interrupts for PTP 1588 features. - * This API should be called when the 1588 feature is enabled - * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. - * ENET_Init should be called before calling this API. - * - * @note The PTP 1588 time-stamp second increase though time-stamp interrupt handler - * and the transmit time-stamp store is done through transmit interrupt handler. - * As a result, the TS interrupt and TX interrupt are enabled when you call this API. - * - * @param base ENET peripheral base address. - * @param handle ENET handler pointer. - * @param ptpConfig The ENET PTP1588 configuration. - */ -void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig); - -/*! - * @brief Starts the ENET PTP 1588 Timer. - * This function is used to initialize the PTP timer. After the PTP starts, - * the PTP timer starts running. - * - * @param base ENET peripheral base address. - * @param ptpClkSrc The clock source of the PTP timer. - */ -void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc); - -/*! - * @brief Stops the ENET PTP 1588 Timer. - * This function is used to stops the ENET PTP timer. - * - * @param base ENET peripheral base address. - */ -static inline void ENET_Ptp1588StopTimer(ENET_Type *base) -{ - /* Disable PTP timer and reset the timer. */ - base->ATCR &= ~ENET_ATCR_EN_MASK; - base->ATCR |= ENET_ATCR_RESTART_MASK; -} - -/*! - * @brief Adjusts the ENET PTP 1588 timer. - * - * @param base ENET peripheral base address. - * @param corrIncrease The correction increment value. This value is added every time the correction - * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, - * a value greater than the 1/ptpClkSrc speeds up the timer. - * @param corrPeriod The PTP timer correction counter wrap-around value. This defines after how - * many timer clock the correction counter should be reset and trigger a correction - * increment on the timer. A value of 0 disables the correction counter and no correction occurs. - */ -void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod); - -/*! - * @brief Sets the ENET PTP 1588 timer channel mode. - * - * @param base ENET peripheral base address. - * @param channel The ENET PTP timer channel number. - * @param mode The PTP timer channel mode, see "enet_ptp_timer_channel_mode_t". - * @param intEnable Enables or disables the interrupt. - */ -static inline void ENET_Ptp1588SetChannelMode(ENET_Type *base, - enet_ptp_timer_channel_t channel, - enet_ptp_timer_channel_mode_t mode, - bool intEnable) -{ - uint32_t tcrReg = 0; - - tcrReg = ENET_TCSR_TMODE(mode) | (intEnable ? ENET_TCSR_TIE_MASK : 0); - - /* Disable channel mode first. */ - base->CHANNEL[channel].TCSR = 0; - base->CHANNEL[channel].TCSR = tcrReg; -} - -#if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL -/*! - * @brief Sets ENET PTP 1588 timer channel mode pulse width. - * - * For the input "mode" in ENET_Ptp1588SetChannelMode, the kENET_PtpChannelPulseLowonCompare - * kENET_PtpChannelPulseHighonCompare only support the pulse width for one 1588 clock. - * this function is extended for control the pulse width from 1 to 32 1588 clock cycles. - * so call this function if you need to set the timer channel mode for - * kENET_PtpChannelPulseLowonCompare or kENET_PtpChannelPulseHighonCompare - * with pulse width more than one 1588 clock, - * - * @param base ENET peripheral base address. - * @param channel The ENET PTP timer channel number. - * @param isOutputLow True --- timer channel is configured for output compare - * pulse output low. - * false --- timer channel is configured for output compare - * pulse output high. - * @param pulseWidth The pulse width control value, range from 0 ~ 31. - * 0 --- pulse width is one 1588 clock cycle. - * 31 --- pulse width is thirty two 1588 clock cycles. - * @param intEnable Enables or disables the interrupt. - */ -static inline void ENET_Ptp1588SetChannelOutputPulseWidth( - ENET_Type *base, enet_ptp_timer_channel_t channel, bool isOutputLow, uint8_t pulseWidth, bool intEnable) -{ - uint32_t tcrReg; - - tcrReg = ENET_TCSR_TIE(intEnable) | ENET_TCSR_TPWC(pulseWidth); - - if (isOutputLow) - { - tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseLowonCompare); - } - else - { - tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseHighonCompare); - } - - /* Disable channel mode first. */ - base->CHANNEL[channel].TCSR = 0; - base->CHANNEL[channel].TCSR = tcrReg; -} -#endif /* FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL */ - -/*! - * @brief Sets the ENET PTP 1588 timer channel comparison value. - * - * @param base ENET peripheral base address. - * @param channel The PTP timer channel, see "enet_ptp_timer_channel_t". - * @param cmpValue The compare value for the compare setting. - */ -static inline void ENET_Ptp1588SetChannelCmpValue(ENET_Type *base, enet_ptp_timer_channel_t channel, uint32_t cmpValue) -{ - base->CHANNEL[channel].TCCR = cmpValue; -} - -/*! - * @brief Gets the ENET PTP 1588 timer channel status. - * - * @param base ENET peripheral base address. - * @param channel The IEEE 1588 timer channel number. - * @return True or false, Compare or capture operation status - */ -static inline bool ENET_Ptp1588GetChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) -{ - return (0 != (base->CHANNEL[channel].TCSR & ENET_TCSR_TF_MASK)); -} - -/*! - * @brief Clears the ENET PTP 1588 timer channel status. - * - * @param base ENET peripheral base address. - * @param channel The IEEE 1588 timer channel number. - */ -static inline void ENET_Ptp1588ClearChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) -{ - base->CHANNEL[channel].TCSR |= ENET_TCSR_TF_MASK; - base->TGSR = (1U << channel); -} - -/*! - * @brief Gets the current ENET time from the PTP 1588 timer. - * - * @param base ENET peripheral base address. - * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. - * @param ptpTime The PTP timer structure. - */ -void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); - -/*! - * @brief Sets the ENET PTP 1588 timer to the assigned time. - * - * @param base ENET peripheral base address. - * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. - * @param ptpTime The timer to be set to the PTP timer. - */ -void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); - -/*! - * @brief The IEEE 1588 PTP time stamp interrupt handler. - * - * @param base ENET peripheral base address. - * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. - */ -void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle); - -/*! - * @brief Gets the time stamp of the received frame. - * - * This function is used for PTP stack to get the timestamp captured by the ENET driver. - * - * @param handle The ENET handler pointer.This is the same state pointer used in - * ENET_Init. - * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. - * @retval kStatus_Success Get 1588 timestamp success. - * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. - * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. - */ -status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); - -/*! - * @brief Gets the time stamp of the transmit frame. - * - * This function is used for PTP stack to get the timestamp captured by the ENET driver. - * - * @param handle The ENET handler pointer.This is the same state pointer used in - * ENET_Init. - * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. - * @retval kStatus_Success Get 1588 timestamp success. - * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. - * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. - */ -status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_ENET_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_ewm.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_ewm.c deleted file mode 100644 index bbc49d62e7..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_ewm.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_ewm.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ewm" -#endif - - -/******************************************************************************* - * Code - ******************************************************************************/ - -void EWM_Init(EWM_Type *base, const ewm_config_t *config) -{ - assert(config); - - uint32_t value = 0U; - -#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ - (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(kCLOCK_Ewm0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif - value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) | - EWM_CTRL_INEN(config->enableEwmInput) | EWM_CTRL_INTEN(config->enableInterrupt); -#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER - base->CLKPRESCALER = config->prescaler; -#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ - -#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT - base->CLKCTRL = config->clockSource; -#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ - - base->CMPL = config->compareLowValue; - base->CMPH = config->compareHighValue; - base->CTRL = value; -} - -void EWM_Deinit(EWM_Type *base) -{ - EWM_DisableInterrupts(base, kEWM_InterruptEnable); -#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ - (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(kCLOCK_Ewm0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */ -} - -void EWM_GetDefaultConfig(ewm_config_t *config) -{ - assert(config); - - config->enableEwm = true; - config->enableEwmInput = false; - config->setInputAssertLogic = false; - config->enableInterrupt = false; -#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT - config->clockSource = kEWM_LpoClockSource0; -#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ -#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER - config->prescaler = 0U; -#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ - config->compareLowValue = 0U; - config->compareHighValue = 0xFEU; -} - -void EWM_Refresh(EWM_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupt to protect refresh sequence */ - primaskValue = DisableGlobalIRQ(); - base->SERV = (uint8_t)0xB4U; - base->SERV = (uint8_t)0x2CU; - EnableGlobalIRQ(primaskValue); -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_ewm.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_ewm.h deleted file mode 100644 index 55ab66af95..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_ewm.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_EWM_H_ -#define _FSL_EWM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ewm - * @{ - */ - - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief EWM driver version 2.0.1. */ -#define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! @brief Describes EWM clock source. */ -#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT -typedef enum _ewm_lpo_clock_source -{ - kEWM_LpoClockSource0 = 0U, /*!< EWM clock sourced from lpo_clk[0]*/ - kEWM_LpoClockSource1 = 1U, /*!< EWM clock sourced from lpo_clk[1]*/ - kEWM_LpoClockSource2 = 2U, /*!< EWM clock sourced from lpo_clk[2]*/ - kEWM_LpoClockSource3 = 3U, /*!< EWM clock sourced from lpo_clk[3]*/ -} ewm_lpo_clock_source_t; -#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ - -/*! -* @brief Data structure for EWM configuration. -* -* This structure is used to configure the EWM. -*/ -typedef struct _ewm_config -{ - bool enableEwm; /*!< Enable EWM module */ - bool enableEwmInput; /*!< Enable EWM_in input */ - bool setInputAssertLogic; /*!< EWM_in signal assertion state */ - bool enableInterrupt; /*!< Enable EWM interrupt */ -#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT - ewm_lpo_clock_source_t clockSource; /*!< Clock source select */ -#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ -#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER - uint8_t prescaler; /*!< Clock prescaler value */ -#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ - uint8_t compareLowValue; /*!< Compare low-register value */ - uint8_t compareHighValue; /*!< Compare high-register value */ -} ewm_config_t; - -/*! - * @brief EWM interrupt configuration structure with default settings all disabled. - * - * This structure contains the settings for all of EWM interrupt configurations. - */ -enum _ewm_interrupt_enable_t -{ - kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable the EWM to generate an interrupt*/ -}; - -/*! - * @brief EWM status flags. - * - * This structure contains the constants for the EWM status flags for use in the EWM functions. - */ -enum _ewm_status_flags_t -{ - kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when EWM is enabled*/ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name EWM initialization and de-initialization - * @{ - */ - -/*! - * @brief Initializes the EWM peripheral. - * - * This function is used to initialize the EWM. After calling, the EWM - * runs immediately according to the configuration. - * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a - * CPU reset. Modifying them more than once generates a bus transfer error. - * - * This is an example. - * @code - * ewm_config_t config; - * EWM_GetDefaultConfig(&config); - * config.compareHighValue = 0xAAU; - * EWM_Init(ewm_base,&config); - * @endcode - * - * @param base EWM peripheral base address - * @param config The configuration of the EWM -*/ -void EWM_Init(EWM_Type *base, const ewm_config_t *config); - -/*! - * @brief Deinitializes the EWM peripheral. - * - * This function is used to shut down the EWM. - * - * @param base EWM peripheral base address -*/ -void EWM_Deinit(EWM_Type *base); - -/*! - * @brief Initializes the EWM configuration structure. - * - * This function initializes the EWM configuration structure to default values. The default - * values are as follows. - * @code - * ewmConfig->enableEwm = true; - * ewmConfig->enableEwmInput = false; - * ewmConfig->setInputAssertLogic = false; - * ewmConfig->enableInterrupt = false; - * ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; - * ewmConfig->prescaler = 0; - * ewmConfig->compareLowValue = 0; - * ewmConfig->compareHighValue = 0xFEU; - * @endcode - * - * @param config Pointer to the EWM configuration structure. - * @see ewm_config_t - */ -void EWM_GetDefaultConfig(ewm_config_t *config); - -/* @} */ - -/*! - * @name EWM functional Operation - * @{ - */ - -/*! - * @brief Enables the EWM interrupt. - * - * This function enables the EWM interrupt. - * - * @param base EWM peripheral base address - * @param mask The interrupts to enable - * The parameter can be combination of the following source if defined - * @arg kEWM_InterruptEnable - */ -static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask) -{ - base->CTRL |= mask; -} - -/*! - * @brief Disables the EWM interrupt. - * - * This function enables the EWM interrupt. - * - * @param base EWM peripheral base address - * @param mask The interrupts to disable - * The parameter can be combination of the following source if defined - * @arg kEWM_InterruptEnable - */ -static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask) -{ - base->CTRL &= ~mask; -} - -/*! - * @brief Gets all status flags. - * - * This function gets all status flags. - * - * This is an example for getting the running flag. - * @code - * uint32_t status; - * status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag; - * @endcode - * @param base EWM peripheral base address - * @return State of the status flag: asserted (true) or not-asserted (false).@see _ewm_status_flags_t - * - True: a related status flag has been set. - * - False: a related status flag is not set. - */ -static inline uint32_t EWM_GetStatusFlags(EWM_Type *base) -{ - return (base->CTRL & EWM_CTRL_EWMEN_MASK); -} - -/*! - * @brief Services the EWM. - * - * This function resets the EWM counter to zero. - * - * @param base EWM peripheral base address -*/ -void EWM_Refresh(EWM_Type *base); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_EWM_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexcan.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexcan.c deleted file mode 100644 index 132dbfb702..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexcan.c +++ /dev/null @@ -1,2127 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flexcan.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcan" -#endif - - -/*! @brief FlexCAN Internal State. */ -enum _flexcan_state -{ - kFLEXCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ - kFLEXCAN_StateRxData = 0x1, /*!< MB receiving.*/ - kFLEXCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ - kFLEXCAN_StateTxData = 0x3, /*!< MB transmitting.*/ - kFLEXCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ - kFLEXCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ -}; - -/*! @brief FlexCAN message buffer CODE for Rx buffers. */ -enum _flexcan_mb_code_rx -{ - kFLEXCAN_RxMbInactive = 0x0, /*!< MB is not active.*/ - kFLEXCAN_RxMbFull = 0x2, /*!< MB is full.*/ - kFLEXCAN_RxMbEmpty = 0x4, /*!< MB is active and empty.*/ - kFLEXCAN_RxMbOverrun = 0x6, /*!< MB is overwritten into a full buffer.*/ - kFLEXCAN_RxMbBusy = 0x8, /*!< FlexCAN is updating the contents of the MB.*/ - /*! The CPU must not access the MB.*/ - kFLEXCAN_RxMbRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame */ - /*! and transmit a Response Frame in return.*/ - kFLEXCAN_RxMbNotUsed = 0xF, /*!< Not used.*/ -}; - -/*! @brief FlexCAN message buffer CODE FOR Tx buffers. */ -enum _flexcan_mb_code_tx -{ - kFLEXCAN_TxMbInactive = 0x8, /*!< MB is not active.*/ - kFLEXCAN_TxMbAbort = 0x9, /*!< MB is aborted.*/ - kFLEXCAN_TxMbDataOrRemote = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or */ - /*!< MB is a TX Remote Request Frame (when MB RTR = 1).*/ - kFLEXCAN_TxMbTanswer = 0xE, /*!< MB is a TX Response Request Frame from */ - /*! an incoming Remote Request Frame.*/ - kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/ -}; - -/* Typedef for interrupt handler. */ -typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Enter FlexCAN Freeze Mode. - * - * This function makes the FlexCAN work under Freeze Mode. - * - * @param base FlexCAN peripheral base address. - */ -static void FLEXCAN_EnterFreezeMode(CAN_Type *base); - -/*! - * @brief Exit FlexCAN Freeze Mode. - * - * This function makes the FlexCAN leave Freeze Mode. - * - * @param base FlexCAN peripheral base address. - */ -static void FLEXCAN_ExitFreezeMode(CAN_Type *base); - -#if !defined(NDEBUG) -/*! - * @brief Check if Message Buffer is occupied by Rx FIFO. - * - * This function check if Message Buffer is occupied by Rx FIFO. - * - * @param base FlexCAN peripheral base address. - * @param mbIdx The FlexCAN Message Buffer index. - */ -static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); -#endif - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) -/*! - * @brief Get the first valid Message buffer ID of give FlexCAN instance. - * - * This function is a helper function for Errata 5641 workaround. - * - * @param base FlexCAN peripheral base address. - * @return The first valid Message Buffer Number. - */ -static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base); -#endif - -/*! - * @brief Check if Message Buffer interrupt is enabled. - * - * This function check if Message Buffer interrupt is enabled. - * - * @param base FlexCAN peripheral base address. - * @param mbIdx The FlexCAN Message Buffer index. - */ -static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx); - -/*! - * @brief Reset the FlexCAN Instance. - * - * Restores the FlexCAN module to reset state, notice that this function - * will set all the registers to reset state so the FlexCAN module can not work - * after calling this API. - * - * @param base FlexCAN peripheral base address. -*/ -static void FLEXCAN_Reset(CAN_Type *base); - -/*! - * @brief Set Baud Rate of FlexCAN. - * - * This function set the baud rate of FlexCAN. - * - * @param base FlexCAN peripheral base address. - * @param sourceClock_Hz Source Clock in Hz. - * @param baudRate_Bps Baud Rate in Bps. - * @param timingConfig FlexCAN timingConfig. - */ -static void FLEXCAN_SetBaudRate(CAN_Type *base, - uint32_t sourceClock_Hz, - uint32_t baudRate_Bps, - flexcan_timing_config_t timingConfig); - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -/*! - * @brief Set Baud Rate of FlexCAN FD frame. - * - * This function set the baud rate of FlexCAN FD frame. - * - * @param base FlexCAN peripheral base address. - * @param sourceClock_Hz Source Clock in Hz. - * @param baudRateFD_Bps FD frame Baud Rate in Bps. - * @param timingConfig FlexCAN timingConfig. - */ -static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps, flexcan_timing_config_t timingConfig); - -/*! - * @brief Get Mailbox offset number by dword. - * - * This function gets the offset number of the specified mailbox. - * Mailbox is not consecutive between memory regions when payload is not 8 bytes - * so need to calculate the specified mailbox address. - * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes - * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword - * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS. - * - * @param base FlexCAN peripheral base address. - * @param mbIdx Mailbox index. - */ -static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx); -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Array of FlexCAN peripheral base address. */ -static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS; - -/* Array of FlexCAN IRQ number. */ -static const IRQn_Type s_flexcanRxWarningIRQ[] = CAN_Rx_Warning_IRQS; -static const IRQn_Type s_flexcanTxWarningIRQ[] = CAN_Tx_Warning_IRQS; -static const IRQn_Type s_flexcanWakeUpIRQ[] = CAN_Wake_Up_IRQS; -static const IRQn_Type s_flexcanErrorIRQ[] = CAN_Error_IRQS; -static const IRQn_Type s_flexcanBusOffIRQ[] = CAN_Bus_Off_IRQS; -static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS; - -/* Array of FlexCAN handle. */ -static flexcan_handle_t *s_flexcanHandle[ARRAY_SIZE(s_flexcanBases)]; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of FlexCAN clock name. */ -static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS; -#if defined(FLEXCAN_PERIPH_CLOCKS) -/* Array of FlexCAN serial clock name. */ -static const clock_ip_name_t s_flexcanPeriphClock[] = FLEXCAN_PERIPH_CLOCKS; -#endif /* FLEXCAN_PERIPH_CLOCKS */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* FlexCAN ISR for transactional APIs. */ -static flexcan_isr_t s_flexcanIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ - -uint32_t FLEXCAN_GetInstance(CAN_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_flexcanBases); instance++) - { - if (s_flexcanBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_flexcanBases)); - - return instance; -} - -static void FLEXCAN_EnterFreezeMode(CAN_Type *base) -{ - /* Set Freeze, Halt bits. */ - base->MCR |= CAN_MCR_FRZ_MASK; - base->MCR |= CAN_MCR_HALT_MASK; - - /* Wait until the FlexCAN Module enter freeze mode. */ - while (!(base->MCR & CAN_MCR_FRZACK_MASK)) - { - } -} - -static void FLEXCAN_ExitFreezeMode(CAN_Type *base) -{ - /* Clear Freeze, Halt bits. */ - base->MCR &= ~CAN_MCR_HALT_MASK; - base->MCR &= ~CAN_MCR_FRZ_MASK; - - /* Wait until the FlexCAN Module exit freeze mode. */ - while (base->MCR & CAN_MCR_FRZACK_MASK) - { - } -} - -#if !defined(NDEBUG) -static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) -{ - uint8_t lastOccupiedMb; - - /* Is Rx FIFO enabled? */ - if (base->MCR & CAN_MCR_RFEN_MASK) - { - /* Get RFFN value. */ - lastOccupiedMb = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); - /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ - lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5; - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) - if (mbIdx <= (lastOccupiedMb + 1)) -#else - if (mbIdx <= lastOccupiedMb) -#endif - { - return true; - } - else - { - return false; - } - } - else - { -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) - if (0 == mbIdx) - { - return true; - } - else - { - return false; - } -#else - return false; -#endif - } -} -#endif - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) -static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base) -{ - uint32_t firstValidMbNum; - - if (base->MCR & CAN_MCR_RFEN_MASK) - { - firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); - firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6; - } - else - { - firstValidMbNum = 0; - } - - return firstValidMbNum; -} -#endif - -static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx) -{ - /* Assertion. */ - assert(mbIdx < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)); - -#if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - if (mbIdx < 32) - { -#endif - if (base->IMASK1 & ((uint32_t)(1 << mbIdx))) - { - return true; - } - else - { - return false; - } -#if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - } - else - { - if (base->IMASK2 & ((uint32_t)(1 << (mbIdx - 32)))) - { - return true; - } - else - { - return false; - } - } -#endif -} - -static void FLEXCAN_Reset(CAN_Type *base) -{ - /* The module must should be first exit from low power - * mode, and then soft reset can be applied. - */ - assert(!(base->MCR & CAN_MCR_MDIS_MASK)); - - uint8_t i; - -#if (FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT != 0) - /* De-assert DOZE Enable Bit. */ - base->MCR &= ~CAN_MCR_DOZE_MASK; -#endif - - /* Wait until FlexCAN exit from any Low Power Mode. */ - while (base->MCR & CAN_MCR_LPMACK_MASK) - { - } - - /* Assert Soft Reset Signal. */ - base->MCR |= CAN_MCR_SOFTRST_MASK; - /* Wait until FlexCAN reset completes. */ - while (base->MCR & CAN_MCR_SOFTRST_MASK) - { - } - -/* Reset MCR rigister. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) && FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) - base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | - CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); -#else - base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); -#endif - - /* Reset CTRL1 and CTRL2 rigister. */ - base->CTRL1 = CAN_CTRL1_SMP_MASK; - base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK; - - /* Clean all individual Rx Mask of Message Buffers. */ - for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) - { - base->RXIMR[i] = 0x3FFFFFFF; - } - - /* Clean Global Mask of Message Buffers. */ - base->RXMGMASK = 0x3FFFFFFF; - /* Clean Global Mask of Message Buffer 14. */ - base->RX14MASK = 0x3FFFFFFF; - /* Clean Global Mask of Message Buffer 15. */ - base->RX15MASK = 0x3FFFFFFF; - /* Clean Global Mask of Rx FIFO. */ - base->RXFGMASK = 0x3FFFFFFF; - - /* Clean all Message Buffer CS fields. */ - for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) - { - base->MB[i].CS = 0x0; - } -} - -static void FLEXCAN_SetBaudRate(CAN_Type *base, - uint32_t sourceClock_Hz, - uint32_t baudRate_Bps, - flexcan_timing_config_t timingConfig) -{ - /* FlexCAN timing setting formula: - * quantum = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1); - */ - uint32_t quantum = 1 + (timingConfig.phaseSeg1 + 1) + (timingConfig.phaseSeg2 + 1) + (timingConfig.propSeg + 1); - uint32_t priDiv = baudRate_Bps * quantum; - - /* Assertion: Desired baud rate is too high. */ - assert(baudRate_Bps <= 1000000U); - /* Assertion: Source clock should greater than baud rate * quantum. */ - assert(priDiv <= sourceClock_Hz); - - if (0 == priDiv) - { - priDiv = 1; - } - - priDiv = (sourceClock_Hz / priDiv) - 1; - - /* Desired baud rate is too low. */ - if (priDiv > 0xFF) - { - priDiv = 0xFF; - } - - timingConfig.preDivider = priDiv; - - /* Update actual timing characteristic. */ - FLEXCAN_SetTimingConfig(base, &timingConfig); -} - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -static void FLEXCAN_SetFDBaudRate(CAN_Type *base, - uint32_t sourceClock_Hz, - uint32_t baudRateFD_Bps, - flexcan_timing_config_t timingConfig) -{ - /* FlexCAN FD timing setting formula: - * quantum = 1 + (FPSEG1 + 1) + (FPSEG2 + 1) + FPROPSEG; - */ - uint32_t quantum = 1 + (timingConfig.fphaseSeg1 + 1) + (timingConfig.fphaseSeg2 + 1) + timingConfig.fpropSeg; - uint32_t priDiv = baudRateFD_Bps * quantum; - - /* Assertion: Desired baud rate is too high. */ - assert(baudRateFD_Bps <= 8000000U); - /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */ - assert(priDiv <= sourceClock_Hz); - - if (0 == priDiv) - { - priDiv = 1; - } - - priDiv = (sourceClock_Hz / priDiv) - 1; - - /* Desired baud rate is too low. */ - if (priDiv > 0xFF) - { - priDiv = 0xFF; - } - - timingConfig.fpreDivider = priDiv; - - /* Update actual timing characteristic. */ - FLEXCAN_SetFDTimingConfig(base, &timingConfig); -} -#endif - -void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz) -{ - uint32_t mcrTemp; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - uint32_t instance; -#endif - - /* Assertion. */ - assert(config); - assert((config->maxMbNum > 0) && (config->maxMbNum <= FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - instance = FLEXCAN_GetInstance(base); - /* Enable FlexCAN clock. */ - CLOCK_EnableClock(s_flexcanClock[instance]); -#if defined(FLEXCAN_PERIPH_CLOCKS) - /* Enable FlexCAN serial clock. */ - CLOCK_EnableClock(s_flexcanPeriphClock[instance]); -#endif /* FLEXCAN_PERIPH_CLOCKS */ -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE - /* Disable FlexCAN Module. */ - FLEXCAN_Enable(base, false); - - /* Protocol-Engine clock source selection, This bit must be set - * when FlexCAN Module in Disable Mode. - */ - base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK : - base->CTRL1 | CAN_CTRL1_CLKSRC_MASK; -#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ - - /* Enable FlexCAN Module for configuartion. */ - FLEXCAN_Enable(base, true); - - /* Reset to known status. */ - FLEXCAN_Reset(base); - - /* Save current MCR value and enable to enter Freeze mode(enabled by default). */ - mcrTemp = base->MCR; - - /* Set the maximum number of Message Buffers */ - mcrTemp = (mcrTemp & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(config->maxMbNum - 1); - - /* Enable Loop Back Mode? */ - base->CTRL1 = (config->enableLoopBack) ? base->CTRL1 | CAN_CTRL1_LPB_MASK : base->CTRL1 & ~CAN_CTRL1_LPB_MASK; - - /* Enable Self Wake Up Mode? */ - mcrTemp = (config->enableSelfWakeup) ? mcrTemp | CAN_MCR_SLFWAK_MASK : mcrTemp & ~CAN_MCR_SLFWAK_MASK; - - /* Enable Individual Rx Masking? */ - mcrTemp = (config->enableIndividMask) ? mcrTemp | CAN_MCR_IRMQ_MASK : mcrTemp & ~CAN_MCR_IRMQ_MASK; - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) - /* Enable Doze Mode? */ - mcrTemp = (config->enableDoze) ? mcrTemp | CAN_MCR_DOZE_MASK : mcrTemp & ~CAN_MCR_DOZE_MASK; -#endif - - /* Save MCR Configuation. */ - base->MCR = mcrTemp; - - /* Baud Rate Configuration.*/ - FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate, config->timingConfig); -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - FLEXCAN_SetFDBaudRate(base, sourceClock_Hz, config->baudRateFD, config->timingConfig); -#endif -} - -void FLEXCAN_Deinit(CAN_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - uint32_t instance; -#endif - /* Reset all Register Contents. */ - FLEXCAN_Reset(base); - - /* Disable FlexCAN module. */ - FLEXCAN_Enable(base, false); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - instance = FLEXCAN_GetInstance(base); -#if defined(FLEXCAN_PERIPH_CLOCKS) - /* Disable FlexCAN serial clock. */ - CLOCK_DisableClock(s_flexcanPeriphClock[instance]); -#endif /* FLEXCAN_PERIPH_CLOCKS */ - /* Disable FlexCAN clock. */ - CLOCK_DisableClock(s_flexcanClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void FLEXCAN_GetDefaultConfig(flexcan_config_t *config) -{ - /* Assertion. */ - assert(config); - - /* Initialize FlexCAN Module config struct with default value. */ -#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE - config->clkSrc = kFLEXCAN_ClkSrcOsc; -#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ - config->baudRate = 1000000U; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - config->baudRateFD = 1000000U; -#endif - config->maxMbNum = 16; - config->enableLoopBack = false; - config->enableSelfWakeup = false; - config->enableIndividMask = false; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) - config->enableDoze = false; -#endif - /* Default protocol timing configuration, time quantum is 10. */ - config->timingConfig.phaseSeg1 = 3; - config->timingConfig.phaseSeg2 = 2; - config->timingConfig.propSeg = 1; - config->timingConfig.rJumpwidth = 1; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - config->timingConfig.fphaseSeg1 = 3; - config->timingConfig.fphaseSeg2 = 3; - config->timingConfig.fpropSeg = 1; - config->timingConfig.frJumpwidth = 1; -#endif -} - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -void FLEXCAN_FDEnable(CAN_Type *base, flexcan_mb_size_t dataSize, bool brs) -{ - if (brs) - { - base->FDCTRL &= CAN_FDCTRL_FDRATE_MASK; - } - else - { - base->FDCTRL &= ~CAN_FDCTRL_FDRATE_MASK; - } - /* Enter Freeze Mode. */ - FLEXCAN_EnterFreezeMode(base); - base->MCR |= CAN_MCR_FDEN_MASK; - base->FDCTRL |= CAN_FDCTRL_MBDSR0(dataSize); -#if defined(CAN_FDCTRL_MBDSR1_MASK) - base->FDCTRL |= CAN_FDCTRL_MBDSR1(dataSize); -#endif -#if defined(CAN_FDCTRL_MBDSR2_MASK) - base->FDCTRL |= CAN_FDCTRL_MBDSR2(dataSize); -#endif -#if defined(CAN_FDCTRL_MBDSR3_MASK) - base->FDCTRL |= CAN_FDCTRL_MBDSR3(dataSize); -#endif - /* Exit Freeze Mode. */ - FLEXCAN_ExitFreezeMode(base); -} -#endif - -void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) -{ - /* Assertion. */ - assert(config); - - /* Enter Freeze Mode. */ - FLEXCAN_EnterFreezeMode(base); - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - /* Cleaning previous Timing Setting. */ - base->CBT &= ~(CAN_CBT_EPRESDIV_MASK | CAN_CBT_ERJW_MASK | CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK | - CAN_CBT_EPROPSEG_MASK); - - /* Updating Timing Setting according to configuration structure. */ - base->CBT |= - (CAN_CBT_EPRESDIV(config->preDivider) | CAN_CBT_ERJW(config->rJumpwidth) | CAN_CBT_EPSEG1(config->phaseSeg1) | - CAN_CBT_EPSEG2(config->phaseSeg2) | CAN_CBT_EPROPSEG(config->propSeg)); -#else - /* Cleaning previous Timing Setting. */ - base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | - CAN_CTRL1_PROPSEG_MASK); - - /* Updating Timing Setting according to configuration structure. */ - base->CTRL1 |= - (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | - CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg)); -#endif - - /* Exit Freeze Mode. */ - FLEXCAN_ExitFreezeMode(base); -} - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) -{ - /* Assertion. */ - assert(config); - - /* Enter Freeze Mode. */ - FLEXCAN_EnterFreezeMode(base); - - base->CBT |= CAN_CBT_BTF(1); - /* Cleaning previous Timing Setting. */ - base->FDCBT &= ~(CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FRJW_MASK | CAN_FDCBT_FPSEG1_MASK | CAN_FDCBT_FPSEG2_MASK | - CAN_FDCBT_FPROPSEG_MASK); - - /* Updating Timing Setting according to configuration structure. */ - base->FDCBT |= (CAN_FDCBT_FPRESDIV(config->fpreDivider) | CAN_FDCBT_FRJW(config->frJumpwidth) | - CAN_FDCBT_FPSEG1(config->fphaseSeg1) | CAN_FDCBT_FPSEG2(config->fphaseSeg2) | - CAN_FDCBT_FPROPSEG(config->fpropSeg)); - - /* Exit Freeze Mode. */ - FLEXCAN_ExitFreezeMode(base); -} -#endif - -void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) -{ - /* Enter Freeze Mode. */ - FLEXCAN_EnterFreezeMode(base); - - /* Setting Rx Message Buffer Global Mask value. */ - base->RXMGMASK = mask; - base->RX14MASK = mask; - base->RX15MASK = mask; - - /* Exit Freeze Mode. */ - FLEXCAN_ExitFreezeMode(base); -} - -void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) -{ - /* Enter Freeze Mode. */ - FLEXCAN_EnterFreezeMode(base); - - /* Setting Rx FIFO Global Mask value. */ - base->RXFGMASK = mask; - - /* Exit Freeze Mode. */ - FLEXCAN_ExitFreezeMode(base); -} - -void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) -{ - assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - /* Enter Freeze Mode. */ - FLEXCAN_EnterFreezeMode(base); - - /* Setting Rx Individual Mask value. */ - base->RXIMR[maskIdx] = mask; - - /* Exit Freeze Mode. */ - FLEXCAN_ExitFreezeMode(base); -} - -void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) -{ - /* Assertion. */ - assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - - /* Inactivate Message Buffer. */ - if (enable) - { - base->MB[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - } - else - { - base->MB[mbIdx].CS = 0; - } - - /* Clean Message Buffer content. */ - base->MB[mbIdx].ID = 0x0; - base->MB[mbIdx].WORD0 = 0x0; - base->MB[mbIdx].WORD1 = 0x0; -} - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx) -{ - uint32_t dataSize; - uint32_t offset = 0; - dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; - switch (dataSize) - { - case kFLEXCAN_8BperMB: - offset = (mbIdx / 32) * 512 + mbIdx % 32 * 16; - break; - case kFLEXCAN_16BperMB: - offset = (mbIdx / 21) * 512 + mbIdx % 21 * 24; - break; - case kFLEXCAN_32BperMB: - offset = (mbIdx / 12) * 512 + mbIdx % 12 * 40; - break; - case kFLEXCAN_64BperMB: - offset = (mbIdx / 7) * 512 + mbIdx % 7 * 72; - break; - default: - break; - } - /* To get the dword aligned offset, need to divide by 4. */ - offset = offset / 4; - return offset; -} -#endif - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) -{ - /* Assertion. */ - assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - uint8_t cnt = 0; - uint8_t payload_dword = 1; - uint32_t dataSize; - dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; - volatile uint32_t *mbAddr = &(base->MB[0].CS); - uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) - uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); -#endif - - /* Inactivate Message Buffer. */ - if (enable) - { - /* Inactivate by writing CS. */ - mbAddr[offset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - } - else - { - mbAddr[offset] = 0x0; - } - - /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 - Bytes payload. */ - for (cnt = 0; cnt < dataSize + 1; cnt++) - { - payload_dword *= 2; - } - - /* Clean ID. */ - mbAddr[offset + 1] = 0x0; - /* Clean Message Buffer content, DWORD by DWORD. */ - for (cnt = 0; cnt < payload_dword; cnt++) - { - mbAddr[offset + 2 + cnt] = 0x0; - } - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) - mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); -#endif -} -#endif - -void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) -{ - /* Assertion. */ - assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(((config) || (false == enable))); - assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - - uint32_t cs_temp = 0; - - /* Inactivate Message Buffer. */ - base->MB[mbIdx].CS = 0; - - /* Clean Message Buffer content. */ - base->MB[mbIdx].ID = 0x0; - base->MB[mbIdx].WORD0 = 0x0; - base->MB[mbIdx].WORD1 = 0x0; - - if (enable) - { - /* Setup Message Buffer ID. */ - base->MB[mbIdx].ID = config->id; - - /* Setup Message Buffer format. */ - if (kFLEXCAN_FrameFormatExtend == config->format) - { - cs_temp |= CAN_CS_IDE_MASK; - } - - /* Setup Message Buffer type. */ - if (kFLEXCAN_FrameTypeRemote == config->type) - { - cs_temp |= CAN_CS_RTR_MASK; - } - - /* Activate Rx Message Buffer. */ - cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); - base->MB[mbIdx].CS = cs_temp; - } -} - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) -{ - /* Assertion. */ - assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(((config) || (false == enable))); - assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - - uint32_t cs_temp = 0; - uint8_t cnt = 0; - volatile uint32_t *mbAddr = &(base->MB[0].CS); - uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); - - /* Inactivate all mailboxes first, clean ID and Message Buffer content. */ - for (cnt = 0; cnt < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); cnt++) - { - base->MB[cnt].CS = 0; - base->MB[cnt].ID = 0; - base->MB[cnt].WORD0 = 0; - base->MB[cnt].WORD1 = 0; - } - - if (enable) - { - /* Setup Message Buffer ID. */ - mbAddr[offset + 1] = config->id; - - /* Setup Message Buffer format. */ - if (kFLEXCAN_FrameFormatExtend == config->format) - { - cs_temp |= CAN_CS_IDE_MASK; - } - - /* Activate Rx Message Buffer. */ - cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); - mbAddr[offset] = cs_temp; - } -} -#endif - -void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) -{ - /* Assertion. */ - assert((config) || (false == enable)); - - volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS); - uint8_t setup_mb, i, rffn = 0; - - /* Enter Freeze Mode. */ - FLEXCAN_EnterFreezeMode(base); - - if (enable) - { - assert(config->idFilterNum <= 128); - - /* Get the setup_mb value. */ - setup_mb = (base->MCR & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT; - setup_mb = (setup_mb < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) ? - setup_mb : - FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); - - /* Determine RFFN value. */ - for (i = 0; i <= 0xF; i++) - { - if ((8 * (i + 1)) >= config->idFilterNum) - { - rffn = i; - assert(((setup_mb - 8) - (2 * rffn)) > 0); - - base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(rffn); - break; - } - } - } - else - { - rffn = (base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT; - } - - /* Clean ID filter table occuyied Message Buffer Region. */ - rffn = (rffn + 1) * 8; - for (i = 0; i < rffn; i++) - { - idFilterRegion[i] = 0x0; - } - - if (enable) - { - /* Disable unused Rx FIFO Filter. */ - for (i = config->idFilterNum; i < rffn; i++) - { - idFilterRegion[i] = 0xFFFFFFFFU; - } - - /* Copy ID filter table to Message Buffer Region. */ - for (i = 0; i < config->idFilterNum; i++) - { - idFilterRegion[i] = config->idFilterTable[i]; - } - - /* Setup ID Fitlter Type. */ - switch (config->idFilterType) - { - case kFLEXCAN_RxFifoFilterTypeA: - base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x0); - break; - case kFLEXCAN_RxFifoFilterTypeB: - base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x1); - break; - case kFLEXCAN_RxFifoFilterTypeC: - base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x2); - break; - case kFLEXCAN_RxFifoFilterTypeD: - /* All frames rejected. */ - base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x3); - break; - default: - break; - } - - /* Setting Message Reception Priority. */ - base->CTRL2 = (config->priority == kFLEXCAN_RxFifoPrioHigh) ? base->CTRL2 & ~CAN_CTRL2_MRP_MASK : - base->CTRL2 | CAN_CTRL2_MRP_MASK; - - /* Enable Rx Message FIFO. */ - base->MCR |= CAN_MCR_RFEN_MASK; - } - else - { - /* Disable Rx Message FIFO. */ - base->MCR &= ~CAN_MCR_RFEN_MASK; - - /* Clean MB0 ~ MB5. */ - FLEXCAN_SetRxMbConfig(base, 0, NULL, false); - FLEXCAN_SetRxMbConfig(base, 1, NULL, false); - FLEXCAN_SetRxMbConfig(base, 2, NULL, false); - FLEXCAN_SetRxMbConfig(base, 3, NULL, false); - FLEXCAN_SetRxMbConfig(base, 4, NULL, false); - FLEXCAN_SetRxMbConfig(base, 5, NULL, false); - } - - /* Exit Freeze Mode. */ - FLEXCAN_ExitFreezeMode(base); -} - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) -void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) -{ - if (enable) - { - /* Enter Freeze Mode. */ - FLEXCAN_EnterFreezeMode(base); - - /* Enable FlexCAN DMA. */ - base->MCR |= CAN_MCR_DMA_MASK; - - /* Exit Freeze Mode. */ - FLEXCAN_ExitFreezeMode(base); - } - else - { - /* Enter Freeze Mode. */ - FLEXCAN_EnterFreezeMode(base); - - /* Disable FlexCAN DMA. */ - base->MCR &= ~CAN_MCR_DMA_MASK; - - /* Exit Freeze Mode. */ - FLEXCAN_ExitFreezeMode(base); - } -} -#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ - -status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame) -{ - /* Assertion. */ - assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(txFrame); - assert(txFrame->length <= 8); - assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - - uint32_t cs_temp = 0; - - /* Check if Message Buffer is available. */ - if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) - { - /* Inactive Tx Message Buffer. */ - base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); - - /* Fill Message ID field. */ - base->MB[mbIdx].ID = txFrame->id; - - /* Fill Message Format field. */ - if (kFLEXCAN_FrameFormatExtend == txFrame->format) - { - cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; - } - - /* Fill Message Type field. */ - if (kFLEXCAN_FrameTypeRemote == txFrame->type) - { - cs_temp |= CAN_CS_RTR_MASK; - } - - cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length); - - /* Load Message Payload. */ - base->MB[mbIdx].WORD0 = txFrame->dataWord0; - base->MB[mbIdx].WORD1 = txFrame->dataWord1; - - /* Activate Tx Message Buffer. */ - base->MB[mbIdx].CS = cs_temp; - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) - base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); -#endif - - return kStatus_Success; - } - else - { - /* Tx Message Buffer is activated, return immediately. */ - return kStatus_Fail; - } -} - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *txFrame) -{ - /* Assertion. */ - assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(txFrame); - assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - - uint32_t cs_temp = 0; - uint8_t cnt = 0; - uint32_t can_cs = 0; - uint8_t payload_dword = 1; - uint32_t dataSize; - dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) - uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); -#endif - volatile uint32_t *mbAddr = &(base->MB[0].CS); - uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); - - can_cs = mbAddr[0]; - /* Check if Message Buffer is available. */ - if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK)) - { - /* Inactive Tx Message Buffer and Fill Message ID field. */ - mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); - mbAddr[offset + 1] = txFrame->id; - - /* Fill Message Format field. */ - if (kFLEXCAN_FrameFormatExtend == txFrame->format) - { - cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; - } - - cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length) | CAN_CS_EDL(1); - - /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 - Bytes payload. */ - for (cnt = 0; cnt < dataSize + 1; cnt++) - { - payload_dword *= 2; - } - - /* Load Message Payload and Activate Tx Message Buffer. */ - for (cnt = 0; cnt < payload_dword; cnt++) - { - mbAddr[offset + 2 + cnt] = txFrame->dataWord[cnt]; - } - mbAddr[offset] = cs_temp; - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) - mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); - mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); -#endif - - return kStatus_Success; - } - else - { - /* Tx Message Buffer is activated, return immediately. */ - return kStatus_Fail; - } -} -#endif - -status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) -{ - /* Assertion. */ - assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(rxFrame); - assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - - uint32_t cs_temp; - uint8_t rx_code; - - /* Read CS field of Rx Message Buffer to lock Message Buffer. */ - cs_temp = base->MB[mbIdx].CS; - /* Get Rx Message Buffer Code field. */ - rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; - - /* Check to see if Rx Message Buffer is full. */ - if ((kFLEXCAN_RxMbFull == rx_code) || (kFLEXCAN_RxMbOverrun == rx_code)) - { - /* Store Message ID. */ - rxFrame->id = base->MB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); - - /* Get the message ID and format. */ - rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard; - - /* Get the message type. */ - rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData; - - /* Get the message length. */ - rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; - - /* Store Message Payload. */ - rxFrame->dataWord0 = base->MB[mbIdx].WORD0; - rxFrame->dataWord1 = base->MB[mbIdx].WORD1; - - /* Read free-running timer to unlock Rx Message Buffer. */ - (void)base->TIMER; - - if (kFLEXCAN_RxMbFull == rx_code) - { - return kStatus_Success; - } - else - { - return kStatus_FLEXCAN_RxOverflow; - } - } - else - { - /* Read free-running timer to unlock Rx Message Buffer. */ - (void)base->TIMER; - - return kStatus_Fail; - } -} - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame) -{ - /* Assertion. */ - assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(rxFrame); - assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - - uint32_t cs_temp; - uint8_t rx_code; - uint8_t cnt = 0; - uint32_t can_id = 0; - uint32_t dataSize; - dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; - uint8_t payload_dword = 1; - volatile uint32_t *mbAddr = &(base->MB[0].CS); - uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); - - /* Read CS field of Rx Message Buffer to lock Message Buffer. */ - cs_temp = mbAddr[offset]; - can_id = mbAddr[offset + 1]; - - /* Get Rx Message Buffer Code field. */ - rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; - - /* Check to see if Rx Message Buffer is full. */ - if ((kFLEXCAN_RxMbFull == rx_code) || (kFLEXCAN_RxMbOverrun == rx_code)) - { - /* Store Message ID. */ - rxFrame->id = can_id & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); - - /* Get the message ID and format. */ - rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard; - - /* Get the message type. */ - rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData; - - /* Get the message length. */ - rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; - - /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 - Bytes payload. */ - for (cnt = 0; cnt < dataSize + 1; cnt++) - { - payload_dword *= 2; - } - - /* Store Message Payload. */ - for (cnt = 0; cnt < payload_dword; cnt++) - { - rxFrame->dataWord[cnt] = mbAddr[offset + 2 + cnt]; - } - - /* Read free-running timer to unlock Rx Message Buffer. */ - (void)base->TIMER; - - if (kFLEXCAN_RxMbFull == rx_code) - { - return kStatus_Success; - } - else - { - return kStatus_FLEXCAN_RxOverflow; - } - } - else - { - /* Read free-running timer to unlock Rx Message Buffer. */ - (void)base->TIMER; - - return kStatus_Fail; - } -} -#endif - -status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) -{ - /* Assertion. */ - assert(rxFrame); - - uint32_t cs_temp; - - /* Check if Rx FIFO is Enabled. */ - if (base->MCR & CAN_MCR_RFEN_MASK) - { - /* Read CS field of Rx Message Buffer to lock Message Buffer. */ - cs_temp = base->MB[0].CS; - - /* Read data from Rx FIFO output port. */ - /* Store Message ID. */ - rxFrame->id = base->MB[0].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); - - /* Get the message ID and format. */ - rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard; - - /* Get the message type. */ - rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData; - - /* Get the message length. */ - rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; - - /* Store Message Payload. */ - rxFrame->dataWord0 = base->MB[0].WORD0; - rxFrame->dataWord1 = base->MB[0].WORD1; - - /* Store ID Filter Hit Index. */ - rxFrame->idhit = (uint8_t)(base->RXFIR & CAN_RXFIR_IDHIT_MASK); - - /* Read free-running timer to unlock Rx Message Buffer. */ - (void)base->TIMER; - - return kStatus_Success; - } - else - { - return kStatus_Fail; - } -} - -status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) -{ - /* Write Tx Message Buffer to initiate a data sending. */ - if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame)) - { - /* Wait until CAN Message send out. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) -#else - while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) -#endif - { - } - - /* Clean Tx Message Buffer Flag. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); -#else - FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); -#endif - - return kStatus_Success; - } - else - { - return kStatus_Fail; - } -} - -status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) -{ - /* Wait until Rx Message Buffer non-empty. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) -#else - while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) -#endif - { - } - - /* Clean Rx Message Buffer Flag. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); -#else - FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); -#endif - - /* Read Received CAN Message. */ - return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame); -} - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *txFrame) -{ - /* Write Tx Message Buffer to initiate a data sending. */ - if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, txFrame)) - { - /* Wait until CAN Message send out. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) -#else - while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) -#endif - { - } - - /* Clean Tx Message Buffer Flag. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); -#else - FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); -#endif - - return kStatus_Success; - } - else - { - return kStatus_Fail; - } -} - -status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame) -{ - /* Wait until Rx Message Buffer non-empty. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) -#else - while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) -#endif - { - } - - /* Clean Rx Message Buffer Flag. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); -#else - FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); -#endif - - /* Read Received CAN Message. */ - return FLEXCAN_ReadFDRxMb(base, mbIdx, rxFrame); -} -#endif - -status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) -{ - status_t rxFifoStatus; - - /* Wait until Rx FIFO non-empty. */ - while (!FLEXCAN_GetMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag)) - { - } - - /* */ - rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame); - - /* Clean Rx Fifo available flag. */ - FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag); - - return rxFifoStatus; -} - -void FLEXCAN_TransferCreateHandle(CAN_Type *base, - flexcan_handle_t *handle, - flexcan_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - uint8_t instance; - - /* Clean FlexCAN transfer handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Get instance from peripheral base address. */ - instance = FLEXCAN_GetInstance(base); - - /* Save the context in global variables to support the double weak mechanism. */ - s_flexcanHandle[instance] = handle; - - /* Register Callback function. */ - handle->callback = callback; - handle->userData = userData; - - s_flexcanIsr = FLEXCAN_TransferHandleIRQ; - - /* We Enable Error & Status interrupt here, because this interrupt just - * report current status of FlexCAN module through Callback function. - * It is insignificance without a available callback function. - */ - if (handle->callback != NULL) - { - FLEXCAN_EnableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable | - kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable | - kFLEXCAN_WakeUpInterruptEnable); - } - else - { - FLEXCAN_DisableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable | - kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable | - kFLEXCAN_WakeUpInterruptEnable); - } - - /* Enable interrupts in NVIC. */ - EnableIRQ((IRQn_Type)(s_flexcanRxWarningIRQ[instance])); - EnableIRQ((IRQn_Type)(s_flexcanTxWarningIRQ[instance])); - EnableIRQ((IRQn_Type)(s_flexcanWakeUpIRQ[instance])); - EnableIRQ((IRQn_Type)(s_flexcanErrorIRQ[instance])); - EnableIRQ((IRQn_Type)(s_flexcanBusOffIRQ[instance])); - EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance])); -} - -status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) -{ - /* Assertion. */ - assert(handle); - assert(xfer); - assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); - - /* Check if Message Buffer is idle. */ - if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) - { - /* Distinguish transmit type. */ - if (kFLEXCAN_FrameTypeRemote == xfer->frame->type) - { - handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxRemote; - - /* Register user Frame buffer to receive remote Frame. */ - handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; - } - else - { - handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxData; - } - - if (kStatus_Success == FLEXCAN_WriteTxMb(base, xfer->mbIdx, xfer->frame)) - { - /* Enable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); -#else - FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); -#endif - - return kStatus_Success; - } - else - { - handle->mbState[xfer->mbIdx] = kFLEXCAN_StateIdle; - return kStatus_Fail; - } - } - else - { - return kStatus_FLEXCAN_TxBusy; - } -} - -status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) -{ - /* Assertion. */ - assert(handle); - assert(xfer); - assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); - - /* Check if Message Buffer is idle. */ - if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) - { - handle->mbState[xfer->mbIdx] = kFLEXCAN_StateRxData; - - /* Register Message Buffer. */ - handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; - - /* Enable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); -#else - FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); -#endif - - return kStatus_Success; - } - else - { - return kStatus_FLEXCAN_RxBusy; - } -} - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) -{ - /* Assertion. */ - assert(handle); - assert(xfer); - assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); - - /* Check if Message Buffer is idle. */ - if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) - { - /* Distinguish transmit type. */ - if (kFLEXCAN_FrameTypeRemote == xfer->frame->type) - { - handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxRemote; - - /* Register user Frame buffer to receive remote Frame. */ - handle->mbFDFrameBuf[xfer->mbIdx] = xfer->framefd; - } - else - { - handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxData; - } - - if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, xfer->mbIdx, xfer->framefd)) - { - /* Enable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); -#else - FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); -#endif - - return kStatus_Success; - } - else - { - handle->mbState[xfer->mbIdx] = kFLEXCAN_StateIdle; - return kStatus_Fail; - } - } - else - { - return kStatus_FLEXCAN_TxBusy; - } -} - -status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) -{ - /* Assertion. */ - assert(handle); - assert(xfer); - assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); - - /* Check if Message Buffer is idle. */ - if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) - { - handle->mbState[xfer->mbIdx] = kFLEXCAN_StateRxData; - - /* Register Message Buffer. */ - handle->mbFDFrameBuf[xfer->mbIdx] = xfer->framefd; - - /* Enable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); -#else - FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); -#endif - - return kStatus_Success; - } - else - { - return kStatus_FLEXCAN_RxBusy; - } -} -#endif - -status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *xfer) -{ - /* Assertion. */ - assert(handle); - assert(xfer); - - /* Check if Message Buffer is idle. */ - if (kFLEXCAN_StateIdle == handle->rxFifoState) - { - handle->rxFifoState = kFLEXCAN_StateRxFifo; - - /* Register Message Buffer. */ - handle->rxFifoFrameBuf = xfer->frame; - - /* Enable Message Buffer Interrupt. */ - FLEXCAN_EnableMbInterrupts( - base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag); - - return kStatus_Success; - } - else - { - return kStatus_FLEXCAN_RxFifoBusy; - } -} - -void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) -{ - /* Assertion. */ - assert(handle); - assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - - /* Disable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); -#else - FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); -#endif - - /* Un-register handle. */ - handle->mbFrameBuf[mbIdx] = 0x0; - - /* Clean Message Buffer. */ - FLEXCAN_SetTxMbConfig(base, mbIdx, true); - - handle->mbState[mbIdx] = kFLEXCAN_StateIdle; -} - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) -{ - /* Assertion. */ - assert(handle); - assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - - /* Disable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); -#else - FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); -#endif - - /* Un-register handle. */ - handle->mbFDFrameBuf[mbIdx] = 0x0; - - /* Clean Message Buffer. */ - FLEXCAN_SetFDTxMbConfig(base, mbIdx, true); - - handle->mbState[mbIdx] = kFLEXCAN_StateIdle; -} - -void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) -{ - /* Assertion. */ - assert(handle); - assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - - /* Disable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); -#else - FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); -#endif - - /* Un-register handle. */ - handle->mbFDFrameBuf[mbIdx] = 0x0; - handle->mbState[mbIdx] = kFLEXCAN_StateIdle; -} -#endif - -void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) -{ - /* Assertion. */ - assert(handle); - assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); - - /* Disable Message Buffer Interrupt. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); -#else - FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); -#endif - - /* Un-register handle. */ - handle->mbFrameBuf[mbIdx] = 0x0; - handle->mbState[mbIdx] = kFLEXCAN_StateIdle; -} - -void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) -{ - /* Assertion. */ - assert(handle); - - /* Check if Rx FIFO is enabled. */ - if (base->MCR & CAN_MCR_RFEN_MASK) - { - /* Disable Rx Message FIFO Interrupts. */ - FLEXCAN_DisableMbInterrupts( - base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag); - - /* Un-register handle. */ - handle->rxFifoFrameBuf = 0x0; - } - - handle->rxFifoState = kFLEXCAN_StateIdle; -} - -void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) -{ - /* Assertion. */ - assert(handle); - - status_t status = kStatus_FLEXCAN_UnHandled; - uint32_t result; - - /* Store Current FlexCAN Module Error and Status. */ - result = base->ESR1; - - do - { - /* Solve FlexCAN Error and Status Interrupt. */ - if (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | - kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)) - { - status = kStatus_FLEXCAN_ErrorStatus; - - /* Clear FlexCAN Error and Status Interrupt. */ - FLEXCAN_ClearStatusFlags(base, kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | - kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag); - } - /* Solve FlexCAN Rx FIFO & Message Buffer Interrupt. */ - else - { - /* For this implementation, we solve the Message with lowest MB index first. */ - for (result = 0; result < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++) - { - /* Get the lowest unhandled Message Buffer */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - if ((FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << result)) && (FLEXCAN_IsMbIntEnabled(base, result))) -#else - if ((FLEXCAN_GetMbStatusFlags(base, 1 << result)) && (FLEXCAN_IsMbIntEnabled(base, result))) -#endif - { - break; - } - } - - /* Does not find Message to deal with. */ - if (result == FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) - { - break; - } - - /* Solve Rx FIFO interrupt. */ - if ((kFLEXCAN_StateIdle != handle->rxFifoState) && ((1 << result) <= kFLEXCAN_RxFifoOverflowFlag)) - { - switch (1 << result) - { - case kFLEXCAN_RxFifoOverflowFlag: - status = kStatus_FLEXCAN_RxFifoOverflow; - break; - - case kFLEXCAN_RxFifoWarningFlag: - status = kStatus_FLEXCAN_RxFifoWarning; - break; - - case kFLEXCAN_RxFifoFrameAvlFlag: - status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); - if (kStatus_Success == status) - { - status = kStatus_FLEXCAN_RxFifoIdle; - } - FLEXCAN_TransferAbortReceiveFifo(base, handle); - break; - - default: - status = kStatus_FLEXCAN_UnHandled; - break; - } - } - else - { - /* Get current State of Message Buffer. */ - switch (handle->mbState[result]) - { - /* Solve Rx Data Frame. */ - case kFLEXCAN_StateRxData: -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - status = FLEXCAN_ReadFDRxMb(base, result, handle->mbFDFrameBuf[result]); -#else - status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); -#endif - if (kStatus_Success == status) - { - status = kStatus_FLEXCAN_RxIdle; - } -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - FLEXCAN_TransferFDAbortReceive(base, handle, result); -#else - FLEXCAN_TransferAbortReceive(base, handle, result); -#endif - break; - - /* Solve Rx Remote Frame. */ - case kFLEXCAN_StateRxRemote: - status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); - if (kStatus_Success == status) - { - status = kStatus_FLEXCAN_RxIdle; - } - FLEXCAN_TransferAbortReceive(base, handle, result); - break; - - /* Solve Tx Data Frame. */ - case kFLEXCAN_StateTxData: - status = kStatus_FLEXCAN_TxIdle; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - FLEXCAN_TransferFDAbortSend(base, handle, result); -#else - FLEXCAN_TransferAbortSend(base, handle, result); -#endif - break; - - /* Solve Tx Remote Frame. */ - case kFLEXCAN_StateTxRemote: - handle->mbState[result] = kFLEXCAN_StateRxRemote; - status = kStatus_FLEXCAN_TxSwitchToRx; - break; - - default: - status = kStatus_FLEXCAN_UnHandled; - break; - } - } - - /* Clear resolved Message Buffer IRQ. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << result); -#else - FLEXCAN_ClearMbStatusFlags(base, 1 << result); -#endif - } - - /* Calling Callback Function if has one. */ - if (handle->callback != NULL) - { - handle->callback(base, handle, status, result, handle->userData); - } - - /* Reset return status */ - status = kStatus_FLEXCAN_UnHandled; - - /* Store Current FlexCAN Module Error and Status. */ - result = base->ESR1; - } -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFFFFFFFFFU)) || - (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | - kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)))); -#else - while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFU)) || - (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | - kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)))); -#endif -} - -#if defined(CAN0) -void CAN0_DriverIRQHandler(void) -{ - assert(s_flexcanHandle[0]); - - s_flexcanIsr(CAN0, s_flexcanHandle[0]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CAN1) -void CAN1_DriverIRQHandler(void) -{ - assert(s_flexcanHandle[1]); - - s_flexcanIsr(CAN1, s_flexcanHandle[1]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CAN2) -void CAN2_DriverIRQHandler(void) -{ - assert(s_flexcanHandle[2]); - - s_flexcanIsr(CAN2, s_flexcanHandle[2]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CAN3) -void CAN3_DriverIRQHandler(void) -{ - assert(s_flexcanHandle[3]); - - s_flexcanIsr(CAN3, s_flexcanHandle[3]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CAN4) -void CAN4_DriverIRQHandler(void) -{ - assert(s_flexcanHandle[4]); - - s_flexcanIsr(CAN4, s_flexcanHandle[4]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(DMA__CAN0) -void DMA_FLEXCAN0_INT_DriverIRQHandler(void) -{ - assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); - - s_flexcanIsr(DMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(DMA__CAN1) -void DMA_FLEXCAN1_INT_DriverIRQHandler(void) -{ - assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); - - s_flexcanIsr(DMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(DMA__CAN2) -void DMA_FLEXCAN2_INT_DriverIRQHandler(void) -{ - assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); - - s_flexcanIsr(DMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(ADMA__CAN0) -void ADMA_FLEXCAN0_INT_DriverIRQHandler(void) -{ - assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); - - s_flexcanIsr(ADMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(ADMA__CAN1) -void ADMA_FLEXCAN1_INT_DriverIRQHandler(void) -{ - assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); - - s_flexcanIsr(ADMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(ADMA__CAN2) -void ADMA_FLEXCAN2_INT_DriverIRQHandler(void) -{ - assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); - - s_flexcanIsr(ADMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexcan.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexcan.h deleted file mode 100644 index 78ec2c4293..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexcan.h +++ /dev/null @@ -1,1327 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_FLEXCAN_H_ -#define _FSL_FLEXCAN_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flexcan_driver - * @{ - */ - -/****************************************************************************** - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexCAN driver version 2.2.0. */ -#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/*! @brief FlexCAN Frame ID helper macro. */ -#define FLEXCAN_ID_STD(id) \ - (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */ -#define FLEXCAN_ID_EXT(id) \ - (((uint32_t)(((uint32_t)(id)) << CAN_ID_EXT_SHIFT)) & \ - (CAN_ID_EXT_MASK | CAN_ID_STD_MASK)) /*!< Extend Frame ID helper macro. */ - -/*! @brief FlexCAN Rx Message Buffer Mask helper macro. */ -#define FLEXCAN_RX_MB_STD_MASK(id, rtr, ide) \ - (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */ -#define FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide) \ - (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */ - -/*! @brief FlexCAN Rx FIFO Mask helper macro. */ -#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) \ - (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */ -#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \ - (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - (((uint32_t)(id)&0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */ -#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \ - (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ - (((uint32_t)(id)&0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */ -#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \ - (((uint32_t)(id)&0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */ -#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \ - (((uint32_t)(id)&0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ -#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \ - (((uint32_t)(id)&0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ -#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \ - (((uint32_t)(id)&0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \ - (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ - ( \ - ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \ - << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ - (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ - ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ - 15)) /*!< Extend Rx FIFO Mask helper macro Type B lower part helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) \ - ((FLEXCAN_ID_EXT(id) & 0x1FE00000) << 3) /*!< Extend Rx FIFO Mask helper macro Type C upper part helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id) \ - ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ - 5) /*!< Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id) \ - ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ - 13) /*!< Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) \ - ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> 21) /*!< Extend Rx FIFO Mask helper macro Type C lower part helper macro. */ - -/*! @brief FlexCAN Rx FIFO Filter helper macro. */ -#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide) \ - FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type A helper macro. */ -#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide) \ - FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH( \ - id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B upper part helper macro. */ -#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide) \ - FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW( \ - id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B lower part helper macro. */ -#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id) \ - FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH( \ - id) /*!< Standard Rx FIFO Filter helper macro Type C upper part helper macro. */ -#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id) \ - FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH( \ - id) /*!< Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ -#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \ - FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \ - id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ -#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ - FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \ - id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \ \ \ \ \ \ - */ -#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \ - FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \ - FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH( \ - id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B upper part helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \ - FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \ - id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ - FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \ - id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \ \ \ \ \ \ - */ -#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \ - FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \ - id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id) \ - FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW( \ - id) /*!< Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ -#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id) \ - FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) /*!< Extend Rx FIFO Filter helper macro Type C lower part helper macro. */ - -/*! @brief FlexCAN transfer status. */ -enum _flexcan_status -{ - kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */ - kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */ - kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS( - kStatusGroup_FLEXCAN, 2), /*!< Remote Message is send out and Message buffer changed to Receive one. */ - kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */ - kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */ - kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */ - kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */ - kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */ - kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */ - kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */ - kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< FlexCAN Module Error and Status. */ - kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< UnHadled Interrupt asserted. */ -}; - -/*! @brief FlexCAN frame format. */ -typedef enum _flexcan_frame_format -{ - kFLEXCAN_FrameFormatStandard = 0x0U, /*!< Standard frame format attribute. */ - kFLEXCAN_FrameFormatExtend = 0x1U, /*!< Extend frame format attribute. */ -} flexcan_frame_format_t; - -/*! @brief FlexCAN frame type. */ -typedef enum _flexcan_frame_type -{ - kFLEXCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ - kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ -} flexcan_frame_type_t; - -#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE -/*! @brief FlexCAN clock source. */ -typedef enum _flexcan_clock_source -{ - kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */ - kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */ -} flexcan_clock_source_t; -#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ - -/*! @brief FlexCAN Rx Fifo Filter type. */ -typedef enum _flexcan_rx_fifo_filter_type -{ - kFLEXCAN_RxFifoFilterTypeA = 0x0U, /*!< One full ID (standard and extended) per ID Filter element. */ - kFLEXCAN_RxFifoFilterTypeB = - 0x1U, /*!< Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element. */ - kFLEXCAN_RxFifoFilterTypeC = - 0x2U, /*!< Four partial 8-bit Standard or extended ID slices per ID Filter Table element. */ - kFLEXCAN_RxFifoFilterTypeD = 0x3U, /*!< All frames rejected. */ -} flexcan_rx_fifo_filter_type_t; - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -/*! - * @brief FlexCAN Message Buffer Data Size. - */ -typedef enum _flexcan_mb_size -{ - kFLEXCAN_8BperMB = 0x0U, /*!< Selects 8 bytes per Message Buffer. */ - kFLEXCAN_16BperMB = 0x1U, /*!< Selects 16 bytes per Message Buffer. */ - kFLEXCAN_32BperMB = 0x2U, /*!< Selects 32 bytes per Message Buffer. */ - kFLEXCAN_64BperMB = 0x3U, /*!< Selects 64 bytes per Message Buffer. */ -} flexcan_mb_size_t; -#endif - -/*! - * @brief FlexCAN Rx FIFO priority. - * - * The matching process starts from the Rx MB(or Rx FIFO) with higher priority. - * If no MB(or Rx FIFO filter) is satisfied, the matching process goes on with - * the Rx FIFO(or Rx MB) with lower priority. - */ -typedef enum _flexcan_rx_fifo_priority -{ - kFLEXCAN_RxFifoPrioLow = 0x0U, /*!< Matching process start from Rx Message Buffer first*/ - kFLEXCAN_RxFifoPrioHigh = 0x1U, /*!< Matching process start from Rx FIFO first*/ -} flexcan_rx_fifo_priority_t; - -/*! - * @brief FlexCAN interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all of the FlexCAN Module interrupt configurations. - * Note: FlexCAN Message Buffers and Rx FIFO have their own interrupts. - */ -enum _flexcan_interrupt_enable -{ - kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt. */ - kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< Error interrupt. */ - kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt. */ - kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt. */ - kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Wake Up interrupt. */ -}; - -/*! - * @brief FlexCAN status flags. - * - * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. - * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to - * read FlEXCAN_ErrorFlag and distinguish which error is occur using - * @ref _flexcan_error_flags enumerations. - */ -enum _flexcan_flags -{ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - kFLEXCAN_FDErrorIntFlag = CAN_ESR1_ERRINT_FAST_MASK, /*!< Error Overrun Status. */ - kFLEXCAN_BusoffDoneIntFlag = CAN_ESR1_BOFFDONEINT_MASK, /*!< Error Overrun Status. */ -#endif - kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK, /*!< CAN Synchronization Status. */ - kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */ - kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */ - kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK, /*!< Tx Error Warning Status. */ - kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK, /*!< Rx Error Warning Status. */ - kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK, /*!< CAN IDLE Status Flag. */ - kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, /*!< Fault Confinement State Flag. */ - kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK, /*!< FlexCAN In Transmission Status. */ - kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK, /*!< FlexCAN In Reception Status. */ - kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */ - kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< Error Interrupt Flag. */ - kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Wake-Up Interrupt Flag. */ - kFLEXCAN_ErrorFlag = /*!< All FlexCAN Error Status. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK | CAN_ESR1_BIT0ERR_FAST_MASK | - CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK | -#endif - CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | - CAN_ESR1_STFERR_MASK, -}; - -/*! - * @brief FlexCAN error status flags. - * - * The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. - * This enumerations should be used with KFLEXCAN_ErrorFlag in @ref _flexcan_flags enumerations - * to ditermine which error is generated. - */ -enum _flexcan_error_flags -{ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */ - kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */ - kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */ - kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */ - kFLEXCAN_FDBit1Error = CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */ - kFLEXCAN_OverrunError = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */ -#endif - kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */ - kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */ - kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK, /*!< Cyclic Redundancy Check Error. */ - kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK, /*!< Received no ACK on transmission. */ - kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */ - kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */ -}; - -/*! - * @brief FlexCAN Rx FIFO status flags. - * - * The FlexCAN Rx FIFO Status enumerations are used to determine the status of the - * Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies - * more Message Buffer space), Rx FIFO status flags are mapped to the corresponding - * Message Buffer status flags. - */ -enum _flexcan_rx_fifo_flags -{ - kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, /*!< Rx FIFO overflow flag. */ - kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */ - kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, /*!< Frames available in Rx FIFO flag. */ -}; - -#if defined(__CC_ARM) -#pragma anon_unions -#endif -/*! @brief FlexCAN message frame structure. */ -typedef struct _flexcan_frame -{ - struct - { - uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ - uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */ - uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ - uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ - uint32_t : 1; /*!< Reserved. */ - uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */ - }; - struct - { - uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ - uint32_t : 3; /*!< Reserved. */ - }; - union - { - struct - { - uint32_t dataWord0; /*!< CAN Frame payload word0. */ - uint32_t dataWord1; /*!< CAN Frame payload word1. */ - }; - struct - { - uint8_t dataByte3; /*!< CAN Frame payload byte3. */ - uint8_t dataByte2; /*!< CAN Frame payload byte2. */ - uint8_t dataByte1; /*!< CAN Frame payload byte1. */ - uint8_t dataByte0; /*!< CAN Frame payload byte0. */ - uint8_t dataByte7; /*!< CAN Frame payload byte7. */ - uint8_t dataByte6; /*!< CAN Frame payload byte6. */ - uint8_t dataByte5; /*!< CAN Frame payload byte5. */ - uint8_t dataByte4; /*!< CAN Frame payload byte4. */ - }; - }; -} flexcan_frame_t; - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -/*! @brief CAN FDmessage frame structure. */ -typedef struct _flexcan_fd_frame -{ - struct - { - uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ - uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */ - uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ - uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ - uint32_t srr : 1; /*!< Substitute Remote request. */ - uint32_t : 1; - uint32_t code : 4; /*!< Message Buffer Code. */ - uint32_t : 1; - uint32_t esi : 1; /*!< Error State Indicator. */ - uint32_t brs : 1; /*!< Bit Rate Switch. */ - uint32_t edl : 1; /*!< Extended Data Length. */ - }; - struct - { - uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ - uint32_t : 3; /*!< Reserved. */ - }; - union - { - struct - { - uint32_t dataWord[16]; /*!< CAN FD Frame payload, 16 double word maximum. */ - }; - struct - { - uint8_t dataByte3; /*!< CAN Frame payload byte3. */ - uint8_t dataByte2; /*!< CAN Frame payload byte2. */ - uint8_t dataByte1; /*!< CAN Frame payload byte1. */ - uint8_t dataByte0; /*!< CAN Frame payload byte0. */ - uint8_t dataByte7; /*!< CAN Frame payload byte7. */ - uint8_t dataByte6; /*!< CAN Frame payload byte6. */ - uint8_t dataByte5; /*!< CAN Frame payload byte5. */ - uint8_t dataByte4; /*!< CAN Frame payload byte4. */ - }; - }; -} flexcan_fd_frame_t; -#endif - -/*! @brief FlexCAN protocol timing characteristic configuration structure. */ -typedef struct _flexcan_timing_config -{ - uint16_t preDivider; /*!< Clock Pre-scaler Division Factor. */ - uint8_t rJumpwidth; /*!< Re-sync Jump Width. */ - uint8_t phaseSeg1; /*!< Phase Segment 1. */ - uint8_t phaseSeg2; /*!< Phase Segment 2. */ - uint8_t propSeg; /*!< Propagation Segment. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - uint16_t fpreDivider; /*!< Fast Clock Pre-scaler Division Factor. */ - uint8_t frJumpwidth; /*!< Fast Re-sync Jump Width. */ - uint8_t fphaseSeg1; /*!< Fast Phase Segment 1. */ - uint8_t fphaseSeg2; /*!< Fast Phase Segment 2. */ - uint8_t fpropSeg; /*!< Fast Propagation Segment. */ -#endif -} flexcan_timing_config_t; - -/*! @brief FlexCAN module configuration structure. */ -typedef struct _flexcan_config -{ - uint32_t baudRate; /*!< FlexCAN baud rate in bps. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - uint32_t baudRateFD; /*!< FlexCAN FD baud rate in bps. */ -#endif -#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE - flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */ -#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ - uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */ - bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */ - bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */ - bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) - bool enableDoze; /*!< Enable or Disable Doze Mode. */ -#endif - flexcan_timing_config_t timingConfig; /* Protocol timing . */ -} flexcan_config_t; - -/*! - * @brief FlexCAN Receive Message Buffer configuration structure - * - * This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. - * The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive - * Message Buffer. The function abort previous receiving process, clean the - * Message Buffer and activate the Rx Message Buffer using given Message Buffer - * setting. - */ -typedef struct _flexcan_rx_mb_config -{ - uint32_t id; /*!< CAN Message Buffer Frame Identifier, should be set using - FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ - flexcan_frame_format_t format; /*!< CAN Frame Identifier format(Standard of Extend). */ - flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */ -} flexcan_rx_mb_config_t; - -/*! @brief FlexCAN Rx FIFO configuration structure. */ -typedef struct _flexcan_rx_fifo_config -{ - uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Rx FIFO identifier filter table. */ - uint8_t idFilterNum; /*!< The quantity of filter elements. */ - flexcan_rx_fifo_filter_type_t idFilterType; /*!< The FlexCAN Rx FIFO Filter type. */ - flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Rx FIFO receive priority. */ -} flexcan_rx_fifo_config_t; - -/*! @brief FlexCAN Message Buffer transfer. */ -typedef struct _flexcan_mb_transfer -{ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - flexcan_fd_frame_t *framefd; -#endif - flexcan_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ - uint8_t mbIdx; /*!< The index of Message buffer used to transfer Message. */ -} flexcan_mb_transfer_t; - -/*! @brief FlexCAN Rx FIFO transfer. */ -typedef struct _flexcan_fifo_transfer -{ - flexcan_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */ -} flexcan_fifo_transfer_t; - -/*! @brief FlexCAN handle structure definition. */ -typedef struct _flexcan_handle flexcan_handle_t; - -/*! @brief FlexCAN transfer callback function. - * - * The FlexCAN transfer callback returns a value from the underlying layer. - * If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of - * FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. - * If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of - * Message Buffer that generate transfer event. - * If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be - * Ignored. - */ -typedef void (*flexcan_transfer_callback_t)( - CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData); - -/*! @brief FlexCAN handle structure. */ -struct _flexcan_handle -{ - flexcan_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< FlexCAN callback function parameter.*/ - flexcan_frame_t *volatile mbFrameBuf[CAN_WORD1_COUNT]; -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) - flexcan_fd_frame_t *volatile mbFDFrameBuf[CAN_WORD1_COUNT]; -#endif - /*!< The buffer for received data from Message Buffers. */ - flexcan_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received data from Rx FIFO. */ - volatile uint8_t mbState[CAN_WORD1_COUNT]; /*!< Message Buffer transfer state. */ - volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ -}; - -/****************************************************************************** - * API - *****************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Get the FlexCAN instance from peripheral base address. - * - * @param base FlexCAN peripheral base address. - * @return FlexCAN instance. - */ -uint32_t FLEXCAN_GetInstance(CAN_Type *base); - -/*! - * @brief Initializes a FlexCAN instance. - * - * This function initializes the FlexCAN module with user-defined settings. - * This example shows how to set up the flexcan_config_t parameters and how - * to call the FLEXCAN_Init function by passing in these parameters. - * @code - * flexcan_config_t flexcanConfig; - * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; - * flexcanConfig.baudRate = 1000000U; - * flexcanConfig.maxMbNum = 16; - * flexcanConfig.enableLoopBack = false; - * flexcanConfig.enableSelfWakeup = false; - * flexcanConfig.enableIndividMask = false; - * flexcanConfig.enableDoze = false; - * flexcanConfig.timingConfig = timingConfig; - * FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL); - * @endcode - * - * @param base FlexCAN peripheral base address. - * @param config Pointer to the user-defined configuration structure. - * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. - */ -void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz); - -/*! - * @brief De-initializes a FlexCAN instance. - * - * This function disables the FlexCAN module clock and sets all register values - * to the reset value. - * - * @param base FlexCAN peripheral base address. - */ -void FLEXCAN_Deinit(CAN_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the FlexCAN configuration structure to default values. The default - * values are as follows. - * flexcanConfig->clkSrc = KFLEXCAN_ClkSrcOsc; - * flexcanConfig->baudRate = 1000000U; - * flexcanConfig->maxMbNum = 16; - * flexcanConfig->enableLoopBack = false; - * flexcanConfig->enableSelfWakeup = false; - * flexcanConfig->enableIndividMask = false; - * flexcanConfig->enableDoze = false; - * flexcanConfig.timingConfig = timingConfig; - * - * @param config Pointer to the FlexCAN configuration structure. - */ -void FLEXCAN_GetDefaultConfig(flexcan_config_t *config); - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -/*! - * @brief Sets the FlexCAN FD protocol characteristic. - * - * This function gives user settings to CAN FD characteristic. - * - * @param base FlexCAN peripheral base address. - * @param dataSize Quantity of data bytes allocated for the message payload. - * @param brs Enable/Disable the effect of bit rate switch during data phase of Tx messages. - */ -void FLEXCAN_FDEnable(CAN_Type *base, flexcan_mb_size_t dataSize, bool brs); -#endif - -/* @} */ - -/*! - * @name Configuration. - * @{ - */ - -/*! - * @brief Sets the FlexCAN protocol timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the FLEXCAN_Init() and fill the baud rate field with a desired value. - * This provides the default timing characteristics to the module. - * - * Note that calling FLEXCAN_SetTimingConfig() overrides the baud rate set - * in FLEXCAN_Init(). - * - * @param base FlexCAN peripheral base address. - * @param config Pointer to the timing configuration structure. - */ -void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config); - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -/*! - * @brief Sets the FlexCAN FD protocol timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the FLEXCAN_Init() and fill the baud rate field with a desired value. - * This provides the default timing characteristics to the module. - * - * Note that calling FLEXCAN_SetFDTimingConfig() overrides the baud rate set - * in FLEXCAN_Init(). - * - * @param base FlexCAN peripheral base address. - * @param config Pointer to the timing configuration structure. - */ -void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config); -#endif - -/*! - * @brief Sets the FlexCAN receive message buffer global mask. - * - * This function sets the global mask for the FlexCAN message buffer in a matching process. - * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). - * - * @param base FlexCAN peripheral base address. - * @param mask Rx Message Buffer Global Mask value. - */ -void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); - -/*! - * @brief Sets the FlexCAN receive FIFO global mask. - * - * This function sets the global mask for FlexCAN FIFO in a matching process. - * - * @param base FlexCAN peripheral base address. - * @param mask Rx Fifo Global Mask value. - */ -void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); - -/*! - * @brief Sets the FlexCAN receive individual mask. - * - * This function sets the individual mask for the FlexCAN matching process. - * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). - * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. - * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to - * the Rx Filter with the same index. Note that only the first 32 - * individual masks can be used as the Rx FIFO filter mask. - * - * @param base FlexCAN peripheral base address. - * @param maskIdx The Index of individual Mask. - * @param mask Rx Individual Mask value. - */ -void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); - -/*! - * @brief Configures a FlexCAN transmit message buffer. - * - * This function aborts the previous transmission, cleans the Message Buffer, and - * configures it as a Transmit Message Buffer. - * - * @param base FlexCAN peripheral base address. - * @param mbIdx The Message Buffer index. - * @param enable Enable/disable Tx Message Buffer. - * - true: Enable Tx Message Buffer. - * - false: Disable Tx Message Buffer. - */ -void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -/*! - * @brief Configures a FlexCAN transmit message buffer. - * - * This function aborts the previous transmission, cleans the Message Buffer, and - * configures it as a Transmit Message Buffer. - * - * @param base FlexCAN peripheral base address. - * @param mbIdx The Message Buffer index. - * @param enable Enable/disable Tx Message Buffer. - * - true: Enable Tx Message Buffer. - * - false: Disable Tx Message Buffer. - */ -void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); -#endif - -/*! - * @brief Configures a FlexCAN Receive Message Buffer. - * - * This function cleans a FlexCAN build-in Message Buffer and configures it - * as a Receive Message Buffer. - * - * @param base FlexCAN peripheral base address. - * @param mbIdx The Message Buffer index. - * @param config Pointer to the FlexCAN Message Buffer configuration structure. - * @param enable Enable/disable Rx Message Buffer. - * - true: Enable Rx Message Buffer. - * - false: Disable Rx Message Buffer. - */ -void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable); - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -/*! - * @brief Configures a FlexCAN Receive Message Buffer. - * - * This function cleans a FlexCAN build-in Message Buffer and configures it - * as a Receive Message Buffer. - * - * @param base FlexCAN peripheral base address. - * @param mbIdx The Message Buffer index. - * @param config Pointer to the FlexCAN Message Buffer configuration structure. - * @param enable Enable/disable Rx Message Buffer. - * - true: Enable Rx Message Buffer. - * - false: Disable Rx Message Buffer. - */ -void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable); -#endif - -/*! - * @brief Configures the FlexCAN Rx FIFO. - * - * This function configures the Rx FIFO with given Rx FIFO configuration. - * - * @param base FlexCAN peripheral base address. - * @param config Pointer to the FlexCAN Rx FIFO configuration structure. - * @param enable Enable/disable Rx FIFO. - * - true: Enable Rx FIFO. - * - false: Disable Rx FIFO. - */ -void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable); - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the FlexCAN module interrupt flags. - * - * This function gets all FlexCAN status flags. The flags are returned as the logical - * OR value of the enumerators @ref _flexcan_flags. To check the specific status, - * compare the return value with enumerators in @ref _flexcan_flags. - * - * @param base FlexCAN peripheral base address. - * @return FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags. - */ -static inline uint32_t FLEXCAN_GetStatusFlags(CAN_Type *base) -{ - return base->ESR1; -} - -/*! - * @brief Clears status flags with the provided mask. - * - * This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag - * can't be cleared by this function. - * - * @param base FlexCAN peripheral base address. - * @param mask The status flags to be cleared, it is logical OR value of @ref _flexcan_flags. - */ -static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) -{ - /* Write 1 to clear status flag. */ - base->ESR1 = mask; -} - -/*! - * @brief Gets the FlexCAN Bus Error Counter value. - * - * This function gets the FlexCAN Bus Error Counter value for both Tx and - * Rx direction. These values may be needed in the upper layer error handling. - * - * @param base FlexCAN peripheral base address. - * @param txErrBuf Buffer to store Tx Error Counter value. - * @param rxErrBuf Buffer to store Rx Error Counter value. - */ -static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) -{ - if (txErrBuf) - { - *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT); - } - - if (rxErrBuf) - { - *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT); - } -} - -/*! - * @brief Gets the FlexCAN Message Buffer interrupt flags. - * - * This function gets the interrupt flags of a given Message Buffers. - * - * @param base FlexCAN peripheral base address. - * @param mask The ORed FlexCAN Message Buffer mask. - * @return The status of given Message Buffers. - */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) -static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask) -#else -static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask) -#endif -{ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - return ((((uint64_t)base->IFLAG1) & mask) | ((((uint64_t)base->IFLAG2) << 32) & mask)); -#else - return (base->IFLAG1 & mask); -#endif -} - -/*! - * @brief Clears the FlexCAN Message Buffer interrupt flags. - * - * This function clears the interrupt flags of a given Message Buffers. - * - * @param base FlexCAN peripheral base address. - * @param mask The ORed FlexCAN Message Buffer mask. - */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) -static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask) -#else -static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask) -#endif -{ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU); - base->IFLAG2 = (uint32_t)(mask >> 32); -#else - base->IFLAG1 = mask; -#endif -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables FlexCAN interrupts according to the provided mask. - * - * This function enables the FlexCAN interrupts according to the provided mask. The mask - * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. - * - * @param base FlexCAN peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _flexcan_interrupt_enable. - */ -static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask) -{ - /* Solve Wake Up Interrupt. */ - if (mask & kFLEXCAN_WakeUpInterruptEnable) - { - base->MCR |= CAN_MCR_WAKMSK_MASK; - } - - /* Solve others. */ - base->CTRL1 |= (mask & (~((uint32_t)kFLEXCAN_WakeUpInterruptEnable))); -} - -/*! - * @brief Disables FlexCAN interrupts according to the provided mask. - * - * This function disables the FlexCAN interrupts according to the provided mask. The mask - * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. - * - * @param base FlexCAN peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _flexcan_interrupt_enable. - */ -static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) -{ - /* Solve Wake Up Interrupt. */ - if (mask & kFLEXCAN_WakeUpInterruptEnable) - { - base->MCR &= ~CAN_MCR_WAKMSK_MASK; - } - - /* Solve others. */ - base->CTRL1 &= ~(mask & (~((uint32_t)kFLEXCAN_WakeUpInterruptEnable))); -} - -/*! - * @brief Enables FlexCAN Message Buffer interrupts. - * - * This function enables the interrupts of given Message Buffers. - * - * @param base FlexCAN peripheral base address. - * @param mask The ORed FlexCAN Message Buffer mask. - */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) -static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask) -#else -static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask) -#endif -{ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU); - base->IMASK2 |= (uint32_t)(mask >> 32); -#else - base->IMASK1 |= mask; -#endif -} - -/*! - * @brief Disables FlexCAN Message Buffer interrupts. - * - * This function disables the interrupts of given Message Buffers. - * - * @param base FlexCAN peripheral base address. - * @param mask The ORed FlexCAN Message Buffer mask. - */ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) -static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask) -#else -static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask) -#endif -{ -#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) - base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); - base->IMASK2 &= ~((uint32_t)(mask >> 32)); -#else - base->IMASK1 &= ~mask; -#endif -} - -/* @} */ - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables or disables the FlexCAN Rx FIFO DMA request. - * - * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. - * - * @param base FlexCAN peripheral base address. - * @param enable true to enable, false to disable. - */ -void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable); - -/*! - * @brief Gets the Rx FIFO Head address. - * - * This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case. - * - * @param base FlexCAN peripheral base address. - * @return FlexCAN Rx FIFO Head address. - */ -static inline uint32_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base) -{ - return (uint32_t) & (base->MB[0].CS); -} - -/* @} */ -#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Enables or disables the FlexCAN module operation. - * - * This function enables or disables the FlexCAN module. - * - * @param base FlexCAN base pointer. - * @param enable true to enable, false to disable. - */ -static inline void FLEXCAN_Enable(CAN_Type *base, bool enable) -{ - if (enable) - { - base->MCR &= ~CAN_MCR_MDIS_MASK; - - /* Wait FlexCAN exit from low-power mode. */ - while (base->MCR & CAN_MCR_LPMACK_MASK) - { - } - } - else - { - base->MCR |= CAN_MCR_MDIS_MASK; - - /* Wait FlexCAN enter low-power mode. */ - while (!(base->MCR & CAN_MCR_LPMACK_MASK)) - { - } - } -} - -/*! - * @brief Writes a FlexCAN Message to the Transmit Message Buffer. - * - * This function writes a CAN Message to the specified Transmit Message Buffer - * and changes the Message Buffer state to start CAN Message transmit. After - * that the function returns immediately. - * - * @param base FlexCAN peripheral base address. - * @param mbIdx The FlexCAN Message Buffer index. - * @param txFrame Pointer to CAN message frame to be sent. - * @retval kStatus_Success - Write Tx Message Buffer Successfully. - * @retval kStatus_Fail - Tx Message Buffer is currently in use. - */ -status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame); - -/*! - * @brief Reads a FlexCAN Message from Receive Message Buffer. - * - * This function reads a CAN message from a specified Receive Message Buffer. - * The function fills a receive CAN message frame structure with - * just received data and activates the Message Buffer again. - * The function returns immediately. - * - * @param base FlexCAN peripheral base address. - * @param mbIdx The FlexCAN Message Buffer index. - * @param rxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. - * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. - * @retval kStatus_Fail - Rx Message Buffer is empty. - */ -status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -/*! - * @brief Writes a FlexCAN FD Message to the Transmit Message Buffer. - * - * This function writes a CAN FD Message to the specified Transmit Message Buffer - * and changes the Message Buffer state to start CAN FD Message transmit. After - * that the function returns immediately. - * - * @param base FlexCAN peripheral base address. - * @param mbIdx The FlexCAN FD Message Buffer index. - * @param txFrame Pointer to CAN FD message frame to be sent. - * @retval kStatus_Success - Write Tx Message Buffer Successfully. - * @retval kStatus_Fail - Tx Message Buffer is currently in use. - */ -status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *txFrame); - -/*! - * @brief Reads a FlexCAN FD Message from Receive Message Buffer. - * - * This function reads a CAN FD message from a specified Receive Message Buffer. - * The function fills a receive CAN FD message frame structure with - * just received data and activates the Message Buffer again. - * The function returns immediately. - * - * @param base FlexCAN peripheral base address. - * @param mbIdx The FlexCAN FD Message Buffer index. - * @param rxFrame Pointer to CAN FD message frame structure for reception. - * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. - * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. - * @retval kStatus_Fail - Rx Message Buffer is empty. - */ -status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame); -#endif - -/*! - * @brief Reads a FlexCAN Message from Rx FIFO. - * - * This function reads a CAN message from the FlexCAN build-in Rx FIFO. - * - * @param base FlexCAN peripheral base address. - * @param rxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Message from Rx FIFO successfully. - * @retval kStatus_Fail - Rx FIFO is not enabled. - */ -status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) -/*! - * @brief Performs a polling send transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base FlexCAN peripheral base pointer. - * @param mbIdx The FlexCAN FD Message Buffer index. - * @param txFrame Pointer to CAN FD message frame to be sent. - * @retval kStatus_Success - Write Tx Message Buffer Successfully. - * @retval kStatus_Fail - Tx Message Buffer is currently in use. - */ -status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *txFrame); - -/*! - * @brief Performs a polling receive transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base FlexCAN peripheral base pointer. - * @param mbIdx The FlexCAN FD Message Buffer index. - * @param rxFrame Pointer to CAN FD message frame structure for reception. - * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. - * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. - * @retval kStatus_Fail - Rx Message Buffer is empty. - */ -status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame); - -/*! - * @brief Sends a message using IRQ. - * - * This function sends a message using IRQ. This is a non-blocking function, which returns - * right away. When messages have been sent out, the send callback function is called. - * - * @param base FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - * @param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. - * @retval kStatus_Success Start Tx Message Buffer sending process successfully. - * @retval kStatus_Fail Write Tx Message Buffer failed. - * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. - */ -status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); - -/*! - * @brief Receives a message using IRQ. - * - * This function receives a message using IRQ. This is non-blocking function, which returns - * right away. When the message has been received, the receive callback function is called. - * - * @param base FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - * @param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. - * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. - * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. - */ -status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); - -/*! - * @brief Aborts the interrupt driven message send process. - * - * This function aborts the interrupt driven message send process. - * - * @param base FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - * @param mbIdx The FlexCAN FD Message Buffer index. - */ -void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); -#endif - -/*! - * @brief Performs a polling send transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base FlexCAN peripheral base pointer. - * @param mbIdx The FlexCAN Message Buffer index. - * @param txFrame Pointer to CAN message frame to be sent. - * @retval kStatus_Success - Write Tx Message Buffer Successfully. - * @retval kStatus_Fail - Tx Message Buffer is currently in use. - */ -status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame); - -/*! - * @brief Performs a polling receive transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base FlexCAN peripheral base pointer. - * @param mbIdx The FlexCAN Message Buffer index. - * @param rxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. - * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. - * @retval kStatus_Fail - Rx Message Buffer is empty. - */ -status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); - -/*! - * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param base FlexCAN peripheral base pointer. - * @param rxFrame Pointer to CAN message frame structure for reception. - * @retval kStatus_Success - Read Message from Rx FIFO successfully. - * @retval kStatus_Fail - Rx FIFO is not enabled. - */ -status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame); - -/*! - * @brief Initializes the FlexCAN handle. - * - * This function initializes the FlexCAN handle, which can be used for other FlexCAN - * transactional APIs. Usually, for a specified FlexCAN instance, - * call this API once to get the initialized handle. - * - * @param base FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -void FLEXCAN_TransferCreateHandle(CAN_Type *base, - flexcan_handle_t *handle, - flexcan_transfer_callback_t callback, - void *userData); - -/*! - * @brief Sends a message using IRQ. - * - * This function sends a message using IRQ. This is a non-blocking function, which returns - * right away. When messages have been sent out, the send callback function is called. - * - * @param base FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - * @param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. - * @retval kStatus_Success Start Tx Message Buffer sending process successfully. - * @retval kStatus_Fail Write Tx Message Buffer failed. - * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. - */ -status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); - -/*! - * @brief Receives a message using IRQ. - * - * This function receives a message using IRQ. This is non-blocking function, which returns - * right away. When the message has been received, the receive callback function is called. - * - * @param base FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - * @param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. - * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. - * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. - */ -status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); - -/*! - * @brief Receives a message from Rx FIFO using IRQ. - * - * This function receives a message using IRQ. This is a non-blocking function, which returns - * right away. When all messages have been received, the receive callback function is called. - * - * @param base FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - * @param xfer FlexCAN Rx FIFO transfer structure. See the @ref flexcan_fifo_transfer_t. - * @retval kStatus_Success - Start Rx FIFO receiving process successfully. - * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. - */ -status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, - flexcan_handle_t *handle, - flexcan_fifo_transfer_t *xfer); - -/*! - * @brief Aborts the interrupt driven message send process. - * - * This function aborts the interrupt driven message send process. - * - * @param base FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - * @param mbIdx The FlexCAN Message Buffer index. - */ -void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); - -/*! - * @brief Aborts the interrupt driven message receive process. - * - * This function aborts the interrupt driven message receive process. - * - * @param base FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - * @param mbIdx The FlexCAN Message Buffer index. - */ -void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); - -/*! - * @brief Aborts the interrupt driven message receive from Rx FIFO process. - * - * This function aborts the interrupt driven message receive from Rx FIFO process. - * - * @param base FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - */ -void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle); - -/*! - * @brief FlexCAN IRQ handle function. - * - * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. - * - * @param base FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - */ -void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_FLEXCAN_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio.c deleted file mode 100644 index e6c256c3ee..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio.c +++ /dev/null @@ -1,320 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flexio.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexio" -#endif - - -/*< @brief user configurable flexio handle count. */ -#define FLEXIO_HANDLE_COUNT 2 - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to flexio bases for each instance. */ -FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to flexio clocks for each instance. */ -const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*< @brief pointer to array of FLEXIO handle. */ -static void *s_flexioHandle[FLEXIO_HANDLE_COUNT]; - -/*< @brief pointer to array of FLEXIO IP types. */ -static void *s_flexioType[FLEXIO_HANDLE_COUNT]; - -/*< @brief pointer to array of FLEXIO Isr. */ -static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT]; - -/******************************************************************************* - * Codes - ******************************************************************************/ - -uint32_t FLEXIO_GetInstance(FLEXIO_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_flexioBases); instance++) - { - if (s_flexioBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_flexioBases)); - - return instance; -} - -void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig) -{ - uint32_t ctrlReg = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_EnableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - FLEXIO_Reset(base); - - ctrlReg = base->CTRL; - ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); - ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | - FLEXIO_CTRL_FLEXEN(userConfig->enableFlexio)); - if (!userConfig->enableInDoze) - { - ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; - } - - base->CTRL = ctrlReg; -} - -void FLEXIO_Deinit(FLEXIO_Type *base) -{ - FLEXIO_Enable(base, false); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig) -{ - assert(userConfig); - - userConfig->enableFlexio = true; - userConfig->enableInDoze = false; - userConfig->enableInDebug = true; - userConfig->enableFastAccess = false; -} - -void FLEXIO_Reset(FLEXIO_Type *base) -{ - /*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/ - base->CTRL |= FLEXIO_CTRL_SWRST_MASK; - base->CTRL = 0; -} - -uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index) -{ - assert(index < FLEXIO_SHIFTBUF_COUNT); - - uint32_t address = 0; - - switch (type) - { - case kFLEXIO_ShifterBuffer: - address = (uint32_t) & (base->SHIFTBUF[index]); - break; - - case kFLEXIO_ShifterBufferBitSwapped: - address = (uint32_t) & (base->SHIFTBUFBIS[index]); - break; - - case kFLEXIO_ShifterBufferByteSwapped: - address = (uint32_t) & (base->SHIFTBUFBYS[index]); - break; - - case kFLEXIO_ShifterBufferBitByteSwapped: - address = (uint32_t) & (base->SHIFTBUFBBS[index]); - break; - -#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP - case kFLEXIO_ShifterBufferNibbleByteSwapped: - address = (uint32_t) & (base->SHIFTBUFNBS[index]); - break; - -#endif -#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP - case kFLEXIO_ShifterBufferHalfWordSwapped: - address = (uint32_t) & (base->SHIFTBUFHWS[index]); - break; - -#endif -#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP - case kFLEXIO_ShifterBufferNibbleSwapped: - address = (uint32_t) & (base->SHIFTBUFNIS[index]); - break; - -#endif - default: - break; - } - return address; -} - -void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig) -{ - base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource) -#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH - | FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth) -#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ - | FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) | - FLEXIO_SHIFTCFG_SSTART(shifterConfig->shifterStart); - - base->SHIFTCTL[index] = - FLEXIO_SHIFTCTL_TIMSEL(shifterConfig->timerSelect) | FLEXIO_SHIFTCTL_TIMPOL(shifterConfig->timerPolarity) | - FLEXIO_SHIFTCTL_PINCFG(shifterConfig->pinConfig) | FLEXIO_SHIFTCTL_PINSEL(shifterConfig->pinSelect) | - FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode); -} - -void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig) -{ - base->TIMCFG[index] = - FLEXIO_TIMCFG_TIMOUT(timerConfig->timerOutput) | FLEXIO_TIMCFG_TIMDEC(timerConfig->timerDecrement) | - FLEXIO_TIMCFG_TIMRST(timerConfig->timerReset) | FLEXIO_TIMCFG_TIMDIS(timerConfig->timerDisable) | - FLEXIO_TIMCFG_TIMENA(timerConfig->timerEnable) | FLEXIO_TIMCFG_TSTOP(timerConfig->timerStop) | - FLEXIO_TIMCFG_TSTART(timerConfig->timerStart); - - base->TIMCMP[index] = FLEXIO_TIMCMP_CMP(timerConfig->timerCompare); - - base->TIMCTL[index] = FLEXIO_TIMCTL_TRGSEL(timerConfig->triggerSelect) | - FLEXIO_TIMCTL_TRGPOL(timerConfig->triggerPolarity) | - FLEXIO_TIMCTL_TRGSRC(timerConfig->triggerSource) | - FLEXIO_TIMCTL_PINCFG(timerConfig->pinConfig) | FLEXIO_TIMCTL_PINSEL(timerConfig->pinSelect) | - FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode); -} - -status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr) -{ - assert(base); - assert(handle); - assert(isr); - - uint8_t index = 0; - - /* Find the an empty handle pointer to store the handle. */ - for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) - { - if (s_flexioHandle[index] == NULL) - { - /* Register FLEXIO simulated driver base, handle and isr. */ - s_flexioType[index] = base; - s_flexioHandle[index] = handle; - s_flexioIsr[index] = isr; - break; - } - } - - if (index == FLEXIO_HANDLE_COUNT) - { - return kStatus_OutOfRange; - } - else - { - return kStatus_Success; - } -} - -status_t FLEXIO_UnregisterHandleIRQ(void *base) -{ - assert(base); - - uint8_t index = 0; - - /* Find the index from base address mappings. */ - for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) - { - if (s_flexioType[index] == base) - { - /* Unregister FLEXIO simulated driver handle and isr. */ - s_flexioType[index] = NULL; - s_flexioHandle[index] = NULL; - s_flexioIsr[index] = NULL; - break; - } - } - - if (index == FLEXIO_HANDLE_COUNT) - { - return kStatus_OutOfRange; - } - else - { - return kStatus_Success; - } -} - -void FLEXIO_CommonIRQHandler(void) -{ - uint8_t index; - - for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) - { - if (s_flexioHandle[index]) - { - s_flexioIsr[index](s_flexioType[index], s_flexioHandle[index]); - } - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void FLEXIO_DriverIRQHandler(void) -{ - FLEXIO_CommonIRQHandler(); -} - -void FLEXIO0_DriverIRQHandler(void) -{ - FLEXIO_CommonIRQHandler(); -} - -void FLEXIO1_DriverIRQHandler(void) -{ - FLEXIO_CommonIRQHandler(); -} - -void UART2_FLEXIO_DriverIRQHandler(void) -{ - FLEXIO_CommonIRQHandler(); -} - -void FLEXIO2_DriverIRQHandler(void) -{ - FLEXIO_CommonIRQHandler(); -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio.h deleted file mode 100644 index bebca939ec..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio.h +++ /dev/null @@ -1,726 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_FLEXIO_H_ -#define _FSL_FLEXIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flexio_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexIO driver version 2.0.2. */ -#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! @brief Calculate FlexIO timer trigger.*/ -#define FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x) ((uint32_t)(x) << 1U) -#define FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x) (((uint32_t)(x) << 2U) | 0x1U) -#define FLEXIO_TIMER_TRIGGER_SEL_TIMn(x) (((uint32_t)(x) << 2U) | 0x3U) - -/*! @brief Define time of timer trigger polarity.*/ -typedef enum _flexio_timer_trigger_polarity -{ - kFLEXIO_TimerTriggerPolarityActiveHigh = 0x0U, /*!< Active high. */ - kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U, /*!< Active low. */ -} flexio_timer_trigger_polarity_t; - -/*! @brief Define type of timer trigger source.*/ -typedef enum _flexio_timer_trigger_source -{ - kFLEXIO_TimerTriggerSourceExternal = 0x0U, /*!< External trigger selected. */ - kFLEXIO_TimerTriggerSourceInternal = 0x1U, /*!< Internal trigger selected. */ -} flexio_timer_trigger_source_t; - -/*! @brief Define type of timer/shifter pin configuration.*/ -typedef enum _flexio_pin_config -{ - kFLEXIO_PinConfigOutputDisabled = 0x0U, /*!< Pin output disabled. */ - kFLEXIO_PinConfigOpenDrainOrBidirection = 0x1U, /*!< Pin open drain or bidirectional output enable. */ - kFLEXIO_PinConfigBidirectionOutputData = 0x2U, /*!< Pin bidirectional output data. */ - kFLEXIO_PinConfigOutput = 0x3U, /*!< Pin output. */ -} flexio_pin_config_t; - -/*! @brief Definition of pin polarity.*/ -typedef enum _flexio_pin_polarity -{ - kFLEXIO_PinActiveHigh = 0x0U, /*!< Active high. */ - kFLEXIO_PinActiveLow = 0x1U, /*!< Active low. */ -} flexio_pin_polarity_t; - -/*! @brief Define type of timer work mode.*/ -typedef enum _flexio_timer_mode -{ - kFLEXIO_TimerModeDisabled = 0x0U, /*!< Timer Disabled. */ - kFLEXIO_TimerModeDual8BitBaudBit = 0x1U, /*!< Dual 8-bit counters baud/bit mode. */ - kFLEXIO_TimerModeDual8BitPWM = 0x2U, /*!< Dual 8-bit counters PWM mode. */ - kFLEXIO_TimerModeSingle16Bit = 0x3U, /*!< Single 16-bit counter mode. */ -} flexio_timer_mode_t; - -/*! @brief Define type of timer initial output or timer reset condition.*/ -typedef enum _flexio_timer_output -{ - kFLEXIO_TimerOutputOneNotAffectedByReset = 0x0U, /*!< Logic one when enabled and is not affected by timer - reset. */ - kFLEXIO_TimerOutputZeroNotAffectedByReset = 0x1U, /*!< Logic zero when enabled and is not affected by timer - reset. */ - kFLEXIO_TimerOutputOneAffectedByReset = 0x2U, /*!< Logic one when enabled and on timer reset. */ - kFLEXIO_TimerOutputZeroAffectedByReset = 0x3U, /*!< Logic zero when enabled and on timer reset. */ -} flexio_timer_output_t; - -/*! @brief Define type of timer decrement.*/ -typedef enum _flexio_timer_decrement_source -{ - kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput = 0x0U, /*!< Decrement counter on FlexIO clock, Shift clock - equals Timer output. */ - kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput = 0x1U, /*!< Decrement counter on Trigger input (both edges), - Shift clock equals Timer output. */ - kFLEXIO_TimerDecSrcOnPinInputShiftPinInput = 0x2U, /*!< Decrement counter on Pin input (both edges), - Shift clock equals Pin input. */ - kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput = 0x3U, /*!< Decrement counter on Trigger input (both edges), - Shift clock equals Trigger input. */ -} flexio_timer_decrement_source_t; - -/*! @brief Define type of timer reset condition.*/ -typedef enum _flexio_timer_reset_condition -{ - kFLEXIO_TimerResetNever = 0x0U, /*!< Timer never reset. */ - kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */ - kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput = 0x3U, /*!< Timer reset on Timer Trigger equal to - Timer Output. */ - kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U, /*!< Timer reset on Timer Pin rising edge. */ - kFLEXIO_TimerResetOnTimerTriggerRisingEdge = 0x6U, /*!< Timer reset on Trigger rising edge. */ - kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U, /*!< Timer reset on Trigger rising or falling edge. */ -} flexio_timer_reset_condition_t; - -/*! @brief Define type of timer disable condition.*/ -typedef enum _flexio_timer_disable_condition -{ - kFLEXIO_TimerDisableNever = 0x0U, /*!< Timer never disabled. */ - kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U, /*!< Timer disabled on Timer N-1 disable. */ - kFLEXIO_TimerDisableOnTimerCompare = 0x2U, /*!< Timer disabled on Timer compare. */ - kFLEXIO_TimerDisableOnTimerCompareTriggerLow = 0x3U, /*!< Timer disabled on Timer compare and Trigger Low. */ - kFLEXIO_TimerDisableOnPinBothEdge = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */ - kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh = 0x5U, /*!< Timer disabled on Pin rising or falling edge provided - Trigger is high. */ - kFLEXIO_TimerDisableOnTriggerFallingEdge = 0x6U, /*!< Timer disabled on Trigger falling edge. */ -} flexio_timer_disable_condition_t; - -/*! @brief Define type of timer enable condition.*/ -typedef enum _flexio_timer_enable_condition -{ - kFLEXIO_TimerEnabledAlways = 0x0U, /*!< Timer always enabled. */ - kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U, /*!< Timer enabled on Timer N-1 enable. */ - kFLEXIO_TimerEnableOnTriggerHigh = 0x2U, /*!< Timer enabled on Trigger high. */ - kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */ - kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U, /*!< Timer enabled on Pin rising edge. */ - kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh = 0x5U, /*!< Timer enabled on Pin rising edge and Trigger high. */ - kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U, /*!< Timer enabled on Trigger rising edge. */ - kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */ -} flexio_timer_enable_condition_t; - -/*! @brief Define type of timer stop bit generate condition.*/ -typedef enum _flexio_timer_stop_bit_condition -{ - kFLEXIO_TimerStopBitDisabled = 0x0U, /*!< Stop bit disabled. */ - kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U, /*!< Stop bit is enabled on timer compare. */ - kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U, /*!< Stop bit is enabled on timer disable. */ - kFLEXIO_TimerStopBitEnableOnTimerCompareDisable = 0x3U, /*!< Stop bit is enabled on timer compare and timer - disable. */ -} flexio_timer_stop_bit_condition_t; - -/*! @brief Define type of timer start bit generate condition.*/ -typedef enum _flexio_timer_start_bit_condition -{ - kFLEXIO_TimerStartBitDisabled = 0x0U, /*!< Start bit disabled. */ - kFLEXIO_TimerStartBitEnabled = 0x1U, /*!< Start bit enabled. */ -} flexio_timer_start_bit_condition_t; - -/*! @brief Define type of timer polarity for shifter control. */ -typedef enum _flexio_shifter_timer_polarity -{ - kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /* Shift on positive edge of shift clock. */ - kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /* Shift on negative edge of shift clock. */ -} flexio_shifter_timer_polarity_t; - -/*! @brief Define type of shifter working mode.*/ -typedef enum _flexio_shifter_mode -{ - kFLEXIO_ShifterDisabled = 0x0U, /*!< Shifter is disabled. */ - kFLEXIO_ShifterModeReceive = 0x1U, /*!< Receive mode. */ - kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */ - kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */ - kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */ -#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE - kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing - programmable state attributes. */ -#endif /* FSL_FEATURE_FLEXIO_HAS_STATE_MODE */ -#if FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE - kFLEXIO_ShifterModeLogic = 0x7U, /*!< SHIFTBUF contents are used for implementing - programmable logic look up table. */ -#endif /* FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE */ -} flexio_shifter_mode_t; - -/*! @brief Define type of shifter input source.*/ -typedef enum _flexio_shifter_input_source -{ - kFLEXIO_ShifterInputFromPin = 0x0U, /*!< Shifter input from pin. */ - kFLEXIO_ShifterInputFromNextShifterOutput = 0x1U, /*!< Shifter input from Shifter N+1. */ -} flexio_shifter_input_source_t; - -/*! @brief Define of STOP bit configuration.*/ -typedef enum _flexio_shifter_stop_bit -{ - kFLEXIO_ShifterStopBitDisable = 0x0U, /*!< Disable shifter stop bit. */ - kFLEXIO_ShifterStopBitLow = 0x2U, /*!< Set shifter stop bit to logic low level. */ - kFLEXIO_ShifterStopBitHigh = 0x3U, /*!< Set shifter stop bit to logic high level. */ -} flexio_shifter_stop_bit_t; - -/*! @brief Define type of START bit configuration.*/ -typedef enum _flexio_shifter_start_bit -{ - kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable = 0x0U, /*!< Disable shifter start bit, transmitter loads - data on enable. */ - kFLEXIO_ShifterStartBitDisabledLoadDataOnShift = 0x1U, /*!< Disable shifter start bit, transmitter loads - data on first shift. */ - kFLEXIO_ShifterStartBitLow = 0x2U, /*!< Set shifter start bit to logic low level. */ - kFLEXIO_ShifterStartBitHigh = 0x3U, /*!< Set shifter start bit to logic high level. */ -} flexio_shifter_start_bit_t; - -/*! @brief Define FlexIO shifter buffer type*/ -typedef enum _flexio_shifter_buffer_type -{ - kFLEXIO_ShifterBuffer = 0x0U, /*!< Shifter Buffer N Register. */ - kFLEXIO_ShifterBufferBitSwapped = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */ - kFLEXIO_ShifterBufferByteSwapped = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */ - kFLEXIO_ShifterBufferBitByteSwapped = 0x3U, /*!< Shifter Buffer N Bit Swapped Register. */ -#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP - kFLEXIO_ShifterBufferNibbleByteSwapped = 0x4U, /*!< Shifter Buffer N Nibble Byte Swapped Register. */ -#endif /*FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP*/ -#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP - kFLEXIO_ShifterBufferHalfWordSwapped = 0x5U, /*!< Shifter Buffer N Half Word Swapped Register. */ -#endif -#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP - kFLEXIO_ShifterBufferNibbleSwapped = 0x6U, /*!< Shifter Buffer N Nibble Swapped Register. */ -#endif -} flexio_shifter_buffer_type_t; - -/*! @brief Define FlexIO user configuration structure. */ -typedef struct _flexio_config_ -{ - bool enableFlexio; /*!< Enable/disable FlexIO module */ - bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode */ - bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode */ - bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires - the FlexIO clock to be at least twice the frequency of the bus clock. */ -} flexio_config_t; - -/*! @brief Define FlexIO timer configuration structure. */ -typedef struct _flexio_timer_config -{ - /* Trigger. */ - uint32_t triggerSelect; /*!< The internal trigger selection number using MACROs. */ - flexio_timer_trigger_polarity_t triggerPolarity; /*!< Trigger Polarity. */ - flexio_timer_trigger_source_t triggerSource; /*!< Trigger Source, internal (see 'trgsel') or external. */ - /* Pin. */ - flexio_pin_config_t pinConfig; /*!< Timer Pin Configuration. */ - uint32_t pinSelect; /*!< Timer Pin number Select. */ - flexio_pin_polarity_t pinPolarity; /*!< Timer Pin Polarity. */ - /* Timer. */ - flexio_timer_mode_t timerMode; /*!< Timer work Mode. */ - flexio_timer_output_t timerOutput; /*!< Configures the initial state of the Timer Output and - whether it is affected by the Timer reset. */ - flexio_timer_decrement_source_t timerDecrement; /*!< Configures the source of the Timer decrement and the - source of the Shift clock. */ - flexio_timer_reset_condition_t timerReset; /*!< Configures the condition that causes the timer counter - (and optionally the timer output) to be reset. */ - flexio_timer_disable_condition_t timerDisable; /*!< Configures the condition that causes the Timer to be - disabled and stop decrementing. */ - flexio_timer_enable_condition_t timerEnable; /*!< Configures the condition that causes the Timer to be - enabled and start decrementing. */ - flexio_timer_stop_bit_condition_t timerStop; /*!< Timer STOP Bit generation. */ - flexio_timer_start_bit_condition_t timerStart; /*!< Timer STRAT Bit generation. */ - uint32_t timerCompare; /*!< Value for Timer Compare N Register. */ -} flexio_timer_config_t; - -/*! @brief Define FlexIO shifter configuration structure. */ -typedef struct _flexio_shifter_config -{ - /* Timer. */ - uint32_t timerSelect; /*!< Selects which Timer is used for controlling the - logic/shift register and generating the Shift clock. */ - flexio_shifter_timer_polarity_t timerPolarity; /*!< Timer Polarity. */ - /* Pin. */ - flexio_pin_config_t pinConfig; /*!< Shifter Pin Configuration. */ - uint32_t pinSelect; /*!< Shifter Pin number Select. */ - flexio_pin_polarity_t pinPolarity; /*!< Shifter Pin Polarity. */ - /* Shifter. */ - flexio_shifter_mode_t shifterMode; /*!< Configures the mode of the Shifter. */ -#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH - uint32_t parallelWidth; /*!< Configures the parallel width when using parallel mode.*/ -#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ - flexio_shifter_input_source_t inputSource; /*!< Selects the input source for the shifter. */ - flexio_shifter_stop_bit_t shifterStop; /*!< Shifter STOP bit. */ - flexio_shifter_start_bit_t shifterStart; /*!< Shifter START bit. */ -} flexio_shifter_config_t; - -/*! @brief typedef for FlexIO simulated driver interrupt handler.*/ -typedef void (*flexio_isr_t)(void *base, void *handle); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to flexio bases for each instance. */ -extern FLEXIO_Type *const s_flexioBases[]; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to flexio clocks for each instance. */ -extern const clock_ip_name_t s_flexioClocks[]; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name FlexIO Initialization and De-initialization - * @{ - */ - -/*! - * @brief Gets the default configuration to configure the FlexIO module. The configuration - * can used directly to call the FLEXIO_Configure(). - * - * Example: - @code - flexio_config_t config; - FLEXIO_GetDefaultConfig(&config); - @endcode - * - * @param userConfig pointer to flexio_config_t structure -*/ -void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig); - -/*! - * @brief Configures the FlexIO with a FlexIO configuration. The configuration structure - * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig(). - * - * Example - @code - flexio_config_t config = { - .enableFlexio = true, - .enableInDoze = false, - .enableInDebug = true, - .enableFastAccess = false - }; - FLEXIO_Configure(base, &config); - @endcode - * - * @param base FlexIO peripheral base address - * @param userConfig pointer to flexio_config_t structure -*/ -void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig); - -/*! - * @brief Gates the FlexIO clock. Call this API to stop the FlexIO clock. - * - * @note After calling this API, call the FLEXO_Init to use the FlexIO module. - * - * @param base FlexIO peripheral base address -*/ -void FLEXIO_Deinit(FLEXIO_Type *base); - -/*! - * @brief Get instance number for FLEXIO module. - * - * @param base FLEXIO peripheral base address. - */ -uint32_t FLEXIO_GetInstance(FLEXIO_Type *base); - -/* @} */ - -/*! - * @name FlexIO Basic Operation - * @{ - */ - -/*! - * @brief Resets the FlexIO module. - * - * @param base FlexIO peripheral base address -*/ -void FLEXIO_Reset(FLEXIO_Type *base); - -/*! - * @brief Enables the FlexIO module operation. - * - * @param base FlexIO peripheral base address - * @param enable true to enable, false to disable. -*/ -static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; - } - else - { - base->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; - } -} - -#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS -/*! - * @brief Reads the input data on each of the FlexIO pins. - * - * @param base FlexIO peripheral base address - * @return FlexIO pin input data -*/ -static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base) -{ - return base->PIN; -} -#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ - -#if defined(FSL_FEATURE_FLEXIO_HAS_STATE_MODE) && FSL_FEATURE_FLEXIO_HAS_STATE_MODE -/*! - * @brief Gets the current state pointer for state mode use. - * - * @param base FlexIO peripheral base address - * @return current State pointer -*/ -static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base) -{ - return ((base->SHIFTSTATE) & FLEXIO_SHIFTSTATE_STATE_MASK); -} -#endif /*FSL_FEATURE_FLEXIO_HAS_STATE_MODE*/ - -/*! - * @brief Configures the shifter with the shifter configuration. The configuration structure - * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper - * mode, select which timer controls the shifter to shift, whether to generate start bit/stop - * bit, and the polarity of start bit and stop bit. - * - * Example - @code - flexio_shifter_config_t config = { - .timerSelect = 0, - .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, - .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, - .pinPolarity = kFLEXIO_PinActiveLow, - .shifterMode = kFLEXIO_ShifterModeTransmit, - .inputSource = kFLEXIO_ShifterInputFromPin, - .shifterStop = kFLEXIO_ShifterStopBitHigh, - .shifterStart = kFLEXIO_ShifterStartBitLow - }; - FLEXIO_SetShifterConfig(base, &config); - @endcode - * - * @param base FlexIO peripheral base address - * @param index Shifter index - * @param shifterConfig Pointer to flexio_shifter_config_t structure -*/ -void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig); -/*! - * @brief Configures the timer with the timer configuration. The configuration structure - * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper - * mode, select trigger source for timer and the timer pin output and the timing for timer. - * - * Example - @code - flexio_timer_config_t config = { - .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), - .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, - .triggerSource = kFLEXIO_TimerTriggerSourceInternal, - .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, - .pinSelect = 0, - .pinPolarity = kFLEXIO_PinActiveHigh, - .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, - .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, - .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, - .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, - .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, - .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, - .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, - .timerStart = kFLEXIO_TimerStartBitEnabled - }; - FLEXIO_SetTimerConfig(base, &config); - @endcode - * - * @param base FlexIO peripheral base address - * @param index Timer index - * @param timerConfig Pointer to the flexio_timer_config_t structure -*/ -void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig); - -/* @} */ - -/*! - * @name FlexIO Interrupt Operation - * @{ - */ - -/*! - * @brief Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set. - * - * @param base FlexIO peripheral base address - * @param mask The shifter status mask which can be calculated by (1 << shifter index) - * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ -static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) -{ - base->SHIFTSIEN |= mask; -} - -/*! - * @brief Disables the shifter status interrupt. The interrupt won't generate when the corresponding SSF is set. - * - * @param base FlexIO peripheral base address - * @param mask The shifter status mask which can be calculated by (1 << shifter index) - * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ -static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) -{ - base->SHIFTSIEN &= ~mask; -} - -/*! - * @brief Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set. - * - * @param base FlexIO peripheral base address - * @param mask The shifter error mask which can be calculated by (1 << shifter index) - * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ -static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) -{ - base->SHIFTEIEN |= mask; -} - -/*! - * @brief Disables the shifter error interrupt. The interrupt won't generate when the corresponding SEF is set. - * - * @param base FlexIO peripheral base address - * @param mask The shifter error mask which can be calculated by (1 << shifter index) - * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ -static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) -{ - base->SHIFTEIEN &= ~mask; -} - -/*! - * @brief Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set. - * - * @param base FlexIO peripheral base address - * @param mask The timer status mask which can be calculated by (1 << timer index) - * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate - * the mask by using ((1 << timer index0) | (1 << timer index1)) -*/ -static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) -{ - base->TIMIEN |= mask; -} - -/*! - * @brief Disables the timer status interrupt. The interrupt won't generate when the corresponding SSF is set. - * - * @param base FlexIO peripheral base address - * @param mask The timer status mask which can be calculated by (1 << timer index) - * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate - * the mask by using ((1 << timer index0) | (1 << timer index1)) -*/ -static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) -{ - base->TIMIEN &= ~mask; -} - -/* @} */ - -/*! - * @name FlexIO Status Operation - * @{ - */ - -/*! - * @brief Gets the shifter status flags. - * - * @param base FlexIO peripheral base address - * @return Shifter status flags -*/ -static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base) -{ - return ((base->SHIFTSTAT) & FLEXIO_SHIFTSTAT_SSF_MASK); -} - -/*! - * @brief Clears the shifter status flags. - * - * @param base FlexIO peripheral base address - * @param mask The shifter status mask which can be calculated by (1 << shifter index) - * @note For clearing multiple shifter status flags, for example, two shifter status flags, can calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ -static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask) -{ - base->SHIFTSTAT = mask; -} - -/*! - * @brief Gets the shifter error flags. - * - * @param base FlexIO peripheral base address - * @return Shifter error flags -*/ -static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base) -{ - return ((base->SHIFTERR) & FLEXIO_SHIFTERR_SEF_MASK); -} - -/*! - * @brief Clears the shifter error flags. - * - * @param base FlexIO peripheral base address - * @param mask The shifter error mask which can be calculated by (1 << shifter index) - * @note For clearing multiple shifter error flags, for example, two shifter error flags, can calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ -static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask) -{ - base->SHIFTERR = mask; -} - -/*! - * @brief Gets the timer status flags. - * - * @param base FlexIO peripheral base address - * @return Timer status flags -*/ -static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base) -{ - return ((base->TIMSTAT) & FLEXIO_TIMSTAT_TSF_MASK); -} - -/*! - * @brief Clears the timer status flags. - * - * @param base FlexIO peripheral base address - * @param mask The timer status mask which can be calculated by (1 << timer index) - * @note For clearing multiple timer status flags, for example, two timer status flags, can calculate - * the mask by using ((1 << timer index0) | (1 << timer index1)) -*/ -static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask) -{ - base->TIMSTAT = mask; -} - -/* @} */ - -/*! - * @name FlexIO DMA Operation - * @{ - */ - -/*! - * @brief Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set. - * - * @note For multiple shifter status DMA enables, for example, calculate - * the mask by using ((1 << shifter index0) | (1 << shifter index1)) - * - * @param base FlexIO peripheral base address - * @param mask The shifter status mask which can be calculated by (1 << shifter index) - * @param enable True to enable, false to disable. -*/ -static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable) -{ - if (enable) - { - base->SHIFTSDEN |= mask; - } - else - { - base->SHIFTSDEN &= ~mask; - } -} - -/*! - * @brief Gets the shifter buffer address for the DMA transfer usage. - * - * @param base FlexIO peripheral base address - * @param type Shifter type of flexio_shifter_buffer_type_t - * @param index Shifter index - * @return Corresponding shifter buffer index -*/ -uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index); - -/*! - * @brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral. - * - * @param base Pointer to the FlexIO simulated peripheral type. - * @param handle Pointer to the handler for FlexIO simulated peripheral. - * @param isr FlexIO simulated peripheral interrupt handler. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. -*/ -status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr); - -/*! - * @brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral. - * - * @param base Pointer to the FlexIO simulated peripheral type. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. -*/ -status_t FLEXIO_UnregisterHandleIRQ(void *base); -/* @} */ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ -/*@}*/ - -#endif /*_FSL_FLEXIO_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2c_master.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2c_master.c deleted file mode 100644 index 3d3ca0d657..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2c_master.c +++ /dev/null @@ -1,818 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flexio_i2c_master.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexio_i2c_master" -#endif - - -/*! @brief FLEXIO I2C transfer state */ -enum _flexio_i2c_master_transfer_states -{ - kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */ - kFLEXIO_I2C_CheckAddress = 0x1U, /*!< 7-bit address check state */ - kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */ - kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/ - kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/ - kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/ -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Set up master transfer, send slave address and decide the initial - * transfer state. - * - * @param base pointer to FLEXIO_I2C_Type structure - * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state - * @param transfer pointer to flexio_i2c_master_transfer_t structure - */ -static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - flexio_i2c_master_transfer_t *xfer); - -/*! - * @brief Master run transfer state machine to perform a byte of transfer. - * - * @param base pointer to FLEXIO_I2C_Type structure - * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state - * @param statusFlags flexio i2c hardware status - * @retval kStatus_Success Successfully run state machine - * @retval kStatus_FLEXIO_I2C_Nak Receive Nak during transfer - */ -static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - uint32_t statusFlags); - -/*! - * @brief Complete transfer, disable interrupt and call callback. - * - * @param base pointer to FLEXIO_I2C_Type structure - * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state - * @param status flexio transfer status - */ -static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - status_t status); - -/******************************************************************************* - * Codes - ******************************************************************************/ - -static uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base) -{ - return FLEXIO_GetInstance(base->flexioBase); -} - -static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - flexio_i2c_master_transfer_t *xfer) -{ - bool needRestart; - uint32_t byteCount; - - /* Init the handle member. */ - handle->transfer.slaveAddress = xfer->slaveAddress; - handle->transfer.direction = xfer->direction; - handle->transfer.subaddress = xfer->subaddress; - handle->transfer.subaddressSize = xfer->subaddressSize; - handle->transfer.data = xfer->data; - handle->transfer.dataSize = xfer->dataSize; - handle->transfer.flags = xfer->flags; - handle->transferSize = xfer->dataSize; - - /* Initial state, i2c check address state. */ - handle->state = kFLEXIO_I2C_CheckAddress; - - /* Clear all status before transfer. */ - FLEXIO_I2C_MasterClearStatusFlags(base, kFLEXIO_I2C_ReceiveNakFlag); - - /* Calculate whether need to send re-start. */ - needRestart = (handle->transfer.subaddressSize != 0) && (handle->transfer.direction == kFLEXIO_I2C_Read); - - /* Calculate total byte count in a frame. */ - byteCount = 1; - - if (!needRestart) - { - byteCount += handle->transfer.dataSize; - } - - if (handle->transfer.subaddressSize != 0) - { - byteCount += handle->transfer.subaddressSize; - /* Next state, send command byte. */ - handle->state = kFLEXIO_I2C_SendCommand; - } - - /* Configure data count. */ - if (FLEXIO_I2C_MasterSetTransferCount(base, byteCount) != kStatus_Success) - { - return kStatus_InvalidArgument; - } - - while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) - { - } - - /* Send address byte first. */ - if (needRestart) - { - FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Write); - } - else - { - FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, handle->transfer.direction); - } - - return kStatus_Success; -} - -static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - uint32_t statusFlags) -{ - if (statusFlags & kFLEXIO_I2C_ReceiveNakFlag) - { - /* Clear receive nak flag. */ - FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); - - if ((!((handle->state == kFLEXIO_I2C_SendData) && (handle->transfer.dataSize == 0U))) && - (!(((handle->state == kFLEXIO_I2C_ReceiveData) || (handle->state == kFLEXIO_I2C_ReceiveDataBegin)) && - (handle->transfer.dataSize == 1U)))) - { - FLEXIO_I2C_MasterReadByte(base); - - FLEXIO_I2C_MasterAbortStop(base); - - handle->state = kFLEXIO_I2C_Idle; - - return kStatus_FLEXIO_I2C_Nak; - } - } - - if (handle->state == kFLEXIO_I2C_CheckAddress) - { - if (handle->transfer.direction == kFLEXIO_I2C_Write) - { - /* Next state, send data. */ - handle->state = kFLEXIO_I2C_SendData; - } - else - { - /* Next state, receive data begin. */ - handle->state = kFLEXIO_I2C_ReceiveDataBegin; - } - } - - if ((statusFlags & kFLEXIO_I2C_RxFullFlag) && (handle->state != kFLEXIO_I2C_ReceiveData)) - { - FLEXIO_I2C_MasterReadByte(base); - } - - switch (handle->state) - { - case kFLEXIO_I2C_SendCommand: - if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) - { - if (handle->transfer.subaddressSize > 0) - { - handle->transfer.subaddressSize--; - FLEXIO_I2C_MasterWriteByte( - base, ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize))); - - if (handle->transfer.subaddressSize == 0) - { - /* Load re-start in advance. */ - if (handle->transfer.direction == kFLEXIO_I2C_Read) - { - while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) - { - } - FLEXIO_I2C_MasterRepeatedStart(base); - } - } - } - else - { - if (handle->transfer.direction == kFLEXIO_I2C_Write) - { - /* Next state, send data. */ - handle->state = kFLEXIO_I2C_SendData; - - /* Send first byte of data. */ - if (handle->transfer.dataSize > 0) - { - FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); - - handle->transfer.data++; - handle->transfer.dataSize--; - } - } - else - { - FLEXIO_I2C_MasterSetTransferCount(base, (handle->transfer.dataSize + 1)); - FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Read); - - /* Next state, receive data begin. */ - handle->state = kFLEXIO_I2C_ReceiveDataBegin; - } - } - } - break; - - /* Send command byte. */ - case kFLEXIO_I2C_SendData: - if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) - { - /* Send one byte of data. */ - if (handle->transfer.dataSize > 0) - { - FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); - - handle->transfer.data++; - handle->transfer.dataSize--; - } - else - { - FLEXIO_I2C_MasterStop(base); - - while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag)) - { - } - FLEXIO_I2C_MasterReadByte(base); - - handle->state = kFLEXIO_I2C_Idle; - } - } - break; - - case kFLEXIO_I2C_ReceiveDataBegin: - if (statusFlags & kFLEXIO_I2C_RxFullFlag) - { - handle->state = kFLEXIO_I2C_ReceiveData; - /* Send nak at the last receive byte. */ - if (handle->transfer.dataSize == 1) - { - FLEXIO_I2C_MasterEnableAck(base, false); - while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) - { - } - FLEXIO_I2C_MasterStop(base); - } - else - { - FLEXIO_I2C_MasterEnableAck(base, true); - } - } - else if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) - { - /* Read one byte of data. */ - FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); - } - else - { - } - break; - - case kFLEXIO_I2C_ReceiveData: - if (statusFlags & kFLEXIO_I2C_RxFullFlag) - { - *handle->transfer.data = FLEXIO_I2C_MasterReadByte(base); - handle->transfer.data++; - if (handle->transfer.dataSize--) - { - if (handle->transfer.dataSize == 0) - { - FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_RxFullInterruptEnable); - handle->state = kFLEXIO_I2C_Idle; - } - - /* Send nak at the last receive byte. */ - if (handle->transfer.dataSize == 1) - { - FLEXIO_I2C_MasterEnableAck(base, false); - while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) - { - } - FLEXIO_I2C_MasterStop(base); - } - } - } - else if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) - { - if (handle->transfer.dataSize > 1) - { - FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); - } - } - else - { - } - break; - - default: - break; - } - - return kStatus_Success; -} - -static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - status_t status) -{ - FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); - - if (handle->completionCallback) - { - handle->completionCallback(base, handle, status, handle->userData); - } -} - -status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - assert(base && masterConfig); - - flexio_shifter_config_t shifterConfig; - flexio_timer_config_t timerConfig; - uint32_t controlVal = 0; - uint16_t timerDiv = 0; - status_t result = kStatus_Success; - - memset(&shifterConfig, 0, sizeof(shifterConfig)); - memset(&timerConfig, 0, sizeof(timerConfig)); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate flexio clock. */ - CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2C_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Do hardware configuration. */ - /* 1. Configure the shifter 0 for tx. */ - shifterConfig.timerSelect = base->timerIndex[1]; - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; - shifterConfig.pinSelect = base->SDAPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveLow; - shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); - - /* 2. Configure the shifter 1 for rx. */ - shifterConfig.timerSelect = base->timerIndex[1]; - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinSelect = base->SDAPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); - - /*3. Configure the timer 0 for generating bit clock. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; - timerConfig.pinSelect = base->SCLPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - - /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1. */ - timerDiv = (srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1; - - if (timerDiv > 0xFFU) - { - result = kStatus_InvalidArgument; - return result; - } - - timerConfig.timerCompare = timerDiv; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); - - /* 4. Configure the timer 1 for controlling shifters. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->SCLPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveLow; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - - /* Set TIMCMP[15:0] = (number of bits x 2) - 1. */ - timerConfig.timerCompare = 8 * 2 - 1; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); - - /* Configure FLEXIO I2C Master. */ - controlVal = base->flexioBase->CTRL; - controlVal &= - ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); - controlVal |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | - FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); - if (!masterConfig->enableInDoze) - { - controlVal |= FLEXIO_CTRL_DOZEN_MASK; - } - - base->flexioBase->CTRL = controlVal; - return result; -} - -void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base) -{ - base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; - base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; - base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; - base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; - base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; - base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; - base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; - base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; - base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; - base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; - /* Clear the shifter flag. */ - base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]); - base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]); - /* Clear the timer flag. */ - base->flexioBase->TIMSTAT = (1U << base->timerIndex[0]); - base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]); -} - -void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig) -{ - assert(masterConfig); - - masterConfig->enableMaster = true; - masterConfig->enableInDoze = false; - masterConfig->enableInDebug = true; - masterConfig->enableFastAccess = false; - - /* Default baud rate at 100kbps. */ - masterConfig->baudRate_Bps = 100000U; -} - -uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base) -{ - uint32_t status = 0; - - status = - ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); - status |= - (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) - << 1U); - status |= - (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) - << 2U); - - return status; -} - -void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_I2C_TxEmptyFlag) - { - FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); - } - - if (mask & kFLEXIO_I2C_RxFullFlag) - { - FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); - } - - if (mask & kFLEXIO_I2C_ReceiveNakFlag) - { - FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); - } - if (mask & kFLEXIO_I2C_RxFullInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); - } - if (mask & kFLEXIO_I2C_RxFullInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - uint16_t timerDiv = 0; - uint16_t timerCmp = 0; - FLEXIO_Type *flexioBase = base->flexioBase; - - /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ - timerDiv = srcClock_Hz / baudRate_Bps; - timerDiv = timerDiv / 2 - 1U; - - timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; - timerCmp &= 0xFF00; - timerCmp |= timerDiv; - - flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; -} - -status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count) -{ - if (count > 14U) - { - return kStatus_InvalidArgument; - } - - uint16_t timerCmp = 0; - uint32_t timerConfig = 0; - FLEXIO_Type *flexioBase = base->flexioBase; - - timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; - timerCmp &= 0x00FFU; - timerCmp |= (count * 18 + 1U) << 8U; - flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; - timerConfig = flexioBase->TIMCFG[base->timerIndex[0]]; - timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; - timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); - flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig; - - return kStatus_Success; -} - -void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction) -{ - uint32_t data; - - data = ((uint32_t)address) << 1U | ((direction == kFLEXIO_I2C_Read) ? 1U : 0U); - - FLEXIO_I2C_MasterWriteByte(base, data); -} - -void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base) -{ - /* Prepare for RESTART condition, no stop.*/ - FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); -} - -void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base) -{ - /* Prepare normal stop. */ - FLEXIO_I2C_MasterSetTransferCount(base, 0x0U); - FLEXIO_I2C_MasterWriteByte(base, 0x0U); -} - -void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base) -{ - uint32_t tmpConfig; - - /* Prepare abort stop. */ - tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[0]]; - tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; - tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge); - base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig; -} - -void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable) -{ - uint32_t tmpConfig = 0; - - tmpConfig = base->flexioBase->SHIFTCFG[base->shifterIndex[0]]; - tmpConfig &= ~FLEXIO_SHIFTCFG_SSTOP_MASK; - if (enable) - { - tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitLow); - } - else - { - tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitHigh); - } - base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig; -} - -status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize) -{ - assert(txBuff); - assert(txSize); - - uint32_t status; - - while (txSize--) - { - FLEXIO_I2C_MasterWriteByte(base, *txBuff++); - - /* Wait until data transfer complete. */ - while (!((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & kFLEXIO_I2C_RxFullFlag)) - { - } - - if (status & kFLEXIO_I2C_ReceiveNakFlag) - { - FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); - return kStatus_FLEXIO_I2C_Nak; - } - } - return kStatus_Success; -} - -void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize) -{ - assert(rxBuff); - assert(rxSize); - - while (rxSize--) - { - /* Wait until data transfer complete. */ - while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag)) - { - } - - *rxBuff++ = FLEXIO_I2C_MasterReadByte(base); - } -} - -status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer) -{ - assert(xfer); - - flexio_i2c_master_handle_t tmpHandle; - uint32_t statusFlags; - uint32_t result = kStatus_Success; - - /* Zero the handle. */ - memset(&tmpHandle, 0, sizeof(tmpHandle)); - - /* Set up transfer machine. */ - FLEXIO_I2C_MasterTransferInitStateMachine(base, &tmpHandle, xfer); - - do - { - /* Wait either tx empty or rx full flag is asserted. */ - while (!((statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base)) & - (kFLEXIO_I2C_TxEmptyFlag | kFLEXIO_I2C_RxFullFlag))) - { - } - - result = FLEXIO_I2C_MasterTransferRunStateMachine(base, &tmpHandle, statusFlags); - - } while ((tmpHandle.state != kFLEXIO_I2C_Idle) && (result == kStatus_Success)); - - return result; -} - -status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - flexio_i2c_master_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - IRQn_Type flexio_irqs[] = FLEXIO_IRQS; - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Register callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Enable interrupt in NVIC. */ - EnableIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]); - - /* Save the context in global variables to support the double weak mechanism. */ - return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ); -} - -status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - flexio_i2c_master_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - if (handle->state != kFLEXIO_I2C_Idle) - { - return kStatus_FLEXIO_I2C_Busy; - } - else - { - /* Set up transfer machine. */ - FLEXIO_I2C_MasterTransferInitStateMachine(base, handle, xfer); - - /* Enable both tx empty and rxfull interrupt. */ - FLEXIO_I2C_MasterEnableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); - - return kStatus_Success; - } -} - -void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle) -{ - assert(handle); - - /* Disable interrupts. */ - FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); - - /* Reset to idle state. */ - handle->state = kFLEXIO_I2C_Idle; -} - -status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count) -{ - if (!count) - { - return kStatus_InvalidArgument; - } - - *count = handle->transferSize - handle->transfer.dataSize; - - return kStatus_Success; -} - -void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle) -{ - FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType; - flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle; - uint32_t statusFlags; - status_t result; - - statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base); - - result = FLEXIO_I2C_MasterTransferRunStateMachine(base, handle, statusFlags); - - if (handle->state == kFLEXIO_I2C_Idle) - { - FLEXIO_I2C_MasterTransferComplete(base, handle, result); - } -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2c_master.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2c_master.h deleted file mode 100644 index 5e6ee2b9bf..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2c_master.h +++ /dev/null @@ -1,487 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_FLEXIO_I2C_MASTER_H_ -#define _FSL_FLEXIO_I2C_MASTER_H_ - -#include "fsl_common.h" -#include "fsl_flexio.h" - -/*! - * @addtogroup flexio_i2c_master - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexIO I2C master driver version 2.1.5. */ -#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) -/*@}*/ - -/*! @brief FlexIO I2C transfer status*/ -enum _flexio_i2c_status -{ - kStatus_FLEXIO_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 0), /*!< I2C is busy doing transfer. */ - kStatus_FLEXIO_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 1), /*!< I2C is busy doing transfer. */ - kStatus_FLEXIO_I2C_Nak = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2), /*!< NAK received during transfer. */ -}; - -/*! @brief Define FlexIO I2C master interrupt mask. */ -enum _flexio_i2c_master_interrupt -{ - kFLEXIO_I2C_TxEmptyInterruptEnable = 0x1U, /*!< Tx buffer empty interrupt enable. */ - kFLEXIO_I2C_RxFullInterruptEnable = 0x2U, /*!< Rx buffer full interrupt enable. */ -}; - -/*! @brief Define FlexIO I2C master status mask. */ -enum _flexio_i2c_master_status_flags -{ - kFLEXIO_I2C_TxEmptyFlag = 0x1U, /*!< Tx shifter empty flag. */ - kFLEXIO_I2C_RxFullFlag = 0x2U, /*!< Rx shifter full/Transfer complete flag. */ - kFLEXIO_I2C_ReceiveNakFlag = 0x4U, /*!< Receive NAK flag. */ -}; - -/*! @brief Direction of master transfer.*/ -typedef enum _flexio_i2c_direction -{ - kFLEXIO_I2C_Write = 0x0U, /*!< Master send to slave. */ - kFLEXIO_I2C_Read = 0x1U, /*!< Master receive from slave. */ -} flexio_i2c_direction_t; - -/*! @brief Define FlexIO I2C master access structure typedef. */ -typedef struct _flexio_i2c_type -{ - FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ - uint8_t SDAPinIndex; /*!< Pin select for I2C SDA. */ - uint8_t SCLPinIndex; /*!< Pin select for I2C SCL. */ - uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO I2C. */ - uint8_t timerIndex[2]; /*!< Timer index used in FlexIO I2C. */ -} FLEXIO_I2C_Type; - -/*! @brief Define FlexIO I2C master user configuration structure. */ -typedef struct _flexio_i2c_master_config -{ - bool enableMaster; /*!< Enables the FlexIO I2C peripheral at initialization time. */ - bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ - bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ - bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires - the FlexIO clock to be at least twice the frequency of the bus clock. */ - uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ -} flexio_i2c_master_config_t; - -/*! @brief Define FlexIO I2C master transfer structure. */ -typedef struct _flexio_i2c_master_transfer -{ - uint32_t flags; /*!< Transfer flag which controls the transfer, reserved for FlexIO I2C. */ - uint8_t slaveAddress; /*!< 7-bit slave address. */ - flexio_i2c_direction_t direction; /*!< Transfer direction, read or write. */ - uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ - uint8_t subaddressSize; /*!< Size of command buffer. */ - uint8_t volatile *data; /*!< Transfer buffer. */ - volatile size_t dataSize; /*!< Transfer size. */ -} flexio_i2c_master_transfer_t; - -/*! @brief FlexIO I2C master handle typedef. */ -typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t; - -/*! @brief FlexIO I2C master transfer callback typedef. */ -typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Define FlexIO I2C master handle structure. */ -struct _flexio_i2c_master_handle -{ - flexio_i2c_master_transfer_t transfer; /*!< FlexIO I2C master transfer copy. */ - size_t transferSize; /*!< Total bytes to be transferred. */ - uint8_t state; /*!< Transfer state maintained during transfer. */ - flexio_i2c_master_transfer_callback_t completionCallback; /*!< Callback function called at transfer event. */ - /*!< Callback function called at transfer event. */ - void *userData; /*!< Callback parameter passed to callback function. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C - * hardware configuration. - * - * Example - @code - FLEXIO_I2C_Type base = { - .flexioBase = FLEXIO, - .SDAPinIndex = 0, - .SCLPinIndex = 1, - .shifterIndex = {0,1}, - .timerIndex = {0,1} - }; - flexio_i2c_master_config_t config = { - .enableInDoze = false, - .enableInDebug = true, - .enableFastAccess = false, - .baudRate_Bps = 100000 - }; - FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz); - @endcode - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param masterConfig Pointer to flexio_i2c_master_config_t structure. - * @param srcClock_Hz FlexIO source clock in Hz. - * @retval kStatus_Success Initialization successful - * @retval kStatus_InvalidArgument The source clock exceed upper range limitation -*/ -status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master - * shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called. - * - * @param base pointer to FLEXIO_I2C_Type structure. - */ -void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base); - -/*! - * @brief Gets the default configuration to configure the FlexIO module. The configuration - * can be used directly for calling the FLEXIO_I2C_MasterInit(). - * - * Example: - @code - flexio_i2c_master_config_t config; - FLEXIO_I2C_MasterGetDefaultConfig(&config); - @endcode - * @param masterConfig Pointer to flexio_i2c_master_config_t structure. -*/ -void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig); - -/*! - * @brief Enables/disables the FlexIO module operation. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param enable Pass true to enable module, false does not have any effect. -*/ -static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable) -{ - if (enable) - { - base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; - } -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the FlexIO I2C master status flags. - * - * @param base Pointer to FLEXIO_I2C_Type structure - * @return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status. -*/ - -uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base); - -/*! - * @brief Clears the FlexIO I2C master status flags. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param mask Status flag. - * The parameter can be any combination of the following values: - * @arg kFLEXIO_I2C_RxFullFlag - * @arg kFLEXIO_I2C_ReceiveNakFlag -*/ - -void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask); - -/*@}*/ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the FlexIO i2c master interrupt requests. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param mask Interrupt source. - * Currently only one interrupt request source: - * @arg kFLEXIO_I2C_TransferCompleteInterruptEnable - */ -void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); - -/*! - * @brief Disables the FlexIO I2C master interrupt requests. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param mask Interrupt source. - */ -void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); - -/*@}*/ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Sets the FlexIO I2C master transfer baudrate. - * - * @param base Pointer to FLEXIO_I2C_Type structure - * @param baudRate_Bps the baud rate value in HZ - * @param srcClock_Hz source clock in HZ - */ -void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/*! - * @brief Sends START + 7-bit address to the bus. - * - * @note This API should be called when the transfer configuration is ready to send a START signal - * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address - * is put into the data register but the address transfer is not finished on the bus. Ensure that - * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API. - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param address 7-bit address. - * @param direction transfer direction. - * This parameter is one of the values in flexio_i2c_direction_t: - * @arg kFLEXIO_I2C_Write: Transmit - * @arg kFLEXIO_I2C_Read: Receive - */ - -void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction); - -/*! - * @brief Sends the stop signal on the bus. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - */ -void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base); - -/*! - * @brief Sends the repeated start signal on the bus. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - */ -void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base); - -/*! - * @brief Sends the stop signal when transfer is still on-going. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - */ -void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base); - -/*! - * @brief Configures the sent ACK/NAK for the following byte. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param enable True to configure send ACK, false configure to send NAK. - */ -void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable); - -/*! - * @brief Sets the number of bytes to be transferred from a start signal to a stop signal. - * - * @note Call this API before a transfer begins because the timer generates a number of clocks according - * to the number of bytes that need to be transferred. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param count Number of bytes need to be transferred from a start signal to a re-start/stop signal - * @retval kStatus_Success Successfully configured the count. - * @retval kStatus_InvalidArgument Input argument is invalid. -*/ -status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count); - -/*! - * @brief Writes one byte of data to the I2C bus. - * - * @note This is a non-blocking API, which returns directly after the data is put into the - * data register but the data transfer is not finished on the bus. Ensure that - * the TxEmptyFlag is asserted before calling this API. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param data a byte of data. - */ -static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data) -{ - base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; -} - -/*! - * @brief Reads one byte of data from the I2C bus. - * - * @note This is a non-blocking API, which returns directly after the data is read from the - * data register. Ensure that the data is ready in the register. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @return data byte read. - */ -static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base) -{ - return base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]; -} - -/*! - * @brief Sends a buffer of data in bytes. - * - * @note This function blocks via polling until all bytes have been sent. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param txBuff The data bytes to send. - * @param txSize The number of data bytes to send. - * @retval kStatus_Success Successfully write data. - * @retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data. - */ -status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize); - -/*! - * @brief Receives a buffer of bytes. - * - * @note This function blocks via polling until all bytes have been received. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param rxBuff The buffer to store the received bytes. - * @param rxSize The number of data bytes to be received. - */ -void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize); - -/*! - * @brief Performs a master polling transfer on the I2C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to receiving NAK. - * - * @param base pointer to FLEXIO_I2C_Type structure. - * @param xfer pointer to flexio_i2c_master_transfer_t structure. - * @return status of status_t. - */ -status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer); -/*@}*/ - -/*Transactional APIs*/ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the I2C handle which is used in transactional functions. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state. - * @param callback Pointer to user callback function. - * @param userData User param passed to the callback function. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range. - */ -status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - flexio_i2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a master interrupt non-blocking transfer on the I2C bus. - * - * @note The API returns immediately after the transfer initiates. - * Call FLEXIO_I2C_MasterGetTransferCount to poll the transfer status to check whether - * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer - * is finished. - * - * @param base Pointer to FLEXIO_I2C_Type structure - * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state - * @param xfer pointer to flexio_i2c_master_transfer_t structure - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer. - */ -status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, - flexio_i2c_master_handle_t *handle, - flexio_i2c_master_transfer_t *xfer); - -/*! - * @brief Gets the master transfer status during a interrupt non-blocking transfer. - * - * @param base Pointer to FLEXIO_I2C_Type structure. - * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Aborts an interrupt non-blocking transfer early. - * - * @note This API can be called at any time when an interrupt non-blocking transfer initiates - * to abort the transfer early. - * - * @param base Pointer to FLEXIO_I2C_Type structure - * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state - */ -void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle); - -/*! - * @brief Master interrupt handler. - * - * @param i2cType Pointer to FLEXIO_I2C_Type structure - * @param i2cHandle Pointer to flexio_i2c_master_transfer_t structure - */ -void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ -/*@}*/ - -#endif /*_FSL_FLEXIO_I2C_MASTER_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s.c deleted file mode 100644 index 5e7bc43773..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s.c +++ /dev/null @@ -1,668 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flexio_i2s.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s" -#endif - - -/******************************************************************************* -* Definitations -******************************************************************************/ -enum _sai_transfer_state -{ - kFLEXIO_I2S_Busy = 0x0U, /*!< FLEXIO_I2S is busy */ - kFLEXIO_I2S_Idle, /*!< Transfer is done. */ -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Receive a piece of data in non-blocking way. - * - * @param base FLEXIO I2S base pointer - * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. - * @param buffer Pointer to the data to be read. - * @param size Bytes to be read. - */ -static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size); - -/*! - * @brief sends a piece of data in non-blocking way. - * - * @param base FLEXIO I2S base pointer - * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. - * @param buffer Pointer to the data to be written. - * @param size Bytes to be written. - */ -static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size); -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base) -{ - return FLEXIO_GetInstance(base->flexioBase); -} - -static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size) -{ - uint32_t i = 0; - uint8_t j = 0; - uint8_t bytesPerWord = bitWidth / 8U; - uint32_t data = 0; - uint32_t temp = 0; - - for (i = 0; i < size / bytesPerWord; i++) - { - for (j = 0; j < bytesPerWord; j++) - { - temp = (uint32_t)(*txData); - data |= (temp << (8U * j)); - txData++; - } - base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth)); - data = 0; - } -} - -static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size) -{ - uint32_t i = 0; - uint8_t j = 0; - uint8_t bytesPerWord = bitWidth / 8U; - uint32_t data = 0; - - for (i = 0; i < size / bytesPerWord; i++) - { - data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex] >> (32U - bitWidth)); - for (j = 0; j < bytesPerWord; j++) - { - *rxData = (data >> (8U * j)) & 0xFF; - rxData++; - } - } -} - -void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config) -{ - assert(base && config); - - flexio_shifter_config_t shifterConfig = {0}; - flexio_timer_config_t timerConfig = {0}; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate flexio clock. */ - CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2S_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Set shifter for I2S Tx data */ - shifterConfig.timerSelect = base->bclkTimerIndex; - shifterConfig.pinSelect = base->txPinIndex; - shifterConfig.timerPolarity = config->txTimerPolarity; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; - shifterConfig.pinPolarity = config->txPinPolarity; - shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; - if (config->masterSlave == kFLEXIO_I2S_Master) - { - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; - } - else - { - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; - } - - FLEXIO_SetShifterConfig(base->flexioBase, base->txShifterIndex, &shifterConfig); - - /* Set shifter for I2S Rx Data */ - shifterConfig.timerSelect = base->bclkTimerIndex; - shifterConfig.pinSelect = base->rxPinIndex; - shifterConfig.timerPolarity = config->rxTimerPolarity; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinPolarity = config->rxPinPolarity; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; - - FLEXIO_SetShifterConfig(base->flexioBase, base->rxShifterIndex, &shifterConfig); - - /* Set Timer to I2S frame sync */ - if (config->masterSlave == kFLEXIO_I2S_Master) - { - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->txPinIndex); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutput; - timerConfig.pinSelect = base->fsPinIndex; - timerConfig.pinPolarity = config->fsPinPolarity; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableNever; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; - timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; - } - else - { - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->fsPinIndex; - timerConfig.pinPolarity = config->fsPinPolarity; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; - timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; - } - FLEXIO_SetTimerConfig(base->flexioBase, base->fsTimerIndex, &timerConfig); - - /* Set Timer to I2S bit clock */ - if (config->masterSlave == kFLEXIO_I2S_Master) - { - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinSelect = base->bclkPinIndex; - timerConfig.pinConfig = kFLEXIO_PinConfigOutput; - timerConfig.pinPolarity = config->bclkPinPolarity; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableNever; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; - } - else - { - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinSelect = base->bclkPinIndex; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinPolarity = config->bclkPinPolarity; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompareTriggerLow; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh; - timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; - } - FLEXIO_SetTimerConfig(base->flexioBase, base->bclkTimerIndex, &timerConfig); - - /* If enable flexio I2S */ - if (config->enableI2S) - { - base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; - } - else - { - base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; - } -} - -void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config) -{ - config->masterSlave = kFLEXIO_I2S_Master; - config->enableI2S = true; - config->txPinPolarity = kFLEXIO_PinActiveHigh; - config->rxPinPolarity = kFLEXIO_PinActiveHigh; - config->bclkPinPolarity = kFLEXIO_PinActiveHigh; - config->fsPinPolarity = kFLEXIO_PinActiveLow; - config->txTimerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - config->rxTimerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; -} - -void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base) -{ - base->flexioBase->SHIFTCFG[base->txShifterIndex] = 0; - base->flexioBase->SHIFTCTL[base->txShifterIndex] = 0; - base->flexioBase->SHIFTCFG[base->rxShifterIndex] = 0; - base->flexioBase->SHIFTCTL[base->rxShifterIndex] = 0; - base->flexioBase->TIMCFG[base->fsTimerIndex] = 0; - base->flexioBase->TIMCMP[base->fsTimerIndex] = 0; - base->flexioBase->TIMCTL[base->fsTimerIndex] = 0; - base->flexioBase->TIMCFG[base->bclkTimerIndex] = 0; - base->flexioBase->TIMCMP[base->bclkTimerIndex] = 0; - base->flexioBase->TIMCTL[base->bclkTimerIndex] = 0; -} - -void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex); - } - if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex); - } -} - -uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base) -{ - uint32_t status = 0; - status = ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->txShifterIndex)) >> base->txShifterIndex); - status |= - (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex)) >> (base->rxShifterIndex)) - << 1U); - return status; -} - -void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex); - } - if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex); - } -} - -void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz) -{ - uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * 32U * 2U); - uint32_t bclkDiv = 0; - - /* Shall keep bclk and fs div an integer */ - if (timDiv % 2) - { - timDiv += 1U; - } - /* Set Frame sync timer cmp */ - base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * timDiv - 1U); - - /* Set bit clock timer cmp */ - bclkDiv = ((timDiv / 2U - 1U) | (63U << 8U)); - base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(bclkDiv); -} - -void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format) -{ - /* Set Frame sync timer cmp */ - base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 4U - 3U); - - /* Set bit clock timer cmp */ - base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 2U - 1U); -} - -void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size) -{ - uint32_t i = 0; - uint8_t bytesPerWord = bitWidth / 8U; - - for (i = 0; i < size / bytesPerWord; i++) - { - /* Wait until it can write data */ - while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0) - { - } - - FLEXIO_I2S_WriteNonBlocking(base, bitWidth, txData, bytesPerWord); - txData += bytesPerWord; - } - - /* Wait until the last data is sent */ - while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0) - { - } -} - -void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size) -{ - uint32_t i = 0; - uint8_t bytesPerWord = bitWidth / 8U; - - for (i = 0; i < size / bytesPerWord; i++) - { - /* Wait until data is received */ - while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex))) - { - } - - FLEXIO_I2S_ReadNonBlocking(base, bitWidth, rxData, bytesPerWord); - rxData += bytesPerWord; - } -} - -void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, - flexio_i2s_handle_t *handle, - flexio_i2s_callback_t callback, - void *userData) -{ - assert(handle); - - IRQn_Type flexio_irqs[] = FLEXIO_IRQS; - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Store callback and user data. */ - handle->callback = callback; - handle->userData = userData; - - /* Save the context in global variables to support the double weak mechanism. */ - FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferTxHandleIRQ); - - /* Set the TX/RX state. */ - handle->state = kFLEXIO_I2S_Idle; - - /* Enable interrupt in NVIC. */ - EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]); -} - -void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, - flexio_i2s_handle_t *handle, - flexio_i2s_callback_t callback, - void *userData) -{ - assert(handle); - - IRQn_Type flexio_irqs[] = FLEXIO_IRQS; - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Store callback and user data. */ - handle->callback = callback; - handle->userData = userData; - - /* Save the context in global variables to support the double weak mechanism. */ - FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferRxHandleIRQ); - - /* Set the TX/RX state. */ - handle->state = kFLEXIO_I2S_Idle; - - /* Enable interrupt in NVIC. */ - EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]); -} - -void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, - flexio_i2s_handle_t *handle, - flexio_i2s_format_t *format, - uint32_t srcClock_Hz) -{ - assert(handle && format); - - /* Set the bitWidth to handle */ - handle->bitWidth = format->bitWidth; - - /* Set sample rate */ - if (srcClock_Hz != 0) - { - /* It is master */ - FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz); - } - else - { - FLEXIO_I2S_SlaveSetFormat(base, format); - } -} - -status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, - flexio_i2s_handle_t *handle, - flexio_i2s_transfer_t *xfer) -{ - assert(handle); - - /* Check if the queue is full */ - if (handle->queue[handle->queueUser].data) - { - return kStatus_FLEXIO_I2S_QueueFull; - } - if ((xfer->dataSize == 0) || (xfer->data == NULL)) - { - return kStatus_InvalidArgument; - } - - /* Add into queue */ - handle->queue[handle->queueUser].data = xfer->data; - handle->queue[handle->queueUser].dataSize = xfer->dataSize; - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; - - /* Set the state to busy */ - handle->state = kFLEXIO_I2S_Busy; - - FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable); - - /* Enable Tx transfer */ - FLEXIO_I2S_Enable(base, true); - - return kStatus_Success; -} - -status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, - flexio_i2s_handle_t *handle, - flexio_i2s_transfer_t *xfer) -{ - assert(handle); - - /* Check if the queue is full */ - if (handle->queue[handle->queueUser].data) - { - return kStatus_FLEXIO_I2S_QueueFull; - } - - if ((xfer->dataSize == 0) || (xfer->data == NULL)) - { - return kStatus_InvalidArgument; - } - - /* Add into queue */ - handle->queue[handle->queueUser].data = xfer->data; - handle->queue[handle->queueUser].dataSize = xfer->dataSize; - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; - - /* Set state to busy */ - handle->state = kFLEXIO_I2S_Busy; - - /* Enable interrupt */ - FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable); - - /* Enable Rx transfer */ - FLEXIO_I2S_Enable(base, true); - - return kStatus_Success; -} - -void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle) -{ - assert(handle); - - /* Stop Tx transfer and disable interrupt */ - FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable); - handle->state = kFLEXIO_I2S_Idle; - - /* Clear the queue */ - memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE); - handle->queueDriver = 0; - handle->queueUser = 0; -} - -void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle) -{ - assert(handle); - - /* Stop rx transfer and disable interrupt */ - FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable); - handle->state = kFLEXIO_I2S_Idle; - - /* Clear the queue */ - memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE); - handle->queueDriver = 0; - handle->queueUser = 0; -} - -status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kFLEXIO_I2S_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize); - } - - return status; -} - -status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kFLEXIO_I2S_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize); - } - - return status; -} - -void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle) -{ - assert(i2sHandle); - - flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle; - FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase; - uint8_t *buffer = handle->queue[handle->queueDriver].data; - uint8_t dataSize = handle->bitWidth / 8U; - - /* Handle error */ - if (FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->txShifterIndex)) - { - FLEXIO_ClearShifterErrorFlags(base->flexioBase, (1U << base->txShifterIndex)); - } - /* Handle transfer */ - if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) != 0) && - (handle->queue[handle->queueDriver].data != NULL)) - { - FLEXIO_I2S_WriteNonBlocking(base, handle->bitWidth, buffer, dataSize); - - /* Update internal counter */ - handle->queue[handle->queueDriver].dataSize -= dataSize; - handle->queue[handle->queueDriver].data += dataSize; - } - - /* If finished a blcok, call the callback function */ - if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL)) - { - memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); - handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_Success, handle->userData); - } - } - - /* If all data finished, just stop the transfer */ - if (handle->queue[handle->queueDriver].data == NULL) - { - FLEXIO_I2S_TransferAbortSend(base, handle); - } -} - -void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle) -{ - assert(i2sHandle); - - flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle; - FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase; - uint8_t *buffer = handle->queue[handle->queueDriver].data; - uint8_t dataSize = handle->bitWidth / 8U; - - /* Handle transfer */ - if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_RxDataRegFullFlag) != 0) && - (handle->queue[handle->queueDriver].data != NULL)) - { - FLEXIO_I2S_ReadNonBlocking(base, handle->bitWidth, buffer, dataSize); - - /* Update internal state */ - handle->queue[handle->queueDriver].dataSize -= dataSize; - handle->queue[handle->queueDriver].data += dataSize; - } - - /* If finished a blcok, call the callback function */ - if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL)) - { - memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); - handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_Success, handle->userData); - } - } - - /* If all data finished, just stop the transfer */ - if (handle->queue[handle->queueDriver].data == NULL) - { - FLEXIO_I2S_TransferAbortReceive(base, handle); - } -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s.h deleted file mode 100644 index 2d7326c37e..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s.h +++ /dev/null @@ -1,574 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_FLEXIO_I2S_H_ -#define _FSL_FLEXIO_I2S_H_ - -#include "fsl_common.h" -#include "fsl_flexio.h" - -/*! - * @addtogroup flexio_i2s - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexIO I2S driver version 2.1.4. */ -#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) -/*@}*/ - -/*! @brief FlexIO I2S transfer status */ -enum _flexio_i2s_status -{ - kStatus_FLEXIO_I2S_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 0), /*!< FlexIO I2S is in idle state */ - kStatus_FLEXIO_I2S_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 1), /*!< FlexIO I2S Tx is busy */ - kStatus_FLEXIO_I2S_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 2), /*!< FlexIO I2S Tx is busy */ - kStatus_FLEXIO_I2S_Error = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 3), /*!< FlexIO I2S error occurred */ - kStatus_FLEXIO_I2S_QueueFull = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 4), /*!< FlexIO I2S transfer queue is full. */ -}; - -/*! @brief Define FlexIO I2S access structure typedef */ -typedef struct _flexio_i2s_type -{ - FLEXIO_Type *flexioBase; /*!< FlexIO base pointer */ - uint8_t txPinIndex; /*!< Tx data pin index in FlexIO pins */ - uint8_t rxPinIndex; /*!< Rx data pin index */ - uint8_t bclkPinIndex; /*!< Bit clock pin index */ - uint8_t fsPinIndex; /*!< Frame sync pin index */ - uint8_t txShifterIndex; /*!< Tx data shifter index */ - uint8_t rxShifterIndex; /*!< Rx data shifter index */ - uint8_t bclkTimerIndex; /*!< Bit clock timer index */ - uint8_t fsTimerIndex; /*!< Frame sync timer index */ -} FLEXIO_I2S_Type; - -/*! @brief Master or slave mode */ -typedef enum _flexio_i2s_master_slave -{ - kFLEXIO_I2S_Master = 0x0U, /*!< Master mode */ - kFLEXIO_I2S_Slave = 0x1U /*!< Slave mode */ -} flexio_i2s_master_slave_t; - -/*! @brief Define FlexIO FlexIO I2S interrupt mask. */ -enum _flexio_i2s_interrupt_enable -{ - kFLEXIO_I2S_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ - kFLEXIO_I2S_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ -}; - -/*! @brief Define FlexIO FlexIO I2S status mask. */ -enum _flexio_i2s_status_flags -{ - kFLEXIO_I2S_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ - kFLEXIO_I2S_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ -}; - -/*! @brief FlexIO I2S configure structure */ -typedef struct _flexio_i2s_config -{ - bool enableI2S; /*!< Enable FlexIO I2S */ - flexio_i2s_master_slave_t masterSlave; /*!< Master or slave */ - flexio_pin_polarity_t txPinPolarity; /*!< Tx data pin polarity, active high or low */ - flexio_pin_polarity_t rxPinPolarity; /*!< Rx data pin polarity */ - flexio_pin_polarity_t bclkPinPolarity; /*!< Bit clock pin polarity */ - flexio_pin_polarity_t fsPinPolarity; /*!< Frame sync pin polarity */ - flexio_shifter_timer_polarity_t txTimerPolarity; /*!< Tx data valid on bclk rising or falling edge */ - flexio_shifter_timer_polarity_t rxTimerPolarity; /*!< Rx data valid on bclk rising or falling edge */ -} flexio_i2s_config_t; - -/*! @brief FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx */ -typedef struct _flexio_i2s_format -{ - uint8_t bitWidth; /*!< Bit width of audio data, always 8/16/24/32 bits */ - uint32_t sampleRate_Hz; /*!< Sample rate of the audio data */ -} flexio_i2s_format_t; - -/*!@brief FlexIO I2S transfer queue size, user can refine it according to use case. */ -#define FLEXIO_I2S_XFER_QUEUE_SIZE (4) - -/*! @brief Audio sample rate */ -typedef enum _flexio_i2s_sample_rate -{ - kFLEXIO_I2S_SampleRate8KHz = 8000U, /*!< Sample rate 8000Hz */ - kFLEXIO_I2S_SampleRate11025Hz = 11025U, /*!< Sample rate 11025Hz */ - kFLEXIO_I2S_SampleRate12KHz = 12000U, /*!< Sample rate 12000Hz */ - kFLEXIO_I2S_SampleRate16KHz = 16000U, /*!< Sample rate 16000Hz */ - kFLEXIO_I2S_SampleRate22050Hz = 22050U, /*!< Sample rate 22050Hz */ - kFLEXIO_I2S_SampleRate24KHz = 24000U, /*!< Sample rate 24000Hz */ - kFLEXIO_I2S_SampleRate32KHz = 32000U, /*!< Sample rate 32000Hz */ - kFLEXIO_I2S_SampleRate44100Hz = 44100U, /*!< Sample rate 44100Hz */ - kFLEXIO_I2S_SampleRate48KHz = 48000U, /*!< Sample rate 48000Hz */ - kFLEXIO_I2S_SampleRate96KHz = 96000U /*!< Sample rate 96000Hz */ -} flexio_i2s_sample_rate_t; - -/*! @brief Audio word width */ -typedef enum _flexio_i2s_word_width -{ - kFLEXIO_I2S_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ - kFLEXIO_I2S_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ - kFLEXIO_I2S_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ - kFLEXIO_I2S_WordWidth32bits = 32U /*!< Audio data width 32 bits */ -} flexio_i2s_word_width_t; - -/*! @brief Define FlexIO I2S transfer structure. */ -typedef struct _flexio_i2s_transfer -{ - uint8_t *data; /*!< Data buffer start pointer */ - size_t dataSize; /*!< Bytes to be transferred. */ -} flexio_i2s_transfer_t; - -typedef struct _flexio_i2s_handle flexio_i2s_handle_t; - -/*! @brief FlexIO I2S xfer callback prototype */ -typedef void (*flexio_i2s_callback_t)(FLEXIO_I2S_Type *base, - flexio_i2s_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Define FlexIO I2S handle structure. */ -struct _flexio_i2s_handle -{ - uint32_t state; /*!< Internal state */ - flexio_i2s_callback_t callback; /*!< Callback function called at transfer event*/ - void *userData; /*!< Callback parameter passed to callback function*/ - uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32bits */ - flexio_i2s_transfer_t queue[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ - size_t transferSize[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ - volatile uint8_t queueUser; /*!< Index for user to queue transfer */ - volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the FlexIO I2S. - * - * This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure. - * The configuration structure can be filled by the user, or be set with default values by - * FLEXIO_I2S_GetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault - * because the clock is not enabled. - * - * @param base FlexIO I2S base pointer - * @param config FlexIO I2S configure structure. -*/ -void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config); - -/*! - * @brief Sets the FlexIO I2S configuration structure to default values. - * - * The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init(). - * Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify - * some fields of the structure before calling FLEXIO_I2S_Init(). - * - * @param config pointer to master configuration structure - */ -void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config); - -/*! - * @brief De-initializes the FlexIO I2S. - * - * Calling this API resets the FlexIO I2S shifter and timer config. After calling this API, - * call the FLEXO_I2S_Init to use the FlexIO I2S module. - * - * @param base FlexIO I2S base pointer -*/ -void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base); - -/*! - * @brief Enables/disables the FlexIO I2S module operation. - * - * @param base Pointer to FLEXIO_I2S_Type - * @param enable True to enable, false dose not have any effect. -*/ -static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable) -{ - if (enable) - { - base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; - } -} - -/*! @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the FlexIO I2S status flags. - * - * @param base Pointer to FLEXIO_I2S_Type structure - * @return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags. -*/ -uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base); - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the FlexIO I2S interrupt. - * - * This function enables the FlexIO UART interrupt. - * - * @param base Pointer to FLEXIO_I2S_Type structure - * @param mask interrupt source - */ -void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask); - -/*! - * @brief Disables the FlexIO I2S interrupt. - * - * This function enables the FlexIO UART interrupt. - * - * @param base pointer to FLEXIO_I2S_Type structure - * @param mask interrupt source - */ -void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask); - -/*! @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables/disables the FlexIO I2S Tx DMA requests. - * - * @param base FlexIO I2S base pointer - * @param enable True means enable DMA, false means disable DMA. - */ -static inline void FLEXIO_I2S_TxEnableDMA(FLEXIO_I2S_Type *base, bool enable) -{ - FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->txShifterIndex, enable); -} - -/*! - * @brief Enables/disables the FlexIO I2S Rx DMA requests. - * - * @param base FlexIO I2S base pointer - * @param enable True means enable DMA, false means disable DMA. - */ -static inline void FLEXIO_I2S_RxEnableDMA(FLEXIO_I2S_Type *base, bool enable) -{ - FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->rxShifterIndex, enable); -} - -/*! - * @brief Gets the FlexIO I2S send data register address. - * - * This function returns the I2S data register address, mainly used by DMA/eDMA. - * - * @param base Pointer to FLEXIO_I2S_Type structure - * @return FlexIO i2s send data register address. - */ -static inline uint32_t FLEXIO_I2S_TxGetDataRegisterAddress(FLEXIO_I2S_Type *base) -{ - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->txShifterIndex); -} - -/*! - * @brief Gets the FlexIO I2S receive data register address. - * - * This function returns the I2S data register address, mainly used by DMA/eDMA. - * - * @param base Pointer to FLEXIO_I2S_Type structure - * @return FlexIO i2s receive data register address. - */ -static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base) -{ - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->rxShifterIndex); -} - -/*! @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Configures the FlexIO I2S audio format in master mode. - * - * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base Pointer to FLEXIO_I2S_Type structure - * @param format Pointer to FlexIO I2S audio data format structure. - * @param srcClock_Hz I2S master clock source frequency in Hz. -*/ -void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz); - -/*! - * @brief Configures the FlexIO I2S audio format in slave mode. - * - * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base Pointer to FLEXIO_I2S_Type structure - * @param format Pointer to FlexIO I2S audio data format structure. -*/ -void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format); - -/*! - * @brief Sends data using a blocking method. - * - * @note This function blocks via polling until data is ready to be sent. - * - * @param base FlexIO I2S base pointer. - * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. - * @param txData Pointer to the data to be written. - * @param size Bytes to be written. - */ -void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size); - -/*! - * @brief Writes data into a data register. - * - * @param base FlexIO I2S base pointer. - * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. - * @param data Data to be written. - */ -static inline void FLEXIO_I2S_WriteData(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint32_t data) -{ - base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth)); -} - -/*! - * @brief Receives a piece of data using a blocking method. - * - * @note This function blocks via polling until data is ready to be sent. - * - * @param base FlexIO I2S base pointer - * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. - * @param rxData Pointer to the data to be read. - * @param size Bytes to be read. - */ -void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size); - -/*! - * @brief Reads a data from the data register. - * - * @param base FlexIO I2S base pointer - * @return Data read from data register. - */ -static inline uint32_t FLEXIO_I2S_ReadData(FLEXIO_I2S_Type *base) -{ - return base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex]; -} - -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the FlexIO I2S handle. - * - * This function initializes the FlexIO I2S handle which can be used for other - * FlexIO I2S transactional APIs. Call this API once to get the - * initialized handle. - * - * @param base Pointer to FLEXIO_I2S_Type structure - * @param handle Pointer to flexio_i2s_handle_t structure to store the transfer state. - * @param callback FlexIO I2S callback function, which is called while finished a block. - * @param userData User parameter for the FlexIO I2S callback. - */ -void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, - flexio_i2s_handle_t *handle, - flexio_i2s_callback_t callback, - void *userData); - -/*! - * @brief Configures the FlexIO I2S audio format. - * - * Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base Pointer to FLEXIO_I2S_Type structure. - * @param handle FlexIO I2S handle pointer. - * @param format Pointer to audio data format structure. - * @param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode. -*/ -void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, - flexio_i2s_handle_t *handle, - flexio_i2s_format_t *format, - uint32_t srcClock_Hz); - -/*! - * @brief Initializes the FlexIO I2S receive handle. - * - * This function initializes the FlexIO I2S handle which can be used for other - * FlexIO I2S transactional APIs. Call this API once to get the - * initialized handle. - * - * @param base Pointer to FLEXIO_I2S_Type structure. - * @param handle Pointer to flexio_i2s_handle_t structure to store the transfer state. - * @param callback FlexIO I2S callback function, which is called while finished a block. - * @param userData User parameter for the FlexIO I2S callback. - */ -void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, - flexio_i2s_handle_t *handle, - flexio_i2s_callback_t callback, - void *userData); - -/*! - * @brief Performs an interrupt non-blocking send transfer on FlexIO I2S. - * - * @note The API returns immediately after transfer initiates. - * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether - * the transfer is finished. If the return status is 0, the transfer is finished. - * - * @param base Pointer to FLEXIO_I2S_Type structure. - * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state - * @param xfer Pointer to flexio_i2s_transfer_t structure - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_FLEXIO_I2S_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * @retval kStatus_InvalidArgument The input parameter is invalid. - */ -status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, - flexio_i2s_handle_t *handle, - flexio_i2s_transfer_t *xfer); - -/*! - * @brief Performs an interrupt non-blocking receive transfer on FlexIO I2S. - * - * @note The API returns immediately after transfer initiates. - * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether - * the transfer is finished. If the return status is 0, the transfer is finished. - * - * @param base Pointer to FLEXIO_I2S_Type structure. - * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state - * @param xfer Pointer to flexio_i2s_transfer_t structure - * @retval kStatus_Success Successfully start the data receive. - * @retval kStatus_FLEXIO_I2S_RxBusy Previous receive still not finished. - * @retval kStatus_InvalidArgument The input parameter is invalid. - */ -status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, - flexio_i2s_handle_t *handle, - flexio_i2s_transfer_t *xfer); - -/*! - * @brief Aborts the current send. - * - * @note This API can be called at any time when interrupt non-blocking transfer initiates - * to abort the transfer in a early time. - * - * @param base Pointer to FLEXIO_I2S_Type structure. - * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state - */ -void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle); - -/*! - * @brief Aborts the current receive. - * - * @note This API can be called at any time when interrupt non-blocking transfer initiates - * to abort the transfer in a early time. - * - * @param base Pointer to FLEXIO_I2S_Type structure. - * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state - */ -void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle); - -/*! - * @brief Gets the remaining bytes to be sent. - * - * @param base Pointer to FLEXIO_I2S_Type structure. - * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state - * @param count Bytes sent. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count); - -/*! - * @brief Gets the remaining bytes to be received. - * - * @param base Pointer to FLEXIO_I2S_Type structure. - * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state - * @return count Bytes received. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count); - -/*! - * @brief Tx interrupt handler. - * - * @param i2sBase Pointer to FLEXIO_I2S_Type structure. - * @param i2sHandle Pointer to flexio_i2s_handle_t structure - */ -void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle); - -/*! - * @brief Rx interrupt handler. - * - * @param i2sBase Pointer to FLEXIO_I2S_Type structure. - * @param i2sHandle Pointer to flexio_i2s_handle_t structure. - */ -void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle); - -/*! @} */ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ - -/*! @} */ - -#endif /* _FSL_FLEXIO_I2S_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s_edma.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s_edma.c deleted file mode 100644 index 223d71d759..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s_edma.c +++ /dev/null @@ -1,377 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flexio_i2s_edma.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s_edma" -#endif - - -/******************************************************************************* - * Definitations - ******************************************************************************/ -/* Used for 32byte aligned */ -#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU) - -/*handle; - - /* If finished a blcok, call the callback function */ - memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); - flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; - if (flexio_i2sHandle->callback) - { - (flexio_i2sHandle->callback)(privHandle->base, flexio_i2sHandle, kStatus_Success, flexio_i2sHandle->userData); - } - - /* If all data finished, just stop the transfer */ - if (flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver].data == NULL) - { - FLEXIO_I2S_TransferAbortSendEDMA(privHandle->base, flexio_i2sHandle); - } -} - -static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) -{ - flexio_i2s_edma_private_handle_t *privHandle = (flexio_i2s_edma_private_handle_t *)userData; - flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle; - - /* If finished a blcok, call the callback function */ - memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); - flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; - if (flexio_i2sHandle->callback) - { - (flexio_i2sHandle->callback)(privHandle->base, flexio_i2sHandle, kStatus_Success, flexio_i2sHandle->userData); - } - - /* If all data finished, just stop the transfer */ - if (flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver].data == NULL) - { - FLEXIO_I2S_TransferAbortReceiveEDMA(privHandle->base, flexio_i2sHandle); - } -} - -void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, - flexio_i2s_edma_handle_t *handle, - flexio_i2s_edma_callback_t callback, - void *userData, - edma_handle_t *dmaHandle) -{ - assert(handle && dmaHandle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set flexio_i2s base to handle */ - handle->dmaHandle = dmaHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set FLEXIO I2S state to idle */ - handle->state = kFLEXIO_I2S_Idle; - - s_edmaPrivateHandle[0].base = base; - s_edmaPrivateHandle[0].handle = handle; - - /* Need to use scatter gather */ - EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), FLEXIO_I2S_XFER_QUEUE_SIZE); - - /* Install callback for Tx dma channel */ - EDMA_SetCallback(dmaHandle, FLEXIO_I2S_TxEDMACallback, &s_edmaPrivateHandle[0]); -} - -void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, - flexio_i2s_edma_handle_t *handle, - flexio_i2s_edma_callback_t callback, - void *userData, - edma_handle_t *dmaHandle) -{ - assert(handle && dmaHandle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set flexio_i2s base to handle */ - handle->dmaHandle = dmaHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set FLEXIO I2S state to idle */ - handle->state = kFLEXIO_I2S_Idle; - - s_edmaPrivateHandle[1].base = base; - s_edmaPrivateHandle[1].handle = handle; - - /* Need to use scatter gather */ - EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), FLEXIO_I2S_XFER_QUEUE_SIZE); - - /* Install callback for Tx dma channel */ - EDMA_SetCallback(dmaHandle, FLEXIO_I2S_RxEDMACallback, &s_edmaPrivateHandle[1]); -} - -void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, - flexio_i2s_edma_handle_t *handle, - flexio_i2s_format_t *format, - uint32_t srcClock_Hz) -{ - assert(handle && format); - - /* Configure the audio format to FLEXIO I2S registers */ - if (srcClock_Hz != 0) - { - /* It is master */ - FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz); - } - else - { - FLEXIO_I2S_SlaveSetFormat(base, format); - } - - /* Get the tranfer size from format, this should be used in EDMA configuration */ - handle->bytesPerFrame = format->bitWidth / 8U; -} - -status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, - flexio_i2s_edma_handle_t *handle, - flexio_i2s_transfer_t *xfer) -{ - assert(handle && xfer); - - edma_transfer_config_t config = {0}; - uint32_t destAddr = FLEXIO_I2S_TxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame); - - /* Check if input parameter invalid */ - if ((xfer->data == NULL) || (xfer->dataSize == 0U)) - { - return kStatus_InvalidArgument; - } - - if (handle->queue[handle->queueUser].data) - { - return kStatus_FLEXIO_I2S_QueueFull; - } - - /* Change the state of handle */ - handle->state = kFLEXIO_I2S_Busy; - - /* Update the queue state */ - handle->queue[handle->queueUser].data = xfer->data; - handle->queue[handle->queueUser].dataSize = xfer->dataSize; - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; - - /* Prepare edma configure */ - EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame, - handle->bytesPerFrame, xfer->dataSize, kEDMA_MemoryToPeripheral); - - /* Store the initially configured eDMA minor byte transfer count into the FLEXIO I2S handle */ - handle->nbytes = handle->bytesPerFrame; - - EDMA_SubmitTransfer(handle->dmaHandle, &config); - - /* Start DMA transfer */ - EDMA_StartTransfer(handle->dmaHandle); - - /* Enable DMA enable bit */ - FLEXIO_I2S_TxEnableDMA(base, true); - - /* Enable FLEXIO I2S Tx clock */ - FLEXIO_I2S_Enable(base, true); - - return kStatus_Success; -} - -status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, - flexio_i2s_edma_handle_t *handle, - flexio_i2s_transfer_t *xfer) -{ - assert(handle && xfer); - - edma_transfer_config_t config = {0}; - uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame); - - /* Check if input parameter invalid */ - if ((xfer->data == NULL) || (xfer->dataSize == 0U)) - { - return kStatus_InvalidArgument; - } - - if (handle->queue[handle->queueUser].data) - { - return kStatus_FLEXIO_I2S_QueueFull; - } - - /* Change the state of handle */ - handle->state = kFLEXIO_I2S_Busy; - - /* Update queue state */ - handle->queue[handle->queueUser].data = xfer->data; - handle->queue[handle->queueUser].dataSize = xfer->dataSize; - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; - - /* Prepare edma configure */ - EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame, - handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory); - - /* Store the initially configured eDMA minor byte transfer count into the FLEXIO I2S handle */ - handle->nbytes = handle->bytesPerFrame; - - EDMA_SubmitTransfer(handle->dmaHandle, &config); - - /* Start DMA transfer */ - EDMA_StartTransfer(handle->dmaHandle); - - /* Enable DMA enable bit */ - FLEXIO_I2S_RxEnableDMA(base, true); - - /* Enable FLEXIO I2S Rx clock */ - FLEXIO_I2S_Enable(base, true); - - return kStatus_Success; -} - -void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle) -{ - assert(handle); - - /* Disable dma */ - EDMA_AbortTransfer(handle->dmaHandle); - - /* Disable DMA enable bit */ - FLEXIO_I2S_TxEnableDMA(base, false); - - /* Set the handle state */ - handle->state = kFLEXIO_I2S_Idle; -} - -void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle) -{ - assert(handle); - - /* Disable dma */ - EDMA_AbortTransfer(handle->dmaHandle); - - /* Disable DMA enable bit */ - FLEXIO_I2S_RxEnableDMA(base, false); - - /* Set the handle state */ - handle->state = kFLEXIO_I2S_Idle; -} - -status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kFLEXIO_I2S_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = handle->transferSize[handle->queueDriver] - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel); - } - - return status; -} - -status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kFLEXIO_I2S_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = handle->transferSize[handle->queueDriver] - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel); - } - - return status; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s_edma.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s_edma.h deleted file mode 100644 index e529fe23f7..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s_edma.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_FLEXIO_I2S_EDMA_H_ -#define _FSL_FLEXIO_I2S_EDMA_H_ - -#include "fsl_flexio_i2s.h" -#include "fsl_edma.h" - -/*! - * @addtogroup flexio_edma_i2s - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexIO I2S EDMA driver version 2.1.4. */ -#define FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) -/*@}*/ - -typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t; - -/*! @brief FlexIO I2S eDMA transfer callback function for finish and error */ -typedef void (*flexio_i2s_edma_callback_t)(FLEXIO_I2S_Type *base, - flexio_i2s_edma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief FlexIO I2S DMA transfer handle, users should not touch the content of the handle.*/ -struct _flexio_i2s_edma_handle -{ - edma_handle_t *dmaHandle; /*!< DMA handler for FlexIO I2S send */ - uint8_t bytesPerFrame; /*!< Bytes in a frame */ - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - uint32_t state; /*!< Internal state for FlexIO I2S eDMA transfer */ - flexio_i2s_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurred */ - void *userData; /*!< User callback parameter */ - edma_tcd_t tcd[FLEXIO_I2S_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ - flexio_i2s_transfer_t queue[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ - size_t transferSize[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ - volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ - volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name eDMA Transactional - * @{ - */ - -/*! - * @brief Initializes the FlexIO I2S eDMA handle. - * - * This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master - * transactional APIs. - * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle. - * - * @param base FlexIO I2S peripheral base address. - * @param handle FlexIO I2S eDMA handle pointer. - * @param callback FlexIO I2S eDMA callback function called while finished a block. - * @param userData User parameter for callback. - * @param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users. - */ -void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, - flexio_i2s_edma_handle_t *handle, - flexio_i2s_edma_callback_t callback, - void *userData, - edma_handle_t *dmaHandle); - -/*! - * @brief Initializes the FlexIO I2S Rx eDMA handle. - * - * This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional - * APIs. - * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle. - * - * @param base FlexIO I2S peripheral base address. - * @param handle FlexIO I2S eDMA handle pointer. - * @param callback FlexIO I2S eDMA callback function called while finished a block. - * @param userData User parameter for callback. - * @param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users. - */ -void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, - flexio_i2s_edma_handle_t *handle, - flexio_i2s_edma_callback_t callback, - void *userData, - edma_handle_t *dmaHandle); - -/*! - * @brief Configures the FlexIO I2S Tx audio format. - * - * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to format. - * - * @param base FlexIO I2S peripheral base address. - * @param handle FlexIO I2S eDMA handle pointer - * @param format Pointer to FlexIO I2S audio data format structure. - * @param srcClock_Hz FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode. - * @retval kStatus_Success Audio format set successfully. - * @retval kStatus_InvalidArgument The input arguments is invalid. -*/ -void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, - flexio_i2s_edma_handle_t *handle, - flexio_i2s_format_t *format, - uint32_t srcClock_Hz); - -/*! - * @brief Performs a non-blocking FlexIO I2S transfer using DMA. - * - * @note This interface returned immediately after transfer initiates. Users should call - * FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished. - * - * @param base FlexIO I2S peripheral base address. - * @param handle FlexIO I2S DMA handle pointer. - * @param xfer Pointer to DMA transfer structure. - * @retval kStatus_Success Start a FlexIO I2S eDMA send successfully. - * @retval kStatus_InvalidArgument The input arguments is invalid. - * @retval kStatus_TxBusy FlexIO I2S is busy sending data. - */ -status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, - flexio_i2s_edma_handle_t *handle, - flexio_i2s_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking FlexIO I2S receive using eDMA. - * - * @note This interface returned immediately after transfer initiates. Users should call - * FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is - * finished. - * - * @param base FlexIO I2S peripheral base address. - * @param handle FlexIO I2S DMA handle pointer. - * @param xfer Pointer to DMA transfer structure. - * @retval kStatus_Success Start a FlexIO I2S eDMA receive successfully. - * @retval kStatus_InvalidArgument The input arguments is invalid. - * @retval kStatus_RxBusy FlexIO I2S is busy receiving data. - */ -status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, - flexio_i2s_edma_handle_t *handle, - flexio_i2s_transfer_t *xfer); - -/*! - * @brief Aborts a FlexIO I2S transfer using eDMA. - * - * @param base FlexIO I2S peripheral base address. - * @param handle FlexIO I2S DMA handle pointer. - */ -void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle); - -/*! - * @brief Aborts a FlexIO I2S receive using eDMA. - * - * @param base FlexIO I2S peripheral base address. - * @param handle FlexIO I2S DMA handle pointer. - */ -void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle); - -/*! - * @brief Gets the remaining bytes to be sent. - * - * @param base FlexIO I2S peripheral base address. - * @param handle FlexIO I2S DMA handle pointer. - * @param count Bytes sent. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count); - -/*! - * @brief Get the remaining bytes to be received. - * - * @param base FlexIO I2S peripheral base address. - * @param handle FlexIO I2S DMA handle pointer. - * @param count Bytes received. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count); - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi.c deleted file mode 100644 index 5cae486ae8..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi.c +++ /dev/null @@ -1,1005 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flexio_spi.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexio_spi" -#endif - - -/*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */ -enum _flexio_spi_transfer_states -{ - kFLEXIO_SPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver's queue. */ - kFLEXIO_SPI_Busy, /*!< Transmiter/Receive's queue is not finished. */ -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Send a piece of data for SPI. - * - * This function computes the number of data to be written into D register or Tx FIFO, - * and write the data into it. At the same time, this function updates the values in - * master handle structure. - * - * @param base pointer to FLEXIO_SPI_Type structure - * @param handle Pointer to SPI master handle structure. - */ -static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); - -/*! - * @brief Receive a piece of data for SPI master. - * - * This function computes the number of data to receive from D register or Rx FIFO, - * and write the data to destination address. At the same time, this function updates - * the values in master handle structure. - * - * @param base pointer to FLEXIO_SPI_Type structure - * @param handle Pointer to SPI master handle structure. - */ -static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Codes - ******************************************************************************/ - -static uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base) -{ - return FLEXIO_GetInstance(base->flexioBase); -} - -static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) -{ - uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; - - if (handle->txData != NULL) - { - /* Transmit data and update tx size/buff. */ - if (handle->bytePerFrame == 1U) - { - tmpData = *(handle->txData); - handle->txData++; - } - else - { - if (handle->direction == kFLEXIO_SPI_MsbFirst) - { - tmpData = (uint32_t)(handle->txData[0]) << 8U; - tmpData += handle->txData[1]; - } - else - { - tmpData = (uint32_t)(handle->txData[1]) << 8U; - tmpData += handle->txData[0]; - } - handle->txData += 2U; - } - } - else - { - tmpData = FLEXIO_SPI_DUMMYDATA; - } - - handle->txRemainingBytes -= handle->bytePerFrame; - - FLEXIO_SPI_WriteData(base, handle->direction, tmpData); - - if (!handle->txRemainingBytes) - { - FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); - } -} - -static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) -{ - uint16_t tmpData; - - tmpData = FLEXIO_SPI_ReadData(base, handle->direction); - - if (handle->rxData != NULL) - { - if (handle->bytePerFrame == 1U) - { - *handle->rxData = tmpData; - handle->rxData++; - } - else - { - if (handle->direction == kFLEXIO_SPI_MsbFirst) - { - *((uint16_t *)(handle->rxData)) = tmpData; - } - else - { - *((uint16_t *)(handle->rxData)) = (((tmpData << 8) & 0xff00U) | ((tmpData >> 8) & 0x00ffU)); - } - handle->rxData += 2U; - } - } - handle->rxRemainingBytes -= handle->bytePerFrame; -} - -void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - assert(base); - assert(masterConfig); - - flexio_shifter_config_t shifterConfig; - flexio_timer_config_t timerConfig; - uint32_t ctrlReg = 0; - uint16_t timerDiv = 0; - uint16_t timerCmp = 0; - - /* Clear the shifterConfig & timerConfig struct. */ - memset(&shifterConfig, 0, sizeof(shifterConfig)); - memset(&timerConfig, 0, sizeof(timerConfig)); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate flexio clock. */ - CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Configure FLEXIO SPI Master */ - ctrlReg = base->flexioBase->CTRL; - ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); - ctrlReg |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | - FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); - if (!masterConfig->enableInDoze) - { - ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; - } - - base->flexioBase->CTRL = ctrlReg; - - /* Do hardware configuration. */ - /* 1. Configure the shifter 0 for tx. */ - shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; - shifterConfig.pinSelect = base->SDOPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; - } - else - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; - } - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); - - /* 2. Configure the shifter 1 for rx. */ - shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinSelect = base->SDIPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; - if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - } - else - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - } - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); - - /*3. Configure the timer 0 for SCK. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutput; - timerConfig.pinSelect = base->SCKPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - - timerDiv = srcClock_Hz / masterConfig->baudRate_Bps; - timerDiv = timerDiv / 2 - 1; - - timerCmp = ((uint32_t)(masterConfig->dataMode * 2 - 1U)) << 8U; - timerCmp |= timerDiv; - - timerConfig.timerCompare = timerCmp; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); - - /* 4. Configure the timer 1 for CSn. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutput; - timerConfig.pinSelect = base->CSnPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveLow; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; - timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; - - timerConfig.timerCompare = 0xFFFFU; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); -} - -void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base) -{ - base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; - base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; - base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; - base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; - base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; - base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; - base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; - base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; - base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; - base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; -} - -void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig) -{ - assert(masterConfig); - - masterConfig->enableMaster = true; - masterConfig->enableInDoze = false; - masterConfig->enableInDebug = true; - masterConfig->enableFastAccess = false; - /* Default baud rate 500kbps. */ - masterConfig->baudRate_Bps = 500000U; - /* Default CPHA = 0. */ - masterConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; - /* Default bit count at 8. */ - masterConfig->dataMode = kFLEXIO_SPI_8BitMode; -} - -void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig) -{ - assert(base && slaveConfig); - - flexio_shifter_config_t shifterConfig; - flexio_timer_config_t timerConfig; - uint32_t ctrlReg = 0; - - /* Clear the shifterConfig & timerConfig struct. */ - memset(&shifterConfig, 0, sizeof(shifterConfig)); - memset(&timerConfig, 0, sizeof(timerConfig)); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate flexio clock. */ - CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Configure FLEXIO SPI Slave */ - ctrlReg = base->flexioBase->CTRL; - ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); - ctrlReg |= (FLEXIO_CTRL_DBGE(slaveConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(slaveConfig->enableFastAccess) | - FLEXIO_CTRL_FLEXEN(slaveConfig->enableSlave)); - if (!slaveConfig->enableInDoze) - { - ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; - } - - base->flexioBase->CTRL = ctrlReg; - - /* Do hardware configuration. */ - /* 1. Configure the shifter 0 for tx. */ - shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; - shifterConfig.pinSelect = base->SDOPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; - if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; - } - else - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; - } - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); - - /* 2. Configure the shifter 1 for rx. */ - shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinSelect = base->SDIPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; - if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - } - else - { - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - } - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); - - /*3. Configure the timer 0 for shift clock. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->SCKPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; - if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) - { - /* The configuration kFLEXIO_TimerDisableOnTimerCompare only support continuous - PCS access, change to kFLEXIO_TimerDisableNever to enable discontinuous PCS access. */ - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; - } - else - { - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - } - - timerConfig.timerCompare = slaveConfig->dataMode * 2 - 1U; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); -} - -void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base) -{ - FLEXIO_SPI_MasterDeinit(base); -} - -void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig) -{ - assert(slaveConfig); - - slaveConfig->enableSlave = true; - slaveConfig->enableInDoze = false; - slaveConfig->enableInDebug = true; - slaveConfig->enableFastAccess = false; - /* Default CPHA = 0. */ - slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; - /* Default bit count at 8. */ - slaveConfig->dataMode = kFLEXIO_SPI_8BitMode; -} - -void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]); - } - if (mask & kFLEXIO_SPI_RxFullInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]); - } -} - -void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]); - } - if (mask & kFLEXIO_SPI_RxFullInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]); - } -} - -void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable) -{ - if (mask & kFLEXIO_SPI_TxDmaEnable) - { - FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[0], enable); - } - - if (mask & kFLEXIO_SPI_RxDmaEnable) - { - FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[1], enable); - } -} - -uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base) -{ - uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase); - uint32_t status = 0; - - status = ((shifterStatus & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); - status |= (((shifterStatus & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U); - - return status; -} - -void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_SPI_TxBufferEmptyFlag) - { - FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); - } - if (mask & kFLEXIO_SPI_RxBufferFullFlag) - { - FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz) -{ - uint16_t timerDiv = 0; - uint16_t timerCmp = 0; - FLEXIO_Type *flexioBase = base->flexioBase; - - /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ - timerDiv = srcClockHz / baudRate_Bps; - timerDiv = timerDiv / 2 - 1U; - - timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; - timerCmp &= 0xFF00U; - timerCmp |= timerDiv; - - flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; -} - -void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, - flexio_spi_shift_direction_t direction, - const uint8_t *buffer, - size_t size) -{ - assert(buffer); - assert(size); - - while (size--) - { - /* Wait until data transfer complete. */ - while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag)) - { - } - FLEXIO_SPI_WriteData(base, direction, *buffer++); - } -} - -void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, - flexio_spi_shift_direction_t direction, - uint8_t *buffer, - size_t size) -{ - assert(buffer); - assert(size); - - while (size--) - { - /* Wait until data transfer complete. */ - while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag)) - { - } - *buffer++ = FLEXIO_SPI_ReadData(base, direction); - } -} - -void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer) -{ - flexio_spi_shift_direction_t direction; - uint8_t bytesPerFrame; - uint32_t dataMode = 0; - uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; - uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; - - timerCmp &= 0x00FFU; - /* Configure the values in handle. */ - switch (xfer->flags) - { - case kFLEXIO_SPI_8bitMsb: - dataMode = (8 * 2 - 1U) << 8U; - bytesPerFrame = 1; - direction = kFLEXIO_SPI_MsbFirst; - break; - - case kFLEXIO_SPI_8bitLsb: - dataMode = (8 * 2 - 1U) << 8U; - bytesPerFrame = 1; - direction = kFLEXIO_SPI_LsbFirst; - break; - - case kFLEXIO_SPI_16bitMsb: - dataMode = (16 * 2 - 1U) << 8U; - bytesPerFrame = 2; - direction = kFLEXIO_SPI_MsbFirst; - break; - - case kFLEXIO_SPI_16bitLsb: - dataMode = (16 * 2 - 1U) << 8U; - bytesPerFrame = 2; - direction = kFLEXIO_SPI_LsbFirst; - break; - - default: - dataMode = (8 * 2 - 1U) << 8U; - bytesPerFrame = 1; - direction = kFLEXIO_SPI_MsbFirst; - assert(true); - break; - } - - dataMode |= timerCmp; - - /* Configure transfer size. */ - base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - - while (xfer->dataSize) - { - /* Wait until data transfer complete. */ - while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag)) - { - } - if (xfer->txData != NULL) - { - /* Transmit data and update tx size/buff. */ - if (bytesPerFrame == 1U) - { - tmpData = *(xfer->txData); - xfer->txData++; - } - else - { - if (direction == kFLEXIO_SPI_MsbFirst) - { - tmpData = (uint32_t)(xfer->txData[0]) << 8U; - tmpData += xfer->txData[1]; - } - else - { - tmpData = (uint32_t)(xfer->txData[1]) << 8U; - tmpData += xfer->txData[0]; - } - xfer->txData += 2U; - } - } - else - { - tmpData = FLEXIO_SPI_DUMMYDATA; - } - - xfer->dataSize -= bytesPerFrame; - - FLEXIO_SPI_WriteData(base, direction, tmpData); - - while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag)) - { - } - tmpData = FLEXIO_SPI_ReadData(base, direction); - - if (xfer->rxData != NULL) - { - if (bytesPerFrame == 1U) - { - *xfer->rxData = tmpData; - xfer->rxData++; - } - else - { - if (direction == kFLEXIO_SPI_MsbFirst) - { - *((uint16_t *)(xfer->rxData)) = tmpData; - } - else - { - *((uint16_t *)(xfer->rxData)) = (((tmpData << 8) & 0xff00U) | ((tmpData >> 8) & 0x00ffU)); - } - xfer->rxData += 2U; - } - } - } -} - -status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, - flexio_spi_master_handle_t *handle, - flexio_spi_master_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - IRQn_Type flexio_irqs[] = FLEXIO_IRQS; - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Register callback and userData. */ - handle->callback = callback; - handle->userData = userData; - - /* Enable interrupt in NVIC. */ - EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); - - /* Save the context in global variables to support the double weak mechanism. */ - return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ); -} - -status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, - flexio_spi_master_handle_t *handle, - flexio_spi_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - uint32_t dataMode = 0; - uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; - uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; - - timerCmp &= 0x00FFU; - - /* Check if SPI is busy. */ - if (handle->state == kFLEXIO_SPI_Busy) - { - return kStatus_FLEXIO_SPI_Busy; - } - - /* Check if the argument is legal. */ - if ((xfer->txData == NULL) && (xfer->rxData == NULL)) - { - return kStatus_InvalidArgument; - } - - /* Configure the values in handle */ - switch (xfer->flags) - { - case kFLEXIO_SPI_8bitMsb: - dataMode = (8 * 2 - 1U) << 8U; - handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_MsbFirst; - break; - case kFLEXIO_SPI_8bitLsb: - dataMode = (8 * 2 - 1U) << 8U; - handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_LsbFirst; - break; - case kFLEXIO_SPI_16bitMsb: - dataMode = (16 * 2 - 1U) << 8U; - handle->bytePerFrame = 2U; - handle->direction = kFLEXIO_SPI_MsbFirst; - break; - case kFLEXIO_SPI_16bitLsb: - dataMode = (16 * 2 - 1U) << 8U; - handle->bytePerFrame = 2U; - handle->direction = kFLEXIO_SPI_LsbFirst; - break; - default: - dataMode = (8 * 2 - 1U) << 8U; - handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_MsbFirst; - assert(true); - break; - } - - dataMode |= timerCmp; - - /* Configure transfer size. */ - base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - - handle->state = kFLEXIO_SPI_Busy; - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; - handle->rxRemainingBytes = xfer->dataSize; - - /* Save total transfer size. */ - handle->transferSize = xfer->dataSize; - - /* Send first byte of data to trigger the rx interrupt. */ - if (handle->txData != NULL) - { - /* Transmit data and update tx size/buff. */ - if (handle->bytePerFrame == 1U) - { - tmpData = *(handle->txData); - handle->txData++; - } - else - { - if (handle->direction == kFLEXIO_SPI_MsbFirst) - { - tmpData = (uint32_t)(handle->txData[0]) << 8U; - tmpData += handle->txData[1]; - } - else - { - tmpData = (uint32_t)(handle->txData[1]) << 8U; - tmpData += handle->txData[0]; - } - handle->txData += 2U; - } - } - else - { - tmpData = FLEXIO_SPI_DUMMYDATA; - } - - handle->txRemainingBytes = xfer->dataSize - handle->bytePerFrame; - - FLEXIO_SPI_WriteData(base, handle->direction, tmpData); - - /* Enable transmit and receive interrupt to handle rx. */ - FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); - - return kStatus_Success; -} - -status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Return remaing bytes in different cases. */ - if (handle->rxData) - { - *count = handle->transferSize - handle->rxRemainingBytes; - } - else - { - *count = handle->transferSize - handle->txRemainingBytes; - } - - return kStatus_Success; -} - -void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) -{ - assert(handle); - - FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); - FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); - - /* Transfer finished, set the state to idle. */ - handle->state = kFLEXIO_SPI_Idle; - - /* Clear the internal state. */ - handle->rxRemainingBytes = 0; - handle->txRemainingBytes = 0; -} - -void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle) -{ - assert(spiHandle); - - flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; - FLEXIO_SPI_Type *base; - uint32_t status; - - if (handle->state == kFLEXIO_SPI_Idle) - { - return; - } - - base = (FLEXIO_SPI_Type *)spiType; - status = FLEXIO_SPI_GetStatusFlags(base); - - /* Handle rx. */ - if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes)) - { - FLEXIO_SPI_TransferReceiveTransaction(base, handle); - } - - /* Handle tx. */ - if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes)) - { - FLEXIO_SPI_TransferSendTransaction(base, handle); - } - - /* All the transfer finished. */ - if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) - { - FLEXIO_SPI_MasterTransferAbort(base, handle); - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); - } - } -} - -status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, - flexio_spi_slave_handle_t *handle, - flexio_spi_slave_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - IRQn_Type flexio_irqs[] = FLEXIO_IRQS; - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Register callback and userData. */ - handle->callback = callback; - handle->userData = userData; - - /* Enable interrupt in NVIC. */ - EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); - - /* Save the context in global variables to support the double weak mechanism. */ - return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ); -} - -status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, - flexio_spi_slave_handle_t *handle, - flexio_spi_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - uint32_t dataMode = 0; - - /* Check if SPI is busy. */ - if (handle->state == kFLEXIO_SPI_Busy) - { - return kStatus_FLEXIO_SPI_Busy; - } - - /* Check if the argument is legal. */ - if ((xfer->txData == NULL) && (xfer->rxData == NULL)) - { - return kStatus_InvalidArgument; - } - - /* Configure the values in handle */ - switch (xfer->flags) - { - case kFLEXIO_SPI_8bitMsb: - dataMode = 8 * 2 - 1U; - handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_MsbFirst; - break; - case kFLEXIO_SPI_8bitLsb: - dataMode = 8 * 2 - 1U; - handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_LsbFirst; - break; - case kFLEXIO_SPI_16bitMsb: - dataMode = 16 * 2 - 1U; - handle->bytePerFrame = 2U; - handle->direction = kFLEXIO_SPI_MsbFirst; - break; - case kFLEXIO_SPI_16bitLsb: - dataMode = 16 * 2 - 1U; - handle->bytePerFrame = 2U; - handle->direction = kFLEXIO_SPI_LsbFirst; - break; - default: - dataMode = 8 * 2 - 1U; - handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_MsbFirst; - assert(true); - break; - } - - /* Configure transfer size. */ - base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - - handle->state = kFLEXIO_SPI_Busy; - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; - handle->txRemainingBytes = xfer->dataSize; - handle->rxRemainingBytes = xfer->dataSize; - - /* Save total transfer size. */ - handle->transferSize = xfer->dataSize; - - /* Enable transmit and receive interrupt to handle tx and rx. */ - FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); - FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); - - return kStatus_Success; -} - -void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle) -{ - assert(spiHandle); - - flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; - FLEXIO_SPI_Type *base; - uint32_t status; - - if (handle->state == kFLEXIO_SPI_Idle) - { - return; - } - - base = (FLEXIO_SPI_Type *)spiType; - status = FLEXIO_SPI_GetStatusFlags(base); - - /* Handle tx. */ - if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes)) - { - FLEXIO_SPI_TransferSendTransaction(base, handle); - } - - /* Handle rx. */ - if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes)) - { - FLEXIO_SPI_TransferReceiveTransaction(base, handle); - } - - /* All the transfer finished. */ - if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) - { - FLEXIO_SPI_SlaveTransferAbort(base, handle); - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); - } - } -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi.h deleted file mode 100644 index e72f6e09cd..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi.h +++ /dev/null @@ -1,707 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_FLEXIO_SPI_H_ -#define _FSL_FLEXIO_SPI_H_ - -#include "fsl_common.h" -#include "fsl_flexio.h" - -/*! - * @addtogroup flexio_spi - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexIO SPI driver version 2.1.3. */ -#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) -/*@}*/ - -#ifndef FLEXIO_SPI_DUMMYDATA -/*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */ -#define FLEXIO_SPI_DUMMYDATA (0xFFFFU) -#endif - -/*! @brief Error codes for the FlexIO SPI driver. */ -enum _flexio_spi_status -{ - kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */ - kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */ - kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */ -}; - -/*! @brief FlexIO SPI clock phase configuration. */ -typedef enum _flexio_spi_clock_phase -{ - kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first - * cycle of a data transfer. */ - kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the - * first cycle of a data transfer. */ -} flexio_spi_clock_phase_t; - -/*! @brief FlexIO SPI data shifter direction options. */ -typedef enum _flexio_spi_shift_direction -{ - kFLEXIO_SPI_MsbFirst = 0, /*!< Data transfers start with most significant bit. */ - kFLEXIO_SPI_LsbFirst = 1, /*!< Data transfers start with least significant bit. */ -} flexio_spi_shift_direction_t; - -/*! @brief FlexIO SPI data length mode options. */ -typedef enum _flexio_spi_data_bitcount_mode -{ - kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */ - kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */ -} flexio_spi_data_bitcount_mode_t; - -/*! @brief Define FlexIO SPI interrupt mask. */ -enum _flexio_spi_interrupt_enable -{ - kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ - kFLEXIO_SPI_RxFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ -}; - -/*! @brief Define FlexIO SPI status mask. */ -enum _flexio_spi_status_flags -{ - kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ - kFLEXIO_SPI_RxBufferFullFlag = 0x2U, /*!< Receive buffer full flag. */ -}; - -/*! @brief Define FlexIO SPI DMA mask. */ -enum _flexio_spi_dma_enable -{ - kFLEXIO_SPI_TxDmaEnable = 0x1U, /*!< Tx DMA request source */ - kFLEXIO_SPI_RxDmaEnable = 0x2U, /*!< Rx DMA request source */ - kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/ -}; - -/*! @brief Define FlexIO SPI transfer flags. */ -enum _flexio_spi_transfer_flags -{ - kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */ - kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */ - kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */ - kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */ -}; - -/*! @brief Define FlexIO SPI access structure typedef. */ -typedef struct _flexio_spi_type -{ - FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ - uint8_t SDOPinIndex; /*!< Pin select for data output. */ - uint8_t SDIPinIndex; /*!< Pin select for data input. */ - uint8_t SCKPinIndex; /*!< Pin select for clock. */ - uint8_t CSnPinIndex; /*!< Pin select for enable. */ - uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO SPI. */ - uint8_t timerIndex[2]; /*!< Timer index used in FlexIO SPI. */ -} FLEXIO_SPI_Type; - -/*! @brief Define FlexIO SPI master configuration structure. */ -typedef struct _flexio_spi_master_config -{ - bool enableMaster; /*!< Enable/disable FlexIO SPI master after configuration. */ - bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ - bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ - bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, - fast access requires the FlexIO clock to be at least - twice the frequency of the bus clock. */ - uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ - flexio_spi_clock_phase_t phase; /*!< Clock phase. */ - flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ -} flexio_spi_master_config_t; - -/*! @brief Define FlexIO SPI slave configuration structure. */ -typedef struct _flexio_spi_slave_config -{ - bool enableSlave; /*!< Enable/disable FlexIO SPI slave after configuration. */ - bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ - bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ - bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, - fast access requires the FlexIO clock to be at least - twice the frequency of the bus clock. */ - flexio_spi_clock_phase_t phase; /*!< Clock phase. */ - flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ -} flexio_spi_slave_config_t; - -/*! @brief Define FlexIO SPI transfer structure. */ -typedef struct _flexio_spi_transfer -{ - uint8_t *txData; /*!< Send buffer. */ - uint8_t *rxData; /*!< Receive buffer. */ - size_t dataSize; /*!< Transfer bytes. */ - uint8_t flags; /*!< FlexIO SPI control flag, MSB first or LSB first. */ -} flexio_spi_transfer_t; - -/*! @brief typedef for flexio_spi_master_handle_t in advance. */ -typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t; - -/*! @brief Slave handle is the same with master handle. */ -typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t; - -/*! @brief FlexIO SPI master callback for finished transmit */ -typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base, - flexio_spi_master_handle_t *handle, - status_t status, - void *userData); - -/*! @brief FlexIO SPI slave callback for finished transmit */ -typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, - flexio_spi_slave_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Define FlexIO SPI handle structure. */ -struct _flexio_spi_master_handle -{ - uint8_t *txData; /*!< Transfer buffer. */ - uint8_t *rxData; /*!< Receive buffer. */ - size_t transferSize; /*!< Total bytes to be transferred. */ - volatile size_t txRemainingBytes; /*!< Send data remaining in bytes. */ - volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes. */ - volatile uint32_t state; /*!< FlexIO SPI internal state. */ - uint8_t bytePerFrame; /*!< SPI mode, 2bytes or 1byte in a frame */ - flexio_spi_shift_direction_t direction; /*!< Shift direction. */ - flexio_spi_master_transfer_callback_t callback; /*!< FlexIO SPI callback. */ - void *userData; /*!< Callback parameter. */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name FlexIO SPI Configuration - * @{ - */ - -/*! - * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, - * and configures the FlexIO SPI with FlexIO SPI master configuration. The - * configuration structure can be filled by the user, or be set with default values - * by the FLEXIO_SPI_MasterGetDefaultConfig(). - * - * @note FlexIO SPI master only support CPOL = 0, which means clock inactive low. - * - * Example - @code - FLEXIO_SPI_Type spiDev = { - .flexioBase = FLEXIO, - .SDOPinIndex = 0, - .SDIPinIndex = 1, - .SCKPinIndex = 2, - .CSnPinIndex = 3, - .shifterIndex = {0,1}, - .timerIndex = {0,1} - }; - flexio_spi_master_config_t config = { - .enableMaster = true, - .enableInDoze = false, - .enableInDebug = true, - .enableFastAccess = false, - .baudRate_Bps = 500000, - .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, - .direction = kFLEXIO_SPI_MsbFirst, - .dataMode = kFLEXIO_SPI_8BitMode - }; - FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz); - @endcode - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param masterConfig Pointer to the flexio_spi_master_config_t structure. - * @param srcClock_Hz FlexIO source clock in Hz. -*/ -void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief Resets the FlexIO SPI timer and shifter config. - * - * @param base Pointer to the FLEXIO_SPI_Type. -*/ -void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base); - -/*! - * @brief Gets the default configuration to configure the FlexIO SPI master. The configuration - * can be used directly by calling the FLEXIO_SPI_MasterConfigure(). - * Example: - @code - flexio_spi_master_config_t masterConfig; - FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig); - @endcode - * @param masterConfig Pointer to the flexio_spi_master_config_t structure. -*/ -void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig); - -/*! - * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware - * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The - * configuration structure can be filled by the user, or be set with default values - * by the FLEXIO_SPI_SlaveGetDefaultConfig(). - * - * @note Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. - * FlexIO SPI slave only support CPOL = 0, which means clock inactive low. - * Example - @code - FLEXIO_SPI_Type spiDev = { - .flexioBase = FLEXIO, - .SDOPinIndex = 0, - .SDIPinIndex = 1, - .SCKPinIndex = 2, - .CSnPinIndex = 3, - .shifterIndex = {0,1}, - .timerIndex = {0} - }; - flexio_spi_slave_config_t config = { - .enableSlave = true, - .enableInDoze = false, - .enableInDebug = true, - .enableFastAccess = false, - .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, - .direction = kFLEXIO_SPI_MsbFirst, - .dataMode = kFLEXIO_SPI_8BitMode - }; - FLEXIO_SPI_SlaveInit(&spiDev, &config); - @endcode - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. -*/ -void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig); - -/*! - * @brief Gates the FlexIO clock. - * - * @param base Pointer to the FLEXIO_SPI_Type. -*/ -void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base); - -/*! - * @brief Gets the default configuration to configure the FlexIO SPI slave. The configuration - * can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). - * Example: - @code - flexio_spi_slave_config_t slaveConfig; - FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig); - @endcode - * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. -*/ -void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig); - -/*@}*/ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets FlexIO SPI status flags. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @return status flag; Use the status flag to AND the following flag mask and get the status. - * @arg kFLEXIO_SPI_TxEmptyFlag - * @arg kFLEXIO_SPI_RxEmptyFlag -*/ - -uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base); - -/*! - * @brief Clears FlexIO SPI status flags. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param mask status flag - * The parameter can be any combination of the following values: - * @arg kFLEXIO_SPI_TxEmptyFlag - * @arg kFLEXIO_SPI_RxEmptyFlag -*/ - -void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask); - -/*@}*/ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the FlexIO SPI interrupt. - * - * This function enables the FlexIO SPI interrupt. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param mask interrupt source. The parameter can be any combination of the following values: - * @arg kFLEXIO_SPI_RxFullInterruptEnable - * @arg kFLEXIO_SPI_TxEmptyInterruptEnable - */ -void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); - -/*! - * @brief Disables the FlexIO SPI interrupt. - * - * This function disables the FlexIO SPI interrupt. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param mask interrupt source The parameter can be any combination of the following values: - * @arg kFLEXIO_SPI_RxFullInterruptEnable - * @arg kFLEXIO_SPI_TxEmptyInterruptEnable - */ -void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); - -/*@}*/ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, - * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param mask SPI DMA source. - * @param enable True means enable DMA, false means disable DMA. - */ -void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable); - -/*! - * @brief Gets the FlexIO SPI transmit data register address for MSB first transfer. - * - * This function returns the SPI data register address, which is mainly used by DMA/eDMA. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param direction Shift direction of MSB first or LSB first. - * @return FlexIO SPI transmit data register address. - */ -static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base, - flexio_spi_shift_direction_t direction) -{ - if (direction == kFLEXIO_SPI_MsbFirst) - { - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, - base->shifterIndex[0]) + - 3U; - } - else - { - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); - } -} - -/*! - * @brief Gets the FlexIO SPI receive data register address for the MSB first transfer. - * - * This function returns the SPI data register address, which is mainly used by DMA/eDMA. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param direction Shift direction of MSB first or LSB first. - * @return FlexIO SPI receive data register address. - */ -static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base, - flexio_spi_shift_direction_t direction) -{ - if (direction == kFLEXIO_SPI_MsbFirst) - { - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->shifterIndex[1]); - } - else - { - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[1]) + 3U; - } -} - -/*@}*/ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Enables/disables the FlexIO SPI module operation. - * - * @param base Pointer to the FLEXIO_SPI_Type. - * @param enable True to enable, false does not have any effect. -*/ -static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable) -{ - if (enable) - { - base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; - } -} - -/*! - * @brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param baudRate_Bps Baud Rate needed in Hz. - * @param srcClockHz SPI source clock frequency in Hz. - */ -void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz); - -/*! - * @brief Writes one byte of data, which is sent using the MSB method. - * - * @note This is a non-blocking API, which returns directly after the data is put into the - * data register but the data transfer is not finished on the bus. Ensure that - * the TxEmptyFlag is asserted before calling this API. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param direction Shift direction of MSB first or LSB first. - * @param data 8 bit/16 bit data. - */ -static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint16_t data) -{ - if (direction == kFLEXIO_SPI_MsbFirst) - { - base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; - } - else - { - base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = data; - } -} - -/*! - * @brief Reads 8 bit/16 bit data. - * - * @note This is a non-blocking API, which returns directly after the data is read from the - * data register. Ensure that the RxFullFlag is asserted before calling this API. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param direction Shift direction of MSB first or LSB first. - * @return 8 bit/16 bit data received. - */ -static inline uint16_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction) -{ - if (direction == kFLEXIO_SPI_MsbFirst) - { - return base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]; - } - else - { - return base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; - } -} - -/*! - * @brief Sends a buffer of data bytes. - * - * @note This function blocks using the polling method until all bytes have been sent. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param direction Shift direction of MSB first or LSB first. - * @param buffer The data bytes to send. - * @param size The number of data bytes to send. - */ -void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, - flexio_spi_shift_direction_t direction, - const uint8_t *buffer, - size_t size); - -/*! - * @brief Receives a buffer of bytes. - * - * @note This function blocks using the polling method until all bytes have been received. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param direction Shift direction of MSB first or LSB first. - * @param buffer The buffer to store the received bytes. - * @param size The number of data bytes to be received. - * @param direction Shift direction of MSB first or LSB first. - */ -void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, - flexio_spi_shift_direction_t direction, - uint8_t *buffer, - size_t size); - -/*! - * @brief Receives a buffer of bytes. - * - * @note This function blocks via polling until all bytes have been received. - * - * @param base pointer to FLEXIO_SPI_Type structure - * @param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t. - */ -void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer); - -/*Transactional APIs*/ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the FlexIO SPI Master handle, which is used in transactional functions. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. - * @param callback The callback function. - * @param userData The parameter of the callback function. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. - */ -status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, - flexio_spi_master_handle_t *handle, - flexio_spi_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Master transfer data using IRQ. - * - * This function sends data using IRQ. This is a non-blocking function, which returns - * right away. When all data is sent out/received, the callback function is called. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. - * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer. - */ -status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, - flexio_spi_master_handle_t *handle, - flexio_spi_transfer_t *xfer); - -/*! - * @brief Aborts the master data transfer, which used IRQ. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. - */ -void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); - -/*! - * @brief Gets the data transfer status which used IRQ. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count); - -/*! - * @brief FlexIO SPI master IRQ handler function. - * - * @param spiType Pointer to the FLEXIO_SPI_Type structure. - * @param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. - */ -void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle); - -/*! - * @brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. - * @param callback The callback function. - * @param userData The parameter of the callback function. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. - */ -status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, - flexio_spi_slave_handle_t *handle, - flexio_spi_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Slave transfer data using IRQ. - * - * This function sends data using IRQ. This is a non-blocking function, which returns - * right away. When all data is sent out/received, the callback function is called. - * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer. - */ -status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, - flexio_spi_slave_handle_t *handle, - flexio_spi_transfer_t *xfer); - -/*! - * @brief Aborts the slave data transfer which used IRQ, share same API with master. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. - */ -static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle) -{ - FLEXIO_SPI_MasterTransferAbort(base, handle); -} -/*! - * @brief Gets the data transfer status which used IRQ, share same API with master. - * - * @param base Pointer to the FLEXIO_SPI_Type structure. - * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, - flexio_spi_slave_handle_t *handle, - size_t *count) -{ - return FLEXIO_SPI_MasterTransferGetCount(base, handle, count); -} - -/*! - * @brief FlexIO SPI slave IRQ handler function. - * - * @param spiType Pointer to the FLEXIO_SPI_Type structure. - * @param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. - */ -void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ -/*@}*/ - -#endif /*_FSL_FLEXIO_SPI_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi_edma.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi_edma.c deleted file mode 100644 index 2c6aeda82b..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi_edma.c +++ /dev/null @@ -1,442 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flexio_spi_edma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexio_spi_edma" -#endif - -/*base, kFLEXIO_SPI_TxDmaEnable, false); - - /* change the state */ - spiPrivateHandle->handle->txInProgress = false; - - /* All finished, call the callback */ - if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) - { - if (spiPrivateHandle->handle->callback) - { - (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, - spiPrivateHandle->handle->userData); - } - } - } -} - -static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) -{ - tcds = tcds; - flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param; - - if (transferDone) - { - /* Disable Rx dma */ - FLEXIO_SPI_EnableDMA(spiPrivateHandle->base, kFLEXIO_SPI_RxDmaEnable, false); - - /* change the state */ - spiPrivateHandle->handle->rxInProgress = false; - - /* All finished, call the callback */ - if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) - { - if (spiPrivateHandle->handle->callback) - { - (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, - spiPrivateHandle->handle->userData); - } - } - } -} - -static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - flexio_spi_transfer_t *xfer) -{ - edma_transfer_config_t xferConfig; - flexio_spi_shift_direction_t direction; - uint8_t bytesPerFrame; - - /* Configure the values in handle. */ - switch (xfer->flags) - { - case kFLEXIO_SPI_8bitMsb: - bytesPerFrame = 1; - direction = kFLEXIO_SPI_MsbFirst; - break; - case kFLEXIO_SPI_8bitLsb: - bytesPerFrame = 1; - direction = kFLEXIO_SPI_LsbFirst; - break; - case kFLEXIO_SPI_16bitMsb: - bytesPerFrame = 2; - direction = kFLEXIO_SPI_MsbFirst; - break; - case kFLEXIO_SPI_16bitLsb: - bytesPerFrame = 2; - direction = kFLEXIO_SPI_LsbFirst; - break; - default: - bytesPerFrame = 1U; - direction = kFLEXIO_SPI_MsbFirst; - assert(true); - break; - } - - /* Save total transfer size. */ - handle->transferSize = xfer->dataSize; - - /* Configure tx transfer EDMA. */ - xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction); - xferConfig.destOffset = 0; - if (bytesPerFrame == 1U) - { - xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; - xferConfig.destTransferSize = kEDMA_TransferSize1Bytes; - xferConfig.minorLoopBytes = 1; - } - else - { - if (direction == kFLEXIO_SPI_MsbFirst) - { - xferConfig.destAddr -= 1U; - } - xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; - xferConfig.destTransferSize = kEDMA_TransferSize2Bytes; - xferConfig.minorLoopBytes = 2; - } - - /* Configure DMA channel. */ - if (xfer->txData) - { - xferConfig.srcOffset = bytesPerFrame; - xferConfig.srcAddr = (uint32_t)(xfer->txData); - } - else - { - /* Disable the source increasement and source set to dummyData. */ - xferConfig.srcOffset = 0; - xferConfig.srcAddr = (uint32_t)(&s_dummyData); - } - - xferConfig.majorLoopCounts = (xfer->dataSize / xferConfig.minorLoopBytes); - - /* Store the initially configured eDMA minor byte transfer count into the FLEXIO SPI handle */ - handle->nbytes = xferConfig.minorLoopBytes; - - if (handle->txHandle) - { - EDMA_SubmitTransfer(handle->txHandle, &xferConfig); - } - - /* Configure tx transfer EDMA. */ - if (xfer->rxData) - { - xferConfig.srcAddr = FLEXIO_SPI_GetRxDataRegisterAddress(base, direction); - if (bytesPerFrame == 2U) - { - if (direction == kFLEXIO_SPI_LsbFirst) - { - xferConfig.srcAddr -= 1U; - } - } - xferConfig.srcOffset = 0; - xferConfig.destAddr = (uint32_t)(xfer->rxData); - xferConfig.destOffset = bytesPerFrame; - EDMA_SubmitTransfer(handle->rxHandle, &xferConfig); - handle->rxInProgress = true; - FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_RxDmaEnable, true); - EDMA_StartTransfer(handle->rxHandle); - } - - /* Always start Tx transfer. */ - if (handle->txHandle) - { - handle->txInProgress = true; - FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_TxDmaEnable, true); - EDMA_StartTransfer(handle->txHandle); - } -} - -status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - flexio_spi_master_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txHandle, - edma_handle_t *rxHandle) -{ - assert(handle); - - uint8_t index = 0; - - /* Find the an empty handle pointer to store the handle. */ - for (index = 0; index < FLEXIO_SPI_HANDLE_COUNT; index++) - { - if (s_edmaPrivateHandle[index].base == NULL) - { - s_edmaPrivateHandle[index].base = base; - s_edmaPrivateHandle[index].handle = handle; - break; - } - } - - if (index == FLEXIO_SPI_HANDLE_COUNT) - { - return kStatus_OutOfRange; - } - - /* Set spi base to handle. */ - handle->txHandle = txHandle; - handle->rxHandle = rxHandle; - - /* Register callback and userData. */ - handle->callback = callback; - handle->userData = userData; - - /* Set SPI state to idle. */ - handle->txInProgress = false; - handle->rxInProgress = false; - - /* Install callback for Tx/Rx dma channel. */ - if (handle->txHandle) - { - EDMA_SetCallback(handle->txHandle, FLEXIO_SPI_TxEDMACallback, &s_edmaPrivateHandle[index]); - } - if (handle->rxHandle) - { - EDMA_SetCallback(handle->rxHandle, FLEXIO_SPI_RxEDMACallback, &s_edmaPrivateHandle[index]); - } - - return kStatus_Success; -} - -status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - flexio_spi_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - uint32_t dataMode = 0; - uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; - - timerCmp &= 0x00FFU; - - /* Check if the device is busy. */ - if ((handle->txInProgress) || (handle->rxInProgress)) - { - return kStatus_FLEXIO_SPI_Busy; - } - - /* Check if input parameter invalid. */ - if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) - { - return kStatus_InvalidArgument; - } - - /* configure data mode. */ - if ((xfer->flags == kFLEXIO_SPI_8bitMsb) || (xfer->flags == kFLEXIO_SPI_8bitLsb)) - { - dataMode = (8 * 2 - 1U) << 8U; - } - else if ((xfer->flags == kFLEXIO_SPI_16bitMsb) || (xfer->flags == kFLEXIO_SPI_16bitLsb)) - { - dataMode = (16 * 2 - 1U) << 8U; - } - else - { - dataMode = 8 * 2 - 1U; - } - - dataMode |= timerCmp; - - base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - - FLEXIO_SPI_EDMAConfig(base, handle, xfer); - - return kStatus_Success; -} - -status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - if (handle->rxInProgress) - { - *count = (handle->transferSize - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->rxHandle->base, handle->rxHandle->channel)); - } - else - { - *count = (handle->transferSize - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->txHandle->base, handle->txHandle->channel)); - } - - return kStatus_Success; -} - -void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle) -{ - assert(handle); - - /* Disable dma. */ - EDMA_StopTransfer(handle->txHandle); - EDMA_StopTransfer(handle->rxHandle); - - /* Disable DMA enable bit. */ - FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_DmaAllEnable, false); - - /* Set the handle state. */ - handle->txInProgress = false; - handle->rxInProgress = false; -} - -status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, - flexio_spi_slave_edma_handle_t *handle, - flexio_spi_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - - uint32_t dataMode = 0; - - /* Check if the device is busy. */ - if ((handle->txInProgress) || (handle->rxInProgress)) - { - return kStatus_FLEXIO_SPI_Busy; - } - - /* Check if input parameter invalid. */ - if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) - { - return kStatus_InvalidArgument; - } - - /* configure data mode. */ - if ((xfer->flags == kFLEXIO_SPI_8bitMsb) || (xfer->flags == kFLEXIO_SPI_8bitLsb)) - { - dataMode = 8 * 2 - 1U; - } - else if ((xfer->flags == kFLEXIO_SPI_16bitMsb) || (xfer->flags == kFLEXIO_SPI_16bitLsb)) - { - dataMode = 16 * 2 - 1U; - } - else - { - dataMode = 8 * 2 - 1U; - } - - base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - - FLEXIO_SPI_EDMAConfig(base, handle, xfer); - - return kStatus_Success; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi_edma.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi_edma.h deleted file mode 100644 index 5dba8de5a1..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi_edma.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_FLEXIO_SPI_EDMA_H_ -#define _FSL_FLEXIO_SPI_EDMA_H_ - -#include "fsl_flexio_spi.h" -#include "fsl_edma.h" - -/*! - * @addtogroup flexio_edma_spi - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexIO SPI EDMA driver version 2.1.3. */ -#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) -/*@}*/ - -/*! @brief typedef for flexio_spi_master_edma_handle_t in advance. */ -typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t; - -/*! @brief Slave handle is the same with master handle. */ -typedef flexio_spi_master_edma_handle_t flexio_spi_slave_edma_handle_t; - -/*! @brief FlexIO SPI master callback for finished transmit */ -typedef void (*flexio_spi_master_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief FlexIO SPI slave callback for finished transmit */ -typedef void (*flexio_spi_slave_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, - flexio_spi_slave_edma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief FlexIO SPI eDMA transfer handle, users should not touch the content of the handle.*/ -struct _flexio_spi_master_edma_handle -{ - size_t transferSize; /*!< Total bytes to be transferred. */ - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - bool txInProgress; /*!< Send transfer in progress */ - bool rxInProgress; /*!< Receive transfer in progress */ - edma_handle_t *txHandle; /*!< DMA handler for SPI send */ - edma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ - flexio_spi_master_edma_transfer_callback_t callback; /*!< Callback for SPI DMA transfer */ - void *userData; /*!< User Data for SPI DMA callback */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name eDMA Transactional - * @{ - */ - -/*! - * @brief Initializes the FlexIO SPI master eDMA handle. - * - * This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master - * transactional - * APIs. - * For a specified FlexIO SPI instance, call this API once to get the initialized handle. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. - * @param callback SPI callback, NULL means no callback. - * @param userData callback function parameter. - * @param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. - * @param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. - */ -status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - flexio_spi_master_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txHandle, - edma_handle_t *rxHandle); - -/*! - * @brief Performs a non-blocking FlexIO SPI transfer using eDMA. - * - * @note This interface returns immediately after transfer initiates. Call - * FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check - * whether the FlexIO SPI transfer is finished. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. - * @param xfer Pointer to FlexIO SPI transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. - */ -status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - flexio_spi_transfer_t *xfer); - -/*! - * @brief Aborts a FlexIO SPI transfer using eDMA. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle FlexIO SPI eDMA handle pointer. - */ -void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle); - -/*! - * @brief Gets the remaining bytes for FlexIO SPI eDMA transfer. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle FlexIO SPI eDMA handle pointer. - * @param count Number of bytes transferred so far by the non-blocking transaction. - */ -status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, - flexio_spi_master_edma_handle_t *handle, - size_t *count); - -/*! - * @brief Initializes the FlexIO SPI slave eDMA handle. - * - * This function initializes the FlexIO SPI slave eDMA handle. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. - * @param callback SPI callback, NULL means no callback. - * @param userData callback function parameter. - * @param txHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. - * @param rxHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. - */ -static inline void FLEXIO_SPI_SlaveTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, - flexio_spi_slave_edma_handle_t *handle, - flexio_spi_slave_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txHandle, - edma_handle_t *rxHandle) -{ - FLEXIO_SPI_MasterTransferCreateHandleEDMA(base, handle, callback, userData, txHandle, rxHandle); -} - -/*! - * @brief Performs a non-blocking FlexIO SPI transfer using eDMA. - * - * @note This interface returns immediately after transfer initiates. Call - * FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and - * check whether the FlexIO SPI transfer is finished. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. - * @param xfer Pointer to FlexIO SPI transfer structure. - * @retval kStatus_Success Successfully start a transfer. - * @retval kStatus_InvalidArgument Input argument is invalid. - * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. - */ -status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, - flexio_spi_slave_edma_handle_t *handle, - flexio_spi_transfer_t *xfer); - -/*! - * @brief Aborts a FlexIO SPI transfer using eDMA. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. - */ -static inline void FLEXIO_SPI_SlaveTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle) -{ - FLEXIO_SPI_MasterTransferAbortEDMA(base, handle); -} - -/*! - * @brief Gets the remaining bytes to be transferred for FlexIO SPI eDMA. - * - * @param base Pointer to FLEXIO_SPI_Type structure. - * @param handle FlexIO SPI eDMA handle pointer. - * @param count Number of bytes transferred so far by the non-blocking transaction. - */ -static inline status_t FLEXIO_SPI_SlaveTransferGetCountEDMA(FLEXIO_SPI_Type *base, - flexio_spi_slave_edma_handle_t *handle, - size_t *count) -{ - return FLEXIO_SPI_MasterTransferGetCountEDMA(base, handle, count); -} - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart.c deleted file mode 100644 index fd7d550ad4..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart.c +++ /dev/null @@ -1,730 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flexio_uart.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexio_uart" -#endif - - -/*flexioBase); -} - -static size_t FLEXIO_UART_TransferGetRxRingBufferLength(flexio_uart_handle_t *handle) -{ - size_t size; - - if (handle->rxRingBufferTail > handle->rxRingBufferHead) - { - size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); - } - else - { - size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); - } - - return size; -} - -static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle) -{ - bool full; - - if (FLEXIO_UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - - return full; -} - -status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz) -{ - assert(base && userConfig); - - flexio_shifter_config_t shifterConfig; - flexio_timer_config_t timerConfig; - uint32_t ctrlReg = 0; - uint16_t timerDiv = 0; - uint16_t timerCmp = 0; - status_t result = kStatus_Success; - - /* Clear the shifterConfig & timerConfig struct. */ - memset(&shifterConfig, 0, sizeof(shifterConfig)); - memset(&timerConfig, 0, sizeof(timerConfig)); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate flexio clock. */ - CLOCK_EnableClock(s_flexioClocks[FLEXIO_UART_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Configure FLEXIO UART */ - ctrlReg = base->flexioBase->CTRL; - ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); - ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | - FLEXIO_CTRL_FLEXEN(userConfig->enableUart)); - if (!userConfig->enableInDoze) - { - ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; - } - - base->flexioBase->CTRL = ctrlReg; - - /* Do hardware configuration. */ - /* 1. Configure the shifter 0 for tx. */ - shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; - shifterConfig.pinSelect = base->TxPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); - - /*2. Configure the timer 0 for tx. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->TxPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - - timerDiv = srcClock_Hz / userConfig->baudRate_Bps; - timerDiv = timerDiv / 2 - 1; - - if (timerDiv > 0xFFU) - { - result = kStatus_InvalidArgument; - } - - timerCmp = ((uint32_t)(userConfig->bitCountPerChar * 2 - 1)) << 8U; - timerCmp |= timerDiv; - - timerConfig.timerCompare = timerCmp; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); - - /* 3. Configure the shifter 1 for rx. */ - shifterConfig.timerSelect = base->timerIndex[1]; - shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinSelect = base->RxPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; - - FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); - - /* 4. Configure the timer 1 for rx. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex); - timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->RxPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveLow; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - - timerConfig.timerCompare = timerCmp; - - FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); - - return result; -} - -void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base) -{ - base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; - base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; - base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; - base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; - base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; - base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; - base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; - base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; - base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; - base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; - /* Clear the shifter flag. */ - base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]); - base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]); - /* Clear the timer flag. */ - base->flexioBase->TIMSTAT = (1U << base->timerIndex[0]); - base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]); -} - -void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig) -{ - assert(userConfig); - - userConfig->enableUart = true; - userConfig->enableInDoze = false; - userConfig->enableInDebug = true; - userConfig->enableFastAccess = false; - /* Default baud rate 115200. */ - userConfig->baudRate_Bps = 115200U; - /* Default bit count at 8. */ - userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar; -} - -void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); - } - if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable) - { - FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); - } - if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable) - { - FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base) -{ - uint32_t status = 0; - status = - ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); - status |= - (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) - << 1U); - status |= - (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) - << 2U); - return status; -} - -void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask) -{ - if (mask & kFLEXIO_UART_TxDataRegEmptyFlag) - { - FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); - } - if (mask & kFLEXIO_UART_RxDataRegFullFlag) - { - FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); - } - if (mask & kFLEXIO_UART_RxOverRunFlag) - { - FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); - } -} - -void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize) -{ - assert(txData); - assert(txSize); - - while (txSize--) - { - /* Wait until data transfer complete. */ - while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))) - { - } - - base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *txData++; - } -} - -void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize) -{ - assert(rxData); - assert(rxSize); - - while (rxSize--) - { - /* Wait until data transfer complete. */ - while (!(FLEXIO_UART_GetStatusFlags(base) & kFLEXIO_UART_RxDataRegFullFlag)) - { - } - - *rxData++ = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; - } -} - -status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - flexio_uart_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - IRQn_Type flexio_irqs[] = FLEXIO_IRQS; - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set the TX/RX state. */ - handle->rxState = kFLEXIO_UART_RxIdle; - handle->txState = kFLEXIO_UART_TxIdle; - - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - - /* Enable interrupt in NVIC. */ - EnableIRQ(flexio_irqs[FLEXIO_UART_GetInstance(base)]); - - /* Save the context in global variables to support the double weak mechanism. */ - return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ); -} - -void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize) -{ - assert(handle); - - /* Setup the ringbuffer address */ - if (ringBuffer) - { - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - - /* Enable the interrupt to accept the data when user need the ring buffer. */ - FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - } -} - -void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) -{ - assert(handle); - - if (handle->rxState == kFLEXIO_UART_RxIdle) - { - FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - } - - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - flexio_uart_transfer_t *xfer) -{ - status_t status; - - /* Return error if xfer invalid. */ - if ((0U == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* Return error if current TX busy. */ - if (kFLEXIO_UART_TxBusy == handle->txState) - { - status = kStatus_FLEXIO_UART_TxBusy; - } - else - { - handle->txData = xfer->data; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = kFLEXIO_UART_TxBusy; - - /* Enable transmiter interrupt. */ - FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); - - status = kStatus_Success; - } - - return status; -} - -void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) -{ - /* Disable the transmitter and disable the interrupt. */ - FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); - - handle->txDataSize = 0; - handle->txState = kFLEXIO_UART_TxIdle; -} - -status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) -{ - assert(handle); - assert(count); - - if (kFLEXIO_UART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize; - - return kStatus_Success; -} - -status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - flexio_uart_transfer_t *xfer, - size_t *receivedBytes) -{ - uint32_t i; - status_t status; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - - /* Return error if xfer invalid. */ - if ((0U == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to uart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to uart handle, receive data - to this empty space and trigger callback when finished. */ - - if (kFLEXIO_UART_RxBusy == handle->rxState) - { - status = kStatus_FLEXIO_UART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0U; - - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer) - { - /* Disable FLEXIO_UART RX IRQ, protect ring buffer. */ - FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = FLEXIO_UART_TransferGetRxRingBufferLength(handle); - - if (bytesToCopy) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - - bytesToReceive -= bytesToCopy; - - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive) - { - /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kFLEXIO_UART_RxBusy; - } - - /* Enable FLEXIO_UART RX IRQ if previously enabled. */ - FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - } - /* Ring buffer not used. */ - else - { - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kFLEXIO_UART_RxBusy; - - /* Enable RX interrupt. */ - FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - } - - /* Return the how many bytes have read. */ - if (receivedBytes) - { - *receivedBytes = bytesCurrentReceived; - } - - status = kStatus_Success; - } - - return status; -} - -void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) -{ - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (!handle->rxRingBuffer) - { - /* Disable RX interrupt. */ - FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - } - - handle->rxDataSize = 0U; - handle->rxState = kFLEXIO_UART_RxIdle; -} - -status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) -{ - assert(handle); - assert(count); - - if (kFLEXIO_UART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle) -{ - uint8_t count = 1; - FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType; - flexio_uart_handle_t *handle = (flexio_uart_handle_t *)uartHandle; - - /* Read the status back. */ - uint8_t status = FLEXIO_UART_GetStatusFlags(base); - - /* If RX overrun. */ - if (kFLEXIO_UART_RxOverRunFlag & status) - { - /* Clear Overrun flag. */ - FLEXIO_UART_ClearStatusFlags(base, kFLEXIO_UART_RxOverRunFlag); - - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_FLEXIO_UART_RxHardwareOverrun, handle->userData); - } - } - - /* Receive data register full */ - if ((kFLEXIO_UART_RxDataRegFullFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[1]))) - { - /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ - if (handle->rxDataSize) - { - /* Using non block API to read the data from the registers. */ - FLEXIO_UART_ReadByte(base, handle->rxData); - handle->rxDataSize--; - handle->rxData++; - count--; - - /* If all the data required for upper layer is ready, trigger callback. */ - if (!handle->rxDataSize) - { - handle->rxState = kFLEXIO_UART_RxIdle; - - if (handle->callback) - { - handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData); - } - } - } - - if (handle->rxRingBuffer) - { - if (count) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_FLEXIO_UART_RxRingBufferOverrun, handle->userData); - } - } - - /* If ring buffer is still full after callback function, the oldest data is overrided. */ - if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - - /* Read data. */ - handle->rxRingBuffer[handle->rxRingBufferHead] = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; - - /* Increase handle->rxRingBufferHead. */ - if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - /* If no receive requst pending, stop RX interrupt. */ - else if (!handle->rxDataSize) - { - FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); - } - else - { - } - } - - /* Send data register empty and the interrupt is enabled. */ - if ((kFLEXIO_UART_TxDataRegEmptyFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[0]))) - { - if (handle->txDataSize) - { - /* Using non block API to write the data to the registers. */ - FLEXIO_UART_WriteByte(base, handle->txData); - handle->txData++; - handle->txDataSize--; - count--; - - /* If all the data are written to data register, TX finished. */ - if (!handle->txDataSize) - { - handle->txState = kFLEXIO_UART_TxIdle; - - /* Disable TX register empty interrupt. */ - FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); - - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_FLEXIO_UART_TxIdle, handle->userData); - } - } - } - } -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart.h deleted file mode 100644 index 356752a14a..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart.h +++ /dev/null @@ -1,586 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_FLEXIO_UART_H_ -#define _FSL_FLEXIO_UART_H_ - -#include "fsl_common.h" -#include "fsl_flexio.h" - -/*! - * @addtogroup flexio_uart - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexIO UART driver version 2.1.4. */ -#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) -/*@}*/ - -/*! @brief Error codes for the UART driver. */ -enum _flexio_uart_status -{ - kStatus_FLEXIO_UART_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 0), /*!< Transmitter is busy. */ - kStatus_FLEXIO_UART_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 1), /*!< Receiver is busy. */ - kStatus_FLEXIO_UART_TxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 2), /*!< UART transmitter is idle. */ - kStatus_FLEXIO_UART_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 3), /*!< UART receiver is idle. */ - kStatus_FLEXIO_UART_ERROR = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4), /*!< ERROR happens on UART. */ - kStatus_FLEXIO_UART_RxRingBufferOverrun = - MAKE_STATUS(kStatusGroup_FLEXIO_UART, 5), /*!< UART RX software ring buffer overrun. */ - kStatus_FLEXIO_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 6) /*!< UART RX receiver overrun. */ -}; - -/*! @brief FlexIO UART bit count per char. */ -typedef enum _flexio_uart_bit_count_per_char -{ - kFLEXIO_UART_7BitsPerChar = 7U, /*!< 7-bit data characters */ - kFLEXIO_UART_8BitsPerChar = 8U, /*!< 8-bit data characters */ - kFLEXIO_UART_9BitsPerChar = 9U, /*!< 9-bit data characters */ -} flexio_uart_bit_count_per_char_t; - -/*! @brief Define FlexIO UART interrupt mask. */ -enum _flexio_uart_interrupt_enable -{ - kFLEXIO_UART_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ - kFLEXIO_UART_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ -}; - -/*! @brief Define FlexIO UART status mask. */ -enum _flexio_uart_status_flags -{ - kFLEXIO_UART_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ - kFLEXIO_UART_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ - kFLEXIO_UART_RxOverRunFlag = 0x4U, /*!< Receive buffer over run flag. */ -}; - -/*! @brief Define FlexIO UART access structure typedef. */ -typedef struct _flexio_uart_type -{ - FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ - uint8_t TxPinIndex; /*!< Pin select for UART_Tx. */ - uint8_t RxPinIndex; /*!< Pin select for UART_Rx. */ - uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO UART. */ - uint8_t timerIndex[2]; /*!< Timer index used in FlexIO UART. */ -} FLEXIO_UART_Type; - -/*! @brief Define FlexIO UART user configuration structure. */ -typedef struct _flexio_uart_config -{ - bool enableUart; /*!< Enable/disable FlexIO UART TX & RX. */ - bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode*/ - bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode*/ - bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, - fast access requires the FlexIO clock to be at least - twice the frequency of the bus clock. */ - uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ - flexio_uart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 7/8/9 -bit */ -} flexio_uart_config_t; - -/*! @brief Define FlexIO UART transfer structure. */ -typedef struct _flexio_uart_transfer -{ - uint8_t *data; /*!< Transfer buffer*/ - size_t dataSize; /*!< Transfer size*/ -} flexio_uart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _flexio_uart_handle flexio_uart_handle_t; - -/*! @brief FlexIO UART transfer callback function. */ -typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Define FLEXIO UART handle structure*/ -struct _flexio_uart_handle -{ - uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t txDataSizeAll; /*!< Total bytes to be sent. */ - size_t rxDataSizeAll; /*!< Total bytes to be received. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - flexio_uart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART - * hardware, and configures the FlexIO UART with FlexIO UART configuration. - * The configuration structure can be filled by the user or be set with - * default values by FLEXIO_UART_GetDefaultConfig(). - * - * Example - @code - FLEXIO_UART_Type base = { - .flexioBase = FLEXIO, - .TxPinIndex = 0, - .RxPinIndex = 1, - .shifterIndex = {0,1}, - .timerIndex = {0,1} - }; - flexio_uart_config_t config = { - .enableInDoze = false, - .enableInDebug = true, - .enableFastAccess = false, - .baudRate_Bps = 115200U, - .bitCountPerChar = 8 - }; - FLEXIO_UART_Init(base, &config, srcClock_Hz); - @endcode - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param userConfig Pointer to the flexio_uart_config_t structure. - * @param srcClock_Hz FlexIO source clock in Hz. - * @retval kStatus_Success Configuration success - * @retval kStatus_InvalidArgument Buadrate configuration out of range -*/ -status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz); - -/*! - * @brief Resets the FlexIO UART shifter and timer config. - * - * @note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module. - * - * @param base Pointer to FLEXIO_UART_Type structure -*/ -void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base); - -/*! - * @brief Gets the default configuration to configure the FlexIO UART. The configuration - * can be used directly for calling the FLEXIO_UART_Init(). - * Example: - @code - flexio_uart_config_t config; - FLEXIO_UART_GetDefaultConfig(&userConfig); - @endcode - * @param userConfig Pointer to the flexio_uart_config_t structure. -*/ -void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig); - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the FlexIO UART status flags. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @return FlexIO UART status flags. -*/ - -uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base); - -/*! - * @brief Gets the FlexIO UART status flags. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param mask Status flag. - * The parameter can be any combination of the following values: - * @arg kFLEXIO_UART_TxDataRegEmptyFlag - * @arg kFLEXIO_UART_RxEmptyFlag - * @arg kFLEXIO_UART_RxOverRunFlag -*/ - -void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the FlexIO UART interrupt. - * - * This function enables the FlexIO UART interrupt. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param mask Interrupt source. - */ -void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); - -/*! - * @brief Disables the FlexIO UART interrupt. - * - * This function disables the FlexIO UART interrupt. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param mask Interrupt source. - */ -void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Gets the FlexIO UARt transmit data register address. - * - * This function returns the UART data register address, which is mainly used by DMA/eDMA. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @return FlexIO UART transmit data register address. - */ -static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base) -{ - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); -} - -/*! - * @brief Gets the FlexIO UART receive data register address. - * - * This function returns the UART data register address, which is mainly used by DMA/eDMA. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @return FlexIO UART receive data register address. - */ -static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base) -{ - return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferByteSwapped, base->shifterIndex[1]); -} - -/*! - * @brief Enables/disables the FlexIO UART transmit DMA. - * This function enables/disables the FlexIO UART Tx DMA, - * which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn't trigger the DMA request. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param enable True to enable, false to disable. - */ -static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable) -{ - FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterIndex[0], enable); -} - -/*! - * @brief Enables/disables the FlexIO UART receive DMA. - * This function enables/disables the FlexIO UART Rx DMA, - * which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn't trigger the DMA request. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param enable True to enable, false to disable. - */ -static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable) -{ - FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterIndex[1], enable); -} - -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Enables/disables the FlexIO UART module operation. - * - * @param base Pointer to the FLEXIO_UART_Type. - * @param enable True to enable, false does not have any effect. -*/ -static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable) -{ - if (enable) - { - base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; - } -} - -/*! - * @brief Writes one byte of data. - * - * @note This is a non-blocking API, which returns directly after the data is put into the - * data register. Ensure that the TxEmptyFlag is asserted before calling - * this API. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param buffer The data bytes to send. - */ -static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer) -{ - base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *buffer; -} - -/*! - * @brief Reads one byte of data. - * - * @note This is a non-blocking API, which returns directly after the data is read from the - * data register. Ensure that the RxFullFlag is asserted before calling this API. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param buffer The buffer to store the received bytes. - */ -static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer) -{ - *buffer = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; -} - -/*! - * @brief Sends a buffer of data bytes. - * - * @note This function blocks using the polling method until all bytes have been sent. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param txData The data bytes to send. - * @param txSize The number of data bytes to send. - */ -void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize); - -/*! - * @brief Receives a buffer of bytes. - * - * @note This function blocks using the polling method until all bytes have been received. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param rxData The buffer to store the received bytes. - * @param rxSize The number of data bytes to be received. - */ -void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the UART handle. - * - * This function initializes the FlexIO UART handle, which can be used for other FlexIO - * UART transactional APIs. Call this API once to get the - * initialized handle. - * - * The UART driver supports the "background" receiving, which means that users can set up - * a RX ring buffer optionally. Data received is stored into the ring buffer even when - * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data - * received in the ring buffer, users can get the received data from the ring buffer - * directly. The ring buffer is disabled if passing NULL as @p ringBuffer. - * - * @param base to FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - * @param callback The callback function. - * @param userData The parameter of the callback function. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. - */ -status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - flexio_uart_transfer_callback_t callback, - void *userData); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific UART handle. - * - * When the RX ring buffer is used, data received is stored into the ring buffer even when - * the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received - * in the ring buffer, users can get the received data from the ring buffer directly. - * - * @note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize Size of the ring buffer. - */ -void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - */ -void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, - * which returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in ISR, the FlexIO UART driver calls the callback - * function and passes the @ref kStatus_FLEXIO_UART_TxIdle as status parameter. - * - * @note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However, it does not ensure that all data is sent out. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - * @param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t. - * @retval kStatus_Success Successfully starts the data transmission. - * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register. - */ -status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - flexio_uart_transfer_t *xfer); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt-driven data sending. Get the remainBytes to find out - * how many bytes are still not sent out. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - */ -void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); - -/*! - * @brief Gets the number of bytes sent. - * - * This function gets the number of bytes sent driven by interrupt. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - * @param count Number of bytes sent so far by the non-blocking transaction. - * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); - -/*! - * @brief Receives a buffer of data using the interrupt method. - * - * This function receives data using the interrupt method. This is a non-blocking function, - * which returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in ring buffer is not enough to read, the receive - * request is saved by the UART driver. When new data arrives, the receive request - * is serviced first. When all data is received, the UART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. - * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, - * the 5 bytes are copied to xfer->data. This function returns with the - * parameter @p receivedBytes set to 5. For the last 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to xfer->data. When all data is received, the upper layer is notified. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - * @param xfer UART transfer structure. See #flexio_uart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into the transmit queue. - * @retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished. - */ -status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, - flexio_uart_handle_t *handle, - flexio_uart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the receive data which was using IRQ. - * - * This function aborts the receive data which was using IRQ. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - */ -void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); - -/*! - * @brief Gets the number of bytes received. - * - * This function gets the number of bytes received driven by interrupt. - * - * @param base Pointer to the FLEXIO_UART_Type structure. - * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. - * @param count Number of bytes received so far by the non-blocking transaction. - * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); - -/*! - * @brief FlexIO UART IRQ handler function. - * - * This function processes the FlexIO UART transmit and receives the IRQ request. - * - * @param uartType Pointer to the FLEXIO_UART_Type structure. - * @param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state. - */ -void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ -/*@}*/ - -#endif /*_FSL_FLEXIO_UART_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart_edma.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart_edma.c deleted file mode 100644 index 3b008e620f..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart_edma.c +++ /dev/null @@ -1,360 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flexio_uart_edma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexio_uart_edma" -#endif - - -/*handle); - - /* Avoid the warning for unused variables. */ - handle = handle; - tcds = tcds; - - if (transferDone) - { - FLEXIO_UART_TransferAbortSendEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); - - if (uartPrivateHandle->handle->callback) - { - uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, - kStatus_FLEXIO_UART_TxIdle, uartPrivateHandle->handle->userData); - } - } -} - -static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle, - void *param, - bool transferDone, - uint32_t tcds) -{ - flexio_uart_edma_private_handle_t *uartPrivateHandle = (flexio_uart_edma_private_handle_t *)param; - - assert(uartPrivateHandle->handle); - - /* Avoid the warning for unused variables. */ - handle = handle; - tcds = tcds; - - if (transferDone) - { - /* Disable transfer. */ - FLEXIO_UART_TransferAbortReceiveEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); - - if (uartPrivateHandle->handle->callback) - { - uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, - kStatus_FLEXIO_UART_RxIdle, uartPrivateHandle->handle->userData); - } - } -} - -status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - flexio_uart_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txEdmaHandle, - edma_handle_t *rxEdmaHandle) -{ - assert(handle); - - uint8_t index = 0; - - /* Find the an empty handle pointer to store the handle. */ - for (index = 0; index < FLEXIO_UART_HANDLE_COUNT; index++) - { - if (s_edmaPrivateHandle[index].base == NULL) - { - s_edmaPrivateHandle[index].base = base; - s_edmaPrivateHandle[index].handle = handle; - break; - } - } - - if (index == FLEXIO_UART_HANDLE_COUNT) - { - return kStatus_OutOfRange; - } - - memset(handle, 0, sizeof(*handle)); - - handle->rxState = kFLEXIO_UART_RxIdle; - handle->txState = kFLEXIO_UART_TxIdle; - - handle->rxEdmaHandle = rxEdmaHandle; - handle->txEdmaHandle = txEdmaHandle; - - handle->callback = callback; - handle->userData = userData; - - /* Configure TX. */ - if (txEdmaHandle) - { - EDMA_SetCallback(handle->txEdmaHandle, FLEXIO_UART_TransferSendEDMACallback, &s_edmaPrivateHandle); - } - - /* Configure RX. */ - if (rxEdmaHandle) - { - EDMA_SetCallback(handle->rxEdmaHandle, FLEXIO_UART_TransferReceiveEDMACallback, &s_edmaPrivateHandle); - } - - return kStatus_Success; -} - -status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - flexio_uart_transfer_t *xfer) -{ - assert(handle->txEdmaHandle); - - edma_transfer_config_t xferConfig; - status_t status; - - /* Return error if xfer invalid. */ - if ((0U == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* If previous TX not finished. */ - if (kFLEXIO_UART_TxBusy == handle->txState) - { - status = kStatus_FLEXIO_UART_TxBusy; - } - else - { - handle->txState = kFLEXIO_UART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), - (void *)FLEXIO_UART_GetTxDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t), - xfer->dataSize, kEDMA_MemoryToPeripheral); - - /* Store the initially configured eDMA minor byte transfer count into the FLEXIO UART handle */ - handle->nbytes = sizeof(uint8_t); - - /* Submit transfer. */ - EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); - EDMA_StartTransfer(handle->txEdmaHandle); - - /* Enable UART TX EDMA. */ - FLEXIO_UART_EnableTxDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - flexio_uart_transfer_t *xfer) -{ - assert(handle->rxEdmaHandle); - - edma_transfer_config_t xferConfig; - status_t status; - - /* Return error if xfer invalid. */ - if ((0U == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* If previous RX not finished. */ - if (kFLEXIO_UART_RxBusy == handle->rxState) - { - status = kStatus_FLEXIO_UART_RxBusy; - } - else - { - handle->rxState = kFLEXIO_UART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, (void *)FLEXIO_UART_GetRxDataRegisterAddress(base), sizeof(uint8_t), - xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); - - /* Store the initially configured eDMA minor byte transfer count into the FLEXIO UART handle */ - handle->nbytes = sizeof(uint8_t); - - /* Submit transfer. */ - EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); - EDMA_StartTransfer(handle->rxEdmaHandle); - - /* Enable UART RX EDMA. */ - FLEXIO_UART_EnableRxDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle) -{ - assert(handle->txEdmaHandle); - - /* Disable UART TX EDMA. */ - FLEXIO_UART_EnableTxDMA(base, false); - - /* Stop transfer. */ - EDMA_StopTransfer(handle->txEdmaHandle); - - handle->txState = kFLEXIO_UART_TxIdle; -} - -void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle) -{ - assert(handle->rxEdmaHandle); - - /* Disable UART RX EDMA. */ - FLEXIO_UART_EnableRxDMA(base, false); - - /* Stop transfer. */ - EDMA_StopTransfer(handle->rxEdmaHandle); - - handle->rxState = kFLEXIO_UART_RxIdle; -} - -status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - size_t *count) -{ - assert(handle); - assert(handle->rxEdmaHandle); - assert(count); - - if (kFLEXIO_UART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); - - return kStatus_Success; -} - -status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count) -{ - assert(handle); - assert(handle->txEdmaHandle); - assert(count); - - if (kFLEXIO_UART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); - - return kStatus_Success; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart_edma.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart_edma.h deleted file mode 100644 index 153525abf3..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart_edma.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_FLEXIO_UART_EDMA_H_ -#define _FSL_FLEXIO_UART_EDMA_H_ - -#include "fsl_flexio_uart.h" -#include "fsl_edma.h" - -/*! - * @addtogroup flexio_edma_uart - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexIO UART EDMA driver version 2.1.4. */ -#define FSL_FLEXIO_UART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) -/*@}*/ - -/* Forward declaration of the handle typedef. */ -typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t; - -/*! @brief UART transfer callback function. */ -typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - status_t status, - void *userData); - -/*! -* @brief UART eDMA handle -*/ -struct _flexio_uart_edma_handle -{ - flexio_uart_edma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< UART callback function parameter.*/ - - size_t txDataSizeAll; /*!< Total bytes to be sent. */ - size_t rxDataSizeAll; /*!< Total bytes to be received. */ - - edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ - edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ - - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name eDMA transactional - * @{ - */ - -/*! - * @brief Initializes the UART handle which is used in transactional functions. - * - * @param base Pointer to FLEXIO_UART_Type. - * @param handle Pointer to flexio_uart_edma_handle_t structure. - * @param callback The callback function. - * @param userData The parameter of the callback function. - * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. - * @param txEdmaHandle User requested DMA handle for TX DMA transfer. - * @retval kStatus_Success Successfully create the handle. - * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. - */ -status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - flexio_uart_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txEdmaHandle, - edma_handle_t *rxEdmaHandle); - -/*! - * @brief Sends data using eDMA. - * - * This function sends data using eDMA. This is a non-blocking function, which returns - * right away. When all data is sent out, the send callback function is called. - * - * @param base Pointer to FLEXIO_UART_Type - * @param handle UART handle pointer. - * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going. - */ -status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - flexio_uart_transfer_t *xfer); - -/*! - * @brief Receives data using eDMA. - * - * This function receives data using eDMA. This is a non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base Pointer to FLEXIO_UART_Type - * @param handle Pointer to flexio_uart_edma_handle_t structure - * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_UART_RxBusy Previous transfer on going. - */ -status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - flexio_uart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data which using eDMA. - * - * This function aborts sent data which using eDMA. - * - * @param base Pointer to FLEXIO_UART_Type - * @param handle Pointer to flexio_uart_edma_handle_t structure - */ -void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle); - -/*! - * @brief Aborts the receive data which using eDMA. - * - * This function aborts the receive data which using eDMA. - * - * @param base Pointer to FLEXIO_UART_Type - * @param handle Pointer to flexio_uart_edma_handle_t structure - */ -void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle); - -/*! - * @brief Gets the number of bytes sent out. - * - * This function gets the number of bytes sent out. - * - * @param base Pointer to FLEXIO_UART_Type - * @param handle Pointer to flexio_uart_edma_handle_t structure - * @param count Number of bytes sent so far by the non-blocking transaction. - * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count); - -/*! - * @brief Gets the number of bytes received. - * - * This function gets the number of bytes received. - * - * @param base Pointer to FLEXIO_UART_Type - * @param handle Pointer to flexio_uart_edma_handle_t structure - * @param count Number of bytes received so far by the non-blocking transaction. - * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, - flexio_uart_edma_handle_t *handle, - size_t *count); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_UART_EDMA_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexram.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexram.c deleted file mode 100644 index 45e3f62be2..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexram.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flexram.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexram" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address to be used to gate or ungate the module clock - * - * @param base FLEXRAM base address - * - * @return The FLEXRAM instance - */ -static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base); - -/*! - * @brief FLEXRAM map TCM size to register value - * - * @param tcmBankNum tcm banknumber - * @retval register value correspond to the tcm size - */ -static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum); - -/*! - * @brief FLEXRAM configure TCM size - * This function is used to set the TCM to the actual size.When access to the TCM memory boundary ,hardfault will - * raised by core. - * @param itcmBankNum itcm bank number to allocate - * @param dtcmBankNum dtcm bank number to allocate - */ -static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to FLEXRAM bases for each instance. */ -static FLEXRAM_Type *const s_flexramBases[] = FLEXRAM_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to FLEXRAM clocks for each instance. */ -static const clock_ip_name_t s_flexramClocks[] = FLEXRAM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_flexramBases); instance++) - { - if (s_flexramBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_flexramBases)); - - return instance; -} - -void FLEXRAM_Init(FLEXRAM_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate ENET clock. */ - CLOCK_EnableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* enable all the interrupt status */ - base->INT_STAT_EN |= kFLEXRAM_InterruptStatusAll; - /* clear all the interrupt status */ - base->INT_STATUS |= kFLEXRAM_InterruptStatusAll; - /* disable all the interrpt */ - base->INT_SIG_EN = 0U; -} - -void FLEXRAN_Deinit(FLEXRAM_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate ENET clock. */ - CLOCK_DisableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum) -{ - uint8_t tcmSizeConfig = 0U; - - switch (tcmBankNum * FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE) - { - case kFLEXRAM_TCMSize32KB: - tcmSizeConfig = 6U; - break; - - case kFLEXRAM_TCMSize64KB: - tcmSizeConfig = 7U; - break; - - case kFLEXRAM_TCMSize128KB: - tcmSizeConfig = 8U; - break; - - case kFLEXRAM_TCMSize256KB: - tcmSizeConfig = 9U; - break; - - case kFLEXRAM_TCMSize512KB: - tcmSizeConfig = 10U; - break; - - default: - break; - } - - return tcmSizeConfig; -} - -static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum) -{ - /* dtcm configuration */ - if (dtcmBankNum != 0U) - { - IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK; - IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(FLEXRAM_MapTcmSizeToRegister(dtcmBankNum)); - IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK; - } - else - { - IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK; - } - /* itcm configuration */ - if (itcmBankNum != 0U) - { - IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK; - IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(FLEXRAM_MapTcmSizeToRegister(itcmBankNum)); - IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK; - } - else - { - IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK; - } - - return kStatus_Success; -} - -status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config) -{ - uint8_t dtcmBankNum = config->dtcmBankNum; - uint8_t itcmBankNum = config->itcmBankNum; - uint8_t ocramBankNum = config->ocramBankNum; - uint32_t bankCfg = 0U, i = 0U; - - /* check the arguments */ - if ((FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum)) || - ((dtcmBankNum != 0U) && ((dtcmBankNum & (dtcmBankNum - 1u)) != 0U)) || - ((itcmBankNum != 0U) && ((itcmBankNum & (itcmBankNum - 1u)) != 0U))) - { - return kStatus_InvalidArgument; - } - /* flexram bank config value */ - for (i = 0U; i < FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS; i++) - { - if (i < ocramBankNum) - { - bankCfg |= ((uint32_t)kFLEXRAM_BankOCRAM) << (i * 2); - continue; - } - - if (i < (dtcmBankNum + ocramBankNum)) - { - bankCfg |= ((uint32_t)kFLEXRAM_BankDTCM) << (i * 2); - continue; - } - - if (i < (dtcmBankNum + ocramBankNum + itcmBankNum)) - { - bankCfg |= ((uint32_t)kFLEXRAM_BankITCM) << (i * 2); - continue; - } - } - IOMUXC_GPR->GPR17 = bankCfg; - /* set TCM size */ - FLEXRAM_SetTCMSize(itcmBankNum, dtcmBankNum); - /* select ram allocate source from FLEXRAM_BANK_CFG */ - FLEXRAM_SetAllocateRamSrc(kFLEXRAM_BankAllocateThroughBankCfg); - - return kStatus_Success; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexram.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexram.h deleted file mode 100644 index b84e8daec9..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexram.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_FLEXRAM_H_ -#define _FSL_FLEXRAM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flexram - * @{ - */ - -/****************************************************************************** - * Definitions. - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.0.2. */ -#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U)) -/*@}*/ - -/*! @brief flexram write read sel */ -enum _flexram_wr_rd_sel -{ - kFLEXRAM_Read = 0U, /*!< read */ - kFLEXRAM_Write = 1U, /*!< write */ -}; - -/*! @brief Interrupt status flag mask */ -enum _flexram_interrupt_status -{ - kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< ocram access unallocated address */ - kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< dtcm access unallocated address */ - kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< itcm access unallocated address */ - kFLEXRAM_OCRAMMagicAddrMatch = FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK, /*!< ocram maigc address match */ - kFLEXRAM_DTCMMagicAddrMatch = FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK, /*!< dtcm maigc address match */ - kFLEXRAM_ITCMMagicAddrMatch = FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK, /*!< itcm maigc address match */ - - kFLEXRAM_InterruptStatusAll = 0x3FU, /*!< all the interrupt status mask */ -}; - -/*! @brief FLEXRAM TCM access mode -* Fast access mode expected to be finished in 1-cycle -* Wait access mode expected to be finished in 2-cycle -* Wait access mode is a feature of the flexram and it should be used when -* the cpu clock too fast to finish tcm access in 1-cycle. -* Normally, fast mode is the default mode, the efficiency of the tcm access will better. -*/ -typedef enum _flexram_tcm_access_mode -{ - kFLEXRAM_TCMAccessFastMode = 0U, /*!< fast access mode */ - kFLEXRAM_TCMAccessWaitMode = 1U, /*!< wait access mode */ -} flexram_tcm_access_mode_t; - -/*! @brief FLEXRAM bank type */ -enum _flexram_bank_type -{ - kFLEXRAM_BankNotUsed = 0U, /*!< bank is not used */ - kFLEXRAM_BankOCRAM = 1U, /*!< bank is OCRAM */ - kFLEXRAM_BankDTCM = 2U, /*!< bank is DTCM */ - kFLEXRAM_BankITCM = 3U, /*!< bank is ITCM */ -}; - -/*! @brief FLEXRAM tcm support size */ -enum _flexram_tcm_size -{ - kFLEXRAM_TCMSize32KB = 32 * 1024U, /*!< TCM total size 32KB */ - kFLEXRAM_TCMSize64KB = 64 * 1024U, /*!< TCM total size 64KB */ - kFLEXRAM_TCMSize128KB = 128 * 1024U, /*!< TCM total size 128KB */ - kFLEXRAM_TCMSize256KB = 256 * 1024U, /*!< TCM total size 256KB */ - kFLEXRAM_TCMSize512KB = 512 * 1024U, /*!< TCM total size 512KB */ -}; - -/*! @brief FLEXRAM bank allocate source */ -typedef enum _flexram_bank_allocate_src -{ - kFLEXRAM_BankAllocateThroughHardwareFuse = 0U, /*!< allocate ram through hardware fuse value */ - kFLEXRAM_BankAllocateThroughBankCfg = 1U, /*!< allocate ram through FLEXRAM_BANK_CFG */ -} flexram_bank_allocate_src_t; - -/*! @brief FLEXRAM allocate ocram, itcm, dtcm size */ -typedef struct _flexram_allocate_ram -{ - const uint8_t ocramBankNum; /*!< ocram banknumber which the SOC support */ - const uint8_t dtcmBankNum; /*!< dtcm bank number to allocate, the number should be power of 2 */ - const uint8_t itcmBankNum; /*!< itcm bank number to allocate, the number should be power of 2 */ -} flexram_allocate_ram_t; -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief FLEXRAM module initialization function. - * - * @param base FLEXRAM base address. - */ -void FLEXRAM_Init(FLEXRAM_Type *base); - -/*! - * @brief Deinitializes the FLEXRAM. - * - */ -void FLEXRAN_Deinit(FLEXRAM_Type *base); - -/* @} */ - -/*! - * @name Status - * @{ - */ -/*! - * @brief FLEXRAM module get interrupt status. - * - * @param base FLEXRAM base address. - */ -static inline uint32_t FLEXRAM_GetInterruptStatus(FLEXRAM_Type *base) -{ - return base->INT_STATUS & kFLEXRAM_InterruptStatusAll; -} - -/*! - * @brief FLEXRAM module clear interrupt status. - * - * @param base FLEXRAM base address. - * @param status status to clear. - */ -static inline void FLEXRAM_ClearInterruptStatus(FLEXRAM_Type *base, uint32_t status) -{ - base->INT_STATUS |= status; -} - -/*! - * @brief FLEXRAM module enable interrupt status. - * - * @param base FLEXRAM base address. - * @param status status to enable. - */ -static inline void FLEXRAM_EnableInterruptStatus(FLEXRAM_Type *base, uint32_t status) -{ - base->INT_STAT_EN |= status; -} - -/*! - * @brief FLEXRAM module disable interrupt status. - * - * @param base FLEXRAM base address. - * @param status status to disable. - */ -static inline void FLEXRAM_DisableInterruptStatus(FLEXRAM_Type *base, uint32_t status) -{ - base->INT_STAT_EN &= ~status; -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief FLEXRAM module enable interrupt. - * - * @param base FLEXRAM base address. - * @param status status interrupt to enable. - */ -static inline void FLEXRAM_EnableInterruptSignal(FLEXRAM_Type *base, uint32_t status) -{ - base->INT_SIG_EN |= status; -} - -/*! - * @brief FLEXRAM module disable interrupt. - * - * @param base FLEXRAM base address. - * @param status status interrupt to disable. - */ -static inline void FLEXRAM_DisableInterruptSignal(FLEXRAM_Type *base, uint32_t status) -{ - base->INT_SIG_EN &= ~status; -} -/* @} */ - -/*! - * @name functional - * @{ - */ - -/*! - * @brief FLEXRAM module set TCM read access mode - * - * @param base FLEXRAM base address. - * @param mode access mode. - */ -static inline void FLEXRAM_SetTCMReadAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode) -{ - base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK; - base->TCM_CTRL |= mode; -} - -/*! - * @brief FLEXRAM module set TCM write access mode - * - * @param base FLEXRAM base address. - * @param mode access mode. - */ -static inline void FLEXRAM_SetTCMWriteAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode) -{ - base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK; - base->TCM_CTRL |= mode; -} - -/*! - * @brief FLEXRAM module force ram clock on - * - * @param base FLEXRAM base address. - * @param enable enable or disable clock force on. - */ -static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable) -{ - if (enable) - { - base->TCM_CTRL |= FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK; - } - else - { - base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK; - } -} - -/*! - * @brief FLEXRAM OCRAM magic addr configuration - * When read/write access hit magic address, it will generate interrupt - * @param magicAddr magic address. - * @param rwsel read write select, 0 read access , 1 write access - */ -static inline void FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel) -{ - base->OCRAM_MAGIC_ADDR = - FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(rwSel) | FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(magicAddr >> 3U); -} - -/*! - * @brief FLEXRAM DTCM magic addr configuration - * When read/write access hit magic address, it will generate interrupt - * @param magicAddr magic address. - * @param rwsel read write select, 0 read access , 1 write access - */ -static inline void FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel) -{ - base->DTCM_MAGIC_ADDR = - FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(rwSel) | FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(magicAddr >> 3U); -} - -/*! - * @brief FLEXRAM ITCM magic addr configuration - * When read/write access hit magic address, it will generate interrupt - * @param magicAddr magic address. - * @param rwsel read write select, 0 read access , 1 write access - */ -static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel) -{ - base->ITCM_MAGIC_ADDR = - FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(rwSel) | FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(magicAddr >> 3U); -} - -/*! - * @brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM - * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate - * is needed. - * @param config allocate configuration. - * @retval kStatus_InvalidArgument the argument is invalid - * kStatus_Success allocate success - */ -status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config); - -/*! - * @brief FLEXRAM set allocate on-chip ram source - * @param src bank config source select value. - */ -static inline void FLEXRAM_SetAllocateRamSrc(flexram_bank_allocate_src_t src) -{ - IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK; - IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(src); -} - -/*! @}*/ - -#endif diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexspi.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexspi.c deleted file mode 100644 index d74ab47e23..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexspi.c +++ /dev/null @@ -1,868 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flexspi.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexspi" -#endif - - -/******************************************************************************* - * Definitations - ******************************************************************************/ - -#define FREQ_1MHz (1000000UL) -#define FLEXSPI_DLLCR_DEFAULT (0x100UL) -#define FLEXSPI_LUT_KEY_VAL (0x5AF05AF0ul) - -enum -{ - kFLEXSPI_DelayCellUnitMin = 75, /* 75ps. */ - kFLEXSPI_DelayCellUnitMax = 225, /* 225ps. */ -}; - -/*! @brief Common sets of flags used by the driver. */ -enum _flexspi_flag_constants -{ - /*! IRQ sources enabled by the non-blocking transactional API. */ - kIrqFlags = kFLEXSPI_IpTxFifoWatermarkEmpltyFlag | kFLEXSPI_IpRxFifoWatermarkAvailableFlag | - kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag | - kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExcutionDoneFlag, - - /*! Errors to check for. */ - kErrorFlags = kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag | - kFLEXSPI_IpCommandGrantTimeoutFlag, -}; - -enum _flexspi_transfer_state -{ - kFLEXSPI_Idle = 0x0U, /*!< Transfer is done. */ - kFLEXSPI_BusyWrite = 0x1U, /*!< FLEXSPI is busy write transfer. */ - kFLEXSPI_BusyRead = 0x2U, /*!< FLEXSPI is busy write transfer. */ -}; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*flexspi_isr_t)(FLEXSPI_Type *base, void *flexspiHandle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! -* @brief Get the instance number for FLEXSPI. -* -* @param base FLEXSPI base pointer. -*/ -uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base); - -/*! -* @brief Configure flash A/B sample clock DLL. -* -* @param base FLEXSPI base pointer. -* @param config Flash configuration parameters. -*/ -static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config); - -/*! -* @brief Check and clear IP command execution errors. -* -* @param base FLEXSPI base pointer. -* @param status interrupt status. -*/ -status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -/*! @brief Pointers to flexspi handles for each instance. */ -static void *s_flexspiHandle[FSL_FEATURE_SOC_FLEXSPI_COUNT]; -#endif - -/*! @brief Pointers to flexspi bases for each instance. */ -static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS; - -/*! @brief Pointers to flexspi IRQ number for each instance. */ -static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Clock name array */ -static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_FLEXSPI_COUNT; instance++) - { - if (s_flexspiBases[instance] == base) - { - break; - } - } - - assert(instance < FSL_FEATURE_SOC_FLEXSPI_COUNT); - - return instance; -} - -static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config) -{ - bool isUnifiedConfig = true; - uint32_t flexspiDllValue; - uint32_t dllValue; - uint32_t temp; - - uint8_t rxSampleClock = (base->MCR0 & FLEXSPI_MCR0_RXCLKSRC_MASK) >> FLEXSPI_MCR0_RXCLKSRC_SHIFT; - switch (rxSampleClock) - { - case kFLEXSPI_ReadSampleClkLoopbackInternally: - case kFLEXSPI_ReadSampleClkLoopbackFromDqsPad: - case kFLEXSPI_ReadSampleClkLoopbackFromSckPad: - isUnifiedConfig = true; - break; - case kFLEXSPI_ReadSampleClkExternalInputFromDqsPad: - if (config->isSck2Enabled) - { - isUnifiedConfig = true; - } - else - { - isUnifiedConfig = false; - } - break; - default: - break; - } - - if (isUnifiedConfig) - { - flexspiDllValue = FLEXSPI_DLLCR_DEFAULT; /* 1 fixed delay cells in DLL delay chain) */ - } - else - { - if (config->flexspiRootClk >= 100 * FREQ_1MHz) - { - /* DLLEN = 1, SLVDLYTARGET = 0xF, */ - flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x0F); - } - else - { - temp = config->dataValidTime * 1000; /* Convert data valid time in ns to ps. */ - dllValue = temp / kFLEXSPI_DelayCellUnitMin; - if (dllValue * kFLEXSPI_DelayCellUnitMin < temp) - { - dllValue++; - } - flexspiDllValue = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(dllValue); - } - } - return flexspiDllValue; -} - -status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status) -{ - status_t result = kStatus_Success; - - /* Check for error. */ - status &= kErrorFlags; - if (status) - { - /* Select the correct error code.. */ - if (status & kFLEXSPI_SequenceExecutionTimeoutFlag) - { - result = kStatus_FLEXSPI_SequenceExecutionTimeout; - } - else if (status & kFLEXSPI_IpCommandSequenceErrorFlag) - { - result = kStatus_FLEXSPI_IpCommandSequenceError; - } - else if (status & kFLEXSPI_IpCommandGrantTimeoutFlag) - { - result = kStatus_FLEXSPI_IpCommandGrantTimeout; - } - else - { - assert(false); - } - - /* Clear the flags. */ - FLEXSPI_ClearInterruptStatusFlags(base, status); - - /* Reset fifos. These flags clear automatically. */ - base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; - base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; - } - - return result; -} - -void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) -{ - uint32_t configValue = 0; - uint8_t i = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the flexspi clock */ - CLOCK_EnableClock(s_flexspiClock[FLEXSPI_GetInstance(base)]); - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset peripheral before configuring it. */ - base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; - FLEXSPI_SoftwareReset(base); - - /* Configure MCR0 configuration items. */ - configValue = FLEXSPI_MCR0_RXCLKSRC(config->rxSampleClock) | FLEXSPI_MCR0_DOZEEN(config->enableDoze) | - FLEXSPI_MCR0_IPGRANTWAIT(config->ipGrantTimeoutCycle) | - FLEXSPI_MCR0_AHBGRANTWAIT(config->ahbConfig.ahbGrantTimeoutCycle) | - FLEXSPI_MCR0_SCKFREERUNEN(config->enableSckFreeRunning) | - FLEXSPI_MCR0_HSEN(config->enableHalfSpeedAccess) | - FLEXSPI_MCR0_COMBINATIONEN(config->enableCombination) | - FLEXSPI_MCR0_ATDFEN(config->ahbConfig.enableAHBWriteIpTxFifo) | - FLEXSPI_MCR0_ARDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) | FLEXSPI_MCR0_MDIS_MASK; - base->MCR0 = configValue; - - /* Configure MCR1 configurations. */ - configValue = - FLEXSPI_MCR1_SEQWAIT(config->seqTimeoutCycle) | FLEXSPI_MCR1_AHBBUSWAIT(config->ahbConfig.ahbBusTimeoutCycle); - base->MCR1 = configValue; - - /* Configure MCR2 configurations. */ - configValue = base->MCR2; - configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK | FLEXSPI_MCR2_SCKBDIFFOPT_MASK | FLEXSPI_MCR2_SAMEDEVICEEN_MASK | - FLEXSPI_MCR2_CLRAHBBUFOPT_MASK); - configValue |= FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) | - FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) | - FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) | - FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt); - - base->MCR2 = configValue; - - /* Configure AHB control items. */ - configValue = base->AHBCR; - configValue &= ~(FLEXSPI_AHBCR_READADDROPT_MASK | FLEXSPI_AHBCR_PREFETCHEN_MASK | FLEXSPI_AHBCR_BUFFERABLEEN_MASK | - FLEXSPI_AHBCR_CACHABLEEN_MASK); - configValue |= FLEXSPI_AHBCR_READADDROPT(config->ahbConfig.enableReadAddressOpt) | - FLEXSPI_AHBCR_PREFETCHEN(config->ahbConfig.enableAHBPrefetch) | - FLEXSPI_AHBCR_BUFFERABLEEN(config->ahbConfig.enableAHBBufferable) | - FLEXSPI_AHBCR_CACHABLEEN(config->ahbConfig.enableAHBCachable); - base->AHBCR = configValue; - - /* Configure AHB rx buffers. */ - for (i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) - { - configValue = base->AHBRXBUFCR0[i]; - - configValue &= ~(FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK | - FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK); - configValue |= FLEXSPI_AHBRXBUFCR0_PREFETCHEN(config->ahbConfig.buffer[i].enablePrefetch) | - FLEXSPI_AHBRXBUFCR0_PRIORITY(config->ahbConfig.buffer[i].priority) | - FLEXSPI_AHBRXBUFCR0_MSTRID(config->ahbConfig.buffer[i].masterIndex) | - FLEXSPI_AHBRXBUFCR0_BUFSZ(config->ahbConfig.buffer[i].bufferSize * 8); - base->AHBRXBUFCR0[i] = configValue; - } - - /* Configure IP Fifo watermarks. */ - base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXWMRK_MASK; - base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK(config->rxWatermark / 8 - 1); - base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK; - base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK(config->txWatermark / 8 - 1); -} - -void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) -{ - config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally; - config->enableSckFreeRunning = false; - config->enableCombination = false; - config->enableDoze = true; - config->enableHalfSpeedAccess = false; - config->enableSckBDiffOpt = false; - config->enableSameConfigForAll = false; - config->seqTimeoutCycle = 0xFFFFU; - config->ipGrantTimeoutCycle = 0xFFU; - config->txWatermark = 8; - config->rxWatermark = 8; - config->ahbConfig.enableAHBWriteIpTxFifo = false; - config->ahbConfig.enableAHBWriteIpRxFifo = false; - config->ahbConfig.ahbGrantTimeoutCycle = 0xFFU; - config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU; - config->ahbConfig.resumeWaitCycle = 0x20U; - memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer)); - for (uint8_t i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) - { - config->ahbConfig.buffer[i].bufferSize = 256; /* Default buffer size 256 bytes*/ - } - config->ahbConfig.enableClearAHBBufferOpt = false; - config->ahbConfig.enableReadAddressOpt = false; - config->ahbConfig.enableAHBPrefetch = false; - config->ahbConfig.enableAHBBufferable = false; - config->ahbConfig.enableAHBCachable = false; -} - -void FLEXSPI_Deinit(FLEXSPI_Type *base) -{ - /* Reset peripheral. */ - FLEXSPI_SoftwareReset(base); -} - -void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port) -{ - uint32_t configValue = 0; - uint8_t index = port >> 1; /* PortA with index 0, PortB with index 1. */ - - /* Wait for bus idle before change flash configuration. */ - while (!FLEXSPI_GetBusIdleStatus(base)) - { - } - - /* Configure flash size. */ - base->FLSHCR0[index] = 0; - base->FLSHCR0[port] = config->flashSize; - - /* Configure flash parameters. */ - base->FLSHCR1[port] = FLEXSPI_FLSHCR1_CSINTERVAL(config->CSInterval) | - FLEXSPI_FLSHCR1_CSINTERVALUNIT(config->CSIntervalUnit) | - FLEXSPI_FLSHCR1_TCSH(config->CSHoldTime) | FLEXSPI_FLSHCR1_TCSS(config->CSSetupTime) | - FLEXSPI_FLSHCR1_CAS(config->columnspace) | FLEXSPI_FLSHCR1_WA(config->enableWordAddress); - - /* Configure AHB operation items. */ - configValue = base->FLSHCR2[port]; - - configValue &= ~(FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK | FLEXSPI_FLSHCR2_AWRWAIT_MASK | FLEXSPI_FLSHCR2_AWRSEQNUM_MASK | - FLEXSPI_FLSHCR2_AWRSEQID_MASK | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK | FLEXSPI_FLSHCR2_AWRSEQID_MASK); - - configValue |= - FLEXSPI_FLSHCR2_AWRWAITUNIT(config->AHBWriteWaitUnit) | FLEXSPI_FLSHCR2_AWRWAIT(config->AHBWriteWaitInterval); - - if (config->AWRSeqNumber > 0U) - { - configValue |= - FLEXSPI_FLSHCR2_AWRSEQID(config->AWRSeqIndex) | FLEXSPI_FLSHCR2_AWRSEQNUM(config->AWRSeqNumber - 1U); - } - - if (config->ARDSeqNumber > 0U) - { - configValue |= - FLEXSPI_FLSHCR2_ARDSEQID(config->ARDSeqIndex) | FLEXSPI_FLSHCR2_ARDSEQNUM(config->ARDSeqNumber - 1U); - } - - base->FLSHCR2[port] = configValue; - - /* Configure DLL. */ - base->DLLCR[index] = FLEXSPI_ConfigureDll(base, config); - - /* Configure write mask. */ - if (config->enableWriteMask) - { - base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMOPT1_MASK; - } - else - { - base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMOPT1_MASK; - } - - if (index == 0) /*PortA*/ - { - base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK; - base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENA(config->enableWriteMask); - } - else - { - base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENB_MASK; - base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENB(config->enableWriteMask); - } - - /* Exit stop mode. */ - base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; -} - -void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count) -{ - assert(index < 64U); - - uint8_t i = 0; - volatile uint32_t *lutBase; - - /* Wait for bus idle before change flash configuration. */ - while (!FLEXSPI_GetBusIdleStatus(base)) - { - } - - /* Unlock LUT for update. */ - base->LUTKEY = FLEXSPI_LUT_KEY_VAL; - base->LUTCR = 0x02; - - lutBase = &base->LUT[index]; - for (i = index; i < count; i++) - { - *lutBase++ = *cmd++; - } - - /* Lock LUT. */ - base->LUTKEY = FLEXSPI_LUT_KEY_VAL; - base->LUTCR = 0x01; -} - -status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) -{ - uint8_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1; - uint32_t status; - status_t result = kStatus_Success; - uint32_t i = 0; - - /* Send data buffer */ - while (size) - { - /* Wait until there is room in the fifo. This also checks for errors. */ - while (!((status = base->INTR) & kFLEXSPI_IpTxFifoWatermarkEmpltyFlag)) - { - } - - result = FLEXSPI_CheckAndClearError(base, status); - - if (result) - { - return result; - } - - /* Write watermark level data into tx fifo . */ - if (size >= 8 * txWatermark) - { - for (i = 0; i < 2 * txWatermark; i++) - { - base->TFDR[i] = *buffer++; - } - - size = size - 8 * txWatermark; - } - else - { - for (i = 0; i < (size / 4 + 1); i++) - { - base->TFDR[i] = *buffer++; - } - size = 0; - } - - /* Push a watermark level datas into IP TX FIFO. */ - base->INTR |= kFLEXSPI_IpTxFifoWatermarkEmpltyFlag; - } - - return result; -} - -status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) -{ - uint8_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1; - uint32_t status; - status_t result = kStatus_Success; - uint32_t i = 0; - - /* Send data buffer */ - while (size) - { - if (size >= 8 * rxWatermark) - { - /* Wait until there is room in the fifo. This also checks for errors. */ - while (!((status = base->INTR) & kFLEXSPI_IpRxFifoWatermarkAvailableFlag)) - { - result = FLEXSPI_CheckAndClearError(base, status); - - if (result) - { - return result; - } - } - } - else - { - /* Wait fill level. This also checks for errors. */ - while (size > ((((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U)) - { - result = FLEXSPI_CheckAndClearError(base, base->INTR); - - if (result) - { - return result; - } - } - } - - result = FLEXSPI_CheckAndClearError(base, base->INTR); - - if (result) - { - return result; - } - - /* Read watermark level data from rx fifo . */ - if (size >= 8 * rxWatermark) - { - for (i = 0; i < 2 * rxWatermark; i++) - { - *buffer++ = base->RFDR[i]; - } - - size = size - 8 * rxWatermark; - } - else - { - for (i = 0; i < (size / 4 + 1); i++) - { - *buffer++ = base->RFDR[i]; - } - size = 0; - } - - /* Pop out a watermark level datas from IP RX FIFO. */ - base->INTR |= kFLEXSPI_IpRxFifoWatermarkAvailableFlag; - } - - return result; -} - -status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer) -{ - uint32_t configValue = 0; - status_t result = kStatus_Success; - - /* Clear sequence pointer before sending data to external devices. */ - base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; - - /* Clear former pending status before start this tranfer. */ - base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | - FLEXSPI_INTR_IPCMDGE_MASK; - - /* Configure base addresss. */ - base->IPCR0 = xfer->deviceAddress; - - /* Reset fifos. */ - base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; - base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; - - /* Configure data size. */ - if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config)) - { - configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize); - } - - /* Configure sequence ID. */ - configValue |= FLEXSPI_IPCR1_ISEQID(xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM(xfer->SeqNumber - 1); - base->IPCR1 = configValue; - - /* Start Transfer. */ - base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; - - if ((xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config)) - { - result = FLEXSPI_WriteBlocking(base, xfer->data, xfer->dataSize); - } - else if (xfer->cmdType == kFLEXSPI_Read) - { - result = FLEXSPI_ReadBlocking(base, xfer->data, xfer->dataSize); - } - else - { - } - - /* Wait for bus idle. */ - while (!FLEXSPI_GetBusIdleStatus(base)) - { - } - - if (xfer->cmdType == kFLEXSPI_Command) - { - result = FLEXSPI_CheckAndClearError(base, base->INTR); - } - - return result; -} - -void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, - flexspi_handle_t *handle, - flexspi_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - uint32_t instance = FLEXSPI_GetInstance(base); - - /* Zero handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set callback and userData. */ - handle->completionCallback = callback; - handle->userData = userData; - -#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ - /* Save the context in global variables to support the double weak mechanism. */ - s_flexspiHandle[instance] = handle; -#endif - - /* Enable NVIC interrupt. */ - EnableIRQ(s_flexspiIrqs[instance]); -} - -status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer) -{ - uint32_t configValue = 0; - status_t result = kStatus_Success; - - assert(handle); - assert(xfer); - - /* Check if the I2C bus is idle - if not return busy status. */ - if (handle->state != kFLEXSPI_Idle) - { - result = kStatus_FLEXSPI_Busy; - } - else - { - handle->data = xfer->data; - handle->dataSize = xfer->dataSize; - handle->transferTotalSize = xfer->dataSize; - handle->state = (xfer->cmdType == kFLEXSPI_Read) ? kFLEXSPI_BusyRead : kFLEXSPI_BusyWrite; - - /* Clear sequence pointer before sending data to external devices. */ - base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; - - /* Clear former pending status before start this tranfer. */ - base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | - FLEXSPI_INTR_IPCMDGE_MASK; - - /* Configure base addresss. */ - base->IPCR0 = xfer->deviceAddress; - - /* Reset fifos. */ - base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; - base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; - - /* Configure data size. */ - if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write)) - { - configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize); - } - - /* Configure sequence ID. */ - configValue |= FLEXSPI_IPCR1_ISEQID(xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM(xfer->SeqNumber - 1); - base->IPCR1 = configValue; - - /* Start Transfer. */ - base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; - - if (handle->state == kFLEXSPI_BusyRead) - { - FLEXSPI_EnableInterrupts(base, kFLEXSPI_IpRxFifoWatermarkAvailableFlag | - kFLEXSPI_SequenceExecutionTimeoutFlag | - kFLEXSPI_IpCommandSequenceErrorFlag | - kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExcutionDoneFlag); - } - else - { - FLEXSPI_EnableInterrupts(base, kFLEXSPI_IpTxFifoWatermarkEmpltyFlag | - kFLEXSPI_SequenceExecutionTimeoutFlag | - kFLEXSPI_IpCommandSequenceErrorFlag | - kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExcutionDoneFlag); - } - } - - return result; -} - -status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t result = kStatus_Success; - - if (handle->state == kFLEXSPI_Idle) - { - result = kStatus_NoTransferInProgress; - } - else - { - *count = handle->transferTotalSize - handle->dataSize; - } - - return result; -} - -void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle) -{ - assert(handle); - - FLEXSPI_DisableInterrupts(base, kIrqFlags); - handle->state = kFLEXSPI_Idle; -} - -void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) -{ - uint8_t status; - status_t result; - uint8_t txWatermark; - uint8_t rxWatermark; - uint8_t i = 0; - - status = base->INTR; - - result = FLEXSPI_CheckAndClearError(base, status); - - if ((result != kStatus_Success) && (handle->completionCallback != NULL)) - { - FLEXSPI_TransferAbort(base, handle); - if (handle->completionCallback) - { - handle->completionCallback(base, handle, result, handle->userData); - } - return; - } - - if ((status & kFLEXSPI_IpRxFifoWatermarkAvailableFlag) && (handle->state == kFLEXSPI_BusyRead)) - { - rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1; - - /* Read watermark level data from rx fifo . */ - if (handle->dataSize >= 8 * rxWatermark) - { - /* Read watermark level data from rx fifo . */ - for (i = 0; i < 2 * rxWatermark; i++) - { - *handle->data++ = base->RFDR[i]; - } - - handle->dataSize = handle->dataSize - 8 * rxWatermark; - } - else - { - for (i = 0; i < (handle->dataSize / 4 + 1); i++) - { - *handle->data++ = base->RFDR[i]; - } - handle->dataSize = 0; - } - /* Pop out a watermark level datas from IP RX FIFO. */ - base->INTR |= kFLEXSPI_IpRxFifoWatermarkAvailableFlag; - } - - if (status & kFLEXSPI_IpCommandExcutionDoneFlag) - { - base->INTR |= kFLEXSPI_IpCommandExcutionDoneFlag; - - FLEXSPI_TransferAbort(base, handle); - - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_Success, handle->userData); - } - } - - /* TX FIFO empty interrupt, push watermark level data into tx FIFO. */ - if ((status & kFLEXSPI_IpTxFifoWatermarkEmpltyFlag) && (handle->state == kFLEXSPI_BusyWrite)) - { - if (handle->dataSize) - { - txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1; - /* Write watermark level data into tx fifo . */ - if (handle->dataSize >= 8 * txWatermark) - { - for (i = 0; i < 2 * txWatermark; i++) - { - base->TFDR[i] = *handle->data++; - } - - handle->dataSize = handle->dataSize - 8 * txWatermark; - } - else - { - for (i = 0; i < (handle->dataSize / 4 + 1); i++) - { - base->TFDR[i] = *handle->data++; - } - handle->dataSize = 0; - } - - /* Push a watermark level datas into IP TX FIFO. */ - base->INTR |= kFLEXSPI_IpTxFifoWatermarkEmpltyFlag; - } - } - else - { - } -} - -#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -#if defined(FLEXSPI) -void FLEXSPI_DriverIRQHandler(void) -{ - FLEXSPI_TransferHandleIRQ(FLEXSPI, s_flexspiHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXSPI0) -void FLEXSPI0_DriverIRQHandler(void) -{ - FLEXSPI_TransferHandleIRQ(FLEXSPI0, s_flexspiHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#if defined(FLEXSPI1) -void FLEXSPI1_DriverIRQHandler(void) -{ - FLEXSPI_TransferHandleIRQ(FLEXSPI1, s_flexspiHandle[1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexspi.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexspi.h deleted file mode 100644 index e2f00393b3..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_flexspi.h +++ /dev/null @@ -1,844 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_FLEXSPI_H_ -#define __FSL_FLEXSPI_H_ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -/*! - * @addtogroup flexspi - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FLEXSPI driver version 2.0.2. */ -#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0) - -/*! @breif Formula to form FLEXSPI instructions in LUT table. */ -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -/*! @brief Status structure of FLEXSPI.*/ -enum _flexspi_status -{ - kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */ - kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Sequence execution timeout - error occurred during FLEXSPI transfer. */ - kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), /*!< IP command Sequence execution - timeout error occurred during FLEXSPI transfer. */ - kStatus_FLEXSPI_IpCommandGrantTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 3), /*!< IP command grant timeout error - occurred during FLEXSPI transfer. */ -}; - -/*! @brief CMD definition of FLEXSPI, use to form LUT instruction. */ -enum _flexspi_command -{ - kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */ - kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */ - kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */ - kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */ - kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */ - kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */ - kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */ - kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */ - kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */ - kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */ - kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */ - kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */ - kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/ - kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller, - dummy cycles decided by RWDS. */ - kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */ - kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */ - kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */ - kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */ - kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */ - kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */ - kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */ - kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */ - kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */ - kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */ - kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */ - kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/ - kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller, - dummy cycles decided by RWDS. */ - kFLEXSPI_Command_JUMP_ON_CS = 0x1FU, /*!< Stop execution, deassert CS and save operand[7:0] as the - instruction start pointer for next sequence */ -}; - -/*! @brief pad definition of FLEXSPI, use to form LUT instruction. */ -enum _flexspi_pad -{ - kFLEXSPI_1PAD = 0x00U, /*!< Transmit command/address and transmit/receive data only through DATA0/DATA1. */ - kFLEXSPI_2PAD = 0x01U, /*!< Transmit command/address and transmit/receive data only through DATA[1:0]. */ - kFLEXSPI_4PAD = 0x02U, /*!< Transmit command/address and transmit/receive data only through DATA[3:0]. */ - kFLEXSPI_8PAD = 0x03U, /*!< Transmit command/address and transmit/receive data only through DATA[7:0]. */ -}; - -/*! @brief FLEXSPI interrupt status flags.*/ -typedef enum _flexspi_flags -{ - kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */ - kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */ - kFLEXSPI_SckStoppedBecauseTxEmptyFlag = - FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, /*!< SCK is stopped during command - sequence because Async TX FIFO empty. */ - kFLEXSPI_SckStoppedBecauseRxFullFlag = - FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK, /*!< SCK is stopped during command - sequence because Async RX FIFO full. */ -#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) - kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, /*!< Data learning failed. */ -#endif - kFLEXSPI_IpTxFifoWatermarkEmpltyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */ - kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, /*!< IP RX FIFO WaterMark available. */ - kFLEXSPI_AhbCommandSequenceErrorFlag = - FLEXSPI_INTEN_AHBCMDERREN_MASK, /*!< AHB triggered Command Sequences Error. */ - kFLEXSPI_IpCommandSequenceErrorFlag = FLEXSPI_INTEN_IPCMDERREN_MASK, /*!< IP triggered Command Sequences Error. */ - kFLEXSPI_AhbCommandGrantTimeoutFlag = - FLEXSPI_INTEN_AHBCMDGEEN_MASK, /*!< AHB triggered Command Sequences Grant Timeout. */ - kFLEXSPI_IpCommandGrantTimeoutFlag = - FLEXSPI_INTEN_IPCMDGEEN_MASK, /*!< IP triggered Command Sequences Grant Timeout. */ - kFLEXSPI_IpCommandExcutionDoneFlag = - FLEXSPI_INTEN_IPCMDDONEEN_MASK, /*!< IP triggered Command Sequences Execution finished. */ - kFLEXSPI_AllInterruptFlags = 0xFFFU, /*!< All flags. */ -} flexspi_flags_t; - -/*! @brief FLEXSPI sample clock source selection for Flash Reading.*/ -typedef enum _flexspi_read_sample_clock -{ - kFLEXSPI_ReadSampleClkLoopbackInternally = 0x0U, /*!< Dummy Read strobe generated by FlexSPI Controller - and loopback internally. */ - kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by FlexSPI Controller - and loopback from DQS pad. */ - kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U, /*!< SCK output clock and loopback from SCK pad. */ - kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, /*!< Flash provided Read strobe and input from DQS pad. */ -} flexspi_read_sample_clock_t; - -/*! @brief FLEXSPI interval unit for flash device select.*/ -typedef enum _flexspi_cs_interval_cycle_unit -{ - kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */ - kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, /*!< Chip selection interval: CSINTERVAL * 256 serial clock cycle. */ -} flexspi_cs_interval_cycle_unit_t; - -/*! @brief FLEXSPI AHB wait interval unit for writting.*/ -typedef enum _flexspi_ahb_write_wait_unit -{ - kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, /*!< AWRWAIT unit is 32768 ahb clock cycle. */ -} flexspi_ahb_write_wait_unit_t; - -/*! @brief Error Code when IP command Error detected.*/ -typedef enum _flexspi_ip_error_code -{ - kFLEXSPI_IpCmdErrorNoError = 0x0U, /*!< No error. */ - kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U, /*!< IP command with JMP_ON_CS instruction used. */ - kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ - kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR - used in DDR sequence. */ - kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR - used in SDR sequence. */ - kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U, /*!< Flash access start address exceed the whole - flash address range (A1/A2/B1/B2). */ - kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, /*!< Sequence execution timeout. */ - kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU, /*!< Flash boundary crossed. */ -} flexspi_ip_error_code_t; - -/*! @brief Error Code when AHB command Error detected.*/ -typedef enum _flexspi_ahb_error_code -{ - kFLEXSPI_AhbCmdErrorNoError = 0x0U, /*!< No error. */ - kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U, /*!< AHB Write command with JMP_ON_CS instruction - used in the sequence. */ - kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ - kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used - in DDR sequence. */ - kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR - used in SDR sequence. */ - kFLEXSPI_AhbCmdSequenceExecutionTimeout = 0x6U, /*!< Sequence execution timeout. */ -} flexspi_ahb_error_code_t; - -/*! @brief FLEXSPI operation port select.*/ -typedef enum _flexspi_port -{ - kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */ - kFLEXSPI_PortA2 = 0x1U, /*!< Access flash on A2 port. */ - kFLEXSPI_PortB1 = 0x2U, /*!< Access flash on B1 port. */ - kFLEXSPI_PortB2 = 0x3U, /*!< Access flash on B2 port. */ -} flexspi_port_t; - -/*! @brief Trigger source of current command sequence granted by arbitrator.*/ -typedef enum _flexspi_arb_command_source -{ - kFLEXSPI_AhbReadCommand = 0x0U, - kFLEXSPI_AhbWriteCommand = 0x1U, - kFLEXSPI_IpCommand = 0x2U, - kFLEXSPI_SuspendedCommand = 0x3U, -} flexspi_arb_command_source_t; - -typedef enum _flexspi_command_type -{ - kFLEXSPI_Command, /*!< FlexSPI operation: Only command, both TX and Rx buffer are ignored. */ - kFLEXSPI_Config, /*!< FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT. */ - kFLEXSPI_Read, /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */ - kFLEXSPI_Write, /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */ -} flexspi_command_type_t; - -typedef struct _flexspi_ahbBuffer_config -{ - uint8_t priority; /*!< This priority for AHB Master Read which this AHB RX Buffer is assigned. */ - uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */ - uint16_t bufferSize; /*!< AHB buffer size in byte. */ - bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows - prefetch disable/enable seperately for each master. */ -} flexspi_ahbBuffer_config_t; - -/*! @brief FLEXSPI configuration structure. */ -typedef struct _flexspi_config -{ - flexspi_read_sample_clock_t rxSampleClock; /*!< Sample Clock source selection for Flash Reading. */ - bool enableSckFreeRunning; /*!< Enable/disable SCK output free-running. */ - bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins - (SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */ - bool enableDoze; /*!< Enable/disable doze mode support. */ - bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half - speed commands. */ - bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock - output, when enable, Port B flash access is not available. */ - bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices - when enabled, same configuration in FLASHA1CRx is applied to all. */ - uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution, - timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles. */ - uint8_t ipGrantTimeoutCycle; /*!< Timeout wait cycle for IP command grant, timeout after - ipGrantTimeoutCycle*1024 AHB clock cycles. */ - uint8_t txWatermark; /*!< FLEXSPI IP transmit watermark value. */ - uint8_t rxWatermark; /*!< FLEXSPI receive watermark value. */ - struct - { - bool enableAHBWriteIpTxFifo; /*!< Enable AHB bus write access to IP TX FIFO. */ - bool enableAHBWriteIpRxFifo; /*!< Enable AHB bus write access to IP RX FIFO. */ - uint8_t ahbGrantTimeoutCycle; /*!< Timeout wait cycle for AHB command grant, - timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles. */ - uint16_t ahbBusTimeoutCycle; /*!< Timeout wait cycle for AHB read/write access, - timeout after ahbBusTimeoutCycle*1024 AHB clock cycles. */ - uint8_t resumeWaitCycle; /*!< Wait cycle for idle state before suspended command sequence - resume, timeout after ahbBusTimeoutCycle AHB clock cycles. */ - flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */ - bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer - when FLEXSPI returns STOP mode ACK. */ - bool enableReadAddressOpt; /*!< Enable/disable remove AHB read burst start address alignment limitation. - when eanble, there is no AHB read burst start address alignment limitation. */ - bool enableAHBPrefetch; /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI - will fetch more data than current AHB burst. */ - bool enableAHBBufferable; /*!< Enable/disable AHB bufferable write access support, when enabled, - FLEXSPI return before waiting for command excution finished. */ - bool enableAHBCachable; /*!< Enable AHB bus cachable read access support. */ - } ahbConfig; -} flexspi_config_t; - -/*! @brief External device configuration items. */ -typedef struct _flexspi_device_config -{ - uint32_t flexspiRootClk; /*!< FLEXSPI serial root clock. */ - bool isSck2Enabled; /*!< FLEXSPI use SCK2. */ - uint32_t flashSize; /*!< Flash size in KByte. */ - flexspi_cs_interval_cycle_unit_t CSIntervalUnit; /*!< CS interval unit, 1 or 256 cycle. */ - uint16_t CSInterval; /*!< CS line assert interval, mutiply CS interval unit to - get the CS line assert interval cycles. */ - uint8_t CSHoldTime; /*!< CS line hold time. */ - uint8_t CSSetupTime; /*!< CS line setup time. */ - uint8_t dataValidTime; /*!< Data valid time for external device. */ - uint8_t columnspace; /*!< Column space size. */ - bool enableWordAddress; /*!< If enable word address.*/ - uint8_t AWRSeqIndex; /*!< Sequence ID for AHB write command. */ - uint8_t AWRSeqNumber; /*!< Sequence number for AHB write command. */ - uint8_t ARDSeqIndex; /*!< Sequence ID for AHB read command. */ - uint8_t ARDSeqNumber; /*!< Sequence number for AHB read command. */ - flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit; /*!< AHB write wait unit. */ - uint16_t AHBWriteWaitInterval; /*!< AHB write wait interval, mutiply AHB write interval - unit to get the AHB write wait cycles. */ - bool enableWriteMask; /*!< Enable/Disable FLEXSPI drive DQS pin as write mask - when writing to external device. */ -} flexspi_device_config_t; - -/*! @brief Transfer structure for FLEXSPI. */ -typedef struct _flexspi_transfer -{ - uint32_t deviceAddress; /*!< Operation device address. */ - flexspi_port_t port; /*!< Operation port. */ - flexspi_command_type_t cmdType; /*!< Execution command type. */ - uint8_t seqIndex; /*!< Sequence ID for command. */ - uint8_t SeqNumber; /*!< Sequence number for command. */ - uint32_t *data; /*!< Data buffer. */ - size_t dataSize; /*!< Data size in bytes. */ -} flexspi_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _flexspi_handle flexspi_handle_t; - -/*! @brief FLEXSPI transfer callback function. */ -typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base, - flexspi_handle_t *handle, - status_t status, - void *userData); - -/*! @brief Transfer handle structure for FLEXSPI. */ -struct _flexspi_handle -{ - uint32_t state; /*!< Internal state for FLEXSPI transfer */ - uint32_t *data; /*!< Data buffer. */ - size_t dataSize; /*!< Remaining Data size in bytes. */ - size_t transferTotalSize; /*!< Total Data size in bytes. */ - flexspi_transfer_callback_t completionCallback; /*!< Callback for users while transfer finish or error occurred */ - void *userData; /*!< FLEXSPI callback function parameter.*/ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ - -/*! - * @name Initialization and deinitialization - * @{ - */ -/*! - * @brief Initializes the FLEXSPI module and internal state. - * - * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the - * input configure parameters. Users should call this function before any FLEXSPI operations. - * - * @param base FLEXSPI peripheral base address. - * @param config FLEXSPI configure structure. - */ -void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config); - -/*! - * @brief Gets default settings for FLEXSPI. - * - * @param config FLEXSPI configuration structure. - */ -void FLEXSPI_GetDefaultConfig(flexspi_config_t *config); - -/*! - * @brief Deinitializes the FLEXSPI module. - * - * Clears the FLEXSPI state and FLEXSPI module registers. - * @param base FLEXSPI peripheral base address. - */ -void FLEXSPI_Deinit(FLEXSPI_Type *base); - -/*! - * @brief Configures the connected device parameter. - * - * This function configures the connected device relevant parameters, such as the size, command, and so on. - * The flash configuration value cannot have a default value. The user needs to configure it according to the - * connected device. - * - * @param base FLEXSPI peripheral base address. - * @param config Flash configuration parameters. - * @param port FLEXSPI Operation port. - */ -void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port); - -/*! - * @brief Software reset for the FLEXSPI logic. - * - * This function sets the software reset flags for both AHB and buffer domain and - * resets both AHB buffer and also IP FIFOs. - * - * @param base FLEXSPI peripheral base address. - */ -static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base) -{ - base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; - while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) - { - } -} - -/*! - * @brief Enables or disables the FLEXSPI module. - * - * @param base FLEXSPI peripheral base address. - * @param enable True means enable FLEXSPI, false means disable. - */ -static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable) -{ - if (enable) - { - base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; - } - else - { - base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; - } -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ -/*! - * @brief Enables the FLEXSPI interrupts. - * - * @param base FLEXSPI peripheral base address. - * @param mask FLEXSPI interrupt source. - */ -static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask) -{ - base->INTEN |= mask; -} - -/*! - * @brief Disable the FLEXSPI interrupts. - * - * @param base FLEXSPI peripheral base address. - * @param mask FLEXSPI interrupt source. - */ -static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask) -{ - base->INTEN &= ~mask; -} - -/* @} */ - -/*! @name DMA control */ -/*@{*/ - -/*! - * @brief Enables or disables FLEXSPI IP Tx FIFO DMA requests. - * - * @param base FLEXSPI peripheral base address. - * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable. - */ -static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable) -{ - if (enable) - { - base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK; - } - else - { - base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK; - } -} - -/*! - * @brief Enables or disables FLEXSPI IP Rx FIFO DMA requests. - * - * @param base FLEXSPI peripheral base address. - * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable. - */ -static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable) -{ - if (enable) - { - base->IPRXFCR |= FLEXSPI_IPRXFCR_RXDMAEN_MASK; - } - else - { - base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXDMAEN_MASK; - } -} - -/*! - * @brief Gets FLEXSPI IP tx fifo address for DMA transfer. - * - * @param base FLEXSPI peripheral base address. - * @retval The tx fifo address. - */ -static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base) -{ - return (uint32_t)&base->TFDR[0]; -} - -/*! - * @brief Gets FLEXSPI IP rx fifo address for DMA transfer. - * - * @param base FLEXSPI peripheral base address. - * @retval The rx fifo address. - */ -static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base) -{ - return (uint32_t)&base->RFDR[0]; -} - -/*@}*/ - -/*! @name FIFO control */ -/*@{*/ - -/*! @brief Clears the FLEXSPI IP FIFO logic. - * - * @param base FLEXSPI peripheral base address. - * @param txFifo Pass true to reset TX FIFO. - * @param rxFifo Pass true to reset RX FIFO. - */ -static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo) -{ - if (txFifo) - { - base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; - } - if (rxFifo) - { - base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; - } -} - -/*! - * @brief Gets the valid data entries in the FLEXSPI FIFOs. - * - * @param base FLEXSPI peripheral base address. - * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. - * Pass NULL if this value is not required. - * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. - * Pass NULL if this value is not required. - */ -static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount) -{ - if (txCount) - { - *txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U; - } - if (rxCount) - { - *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U; - } -} - -/*@}*/ - -/*! - * @name Status - * @{ - */ -/*! - * @brief Get the FLEXSPI interrupt status flags. - * - * @param base FLEXSPI peripheral base address. - * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status. - */ -static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base) -{ - return base->INTR; -} - -/*! - * @brief Get the FLEXSPI interrupt status flags. - * - * @param base FLEXSPI peripheral base address. - * @param interrupt status flag. - */ -static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask) -{ - base->INTR |= mask; -} - -#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) -/*! @brief Gets the sampling clock phase selection after Data Learning. - * - * @param base FLEXSPI peripheral base address. - * @param portAPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTA. - * @param portBPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTB. - */ -static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *portAPhase, uint8_t *portBPhase) -{ - if (portAPhase) - { - *portAPhase = (base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT; - } - - if (portBPhase) - { - *portBPhase = (base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT; - } -} -#endif - -/*! @brief Gets the trigger source of current command sequence granted by arbitrator. - * - * @param base FLEXSPI peripheral base address. - * @retval trigger source of current command sequence. - */ -static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base) -{ - return (flexspi_arb_command_source_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT); -} - -/*! @brief Gets the error code when IP command error detected. - * - * @param base FLEXSPI peripheral base address. - * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. - * @retval error code when IP command error detected. - */ -static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) -{ - *index = (base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT; - return (flexspi_ip_error_code_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT); -} - -/*! @brief Gets the error code when AHB command error detected. - * - * @param base FLEXSPI peripheral base address. - * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. - * @retval error code when AHB command error detected. - */ -static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) -{ - *index = (base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT; - return (flexspi_ahb_error_code_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> - FLEXSPI_STS1_AHBCMDERRCODE_SHIFT); -} - -/*! @brief Returns whether the bus is idle. - * - * @param base FLEXSPI peripheral base address. - * @retval true Bus is idle. - * @retval false Bus is busy. - */ -static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base) -{ - return (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK); -} -/*@}*/ - -/*! - * @name Bus Operations - * @{ - */ - -/*! @brief Enables/disables the FLEXSPI IP command parallel mode. - * - * @param base FLEXSPI peripheral base address. - * @param enable True means enable parallel mode, false means disable parallel mode. - */ -static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable) -{ - if (enable) - { - base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK; - } - else - { - base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK; - } -} - -/*! @brief Enables/disables the FLEXSPI AHB command parallel mode. - * - * @param base FLEXSPI peripheral base address. - * @param enable True means enable parallel mode, false means disable parallel mode. - */ -static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable) -{ - if (enable) - { - base->AHBCR |= FLEXSPI_AHBCR_APAREN_MASK; - } - else - { - base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK; - } -} - -/*! @brief Updates the LUT table. -* -* @param base FLEXSPI peripheral base address. -* @param index From which index start to update. It could be any index of the LUT table, which -* also allows user to update command content inside a command. Each command consists of up to -* 8 instructions and occupy 4*32-bit memory. -* @param cmd Command sequence array. -* @param count Number of sequences. -*/ -void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count); - -/*! - * @brief Writes data into FIFO. - * - * @param base FLEXSPI peripheral base address - * @param data The data bytes to send - * @param fifoIndex Destination fifo index. - */ -static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex) -{ - base->TFDR[fifoIndex] = data; -} - -/*! - * @brief Receives data from data FIFO. - * - * @param base FLEXSPI peripheral base address - * @param fifoIndex Source fifo index. - * @return The data in the FIFO. - */ -static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex) -{ - return base->RFDR[fifoIndex]; -} - -/*! - * @brief Sends a buffer of data bytes using blocking method. - * @note This function blocks via polling until all bytes have been sent. - * @param base FLEXSPI peripheral base address - * @param buffer The data bytes to send - * @param size The number of data bytes to send - * @retval kStatus_Success write success without error - * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout - * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected - * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected - */ -status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size); - -/*! - * @brief Receives a buffer of data bytes using a blocking method. - * @note This function blocks via polling until all bytes have been sent. - * @param base FLEXSPI peripheral base address - * @param buffer The data bytes to send - * @param size The number of data bytes to receive - * @retval kStatus_Success read success without error - * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout - * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected - * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected - */ -status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size); - -/*! - * @brief Execute command to transfer a buffer data bytes using a blocking method. - * @param base FLEXSPI peripheral base address - * @param xfer pointer to the transfer structure. - * @retval kStatus_Success command transfer success without error - * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout - * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected - * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected -*/ -status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer); -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the FLEXSPI handle which is used in transactional functions. - * - * @param base FLEXSPI peripheral base address. - * @param handle pointer to flexspi_handle_t structure to store the transfer state. - * @param callback pointer to user callback function. - * @param userData user parameter passed to the callback function. - */ -void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, - flexspi_handle_t *handle, - flexspi_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a interrupt non-blocking transfer on the FLEXSPI bus. - * - * @note Calling the API returns immediately after transfer initiates. The user needs - * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether - * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer - * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark levle, or - * FLEXSPI could not read data properly. - * - * @param base FLEXSPI peripheral base address. - * @param handle pointer to flexspi_handle_t structure which stores the transfer state. - * @param xfer pointer to flexspi_transfer_t structure. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_FLEXSPI_Busy Previous transmission still not finished. - */ -status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer); - -/*! - * @brief Gets the master transfer status during a interrupt non-blocking transfer. - * - * @param base FLEXSPI peripheral base address. - * @param handle pointer to flexspi_handle_t structure which stores the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @retval kStatus_InvalidArgument count is Invalid. - * @retval kStatus_Success Successfully return the count. - */ -status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count); - -/*! - * @brief Aborts an interrupt non-blocking transfer early. - * - * @note This API can be called at any time when an interrupt non-blocking transfer initiates - * to abort the transfer early. - * - * @param base FLEXSPI peripheral base address. - * @param handle pointer to flexspi_handle_t structure which stores the transfer state - */ -void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle); - -/*! - * @brief Master interrupt handler. - * - * @param base FLEXSPI peripheral base address. - * @param handle pointer to flexspi_handle_t structure. - */ -void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle); -/*! @} */ - -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ -/*@}*/ - -#endif /* __FSL_FLEXSPI_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpc.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpc.c deleted file mode 100644 index 90b7eb1542..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpc.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_gpc.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.gpc_1" -#endif - - -void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId) -{ - uint32_t irqRegNum = irqId / 32U; - uint32_t irqRegShiftNum = irqId % 32U; - - assert(irqRegNum > 0U); - assert(irqRegNum <= GPC_IMR_COUNT); - -#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31) - if (irqRegNum == GPC_IMR_COUNT) - { - base->IMR5 &= ~(1U << irqRegShiftNum); - } - else - { - base->IMR[irqRegNum] &= ~(1U << irqRegShiftNum); - } -#else - base->IMR[irqRegNum - 1U] &= ~(1U << irqRegShiftNum); -#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ -} - -void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId) -{ - uint32_t irqRegNum = irqId / 32U; - uint32_t irqRegShiftNum = irqId % 32U; - - assert(irqRegNum > 0U); - assert(irqRegNum <= GPC_IMR_COUNT); - -#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31) - if (irqRegNum == GPC_IMR_COUNT) - { - base->IMR5 |= (1U << irqRegShiftNum); - } - else - { - base->IMR[irqRegNum] |= (1U << irqRegShiftNum); - } -#else - base->IMR[irqRegNum - 1U] |= (1U << irqRegShiftNum); -#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ -} - -bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId) -{ - uint32_t irqRegNum = irqId / 32U; - uint32_t irqRegShiftNum = irqId % 32U; - uint32_t ret; - - assert(irqRegNum > 0U); - assert(irqRegNum <= GPC_IMR_COUNT); - -#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31) - if (irqRegNum == GPC_IMR_COUNT) - { - ret = base->ISR5 & (1U << irqRegShiftNum); - } - else - { - ret = base->ISR[irqRegNum] & (1U << irqRegShiftNum); - } -#else - ret = base->ISR[irqRegNum - 1U] & (1U << irqRegShiftNum); -#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ - - return (1U << irqRegShiftNum) == ret; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpc.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpc.h deleted file mode 100644 index 5ba31ecf65..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpc.h +++ /dev/null @@ -1,257 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_GPC_H_ -#define _FSL_GPC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gpc - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief GPC driver version 2.1.0. */ -#define FSL_GPC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if (defined(FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM) && FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM) -/*! - * @brief Allow all the IRQ/Events within the charge of GPC. - * - * @param base GPC peripheral base address. - */ -static inline void GPC_AllowIRQs(GPC_Type *base) -{ - base->CNTR &= ~GPC_CNTR_GPCIRQM_MASK; /* Events would not be masked. */ -} - -/*! - * @brief Disallow all the IRQ/Events within the charge of GPC. - * - * @param base GPC peripheral base address. - */ -static inline void GPC_DisallowIRQs(GPC_Type *base) -{ - base->CNTR |= GPC_CNTR_GPCIRQM_MASK; /* Mask all the events. */ -} -#endif /* FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM */ - -/*! - * @brief Enable the IRQ. - * - * @param base GPC peripheral base address. - * @param irqId ID number of IRQ to be enabled, available range is 32-159. - */ -void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId); - -/*! - * @brief Disable the IRQ. - * - * @param base GPC peripheral base address. - * @param irqId ID number of IRQ to be disabled, available range is 32-159. - */ -void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId); - -/*! - * @brief Get the IRQ/Event flag. - * - * @param base GPC peripheral base address. - * @param irqId ID number of IRQ to be enabled, available range is 32-159. - * @return Indicated IRQ/Event is asserted or not. - */ -bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId); - -#if (defined(FSL_FEATURE_GPC_HAS_CNTR_L2PGE) && FSL_FEATURE_GPC_HAS_CNTR_L2PGE) -/*! - * @brief L2 Cache Power Gate Enable - * - * This function configures the L2 cache if it will keep power when in low power mode. - * When the L2 cache power is OFF, L2 cache will be power down once when CPU core is power down - * and will be hardware invalidated automatically when CPU core is re-power up. - * When the L2 cache power is ON, L2 cache will keep power on even if CPU core is power down and - * will not be hardware invalidated. - * When CPU core is re-power up, the default setting is OFF. - * - * @param base GPC peripheral base address. - * @param enable Enable the request or not. - */ -static inline void GPC_RequestL2CachePowerDown(GPC_Type *base, bool enable) -{ - if (enable) - { - base->CNTR |= GPC_CNTR_L2_PGE_MASK; /* OFF. */ - } - else - { - base->CNTR &= ~GPC_CNTR_L2_PGE_MASK; /* ON. */ - } -} -#endif /* FSL_FEATURE_GPC_HAS_CNTR_L2PGE */ - -#if (defined(FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE) && FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE) -/*! - * @brief FLEXRAM PDRAM0 Power Gate Enable - * - * This function configures the FLEXRAM PDRAM0 if it will keep power when cpu core is power down. - * When the PDRAM0 Power is 1, PDRAM0 will be power down once when CPU core is power down. - * When the PDRAM0 Power is 0, PDRAM0 will keep power on even if CPU core is power down. - * When CPU core is re-power up, the default setting is 1. - * - * @param base GPC peripheral base address. - * @param enable Enable the request or not. - */ -static inline void GPC_RequestPdram0PowerDown(GPC_Type *base, bool enable) -{ - if (enable) - { - base->CNTR |= GPC_CNTR_PDRAM0_PGE_MASK; /* OFF. */ - } - else - { - base->CNTR &= ~GPC_CNTR_PDRAM0_PGE_MASK; /* ON. */ - } -} -#endif /* FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE */ - -#if (defined(FSL_FEATURE_GPC_HAS_CNTR_VADC) && FSL_FEATURE_GPC_HAS_CNTR_VADC) -/*! - * @brief VADC power down. - * - * This function requests the VADC power down. - * - * @param base GPC peripheral base address. - * @param enable Enable the request or not. - */ -static inline void GPC_RequestVADCPowerDown(GPC_Type *base, bool enable) -{ - if (enable) - { - base->CNTR &= ~GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC power down. */ - } - else - { - base->CNTR |= GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC not power down. */ - } -} - -/*! - * @brief Checks if the VADC is power off. - * - * @param base GPC peripheral base address. - * @return Whether the VADC is power off or not. - */ -static inline bool GPC_GetVADCPowerDownFlag(GPC_Type *base) -{ - return (GPC_CNTR_VADC_ANALOG_OFF_MASK == (GPC_CNTR_VADC_ANALOG_OFF_MASK & base->CNTR)); -} -#endif /* FSL_FEATURE_GPC_HAS_CNTR_VADC */ - -#if (defined(FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR) && FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR) -/*! - * @brief Checks if the DVFS0 is requesting for frequency/voltage update. - * - * @param base GPC peripheral base address. - * @return Whether the DVFS0 is requesting for frequency/voltage update. - */ -static inline bool GPC_HasDVFS0ChangeRequest(GPC_Type *base) -{ - return (GPC_CNTR_DVFS0CR_MASK == (GPC_CNTR_DVFS0CR_MASK & base->CNTR)); -} -#endif /* FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR */ - -#if (defined(FSL_FEATURE_GPC_HAS_CNTR_DISPLAY) && FSL_FEATURE_GPC_HAS_CNTR_DISPLAY) -/*! - * @brief Requests the display power switch sequence. - * - * @param base GPC peripheral base address. - * @param enable Enable the power on sequence, or the power down sequence. - */ -static inline void GPC_RequestDisplayPowerOn(GPC_Type *base, bool enable) -{ - if (enable) - { - base->CNTR |= GPC_CNTR_DISPLAY_PUP_REQ_MASK; /* Power on sequence. */ - } - else - { - base->CNTR |= GPC_CNTR_DISPLAY_PDN_REQ_MASK; /* Power down sequence. */ - } -} -#endif /* FSL_FEATURE_GPC_HAS_CNTR_DISPLAY */ - -/*! - * @brief Requests the MEGA power switch sequence. - * - * @param base GPC peripheral base address. - * @param enable Enable the power on sequence, or the power down sequence. - */ -static inline void GPC_RequestMEGAPowerOn(GPC_Type *base, bool enable) -{ - if (enable) - { - base->CNTR |= GPC_CNTR_MEGA_PUP_REQ_MASK; /* Power on sequence. */ - } - else - { - base->CNTR |= GPC_CNTR_MEGA_PDN_REQ_MASK; /* Power down sequence. */ - } -} - -/*! - * @} - */ - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_GPC_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpio.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpio.c deleted file mode 100644 index f4714aa53e..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpio.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_gpio.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.igpio" -#endif - - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Array of GPIO peripheral base address. */ -static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of GPIO clock name. */ -static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* -* Prototypes -******************************************************************************/ - -/*! -* @brief Gets the GPIO instance according to the GPIO base -* -* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) -* @retval GPIO instance -*/ -static uint32_t GPIO_GetInstance(GPIO_Type *base); - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t GPIO_GetInstance(GPIO_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++) - { - if (s_gpioBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_gpioBases)); - - return instance; -} - -void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable GPIO clock. */ - CLOCK_EnableClock(s_gpioClock[GPIO_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Register reset to default value */ - base->IMR &= ~(1U << pin); - - /* Configure GPIO pin direction */ - if (Config->direction == kGPIO_DigitalInput) - { - base->GDIR &= ~(1U << pin); - } - else - { - GPIO_PinWrite(base, pin, Config->outputLogic); - base->GDIR |= (1U << pin); - } - - /* Configure GPIO pin interrupt mode */ - GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode); -} - -void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) -{ - assert(pin < 32); - if (output == 0U) - { - base->DR &= ~(1U << pin); /* Set pin output to low level.*/ - } - else - { - base->DR |= (1U << pin); /* Set pin output to high level.*/ - } -} - -void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) -{ - volatile uint32_t *icr; - uint32_t icrShift; - - icrShift = pin; - - /* Register reset to default value */ - base->EDGE_SEL &= ~(1U << pin); - - if (pin < 16) - { - icr = &(base->ICR1); - } - else - { - icr = &(base->ICR2); - icrShift -= 16; - } - switch (pinInterruptMode) - { - case (kGPIO_IntLowLevel): - *icr &= ~(3U << (2 * icrShift)); - break; - case (kGPIO_IntHighLevel): - *icr = (*icr & (~(3U << (2 * icrShift)))) | (1U << (2 * icrShift)); - break; - case (kGPIO_IntRisingEdge): - *icr = (*icr & (~(3U << (2 * icrShift)))) | (2U << (2 * icrShift)); - break; - case (kGPIO_IntFallingEdge): - *icr |= (3U << (2 * icrShift)); - break; - case (kGPIO_IntRisingOrFallingEdge): - base->EDGE_SEL |= (1U << pin); - break; - default: - break; - } -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpio.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpio.h deleted file mode 100644 index 834a9c981a..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpio.h +++ /dev/null @@ -1,368 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_GPIO_H_ -#define _FSL_GPIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gpio_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief GPIO driver version 2.0.1. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! @brief GPIO direction definition. */ -typedef enum _gpio_pin_direction -{ - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/ - kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/ -} gpio_pin_direction_t; - -/*! @brief GPIO interrupt mode definition. */ -typedef enum _gpio_interrupt_mode -{ - kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/ - kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/ - kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/ - kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/ - kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/ - kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/ -} gpio_interrupt_mode_t; - -/*! @brief GPIO Init structure definition. */ -typedef struct _gpio_pin_config -{ - gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ - uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ - gpio_interrupt_mode_t - interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ -} gpio_pin_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name GPIO Initialization and Configuration functions - * @{ - */ - -/*! - * @brief Initializes the GPIO peripheral according to the specified - * parameters in the initConfig. - * - * @param base GPIO base pointer. - * @param pin Specifies the pin number - * @param initConfig pointer to a @ref gpio_pin_config_t structure that - * contains the configuration information. - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config); -/*@}*/ - -/*! - * @name GPIO Reads and Write Functions - * @{ - */ - -/*! - * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. - * - * @param base GPIO base pointer. - * @param pin GPIO port pin number. - * @param output GPIOpin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output); - -/*! - * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. - */ -static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) -{ - GPIO_PinWrite(base, pin, output); -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * - * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask) -{ -#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && (FSL_FEATURE_IGPIO_HAS_DR_SET == 1)) - base->DR_SET = mask; -#else - base->DR |= mask; -#endif /* FSL_FEATURE_IGPIO_HAS_DR_SET */ -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet. - */ -static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) -{ - GPIO_PortSet(base, mask); -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * - * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask) -{ -#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && (FSL_FEATURE_IGPIO_HAS_DR_CLEAR == 1)) - base->DR_CLEAR = mask; -#else - base->DR &= ~mask; -#endif /* FSL_FEATURE_IGPIO_HAS_DR_CLEAR */ -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear. - */ -static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) -{ - GPIO_PortClear(base, mask); -} - -/*! - * @brief Reverses the current output logic of the multiple GPIO pins. - * - * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) -{ -#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1)) - base->DR_TOGGLE = mask; -#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */ -} - -/*! - * @brief Reads the current input value of the GPIO port. - * - * @param base GPIO base pointer. - * @param pin GPIO port pin number. - * @retval GPIO port input value. - */ -static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) -{ - assert(pin < 32); - - return (((base->DR) >> pin) & 0x1U); -} - -/*! - * @brief Reads the current input value of the GPIO port. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead. - */ -static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) -{ - return GPIO_PinRead(base, pin); -} -/*@}*/ - -/*! - * @name GPIO Reads Pad Status Functions - * @{ - */ - -/*! -* @brief Reads the current GPIO pin pad status. -* -* @param base GPIO base pointer. -* @param pin GPIO port pin number. -* @retval GPIO pin pad status value. -*/ -static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin) -{ - assert(pin < 32); - - return (uint8_t)(((base->PSR) >> pin) & 0x1U); -} - -/*! -* @brief Reads the current GPIO pin pad status. -* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinReadPadStatus. -*/ -static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin) -{ - return GPIO_PinReadPadStatus(base, pin); -} - -/*@}*/ - -/*! - * @name Interrupts and flags management functions - * @{ - */ - -/*! - * @brief Sets the current pin interrupt mode. - * - * @param base GPIO base pointer. - * @param pin GPIO port pin number. - * @param pininterruptMode pointer to a @ref gpio_interrupt_mode_t structure - * that contains the interrupt mode information. - */ -void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode); - -/*! - * @brief Sets the current pin interrupt mode. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinSetInterruptConfig. - */ -static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) -{ - GPIO_PinSetInterruptConfig(base, pin, pinInterruptMode); -} - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param mask GPIO pin number macro. - */ -static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask) -{ - base->IMR |= mask; -} - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param mask GPIO pin number macro. - */ -static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask) -{ - GPIO_PortEnableInterrupts(base, mask); -} - -/*! - * @brief Disables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param mask GPIO pin number macro. - */ -static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask) -{ - base->IMR &= ~mask; -} - -/*! - * @brief Disables the specific pin interrupt. - * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortDisableInterrupts. - */ -static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask) -{ - GPIO_PortDisableInterrupts(base, mask); -} - -/*! - * @brief Reads individual pin interrupt status. - * - * @param base GPIO base pointer. - * @retval current pin interrupt status flag. - */ -static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base) -{ - return base->ISR; -} - -/*! - * @brief Reads individual pin interrupt status. - * - * @param base GPIO base pointer. - * @retval current pin interrupt status flag. - */ -static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) -{ - return GPIO_PortGetInterruptFlags(base); -} - -/*! - * @brief Clears pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param mask GPIO pin number macro. - */ -static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask) -{ - base->ISR = mask; -} - -/*! - * @brief Clears pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param mask GPIO pin number macro. - */ -static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) -{ - GPIO_PortClearInterruptFlags(base, mask); -} -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _FSL_GPIO_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpt.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpt.c deleted file mode 100644 index 39b0e89fb5..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpt.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_gpt.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.gpt" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to GPT bases for each instance. */ -static GPT_Type *const s_gptBases[] = GPT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to GPT clocks for each instance. */ -static const clock_ip_name_t s_gptClocks[] = GPT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t GPT_GetInstance(GPT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0U; instance < ARRAY_SIZE(s_gptBases); instance++) - { - if (s_gptBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_gptBases)); - - return instance; -} - -void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig) -{ - assert(initConfig); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the GPT clock*/ - CLOCK_EnableClock(s_gptClocks[GPT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - base->CR = 0U; - - GPT_SoftwareReset(base); - - base->CR = - (initConfig->enableFreeRun ? GPT_CR_FRR_MASK : 0U) | (initConfig->enableRunInWait ? GPT_CR_WAITEN_MASK : 0U) | - (initConfig->enableRunInStop ? GPT_CR_STOPEN_MASK : 0U) | - (initConfig->enableRunInDoze ? GPT_CR_DOZEEN_MASK : 0U) | - (initConfig->enableRunInDbg ? GPT_CR_DBGEN_MASK : 0U) | (initConfig->enableMode ? GPT_CR_ENMOD_MASK : 0U); - - GPT_SetClockSource(base, initConfig->clockSource); - GPT_SetClockDivider(base, initConfig->divider); -} - -void GPT_Deinit(GPT_Type *base) -{ - /* Disable GPT timers */ - base->CR = 0U; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the GPT clock*/ - CLOCK_DisableClock(s_gptClocks[GPT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void GPT_GetDefaultConfig(gpt_config_t *config) -{ - assert(config); - - config->clockSource = kGPT_ClockSource_Periph; - config->divider = 1U; - config->enableRunInStop = true; - config->enableRunInWait = true; - config->enableRunInDoze = false; - config->enableRunInDbg = false; - config->enableFreeRun = false; - config->enableMode = true; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpt.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpt.h deleted file mode 100644 index 1cea054557..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_gpt.h +++ /dev/null @@ -1,533 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_GPT_H_ -#define _FSL_GPT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup gpt - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ - /*@}*/ - -/*! - * @brief List of clock sources - * @note Actual number of clock sources is SoC dependent - */ -typedef enum _gpt_clock_source -{ - kGPT_ClockSource_Off = 0U, /*!< GPT Clock Source Off.*/ - kGPT_ClockSource_Periph = 1U, /*!< GPT Clock Source from Peripheral Clock.*/ - kGPT_ClockSource_HighFreq = 2U, /*!< GPT Clock Source from High Frequency Reference Clock.*/ - kGPT_ClockSource_Ext = 3U, /*!< GPT Clock Source from external pin.*/ - kGPT_ClockSource_LowFreq = 4U, /*!< GPT Clock Source from Low Frequency Reference Clock.*/ - kGPT_ClockSource_Osc = 5U, /*!< GPT Clock Source from Crystal oscillator.*/ -} gpt_clock_source_t; - -/*! @brief List of input capture channel number. */ -typedef enum _gpt_input_capture_channel -{ - kGPT_InputCapture_Channel1 = 0U, /*!< GPT Input Capture Channel1.*/ - kGPT_InputCapture_Channel2 = 1U, /*!< GPT Input Capture Channel2.*/ -} gpt_input_capture_channel_t; - -/*! @brief List of input capture operation mode. */ -typedef enum _gpt_input_operation_mode -{ - kGPT_InputOperation_Disabled = 0U, /*!< Don't capture.*/ - kGPT_InputOperation_RiseEdge = 1U, /*!< Capture on rising edge of input pin.*/ - kGPT_InputOperation_FallEdge = 2U, /*!< Capture on falling edge of input pin.*/ - kGPT_InputOperation_BothEdge = 3U, /*!< Capture on both edges of input pin.*/ -} gpt_input_operation_mode_t; - -/*! @brief List of output compare channel number. */ -typedef enum _gpt_output_compare_channel -{ - kGPT_OutputCompare_Channel1 = 0U, /*!< Output Compare Channel1.*/ - kGPT_OutputCompare_Channel2 = 1U, /*!< Output Compare Channel2.*/ - kGPT_OutputCompare_Channel3 = 2U, /*!< Output Compare Channel3.*/ -} gpt_output_compare_channel_t; - -/*! @brief List of output compare operation mode. */ -typedef enum _gpt_output_operation_mode -{ - kGPT_OutputOperation_Disconnected = 0U, /*!< Don't change output pin.*/ - kGPT_OutputOperation_Toggle = 1U, /*!< Toggle output pin.*/ - kGPT_OutputOperation_Clear = 2U, /*!< Set output pin low.*/ - kGPT_OutputOperation_Set = 3U, /*!< Set output pin high.*/ - kGPT_OutputOperation_Activelow = 4U, /*!< Generate a active low pulse on output pin.*/ -} gpt_output_operation_mode_t; - -/*! @brief List of GPT interrupts */ -typedef enum _gpt_interrupt_enable -{ - kGPT_OutputCompare1InterruptEnable = GPT_IR_OF1IE_MASK, /*!< Output Compare Channel1 interrupt enable*/ - kGPT_OutputCompare2InterruptEnable = GPT_IR_OF2IE_MASK, /*!< Output Compare Channel2 interrupt enable*/ - kGPT_OutputCompare3InterruptEnable = GPT_IR_OF3IE_MASK, /*!< Output Compare Channel3 interrupt enable*/ - kGPT_InputCapture1InterruptEnable = GPT_IR_IF1IE_MASK, /*!< Input Capture Channel1 interrupt enable*/ - kGPT_InputCapture2InterruptEnable = GPT_IR_IF2IE_MASK, /*!< Input Capture Channel1 interrupt enable*/ - kGPT_RollOverFlagInterruptEnable = GPT_IR_ROVIE_MASK, /*!< Counter rolled over interrupt enable*/ -} gpt_interrupt_enable_t; - -/*! @brief Status flag. */ -typedef enum _gpt_status_flag -{ - kGPT_OutputCompare1Flag = GPT_SR_OF1_MASK, /*!< Output compare channel 1 event.*/ - kGPT_OutputCompare2Flag = GPT_SR_OF2_MASK, /*!< Output compare channel 2 event.*/ - kGPT_OutputCompare3Flag = GPT_SR_OF3_MASK, /*!< Output compare channel 3 event.*/ - kGPT_InputCapture1Flag = GPT_SR_IF1_MASK, /*!< Input Capture channel 1 event.*/ - kGPT_InputCapture2Flag = GPT_SR_IF2_MASK, /*!< Input Capture channel 2 event.*/ - kGPT_RollOverFlag = GPT_SR_ROV_MASK, /*!< Counter reaches maximum value and rolled over to 0 event.*/ -} gpt_status_flag_t; - -/*! @brief Structure to configure the running mode. */ -typedef struct _gpt_init_config -{ - gpt_clock_source_t clockSource; /*!< clock source for GPT module. */ - uint32_t divider; /*!< clock divider (prescaler+1) from clock source to counter. */ - bool enableFreeRun; /*!< true: FreeRun mode, false: Restart mode. */ - bool enableRunInWait; /*!< GPT enabled in wait mode. */ - bool enableRunInStop; /*!< GPT enabled in stop mode. */ - bool enableRunInDoze; /*!< GPT enabled in doze mode. */ - bool enableRunInDbg; /*!< GPT enabled in debug mode. */ - bool enableMode; /*!< true: counter reset to 0 when enabled; - false: counter retain its value when enabled. */ -} gpt_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initialize GPT to reset state and initialize running mode. - * - * @param base GPT peripheral base address. - * @param initConfig GPT mode setting configuration. - */ -void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig); - -/*! - * @brief Disables the module and gates the GPT clock. - * - * @param base GPT peripheral base address. - */ -void GPT_Deinit(GPT_Type *base); - -/*! - * @brief Fills in the GPT configuration structure with default settings. - * - * The default values are: - * @code - * config->clockSource = kGPT_ClockSource_Periph; - * config->divider = 1U; - * config->enableRunInStop = true; - * config->enableRunInWait = true; - * config->enableRunInDoze = false; - * config->enableRunInDbg = false; - * config->enableFreeRun = true; - * config->enableMode = true; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void GPT_GetDefaultConfig(gpt_config_t *config); - -/*! - * @name Software Reset - * @{ - */ - -/*! - * @brief Software reset of GPT module. - * - * @param base GPT peripheral base address. - */ -static inline void GPT_SoftwareReset(GPT_Type *base) -{ - base->CR |= GPT_CR_SWR_MASK; - /* Wait reset finished. */ - while ((base->CR & GPT_CR_SWR_MASK) == GPT_CR_SWR_MASK) - { - } -} - -/*! - * @name Clock source and frequency control - * @{ - */ - -/*! - * @brief Set clock source of GPT. - * - * @param base GPT peripheral base address. - * @param source Clock source (see @ref gpt_clock_source_t typedef enumeration). - */ -static inline void GPT_SetClockSource(GPT_Type *base, gpt_clock_source_t source) -{ - if (source == kGPT_ClockSource_Osc) - { - base->CR = (base->CR & ~GPT_CR_CLKSRC_MASK) | GPT_CR_EN_24M_MASK | GPT_CR_CLKSRC(source); - } - else - { - base->CR = (base->CR & ~(GPT_CR_CLKSRC_MASK | GPT_CR_EN_24M_MASK)) | GPT_CR_CLKSRC(source); - } -} - -/*! - * @brief Get clock source of GPT. - * - * @param base GPT peripheral base address. - * @return clock source (see @ref gpt_clock_source_t typedef enumeration). - */ -static inline gpt_clock_source_t GPT_GetClockSource(GPT_Type *base) -{ - return (gpt_clock_source_t)((base->CR & GPT_CR_CLKSRC_MASK) >> GPT_CR_CLKSRC_SHIFT); -} - -/*! - * @brief Set pre scaler of GPT. - * - * @param base GPT peripheral base address. - * @param divider Divider of GPT (1-4096). - */ -static inline void GPT_SetClockDivider(GPT_Type *base, uint32_t divider) -{ - assert(divider - 1 <= GPT_PR_PRESCALER_MASK); - - base->PR = (base->PR & ~GPT_PR_PRESCALER_MASK) | GPT_PR_PRESCALER(divider - 1); -} - -/*! - * @brief Get clock divider in GPT module. - * - * @param base GPT peripheral base address. - * @return clock divider in GPT module (1-4096). - */ -static inline uint32_t GPT_GetClockDivider(GPT_Type *base) -{ - return ((base->PR & GPT_PR_PRESCALER_MASK) >> GPT_PR_PRESCALER_SHIFT) + 1; -} - -/*! - * @brief OSC 24M pre-scaler before selected by clock source. - * - * @param base GPT peripheral base address. - * @param divider OSC Divider(1-16). - */ -static inline void GPT_SetOscClockDivider(GPT_Type *base, uint32_t divider) -{ - assert(divider - 1 <= (GPT_PR_PRESCALER24M_MASK >> GPT_PR_PRESCALER24M_SHIFT)); - - base->PR = (base->PR & ~GPT_PR_PRESCALER24M_MASK) | GPT_PR_PRESCALER24M(divider - 1); -} - -/*! - * @brief Get OSC 24M clock divider in GPT module. - * - * @param base GPT peripheral base address. - * @return OSC clock divider in GPT module (1-16). - */ -static inline uint32_t GPT_GetOscClockDivider(GPT_Type *base) -{ - return ((base->PR & GPT_PR_PRESCALER24M_MASK) >> GPT_PR_PRESCALER24M_SHIFT) + 1; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ -/*! - * @brief Start GPT timer. - * - * @param base GPT peripheral base address. - */ -static inline void GPT_StartTimer(GPT_Type *base) -{ - base->CR |= GPT_CR_EN_MASK; -} - -/*! - * @brief Stop GPT timer. - * - * @param base GPT peripheral base address. - */ -static inline void GPT_StopTimer(GPT_Type *base) -{ - base->CR &= ~GPT_CR_EN_MASK; -} - -/*! - * @name Read the timer period - * @{ - */ - -/*! - * @brief Reads the current GPT counting value. - * - * @param base GPT peripheral base address. - * @return Current GPT counter value. - */ -static inline uint32_t GPT_GetCurrentTimerCount(GPT_Type *base) -{ - return base->CNT; -} - -/*@}*/ - -/*! - * @name GPT Input/Output Signal Control - * @{ - */ - -/*! - * @brief Set GPT operation mode of input capture channel. - * - * @param base GPT peripheral base address. - * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration). - * @param mode GPT input capture operation mode (see @ref gpt_input_operation_mode_t typedef enumeration). - */ -static inline void GPT_SetInputOperationMode(GPT_Type *base, - gpt_input_capture_channel_t channel, - gpt_input_operation_mode_t mode) -{ - assert(channel <= kGPT_InputCapture_Channel2); - - base->CR = (base->CR & ~(GPT_CR_IM1_MASK << (channel * 2))) | (GPT_CR_IM1(mode) << (channel * 2)); -} - -/*! - * @brief Get GPT operation mode of input capture channel. - * - * @param base GPT peripheral base address. - * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration). - * @return GPT input capture operation mode (see @ref gpt_input_operation_mode_t typedef enumeration). - */ -static inline gpt_input_operation_mode_t GPT_GetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel) -{ - assert(channel <= kGPT_InputCapture_Channel2); - - return (gpt_input_operation_mode_t)((base->CR >> (GPT_CR_IM1_SHIFT + channel * 2)) & - (GPT_CR_IM1_MASK >> GPT_CR_IM1_SHIFT)); -} - -/*! - * @brief Get GPT input capture value of certain channel. - * - * @param base GPT peripheral base address. - * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration). - * @return GPT input capture value. - */ -static inline uint32_t GPT_GetInputCaptureValue(GPT_Type *base, gpt_input_capture_channel_t channel) -{ - assert(channel <= kGPT_InputCapture_Channel2); - - return *(&base->ICR[0] + channel); -} - -/*! - * @brief Set GPT operation mode of output compare channel. - * - * @param base GPT peripheral base address. - * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). - * @param mode GPT output operation mode (see @ref gpt_output_operation_mode_t typedef enumeration). - */ -static inline void GPT_SetOutputOperationMode(GPT_Type *base, - gpt_output_compare_channel_t channel, - gpt_output_operation_mode_t mode) -{ - assert(channel <= kGPT_OutputCompare_Channel3); - - base->CR = (base->CR & ~(GPT_CR_OM1_MASK << (channel * 3))) | (GPT_CR_OM1(mode) << (channel * 3)); -} - -/*! - * @brief Get GPT operation mode of output compare channel. - * - * @param base GPT peripheral base address. - * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). - * @return GPT output operation mode (see @ref gpt_output_operation_mode_t typedef enumeration). - */ -static inline gpt_output_operation_mode_t GPT_GetOutputOperationMode(GPT_Type *base, - gpt_output_compare_channel_t channel) -{ - assert(channel <= kGPT_OutputCompare_Channel3); - - return (gpt_output_operation_mode_t)((base->CR >> (GPT_CR_OM1_SHIFT + channel * 3)) & - (GPT_CR_OM1_MASK >> GPT_CR_OM1_SHIFT)); -} - -/*! - * @brief Set GPT output compare value of output compare channel. - * - * @param base GPT peripheral base address. - * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). - * @param value GPT output compare value. - */ -static inline void GPT_SetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel, uint32_t value) -{ - assert(channel <= kGPT_OutputCompare_Channel3); - - *(&base->OCR[0] + channel) = value; -} - -/*! - * @brief Get GPT output compare value of output compare channel. - * - * @param base GPT peripheral base address. - * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). - * @return GPT output compare value. - */ -static inline uint32_t GPT_GetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel) -{ - assert(channel <= kGPT_OutputCompare_Channel3); - - return *(&base->OCR[0] + channel); -} - -/*! - * @brief Force GPT output action on output compare channel, ignoring comparator. - * - * @param base GPT peripheral base address. - * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). - */ -static inline void GPT_ForceOutput(GPT_Type *base, gpt_output_compare_channel_t channel) -{ - assert(channel <= kGPT_OutputCompare_Channel3); - - base->CR |= (GPT_CR_FO1_MASK << channel); -} - -/*@}*/ - -/*! - * @name GPT Interrupt and Status Interface - * @{ - */ - -/*! - * @brief Enables the selected GPT interrupts. - * - * @param base GPT peripheral base address. - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::gpt_interrupt_enable_t - */ -static inline void GPT_EnableInterrupts(GPT_Type *base, uint32_t mask) -{ - base->IR |= mask; -} - -/*! - * @brief Disables the selected GPT interrupts. - * - * @param base GPT peripheral base address - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::gpt_interrupt_enable_t - */ -static inline void GPT_DisableInterrupts(GPT_Type *base, uint32_t mask) -{ - base->IR &= ~mask; -} - -/*! - * @brief Gets the enabled GPT interrupts. - * - * @param base GPT peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::gpt_interrupt_enable_t - */ -static inline uint32_t GPT_GetEnabledInterrupts(GPT_Type *base) -{ - return (base->IR & (GPT_IR_OF1IE_MASK | GPT_IR_OF2IE_MASK | GPT_IR_OF3IE_MASK | GPT_IR_IF1IE_MASK | - GPT_IR_IF2IE_MASK | GPT_IR_ROVIE_MASK)); -} - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Get GPT status flags. - * - * @param base GPT peripheral base address. - * @param flags GPT status flag mask (see @ref gpt_status_flag_t for bit definition). - * @return GPT status, each bit represents one status flag. - */ -static inline uint32_t GPT_GetStatusFlags(GPT_Type *base, gpt_status_flag_t flags) -{ - return base->SR & flags; -} - -/*! - * @brief Clears the GPT status flags. - * - * @param base GPT peripheral base address. - * @param flags GPT status flag mask (see @ref gpt_status_flag_t for bit definition). - */ -static inline void GPT_ClearStatusFlags(GPT_Type *base, gpt_status_flag_t flags) -{ - base->SR = flags; -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_GPT_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_iomuxc.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_iomuxc.h deleted file mode 100644 index 2a7dabb802..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_iomuxc.h +++ /dev/null @@ -1,1272 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_IOMUXC_H_ -#define _FSL_IOMUXC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup iomuxc_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.iomuxc" -#endif - -/*! @name Driver version */ -/*@{*/ -/*! @brief IOMUXC driver version 2.0.0. */ -#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @name Pin function ID */ -/*@{*/ -/*! @brief The pin function ID is a tuple of */ -#define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U -#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U - -#define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU -#define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU - -#define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ 0x400A8008U, 0x0U, 0, 0, 0x400A8020U -#define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 0x400A8008U, 0x5U, 0, 0, 0x400A8020U - -#define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU - -#define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U - -#define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U - -#define IOMUXC_GPIO_EMC_00_SEMC_DATA00 0x401F8014U, 0x0U, 0, 0, 0x401F8204U -#define IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00 0x401F8014U, 0x1U, 0x401F8494U, 0x0U, 0x401F8204U -#define IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x401F8014U, 0x2U, 0x401F8500U, 0x1U, 0x401F8204U -#define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U -#define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U -#define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U - -#define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U -#define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00 0x401F8018U, 0x1U, 0, 0, 0x401F8208U -#define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x401F8018U, 0x2U, 0x401F84FCU, 0x1U, 0x401F8208U -#define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U -#define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U -#define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U - -#define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU -#define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU -#define IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x401F801CU, 0x2U, 0x401F8508U, 0x1U, 0x401F820CU -#define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU -#define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU -#define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU - -#define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U -#define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01 0x401F8020U, 0x1U, 0, 0, 0x401F8210U -#define IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x401F8020U, 0x2U, 0x401F8504U, 0x1U, 0x401F8210U -#define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U -#define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U -#define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U - -#define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U -#define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U -#define IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x401F8024U, 0x2U, 0, 0, 0x401F8214U -#define IOMUXC_GPIO_EMC_04_XBAR1_INOUT06 0x401F8024U, 0x3U, 0x401F861CU, 0x0U, 0x401F8214U -#define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 0x401F8024U, 0x4U, 0, 0, 0x401F8214U -#define IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8214U - -#define IOMUXC_GPIO_EMC_05_SEMC_DATA05 0x401F8028U, 0x0U, 0, 0, 0x401F8218U -#define IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02 0x401F8028U, 0x1U, 0, 0, 0x401F8218U -#define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x2U, 0x401F85C4U, 0x0U, 0x401F8218U -#define IOMUXC_GPIO_EMC_05_XBAR1_INOUT07 0x401F8028U, 0x3U, 0x401F8620U, 0x0U, 0x401F8218U -#define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 0x401F8028U, 0x4U, 0, 0, 0x401F8218U -#define IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F8218U - -#define IOMUXC_GPIO_EMC_06_SEMC_DATA06 0x401F802CU, 0x0U, 0, 0, 0x401F821CU -#define IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA00 0x401F802CU, 0x1U, 0x401F8478U, 0x0U, 0x401F821CU -#define IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x401F802CU, 0x2U, 0x401F85C0U, 0x0U, 0x401F821CU -#define IOMUXC_GPIO_EMC_06_XBAR1_INOUT08 0x401F802CU, 0x3U, 0x401F8624U, 0x0U, 0x401F821CU -#define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 0x401F802CU, 0x4U, 0, 0, 0x401F821CU -#define IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F821CU - -#define IOMUXC_GPIO_EMC_07_SEMC_DATA07 0x401F8030U, 0x0U, 0, 0, 0x401F8220U -#define IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB00 0x401F8030U, 0x1U, 0x401F8488U, 0x0U, 0x401F8220U -#define IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x401F8030U, 0x2U, 0x401F85B0U, 0x0U, 0x401F8220U -#define IOMUXC_GPIO_EMC_07_XBAR1_INOUT09 0x401F8030U, 0x3U, 0x401F8628U, 0x0U, 0x401F8220U -#define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 0x401F8030U, 0x4U, 0, 0, 0x401F8220U -#define IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F8220U - -#define IOMUXC_GPIO_EMC_08_SEMC_DM00 0x401F8034U, 0x0U, 0, 0, 0x401F8224U -#define IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA01 0x401F8034U, 0x1U, 0x401F847CU, 0x0U, 0x401F8224U -#define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x2U, 0x401F85B8U, 0x0U, 0x401F8224U -#define IOMUXC_GPIO_EMC_08_XBAR1_INOUT17 0x401F8034U, 0x3U, 0x401F862CU, 0x0U, 0x401F8224U -#define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 0x401F8034U, 0x4U, 0, 0, 0x401F8224U -#define IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F8224U - -#define IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x401F8038U, 0x0U, 0, 0, 0x401F8228U -#define IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB01 0x401F8038U, 0x1U, 0x401F848CU, 0x0U, 0x401F8228U -#define IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x401F8038U, 0x2U, 0x401F85BCU, 0x0U, 0x401F8228U -#define IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x401F8038U, 0x3U, 0, 0, 0x401F8228U -#define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 0x401F8038U, 0x4U, 0, 0, 0x401F8228U -#define IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F8228U - -#define IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x401F803CU, 0x0U, 0, 0, 0x401F822CU -#define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA02 0x401F803CU, 0x1U, 0x401F8480U, 0x0U, 0x401F822CU -#define IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x401F803CU, 0x2U, 0x401F85B4U, 0x0U, 0x401F822CU -#define IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F822CU -#define IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 0x401F803CU, 0x4U, 0, 0, 0x401F822CU -#define IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x401F803CU, 0x5U, 0, 0, 0x401F822CU - -#define IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x401F8040U, 0x0U, 0, 0, 0x401F8230U -#define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02 0x401F8040U, 0x1U, 0x401F8490U, 0x0U, 0x401F8230U -#define IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x401F8040U, 0x2U, 0x401F84E8U, 0x0U, 0x401F8230U -#define IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x401F8040U, 0x3U, 0, 0, 0x401F8230U -#define IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 0x401F8040U, 0x4U, 0, 0, 0x401F8230U -#define IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x401F8040U, 0x5U, 0, 0, 0x401F8230U - -#define IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x401F8044U, 0x0U, 0, 0, 0x401F8234U -#define IOMUXC_GPIO_EMC_12_XBAR1_IN24 0x401F8044U, 0x1U, 0x401F8640U, 0x0U, 0x401F8234U -#define IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x401F8044U, 0x2U, 0x401F84E4U, 0x0U, 0x401F8234U -#define IOMUXC_GPIO_EMC_12_USDHC1_WP 0x401F8044U, 0x3U, 0x401F85D8U, 0x0U, 0x401F8234U -#define IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03 0x401F8044U, 0x4U, 0x401F8454U, 0x1U, 0x401F8234U -#define IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x401F8044U, 0x5U, 0, 0, 0x401F8234U - -#define IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x401F8048U, 0x0U, 0, 0, 0x401F8238U -#define IOMUXC_GPIO_EMC_13_XBAR1_IN25 0x401F8048U, 0x1U, 0x401F8650U, 0x1U, 0x401F8238U -#define IOMUXC_GPIO_EMC_13_LPUART3_TX 0x401F8048U, 0x2U, 0x401F853CU, 0x1U, 0x401F8238U -#define IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x401F8048U, 0x3U, 0, 0, 0x401F8238U -#define IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03 0x401F8048U, 0x4U, 0x401F8464U, 0x1U, 0x401F8238U -#define IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x401F8048U, 0x5U, 0, 0, 0x401F8238U - -#define IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x401F804CU, 0x0U, 0, 0, 0x401F823CU -#define IOMUXC_GPIO_EMC_14_XBAR1_INOUT19 0x401F804CU, 0x1U, 0x401F8654U, 0x0U, 0x401F823CU -#define IOMUXC_GPIO_EMC_14_LPUART3_RX 0x401F804CU, 0x2U, 0x401F8538U, 0x1U, 0x401F823CU -#define IOMUXC_GPIO_EMC_14_MQS_LEFT 0x401F804CU, 0x3U, 0, 0, 0x401F823CU -#define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x401F804CU, 0x4U, 0, 0, 0x401F823CU -#define IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x401F804CU, 0x5U, 0, 0, 0x401F823CU - -#define IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x401F8050U, 0x0U, 0, 0, 0x401F8240U -#define IOMUXC_GPIO_EMC_15_XBAR1_IN20 0x401F8050U, 0x1U, 0x401F8634U, 0x0U, 0x401F8240U -#define IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x401F8050U, 0x2U, 0x401F8534U, 0x0U, 0x401F8240U -#define IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x401F8050U, 0x3U, 0, 0, 0x401F8240U -#define IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 0x401F8050U, 0x4U, 0x401F857CU, 0x0U, 0x401F8240U -#define IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x401F8050U, 0x5U, 0, 0, 0x401F8240U - -#define IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x401F8054U, 0x0U, 0, 0, 0x401F8244U -#define IOMUXC_GPIO_EMC_16_XBAR1_IN21 0x401F8054U, 0x1U, 0x401F8658U, 0x0U, 0x401F8244U -#define IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x401F8054U, 0x2U, 0, 0, 0x401F8244U -#define IOMUXC_GPIO_EMC_16_SPDIF_IN 0x401F8054U, 0x3U, 0x401F85C8U, 0x1U, 0x401F8244U -#define IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 0x401F8054U, 0x4U, 0x401F8580U, 0x1U, 0x401F8244U -#define IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F8244U - -#define IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x401F8058U, 0x0U, 0, 0, 0x401F8248U -#define IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03 0x401F8058U, 0x1U, 0x401F84A0U, 0x0U, 0x401F8248U -#define IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x401F8058U, 0x2U, 0, 0, 0x401F8248U -#define IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x401F8058U, 0x3U, 0, 0, 0x401F8248U -#define IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 0x401F8058U, 0x4U, 0x401F8584U, 0x0U, 0x401F8248U -#define IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F8248U - -#define IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x401F805CU, 0x0U, 0, 0, 0x401F824CU -#define IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03 0x401F805CU, 0x1U, 0, 0, 0x401F824CU -#define IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x401F805CU, 0x2U, 0, 0, 0x401F824CU -#define IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x401F805CU, 0x3U, 0x401F844CU, 0x1U, 0x401F824CU -#define IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 0x401F805CU, 0x4U, 0x401F8588U, 0x0U, 0x401F824CU -#define IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F824CU -#define IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x401F805CU, 0x6U, 0, 0, 0x401F824CU - -#define IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x401F8060U, 0x0U, 0, 0, 0x401F8250U -#define IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03 0x401F8060U, 0x1U, 0x401F8474U, 0x1U, 0x401F8250U -#define IOMUXC_GPIO_EMC_19_LPUART4_TX 0x401F8060U, 0x2U, 0x401F8544U, 0x1U, 0x401F8250U -#define IOMUXC_GPIO_EMC_19_ENET_RDATA01 0x401F8060U, 0x3U, 0x401F8438U, 0x0U, 0x401F8250U -#define IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 0x401F8060U, 0x4U, 0x401F856CU, 0x0U, 0x401F8250U -#define IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F8250U -#define IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x401F8060U, 0x6U, 0, 0, 0x401F8250U - -#define IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x401F8064U, 0x0U, 0, 0, 0x401F8254U -#define IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03 0x401F8064U, 0x1U, 0x401F8484U, 0x1U, 0x401F8254U -#define IOMUXC_GPIO_EMC_20_LPUART4_RX 0x401F8064U, 0x2U, 0x401F8540U, 0x1U, 0x401F8254U -#define IOMUXC_GPIO_EMC_20_ENET_RDATA00 0x401F8064U, 0x3U, 0x401F8434U, 0x0U, 0x401F8254U -#define IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 0x401F8064U, 0x4U, 0x401F8570U, 0x0U, 0x401F8254U -#define IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F8254U - -#define IOMUXC_GPIO_EMC_21_SEMC_BA0 0x401F8068U, 0x0U, 0, 0, 0x401F8258U -#define IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA03 0x401F8068U, 0x1U, 0, 0, 0x401F8258U -#define IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x401F8068U, 0x2U, 0x401F84E0U, 0x0U, 0x401F8258U -#define IOMUXC_GPIO_EMC_21_ENET_TDATA01 0x401F8068U, 0x3U, 0, 0, 0x401F8258U -#define IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 0x401F8068U, 0x4U, 0x401F8574U, 0x0U, 0x401F8258U -#define IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F8258U - -#define IOMUXC_GPIO_EMC_22_SEMC_BA1 0x401F806CU, 0x0U, 0, 0, 0x401F825CU -#define IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03 0x401F806CU, 0x1U, 0, 0, 0x401F825CU -#define IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x401F806CU, 0x2U, 0x401F84DCU, 0x0U, 0x401F825CU -#define IOMUXC_GPIO_EMC_22_ENET_TDATA00 0x401F806CU, 0x3U, 0, 0, 0x401F825CU -#define IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 0x401F806CU, 0x4U, 0x401F8578U, 0x0U, 0x401F825CU -#define IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F825CU - -#define IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x401F8070U, 0x0U, 0, 0, 0x401F8260U -#define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00 0x401F8070U, 0x1U, 0x401F8458U, 0x0U, 0x401F8260U -#define IOMUXC_GPIO_EMC_23_LPUART5_TX 0x401F8070U, 0x2U, 0x401F854CU, 0x0U, 0x401F8260U -#define IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x401F8070U, 0x3U, 0x401F843CU, 0x0U, 0x401F8260U -#define IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x401F8070U, 0x4U, 0, 0, 0x401F8260U -#define IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F8260U - -#define IOMUXC_GPIO_EMC_24_SEMC_CAS 0x401F8074U, 0x0U, 0, 0, 0x401F8264U -#define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB00 0x401F8074U, 0x1U, 0x401F8468U, 0x0U, 0x401F8264U -#define IOMUXC_GPIO_EMC_24_LPUART5_RX 0x401F8074U, 0x2U, 0x401F8548U, 0x0U, 0x401F8264U -#define IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x401F8074U, 0x3U, 0, 0, 0x401F8264U -#define IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x401F8074U, 0x4U, 0, 0, 0x401F8264U -#define IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F8264U - -#define IOMUXC_GPIO_EMC_25_SEMC_RAS 0x401F8078U, 0x0U, 0, 0, 0x401F8268U -#define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA01 0x401F8078U, 0x1U, 0x401F845CU, 0x0U, 0x401F8268U -#define IOMUXC_GPIO_EMC_25_LPUART6_TX 0x401F8078U, 0x2U, 0x401F8554U, 0x0U, 0x401F8268U -#define IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x401F8078U, 0x3U, 0x401F8448U, 0x0U, 0x401F8268U -#define IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x401F8078U, 0x4U, 0x401F842CU, 0x0U, 0x401F8268U -#define IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F8268U - -#define IOMUXC_GPIO_EMC_26_SEMC_CLK 0x401F807CU, 0x0U, 0, 0, 0x401F826CU -#define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB01 0x401F807CU, 0x1U, 0x401F846CU, 0x0U, 0x401F826CU -#define IOMUXC_GPIO_EMC_26_LPUART6_RX 0x401F807CU, 0x2U, 0x401F8550U, 0x0U, 0x401F826CU -#define IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x401F807CU, 0x3U, 0x401F8440U, 0x0U, 0x401F826CU -#define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 0x401F807CU, 0x4U, 0, 0, 0x401F826CU -#define IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F826CU - -#define IOMUXC_GPIO_EMC_27_SEMC_CKE 0x401F8080U, 0x0U, 0, 0, 0x401F8270U -#define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA02 0x401F8080U, 0x1U, 0x401F8460U, 0x0U, 0x401F8270U -#define IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x401F8080U, 0x2U, 0, 0, 0x401F8270U -#define IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x401F8080U, 0x3U, 0x401F84F0U, 0x0U, 0x401F8270U -#define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 0x401F8080U, 0x4U, 0, 0, 0x401F8270U -#define IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F8270U - -#define IOMUXC_GPIO_EMC_28_SEMC_WE 0x401F8084U, 0x0U, 0, 0, 0x401F8274U -#define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB02 0x401F8084U, 0x1U, 0x401F8470U, 0x0U, 0x401F8274U -#define IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x401F8084U, 0x2U, 0, 0, 0x401F8274U -#define IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x401F8084U, 0x3U, 0x401F84F8U, 0x0U, 0x401F8274U -#define IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 0x401F8084U, 0x4U, 0, 0, 0x401F8274U -#define IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x401F8084U, 0x5U, 0, 0, 0x401F8274U - -#define IOMUXC_GPIO_EMC_29_SEMC_CS0 0x401F8088U, 0x0U, 0, 0, 0x401F8278U -#define IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00 0x401F8088U, 0x1U, 0, 0, 0x401F8278U -#define IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x401F8088U, 0x2U, 0, 0, 0x401F8278U -#define IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x401F8088U, 0x3U, 0x401F84F4U, 0x0U, 0x401F8278U -#define IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 0x401F8088U, 0x4U, 0, 0, 0x401F8278U -#define IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x401F8088U, 0x5U, 0, 0, 0x401F8278U - -#define IOMUXC_GPIO_EMC_30_SEMC_DATA08 0x401F808CU, 0x0U, 0, 0, 0x401F827CU -#define IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB00 0x401F808CU, 0x1U, 0, 0, 0x401F827CU -#define IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x401F808CU, 0x2U, 0, 0, 0x401F827CU -#define IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x401F808CU, 0x3U, 0x401F84ECU, 0x1U, 0x401F827CU -#define IOMUXC_GPIO_EMC_30_CSI_DATA23 0x401F808CU, 0x4U, 0, 0, 0x401F827CU -#define IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x401F808CU, 0x5U, 0, 0, 0x401F827CU - -#define IOMUXC_GPIO_EMC_31_SEMC_DATA09 0x401F8090U, 0x0U, 0, 0, 0x401F8280U -#define IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA01 0x401F8090U, 0x1U, 0, 0, 0x401F8280U -#define IOMUXC_GPIO_EMC_31_LPUART7_TX 0x401F8090U, 0x2U, 0x401F855CU, 0x1U, 0x401F8280U -#define IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x401F8090U, 0x3U, 0, 0, 0x401F8280U -#define IOMUXC_GPIO_EMC_31_CSI_DATA22 0x401F8090U, 0x4U, 0, 0, 0x401F8280U -#define IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x401F8090U, 0x5U, 0, 0, 0x401F8280U - -#define IOMUXC_GPIO_EMC_32_SEMC_DATA10 0x401F8094U, 0x0U, 0, 0, 0x401F8284U -#define IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB01 0x401F8094U, 0x1U, 0, 0, 0x401F8284U -#define IOMUXC_GPIO_EMC_32_LPUART7_RX 0x401F8094U, 0x2U, 0x401F8558U, 0x1U, 0x401F8284U -#define IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY 0x401F8094U, 0x3U, 0x401F83FCU, 0x4U, 0x401F8284U -#define IOMUXC_GPIO_EMC_32_CSI_DATA21 0x401F8094U, 0x4U, 0, 0, 0x401F8284U -#define IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x401F8094U, 0x5U, 0, 0, 0x401F8284U - -#define IOMUXC_GPIO_EMC_33_SEMC_DATA11 0x401F8098U, 0x0U, 0, 0, 0x401F8288U -#define IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA02 0x401F8098U, 0x1U, 0, 0, 0x401F8288U -#define IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x401F8098U, 0x2U, 0, 0, 0x401F8288U -#define IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x401F8098U, 0x3U, 0, 0, 0x401F8288U -#define IOMUXC_GPIO_EMC_33_CSI_DATA20 0x401F8098U, 0x4U, 0, 0, 0x401F8288U -#define IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x401F8098U, 0x5U, 0, 0, 0x401F8288U - -#define IOMUXC_GPIO_EMC_34_SEMC_DATA12 0x401F809CU, 0x0U, 0, 0, 0x401F828CU -#define IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB02 0x401F809CU, 0x1U, 0, 0, 0x401F828CU -#define IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x401F809CU, 0x2U, 0, 0, 0x401F828CU -#define IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x401F809CU, 0x3U, 0, 0, 0x401F828CU -#define IOMUXC_GPIO_EMC_34_CSI_DATA19 0x401F809CU, 0x4U, 0, 0, 0x401F828CU -#define IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x401F809CU, 0x5U, 0, 0, 0x401F828CU - -#define IOMUXC_GPIO_EMC_35_SEMC_DATA13 0x401F80A0U, 0x0U, 0, 0, 0x401F8290U -#define IOMUXC_GPIO_EMC_35_XBAR1_INOUT18 0x401F80A0U, 0x1U, 0x401F8630U, 0x0U, 0x401F8290U -#define IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x401F80A0U, 0x2U, 0, 0, 0x401F8290U -#define IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x401F80A0U, 0x3U, 0, 0, 0x401F8290U -#define IOMUXC_GPIO_EMC_35_CSI_DATA18 0x401F80A0U, 0x4U, 0, 0, 0x401F8290U -#define IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x401F80A0U, 0x5U, 0, 0, 0x401F8290U -#define IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x401F80A0U, 0x6U, 0x401F85D4U, 0x0U, 0x401F8290U - -#define IOMUXC_GPIO_EMC_36_SEMC_DATA14 0x401F80A4U, 0x0U, 0, 0, 0x401F8294U -#define IOMUXC_GPIO_EMC_36_XBAR1_IN22 0x401F80A4U, 0x1U, 0x401F8638U, 0x0U, 0x401F8294U -#define IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x401F80A4U, 0x2U, 0, 0, 0x401F8294U -#define IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x401F80A4U, 0x3U, 0, 0, 0x401F8294U -#define IOMUXC_GPIO_EMC_36_CSI_DATA17 0x401F80A4U, 0x4U, 0, 0, 0x401F8294U -#define IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x401F80A4U, 0x5U, 0, 0, 0x401F8294U -#define IOMUXC_GPIO_EMC_36_USDHC1_WP 0x401F80A4U, 0x6U, 0x401F85D8U, 0x1U, 0x401F8294U - -#define IOMUXC_GPIO_EMC_37_SEMC_DATA15 0x401F80A8U, 0x0U, 0, 0, 0x401F8298U -#define IOMUXC_GPIO_EMC_37_XBAR1_IN23 0x401F80A8U, 0x1U, 0x401F863CU, 0x0U, 0x401F8298U -#define IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x401F80A8U, 0x2U, 0, 0, 0x401F8298U -#define IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x401F80A8U, 0x3U, 0, 0, 0x401F8298U -#define IOMUXC_GPIO_EMC_37_CSI_DATA16 0x401F80A8U, 0x4U, 0, 0, 0x401F8298U -#define IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x401F80A8U, 0x5U, 0, 0, 0x401F8298U -#define IOMUXC_GPIO_EMC_37_USDHC2_WP 0x401F80A8U, 0x6U, 0x401F8608U, 0x0U, 0x401F8298U - -#define IOMUXC_GPIO_EMC_38_SEMC_DM01 0x401F80ACU, 0x0U, 0, 0, 0x401F829CU -#define IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03 0x401F80ACU, 0x1U, 0x401F8454U, 0x2U, 0x401F829CU -#define IOMUXC_GPIO_EMC_38_LPUART8_TX 0x401F80ACU, 0x2U, 0x401F8564U, 0x2U, 0x401F829CU -#define IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x401F80ACU, 0x3U, 0, 0, 0x401F829CU -#define IOMUXC_GPIO_EMC_38_CSI_FIELD 0x401F80ACU, 0x4U, 0, 0, 0x401F829CU -#define IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x401F80ACU, 0x5U, 0, 0, 0x401F829CU -#define IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x401F80ACU, 0x6U, 0, 0, 0x401F829CU - -#define IOMUXC_GPIO_EMC_39_SEMC_DQS 0x401F80B0U, 0x0U, 0, 0, 0x401F82A0U -#define IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03 0x401F80B0U, 0x1U, 0x401F8464U, 0x2U, 0x401F82A0U -#define IOMUXC_GPIO_EMC_39_LPUART8_RX 0x401F80B0U, 0x2U, 0x401F8560U, 0x2U, 0x401F82A0U -#define IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x401F80B0U, 0x3U, 0, 0, 0x401F82A0U -#define IOMUXC_GPIO_EMC_39_WDOG1_WDOG_B 0x401F80B0U, 0x4U, 0, 0, 0x401F82A0U -#define IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x401F80B0U, 0x5U, 0, 0, 0x401F82A0U -#define IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x401F80B0U, 0x6U, 0x401F85E0U, 0x1U, 0x401F82A0U - -#define IOMUXC_GPIO_EMC_40_SEMC_RDY 0x401F80B4U, 0x0U, 0, 0, 0x401F82A4U -#define IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x401F80B4U, 0x1U, 0, 0, 0x401F82A4U -#define IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x401F80B4U, 0x2U, 0, 0, 0x401F82A4U -#define IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x401F80B4U, 0x3U, 0x401F85CCU, 0x1U, 0x401F82A4U -#define IOMUXC_GPIO_EMC_40_ENET_MDC 0x401F80B4U, 0x4U, 0, 0, 0x401F82A4U -#define IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x401F80B4U, 0x5U, 0, 0, 0x401F82A4U -#define IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x401F80B4U, 0x6U, 0, 0, 0x401F82A4U - -#define IOMUXC_GPIO_EMC_41_SEMC_CSX00 0x401F80B8U, 0x0U, 0, 0, 0x401F82A8U -#define IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x401F80B8U, 0x1U, 0, 0, 0x401F82A8U -#define IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x401F80B8U, 0x2U, 0, 0, 0x401F82A8U -#define IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x401F80B8U, 0x3U, 0, 0, 0x401F82A8U -#define IOMUXC_GPIO_EMC_41_ENET_MDIO 0x401F80B8U, 0x4U, 0x401F8430U, 0x1U, 0x401F82A8U -#define IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x401F80B8U, 0x5U, 0, 0, 0x401F82A8U -#define IOMUXC_GPIO_EMC_41_USDHC1_VSELECT 0x401F80B8U, 0x6U, 0, 0, 0x401F82A8U - -#define IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA03 0x401F80BCU, 0x0U, 0x401F8474U, 0x2U, 0x401F82ACU -#define IOMUXC_GPIO_AD_B0_00_XBAR1_INOUT14 0x401F80BCU, 0x1U, 0x401F8644U, 0x0U, 0x401F82ACU -#define IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x401F80BCU, 0x2U, 0, 0, 0x401F82ACU -#define IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x401F80BCU, 0x3U, 0x401F83F8U, 0x0U, 0x401F82ACU -#define IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x401F80BCU, 0x4U, 0, 0, 0x401F82ACU -#define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F82ACU -#define IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x401F80BCU, 0x6U, 0, 0, 0x401F82ACU -#define IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x401F80BCU, 0x7U, 0x401F8510U, 0x0U, 0x401F82ACU - -#define IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB03 0x401F80C0U, 0x0U, 0x401F8484U, 0x2U, 0x401F82B0U -#define IOMUXC_GPIO_AD_B0_01_XBAR1_INOUT15 0x401F80C0U, 0x1U, 0x401F8648U, 0x0U, 0x401F82B0U -#define IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x401F80C0U, 0x2U, 0, 0, 0x401F82B0U -#define IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x401F80C0U, 0x3U, 0x401F83F4U, 0x0U, 0x401F82B0U -#define IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x401F80C0U, 0x4U, 0, 0, 0x401F82B0U -#define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x401F80C0U, 0x5U, 0, 0, 0x401F82B0U -#define IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x401F80C0U, 0x6U, 0, 0, 0x401F82B0U -#define IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x401F80C0U, 0x7U, 0x401F8518U, 0x0U, 0x401F82B0U - -#define IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x401F80C4U, 0x0U, 0, 0, 0x401F82B4U -#define IOMUXC_GPIO_AD_B0_02_XBAR1_INOUT16 0x401F80C4U, 0x1U, 0x401F864CU, 0x0U, 0x401F82B4U -#define IOMUXC_GPIO_AD_B0_02_LPUART6_TX 0x401F80C4U, 0x2U, 0x401F8554U, 0x1U, 0x401F82B4U -#define IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x401F80C4U, 0x3U, 0, 0, 0x401F82B4U -#define IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX00 0x401F80C4U, 0x4U, 0, 0, 0x401F82B4U -#define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x401F80C4U, 0x5U, 0, 0, 0x401F82B4U -#define IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x401F80C4U, 0x6U, 0, 0, 0x401F82B4U -#define IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x401F80C4U, 0x7U, 0x401F8514U, 0x0U, 0x401F82B4U - -#define IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x401F80C8U, 0x0U, 0x401F8450U, 0x1U, 0x401F82B8U -#define IOMUXC_GPIO_AD_B0_03_XBAR1_INOUT17 0x401F80C8U, 0x1U, 0x401F862CU, 0x1U, 0x401F82B8U -#define IOMUXC_GPIO_AD_B0_03_LPUART6_RX 0x401F80C8U, 0x2U, 0x401F8550U, 0x1U, 0x401F82B8U -#define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x401F80C8U, 0x3U, 0x401F85D0U, 0x0U, 0x401F82B8U -#define IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX01 0x401F80C8U, 0x4U, 0, 0, 0x401F82B8U -#define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x401F80C8U, 0x5U, 0, 0, 0x401F82B8U -#define IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x401F80C8U, 0x6U, 0, 0, 0x401F82B8U -#define IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x401F80C8U, 0x7U, 0x401F850CU, 0x0U, 0x401F82B8U - -#define IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x401F80CCU, 0x0U, 0, 0, 0x401F82BCU -#define IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x401F80CCU, 0x1U, 0, 0, 0x401F82BCU -#define IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x401F80CCU, 0x2U, 0, 0, 0x401F82BCU -#define IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x401F80CCU, 0x3U, 0x401F85C4U, 0x1U, 0x401F82BCU -#define IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x401F80CCU, 0x4U, 0x401F841CU, 0x1U, 0x401F82BCU -#define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F82BCU -#define IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x401F80CCU, 0x6U, 0, 0, 0x401F82BCU -#define IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x401F80CCU, 0x7U, 0, 0, 0x401F82BCU - -#define IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x401F80D0U, 0x0U, 0, 0, 0x401F82C0U -#define IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x401F80D0U, 0x1U, 0, 0, 0x401F82C0U -#define IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x401F80D0U, 0x2U, 0, 0, 0x401F82C0U -#define IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x401F80D0U, 0x3U, 0x401F85C0U, 0x1U, 0x401F82C0U -#define IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x401F80D0U, 0x4U, 0x401F8418U, 0x1U, 0x401F82C0U -#define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F82C0U -#define IOMUXC_GPIO_AD_B0_05_XBAR1_INOUT17 0x401F80D0U, 0x6U, 0x401F862CU, 0x2U, 0x401F82C0U -#define IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x401F80D0U, 0x7U, 0, 0, 0x401F82C0U - -#define IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x401F80D4U, 0x0U, 0, 0, 0x401F82C4U -#define IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x401F80D4U, 0x1U, 0, 0, 0x401F82C4U -#define IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x401F80D4U, 0x2U, 0, 0, 0x401F82C4U -#define IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x401F80D4U, 0x3U, 0x401F85B4U, 0x1U, 0x401F82C4U -#define IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x401F80D4U, 0x4U, 0x401F8414U, 0x1U, 0x401F82C4U -#define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F82C4U -#define IOMUXC_GPIO_AD_B0_06_XBAR1_INOUT18 0x401F80D4U, 0x6U, 0x401F8630U, 0x1U, 0x401F82C4U -#define IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x401F80D4U, 0x7U, 0, 0, 0x401F82C4U - -#define IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x401F80D8U, 0x0U, 0, 0, 0x401F82C8U -#define IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x401F80D8U, 0x1U, 0, 0, 0x401F82C8U -#define IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x401F80D8U, 0x2U, 0, 0, 0x401F82C8U -#define IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x401F80D8U, 0x3U, 0x401F85BCU, 0x1U, 0x401F82C8U -#define IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x401F80D8U, 0x4U, 0x401F8410U, 0x1U, 0x401F82C8U -#define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F82C8U -#define IOMUXC_GPIO_AD_B0_07_XBAR1_INOUT19 0x401F80D8U, 0x6U, 0x401F8654U, 0x1U, 0x401F82C8U -#define IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x401F80D8U, 0x7U, 0, 0, 0x401F82C8U - -#define IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x401F80DCU, 0x0U, 0, 0, 0x401F82CCU -#define IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x401F80DCU, 0x1U, 0, 0, 0x401F82CCU -#define IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x401F80DCU, 0x2U, 0, 0, 0x401F82CCU -#define IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x401F80DCU, 0x3U, 0x401F85B8U, 0x1U, 0x401F82CCU -#define IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x401F80DCU, 0x4U, 0x401F840CU, 0x1U, 0x401F82CCU -#define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F82CCU -#define IOMUXC_GPIO_AD_B0_08_XBAR1_IN20 0x401F80DCU, 0x6U, 0x401F8634U, 0x1U, 0x401F82CCU -#define IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x401F80DCU, 0x7U, 0, 0, 0x401F82CCU - -#define IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x401F80E0U, 0x0U, 0, 0, 0x401F82D0U -#define IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03 0x401F80E0U, 0x1U, 0x401F8474U, 0x3U, 0x401F82D0U -#define IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x401F80E0U, 0x2U, 0, 0, 0x401F82D0U -#define IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x401F80E0U, 0x3U, 0, 0, 0x401F82D0U -#define IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x401F80E0U, 0x4U, 0x401F8408U, 0x1U, 0x401F82D0U -#define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F82D0U -#define IOMUXC_GPIO_AD_B0_09_XBAR1_IN21 0x401F80E0U, 0x6U, 0x401F8658U, 0x1U, 0x401F82D0U -#define IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x401F80E0U, 0x7U, 0, 0, 0x401F82D0U - -#define IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x401F80E4U, 0x0U, 0, 0, 0x401F82D4U -#define IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03 0x401F80E4U, 0x1U, 0x401F8454U, 0x3U, 0x401F82D4U -#define IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x401F80E4U, 0x2U, 0, 0, 0x401F82D4U -#define IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x401F80E4U, 0x3U, 0x401F85B0U, 0x1U, 0x401F82D4U -#define IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x401F80E4U, 0x4U, 0x401F8404U, 0x1U, 0x401F82D4U -#define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F82D4U -#define IOMUXC_GPIO_AD_B0_10_XBAR1_IN22 0x401F80E4U, 0x6U, 0x401F8638U, 0x1U, 0x401F82D4U -#define IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x401F80E4U, 0x7U, 0, 0, 0x401F82D4U - -#define IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x401F80E8U, 0x0U, 0, 0, 0x401F82D8U -#define IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03 0x401F80E8U, 0x1U, 0x401F8464U, 0x3U, 0x401F82D8U -#define IOMUXC_GPIO_AD_B0_11_ENET_COL 0x401F80E8U, 0x2U, 0, 0, 0x401F82D8U -#define IOMUXC_GPIO_AD_B0_11_WDOG1_WDOG_B 0x401F80E8U, 0x3U, 0, 0, 0x401F82D8U -#define IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x401F80E8U, 0x4U, 0x401F8400U, 0x1U, 0x401F82D8U -#define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F82D8U -#define IOMUXC_GPIO_AD_B0_11_XBAR1_IN23 0x401F80E8U, 0x6U, 0x401F863CU, 0x1U, 0x401F82D8U -#define IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x401F80E8U, 0x7U, 0x401F8444U, 0x1U, 0x401F82D8U - -#define IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x401F80ECU, 0x0U, 0x401F84E4U, 0x1U, 0x401F82DCU -#define IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x401F80ECU, 0x1U, 0x401F83FCU, 0x1U, 0x401F82DCU -#define IOMUXC_GPIO_AD_B0_12_LPUART1_TX 0x401F80ECU, 0x2U, 0, 0, 0x401F82DCU -#define IOMUXC_GPIO_AD_B0_12_WDOG2_WDOG_B 0x401F80ECU, 0x3U, 0, 0, 0x401F82DCU -#define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU -#define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU -#define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU -#define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU - -#define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U -#define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0, 0, 0x401F82E0U -#define IOMUXC_GPIO_AD_B0_13_LPUART1_RX 0x401F80F0U, 0x2U, 0, 0, 0x401F82E0U -#define IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x401F80F0U, 0x3U, 0, 0, 0x401F82E0U -#define IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03 0x401F80F0U, 0x4U, 0, 0, 0x401F82E0U -#define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F82E0U -#define IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x401F80F0U, 0x6U, 0, 0, 0x401F82E0U -#define IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x401F80F0U, 0x7U, 0, 0, 0x401F82E0U - -#define IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x401F80F4U, 0x0U, 0x401F85CCU, 0x0U, 0x401F82E4U -#define IOMUXC_GPIO_AD_B0_14_XBAR1_IN24 0x401F80F4U, 0x1U, 0x401F8640U, 0x1U, 0x401F82E4U -#define IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x401F80F4U, 0x2U, 0, 0, 0x401F82E4U -#define IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x401F80F4U, 0x3U, 0, 0, 0x401F82E4U -#define IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x401F80F4U, 0x4U, 0x401F8428U, 0x0U, 0x401F82E4U -#define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F82E4U -#define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x401F80F4U, 0x6U, 0, 0, 0x401F82E4U - -#define IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x401F80F8U, 0x0U, 0, 0, 0x401F82E8U -#define IOMUXC_GPIO_AD_B0_15_XBAR1_IN25 0x401F80F8U, 0x1U, 0x401F8650U, 0x0U, 0x401F82E8U -#define IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x401F80F8U, 0x2U, 0, 0, 0x401F82E8U -#define IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x401F80F8U, 0x3U, 0x401F8444U, 0x0U, 0x401F82E8U -#define IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x401F80F8U, 0x4U, 0x401F8420U, 0x0U, 0x401F82E8U -#define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F82E8U -#define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x401F80F8U, 0x6U, 0x401F8450U, 0x2U, 0x401F82E8U -#define IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x401F80F8U, 0x7U, 0, 0, 0x401F82E8U - -#define IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x401F80FCU, 0x0U, 0x401F83F8U, 0x1U, 0x401F82ECU -#define IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 0x401F80FCU, 0x1U, 0x401F857CU, 0x1U, 0x401F82ECU -#define IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x401F80FCU, 0x2U, 0, 0, 0x401F82ECU -#define IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x401F80FCU, 0x3U, 0x401F84CCU, 0x1U, 0x401F82ECU -#define IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x401F80FCU, 0x4U, 0, 0, 0x401F82ECU -#define IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x401F80FCU, 0x5U, 0, 0, 0x401F82ECU -#define IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x401F80FCU, 0x6U, 0x401F85D8U, 0x2U, 0x401F82ECU -#define IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x401F80FCU, 0x7U, 0, 0, 0x401F82ECU - -#define IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x401F8100U, 0x0U, 0, 0, 0x401F82F0U -#define IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 0x401F8100U, 0x1U, 0x401F8580U, 0x0U, 0x401F82F0U -#define IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x401F8100U, 0x2U, 0, 0, 0x401F82F0U -#define IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x401F8100U, 0x3U, 0x401F84D0U, 0x1U, 0x401F82F0U -#define IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x401F8100U, 0x4U, 0x401F83FCU, 0x2U, 0x401F82F0U -#define IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x401F8100U, 0x5U, 0, 0, 0x401F82F0U -#define IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x401F8100U, 0x6U, 0, 0, 0x401F82F0U -#define IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x401F8100U, 0x7U, 0, 0, 0x401F82F0U - -#define IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x401F8104U, 0x0U, 0x401F83F4U, 0x1U, 0x401F82F4U -#define IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 0x401F8104U, 0x1U, 0x401F8584U, 0x1U, 0x401F82F4U -#define IOMUXC_GPIO_AD_B1_02_LPUART2_TX 0x401F8104U, 0x2U, 0x401F8530U, 0x1U, 0x401F82F4U -#define IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x401F8104U, 0x3U, 0, 0, 0x401F82F4U -#define IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x401F8104U, 0x4U, 0, 0, 0x401F82F4U -#define IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x401F8104U, 0x5U, 0, 0, 0x401F82F4U -#define IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x401F8104U, 0x6U, 0x401F85D4U, 0x1U, 0x401F82F4U -#define IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x401F8104U, 0x7U, 0, 0, 0x401F82F4U - -#define IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x401F8108U, 0x0U, 0x401F85D0U, 0x1U, 0x401F82F8U -#define IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 0x401F8108U, 0x1U, 0x401F8588U, 0x1U, 0x401F82F8U -#define IOMUXC_GPIO_AD_B1_03_LPUART2_RX 0x401F8108U, 0x2U, 0x401F852CU, 0x1U, 0x401F82F8U -#define IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x401F8108U, 0x3U, 0x401F85C8U, 0x0U, 0x401F82F8U -#define IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x401F8108U, 0x4U, 0, 0, 0x401F82F8U -#define IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x401F8108U, 0x5U, 0, 0, 0x401F82F8U -#define IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x401F8108U, 0x6U, 0x401F85E0U, 0x0U, 0x401F82F8U -#define IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x401F8108U, 0x7U, 0, 0, 0x401F82F8U - -#define IOMUXC_GPIO_AD_B1_04_FLEXSPIB_DATA03 0x401F810CU, 0x0U, 0x401F84C4U, 0x1U, 0x401F82FCU -#define IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x401F810CU, 0x1U, 0, 0, 0x401F82FCU -#define IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x401F810CU, 0x2U, 0x401F8534U, 0x1U, 0x401F82FCU -#define IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x401F810CU, 0x3U, 0, 0, 0x401F82FCU -#define IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x401F810CU, 0x4U, 0x401F8424U, 0x0U, 0x401F82FCU -#define IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x401F810CU, 0x5U, 0, 0, 0x401F82FCU -#define IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x401F810CU, 0x6U, 0x401F85E8U, 0x1U, 0x401F82FCU -#define IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x401F810CU, 0x7U, 0, 0, 0x401F82FCU - -#define IOMUXC_GPIO_AD_B1_05_FLEXSPIB_DATA02 0x401F8110U, 0x0U, 0x401F84C0U, 0x1U, 0x401F8300U -#define IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x401F8110U, 0x1U, 0x401F8430U, 0x0U, 0x401F8300U -#define IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x401F8110U, 0x2U, 0, 0, 0x401F8300U -#define IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x401F8110U, 0x3U, 0, 0, 0x401F8300U -#define IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x401F8110U, 0x4U, 0, 0, 0x401F8300U -#define IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x401F8110U, 0x5U, 0, 0, 0x401F8300U -#define IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x401F8110U, 0x6U, 0x401F85ECU, 0x1U, 0x401F8300U -#define IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x401F8110U, 0x7U, 0, 0, 0x401F8300U - -#define IOMUXC_GPIO_AD_B1_06_FLEXSPIB_DATA01 0x401F8114U, 0x0U, 0x401F84BCU, 0x1U, 0x401F8304U -#define IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x401F8114U, 0x1U, 0x401F84E0U, 0x2U, 0x401F8304U -#define IOMUXC_GPIO_AD_B1_06_LPUART3_TX 0x401F8114U, 0x2U, 0x401F853CU, 0x0U, 0x401F8304U -#define IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x401F8114U, 0x3U, 0, 0, 0x401F8304U -#define IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x401F8114U, 0x4U, 0x401F8428U, 0x1U, 0x401F8304U -#define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x401F8114U, 0x5U, 0, 0, 0x401F8304U -#define IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x401F8114U, 0x6U, 0x401F85F0U, 0x1U, 0x401F8304U -#define IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x401F8114U, 0x7U, 0, 0, 0x401F8304U - -#define IOMUXC_GPIO_AD_B1_07_FLEXSPIB_DATA00 0x401F8118U, 0x0U, 0x401F84B8U, 0x1U, 0x401F8308U -#define IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x401F8118U, 0x1U, 0x401F84DCU, 0x2U, 0x401F8308U -#define IOMUXC_GPIO_AD_B1_07_LPUART3_RX 0x401F8118U, 0x2U, 0x401F8538U, 0x0U, 0x401F8308U -#define IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x401F8118U, 0x3U, 0, 0, 0x401F8308U -#define IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x401F8118U, 0x4U, 0x401F8420U, 0x1U, 0x401F8308U -#define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x401F8118U, 0x5U, 0, 0, 0x401F8308U -#define IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x401F8118U, 0x6U, 0x401F85F4U, 0x1U, 0x401F8308U -#define IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x401F8118U, 0x7U, 0, 0, 0x401F8308U - -#define IOMUXC_GPIO_AD_B1_08_FLEXSPIA_SS1_B 0x401F811CU, 0x0U, 0, 0, 0x401F830CU -#define IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00 0x401F811CU, 0x1U, 0x401F8494U, 0x1U, 0x401F830CU -#define IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x401F811CU, 0x2U, 0, 0, 0x401F830CU -#define IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x401F811CU, 0x3U, 0x401F83FCU, 0x3U, 0x401F830CU -#define IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x401F811CU, 0x4U, 0x401F841CU, 0x0U, 0x401F830CU -#define IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x401F811CU, 0x5U, 0, 0, 0x401F830CU -#define IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x401F811CU, 0x6U, 0x401F85E4U, 0x1U, 0x401F830CU -#define IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x401F811CU, 0x7U, 0, 0, 0x401F830CU - -#define IOMUXC_GPIO_AD_B1_09_FLEXSPIA_DQS 0x401F8120U, 0x0U, 0x401F84A4U, 0x1U, 0x401F8310U -#define IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA01 0x401F8120U, 0x1U, 0x401F8498U, 0x1U, 0x401F8310U -#define IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x401F8120U, 0x2U, 0x401F844CU, 0x2U, 0x401F8310U -#define IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x401F8120U, 0x3U, 0x401F858CU, 0x1U, 0x401F8310U -#define IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x401F8120U, 0x4U, 0x401F8418U, 0x0U, 0x401F8310U -#define IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x401F8120U, 0x5U, 0, 0, 0x401F8310U -#define IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x401F8120U, 0x6U, 0x401F85DCU, 0x1U, 0x401F8310U -#define IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x401F8120U, 0x7U, 0, 0, 0x401F8310U - -#define IOMUXC_GPIO_AD_B1_10_FLEXSPIA_DATA03 0x401F8124U, 0x0U, 0x401F84B4U, 0x1U, 0x401F8314U -#define IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x401F8124U, 0x1U, 0, 0, 0x401F8314U -#define IOMUXC_GPIO_AD_B1_10_LPUART8_TX 0x401F8124U, 0x2U, 0x401F8564U, 0x1U, 0x401F8314U -#define IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x401F8124U, 0x3U, 0x401F85A4U, 0x1U, 0x401F8314U -#define IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x401F8124U, 0x4U, 0x401F8414U, 0x0U, 0x401F8314U -#define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x401F8124U, 0x5U, 0, 0, 0x401F8314U -#define IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x401F8124U, 0x6U, 0x401F8608U, 0x1U, 0x401F8314U -#define IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x401F8124U, 0x7U, 0, 0, 0x401F8314U - -#define IOMUXC_GPIO_AD_B1_11_FLEXSPIA_DATA02 0x401F8128U, 0x0U, 0x401F84B0U, 0x1U, 0x401F8318U -#define IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x401F8128U, 0x1U, 0, 0, 0x401F8318U -#define IOMUXC_GPIO_AD_B1_11_LPUART8_RX 0x401F8128U, 0x2U, 0x401F8560U, 0x1U, 0x401F8318U -#define IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x401F8128U, 0x3U, 0x401F8590U, 0x1U, 0x401F8318U -#define IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x401F8128U, 0x4U, 0x401F8410U, 0x0U, 0x401F8318U -#define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x401F8128U, 0x5U, 0, 0, 0x401F8318U -#define IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x401F8128U, 0x6U, 0, 0, 0x401F8318U -#define IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x401F8128U, 0x7U, 0, 0, 0x401F8318U - -#define IOMUXC_GPIO_AD_B1_12_FLEXSPIA_DATA01 0x401F812CU, 0x0U, 0x401F84ACU, 0x1U, 0x401F831CU -#define IOMUXC_GPIO_AD_B1_12_ACMP_OUT00 0x401F812CU, 0x1U, 0, 0, 0x401F831CU -#define IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x401F812CU, 0x2U, 0x401F850CU, 0x1U, 0x401F831CU -#define IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x401F812CU, 0x3U, 0x401F8594U, 0x1U, 0x401F831CU -#define IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x401F812CU, 0x4U, 0x401F840CU, 0x0U, 0x401F831CU -#define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x401F812CU, 0x5U, 0, 0, 0x401F831CU -#define IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x401F812CU, 0x6U, 0x401F85F8U, 0x1U, 0x401F831CU -#define IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x401F812CU, 0x7U, 0, 0, 0x401F831CU - -#define IOMUXC_GPIO_AD_B1_13_FLEXSPIA_DATA00 0x401F8130U, 0x0U, 0x401F84A8U, 0x1U, 0x401F8320U -#define IOMUXC_GPIO_AD_B1_13_ACMP_OUT01 0x401F8130U, 0x1U, 0, 0, 0x401F8320U -#define IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x401F8130U, 0x2U, 0x401F8514U, 0x1U, 0x401F8320U -#define IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x401F8130U, 0x3U, 0, 0, 0x401F8320U -#define IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x401F8130U, 0x4U, 0x401F8408U, 0x0U, 0x401F8320U -#define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x401F8130U, 0x5U, 0, 0, 0x401F8320U -#define IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x401F8130U, 0x6U, 0x401F85FCU, 0x1U, 0x401F8320U -#define IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x401F8130U, 0x7U, 0, 0, 0x401F8320U - -#define IOMUXC_GPIO_AD_B1_14_FLEXSPIA_SCLK 0x401F8134U, 0x0U, 0x401F84C8U, 0x1U, 0x401F8324U -#define IOMUXC_GPIO_AD_B1_14_ACMP_OUT02 0x401F8134U, 0x1U, 0, 0, 0x401F8324U -#define IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x401F8134U, 0x2U, 0x401F8518U, 0x1U, 0x401F8324U -#define IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x401F8134U, 0x3U, 0x401F85A8U, 0x1U, 0x401F8324U -#define IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x401F8134U, 0x4U, 0x401F8404U, 0x0U, 0x401F8324U -#define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x401F8134U, 0x5U, 0, 0, 0x401F8324U -#define IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x401F8134U, 0x6U, 0x401F8600U, 0x1U, 0x401F8324U -#define IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x401F8134U, 0x7U, 0, 0, 0x401F8324U - -#define IOMUXC_GPIO_AD_B1_15_FLEXSPIA_SS0_B 0x401F8138U, 0x0U, 0, 0, 0x401F8328U -#define IOMUXC_GPIO_AD_B1_15_ACMP_OUT03 0x401F8138U, 0x1U, 0, 0, 0x401F8328U -#define IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x401F8138U, 0x2U, 0, 0, 0x401F8328U -#define IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x401F8138U, 0x3U, 0x401F85ACU, 0x1U, 0x401F8328U -#define IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x401F8138U, 0x4U, 0x401F8400U, 0x0U, 0x401F8328U -#define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x401F8138U, 0x5U, 0, 0, 0x401F8328U -#define IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x401F8138U, 0x6U, 0x401F8604U, 0x1U, 0x401F8328U -#define IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x401F8138U, 0x7U, 0, 0, 0x401F8328U - -#define IOMUXC_GPIO_B0_00_LCD_CLK 0x401F813CU, 0x0U, 0, 0, 0x401F832CU -#define IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 0x401F813CU, 0x1U, 0, 0, 0x401F832CU -#define IOMUXC_GPIO_B0_00_MQS_RIGHT 0x401F813CU, 0x2U, 0, 0, 0x401F832CU -#define IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x401F813CU, 0x3U, 0x401F851CU, 0x0U, 0x401F832CU -#define IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 0x401F813CU, 0x4U, 0, 0, 0x401F832CU -#define IOMUXC_GPIO_B0_00_GPIO2_IO00 0x401F813CU, 0x5U, 0, 0, 0x401F832CU -#define IOMUXC_GPIO_B0_00_SEMC_CSX01 0x401F813CU, 0x6U, 0, 0, 0x401F832CU - -#define IOMUXC_GPIO_B0_01_LCD_ENABLE 0x401F8140U, 0x0U, 0, 0, 0x401F8330U -#define IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 0x401F8140U, 0x1U, 0, 0, 0x401F8330U -#define IOMUXC_GPIO_B0_01_MQS_LEFT 0x401F8140U, 0x2U, 0, 0, 0x401F8330U -#define IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x401F8140U, 0x3U, 0x401F8524U, 0x0U, 0x401F8330U -#define IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 0x401F8140U, 0x4U, 0, 0, 0x401F8330U -#define IOMUXC_GPIO_B0_01_GPIO2_IO01 0x401F8140U, 0x5U, 0, 0, 0x401F8330U -#define IOMUXC_GPIO_B0_01_SEMC_CSX02 0x401F8140U, 0x6U, 0, 0, 0x401F8330U - -#define IOMUXC_GPIO_B0_02_LCD_HSYNC 0x401F8144U, 0x0U, 0, 0, 0x401F8334U -#define IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 0x401F8144U, 0x1U, 0, 0, 0x401F8334U -#define IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x401F8144U, 0x2U, 0, 0, 0x401F8334U -#define IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x401F8144U, 0x3U, 0x401F8528U, 0x0U, 0x401F8334U -#define IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 0x401F8144U, 0x4U, 0, 0, 0x401F8334U -#define IOMUXC_GPIO_B0_02_GPIO2_IO02 0x401F8144U, 0x5U, 0, 0, 0x401F8334U -#define IOMUXC_GPIO_B0_02_SEMC_CSX03 0x401F8144U, 0x6U, 0, 0, 0x401F8334U - -#define IOMUXC_GPIO_B0_03_LCD_VSYNC 0x401F8148U, 0x0U, 0, 0, 0x401F8338U -#define IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 0x401F8148U, 0x1U, 0x401F856CU, 0x1U, 0x401F8338U -#define IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x401F8148U, 0x2U, 0x401F844CU, 0x3U, 0x401F8338U -#define IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x401F8148U, 0x3U, 0x401F8520U, 0x0U, 0x401F8338U -#define IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 0x401F8148U, 0x4U, 0, 0, 0x401F8338U -#define IOMUXC_GPIO_B0_03_GPIO2_IO03 0x401F8148U, 0x5U, 0, 0, 0x401F8338U -#define IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x401F8148U, 0x6U, 0, 0, 0x401F8338U - -#define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU -#define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU -#define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU -#define IOMUXC_GPIO_B0_04_ARM_CM7_TRACE00 0x401F814CU, 0x3U, 0, 0, 0x401F833CU -#define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU -#define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU -#define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU - -#define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U -#define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U -#define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U -#define IOMUXC_GPIO_B0_05_ARM_CM7_TRACE01 0x401F8150U, 0x3U, 0, 0, 0x401F8340U -#define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U -#define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U -#define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U - -#define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U -#define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U -#define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U -#define IOMUXC_GPIO_B0_06_ARM_CM7_TRACE02 0x401F8154U, 0x3U, 0, 0, 0x401F8344U -#define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U -#define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U -#define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U - -#define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U -#define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U -#define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U -#define IOMUXC_GPIO_B0_07_ARM_CM7_TRACE03 0x401F8158U, 0x3U, 0, 0, 0x401F8348U -#define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U -#define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U -#define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U - -#define IOMUXC_GPIO_B0_08_LCD_DATA04 0x401F815CU, 0x0U, 0, 0, 0x401F834CU -#define IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 0x401F815CU, 0x1U, 0x401F8584U, 0x2U, 0x401F834CU -#define IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA01 0x401F815CU, 0x2U, 0x401F847CU, 0x1U, 0x401F834CU -#define IOMUXC_GPIO_B0_08_LPUART3_TX 0x401F815CU, 0x3U, 0x401F853CU, 0x2U, 0x401F834CU -#define IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 0x401F815CU, 0x4U, 0, 0, 0x401F834CU -#define IOMUXC_GPIO_B0_08_GPIO2_IO08 0x401F815CU, 0x5U, 0, 0, 0x401F834CU -#define IOMUXC_GPIO_B0_08_SRC_BOOT_CFG04 0x401F815CU, 0x6U, 0, 0, 0x401F834CU - -#define IOMUXC_GPIO_B0_09_LCD_DATA05 0x401F8160U, 0x0U, 0, 0, 0x401F8350U -#define IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 0x401F8160U, 0x1U, 0, 0, 0x401F8350U -#define IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB01 0x401F8160U, 0x2U, 0x401F848CU, 0x1U, 0x401F8350U -#define IOMUXC_GPIO_B0_09_LPUART3_RX 0x401F8160U, 0x3U, 0x401F8538U, 0x2U, 0x401F8350U -#define IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 0x401F8160U, 0x4U, 0, 0, 0x401F8350U -#define IOMUXC_GPIO_B0_09_GPIO2_IO09 0x401F8160U, 0x5U, 0, 0, 0x401F8350U -#define IOMUXC_GPIO_B0_09_SRC_BOOT_CFG05 0x401F8160U, 0x6U, 0, 0, 0x401F8350U - -#define IOMUXC_GPIO_B0_10_LCD_DATA06 0x401F8164U, 0x0U, 0, 0, 0x401F8354U -#define IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 0x401F8164U, 0x1U, 0, 0, 0x401F8354U -#define IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA02 0x401F8164U, 0x2U, 0x401F8480U, 0x1U, 0x401F8354U -#define IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x401F8164U, 0x3U, 0x401F8598U, 0x1U, 0x401F8354U -#define IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 0x401F8164U, 0x4U, 0, 0, 0x401F8354U -#define IOMUXC_GPIO_B0_10_GPIO2_IO10 0x401F8164U, 0x5U, 0, 0, 0x401F8354U -#define IOMUXC_GPIO_B0_10_SRC_BOOT_CFG06 0x401F8164U, 0x6U, 0, 0, 0x401F8354U - -#define IOMUXC_GPIO_B0_11_LCD_DATA07 0x401F8168U, 0x0U, 0, 0, 0x401F8358U -#define IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 0x401F8168U, 0x1U, 0, 0, 0x401F8358U -#define IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02 0x401F8168U, 0x2U, 0x401F8490U, 0x1U, 0x401F8358U -#define IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x401F8168U, 0x3U, 0x401F859CU, 0x1U, 0x401F8358U -#define IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 0x401F8168U, 0x4U, 0, 0, 0x401F8358U -#define IOMUXC_GPIO_B0_11_GPIO2_IO11 0x401F8168U, 0x5U, 0, 0, 0x401F8358U -#define IOMUXC_GPIO_B0_11_SRC_BOOT_CFG07 0x401F8168U, 0x6U, 0, 0, 0x401F8358U - -#define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU -#define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU -#define IOMUXC_GPIO_B0_12_ARM_CM7_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU -#define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU -#define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU -#define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU -#define IOMUXC_GPIO_B0_12_SRC_BOOT_CFG08 0x401F816CU, 0x6U, 0, 0, 0x401F835CU - -#define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U -#define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U -#define IOMUXC_GPIO_B0_13_ARM_CM7_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U -#define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U -#define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U -#define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U -#define IOMUXC_GPIO_B0_13_SRC_BOOT_CFG09 0x401F8170U, 0x6U, 0, 0, 0x401F8360U - -#define IOMUXC_GPIO_B0_14_LCD_DATA10 0x401F8174U, 0x0U, 0, 0, 0x401F8364U -#define IOMUXC_GPIO_B0_14_XBAR1_INOUT12 0x401F8174U, 0x1U, 0, 0, 0x401F8364U -#define IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x401F8174U, 0x2U, 0, 0, 0x401F8364U -#define IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x401F8174U, 0x3U, 0x401F85A4U, 0x2U, 0x401F8364U -#define IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 0x401F8174U, 0x4U, 0, 0, 0x401F8364U -#define IOMUXC_GPIO_B0_14_GPIO2_IO14 0x401F8174U, 0x5U, 0, 0, 0x401F8364U -#define IOMUXC_GPIO_B0_14_SRC_BOOT_CFG10 0x401F8174U, 0x6U, 0, 0, 0x401F8364U - -#define IOMUXC_GPIO_B0_15_LCD_DATA11 0x401F8178U, 0x0U, 0, 0, 0x401F8368U -#define IOMUXC_GPIO_B0_15_XBAR1_INOUT13 0x401F8178U, 0x1U, 0, 0, 0x401F8368U -#define IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x401F8178U, 0x2U, 0, 0, 0x401F8368U -#define IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x401F8178U, 0x3U, 0x401F8590U, 0x2U, 0x401F8368U -#define IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 0x401F8178U, 0x4U, 0, 0, 0x401F8368U -#define IOMUXC_GPIO_B0_15_GPIO2_IO15 0x401F8178U, 0x5U, 0, 0, 0x401F8368U -#define IOMUXC_GPIO_B0_15_SRC_BOOT_CFG11 0x401F8178U, 0x6U, 0, 0, 0x401F8368U - -#define IOMUXC_GPIO_B1_00_LCD_DATA12 0x401F817CU, 0x0U, 0, 0, 0x401F836CU -#define IOMUXC_GPIO_B1_00_XBAR1_INOUT14 0x401F817CU, 0x1U, 0x401F8644U, 0x1U, 0x401F836CU -#define IOMUXC_GPIO_B1_00_LPUART4_TX 0x401F817CU, 0x2U, 0x401F8544U, 0x2U, 0x401F836CU -#define IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x401F817CU, 0x3U, 0x401F8594U, 0x2U, 0x401F836CU -#define IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 0x401F817CU, 0x4U, 0, 0, 0x401F836CU -#define IOMUXC_GPIO_B1_00_GPIO2_IO16 0x401F817CU, 0x5U, 0, 0, 0x401F836CU -#define IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03 0x401F817CU, 0x6U, 0x401F8454U, 0x4U, 0x401F836CU - -#define IOMUXC_GPIO_B1_01_LCD_DATA13 0x401F8180U, 0x0U, 0, 0, 0x401F8370U -#define IOMUXC_GPIO_B1_01_XBAR1_INOUT15 0x401F8180U, 0x1U, 0x401F8648U, 0x1U, 0x401F8370U -#define IOMUXC_GPIO_B1_01_LPUART4_RX 0x401F8180U, 0x2U, 0x401F8540U, 0x2U, 0x401F8370U -#define IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x401F8180U, 0x3U, 0, 0, 0x401F8370U -#define IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 0x401F8180U, 0x4U, 0, 0, 0x401F8370U -#define IOMUXC_GPIO_B1_01_GPIO2_IO17 0x401F8180U, 0x5U, 0, 0, 0x401F8370U -#define IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03 0x401F8180U, 0x6U, 0x401F8464U, 0x4U, 0x401F8370U - -#define IOMUXC_GPIO_B1_02_LCD_DATA14 0x401F8184U, 0x0U, 0, 0, 0x401F8374U -#define IOMUXC_GPIO_B1_02_XBAR1_INOUT16 0x401F8184U, 0x1U, 0x401F864CU, 0x1U, 0x401F8374U -#define IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x401F8184U, 0x2U, 0, 0, 0x401F8374U -#define IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x401F8184U, 0x3U, 0x401F85A8U, 0x2U, 0x401F8374U -#define IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 0x401F8184U, 0x4U, 0, 0, 0x401F8374U -#define IOMUXC_GPIO_B1_02_GPIO2_IO18 0x401F8184U, 0x5U, 0, 0, 0x401F8374U -#define IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03 0x401F8184U, 0x6U, 0x401F8474U, 0x4U, 0x401F8374U - -#define IOMUXC_GPIO_B1_03_LCD_DATA15 0x401F8188U, 0x0U, 0, 0, 0x401F8378U -#define IOMUXC_GPIO_B1_03_XBAR1_INOUT17 0x401F8188U, 0x1U, 0x401F862CU, 0x3U, 0x401F8378U -#define IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x401F8188U, 0x2U, 0, 0, 0x401F8378U -#define IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x401F8188U, 0x3U, 0x401F85ACU, 0x2U, 0x401F8378U -#define IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 0x401F8188U, 0x4U, 0, 0, 0x401F8378U -#define IOMUXC_GPIO_B1_03_GPIO2_IO19 0x401F8188U, 0x5U, 0, 0, 0x401F8378U -#define IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03 0x401F8188U, 0x6U, 0x401F8484U, 0x3U, 0x401F8378U - -#define IOMUXC_GPIO_B1_04_LCD_DATA16 0x401F818CU, 0x0U, 0, 0, 0x401F837CU -#define IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x401F818CU, 0x1U, 0x401F851CU, 0x1U, 0x401F837CU -#define IOMUXC_GPIO_B1_04_CSI_DATA15 0x401F818CU, 0x2U, 0, 0, 0x401F837CU -#define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU -#define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU -#define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU - -#define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U -#define IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U -#define IOMUXC_GPIO_B1_05_CSI_DATA14 0x401F8190U, 0x2U, 0, 0, 0x401F8380U -#define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U -#define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U -#define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U - -#define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U -#define IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U -#define IOMUXC_GPIO_B1_06_CSI_DATA13 0x401F8194U, 0x2U, 0, 0, 0x401F8384U -#define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U -#define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U -#define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U - -#define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U -#define IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U -#define IOMUXC_GPIO_B1_07_CSI_DATA12 0x401F8198U, 0x2U, 0, 0, 0x401F8388U -#define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U -#define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U -#define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U - -#define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU -#define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU -#define IOMUXC_GPIO_B1_08_CSI_DATA11 0x401F819CU, 0x2U, 0, 0, 0x401F838CU -#define IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x401F819CU, 0x3U, 0, 0, 0x401F838CU -#define IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 0x401F819CU, 0x4U, 0, 0, 0x401F838CU -#define IOMUXC_GPIO_B1_08_GPIO2_IO24 0x401F819CU, 0x5U, 0, 0, 0x401F838CU -#define IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x401F819CU, 0x6U, 0, 0, 0x401F838CU - -#define IOMUXC_GPIO_B1_09_LCD_DATA21 0x401F81A0U, 0x0U, 0, 0, 0x401F8390U -#define IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 0x401F81A0U, 0x1U, 0x401F8578U, 0x1U, 0x401F8390U -#define IOMUXC_GPIO_B1_09_CSI_DATA10 0x401F81A0U, 0x2U, 0, 0, 0x401F8390U -#define IOMUXC_GPIO_B1_09_ENET_TX_EN 0x401F81A0U, 0x3U, 0, 0, 0x401F8390U -#define IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 0x401F81A0U, 0x4U, 0, 0, 0x401F8390U -#define IOMUXC_GPIO_B1_09_GPIO2_IO25 0x401F81A0U, 0x5U, 0, 0, 0x401F8390U -#define IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x401F81A0U, 0x6U, 0x401F8450U, 0x3U, 0x401F8390U - -#define IOMUXC_GPIO_B1_10_LCD_DATA22 0x401F81A4U, 0x0U, 0, 0, 0x401F8394U -#define IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 0x401F81A4U, 0x1U, 0x401F8588U, 0x2U, 0x401F8394U -#define IOMUXC_GPIO_B1_10_CSI_DATA00 0x401F81A4U, 0x2U, 0, 0, 0x401F8394U -#define IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x401F81A4U, 0x3U, 0x401F8448U, 0x1U, 0x401F8394U -#define IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 0x401F81A4U, 0x4U, 0, 0, 0x401F8394U -#define IOMUXC_GPIO_B1_10_GPIO2_IO26 0x401F81A4U, 0x5U, 0, 0, 0x401F8394U -#define IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x401F81A4U, 0x6U, 0x401F842CU, 0x1U, 0x401F8394U - -#define IOMUXC_GPIO_B1_11_LCD_DATA23 0x401F81A8U, 0x0U, 0, 0, 0x401F8398U -#define IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 0x401F81A8U, 0x1U, 0, 0, 0x401F8398U -#define IOMUXC_GPIO_B1_11_CSI_DATA01 0x401F81A8U, 0x2U, 0, 0, 0x401F8398U -#define IOMUXC_GPIO_B1_11_ENET_RX_ER 0x401F81A8U, 0x3U, 0x401F8440U, 0x1U, 0x401F8398U -#define IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 0x401F81A8U, 0x4U, 0, 0, 0x401F8398U -#define IOMUXC_GPIO_B1_11_GPIO2_IO27 0x401F81A8U, 0x5U, 0, 0, 0x401F8398U -#define IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x401F81A8U, 0x6U, 0, 0, 0x401F8398U - -#define IOMUXC_GPIO_B1_12_LPUART5_TX 0x401F81ACU, 0x1U, 0x401F854CU, 0x1U, 0x401F839CU -#define IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x401F81ACU, 0x2U, 0x401F8424U, 0x1U, 0x401F839CU -#define IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x401F81ACU, 0x3U, 0x401F8444U, 0x2U, 0x401F839CU -#define IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 0x401F81ACU, 0x4U, 0, 0, 0x401F839CU -#define IOMUXC_GPIO_B1_12_GPIO2_IO28 0x401F81ACU, 0x5U, 0, 0, 0x401F839CU -#define IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x401F81ACU, 0x6U, 0x401F85D4U, 0x2U, 0x401F839CU - -#define IOMUXC_GPIO_B1_13_WDOG1_B 0x401F81B0U, 0x0U, 0, 0, 0x401F83A0U -#define IOMUXC_GPIO_B1_13_LPUART5_RX 0x401F81B0U, 0x1U, 0x401F8548U, 0x1U, 0x401F83A0U -#define IOMUXC_GPIO_B1_13_CSI_VSYNC 0x401F81B0U, 0x2U, 0x401F8428U, 0x2U, 0x401F83A0U -#define IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x401F81B0U, 0x3U, 0, 0, 0x401F83A0U -#define IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 0x401F81B0U, 0x4U, 0, 0, 0x401F83A0U -#define IOMUXC_GPIO_B1_13_GPIO2_IO29 0x401F81B0U, 0x5U, 0, 0, 0x401F83A0U -#define IOMUXC_GPIO_B1_13_USDHC1_WP 0x401F81B0U, 0x6U, 0x401F85D8U, 0x3U, 0x401F83A0U - -#define IOMUXC_GPIO_B1_14_ENET_MDC 0x401F81B4U, 0x0U, 0, 0, 0x401F83A4U -#define IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02 0x401F81B4U, 0x1U, 0x401F849CU, 0x1U, 0x401F83A4U -#define IOMUXC_GPIO_B1_14_CSI_HSYNC 0x401F81B4U, 0x2U, 0x401F8420U, 0x2U, 0x401F83A4U -#define IOMUXC_GPIO_B1_14_XBAR1_IN02 0x401F81B4U, 0x3U, 0x401F860CU, 0x1U, 0x401F83A4U -#define IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 0x401F81B4U, 0x4U, 0, 0, 0x401F83A4U -#define IOMUXC_GPIO_B1_14_GPIO2_IO30 0x401F81B4U, 0x5U, 0, 0, 0x401F83A4U -#define IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x401F81B4U, 0x6U, 0, 0, 0x401F83A4U - -#define IOMUXC_GPIO_B1_15_ENET_MDIO 0x401F81B8U, 0x0U, 0x401F8430U, 0x2U, 0x401F83A8U -#define IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03 0x401F81B8U, 0x1U, 0x401F84A0U, 0x1U, 0x401F83A8U -#define IOMUXC_GPIO_B1_15_CSI_MCLK 0x401F81B8U, 0x2U, 0, 0, 0x401F83A8U -#define IOMUXC_GPIO_B1_15_XBAR1_IN03 0x401F81B8U, 0x3U, 0x401F8610U, 0x1U, 0x401F83A8U -#define IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 0x401F81B8U, 0x4U, 0, 0, 0x401F83A8U -#define IOMUXC_GPIO_B1_15_GPIO2_IO31 0x401F81B8U, 0x5U, 0, 0, 0x401F83A8U -#define IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x401F81B8U, 0x6U, 0, 0, 0x401F83A8U - -#define IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x401F81BCU, 0x0U, 0, 0, 0x401F83ACU -#define IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00 0x401F81BCU, 0x1U, 0x401F8458U, 0x1U, 0x401F83ACU -#define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x401F81BCU, 0x2U, 0x401F84DCU, 0x1U, 0x401F83ACU -#define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT04 0x401F81BCU, 0x3U, 0x401F8614U, 0x1U, 0x401F83ACU -#define IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x401F81BCU, 0x4U, 0x401F84F0U, 0x1U, 0x401F83ACU -#define IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x401F81BCU, 0x5U, 0, 0, 0x401F83ACU -#define IOMUXC_GPIO_SD_B0_00_FLEXSPIA_SS1_B 0x401F81BCU, 0x6U, 0, 0, 0x401F83ACU - -#define IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x401F81C0U, 0x0U, 0, 0, 0x401F83B0U -#define IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB00 0x401F81C0U, 0x1U, 0x401F8468U, 0x1U, 0x401F83B0U -#define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x401F81C0U, 0x2U, 0x401F84E0U, 0x1U, 0x401F83B0U -#define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT05 0x401F81C0U, 0x3U, 0x401F8618U, 0x1U, 0x401F83B0U -#define IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x401F81C0U, 0x4U, 0x401F84ECU, 0x0U, 0x401F83B0U -#define IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x401F81C0U, 0x5U, 0, 0, 0x401F83B0U -#define IOMUXC_GPIO_SD_B0_01_FLEXSPIB_SS1_B 0x401F81C0U, 0x6U, 0, 0, 0x401F83B0U - -#define IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x401F81C4U, 0x0U, 0, 0, 0x401F83B4U -#define IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA01 0x401F81C4U, 0x1U, 0x401F845CU, 0x1U, 0x401F83B4U -#define IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x401F81C4U, 0x2U, 0, 0, 0x401F83B4U -#define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT06 0x401F81C4U, 0x3U, 0x401F861CU, 0x1U, 0x401F83B4U -#define IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x401F81C4U, 0x4U, 0x401F84F8U, 0x1U, 0x401F83B4U -#define IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x401F81C4U, 0x5U, 0, 0, 0x401F83B4U - -#define IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x401F81C8U, 0x0U, 0, 0, 0x401F83B8U -#define IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB01 0x401F81C8U, 0x1U, 0x401F846CU, 0x1U, 0x401F83B8U -#define IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x401F81C8U, 0x2U, 0, 0, 0x401F83B8U -#define IOMUXC_GPIO_SD_B0_03_XBAR1_INOUT07 0x401F81C8U, 0x3U, 0x401F8620U, 0x1U, 0x401F83B8U -#define IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x401F81C8U, 0x4U, 0x401F84F4U, 0x1U, 0x401F83B8U -#define IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x401F81C8U, 0x5U, 0, 0, 0x401F83B8U - -#define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x401F81CCU, 0x0U, 0, 0, 0x401F83BCU -#define IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA02 0x401F81CCU, 0x1U, 0x401F8460U, 0x1U, 0x401F83BCU -#define IOMUXC_GPIO_SD_B0_04_LPUART8_TX 0x401F81CCU, 0x2U, 0x401F8564U, 0x0U, 0x401F83BCU -#define IOMUXC_GPIO_SD_B0_04_XBAR1_INOUT08 0x401F81CCU, 0x3U, 0x401F8624U, 0x1U, 0x401F83BCU -#define IOMUXC_GPIO_SD_B0_04_FLEXSPIB_SS0_B 0x401F81CCU, 0x4U, 0, 0, 0x401F83BCU -#define IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x401F81CCU, 0x5U, 0, 0, 0x401F83BCU -#define IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x401F81CCU, 0x6U, 0, 0, 0x401F83BCU - -#define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x401F81D0U, 0x0U, 0, 0, 0x401F83C0U -#define IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB02 0x401F81D0U, 0x1U, 0x401F8470U, 0x1U, 0x401F83C0U -#define IOMUXC_GPIO_SD_B0_05_LPUART8_RX 0x401F81D0U, 0x2U, 0x401F8560U, 0x0U, 0x401F83C0U -#define IOMUXC_GPIO_SD_B0_05_XBAR1_INOUT09 0x401F81D0U, 0x3U, 0x401F8628U, 0x1U, 0x401F83C0U -#define IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS 0x401F81D0U, 0x4U, 0, 0, 0x401F83C0U -#define IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x401F81D0U, 0x5U, 0, 0, 0x401F83C0U -#define IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x401F81D0U, 0x6U, 0, 0, 0x401F83C0U - -#define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x401F81D4U, 0x0U, 0x401F85F4U, 0x0U, 0x401F83C4U -#define IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03 0x401F81D4U, 0x1U, 0x401F84C4U, 0x0U, 0x401F83C4U -#define IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03 0x401F81D4U, 0x2U, 0x401F8454U, 0x0U, 0x401F83C4U -#define IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x401F81D4U, 0x3U, 0x401F8598U, 0x0U, 0x401F83C4U -#define IOMUXC_GPIO_SD_B1_00_LPUART4_TX 0x401F81D4U, 0x4U, 0x401F8544U, 0x0U, 0x401F83C4U -#define IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x401F81D4U, 0x5U, 0, 0, 0x401F83C4U - -#define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x401F81D8U, 0x0U, 0x401F85F0U, 0x0U, 0x401F83C8U -#define IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02 0x401F81D8U, 0x1U, 0x401F84C0U, 0x0U, 0x401F83C8U -#define IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03 0x401F81D8U, 0x2U, 0x401F8464U, 0x0U, 0x401F83C8U -#define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U -#define IOMUXC_GPIO_SD_B1_01_LPUART4_RX 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U -#define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U - -#define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU -#define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU -#define IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03 0x401F81DCU, 0x2U, 0x401F8474U, 0x0U, 0x401F83CCU -#define IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x401F81DCU, 0x3U, 0x401F85A0U, 0x0U, 0x401F83CCU -#define IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x401F81DCU, 0x4U, 0, 0, 0x401F83CCU -#define IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x401F81DCU, 0x5U, 0, 0, 0x401F83CCU -#define IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x401F81DCU, 0x6U, 0, 0, 0x401F83CCU - -#define IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x401F81E0U, 0x0U, 0x401F85E8U, 0x0U, 0x401F83D0U -#define IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00 0x401F81E0U, 0x1U, 0x401F84B8U, 0x0U, 0x401F83D0U -#define IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03 0x401F81E0U, 0x2U, 0x401F8484U, 0x0U, 0x401F83D0U -#define IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x401F81E0U, 0x3U, 0x401F858CU, 0x0U, 0x401F83D0U -#define IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x401F81E0U, 0x4U, 0x401F844CU, 0x0U, 0x401F83D0U -#define IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x401F81E0U, 0x5U, 0, 0, 0x401F83D0U -#define IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x401F81E0U, 0x6U, 0x401F83FCU, 0x0U, 0x401F83D0U - -#define IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x401F81E4U, 0x0U, 0x401F85DCU, 0x0U, 0x401F83D4U -#define IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK 0x401F81E4U, 0x1U, 0, 0, 0x401F83D4U -#define IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x401F81E4U, 0x2U, 0x401F84CCU, 0x0U, 0x401F83D4U -#define IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x401F81E4U, 0x3U, 0x401F85A4U, 0x0U, 0x401F83D4U -#define IOMUXC_GPIO_SD_B1_04_FLEXSPIA_SS1_B 0x401F81E4U, 0x4U, 0, 0, 0x401F83D4U -#define IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x401F81E4U, 0x5U, 0, 0, 0x401F83D4U -#define IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x401F81E4U, 0x6U, 0, 0, 0x401F83D4U - -#define IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x401F81E8U, 0x0U, 0x401F85E4U, 0x0U, 0x401F83D8U -#define IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS 0x401F81E8U, 0x1U, 0x401F84A4U, 0x0U, 0x401F83D8U -#define IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x401F81E8U, 0x2U, 0x401F84D0U, 0x0U, 0x401F83D8U -#define IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x401F81E8U, 0x3U, 0x401F8590U, 0x0U, 0x401F83D8U -#define IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B 0x401F81E8U, 0x4U, 0, 0, 0x401F83D8U -#define IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x401F81E8U, 0x5U, 0, 0, 0x401F83D8U - -#define IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x401F81ECU, 0x0U, 0, 0, 0x401F83DCU -#define IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B 0x401F81ECU, 0x1U, 0, 0, 0x401F83DCU -#define IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x401F81ECU, 0x2U, 0, 0, 0x401F83DCU -#define IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x401F81ECU, 0x3U, 0x401F8594U, 0x0U, 0x401F83DCU -#define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F81ECU, 0x4U, 0x401F84FCU, 0x0U, 0x401F83DCU -#define IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x401F81ECU, 0x5U, 0, 0, 0x401F83DCU - -#define IOMUXC_GPIO_SD_B1_07_SEMC_CSX01 0x401F81F0U, 0x0U, 0, 0, 0x401F83E0U -#define IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK 0x401F81F0U, 0x1U, 0x401F84C8U, 0x0U, 0x401F83E0U -#define IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x401F81F0U, 0x2U, 0, 0, 0x401F83E0U -#define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U -#define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U -#define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U - -#define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U -#define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U -#define IOMUXC_GPIO_SD_B1_08_LPUART7_TX 0x401F81F4U, 0x2U, 0x401F855CU, 0x0U, 0x401F83E4U -#define IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK 0x401F81F4U, 0x3U, 0x401F85A8U, 0x0U, 0x401F83E4U -#define IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 0x401F81F4U, 0x4U, 0x401F8508U, 0x0U, 0x401F83E4U -#define IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x401F81F4U, 0x5U, 0, 0, 0x401F83E4U -#define IOMUXC_GPIO_SD_B1_08_SEMC_CSX02 0x401F81F4U, 0x6U, 0, 0, 0x401F83E4U - -#define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x401F81F8U, 0x0U, 0x401F85FCU, 0x0U, 0x401F83E8U -#define IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01 0x401F81F8U, 0x1U, 0x401F84ACU, 0x0U, 0x401F83E8U -#define IOMUXC_GPIO_SD_B1_09_LPUART7_RX 0x401F81F8U, 0x2U, 0x401F8558U, 0x0U, 0x401F83E8U -#define IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x401F81F8U, 0x3U, 0x401F85ACU, 0x0U, 0x401F83E8U -#define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F81F8U, 0x4U, 0x401F8504U, 0x0U, 0x401F83E8U -#define IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x401F81F8U, 0x5U, 0, 0, 0x401F83E8U - -#define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x401F81FCU, 0x0U, 0x401F8600U, 0x0U, 0x401F83ECU -#define IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02 0x401F81FCU, 0x1U, 0x401F84B0U, 0x0U, 0x401F83ECU -#define IOMUXC_GPIO_SD_B1_10_LPUART2_RX 0x401F81FCU, 0x2U, 0x401F852CU, 0x0U, 0x401F83ECU -#define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU -#define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU -#define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU - -#define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U -#define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U -#define IOMUXC_GPIO_SD_B1_11_LPUART2_TX 0x401F8200U, 0x2U, 0x401F8530U, 0x0U, 0x401F83F0U -#define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U -#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U -#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U - -#define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) -#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U) - -typedef enum _iomuxc_gpr_mode -{ - kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK, - kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK, - kIOMUXC_GPR_USBExposureMode = IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK, - kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK, - kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK, - kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK, - kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, - kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK, - kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK, - kIOMUXC_GPR_AHBClockEnable = IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, -} iomuxc_gpr_mode_t; - -typedef enum _iomuxc_gpr_saimclk -{ - kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, - kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, - kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, - kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, - kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, -} iomuxc_gpr_saimclk_t; - -typedef enum _iomuxc_mqs_pwm_oversample_rate -{ - kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */ - kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */ -} iomuxc_mqs_pwm_oversample_rate_t; - -/*@}*/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus */ - -/*! @name Configuration */ -/*@{*/ - -/*! - * @brief Sets the IOMUXC pin mux mode. - * @note The first five parameters can be filled with the pin function ID macros. - * - * This is an example to set the PTA6 as the lpuart0_tx: - * @code - * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0); - * @endcode - * - * This is an example to set the PTA0 as GPIOA0: - * @code - * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0); - * @endcode - * - * @param muxRegister The pin mux register. - * @param muxMode The pin mux mode. - * @param inputRegister The select input register. - * @param inputDaisy The input daisy. - * @param configRegister The config register. - * @param inputOnfield Software input on field. - */ -static inline void IOMUXC_SetPinMux(uint32_t muxRegister, - uint32_t muxMode, - uint32_t inputRegister, - uint32_t inputDaisy, - uint32_t configRegister, - uint32_t inputOnfield) -{ - *((volatile uint32_t *)muxRegister) = - IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); - - if (inputRegister) - { - *((volatile uint32_t *)inputRegister) = inputDaisy; - } -} - -/*! - * @brief Sets the IOMUXC pin configuration. - * @note The previous five parameters can be filled with the pin function ID macros. - * - * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS: - * @code - * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U)) - * @endcode - * - * @param muxRegister The pin mux register. - * @param muxMode The pin mux mode. - * @param inputRegister The select input register. - * @param inputDaisy The input daisy. - * @param configRegister The config register. - * @param configValue The pin config value. - */ -static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, - uint32_t muxMode, - uint32_t inputRegister, - uint32_t inputDaisy, - uint32_t configRegister, - uint32_t configValue) -{ - if (configRegister) - { - *((volatile uint32_t *)configRegister) = configValue; - } -} - -/*! - * @brief Sets IOMUXC general configuration for some mode. - * - * @param base The IOMUXC GPR base address. - * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode" - * @param enable True enable false disable. - */ -static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable) -{ - mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK - | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK - | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK - | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK - | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); - - if (enable) - { - base->GPR1 |= mode; - } - else - { - base->GPR1 &= ~mode; - } -} - -/*! - * @brief Sets IOMUXC general configuration for SAI MCLK selection. - * - * @param base The IOMUXC GPR base address. - * @param mclk The SAI MCLK. - * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM. - */ -static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc) -{ - uint32_t gpr; - - if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) - { - gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk); - base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; - } - else - { - gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk); - base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; - } -} - -/*! - * @brief Enters or exit MQS software reset. - * - * @param base The IOMUXC GPR base address. - * @param enable Enter or exit MQS software reset. - */ -static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable) -{ - if (enable) - { - base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; - } - else - { - base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; - } -} - - -/*! - * @brief Enables or disables MQS. - * - * @param base The IOMUXC GPR base address. - * @param enable Enable or disable the MQS. - */ -static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) -{ - if (enable) - { - base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; - } - else - { - base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; - } -} - -/*! - * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. - * - * @param base The IOMUXC GPR base address. - * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". - * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq. - */ - -static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) -{ - uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK); - - base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /*_cplusplus */ - -/*! @}*/ - -#endif /* _FSL_IOMUXC_H_ */ - diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_kpp.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_kpp.c deleted file mode 100644 index f83fd25705..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_kpp.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_kpp.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.kpp" -#endif - -#define KPP_KEYPAD_SCAN_TIMES (3U) -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to SEMC clocks for each instance. */ -static const clock_ip_name_t s_kppClock[FSL_FEATURE_SOC_KPP_COUNT] = KPP_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to SEMC bases for each instance. */ -static KPP_Type *const s_kppBases[] = KPP_BASE_PTRS; - -/*! @brief Pointers to KPP IRQ number for each instance. */ -static const IRQn_Type s_kppIrqs[] = KPP_IRQS; -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t KPP_GetInstance(KPP_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_kppBases); instance++) - { - if (s_kppBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_kppBases)); - - return instance; -} -static void KPP_Mdelay(uint64_t tickets) -{ - while (tickets--) - { - __NOP(); - } -} - -void KPP_Init(KPP_Type *base, kpp_config_t *configure) -{ - assert(configure); - - uint32_t instance = KPP_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Un-gate sdram controller clock. */ - CLOCK_EnableClock(s_kppClock[KPP_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Clear all. */ - base->KPSR &= ~(KPP_KPSR_KRIE_MASK | KPP_KPSR_KDIE_MASK); - - /* Enable the keypad row and set the column strobe output to open drain. */ - base->KPCR = KPP_KPCR_KRE(configure->activeRow); - base->KPDR = KPP_KPDR_KCD((uint8_t)~(configure->activeColumn)); - base->KPCR |= KPP_KPCR_KCO(configure->activeColumn); - - /* Set the input direction for row and output direction for column. */ - base->KDDR = KPP_KDDR_KCDD(configure->activeColumn) | KPP_KDDR_KRDD((uint8_t)~(configure->activeRow)); - - /* Clear the status flag and enable the interrupt. */ - base->KPSR = - KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK | KPP_KPSR_KDSC_MASK | configure->interrupt; - - if (configure->interrupt) - { - /* Enable at the Interrupt */ - EnableIRQ(s_kppIrqs[instance]); - } -} - -void KPP_Deinit(KPP_Type *base) -{ - /* Disable interrupts and disable all rows. */ - base->KPSR &= ~(KPP_KPSR_KRIE_MASK | KPP_KPSR_KDIE_MASK); - base->KPCR = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable KPP clock. */ - CLOCK_DisableClock(s_kppClock[KPP_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz) -{ - assert(data); - - uint16_t kppKCO = base->KPCR & KPP_KPCR_KCO_MASK; - uint8_t columIndex = 0; - uint8_t activeColumn = (base->KPCR & KPP_KPCR_KCO_MASK) >> KPP_KPCR_KCO_SHIFT; - uint8_t times; - uint8_t rowData[KPP_KEYPAD_SCAN_TIMES][KPP_KEYPAD_COLUMNNUM_MAX]; - bool press = false; - uint8_t column; - - /* Initialize row data to zero. */ - memset(&rowData[0][0], 0, sizeof(rowData)); - - /* Scanning. */ - /* Configure the column data to 1 according to column numbers. */ - base->KPDR = KPP_KPDR_KCD_MASK; - /* Configure column to totem pole for quick discharge of keypad capacitance. */ - base->KPCR &= (uint16_t)(((uint16_t)~kppKCO) | KPP_KPCR_KRE_MASK); - /* Recover. */ - base->KPCR |= kppKCO; - /* Three times scanning. */ - for (times = 0; times < KPP_KEYPAD_SCAN_TIMES; times++) - { - for (columIndex = 0; columIndex < KPP_KEYPAD_COLUMNNUM_MAX; columIndex++) - { - column = activeColumn & (1U << columIndex); - if (column) - { - /* Set the single column line to 0. */ - base->KPDR = KPP_KPDR_KCD(~(uint16_t)column); - /* Take 100us delays. */ - KPP_Mdelay(clockSrc_Hz / 10000000); - /* Read row data. */ - rowData[times][columIndex] = ~(base->KPDR & KPP_KPDR_KRD_MASK); - } - else - { - /* Read row data. */ - rowData[times][columIndex] = 0; - } - } - } - - /* Return all columns to 0 in preparation for standby mode. */ - base->KPDR &= ~KPP_KPDR_KCD_MASK; - - /* Check if three time scan data is the same. */ - for (columIndex = 0; columIndex < KPP_KEYPAD_COLUMNNUM_MAX; columIndex++) - { - if ((uint8_t)(rowData[0][columIndex] & rowData[1][columIndex]) & rowData[2][columIndex]) - { - press = true; - } - } - - if (press) - { - memcpy((void *)data, &rowData[0][0], sizeof(rowData[0])); - } - else - { - memset((void *)data, 0, sizeof(rowData[0])); - } -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_kpp.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_kpp.h deleted file mode 100644 index 46eb3aab57..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_kpp.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_KPP_H_ -#define _FSL_KPP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup kpp - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief KPP driver version 2.0.0. */ -#define FSL_KPP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -#define KPP_KEYPAD_COLUMNNUM_MAX (8U) -#define KPP_KEYPAD_ROWNUM_MAX (8U) - -/*! @brief List of interrupts supported by the peripheral. This - * enumeration uses one-bot encoding to allow a logical OR of multiple - * members. Members usually map to interrupt enable bits in one or more - * peripheral registers. - */ -typedef enum _kpp_interrupt_enable { - kKPP_keyDepressInterrupt = KPP_KPSR_KDIE_MASK, /*!< Keypad depress interrupt source */ - kKPP_keyReleaseInterrupt = KPP_KPSR_KRIE_MASK /*!< Keypad release interrupt source */ -} kpp_interrupt_enable_t; - -/*! @brief Lists of KPP synchronize chain operation. */ -typedef enum _kpp_sync_operation { - kKPP_ClearKeyDepressSyncChain = KPP_KPSR_KDSC_MASK, /*!< Keypad depress interrupt status. */ - kKPP_SetKeyReleasesSyncChain = KPP_KPSR_KRSS_MASK, /*!< Keypad release interrupt status. */ -} kpp_sync_operation_t; - -/*! @brief Lists of KPP status. */ -typedef struct _kpp_config -{ - uint8_t activeRow; /*!< The row number: bit 7 ~ 0 represents the row 7 ~ 0. */ - uint8_t activeColumn; /*!< The column number: bit 7 ~ 0 represents the column 7 ~ 0. */ - uint16_t interrupt; /*!< KPP interrupt source. A logical OR of "kpp_interrupt_enable_t". */ -} kpp_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and De-initialization - * @{ - */ - -/*! - * @brief KPP initialize. - * This function ungates the KPP clock and initializes KPP. - * This function must be called before calling any other KPP driver functions. - * - * @param base KPP peripheral base address. - * @param configure The KPP configuration structure pointer. - */ -void KPP_Init(KPP_Type *base, kpp_config_t *configure); - -/*! - * @brief Deinitializes the KPP module and gates the clock. - * This function gates the KPP clock. As a result, the KPP - * module doesn't work after calling this function. - * - * @param base KPP peripheral base address. - */ -void KPP_Deinit(KPP_Type *base); - -/* @} */ - -/*! - * @name KPP Basic Operation - * @{ - */ - -/*! - * @brief Enable the interrupt. - * - * @param base KPP peripheral base address. - * @param mask KPP interrupts to enable. This is a logical OR of the - * enumeration :: kpp_interrupt_enable_t. - */ -static inline void KPP_EnableInterrupts(KPP_Type *base, uint16_t mask) -{ - uint16_t data = base->KPSR & ~(KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK); - base->KPSR = data | mask; -} - -/*! - * @brief Disable the interrupt. - * - * @param base KPP peripheral base address. - * @param mask KPP interrupts to disable. This is a logical OR of the - * enumeration :: kpp_interrupt_enable_t. - */ -static inline void KPP_DisableInterrupts(KPP_Type *base, uint16_t mask) -{ - base->KPSR &= ~(mask | KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK); -} - -/*! - * @brief Gets the KPP interrupt event status. - * - * @param base KPP peripheral base address. - * @return The status of the KPP. Application can use the enum type in the "kpp_interrupt_enable_t" - * to get the right status of the related event. - */ -static inline uint16_t KPP_GetStatusFlag(KPP_Type *base) -{ - return (base->KPSR & (KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK)) << KPP_KPSR_KDIE_SHIFT; -} - -/*! - * @brief Clears KPP status flag. - * - * @param base KPP peripheral base address. - * @param mask KPP mask to be cleared. This is a logical OR of the - * enumeration :: kpp_interrupt_enable_t. - */ -static inline void KPP_ClearStatusFlag(KPP_Type *base, uint16_t mask) -{ - base->KPSR |= (uint16_t)((mask) >> KPP_KPSR_KDIE_SHIFT); -} - -/*! - * @brief Set KPP synchronization chain. - * - * @param base KPP peripheral base address. - * @param mask KPP mask to be cleared. This is a logical OR of the - * enumeration :: kpp_sync_operation_t. - */ -static inline void KPP_SetSynchronizeChain(KPP_Type *base, uint16_t mask) -{ - uint16_t data = base->KPSR & (KPP_KPSR_KRSS_MASK | KPP_KPSR_KDSC_MASK | KPP_KPSR_KRIE_MASK | KPP_KPSR_KDIE_MASK); - base->KPSR = data | mask; -} - -/*! - * @brief Keypad press scanning. - * - * This function will scanning all columns and rows. so - * all scanning data will be stored in the data pointer. - * - * @param base KPP peripheral base address. - * @param data KPP key press scanning data. The data buffer should be prepared with - * length at least equal to KPP_KEYPAD_COLUMNNUM_MAX * KPP_KEYPAD_ROWNUM_MAX. - * the data pointer is recommended to be a array like uint8_t data[KPP_KEYPAD_COLUMNNUM_MAX]. - * for example the data[2] = 4, that means in column 1 row 2 has a key press event. - */ -void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_KPP_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c.c deleted file mode 100644 index 7ce2c37213..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c.c +++ /dev/null @@ -1,1927 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_lpi2c.h" -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpi2c" -#endif - -/*! @brief Common sets of flags used by the driver. */ -enum _lpi2c_flag_constants -{ - /*! All flags which are cleared by the driver upon starting a transfer. */ - kMasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | - kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag | - kLPI2C_MasterDataMatchFlag, - - /*! IRQ sources enabled by the non-blocking transactional API. */ - kMasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | - kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | - kLPI2C_MasterFifoErrFlag, - - /*! Errors to check for. */ - kMasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | - kLPI2C_MasterPinLowTimeoutFlag, - - /*! All flags which are cleared by the driver upon starting a transfer. */ - kSlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag | - kLPI2C_SlaveFifoErrFlag, - - /*! IRQ sources enabled by the non-blocking transactional API. */ - kSlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | - kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | - kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, - - /*! Errors to check for. */ - kSlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag, -}; - -/* ! @brief LPI2C master fifo commands. */ -enum _lpi2c_master_fifo_cmd -{ - kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ - kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ - kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ - kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ -}; - -/*! - * @brief Default watermark values. - * - * The default watermarks are set to zero. - */ -enum _lpi2c_default_watermarks -{ - kDefaultTxWatermark = 0, - kDefaultRxWatermark = 0, -}; - -/*! @brief States for the state machine used by transactional APIs. */ -enum _lpi2c_transfer_states -{ - kIdleState = 0, - kSendCommandState, - kIssueReadCommandState, - kTransferDataState, - kStopState, - kWaitForCompletionState, -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*lpi2c_master_isr_t)(LPI2C_Type *base, lpi2c_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*lpi2c_slave_isr_t)(LPI2C_Type *base, lpi2c_slave_handle_t *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/* Not static so it can be used from fsl_lpi2c_edma.c. */ -uint32_t LPI2C_GetInstance(LPI2C_Type *base); - -static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz, - uint32_t width_ns, - uint32_t maxCycles, - uint32_t prescaler); - -static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base); - -static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone); - -static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle); - -static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags); - -static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Array to map LPI2C instance number to base pointer. */ -static LPI2C_Type *const kLpi2cBases[] = LPI2C_BASE_PTRS; - -/*! @brief Array to map LPI2C instance number to IRQ number. */ -static IRQn_Type const kLpi2cIrqs[] = LPI2C_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map LPI2C instance number to clock gate enum. */ -static clock_ip_name_t const kLpi2cClocks[] = LPI2C_CLOCKS; - -#if defined(LPI2C_PERIPH_CLOCKS) -/*! @brief Array to map LPI2C instance number to pheripheral clock gate enum. */ -static const clock_ip_name_t kLpi2cPeriphClocks[] = LPI2C_PERIPH_CLOCKS; -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointer to master IRQ handler for each instance. */ -static lpi2c_master_isr_t s_lpi2cMasterIsr; - -/*! @brief Pointers to master handles for each instance. */ -static lpi2c_master_handle_t *s_lpi2cMasterHandle[ARRAY_SIZE(kLpi2cBases)]; - -/*! @brief Pointer to slave IRQ handler for each instance. */ -static lpi2c_slave_isr_t s_lpi2cSlaveIsr; - -/*! @brief Pointers to slave handles for each instance. */ -static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[ARRAY_SIZE(kLpi2cBases)]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The LPI2C peripheral base address. - * @return LPI2C instance number starting from 0. - */ -uint32_t LPI2C_GetInstance(LPI2C_Type *base) -{ - uint32_t instance; - for (instance = 0; instance < ARRAY_SIZE(kLpi2cBases); ++instance) - { - if (kLpi2cBases[instance] == base) - { - return instance; - } - } - - assert(false); - return 0; -} - -/*! - * @brief Computes a cycle count for a given time in nanoseconds. - * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. - * @param width_ns Desired with in nanoseconds. - * @param maxCycles Maximum cycle count, determined by the number of bits wide the cycle count field is. - * @param prescaler LPI2C prescaler setting. Pass 1 if the prescaler should not be used, as for slave glitch widths. - */ -static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz, - uint32_t width_ns, - uint32_t maxCycles, - uint32_t prescaler) -{ - assert(sourceClock_Hz > 0); - assert(prescaler > 0); - - uint32_t busCycle_ns = 1000000 / (sourceClock_Hz / prescaler / 1000); - uint32_t cycles = 0; - - /* Search for the cycle count just below the desired glitch width. */ - while ((((cycles + 1) * busCycle_ns) < width_ns) && (cycles + 1 < maxCycles)) - { - ++cycles; - } - - /* If we end up with zero cycles, then set the filter to a single cycle unless the */ - /* bus clock is greater than 10x the desired glitch width. */ - if ((cycles == 0) && (busCycle_ns <= (width_ns * 10))) - { - cycles = 1; - } - - return cycles; -} - -/*! - * @brief Convert provided flags to status code, and clear any errors if present. - * @param base The LPI2C peripheral base address. - * @param status Current status flags value that will be checked. - * @retval #kStatus_Success - * @retval #kStatus_LPI2C_PinLowTimeout - * @retval #kStatus_LPI2C_ArbitrationLost - * @retval #kStatus_LPI2C_Nak - * @retval #kStatus_LPI2C_FifoError - */ -status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status) -{ - status_t result = kStatus_Success; - - /* Check for error. These errors cause a stop to automatically be sent. We must */ - /* clear the errors before a new transfer can start. */ - status &= kMasterErrorFlags; - if (status) - { - /* Select the correct error code. Ordered by severity, with bus issues first. */ - if (status & kLPI2C_MasterPinLowTimeoutFlag) - { - result = kStatus_LPI2C_PinLowTimeout; - } - else if (status & kLPI2C_MasterArbitrationLostFlag) - { - result = kStatus_LPI2C_ArbitrationLost; - } - else if (status & kLPI2C_MasterNackDetectFlag) - { - result = kStatus_LPI2C_Nak; - } - else if (status & kLPI2C_MasterFifoErrFlag) - { - result = kStatus_LPI2C_FifoError; - } - else - { - assert(false); - } - - /* Clear the flags. */ - LPI2C_MasterClearStatusFlags(base, status); - - /* Reset fifos. These flags clear automatically. */ - base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; - } - - return result; -} - -/*! - * @brief Wait until there is room in the tx fifo. - * @param base The LPI2C peripheral base address. - * @retval #kStatus_Success - * @retval #kStatus_LPI2C_PinLowTimeout - * @retval #kStatus_LPI2C_ArbitrationLost - * @retval #kStatus_LPI2C_Nak - * @retval #kStatus_LPI2C_FifoError - */ -static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base) -{ - uint32_t status; - size_t txCount; - size_t txFifoSize = FSL_FEATURE_LPI2C_FIFO_SIZEn(base); - -#if LPI2C_WAIT_TIMEOUT - uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; -#endif - do - { - status_t result; - - /* Get the number of words in the tx fifo and compute empty slots. */ - LPI2C_MasterGetFifoCounts(base, NULL, &txCount); - txCount = txFifoSize - txCount; - - /* Check for error flags. */ - status = LPI2C_MasterGetStatusFlags(base); - result = LPI2C_MasterCheckAndClearError(base, status); - if (result) - { - return result; - } -#if LPI2C_WAIT_TIMEOUT - } while ((!txCount) && (--waitTimes)); - - if (waitTimes == 0) - { - return kStatus_LPI2C_Timeout; - } -#else - } while (!txCount); -#endif - - return kStatus_Success; -} - -/*! - * @brief Make sure the bus isn't already busy. - * - * A busy bus is allowed if we are the one driving it. - * - * @param base The LPI2C peripheral base address. - * @retval #kStatus_Success - * @retval #kStatus_LPI2C_Busy - */ -status_t LPI2C_CheckForBusyBus(LPI2C_Type *base) -{ - uint32_t status = LPI2C_MasterGetStatusFlags(base); - if ((status & kLPI2C_MasterBusBusyFlag) && (!(status & kLPI2C_MasterBusyFlag))) - { - return kStatus_LPI2C_Busy; - } - - return kStatus_Success; -} - -void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig) -{ - masterConfig->enableMaster = true; - masterConfig->debugEnable = false; - masterConfig->enableDoze = true; - masterConfig->ignoreAck = false; - masterConfig->pinConfig = kLPI2C_2PinOpenDrain; - masterConfig->baudRate_Hz = 100000U; - masterConfig->busIdleTimeout_ns = 0; - masterConfig->pinLowTimeout_ns = 0; - masterConfig->sdaGlitchFilterWidth_ns = 0; - masterConfig->sclGlitchFilterWidth_ns = 0; - masterConfig->hostRequest.enable = false; - masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; - masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; -} - -void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz) -{ - uint32_t prescaler; - uint32_t cycles; - uint32_t cfgr2; - uint32_t value; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPI2C_GetInstance(base); - - /* Ungate the clock. */ - CLOCK_EnableClock(kLpi2cClocks[instance]); -#if defined(LPI2C_PERIPH_CLOCKS) - /* Ungate the functional clock in initialize function. */ - CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset peripheral before configuring it. */ - LPI2C_MasterReset(base); - - /* Doze bit: 0 is enable, 1 is disable */ - base->MCR = LPI2C_MCR_DBGEN(masterConfig->debugEnable) | LPI2C_MCR_DOZEN(!(masterConfig->enableDoze)); - - /* host request */ - value = base->MCFGR0; - value &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK | LPI2C_MCFGR0_HRSEL_MASK)); - value |= LPI2C_MCFGR0_HREN(masterConfig->hostRequest.enable) | - LPI2C_MCFGR0_HRPOL(masterConfig->hostRequest.polarity) | - LPI2C_MCFGR0_HRSEL(masterConfig->hostRequest.source); - base->MCFGR0 = value; - - /* pin config and ignore ack */ - value = base->MCFGR1; - value &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK); - value |= LPI2C_MCFGR1_PINCFG(masterConfig->pinConfig); - value |= LPI2C_MCFGR1_IGNACK(masterConfig->ignoreAck); - base->MCFGR1 = value; - - LPI2C_MasterSetWatermarks(base, kDefaultTxWatermark, kDefaultRxWatermark); - - LPI2C_MasterSetBaudRate(base, sourceClock_Hz, masterConfig->baudRate_Hz); - - /* Configure glitch filters and bus idle and pin low timeouts. */ - prescaler = (base->MCFGR1 & LPI2C_MCFGR1_PRESCALE_MASK) >> LPI2C_MCFGR1_PRESCALE_SHIFT; - cfgr2 = base->MCFGR2; - if (masterConfig->busIdleTimeout_ns) - { - cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->busIdleTimeout_ns, - (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); - cfgr2 &= ~LPI2C_MCFGR2_BUSIDLE_MASK; - cfgr2 |= LPI2C_MCFGR2_BUSIDLE(cycles); - } - if (masterConfig->sdaGlitchFilterWidth_ns) - { - cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sdaGlitchFilterWidth_ns, - (LPI2C_MCFGR2_FILTSDA_MASK >> LPI2C_MCFGR2_FILTSDA_SHIFT), 1); - cfgr2 &= ~LPI2C_MCFGR2_FILTSDA_MASK; - cfgr2 |= LPI2C_MCFGR2_FILTSDA(cycles); - } - if (masterConfig->sclGlitchFilterWidth_ns) - { - cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sclGlitchFilterWidth_ns, - (LPI2C_MCFGR2_FILTSCL_MASK >> LPI2C_MCFGR2_FILTSCL_SHIFT), 1); - cfgr2 &= ~LPI2C_MCFGR2_FILTSCL_MASK; - cfgr2 |= LPI2C_MCFGR2_FILTSCL(cycles); - } - base->MCFGR2 = cfgr2; - if (masterConfig->pinLowTimeout_ns) - { - cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256, - (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); - base->MCFGR3 = (base->MCFGR3 & ~LPI2C_MCFGR3_PINLOW_MASK) | LPI2C_MCFGR3_PINLOW(cycles); - } - - LPI2C_MasterEnable(base, masterConfig->enableMaster); -} - -void LPI2C_MasterDeinit(LPI2C_Type *base) -{ - /* Restore to reset state. */ - LPI2C_MasterReset(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPI2C_GetInstance(base); - - /* Gate clock. */ - CLOCK_DisableClock(kLpi2cClocks[instance]); -#if defined(LPI2C_PERIPH_CLOCKS) - /* Gate the functional clock. */ - CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config) -{ - /* Disable master mode. */ - bool wasEnabled = (base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT; - LPI2C_MasterEnable(base, false); - - base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(config->matchMode); - base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(config->rxDataMatchOnly); - base->MDMR = LPI2C_MDMR_MATCH0(config->match0) | LPI2C_MDMR_MATCH1(config->match1); - - /* Restore master mode. */ - if (wasEnabled) - { - LPI2C_MasterEnable(base, true); - } -} - -void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz) -{ - uint32_t prescale = 0; - uint32_t bestPre = 0; - uint32_t bestClkHi = 0; - uint32_t absError = 0; - uint32_t bestError = 0xffffffffu; - uint32_t value; - uint32_t clkHiCycle; - uint32_t computedRate; - int i; - bool wasEnabled; - - /* Disable master mode. */ - wasEnabled = (base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT; - LPI2C_MasterEnable(base, false); - - /* Baud rate = (sourceClock_Hz/2^prescale)/(CLKLO+1+CLKHI+1 + ROUNDDOWN((2+FILTSCL)/2^prescale) */ - /* Assume CLKLO = 2*CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2. */ - for (prescale = 1; (prescale <= 128) && (bestError != 0); prescale = 2 * prescale) - { - for (clkHiCycle = 1; clkHiCycle < 32; clkHiCycle++) - { - if (clkHiCycle == 1) - { - computedRate = (sourceClock_Hz / prescale) / (1 + 3 + 2 + 2 / prescale); - } - else - { - computedRate = (sourceClock_Hz / prescale) / (3 * clkHiCycle + 2 + 2 / prescale); - } - - absError = baudRate_Hz > computedRate ? baudRate_Hz - computedRate : computedRate - baudRate_Hz; - - if (absError < bestError) - { - bestPre = prescale; - bestClkHi = clkHiCycle; - bestError = absError; - - /* If the error is 0, then we can stop searching because we won't find a better match. */ - if (absError == 0) - { - break; - } - } - } - } - - /* Standard, fast, fast mode plus and ultra-fast transfers. */ - value = LPI2C_MCCR0_CLKHI(bestClkHi); - - if (bestClkHi < 2) - { - value |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1); - } - else - { - value |= LPI2C_MCCR0_CLKLO(2 * bestClkHi) | LPI2C_MCCR0_SETHOLD(bestClkHi) | LPI2C_MCCR0_DATAVD(bestClkHi / 2); - } - - base->MCCR0 = value; - - for (i = 0; i < 8; i++) - { - if (bestPre == (1U << i)) - { - bestPre = i; - break; - } - } - base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_PRESCALE_MASK) | LPI2C_MCFGR1_PRESCALE(bestPre); - - /* Restore master mode. */ - if (wasEnabled) - { - LPI2C_MasterEnable(base, true); - } -} - -status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) -{ - /* Return an error if the bus is already in use not by us. */ - status_t result = LPI2C_CheckForBusyBus(base); - if (result) - { - return result; - } - - /* Clear all flags. */ - LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); - - /* Turn off auto-stop option. */ - base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; - - /* Wait until there is room in the fifo. */ - result = LPI2C_MasterWaitForTxReady(base); - if (result) - { - return result; - } - - /* Issue start command. */ - base->MTDR = kStartCmd | (((uint32_t)address << 1U) | (uint32_t)dir); - - return kStatus_Success; -} - -status_t LPI2C_MasterStop(LPI2C_Type *base) -{ - /* Wait until there is room in the fifo. */ - status_t result = LPI2C_MasterWaitForTxReady(base); - if (result) - { - return result; - } - - /* Send the STOP signal */ - base->MTDR = kStopCmd; - -/* Wait for the stop detected flag to set, indicating the transfer has completed on the bus. */ -/* Also check for errors while waiting. */ -#if LPI2C_WAIT_TIMEOUT - uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; -#endif - -#if LPI2C_WAIT_TIMEOUT - while ((result == kStatus_Success) && (--waitTimes)) -#else - while (result == kStatus_Success) -#endif - { - uint32_t status = LPI2C_MasterGetStatusFlags(base); - - /* Check for error flags. */ - result = LPI2C_MasterCheckAndClearError(base, status); - - /* Check if the stop was sent successfully. */ - if (status & kLPI2C_MasterStopDetectFlag) - { - LPI2C_MasterClearStatusFlags(base, kLPI2C_MasterStopDetectFlag); - break; - } - } - -#if LPI2C_WAIT_TIMEOUT - if (waitTimes == 0) - { - return kStatus_LPI2C_Timeout; - } -#endif - - return result; -} - -status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize) -{ - status_t result; - uint8_t *buf; - - assert(rxBuff); - - /* Handle empty read. */ - if (!rxSize) - { - return kStatus_Success; - } - - /* Wait until there is room in the command fifo. */ - result = LPI2C_MasterWaitForTxReady(base); - if (result) - { - return result; - } - - /* Issue command to receive data. */ - base->MTDR = kRxDataCmd | LPI2C_MTDR_DATA(rxSize - 1); - -#if LPI2C_WAIT_TIMEOUT - uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; -#endif - - /* Receive data */ - buf = (uint8_t *)rxBuff; - while (rxSize--) - { - /* Read LPI2C receive fifo register. The register includes a flag to indicate whether */ - /* the FIFO is empty, so we can both get the data and check if we need to keep reading */ - /* using a single register read. */ - uint32_t value; - do - { - /* Check for errors. */ - result = LPI2C_MasterCheckAndClearError(base, LPI2C_MasterGetStatusFlags(base)); - if (result) - { - return result; - } - - value = base->MRDR; -#if LPI2C_WAIT_TIMEOUT - } while ((value & LPI2C_MRDR_RXEMPTY_MASK) && (--waitTimes)); - if (waitTimes == 0) - { - return kStatus_LPI2C_Timeout; - } -#else - } while (value & LPI2C_MRDR_RXEMPTY_MASK); -#endif - - *buf++ = value & LPI2C_MRDR_DATA_MASK; - } - - return kStatus_Success; -} - -status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize) -{ - const uint8_t *buf = (const uint8_t *)((const void *)txBuff); - - assert(txBuff); - - /* Send data buffer */ - while (txSize--) - { - /* Wait until there is room in the fifo. This also checks for errors. */ - status_t result = LPI2C_MasterWaitForTxReady(base); - if (result) - { - return result; - } - - /* Write byte into LPI2C master data register. */ - base->MTDR = *buf++; - } - - return kStatus_Success; -} - -status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer) -{ - status_t result = kStatus_Success; - uint16_t commandBuffer[7]; - uint32_t cmdCount = 0; - - assert(transfer); - assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); - - /* Return an error if the bus is already in use not by us. */ - result = LPI2C_CheckForBusyBus(base); - if (result) - { - return result; - } - - /* Clear all flags. */ - LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); - - /* Turn off auto-stop option. */ - base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; - - lpi2c_direction_t direction = transfer->subaddressSize ? kLPI2C_Write : transfer->direction; - if (!(transfer->flags & kLPI2C_TransferNoStartFlag)) - { - commandBuffer[cmdCount++] = - (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)direction); - } - - /* Subaddress, MSB first. */ - if (transfer->subaddressSize) - { - uint32_t subaddressRemaining = transfer->subaddressSize; - while (subaddressRemaining--) - { - uint8_t subaddressByte = (transfer->subaddress >> (8 * subaddressRemaining)) & 0xff; - commandBuffer[cmdCount++] = subaddressByte; - } - } - - /* Reads need special handling. */ - if ((transfer->dataSize) && (transfer->direction == kLPI2C_Read)) - { - /* Need to send repeated start if switching directions to read. */ - if (direction == kLPI2C_Write) - { - commandBuffer[cmdCount++] = - (uint16_t)kStartCmd | - (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); - } - } - - /* Send command buffer */ - uint32_t index = 0; - while (cmdCount--) - { - /* Wait until there is room in the fifo. This also checks for errors. */ - result = LPI2C_MasterWaitForTxReady(base); - if (result) - { - return result; - } - - /* Write byte into LPI2C master data register. */ - base->MTDR = commandBuffer[index]; - index++; - } - - /* Transmit data. */ - if ((transfer->direction == kLPI2C_Write) && (transfer->dataSize > 0)) - { - /* Send Data. */ - result = LPI2C_MasterSend(base, transfer->data, transfer->dataSize); - } - - /* Receive Data. */ - if ((transfer->direction == kLPI2C_Read) && (transfer->dataSize > 0)) - { - result = LPI2C_MasterReceive(base, transfer->data, transfer->dataSize); - } - - if (result) - { - return result; - } - - if ((transfer->flags & kLPI2C_TransferNoStopFlag) == 0) - { - result = LPI2C_MasterStop(base); - } - - return result; -} - -void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, - lpi2c_master_handle_t *handle, - lpi2c_master_transfer_callback_t callback, - void *userData) -{ - uint32_t instance; - - assert(handle); - - /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = LPI2C_GetInstance(base); - - /* Save base and instance. */ - handle->completionCallback = callback; - handle->userData = userData; - - /* Save this handle for IRQ use. */ - s_lpi2cMasterHandle[instance] = handle; - - /* Set irq handler. */ - s_lpi2cMasterIsr = LPI2C_MasterTransferHandleIRQ; - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); - - /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. - In some cases the LPI2C IRQ is configured through INTMUX, user needs to enable - INTMUX IRQ in application code. */ - EnableIRQ(kLpi2cIrqs[instance]); -} - -/*! - * @brief Execute states until FIFOs are exhausted. - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_LPI2C_PinLowTimeout - * @retval #kStatus_LPI2C_ArbitrationLost - * @retval #kStatus_LPI2C_Nak - * @retval #kStatus_LPI2C_FifoError - */ -static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone) -{ - uint32_t status; - status_t result = kStatus_Success; - lpi2c_master_transfer_t *xfer; - size_t txCount; - size_t rxCount; - size_t txFifoSize = FSL_FEATURE_LPI2C_FIFO_SIZEn(base); - bool state_complete = false; - - /* Set default isDone return value. */ - *isDone = false; - - /* Check for errors. */ - status = LPI2C_MasterGetStatusFlags(base); - result = LPI2C_MasterCheckAndClearError(base, status); - if (result) - { - return result; - } - - /* Get pointer to private data. */ - xfer = &handle->transfer; - - /* Get fifo counts and compute room in tx fifo. */ - LPI2C_MasterGetFifoCounts(base, &rxCount, &txCount); - txCount = txFifoSize - txCount; - - while (!state_complete) - { - /* Execute the state. */ - switch (handle->state) - { - case kSendCommandState: - { - /* Make sure there is room in the tx fifo for the next command. */ - if (!txCount--) - { - state_complete = true; - break; - } - - /* Issue command. buf is a uint8_t* pointing at the uint16 command array. */ - base->MTDR = *(uint16_t *)handle->buf; - handle->buf += sizeof(uint16_t); - - /* Count down until all commands are sent. */ - if (--handle->remainingBytes == 0) - { - /* Choose next state and set up buffer pointer and count. */ - if (xfer->dataSize) - { - /* Either a send or receive transfer is next. */ - handle->state = kTransferDataState; - handle->buf = (uint8_t *)xfer->data; - handle->remainingBytes = xfer->dataSize; - if (xfer->direction == kLPI2C_Read) - { - /* Disable TX interrupt */ - LPI2C_MasterDisableInterrupts(base, kLPI2C_MasterTxReadyFlag); - } - } - else - { - /* No transfer, so move to stop state. */ - handle->state = kStopState; - } - } - break; - } - - case kIssueReadCommandState: - /* Make sure there is room in the tx fifo for the read command. */ - if (!txCount--) - { - state_complete = true; - break; - } - - base->MTDR = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); - - /* Move to transfer state. */ - handle->state = kTransferDataState; - if (xfer->direction == kLPI2C_Read) - { - /* Disable TX interrupt */ - LPI2C_MasterDisableInterrupts(base, kLPI2C_MasterTxReadyFlag); - } - break; - - case kTransferDataState: - if (xfer->direction == kLPI2C_Write) - { - /* Make sure there is room in the tx fifo. */ - if (!txCount--) - { - state_complete = true; - break; - } - - /* Put byte to send in fifo. */ - base->MTDR = *(handle->buf)++; - } - else - { - /* XXX handle receive sizes > 256, use kIssueReadCommandState */ - /* Make sure there is data in the rx fifo. */ - if (!rxCount--) - { - state_complete = true; - break; - } - - /* Read byte from fifo. */ - *(handle->buf)++ = base->MRDR & LPI2C_MRDR_DATA_MASK; - } - - /* Move to stop when the transfer is done. */ - if (--handle->remainingBytes == 0) - { - handle->state = kStopState; - } - break; - - case kStopState: - /* Only issue a stop transition if the caller requested it. */ - if ((xfer->flags & kLPI2C_TransferNoStopFlag) == 0) - { - /* Make sure there is room in the tx fifo for the stop command. */ - if (!txCount--) - { - state_complete = true; - break; - } - - base->MTDR = kStopCmd; - } - else - { - /* Caller doesn't want to send a stop, so we're done now. */ - *isDone = true; - state_complete = true; - break; - } - handle->state = kWaitForCompletionState; - break; - - case kWaitForCompletionState: - /* We stay in this state until the stop state is detected. */ - if (status & kLPI2C_MasterStopDetectFlag) - { - *isDone = true; - } - state_complete = true; - break; - default: - assert(false); - break; - } - } - return result; -} - -/*! - * @brief Prepares the transfer state machine and fills in the command buffer. - * @param handle Master nonblocking driver handle. - */ -static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle) -{ - lpi2c_master_transfer_t *xfer = &handle->transfer; - - /* Handle no start option. */ - if (xfer->flags & kLPI2C_TransferNoStartFlag) - { - if (xfer->direction == kLPI2C_Read) - { - /* Need to issue read command first. */ - handle->state = kIssueReadCommandState; - } - else - { - /* Start immediately in the data transfer state. */ - handle->state = kTransferDataState; - } - - handle->buf = (uint8_t *)xfer->data; - handle->remainingBytes = xfer->dataSize; - } - else - { - uint16_t *cmd = (uint16_t *)&handle->commandBuffer; - uint32_t cmdCount = 0; - - /* Initial direction depends on whether a subaddress was provided, and of course the actual */ - /* data transfer direction. */ - lpi2c_direction_t direction = xfer->subaddressSize ? kLPI2C_Write : xfer->direction; - - /* Start command. */ - cmd[cmdCount++] = - (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); - - /* Subaddress, MSB first. */ - if (xfer->subaddressSize) - { - uint32_t subaddressRemaining = xfer->subaddressSize; - while (subaddressRemaining--) - { - uint8_t subaddressByte = (xfer->subaddress >> (8 * subaddressRemaining)) & 0xff; - cmd[cmdCount++] = subaddressByte; - } - } - - /* Reads need special handling. */ - if ((xfer->dataSize) && (xfer->direction == kLPI2C_Read)) - { - /* Need to send repeated start if switching directions to read. */ - if (direction == kLPI2C_Write) - { - cmd[cmdCount++] = (uint16_t)kStartCmd | - (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); - } - - /* Read command. */ - cmd[cmdCount++] = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); - } - - /* Set up state machine for transferring the commands. */ - handle->state = kSendCommandState; - handle->remainingBytes = cmdCount; - handle->buf = (uint8_t *)&handle->commandBuffer; - } -} - -status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, - lpi2c_master_handle_t *handle, - lpi2c_master_transfer_t *transfer) -{ - status_t result; - - assert(handle); - assert(transfer); - assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->state != kIdleState) - { - return kStatus_LPI2C_Busy; - } - - /* Return an error if the bus is already in use not by us. */ - result = LPI2C_CheckForBusyBus(base); - if (result) - { - return result; - } - - /* Disable LPI2C IRQ sources while we configure stuff. */ - LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); - - /* Save transfer into handle. */ - handle->transfer = *transfer; - - /* Generate commands to send. */ - LPI2C_InitTransferStateMachine(handle); - - /* Clear all flags. */ - LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); - - /* Turn off auto-stop option. */ - base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; - - /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ - LPI2C_MasterEnableInterrupts(base, kMasterIrqFlags); - - return result; -} - -status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state == kIdleState) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - uint8_t state; - uint16_t remainingBytes; - uint32_t dataSize; - - /* Cache some fields with IRQs disabled. This ensures all field values */ - /* are synchronized with each other during an ongoing transfer. */ - uint32_t irqs = LPI2C_MasterGetEnabledInterrupts(base); - LPI2C_MasterDisableInterrupts(base, irqs); - state = handle->state; - remainingBytes = handle->remainingBytes; - dataSize = handle->transfer.dataSize; - LPI2C_MasterEnableInterrupts(base, irqs); - - /* Get transfer count based on current transfer state. */ - switch (state) - { - case kIdleState: - case kSendCommandState: - case kIssueReadCommandState: /* XXX return correct value for this state when >256 reads are supported */ - *count = 0; - break; - - case kTransferDataState: - *count = dataSize - remainingBytes; - break; - - case kStopState: - case kWaitForCompletionState: - default: - *count = dataSize; - break; - } - - return kStatus_Success; -} - -void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle) -{ - if (handle->state != kIdleState) - { - /* Disable internal IRQ enables. */ - LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); - - /* Reset fifos. */ - base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; - - /* Send a stop command to finalize the transfer. */ - base->MTDR = kStopCmd; - - /* Reset handle. */ - handle->state = kIdleState; - } -} - -void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *handle) -{ - bool isDone; - status_t result; - - /* Don't do anything if we don't have a valid handle. */ - if (!handle) - { - return; - } - - if (handle->state == kIdleState) - { - return; - } - - result = LPI2C_RunTransferStateMachine(base, handle, &isDone); - - if (isDone || (result != kStatus_Success)) - { - /* XXX need to handle data that may be in rx fifo below watermark level? */ - - /* XXX handle error, terminate xfer */ - - /* Disable internal IRQ enables. */ - LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); - - /* Set handle to idle state. */ - handle->state = kIdleState; - - /* Invoke callback. */ - if (handle->completionCallback) - { - handle->completionCallback(base, handle, result, handle->userData); - } - } -} - -void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig) -{ - slaveConfig->enableSlave = true; - slaveConfig->address0 = 0U; - slaveConfig->address1 = 0U; - slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; - slaveConfig->filterDozeEnable = true; - slaveConfig->filterEnable = true; - slaveConfig->enableGeneralCall = false; - slaveConfig->sclStall.enableAck = false; - slaveConfig->sclStall.enableTx = true; - slaveConfig->sclStall.enableRx = true; - slaveConfig->sclStall.enableAddress = false; - slaveConfig->ignoreAck = false; - slaveConfig->enableReceivedAddressRead = false; - slaveConfig->sdaGlitchFilterWidth_ns = 0; /* TODO determine default width values */ - slaveConfig->sclGlitchFilterWidth_ns = 0; - slaveConfig->dataValidDelay_ns = 0; - slaveConfig->clockHoldTime_ns = 0; -} - -void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPI2C_GetInstance(base); - - /* Ungate the clock. */ - CLOCK_EnableClock(kLpi2cClocks[instance]); -#if defined(LPI2C_PERIPH_CLOCKS) - /* Ungate the functional clock in initialize function. */ - CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Restore to reset conditions. */ - LPI2C_SlaveReset(base); - - /* Configure peripheral. */ - base->SAMR = LPI2C_SAMR_ADDR0(slaveConfig->address0) | LPI2C_SAMR_ADDR1(slaveConfig->address1); - - base->SCFGR1 = - LPI2C_SCFGR1_ADDRCFG(slaveConfig->addressMatchMode) | LPI2C_SCFGR1_IGNACK(slaveConfig->ignoreAck) | - LPI2C_SCFGR1_RXCFG(slaveConfig->enableReceivedAddressRead) | LPI2C_SCFGR1_GCEN(slaveConfig->enableGeneralCall) | - LPI2C_SCFGR1_ACKSTALL(slaveConfig->sclStall.enableAck) | LPI2C_SCFGR1_TXDSTALL(slaveConfig->sclStall.enableTx) | - LPI2C_SCFGR1_RXSTALL(slaveConfig->sclStall.enableRx) | - LPI2C_SCFGR1_ADRSTALL(slaveConfig->sclStall.enableAddress); - - base->SCFGR2 = - LPI2C_SCFGR2_FILTSDA(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sdaGlitchFilterWidth_ns, - (LPI2C_SCFGR2_FILTSDA_MASK >> LPI2C_SCFGR2_FILTSDA_SHIFT), 1)) | - LPI2C_SCFGR2_FILTSCL(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sclGlitchFilterWidth_ns, - (LPI2C_SCFGR2_FILTSCL_MASK >> LPI2C_SCFGR2_FILTSCL_SHIFT), 1)) | - LPI2C_SCFGR2_DATAVD(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->dataValidDelay_ns, - (LPI2C_SCFGR2_DATAVD_MASK >> LPI2C_SCFGR2_DATAVD_SHIFT), 1)) | - LPI2C_SCFGR2_CLKHOLD(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->clockHoldTime_ns, - (LPI2C_SCFGR2_CLKHOLD_MASK >> LPI2C_SCFGR2_CLKHOLD_SHIFT), 1)); - - /* Save SCR to last so we don't enable slave until it is configured */ - base->SCR = LPI2C_SCR_FILTDZ(slaveConfig->filterDozeEnable) | LPI2C_SCR_FILTEN(slaveConfig->filterEnable) | - LPI2C_SCR_SEN(slaveConfig->enableSlave); -} - -void LPI2C_SlaveDeinit(LPI2C_Type *base) -{ - LPI2C_SlaveReset(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPI2C_GetInstance(base); - - /* Gate the clock. */ - CLOCK_DisableClock(kLpi2cClocks[instance]); - -#if defined(LPI2C_PERIPH_CLOCKS) - /* Gate the functional clock. */ - CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Convert provided flags to status code, and clear any errors if present. - * @param base The LPI2C peripheral base address. - * @param status Current status flags value that will be checked. - * @retval #kStatus_Success - * @retval #kStatus_LPI2C_BitError - * @retval #kStatus_LPI2C_FifoError - */ -static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags) -{ - status_t result = kStatus_Success; - - flags &= kSlaveErrorFlags; - if (flags) - { - if (flags & kLPI2C_SlaveBitErrFlag) - { - result = kStatus_LPI2C_BitError; - } - else if (flags & kLPI2C_SlaveFifoErrFlag) - { - result = kStatus_LPI2C_FifoError; - } - else - { - assert(false); - } - - /* Clear the errors. */ - LPI2C_SlaveClearStatusFlags(base, flags); - } - - return result; -} - -status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, size_t *actualTxSize) -{ - const uint8_t *buf = (const uint8_t *)((const void *)txBuff); - size_t remaining = txSize; - - assert(txBuff); - -#if LPI2C_WAIT_TIMEOUT - uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; -#endif - - while (remaining) - { - uint32_t flags; - status_t result; - - /* Wait until we can transmit. */ - do - { - /* Check for errors */ - flags = LPI2C_SlaveGetStatusFlags(base); - result = LPI2C_SlaveCheckAndClearError(base, flags); - if (result) - { - if (actualTxSize) - { - *actualTxSize = txSize - remaining; - } - return result; - } -#if LPI2C_WAIT_TIMEOUT - } while ( - (!(flags & (kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))) && - (--waitTimes)); - if (waitTimes == 0) - { - return kStatus_LPI2C_Timeout; - } -#else - } while ( - !(flags & (kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))); -#endif - - /* Send a byte. */ - if (flags & kLPI2C_SlaveTxReadyFlag) - { - base->STDR = *buf++; - --remaining; - } - - /* Exit loop if we see a stop or restart */ - if (flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag)) - { - LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag); - break; - } - } - - if (actualTxSize) - { - *actualTxSize = txSize - remaining; - } - - return kStatus_Success; -} - -status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize) -{ - uint8_t *buf = (uint8_t *)rxBuff; - size_t remaining = rxSize; - - assert(rxBuff); - -#if LPI2C_WAIT_TIMEOUT - uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; -#endif - - while (remaining) - { - uint32_t flags; - status_t result; - - /* Wait until we can receive. */ - do - { - /* Check for errors */ - flags = LPI2C_SlaveGetStatusFlags(base); - result = LPI2C_SlaveCheckAndClearError(base, flags); - if (result) - { - if (actualRxSize) - { - *actualRxSize = rxSize - remaining; - } - return result; - } -#if LPI2C_WAIT_TIMEOUT - } while ( - (!(flags & (kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))) && - (--waitTimes)); - if (waitTimes == 0) - { - return kStatus_LPI2C_Timeout; - } -#else - } while ( - !(flags & (kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))); -#endif - - /* Receive a byte. */ - if (flags & kLPI2C_SlaveRxReadyFlag) - { - *buf++ = base->SRDR & LPI2C_SRDR_DATA_MASK; - --remaining; - } - - /* Exit loop if we see a stop or restart */ - if (flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag)) - { - LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag); - break; - } - } - - if (actualRxSize) - { - *actualRxSize = rxSize - remaining; - } - - return kStatus_Success; -} - -void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, - lpi2c_slave_handle_t *handle, - lpi2c_slave_transfer_callback_t callback, - void *userData) -{ - uint32_t instance; - - assert(handle); - - /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Look up instance number */ - instance = LPI2C_GetInstance(base); - - /* Save base and instance. */ - handle->callback = callback; - handle->userData = userData; - - /* Save this handle for IRQ use. */ - s_lpi2cSlaveHandle[instance] = handle; - - /* Set irq handler. */ - s_lpi2cSlaveIsr = LPI2C_SlaveTransferHandleIRQ; - - /* Clear internal IRQ enables and enable NVIC IRQ. */ - LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags); - EnableIRQ(kLpi2cIrqs[instance]); - - /* Nack by default. */ - base->STAR = LPI2C_STAR_TXNACK_MASK; -} - -status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask) -{ - uint32_t status; - - assert(handle); - - /* Return busy if another transaction is in progress. */ - if (handle->isBusy) - { - return kStatus_LPI2C_Busy; - } - - /* Return an error if the bus is already in use not by us. */ - status = LPI2C_SlaveGetStatusFlags(base); - if ((status & kLPI2C_SlaveBusBusyFlag) && (!(status & kLPI2C_SlaveBusyFlag))) - { - return kStatus_LPI2C_Busy; - } - - /* Disable LPI2C IRQ sources while we configure stuff. */ - LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags); - - /* Clear transfer in handle. */ - memset(&handle->transfer, 0, sizeof(handle->transfer)); - - /* Record that we're busy. */ - handle->isBusy = true; - - /* Set up event mask. tx and rx are always enabled. */ - handle->eventMask = eventMask | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent; - - /* Ack by default. */ - base->STAR = 0; - - /* Clear all flags. */ - LPI2C_SlaveClearStatusFlags(base, kSlaveClearFlags); - - /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ - LPI2C_SlaveEnableInterrupts(base, kSlaveIrqFlags); - - return kStatus_Success; -} - -status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - /* For an active transfer, just return the count from the handle. */ - *count = handle->transferredCount; - - return kStatus_Success; -} - -void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle) -{ - assert(handle); - - /* Return idle if no transaction is in progress. */ - if (handle->isBusy) - { - /* Disable LPI2C IRQ sources. */ - LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags); - - /* Nack by default. */ - base->STAR = LPI2C_STAR_TXNACK_MASK; - - /* Reset transfer info. */ - memset(&handle->transfer, 0, sizeof(handle->transfer)); - - /* We're no longer busy. */ - handle->isBusy = false; - } -} - -void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle) -{ - uint32_t flags; - lpi2c_slave_transfer_t *xfer; - - /* Check for a valid handle in case of a spurious interrupt. */ - if (!handle) - { - return; - } - - xfer = &handle->transfer; - - /* Get status flags. */ - flags = LPI2C_SlaveGetStatusFlags(base); - - if (flags & (kLPI2C_SlaveBitErrFlag | kLPI2C_SlaveFifoErrFlag)) - { - xfer->event = kLPI2C_SlaveCompletionEvent; - xfer->completionStatus = LPI2C_SlaveCheckAndClearError(base, flags); - - if ((handle->eventMask & kLPI2C_SlaveCompletionEvent) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - return; - } - if (flags & (kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag)) - { - xfer->event = (flags & kLPI2C_SlaveRepeatedStartDetectFlag) ? kLPI2C_SlaveRepeatedStartEvent : - kLPI2C_SlaveCompletionEvent; - xfer->receivedAddress = 0; - xfer->completionStatus = kStatus_Success; - xfer->transferredCount = handle->transferredCount; - - if (xfer->event == kLPI2C_SlaveCompletionEvent) - { - handle->isBusy = false; - } - - if (handle->wasTransmit) - { - /* Subtract one from the transmit count to offset the fact that LPI2C asserts the */ - /* tx flag before it sees the nack from the master-receiver, thus causing one more */ - /* count that the master actually receives. */ - --xfer->transferredCount; - handle->wasTransmit = false; - } - - /* Clear the flag. */ - LPI2C_SlaveClearStatusFlags(base, flags & (kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag)); - - /* Revert to sending an Ack by default, in case we sent a Nack for receive. */ - base->STAR = 0; - - if ((handle->eventMask & xfer->event) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - - /* Clean up transfer info on completion, after the callback has been invoked. */ - memset(&handle->transfer, 0, sizeof(handle->transfer)); - } - if (flags & kLPI2C_SlaveAddressValidFlag) - { - xfer->event = kLPI2C_SlaveAddressMatchEvent; - xfer->receivedAddress = base->SASR & LPI2C_SASR_RADDR_MASK; - - if ((handle->eventMask & kLPI2C_SlaveAddressMatchEvent) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - } - if (flags & kLPI2C_SlaveTransmitAckFlag) - { - xfer->event = kLPI2C_SlaveTransmitAckEvent; - - if ((handle->eventMask & kLPI2C_SlaveTransmitAckEvent) && (handle->callback)) - { - handle->callback(base, xfer, handle->userData); - } - } - - /* Handle transmit and receive. */ - if (flags & kLPI2C_SlaveTxReadyFlag) - { - handle->wasTransmit = true; - - /* If we're out of data, invoke callback to get more. */ - if ((!xfer->data) || (!xfer->dataSize)) - { - xfer->event = kLPI2C_SlaveTransmitEvent; - if (handle->callback) - { - handle->callback(base, xfer, handle->userData); - } - - /* Clear the transferred count now that we have a new buffer. */ - handle->transferredCount = 0; - } - - /* Transmit a byte. */ - if ((xfer->data) && (xfer->dataSize)) - { - base->STDR = *xfer->data++; - --xfer->dataSize; - ++handle->transferredCount; - } - } - if (flags & kLPI2C_SlaveRxReadyFlag) - { - /* If we're out of room in the buffer, invoke callback to get another. */ - if ((!xfer->data) || (!xfer->dataSize)) - { - xfer->event = kLPI2C_SlaveReceiveEvent; - if (handle->callback) - { - handle->callback(base, xfer, handle->userData); - } - - /* Clear the transferred count now that we have a new buffer. */ - handle->transferredCount = 0; - } - - /* Receive a byte. */ - if ((xfer->data) && (xfer->dataSize)) - { - *xfer->data++ = base->SRDR; - --xfer->dataSize; - ++handle->transferredCount; - } - else - { - /* We don't have any room to receive more data, so send a nack. */ - base->STAR = LPI2C_STAR_TXNACK_MASK; - } - } -} - -/*! - * @brief Shared IRQ handler that can call both master and slave ISRs. - * - * The master and slave ISRs are called through function pointers in order to decouple - * this code from the ISR functions. Without this, the linker would always pull in both - * ISRs and every function they call, even if only the functional API was used. - * - * @param base The LPI2C peripheral base address. - * @param instance The LPI2C peripheral instance number. - */ -static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance) -{ - /* Check for master IRQ. */ - if ((base->MCR & LPI2C_MCR_MEN_MASK) && s_lpi2cMasterIsr) - { - /* Master mode. */ - s_lpi2cMasterIsr(base, s_lpi2cMasterHandle[instance]); - } - - /* Check for slave IRQ. */ - if ((base->SCR & LPI2C_SCR_SEN_MASK) && s_lpi2cSlaveIsr) - { - /* Slave mode. */ - s_lpi2cSlaveIsr(base, s_lpi2cSlaveHandle[instance]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#if defined(LPI2C0) -/* Implementation of LPI2C0 handler named in startup code. */ -void LPI2C0_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(LPI2C0, 0); -} -#endif - -#if defined(LPI2C1) -/* Implementation of LPI2C1 handler named in startup code. */ -void LPI2C1_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(LPI2C1, 1); -} -#endif - -#if defined(LPI2C2) -/* Implementation of LPI2C2 handler named in startup code. */ -void LPI2C2_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(LPI2C2, 2); -} -#endif - -#if defined(LPI2C3) -/* Implementation of LPI2C3 handler named in startup code. */ -void LPI2C3_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(LPI2C3, 3); -} -#endif - -#if defined(LPI2C4) -/* Implementation of LPI2C4 handler named in startup code. */ -void LPI2C4_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(LPI2C4, 4); -} -#endif - -#if defined(CM4_0__LPI2C) -/* Implementation of CM4_0__LPI2C handler named in startup code. */ -void M4_0_LPI2C_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(CM4_0__LPI2C, LPI2C_GetInstance(CM4_0__LPI2C)); -} -#endif - -#if defined(CM4__LPI2C) -/* Implementation of CM4__LPI2C handler named in startup code. */ -void M4_LPI2C_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(CM4__LPI2C, LPI2C_GetInstance(CM4__LPI2C)); -} -#endif - -#if defined(CM4_1__LPI2C) -/* Implementation of CM4_1__LPI2C handler named in startup code. */ -void M4_1_LPI2C_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(CM4_1__LPI2C, LPI2C_GetInstance(CM4_1__LPI2C)); -} -#endif - -#if defined(DMA__LPI2C0) -/* Implementation of DMA__LPI2C0 handler named in startup code. */ -void DMA_I2C0_INT_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(DMA__LPI2C0, LPI2C_GetInstance(DMA__LPI2C0)); -} -#endif - -#if defined(DMA__LPI2C1) -/* Implementation of DMA__LPI2C1 handler named in startup code. */ -void DMA_I2C1_INT_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(DMA__LPI2C1, LPI2C_GetInstance(DMA__LPI2C1)); -} -#endif - -#if defined(DMA__LPI2C2) -/* Implementation of DMA__LPI2C2 handler named in startup code. */ -void DMA_I2C2_INT_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(DMA__LPI2C2, LPI2C_GetInstance(DMA__LPI2C2)); -} -#endif - -#if defined(DMA__LPI2C3) -/* Implementation of DMA__LPI2C3 handler named in startup code. */ -void DMA_I2C3_INT_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(DMA__LPI2C3, LPI2C_GetInstance(DMA__LPI2C3)); -} -#endif - -#if defined(DMA__LPI2C4) -/* Implementation of DMA__LPI2C3 handler named in startup code. */ -void DMA_I2C4_INT_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(DMA__LPI2C4, LPI2C_GetInstance(DMA__LPI2C4)); -} -#endif - -#if defined(ADMA__LPI2C0) -/* Implementation of DMA__LPI2C0 handler named in startup code. */ -void ADMA_I2C0_INT_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(ADMA__LPI2C0, LPI2C_GetInstance(ADMA__LPI2C0)); -} -#endif - -#if defined(ADMA__LPI2C1) -/* Implementation of DMA__LPI2C1 handler named in startup code. */ -void ADMA_I2C1_INT_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(ADMA__LPI2C1, LPI2C_GetInstance(ADMA__LPI2C1)); -} -#endif - -#if defined(ADMA__LPI2C2) -/* Implementation of DMA__LPI2C2 handler named in startup code. */ -void ADMA_I2C2_INT_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(ADMA__LPI2C2, LPI2C_GetInstance(ADMA__LPI2C2)); -} -#endif - -#if defined(ADMA__LPI2C3) -/* Implementation of DMA__LPI2C3 handler named in startup code. */ -void ADMA_I2C3_INT_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(ADMA__LPI2C3, LPI2C_GetInstance(ADMA__LPI2C3)); -} -#endif - -#if defined(ADMA__LPI2C4) -/* Implementation of DMA__LPI2C3 handler named in startup code. */ -void ADMA_I2C4_INT_DriverIRQHandler(void) -{ - LPI2C_CommonIRQHandler(ADMA__LPI2C4, LPI2C_GetInstance(ADMA__LPI2C4)); -} -#endif diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c.h deleted file mode 100644 index 1706a548ef..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c.h +++ /dev/null @@ -1,1293 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LPI2C_H_ -#define _FSL_LPI2C_H_ - -#include -#include "fsl_device_registers.h" -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @addtogroup lpi2c - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPI2C driver version 2.1.5. */ -#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) -/*@}*/ - -/*! @brief Timeout times for waiting flag. */ -#ifndef LPI2C_WAIT_TIMEOUT -#define LPI2C_WAIT_TIMEOUT 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ -#endif - -/*! @brief LPI2C status return codes. */ -enum _lpi2c_status -{ - kStatus_LPI2C_Busy = MAKE_STATUS(kStatusGroup_LPI2C, 0), /*!< The master is already performing a transfer. */ - kStatus_LPI2C_Idle = MAKE_STATUS(kStatusGroup_LPI2C, 1), /*!< The slave driver is idle. */ - kStatus_LPI2C_Nak = MAKE_STATUS(kStatusGroup_LPI2C, 2), /*!< The slave device sent a NAK in response to a byte. */ - kStatus_LPI2C_FifoError = MAKE_STATUS(kStatusGroup_LPI2C, 3), /*!< FIFO under run or overrun. */ - kStatus_LPI2C_BitError = MAKE_STATUS(kStatusGroup_LPI2C, 4), /*!< Transferred bit was not seen on the bus. */ - kStatus_LPI2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_LPI2C, 5), /*!< Arbitration lost error. */ - kStatus_LPI2C_PinLowTimeout = - MAKE_STATUS(kStatusGroup_LPI2C, 6), /*!< SCL or SDA were held low longer than the timeout. */ - kStatus_LPI2C_NoTransferInProgress = - MAKE_STATUS(kStatusGroup_LPI2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */ - kStatus_LPI2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_LPI2C, 8), /*!< DMA request failed. */ - kStatus_LPI2C_Timeout = MAKE_STATUS(kStatusGroup_LPI2C, 9), /*!< Timeout poling status flags. */ -}; - -/*! @} */ - -/*! - * @addtogroup lpi2c_master_driver - * @{ - */ - -/*! - * @brief LPI2C master peripheral flags. - * - * The following status register flags can be cleared: - * - #kLPI2C_MasterEndOfPacketFlag - * - #kLPI2C_MasterStopDetectFlag - * - #kLPI2C_MasterNackDetectFlag - * - #kLPI2C_MasterArbitrationLostFlag - * - #kLPI2C_MasterFifoErrFlag - * - #kLPI2C_MasterPinLowTimeoutFlag - * - #kLPI2C_MasterDataMatchFlag - * - * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as - * interrupts. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _lpi2c_master_flags -{ - kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK, /*!< Transmit data flag */ - kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK, /*!< Receive data flag */ - kLPI2C_MasterEndOfPacketFlag = LPI2C_MSR_EPF_MASK, /*!< End Packet flag */ - kLPI2C_MasterStopDetectFlag = LPI2C_MSR_SDF_MASK, /*!< Stop detect flag */ - kLPI2C_MasterNackDetectFlag = LPI2C_MSR_NDF_MASK, /*!< NACK detect flag */ - kLPI2C_MasterArbitrationLostFlag = LPI2C_MSR_ALF_MASK, /*!< Arbitration lost flag */ - kLPI2C_MasterFifoErrFlag = LPI2C_MSR_FEF_MASK, /*!< FIFO error flag */ - kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */ - kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK, /*!< Data match flag */ - kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK, /*!< Master busy flag */ - kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK /*!< Bus busy flag */ -}; - -/*! @brief Direction of master and slave transfers. */ -typedef enum _lpi2c_direction -{ - kLPI2C_Write = 0U, /*!< Master transmit. */ - kLPI2C_Read = 1U /*!< Master receive. */ -} lpi2c_direction_t; - -/*! @brief LPI2C pin configuration. */ -typedef enum _lpi2c_master_pin_config -{ - kLPI2C_2PinOpenDrain = 0x0U, /*!< LPI2C Configured for 2-pin open drain mode */ - kLPI2C_2PinOutputOnly = 0x1U, /*!< LPI2C Configured for 2-pin output only mode (ultra-fast mode) */ - kLPI2C_2PinPushPull = 0x2U, /*!< LPI2C Configured for 2-pin push-pull mode */ - kLPI2C_4PinPushPull = 0x3U, /*!< LPI2C Configured for 4-pin push-pull mode */ - kLPI2C_2PinOpenDrainWithSeparateSlave = - 0x4U, /*!< LPI2C Configured for 2-pin open drain mode with separate LPI2C slave */ - kLPI2C_2PinOutputOnlyWithSeparateSlave = - 0x5U, /*!< LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave */ - kLPI2C_2PinPushPullWithSeparateSlave = - 0x6U, /*!< LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave */ - kLPI2C_4PinPushPullWithInvertedOutput = 0x7U /*!< LPI2C Configured for 4-pin push-pull mode(inverted outputs) */ -} lpi2c_master_pin_config_t; - -/*! @brief LPI2C master host request selection. */ -typedef enum _lpi2c_host_request_source -{ - kLPI2C_HostRequestExternalPin = 0x0U, /*!< Select the LPI2C_HREQ pin as the host request input */ - kLPI2C_HostRequestInputTrigger = 0x1U, /*!< Select the input trigger as the host request input */ -} lpi2c_host_request_source_t; - -/*! @brief LPI2C master host request pin polarity configuration. */ -typedef enum _lpi2c_host_request_polarity -{ - kLPI2C_HostRequestPinActiveLow = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */ - kLPI2C_HostRequestPinActiveHigh = 0x1U /*!< Configure the LPI2C_HREQ pin active high */ -} lpi2c_host_request_polarity_t; - -/*! - * @brief Structure with settings to initialize the LPI2C master module. - * - * This structure holds configuration settings for the LPI2C peripheral. To initialize this - * structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _lpi2c_master_config -{ - bool enableMaster; /*!< Whether to enable master mode. */ - bool enableDoze; /*!< Whether master is enabled in doze mode. */ - bool debugEnable; /*!< Enable transfers to continue when halted in debug mode. */ - bool ignoreAck; /*!< Whether to ignore ACK/NACK. */ - lpi2c_master_pin_config_t pinConfig; /*!< The pin configuration option. */ - uint32_t baudRate_Hz; /*!< Desired baud rate in Hertz. */ - uint32_t busIdleTimeout_ns; /*!< Bus idle timeout in nanoseconds. Set to 0 to disable. */ - uint32_t pinLowTimeout_ns; /*!< Pin low timeout in nanoseconds. Set to 0 to disable. */ - uint8_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable. */ - uint8_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable. */ - struct - { - bool enable; /*!< Enable host request. */ - lpi2c_host_request_source_t source; /*!< Host request source. */ - lpi2c_host_request_polarity_t polarity; /*!< Host request pin polarity. */ - } hostRequest; /*!< Host request options. */ -} lpi2c_master_config_t; - -/*! @brief LPI2C master data match configuration modes. */ -typedef enum _lpi2c_data_match_config_mode -{ - kLPI2C_MatchDisabled = 0x0U, /*!< LPI2C Match Disabled */ - kLPI2C_1stWordEqualsM0OrM1 = 0x2U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1 */ - kLPI2C_AnyWordEqualsM0OrM1 = 0x3U, /*!< LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1 */ - kLPI2C_1stWordEqualsM0And2ndWordEqualsM1 = - 0x4U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1 */ - kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1 = - 0x5U, /*!< LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1 */ - kLPI2C_1stWordAndM1EqualsM0AndM1 = - 0x6U, /*!< LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1 */ - kLPI2C_AnyWordAndM1EqualsM0AndM1 = - 0x7U /*!< LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1 */ -} lpi2c_data_match_config_mode_t; - -/*! @brief LPI2C master data match configuration structure. */ -typedef struct _lpi2c_match_config -{ - lpi2c_data_match_config_mode_t matchMode; /*!< Data match configuration setting. */ - bool rxDataMatchOnly; /*!< When set to true, received data is ignored until a successful match. */ - uint32_t match0; /*!< Match value 0. */ - uint32_t match1; /*!< Match value 1. */ -} lpi2c_data_match_config_t; - -/* Forward declaration of the transfer descriptor and handle typedefs. */ -typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t; -typedef struct _lpi2c_master_handle lpi2c_master_handle_t; - -/*! - * @brief Master completion callback function pointer type. - * - * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use - * in the call to LPI2C_MasterTransferCreateHandle(). - * - * @param base The LPI2C peripheral base address. - * @param completionStatus Either #kStatus_Success or an error code describing how the transfer completed. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, - lpi2c_master_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! - * @brief Transfer option flags. - * - * @note These enumerations are intended to be OR'd together to form a bit mask of options for - * the #_lpi2c_master_transfer::flags field. - */ -enum _lpi2c_master_transfer_flags -{ - kLPI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ - kLPI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ - kLPI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ - kLPI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ -}; - -/*! - * @brief Non-blocking transfer descriptor structure. - * - * This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API. - */ -struct _lpi2c_master_transfer -{ - uint32_t - flags; /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for available - options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */ - uint16_t slaveAddress; /*!< The 7-bit slave address. */ - lpi2c_direction_t direction; /*!< Either #kLPI2C_Read or #kLPI2C_Write. */ - uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ - size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ - void *data; /*!< Pointer to data to transfer. */ - size_t dataSize; /*!< Number of bytes to transfer. */ -}; - -/*! - * @brief Driver handle for master non-blocking APIs. - * @note The contents of this structure are private and subject to change. - */ -struct _lpi2c_master_handle -{ - uint8_t state; /*!< Transfer state machine current state. */ - uint16_t remainingBytes; /*!< Remaining byte count in current state. */ - uint8_t *buf; /*!< Buffer pointer for current state. */ - uint16_t commandBuffer[7]; /*!< LPI2C command sequence. */ - lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - lpi2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ - void *userData; /*!< Application data passed to callback. */ -}; - -/*! @} */ - -/*! - * @addtogroup lpi2c_slave_driver - * @{ - */ - -/*! - * @brief LPI2C slave peripheral flags. - * - * The following status register flags can be cleared: - * - #kLPI2C_SlaveRepeatedStartDetectFlag - * - #kLPI2C_SlaveStopDetectFlag - * - #kLPI2C_SlaveBitErrFlag - * - #kLPI2C_SlaveFifoErrFlag - * - * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as - * interrupts. - * - * @note These enumerations are meant to be OR'd together to form a bit mask. - */ -enum _lpi2c_slave_flags -{ - kLPI2C_SlaveTxReadyFlag = LPI2C_SSR_TDF_MASK, /*!< Transmit data flag */ - kLPI2C_SlaveRxReadyFlag = LPI2C_SSR_RDF_MASK, /*!< Receive data flag */ - kLPI2C_SlaveAddressValidFlag = LPI2C_SSR_AVF_MASK, /*!< Address valid flag */ - kLPI2C_SlaveTransmitAckFlag = LPI2C_SSR_TAF_MASK, /*!< Transmit ACK flag */ - kLPI2C_SlaveRepeatedStartDetectFlag = LPI2C_SSR_RSF_MASK, /*!< Repeated start detect flag */ - kLPI2C_SlaveStopDetectFlag = LPI2C_SSR_SDF_MASK, /*!< Stop detect flag */ - kLPI2C_SlaveBitErrFlag = LPI2C_SSR_BEF_MASK, /*!< Bit error flag */ - kLPI2C_SlaveFifoErrFlag = LPI2C_SSR_FEF_MASK, /*!< FIFO error flag */ - kLPI2C_SlaveAddressMatch0Flag = LPI2C_SSR_AM0F_MASK, /*!< Address match 0 flag */ - kLPI2C_SlaveAddressMatch1Flag = LPI2C_SSR_AM1F_MASK, /*!< Address match 1 flag */ - kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK, /*!< General call flag */ - kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK, /*!< Master busy flag */ - kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK, /*!< Bus busy flag */ -}; - -/*! @brief LPI2C slave address match options. */ -typedef enum _lpi2c_slave_address_match -{ - kLPI2C_MatchAddress0 = 0U, /*!< Match only address 0. */ - kLPI2C_MatchAddress0OrAddress1 = 2U, /*!< Match either address 0 or address 1. */ - kLPI2C_MatchAddress0ThroughAddress1 = 6U, /*!< Match a range of slave addresses from address 0 through address 1. */ -} lpi2c_slave_address_match_t; - -/*! - * @brief Structure with settings to initialize the LPI2C slave module. - * - * This structure holds configuration settings for the LPI2C slave peripheral. To initialize this - * structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and - * pass a pointer to your configuration structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _lpi2c_slave_config -{ - bool enableSlave; /*!< Enable slave mode. */ - uint8_t address0; /*!< Slave's 7-bit address. */ - uint8_t address1; /*!< Alternate slave 7-bit address. */ - lpi2c_slave_address_match_t addressMatchMode; /*!< Address matching options. */ - bool filterDozeEnable; /*!< Enable digital glitch filter in doze mode. */ - bool filterEnable; /*!< Enable digital glitch filter. */ - bool enableGeneralCall; /*!< Enable general call address matching. */ - struct - { - bool enableAck; /*!< Enables SCL clock stretching during slave-transmit address byte(s) - and slave-receiver address and data byte(s) to allow software to - write the Transmit ACK Register before the ACK or NACK is transmitted. - Clock stretching occurs when transmitting the 9th bit. When - enableAckSCLStall is enabled, there is no need to set either - enableRxDataSCLStall or enableAddressSCLStall. */ - bool enableTx; /*!< Enables SCL clock stretching when the transmit data flag is set - during a slave-transmit transfer. */ - bool enableRx; /*!< Enables SCL clock stretching when receive data flag is set during - a slave-receive transfer. */ - bool enableAddress; /*!< Enables SCL clock stretching when the address valid flag is asserted. */ - } sclStall; - bool ignoreAck; /*!< Continue transfers after a NACK is detected. */ - bool enableReceivedAddressRead; /*!< Enable reading the address received address as the first byte of data. */ - uint32_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SDA signal. */ - uint32_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SCL signal. */ - uint32_t dataValidDelay_ns; /*!< Width in nanoseconds of the data valid delay. */ - uint32_t clockHoldTime_ns; /*!< Width in nanoseconds of the clock hold time. */ -} lpi2c_slave_config_t; - -/*! - * @brief Set of events sent to the callback for non blocking slave transfers. - * - * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together - * events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. - * Then, when the slave callback is invoked, it is passed the current event through its @a transfer - * parameter. - * - * @note These enumerations are meant to be OR'd together to form a bit mask of events. - */ -typedef enum _lpi2c_slave_transfer_event -{ - kLPI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ - kLPI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit - (slave-transmitter role). */ - kLPI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received - data (slave-receiver role). */ - kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */ - kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ - kLPI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected, completing the transfer. */ - - /*! Bit mask of all available events. */ - kLPI2C_SlaveAllEvents = kLPI2C_SlaveAddressMatchEvent | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent | - kLPI2C_SlaveTransmitAckEvent | kLPI2C_SlaveRepeatedStartEvent | kLPI2C_SlaveCompletionEvent, -} lpi2c_slave_transfer_event_t; - -/*! @brief LPI2C slave transfer structure */ -typedef struct _lpi2c_slave_transfer -{ - lpi2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ - uint8_t receivedAddress; /*!< Matching address send by master. */ - uint8_t *data; /*!< Transfer buffer */ - size_t dataSize; /*!< Transfer size */ - status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for - #kLPI2C_SlaveCompletionEvent. */ - size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */ -} lpi2c_slave_transfer_t; - -/* Forward declaration. */ -typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t; - -/*! - * @brief Slave event callback function pointer type. - * - * This callback is used only for the slave non-blocking transfer API. To install a callback, - * use the LPI2C_SlaveSetCallback() function after you have created a handle. - * - * @param base Base address for the LPI2C instance on which the event occurred. - * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData); - -/*! - * @brief LPI2C slave handle structure. - * @note The contents of this structure are private and subject to change. - */ -struct _lpi2c_slave_handle -{ - lpi2c_slave_transfer_t transfer; /*!< LPI2C slave transfer copy. */ - bool isBusy; /*!< Whether transfer is busy. */ - bool wasTransmit; /*!< Whether the last transfer was a transmit. */ - uint32_t eventMask; /*!< Mask of enabled events. */ - uint32_t transferredCount; /*!< Count of bytes transferred. */ - lpi2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ - void *userData; /*!< Callback parameter passed to callback. */ -}; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup lpi2c_master_driver - * @{ - */ - -/*! @name Initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the LPI2C master peripheral. - * - * This function provides the following default configuration for the LPI2C master peripheral: - * @code - * masterConfig->enableMaster = true; - * masterConfig->debugEnable = false; - * masterConfig->ignoreAck = false; - * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; - * masterConfig->baudRate_Hz = 100000U; - * masterConfig->busIdleTimeout_ns = 0; - * masterConfig->pinLowTimeout_ns = 0; - * masterConfig->sdaGlitchFilterWidth_ns = 0; - * masterConfig->sclGlitchFilterWidth_ns = 0; - * masterConfig->hostRequest.enable = false; - * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; - * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; - * @endcode - * - * After calling this function, you can override any settings in order to customize the configuration, - * prior to initializing the master driver with LPI2C_MasterInit(). - * - * @param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. - */ -void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig); - -/*! - * @brief Initializes the LPI2C master peripheral. - * - * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user - * provided configuration. A software reset is performed prior to configuration. - * - * @param base The LPI2C peripheral base address. - * @param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of - * defaults - * that you can override. - * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, - * filter widths, and timeout periods. - */ -void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz); - -/*! -* @brief Deinitializes the LPI2C master peripheral. -* - * This function disables the LPI2C master peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The LPI2C peripheral base address. - */ -void LPI2C_MasterDeinit(LPI2C_Type *base); - -/*! - * @brief Configures LPI2C master data match feature. - * - * @param base The LPI2C peripheral base address. - * @param config Settings for the data match feature. - */ -void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config); - -/* Not static so it can be used from fsl_lpi2c_edma.c. */ -status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); - -/* Not static so it can be used from fsl_lpi2c_edma.c. */ -status_t LPI2C_CheckForBusyBus(LPI2C_Type *base); - -/*! - * @brief Performs a software reset. - * - * Restores the LPI2C master peripheral to reset conditions. - * - * @param base The LPI2C peripheral base address. - */ -static inline void LPI2C_MasterReset(LPI2C_Type *base) -{ - base->MCR = LPI2C_MCR_RST_MASK; - base->MCR = 0; -} - -/*! - * @brief Enables or disables the LPI2C module as master. - * - * @param base The LPI2C peripheral base address. - * @param enable Pass true to enable or false to disable the specified LPI2C as master. - */ -static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable) -{ - base->MCR = (base->MCR & ~LPI2C_MCR_MEN_MASK) | LPI2C_MCR_MEN(enable); -} - -/*@}*/ - -/*! @name Status */ -/*@{*/ - -/*! - * @brief Gets the LPI2C master status flags. - * - * A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The LPI2C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see _lpi2c_master_flags - */ -static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base) -{ - return base->MSR; -} - -/*! - * @brief Clears the LPI2C master status flag state. - * - * The following status register flags can be cleared: - * - #kLPI2C_MasterEndOfPacketFlag - * - #kLPI2C_MasterStopDetectFlag - * - #kLPI2C_MasterNackDetectFlag - * - #kLPI2C_MasterArbitrationLostFlag - * - #kLPI2C_MasterFifoErrFlag - * - #kLPI2C_MasterPinLowTimeoutFlag - * - #kLPI2C_MasterDataMatchFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The LPI2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_lpi2c_master_flags enumerators OR'd together. You may pass the result of a previous call to - * LPI2C_MasterGetStatusFlags(). - * @see _lpi2c_master_flags. - */ -static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) -{ - base->MSR = statusMask; -} - -/*@}*/ - -/*! @name Interrupts */ -/*@{*/ - -/*! - * @brief Enables the LPI2C master interrupt requests. - * - * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as - * interrupts. - * - * @param base The LPI2C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_master_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) -{ - base->MIER |= interruptMask; -} - -/*! - * @brief Disables the LPI2C master interrupt requests. - * - * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as - * interrupts. - * - * @param base The LPI2C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_master_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) -{ - base->MIER &= ~interruptMask; -} - -/*! - * @brief Returns the set of currently enabled LPI2C master interrupt requests. - * - * @param base The LPI2C peripheral base address. - * @return A bitmask composed of #_lpi2c_master_flags enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base) -{ - return base->MIER; -} - -/*@}*/ - -/*! @name DMA control */ -/*@{*/ - -/*! - * @brief Enables or disables LPI2C master DMA requests. - * - * @param base The LPI2C peripheral base address. - * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. - * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. - */ -static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx) -{ - base->MDER = LPI2C_MDER_TDDE(enableTx) | LPI2C_MDER_RDDE(enableRx); -} - -/*! - * @brief Gets LPI2C master transmit data register address for DMA transfer. - * - * @param base The LPI2C peripheral base address. - * @return The LPI2C Master Transmit Data Register address. - */ -static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base) -{ - return (uint32_t)&base->MTDR; -} - -/*! - * @brief Gets LPI2C master receive data register address for DMA transfer. - * - * @param base The LPI2C peripheral base address. - * @return The LPI2C Master Receive Data Register address. - */ -static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base) -{ - return (uint32_t)&base->MRDR; -} - -/*@}*/ - -/*! @name FIFO control */ -/*@{*/ - -/*! - * @brief Sets the watermarks for LPI2C master FIFOs. - * - * @param base The LPI2C peripheral base address. - * @param txWords Transmit FIFO watermark value in words. The #kLPI2C_MasterTxReadyFlag flag is set whenever - * the number of words in the transmit FIFO is equal or less than @a txWords. Writing a value equal or - * greater than the FIFO size is truncated. - * @param rxWords Receive FIFO watermark value in words. The #kLPI2C_MasterRxReadyFlag flag is set whenever - * the number of words in the receive FIFO is greater than @a rxWords. Writing a value equal or greater - * than the FIFO size is truncated. - */ -static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords) -{ - base->MFCR = LPI2C_MFCR_TXWATER(txWords) | LPI2C_MFCR_RXWATER(rxWords); -} - -/*! - * @brief Gets the current number of words in the LPI2C master FIFOs. - * - * @param base The LPI2C peripheral base address. - * @param[out] txCount Pointer through which the current number of words in the transmit FIFO is returned. - * Pass NULL if this value is not required. - * @param[out] rxCount Pointer through which the current number of words in the receive FIFO is returned. - * Pass NULL if this value is not required. - */ -static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount) -{ - if (txCount) - { - *txCount = (base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT; - } - if (rxCount) - { - *rxCount = (base->MFSR & LPI2C_MFSR_RXCOUNT_MASK) >> LPI2C_MFSR_RXCOUNT_SHIFT; - } -} - -/*@}*/ - -/*! @name Bus operations */ -/*@{*/ - -/*! - * @brief Sets the I2C bus frequency for master transactions. - * - * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud - * rate. Do not call this function during a transfer, or the transfer is aborted. - * - * @note Please note that the second parameter is the clock frequency of LPI2C module, the third - * parameter means user configured bus baudrate, this implementation is different from other I2C drivers - * which use baudrate configuration as second parameter and source clock frequency as third parameter. - * - * @param base The LPI2C peripheral base address. - * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. - * @param baudRate_Hz Requested bus frequency in Hertz. - */ -void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz); - -/*! - * @brief Returns whether the bus is idle. - * - * Requires the master mode to be enabled. - * - * @param base The LPI2C peripheral base address. - * @retval true Bus is busy. - * @retval false Bus is idle. - */ -static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base) -{ - return (base->MSR & LPI2C_MSR_BBF_MASK) >> LPI2C_MSR_BBF_SHIFT; -} - -/*! - * @brief Sends a START signal and slave address on the I2C bus. - * - * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure - * that another master is not occupying the bus. Then a START signal is transmitted, followed by the - * 7-bit address specified in the @a address parameter. Note that this function does not actually wait - * until the START and address are successfully sent on the bus before returning. - * - * @param base The LPI2C peripheral base address. - * @param address 7-bit slave device address, in bits [6:0]. - * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set - * the R/w bit (bit 0) in the transmitted slave address. - * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. - * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. - */ -status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir); - -/*! - * @brief Sends a repeated START signal and slave address on the I2C bus. - * - * This function is used to send a Repeated START signal when a transfer is already in progress. Like - * LPI2C_MasterStart(), it also sends the specified 7-bit address. - * - * @note This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, - * as well as to better document the intent of code that uses these APIs. - * - * @param base The LPI2C peripheral base address. - * @param address 7-bit slave device address, in bits [6:0]. - * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set - * the R/w bit (bit 0) in the transmitted slave address. - * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. - * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. - */ -static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) -{ - return LPI2C_MasterStart(base, address, dir); -} - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may - * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this - * function returns #kStatus_LPI2C_Nak. - * - * @param base The LPI2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @retval #kStatus_Success Data was sent successfully. - * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_LPI2C_FifoError FIFO under run or over run. - * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. - * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. - */ -status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * @param base The LPI2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @retval #kStatus_Success Data was received successfully. - * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. - * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. - * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. - */ -status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize); - -/*! - * @brief Sends a STOP signal on the I2C bus. - * - * This function does not return until the STOP signal is seen on the bus, or an error occurs. - * - * @param base The LPI2C peripheral base address. - * @retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. - * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. - * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. - * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. - */ -status_t LPI2C_MasterStop(LPI2C_Type *base); - -/*! - * @brief Performs a master polling transfer on the I2C bus. - * - * @note The API does not return until the transfer succeeds or fails due - * to error happens during transfer. - * - * @param base The LPI2C peripheral base address. - * @param transfer Pointer to the transfer structure. - * @retval #kStatus_Success Data was received successfully. - * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. - * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. - * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. - * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. - * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. - */ -status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer); - -/*@}*/ - -/*! @name Non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the LPI2C master non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. - * - * - * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice - * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to - * enable the associated INTMUX IRQ in application. - * - * @param base The LPI2C peripheral base address. - * @param[out] handle Pointer to the LPI2C master driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, - lpi2c_master_handle_t *handle, - lpi2c_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a non-blocking transaction on the I2C bus. - * - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - * @param transfer The pointer to the transfer descriptor. - * @retval #kStatus_Success The transaction was started successfully. - * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking - * transaction is already in progress. - */ -status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, - lpi2c_master_handle_t *handle, - lpi2c_master_transfer_t *transfer); - -/*! - * @brief Returns number of bytes transferred so far. - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - * @param[out] count Number of bytes transferred so far by the non-blocking transaction. - * @retval #kStatus_Success - * @retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count); - -/*! - * @brief Terminates a non-blocking LPI2C master transmission early. - * - * @note It is not safe to call this function from an IRQ handler that has a higher priority than the - * LPI2C peripheral's IRQ priority. - * - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - * @retval #kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress. - */ -void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle); - -/*@}*/ - -/*! @name IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle master interrupts. - * @note This function does not need to be called unless you are reimplementing the - * nonblocking API's interrupt handler routines to add special functionality. - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - */ -void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *handle); - -/*@}*/ - -/*! @} */ - -/*! - * @addtogroup lpi2c_slave_driver - * @{ - */ - -/*! @name Slave initialization and deinitialization */ -/*@{*/ - -/*! - * @brief Provides a default configuration for the LPI2C slave peripheral. - * - * This function provides the following default configuration for the LPI2C slave peripheral: - * @code - * slaveConfig->enableSlave = true; - * slaveConfig->address0 = 0U; - * slaveConfig->address1 = 0U; - * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; - * slaveConfig->filterDozeEnable = true; - * slaveConfig->filterEnable = true; - * slaveConfig->enableGeneralCall = false; - * slaveConfig->sclStall.enableAck = false; - * slaveConfig->sclStall.enableTx = true; - * slaveConfig->sclStall.enableRx = true; - * slaveConfig->sclStall.enableAddress = true; - * slaveConfig->ignoreAck = false; - * slaveConfig->enableReceivedAddressRead = false; - * slaveConfig->sdaGlitchFilterWidth_ns = 0; - * slaveConfig->sclGlitchFilterWidth_ns = 0; - * slaveConfig->dataValidDelay_ns = 0; - * slaveConfig->clockHoldTime_ns = 0; - * @endcode - * - * After calling this function, override any settings to customize the configuration, - * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the @a - * address0 member of the configuration structure with the desired slave address. - * - * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to - * #lpi2c_slave_config_t. - */ -void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig); - -/*! - * @brief Initializes the LPI2C slave peripheral. - * - * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user - * provided configuration. - * - * @param base The LPI2C peripheral base address. - * @param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults - * that you can override. - * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, - * data valid delay, and clock hold time. - */ -void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz); - -/*! -* @brief Deinitializes the LPI2C slave peripheral. -* - * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software - * reset to restore the peripheral to reset conditions. - * - * @param base The LPI2C peripheral base address. - */ -void LPI2C_SlaveDeinit(LPI2C_Type *base); - -/*! - * @brief Performs a software reset of the LPI2C slave peripheral. - * - * @param base The LPI2C peripheral base address. - */ -static inline void LPI2C_SlaveReset(LPI2C_Type *base) -{ - base->SCR = LPI2C_SCR_RST_MASK; - base->SCR = 0; -} - -/*! - * @brief Enables or disables the LPI2C module as slave. - * - * @param base The LPI2C peripheral base address. - * @param enable Pass true to enable or false to disable the specified LPI2C as slave. - */ -static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable) -{ - base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable); -} - -/*@}*/ - -/*! @name Slave status */ -/*@{*/ - -/*! - * @brief Gets the LPI2C slave status flags. - * - * A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit - * in the return value is set if the flag is asserted. - * - * @param base The LPI2C peripheral base address. - * @return State of the status flags: - * - 1: related status flag is set. - * - 0: related status flag is not set. - * @see _lpi2c_slave_flags - */ -static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base) -{ - return base->SSR; -} - -/*! - * @brief Clears the LPI2C status flag state. - * - * The following status register flags can be cleared: - * - #kLPI2C_SlaveRepeatedStartDetectFlag - * - #kLPI2C_SlaveStopDetectFlag - * - #kLPI2C_SlaveBitErrFlag - * - #kLPI2C_SlaveFifoErrFlag - * - * Attempts to clear other flags has no effect. - * - * @param base The LPI2C peripheral base address. - * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_lpi2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to - * LPI2C_SlaveGetStatusFlags(). - * @see _lpi2c_slave_flags. - */ -static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) -{ - base->SSR = statusMask; -} - -/*@}*/ - -/*! @name Slave interrupts */ -/*@{*/ - -/*! - * @brief Enables the LPI2C slave interrupt requests. - * - * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as - * interrupts. - * - * @param base The LPI2C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_slave_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) -{ - base->SIER |= interruptMask; -} - -/*! - * @brief Disables the LPI2C slave interrupt requests. - * - * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as - * interrupts. - * - * @param base The LPI2C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_slave_flags for the set - * of constants that should be OR'd together to form the bit mask. - */ -static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) -{ - base->SIER &= ~interruptMask; -} - -/*! - * @brief Returns the set of currently enabled LPI2C slave interrupt requests. - * @param base The LPI2C peripheral base address. - * @return A bitmask composed of #_lpi2c_slave_flags enumerators OR'd together to indicate the - * set of enabled interrupts. - */ -static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base) -{ - return base->SIER; -} - -/*@}*/ - -/*! @name Slave DMA control */ -/*@{*/ - -/*! - * @brief Enables or disables the LPI2C slave peripheral DMA requests. - * - * @param base The LPI2C peripheral base address. - * @param enableAddressValid Enable flag for the address valid DMA request. Pass true for enable, false for disable. - * The address valid DMA request is shared with the receive data DMA request. - * @param enableRx Enable flag for the receive data DMA request. Pass true for enable, false for disable. - * @param enableTx Enable flag for the transmit data DMA request. Pass true for enable, false for disable. - */ -static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx) -{ - base->SDER = (base->SDER & ~(LPI2C_SDER_AVDE_MASK | LPI2C_SDER_RDDE_MASK | LPI2C_SDER_TDDE_MASK)) | - LPI2C_SDER_AVDE(enableAddressValid) | LPI2C_SDER_RDDE(enableRx) | LPI2C_SDER_TDDE(enableTx); -} - -/*@}*/ - -/*! @name Slave bus operations */ -/*@{*/ - -/*! - * @brief Returns whether the bus is idle. - * - * Requires the slave mode to be enabled. - * - * @param base The LPI2C peripheral base address. - * @retval true Bus is busy. - * @retval false Bus is idle. - */ -static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base) -{ - return (base->SSR & LPI2C_SSR_BBF_MASK) >> LPI2C_SSR_BBF_SHIFT; -} - -/*! - * @brief Transmits either an ACK or NAK on the I2C bus in response to a byte from the master. - * - * Use this function to send an ACK or NAK when the #kLPI2C_SlaveTransmitAckFlag is asserted. This - * only happens if you enable the sclStall.enableAck field of the ::lpi2c_slave_config_t configuration - * structure used to initialize the slave peripheral. - * - * @param base The LPI2C peripheral base address. - * @param ackOrNack Pass true for an ACK or false for a NAK. - */ -static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack) -{ - base->STAR = LPI2C_STAR_TXNACK(!ackOrNack); -} - -/*! - * @brief Returns the slave address sent by the I2C master. - * - * This function should only be called if the #kLPI2C_SlaveAddressValidFlag is asserted. - * - * @param base The LPI2C peripheral base address. - * @return The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and - * the 7-bit slave address is in the upper 7 bits. - */ -static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base) -{ - return base->SASR & LPI2C_SASR_RADDR_MASK; -} - -/*! - * @brief Performs a polling send transfer on the I2C bus. - * - * @param base The LPI2C peripheral base address. - * @param txBuff The pointer to the data to be transferred. - * @param txSize The length in bytes of the data to be transferred. - * @param[out] actualTxSize - * @return Error or success status returned by API. - */ -status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, size_t *actualTxSize); - -/*! - * @brief Performs a polling receive transfer on the I2C bus. - * - * @param base The LPI2C peripheral base address. - * @param rxBuff The pointer to the data to be transferred. - * @param rxSize The length in bytes of the data to be transferred. - * @param[out] actualRxSize - * @return Error or success status returned by API. - */ -status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize); - -/*@}*/ - -/*! @name Slave non-blocking */ -/*@{*/ - -/*! - * @brief Creates a new handle for the LPI2C slave non-blocking APIs. - * - * The creation of a handle is for use with the non-blocking APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. - * - * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice - * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to - * enable the associated INTMUX IRQ in application. - - * @param base The LPI2C peripheral base address. - * @param[out] handle Pointer to the LPI2C slave driver handle. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, - lpi2c_slave_handle_t *handle, - lpi2c_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to - * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. - * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need - * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and - * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as - * a convenient way to enable all events. - * - * @param base The LPI2C peripheral base address. - * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. - * @param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify - * which events to send to the callback. Other accepted values are 0 to get a default set of - * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. - * - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. - */ -status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask); - -/*! - * @brief Gets the slave transfer status during a non-blocking transfer. - * @param base The LPI2C peripheral base address. - * @param handle Pointer to i2c_slave_handle_t structure. - * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not - * required. - * @retval #kStatus_Success - * @retval #kStatus_NoTransferInProgress - */ -status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count); - -/*! - * @brief Aborts the slave non-blocking transfers. - * @note This API could be called at any time to stop slave for handling the bus events. - * @param base The LPI2C peripheral base address. - * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. - * @retval #kStatus_Success - * @retval #kStatus_LPI2C_Idle - */ -void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle); - -/*@}*/ - -/*! @name Slave IRQ handler */ -/*@{*/ - -/*! - * @brief Reusable routine to handle slave interrupts. - * @note This function does not need to be called unless you are reimplementing the - * non blocking API's interrupt handler routines to add special functionality. - * @param base The LPI2C peripheral base address. - * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. - */ -void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle); - -/*@}*/ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_LPI2C_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c_edma.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c_edma.c deleted file mode 100644 index b79dea63a1..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c_edma.c +++ /dev/null @@ -1,486 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_lpi2c_edma.h" -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpi2c_edma" -#endif - -/* @brief Mask to align an address to 32 bytes. */ -#define ALIGN_32_MASK (0x1fU) - -/*! @brief Common sets of flags used by the driver. */ -enum _lpi2c_flag_constants -{ - /*! All flags which are cleared by the driver upon starting a transfer. */ - kMasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | - kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag | - kLPI2C_MasterDataMatchFlag, - - /*! IRQ sources enabled by the non-blocking transactional API. */ - kMasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | - kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | - kLPI2C_MasterFifoErrFlag, - - /*! Errors to check for. */ - kMasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | - kLPI2C_MasterPinLowTimeoutFlag, - - /*! All flags which are cleared by the driver upon starting a transfer. */ - kSlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag | - kLPI2C_SlaveFifoErrFlag, - - /*! IRQ sources enabled by the non-blocking transactional API. */ - kSlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | - kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | - kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, - - /*! Errors to check for. */ - kSlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag, -}; - -/* ! @brief LPI2C master fifo commands. */ -enum _lpi2c_master_fifo_cmd -{ - kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ - kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ - kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ - kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ -}; - -/*! @brief States for the state machine used by transactional APIs. */ -enum _lpi2c_transfer_states -{ - kIdleState = 0, - kSendCommandState, - kIssueReadCommandState, - kTransferDataState, - kStopState, - kWaitForCompletionState, -}; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*lpi2c_isr_t)(LPI2C_Type *base, void *handle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle); - -static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds); - -/******************************************************************************* - * Code - ******************************************************************************/ - -void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, - lpi2c_master_edma_handle_t *handle, - edma_handle_t *rxDmaHandle, - edma_handle_t *txDmaHandle, - lpi2c_master_edma_transfer_callback_t callback, - void *userData) -{ - assert(handle); - assert(rxDmaHandle); - assert(txDmaHandle); - - /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set up the handle. For combined rx/tx DMA requests, the tx channel handle is set to the rx handle */ - /* in order to make the transfer API code simpler. */ - handle->base = base; - handle->completionCallback = callback; - handle->userData = userData; - handle->rx = rxDmaHandle; - handle->tx = FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) ? txDmaHandle : rxDmaHandle; - - /* Set DMA channel completion callbacks. */ - EDMA_SetCallback(handle->rx, LPI2C_MasterEDMACallback, handle); - if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_SetCallback(handle->tx, LPI2C_MasterEDMACallback, handle); - } -} - -/*! - * @brief Prepares the command buffer with the sequence of commands needed to send the requested transaction. - * @param handle Master DMA driver handle. - * @return Number of command words. - */ -static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle) -{ - lpi2c_master_transfer_t *xfer = &handle->transfer; - uint16_t *cmd = (uint16_t *)&handle->commandBuffer; - uint32_t cmdCount = 0; - - /* Handle no start option. */ - if (xfer->flags & kLPI2C_TransferNoStartFlag) - { - if (xfer->direction == kLPI2C_Read) - { - /* Need to issue read command first. */ - cmd[cmdCount++] = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); - } - } - else - { - /* - * Initial direction depends on whether a subaddress was provided, and of course the actual - * data transfer direction. - */ - lpi2c_direction_t direction = xfer->subaddressSize ? kLPI2C_Write : xfer->direction; - - /* Start command. */ - cmd[cmdCount++] = - (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); - - /* Subaddress, MSB first. */ - if (xfer->subaddressSize) - { - uint32_t subaddressRemaining = xfer->subaddressSize; - while (subaddressRemaining--) - { - uint8_t subaddressByte = (xfer->subaddress >> (8 * subaddressRemaining)) & 0xff; - cmd[cmdCount++] = subaddressByte; - } - } - - /* Reads need special handling because we have to issue a read command and maybe a repeated start. */ - if ((xfer->dataSize) && (xfer->direction == kLPI2C_Read)) - { - /* Need to send repeated start if switching directions to read. */ - if (direction == kLPI2C_Write) - { - cmd[cmdCount++] = (uint16_t)kStartCmd | - (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); - } - - /* Read command. */ - cmd[cmdCount++] = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); - } - } - - return cmdCount; -} - -status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, - lpi2c_master_edma_handle_t *handle, - lpi2c_master_transfer_t *transfer) -{ - status_t result; - - assert(handle); - assert(transfer); - assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); - - /* Return busy if another transaction is in progress. */ - if (handle->isBusy) - { - return kStatus_LPI2C_Busy; - } - - /* Return an error if the bus is already in use not by us. */ - result = LPI2C_CheckForBusyBus(base); - if (result) - { - return result; - } - - /* We're now busy. */ - handle->isBusy = true; - - /* Disable LPI2C IRQ and DMA sources while we configure stuff. */ - LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); - LPI2C_MasterEnableDMA(base, false, false); - - /* Clear all flags. */ - LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); - - /* Save transfer into handle. */ - handle->transfer = *transfer; - - /* Generate commands to send. */ - uint32_t commandCount = LPI2C_GenerateCommands(handle); - - /* If the user is transmitting no data with no start or stop, then just go ahead and invoke the callback. */ - if ((!commandCount) && (transfer->dataSize == 0)) - { - if (handle->completionCallback) - { - handle->completionCallback(base, handle, kStatus_Success, handle->userData); - } - return kStatus_Success; - } - - /* Reset DMA channels. */ - EDMA_ResetChannel(handle->rx->base, handle->rx->channel); - if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_ResetChannel(handle->tx->base, handle->tx->channel); - } - - /* Get a 32-byte aligned TCD pointer. */ - edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_32_MASK)); - - bool hasSendData = (transfer->direction == kLPI2C_Write) && (transfer->dataSize); - bool hasReceiveData = (transfer->direction == kLPI2C_Read) && (transfer->dataSize); - - edma_transfer_config_t transferConfig; - edma_tcd_t *linkTcd = NULL; - - /* Set up data transmit. */ - if (hasSendData) - { - transferConfig.srcAddr = (uint32_t)transfer->data; - transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); - transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfig.srcOffset = sizeof(uint8_t); - transferConfig.destOffset = 0; - transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to fill fifo */ - transferConfig.majorLoopCounts = transfer->dataSize; - - /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ - handle->nbytes = transferConfig.minorLoopBytes; - - if (commandCount) - { - /* Create a software TCD, which will be chained after the commands. */ - EDMA_TcdReset(tcd); - EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); - EDMA_TcdEnableInterrupts(tcd, kEDMA_MajorInterruptEnable); - linkTcd = tcd; - } - else - { - /* User is only transmitting data with no required commands, so this transfer can stand alone. */ - EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, NULL); - EDMA_EnableChannelInterrupts(handle->tx->base, handle->tx->channel, kEDMA_MajorInterruptEnable); - } - } - else if (hasReceiveData) - { - /* Set up data receive. */ - transferConfig.srcAddr = (uint32_t)LPI2C_MasterGetRxFifoAddress(base); - transferConfig.destAddr = (uint32_t)transfer->data; - transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfig.srcOffset = 0; - transferConfig.destOffset = sizeof(uint8_t); - transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to empty fifo */ - transferConfig.majorLoopCounts = transfer->dataSize; - - /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ - handle->nbytes = transferConfig.minorLoopBytes; - - if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) || (!commandCount)) - { - /* We can put this receive transfer on its own DMA channel. */ - EDMA_SetTransferConfig(handle->rx->base, handle->rx->channel, &transferConfig, NULL); - EDMA_EnableChannelInterrupts(handle->rx->base, handle->rx->channel, kEDMA_MajorInterruptEnable); - } - else - { - /* For shared rx/tx DMA requests when there are commands, create a software TCD which will be */ - /* chained onto the commands transfer, notice that in this situation assume tx/rx uses same channel */ - EDMA_TcdReset(tcd); - EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); - EDMA_TcdEnableInterrupts(tcd, kEDMA_MajorInterruptEnable); - linkTcd = tcd; - } - } - else - { - /* No data to send */ - } - - /* Set up commands transfer. */ - if (commandCount) - { - transferConfig.srcAddr = (uint32_t)handle->commandBuffer; - transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); - transferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; - transferConfig.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfig.srcOffset = sizeof(uint16_t); - transferConfig.destOffset = 0; - transferConfig.minorLoopBytes = sizeof(uint16_t); /* TODO optimize to fill fifo */ - transferConfig.majorLoopCounts = commandCount; - - EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, linkTcd); - } - - /* Start DMA transfer. */ - if (hasReceiveData || !FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_StartTransfer(handle->rx); - } - - if (hasReceiveData && !FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_EnableChannelInterrupts(handle->tx->base, handle->tx->channel, kEDMA_MajorInterruptEnable); - } - - if ((hasSendData || commandCount) && FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_StartTransfer(handle->tx); - } - - /* Enable DMA in both directions. This actually kicks of the transfer. */ - LPI2C_MasterEnableDMA(base, true, true); - - return result; -} - -status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - uint32_t remaining = handle->transfer.dataSize; - - /* If the DMA is still on a commands transfer that chains to the actual data transfer, */ - /* we do nothing and return the number of transferred bytes as zero. */ - if (EDMA_GetNextTCDAddress(handle->tx) == 0) - { - if (handle->transfer.direction == kLPI2C_Write) - { - remaining = - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->tx->base, handle->tx->channel); - } - else - { - remaining = - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->rx->base, handle->rx->channel); - } - } - - *count = handle->transfer.dataSize - remaining; - - return kStatus_Success; -} - -status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle) -{ - /* Catch when there is not an active transfer. */ - if (!handle->isBusy) - { - return kStatus_LPI2C_Idle; - } - - /* Terminate DMA transfers. */ - EDMA_AbortTransfer(handle->rx); - if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - EDMA_AbortTransfer(handle->tx); - } - - /* Reset fifos. */ - base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; - - /* Send a stop command to finalize the transfer. */ - base->MTDR = kStopCmd; - - /* Reset handle. */ - handle->isBusy = false; - - return kStatus_Success; -} - -/*! - * @brief DMA completion callback. - * @param dmaHandle DMA channel handle for the channel that completed. - * @param userData User data associated with the channel handle. For this callback, the user data is the - * LPI2C DMA driver handle. - * @param isTransferDone Whether the DMA transfer has completed. - * @param tcds Number of TCDs that completed. - */ -static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds) -{ - lpi2c_master_edma_handle_t *handle = (lpi2c_master_edma_handle_t *)userData; - bool hasReceiveData; - - if (!handle) - { - return; - } - - hasReceiveData = (handle->transfer.direction == kLPI2C_Read) && (handle->transfer.dataSize); - - if (hasReceiveData && !FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) - { - if (EDMA_GetNextTCDAddress(handle->tx) != 0) - { - LPI2C_MasterEnableDMA(handle->base, false, true); - } - } - - /* Check for errors. */ - status_t result = LPI2C_MasterCheckAndClearError(handle->base, LPI2C_MasterGetStatusFlags(handle->base)); - - /* Done with this transaction. */ - handle->isBusy = false; - - if (!(handle->transfer.flags & kLPI2C_TransferNoStopFlag)) - { - /* Send a stop command to finalize the transfer. */ - handle->base->MTDR = kStopCmd; - } - - /* Invoke callback. */ - if (handle->completionCallback) - { - handle->completionCallback(handle->base, handle, result, handle->userData); - } -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c_edma.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c_edma.h deleted file mode 100644 index b66edbfd4b..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c_edma.h +++ /dev/null @@ -1,183 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LPI2C_EDMA_H_ -#define _FSL_LPI2C_EDMA_H_ - -#include "fsl_lpi2c.h" -#include "fsl_edma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPI2C EDMA driver version 2.1.5. */ -#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) -/*@}*/ - -/*! - * @addtogroup lpi2c_master_edma_driver - * @{ - */ - -/* Forward declaration of the transfer descriptor and handle typedefs. */ -typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t; - -/*! - * @brief Master DMA completion callback function pointer type. - * - * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use - * in the call to LPI2C_MasterCreateEDMAHandle(). - * - * @param base The LPI2C peripheral base address. - * @param handle Handle associated with the completed transfer. - * @param completionStatus Either #kStatus_Success or an error code describing how the transfer completed. - * @param userData Arbitrary pointer-sized value passed from the application. - */ -typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, - lpi2c_master_edma_handle_t *handle, - status_t completionStatus, - void *userData); - -/*! - * @brief Driver handle for master DMA APIs. - * @note The contents of this structure are private and subject to change. - */ -struct _lpi2c_master_edma_handle -{ - LPI2C_Type *base; /*!< LPI2C base pointer. */ - bool isBusy; /*!< Transfer state machine current state. */ - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - uint16_t commandBuffer[7]; /*!< LPI2C command sequence. */ - lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ - lpi2c_master_edma_transfer_callback_t completionCallback; /*!< Callback function pointer. */ - void *userData; /*!< Application data passed to callback. */ - edma_handle_t *rx; /*!< Handle for receive DMA channel. */ - edma_handle_t *tx; /*!< Handle for transmit DMA channel. */ - edma_tcd_t tcds[2]; /*!< Software TCD. Two are allocated to provide enough room to align to 32-bytes. */ -}; - -/*! @} */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @addtogroup lpi2c_master_edma_driver - * @{ - */ - -/*! @name Master DMA */ -/*@{*/ - -/*! - * @brief Create a new handle for the LPI2C master DMA APIs. - * - * The creation of a handle is for use with the DMA APIs. Once a handle - * is created, there is not a corresponding destroy handle. If the user wants to - * terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called. - * - * For devices where the LPI2C send and receive DMA requests are OR'd together, the @a txDmaHandle - * parameter is ignored and may be set to NULL. - * - * @param base The LPI2C peripheral base address. - * @param[out] handle Pointer to the LPI2C master driver handle. - * @param rxDmaHandle Handle for the eDMA receive channel. Created by the user prior to calling this function. - * @param txDmaHandle Handle for the eDMA transmit channel. Created by the user prior to calling this function. - * @param callback User provided pointer to the asynchronous callback function. - * @param userData User provided pointer to the application callback data. - */ -void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, - lpi2c_master_edma_handle_t *handle, - edma_handle_t *rxDmaHandle, - edma_handle_t *txDmaHandle, - lpi2c_master_edma_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs a non-blocking DMA-based transaction on the I2C bus. - * - * The callback specified when the @a handle was created is invoked when the transaction has - * completed. - * - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - * @param transfer The pointer to the transfer descriptor. - * @retval #kStatus_Success The transaction was started successfully. - * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or another DMA - * transaction is already in progress. - */ -status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, - lpi2c_master_edma_handle_t *handle, - lpi2c_master_transfer_t *transfer); - -/*! - * @brief Returns number of bytes transferred so far. - * - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - * @param[out] count Number of bytes transferred so far by the non-blocking transaction. - * @retval #kStatus_Success - * @retval #kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. - */ -status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count); - -/*! - * @brief Terminates a non-blocking LPI2C master transmission early. - * - * @note It is not safe to call this function from an IRQ handler that has a higher priority than the - * eDMA peripheral's IRQ priority. - * - * @param base The LPI2C peripheral base address. - * @param handle Pointer to the LPI2C master driver handle. - * @retval #kStatus_Success A transaction was successfully aborted. - * @retval #kStatus_LPI2C_Idle There is not a DMA transaction currently in progress. - */ -status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle); - -/*@}*/ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_LPI2C_EDMA_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi.c deleted file mode 100644 index 3a515e1739..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi.c +++ /dev/null @@ -1,1851 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_lpspi.h" - -/******************************************************************************* -* Definitions -******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpspi" -#endif - -/*! - * @brief Default watermark values. - * - * The default watermarks are set to zero. - */ -enum _lpspi_default_watermarks -{ - kLpspiDefaultTxWatermark = 0, - kLpspiDefaultRxWatermark = 0, -}; - -/*! @brief Typedef for master interrupt handler. */ -typedef void (*lpspi_master_isr_t)(LPSPI_Type *base, lpspi_master_handle_t *handle); - -/*! @brief Typedef for slave interrupt handler. */ -typedef void (*lpspi_slave_isr_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle); - -/******************************************************************************* -* Prototypes -******************************************************************************/ - -/*! -* @brief Configures the LPSPI peripheral chip select polarity. -* -* This function takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and -* configures the Pcs signal to operate with the desired characteristic. -* -* @param base LPSPI peripheral address. -* @param pcs The particular peripheral chip select (parameter value is of type lpspi_which_pcs_t) for which we wish to -* apply the active high or active low characteristic. -* @param activeLowOrHigh The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of -* type lpspi_pcs_polarity_config_t. -*/ -static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, - lpspi_which_pcs_t pcs, - lpspi_pcs_polarity_config_t activeLowOrHigh); - -/*! -* @brief Combine the write data for 1 byte to 4 bytes. -* This is not a public API. -*/ -static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint32_t bytesEachWrite, bool isByteSwap); - -/*! -* @brief Separate the read data for 1 byte to 4 bytes. -* This is not a public API. -*/ -static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); - -/*! -* @brief Master fill up the TX FIFO with data. -* This is not a public API. -*/ -static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle); - -/*! -* @brief Master finish up a transfer. -* It would call back if there is callback function and set the state to idle. -* This is not a public API. -*/ -static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle); - -/*! -* @brief Slave fill up the TX FIFO with data. -* This is not a public API. -*/ -static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle); - -/*! -* @brief Slave finish up a transfer. -* It would call back if there is callback function and set the state to idle. -* This is not a public API. -*/ -static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle); - -/*! -* @brief LPSPI common interrupt handler. -* -* @param handle pointer to s_lpspiHandle which stores the transfer state. -*/ -static void LPSPI_CommonIRQHandler(LPSPI_Type *base, void *param); - -/******************************************************************************* -* Variables -******************************************************************************/ - -/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ -static const uint8_t s_baudratePrescaler[] = {1, 2, 4, 8, 16, 32, 64, 128}; - -/*! @brief Pointers to lpspi bases for each instance. */ -static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS; - -/*! @brief Pointers to lpspi IRQ number for each instance. */ -static const IRQn_Type s_lpspiIRQ[] = LPSPI_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to lpspi clocks for each instance. */ -static const clock_ip_name_t s_lpspiClocks[] = LPSPI_CLOCKS; - -#if defined(LPSPI_PERIPH_CLOCKS) -static const clock_ip_name_t s_LpspiPeriphClocks[] = LPSPI_PERIPH_CLOCKS; -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to lpspi handles for each instance. */ -static void *s_lpspiHandle[ARRAY_SIZE(s_lpspiBases)] = {NULL}; - -/*! @brief Pointer to master IRQ handler for each instance. */ -static lpspi_master_isr_t s_lpspiMasterIsr; -/*! @brief Pointer to slave IRQ handler for each instance. */ -static lpspi_slave_isr_t s_lpspiSlaveIsr; -/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ -volatile uint8_t g_lpspiDummyData[ARRAY_SIZE(s_lpspiBases)] = {0}; -/********************************************************************************************************************** -* Code -*********************************************************************************************************************/ -uint32_t LPSPI_GetInstance(LPSPI_Type *base) -{ - uint8_t instance = 0; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_lpspiBases); instance++) - { - if (s_lpspiBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_lpspiBases)); - - return instance; -} - -void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData) -{ - uint32_t instance = LPSPI_GetInstance(base); - g_lpspiDummyData[instance] = dummyData; -} - -void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz) -{ - assert(masterConfig); - - uint32_t tcrPrescaleValue = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPSPI_GetInstance(base); - /* Enable LPSPI clock */ - CLOCK_EnableClock(s_lpspiClocks[instance]); - -#if defined(LPSPI_PERIPH_CLOCKS) - CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset to known status */ - LPSPI_Reset(base); - - /* Set LPSPI to master */ - LPSPI_SetMasterSlaveMode(base, kLPSPI_Master); - - /* Set specific PCS to active high or low */ - LPSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow); - - /* Set Configuration Register 1 related setting.*/ - base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK)) | - LPSPI_CFGR1_OUTCFG(masterConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(masterConfig->pinCfg) | - LPSPI_CFGR1_NOSTALL(0); - - /* Set baudrate and delay times*/ - LPSPI_MasterSetBaudRate(base, masterConfig->baudRate, srcClock_Hz, &tcrPrescaleValue); - - /* Set default watermarks */ - LPSPI_SetFifoWatermarks(base, kLpspiDefaultTxWatermark, kLpspiDefaultRxWatermark); - - /* Set Transmit Command Register*/ - base->TCR = LPSPI_TCR_CPOL(masterConfig->cpol) | LPSPI_TCR_CPHA(masterConfig->cpha) | - LPSPI_TCR_LSBF(masterConfig->direction) | LPSPI_TCR_FRAMESZ(masterConfig->bitsPerFrame - 1) | - LPSPI_TCR_PRESCALE(tcrPrescaleValue) | LPSPI_TCR_PCS(masterConfig->whichPcs); - - LPSPI_Enable(base, true); - - LPSPI_MasterSetDelayTimes(base, masterConfig->pcsToSckDelayInNanoSec, kLPSPI_PcsToSck, srcClock_Hz); - LPSPI_MasterSetDelayTimes(base, masterConfig->lastSckToPcsDelayInNanoSec, kLPSPI_LastSckToPcs, srcClock_Hz); - LPSPI_MasterSetDelayTimes(base, masterConfig->betweenTransferDelayInNanoSec, kLPSPI_BetweenTransfer, srcClock_Hz); - - LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); -} - -void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) -{ - assert(masterConfig); - - masterConfig->baudRate = 500000; - masterConfig->bitsPerFrame = 8; - masterConfig->cpol = kLPSPI_ClockPolarityActiveHigh; - masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge; - masterConfig->direction = kLPSPI_MsbFirst; - - masterConfig->pcsToSckDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; - masterConfig->lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; - masterConfig->betweenTransferDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; - - masterConfig->whichPcs = kLPSPI_Pcs0; - masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; - - masterConfig->pinCfg = kLPSPI_SdiInSdoOut; - masterConfig->dataOutConfig = kLpspiDataOutRetained; -} - -void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig) -{ - assert(slaveConfig); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPSPI_GetInstance(base); - /* Enable LPSPI clock */ - CLOCK_EnableClock(s_lpspiClocks[instance]); - -#if defined(LPSPI_PERIPH_CLOCKS) - CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset to known status */ - LPSPI_Reset(base); - - LPSPI_SetMasterSlaveMode(base, kLPSPI_Slave); - - LPSPI_SetOnePcsPolarity(base, slaveConfig->whichPcs, slaveConfig->pcsActiveHighOrLow); - - base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK)) | - LPSPI_CFGR1_OUTCFG(slaveConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(slaveConfig->pinCfg); - - LPSPI_SetFifoWatermarks(base, kLpspiDefaultTxWatermark, kLpspiDefaultRxWatermark); - - base->TCR = LPSPI_TCR_CPOL(slaveConfig->cpol) | LPSPI_TCR_CPHA(slaveConfig->cpha) | - LPSPI_TCR_LSBF(slaveConfig->direction) | LPSPI_TCR_FRAMESZ(slaveConfig->bitsPerFrame - 1); - - /* This operation will set the dummy data for edma transfer, no effect in interrupt way. */ - LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); - - LPSPI_Enable(base, true); -} - -void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig) -{ - assert(slaveConfig); - - slaveConfig->bitsPerFrame = 8; /*!< Bits per frame, minimum 8, maximum 4096.*/ - slaveConfig->cpol = kLPSPI_ClockPolarityActiveHigh; /*!< Clock polarity. */ - slaveConfig->cpha = kLPSPI_ClockPhaseFirstEdge; /*!< Clock phase. */ - slaveConfig->direction = kLPSPI_MsbFirst; /*!< MSB or LSB data shift direction. */ - - slaveConfig->whichPcs = kLPSPI_Pcs0; /*!< Desired Peripheral Chip Select (pcs) */ - slaveConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; /*!< Desired PCS active high or low */ - - slaveConfig->pinCfg = kLPSPI_SdiInSdoOut; - slaveConfig->dataOutConfig = kLpspiDataOutRetained; -} - -void LPSPI_Reset(LPSPI_Type *base) -{ - /* Reset all internal logic and registers, except the Control Register. Remains set until cleared by software.*/ - base->CR |= LPSPI_CR_RST_MASK; - - /* Software reset doesn't reset the CR, so manual reset the FIFOs */ - base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK; - - /* Master logic is not reset and module is disabled.*/ - base->CR = 0x00U; -} - -void LPSPI_Deinit(LPSPI_Type *base) -{ - /* Reset to default value */ - LPSPI_Reset(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPSPI_GetInstance(base); - /* Enable LPSPI clock */ - CLOCK_DisableClock(s_lpspiClocks[instance]); - -#if defined(LPSPI_PERIPH_CLOCKS) - CLOCK_DisableClock(s_LpspiPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, - lpspi_which_pcs_t pcs, - lpspi_pcs_polarity_config_t activeLowOrHigh) -{ - uint32_t cfgr1Value = 0; - /* Clear the PCS polarity bit */ - cfgr1Value = base->CFGR1 & ~(1U << (LPSPI_CFGR1_PCSPOL_SHIFT + pcs)); - - /* Configure the PCS polarity bit according to the activeLowOrHigh setting */ - base->CFGR1 = cfgr1Value | ((uint32_t)activeLowOrHigh << (LPSPI_CFGR1_PCSPOL_SHIFT + pcs)); -} - -uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, - uint32_t baudRate_Bps, - uint32_t srcClock_Hz, - uint32_t *tcrPrescaleValue) -{ - assert(tcrPrescaleValue); - - /* For master mode configuration only, if slave mode detected, return 0. - * Also, the LPSPI module needs to be disabled first, if enabled, return 0 - */ - if ((!LPSPI_IsMaster(base)) || (base->CR & LPSPI_CR_MEN_MASK)) - { - return 0; - } - - uint32_t prescaler, bestPrescaler; - uint32_t scaler, bestScaler; - uint32_t realBaudrate, bestBaudrate; - uint32_t diff, min_diff; - uint32_t desiredBaudrate = baudRate_Bps; - - /* find combination of prescaler and scaler resulting in baudrate closest to the - * requested value - */ - min_diff = 0xFFFFFFFFU; - - /* Set to maximum divisor value bit settings so that if baud rate passed in is less - * than the minimum possible baud rate, then the SPI will be configured to the lowest - * possible baud rate - */ - bestPrescaler = 7; - bestScaler = 255; - - bestBaudrate = 0; /* required to avoid compilation warning */ - - /* In all for loops, if min_diff = 0, the exit for loop*/ - for (prescaler = 0; (prescaler < 8) && min_diff; prescaler++) - { - for (scaler = 0; (scaler < 256) && min_diff; scaler++) - { - realBaudrate = (srcClock_Hz / (s_baudratePrescaler[prescaler] * (scaler + 2U))); - - /* calculate the baud rate difference based on the conditional statement - * that states that the calculated baud rate must not exceed the desired baud rate - */ - if (desiredBaudrate >= realBaudrate) - { - diff = desiredBaudrate - realBaudrate; - if (min_diff > diff) - { - /* a better match found */ - min_diff = diff; - bestPrescaler = prescaler; - bestScaler = scaler; - bestBaudrate = realBaudrate; - } - } - } - } - - /* Write the best baud rate scalar to the CCR. - * Note, no need to check for error since we've already checked to make sure the module is - * disabled and in master mode. Also, there is a limit on the maximum divider so we will not - * exceed this. - */ - base->CCR = (base->CCR & ~LPSPI_CCR_SCKDIV_MASK) | LPSPI_CCR_SCKDIV(bestScaler); - - /* return the best prescaler value for user to use later */ - *tcrPrescaleValue = bestPrescaler; - - /* return the actual calculated baud rate */ - return bestBaudrate; -} - -void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay) -{ - /*These settings are only relevant in master mode */ - switch (whichDelay) - { - case kLPSPI_PcsToSck: - base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler); - - break; - case kLPSPI_LastSckToPcs: - base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler); - - break; - case kLPSPI_BetweenTransfer: - base->CCR = (base->CCR & (~LPSPI_CCR_DBT_MASK)) | LPSPI_CCR_DBT(scaler); - - break; - default: - assert(false); - break; - } -} - -uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, - uint32_t delayTimeInNanoSec, - lpspi_delay_type_t whichDelay, - uint32_t srcClock_Hz) -{ - uint64_t realDelay, bestDelay; - uint32_t scaler, bestScaler; - uint32_t diff, min_diff; - uint64_t initialDelayNanoSec; - uint32_t clockDividedPrescaler; - - /* For delay between transfer, an additional scaler value is needed */ - uint32_t additionalScaler = 0; - - /*As the RM note, the LPSPI baud rate clock is itself divided by the PRESCALE setting, which can vary between - * transfers.*/ - clockDividedPrescaler = - srcClock_Hz / s_baudratePrescaler[(base->TCR & LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIFT]; - - /* Find combination of prescaler and scaler resulting in the delay closest to the requested value.*/ - min_diff = 0xFFFFFFFFU; - - /* Initialize scaler to max value to generate the max delay */ - bestScaler = 0xFFU; - - /* Calculate the initial (min) delay and maximum possible delay based on the specific delay as - * the delay divisors are slightly different based on which delay we are configuring. - */ - if (whichDelay == kLPSPI_BetweenTransfer) - { - /* First calculate the initial, default delay, note min delay is 2 clock cycles. Due to large size of - calculated values (uint64_t), we need to break up the calculation into several steps to ensure - accurate calculated results - */ - initialDelayNanoSec = 1000000000U; - initialDelayNanoSec *= 2U; - initialDelayNanoSec /= clockDividedPrescaler; - - /* Calculate the maximum delay */ - bestDelay = 1000000000U; - bestDelay *= 257U; /* based on DBT+2, or 255 + 2 */ - bestDelay /= clockDividedPrescaler; - - additionalScaler = 1U; - } - else - { - /* First calculate the initial, default delay, min delay is 1 clock cycle. Due to large size of calculated - values (uint64_t), we need to break up the calculation into several steps to ensure accurate calculated - results. - */ - initialDelayNanoSec = 1000000000U; - initialDelayNanoSec /= clockDividedPrescaler; - - /* Calculate the maximum delay */ - bestDelay = 1000000000U; - bestDelay *= 256U; /* based on SCKPCS+1 or PCSSCK+1, or 255 + 1 */ - bestDelay /= clockDividedPrescaler; - - additionalScaler = 0; - } - - /* If the initial, default delay is already greater than the desired delay, then - * set the delay to their initial value (0) and return the delay. In other words, - * there is no way to decrease the delay value further. - */ - if (initialDelayNanoSec >= delayTimeInNanoSec) - { - LPSPI_MasterSetDelayScaler(base, 0, whichDelay); - return initialDelayNanoSec; - } - - /* If min_diff = 0, the exit for loop */ - for (scaler = 0; (scaler < 256U) && min_diff; scaler++) - { - /* Calculate the real delay value as we cycle through the scaler values. - Due to large size of calculated values (uint64_t), we need to break up the - calculation into several steps to ensure accurate calculated results - */ - realDelay = 1000000000U; - realDelay *= (scaler + 1 + additionalScaler); - realDelay /= clockDividedPrescaler; - - /* calculate the delay difference based on the conditional statement - * that states that the calculated delay must not be less then the desired delay - */ - if (realDelay >= delayTimeInNanoSec) - { - diff = realDelay - delayTimeInNanoSec; - if (min_diff > diff) - { - /* a better match found */ - min_diff = diff; - bestScaler = scaler; - bestDelay = realDelay; - } - } - } - - /* write the best scaler value for the delay */ - LPSPI_MasterSetDelayScaler(base, bestScaler, whichDelay); - - /* return the actual calculated delay value (in ns) */ - return bestDelay; -} - -/*Transactional APIs -- Master*/ - -void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, - lpspi_master_handle_t *handle, - lpspi_master_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - s_lpspiHandle[LPSPI_GetInstance(base)] = handle; - - /* Set irq handler. */ - s_lpspiMasterIsr = LPSPI_MasterTransferHandleIRQ; - - handle->callback = callback; - handle->userData = userData; -} - -bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame) -{ - assert(transfer); - - /* If the transfer count is zero, then return immediately.*/ - if (transfer->dataSize == 0) - { - return false; - } - - /* If both send buffer and receive buffer is null */ - if ((!(transfer->txData)) && (!(transfer->rxData))) - { - return false; - } - - /*The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4 . - *For bytesPerFrame greater than 4 situation: - *the transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4 , - *otherwise , the transfer data size can be integer multiples of bytesPerFrame. - */ - if (bytesPerFrame <= 4) - { - if ((transfer->dataSize % bytesPerFrame) != 0) - { - return false; - } - } - else - { - if ((bytesPerFrame % 4U) != 0) - { - if (transfer->dataSize != bytesPerFrame) - { - return false; - } - } - else - { - if ((transfer->dataSize % bytesPerFrame) != 0) - { - return false; - } - } - } - - return true; -} - -status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer) -{ - assert(transfer); - - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; - uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - uint32_t temp = 0U; - uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; - - if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) - { - return kStatus_InvalidArgument; - } - - /* Check that LPSPI is not busy.*/ - if (LPSPI_GetStatusFlags(base) & kLPSPI_ModuleBusyFlag) - { - return kStatus_LPSPI_Busy; - } - - uint8_t *txData = transfer->txData; - uint8_t *rxData = transfer->rxData; - uint32_t txRemainingByteCount = transfer->dataSize; - uint32_t rxRemainingByteCount = transfer->dataSize; - - uint8_t bytesEachWrite; - uint8_t bytesEachRead; - - uint32_t readData = 0; - uint32_t wordToSend = - ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); - - /*The TX and RX FIFO sizes are always the same*/ - uint32_t fifoSize = LPSPI_GetRxFifoSize(base); - - uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; - - bool isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); - bool isRxMask = false; - bool isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); - - LPSPI_FlushFifo(base, true, true); - LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); - - if (!rxData) - { - isRxMask = true; - } - - LPSPI_Enable(base, false); - base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); - /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ - temp = base->CFGR1; - temp &= LPSPI_CFGR1_PINCFG_MASK; - if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) - { - if (!txData) - { - base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; - } - /* The 3-wire mode can't send and receive data at the same time. */ - if ((txData) && (rxData)) - { - return kStatus_InvalidArgument; - } - } - LPSPI_Enable(base, true); - - base->TCR = - (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) | - LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_PCS(whichPcs); - - if (bytesPerFrame <= 4) - { - bytesEachWrite = bytesPerFrame; - bytesEachRead = bytesPerFrame; - } - else - { - bytesEachWrite = 4; - bytesEachRead = 4; - } - - /*Write the TX data until txRemainingByteCount is equal to 0 */ - while (txRemainingByteCount > 0) - { - if (txRemainingByteCount < bytesEachWrite) - { - bytesEachWrite = txRemainingByteCount; - } - - /*Wait until TX FIFO is not full*/ - while (LPSPI_GetTxFifoCount(base) == fifoSize) - { - } - - if (txData) - { - wordToSend = LPSPI_CombineWriteData(txData, bytesEachWrite, isByteSwap); - txData += bytesEachWrite; - } - - LPSPI_WriteData(base, wordToSend); - txRemainingByteCount -= bytesEachWrite; - - /*Check whether there is RX data in RX FIFO . Read out the RX data so that the RX FIFO would not overrun.*/ - if (rxData) - { - while (LPSPI_GetRxFifoCount(base)) - { - readData = LPSPI_ReadData(base); - if (rxRemainingByteCount < bytesEachRead) - { - bytesEachRead = rxRemainingByteCount; - } - - LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap); - rxData += bytesEachRead; - - rxRemainingByteCount -= bytesEachRead; - } - } - } - - /* After write all the data in TX FIFO , should write the TCR_CONTC to 0 to de-assert the PCS. Note that TCR - * register also use the TX FIFO. - */ - while ((LPSPI_GetTxFifoCount(base) == fifoSize)) - { - } - base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); - - /*Read out the RX data in FIFO*/ - if (rxData) - { - while (rxRemainingByteCount > 0) - { - while (LPSPI_GetRxFifoCount(base)) - { - readData = LPSPI_ReadData(base); - - if (rxRemainingByteCount < bytesEachRead) - { - bytesEachRead = rxRemainingByteCount; - } - - LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap); - rxData += bytesEachRead; - - rxRemainingByteCount -= bytesEachRead; - } - } - } - else - { - /* If no RX buffer, then transfer is not complete until transfer complete flag sets */ - while (!(LPSPI_GetStatusFlags(base) & kLPSPI_TransferCompleteFlag)) - { - } - } - - return kStatus_Success; -} - -status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; - uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - uint32_t temp = 0U; - uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; - - if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == kLPSPI_Busy) - { - return kStatus_LPSPI_Busy; - } - - handle->state = kLPSPI_Busy; - - bool isRxMask = false; - - uint8_t txWatermark; - - uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; - - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->txRemainingByteCount = transfer->dataSize; - handle->rxRemainingByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - handle->writeTcrInIsr = false; - - handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); - handle->readRegRemainingTimes = handle->writeRegRemainingTimes; - - handle->txBuffIfNull = - ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); - - /*The TX and RX FIFO sizes are always the same*/ - handle->fifoSize = LPSPI_GetRxFifoSize(base); - - handle->isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); - handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); - - /*Set the RX and TX watermarks to reduce the ISR times.*/ - if (handle->fifoSize > 1) - { - txWatermark = 1; - handle->rxWatermark = handle->fifoSize - 2; - } - else - { - txWatermark = 0; - handle->rxWatermark = 0; - } - - LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); - - LPSPI_Enable(base, false); - /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ - base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); - /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ - temp = base->CFGR1; - temp &= LPSPI_CFGR1_PINCFG_MASK; - if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) - { - if (!handle->txData) - { - base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; - } - /* The 3-wire mode can't send and receive data at the same time. */ - if ((handle->txData) && (handle->rxData)) - { - return kStatus_InvalidArgument; - } - } - LPSPI_Enable(base, true); - - /*Flush FIFO , clear status , disable all the inerrupts.*/ - LPSPI_FlushFifo(base, true, true); - LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - /* If there is not rxData , can mask the receive data (receive data is not stored in receive FIFO). - * For master transfer , we'd better not masked the transmit data in TCR since the transfer flow is hard to - * controlled by software.*/ - if (handle->rxData == NULL) - { - isRxMask = true; - handle->rxRemainingByteCount = 0; - } - - base->TCR = - (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) | - LPSPI_TCR_CONT(handle->isPcsContinuous) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | - LPSPI_TCR_PCS(whichPcs); - - /*Calculate the bytes for write/read the TX/RX register each time*/ - if (bytesPerFrame <= 4) - { - handle->bytesEachWrite = bytesPerFrame; - handle->bytesEachRead = bytesPerFrame; - } - else - { - handle->bytesEachWrite = 4; - handle->bytesEachRead = 4; - } - - /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , - * and you should also enable the INTMUX interupt in your application. - */ - EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); - - /*TCR is also shared the FIFO , so wait for TCR written.*/ - while (LPSPI_GetTxFifoCount(base) != 0) - { - } - /*Fill up the TX data in FIFO */ - LPSPI_MasterTransferFillUpTxFifo(base, handle); - - /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. - * The IRQ handler will get the status of RX and TX interrupt flags. - */ - if (handle->rxData) - { - /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there - *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. - */ - if ((handle->readRegRemainingTimes) <= handle->rxWatermark) - { - base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->readRegRemainingTimes - 1); - } - - LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable); - } - else - { - LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable); - } - - return kStatus_Success; -} - -static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle) -{ - assert(handle); - - uint32_t wordToSend = 0; - - /* Make sure the difference in remaining TX and RX byte counts does not exceed FIFO depth - * and that the number of TX FIFO entries does not exceed the FIFO depth. - * But no need to make the protection if there is no rxData. - */ - while ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize)) && - (((handle->readRegRemainingTimes - handle->writeRegRemainingTimes) < handle->fifoSize) || - (handle->rxData == NULL))) - { - if (handle->txRemainingByteCount < handle->bytesEachWrite) - { - handle->bytesEachWrite = handle->txRemainingByteCount; - } - - if (handle->txData) - { - wordToSend = LPSPI_CombineWriteData(handle->txData, handle->bytesEachWrite, handle->isByteSwap); - handle->txData += handle->bytesEachWrite; - } - else - { - wordToSend = handle->txBuffIfNull; - } - - /*Write the word to TX register*/ - LPSPI_WriteData(base, wordToSend); - - /*Decrease the write TX register times.*/ - --handle->writeRegRemainingTimes; - - /*Decrease the remaining TX byte count.*/ - handle->txRemainingByteCount -= handle->bytesEachWrite; - - if (handle->txRemainingByteCount == 0) - { - /* If PCS is continuous, update TCR to de-assert PCS */ - if (handle->isPcsContinuous) - { - /* Only write to the TCR if the FIFO has room */ - if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize))) - { - base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); - handle->writeTcrInIsr = false; - } - /* Else, set a global flag to tell the ISR to do write to the TCR */ - else - { - handle->writeTcrInIsr = true; - } - } - break; - } - } -} - -static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle) -{ - assert(handle); - - /* Disable interrupt requests*/ - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - handle->state = kLPSPI_Idle; - - if (handle->callback) - { - handle->callback(base, handle, kStatus_Success, handle->userData); - } -} - -status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kLPSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t remainingByte; - - if (handle->rxData) - { - remainingByte = handle->rxRemainingByteCount; - } - else - { - remainingByte = handle->txRemainingByteCount; - } - - *count = handle->totalByteCount - remainingByte; - - return kStatus_Success; -} - -void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle) -{ - assert(handle); - - /* Disable interrupt requests*/ - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - LPSPI_Reset(base); - - handle->state = kLPSPI_Idle; - handle->txRemainingByteCount = 0; - handle->rxRemainingByteCount = 0; -} - -void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle) -{ - assert(handle); - - uint32_t readData; - - if (handle->rxData != NULL) - { - if (handle->rxRemainingByteCount) - { - /* First, disable the interrupts to avoid potentially triggering another interrupt - * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll - * re-enable the interrupts based on the LPSPI state after reading out the FIFO. - */ - LPSPI_DisableInterrupts(base, kLPSPI_RxInterruptEnable); - - while ((LPSPI_GetRxFifoCount(base)) && (handle->rxRemainingByteCount)) - { - /*Read out the data*/ - readData = LPSPI_ReadData(base); - - /*Decrease the read RX register times.*/ - --handle->readRegRemainingTimes; - - if (handle->rxRemainingByteCount < handle->bytesEachRead) - { - handle->bytesEachRead = handle->rxRemainingByteCount; - } - - LPSPI_SeparateReadData(handle->rxData, readData, handle->bytesEachRead, handle->isByteSwap); - handle->rxData += handle->bytesEachRead; - - /*Decrease the remaining RX byte count.*/ - handle->rxRemainingByteCount -= handle->bytesEachRead; - } - - /* Re-enable the interrupts only if rxCount indicates there is more data to receive, - * else we may get a spurious interrupt. - * */ - if (handle->rxRemainingByteCount) - { - /* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */ - LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable); - } - } - - /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there - *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. - */ - if ((handle->readRegRemainingTimes) <= (handle->rxWatermark)) - { - base->FCR = - (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | - LPSPI_FCR_RXWATER((handle->readRegRemainingTimes > 1) ? (handle->readRegRemainingTimes - 1U) : (0U)); - } - } - - if (handle->txRemainingByteCount) - { - LPSPI_MasterTransferFillUpTxFifo(base, handle); - } - else - { - if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize))) - { - if ((handle->isPcsContinuous) && (handle->writeTcrInIsr)) - { - base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); - handle->writeTcrInIsr = false; - } - } - } - - if ((handle->txRemainingByteCount == 0) && (handle->rxRemainingByteCount == 0) && (!handle->writeTcrInIsr)) - { - /* If no RX buffer, then transfer is not complete until transfer complete flag sets */ - if (handle->rxData == NULL) - { - if (LPSPI_GetStatusFlags(base) & kLPSPI_TransferCompleteFlag) - { - /* Complete the transfer and disable the interrupts */ - LPSPI_MasterTransferComplete(base, handle); - } - else - { - LPSPI_EnableInterrupts(base, kLPSPI_TransferCompleteInterruptEnable); - LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable); - } - } - else - { - /* Complete the transfer and disable the interrupts */ - LPSPI_MasterTransferComplete(base, handle); - } - } -} - -/*Transactional APIs -- Slave*/ -void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, - lpspi_slave_handle_t *handle, - lpspi_slave_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - s_lpspiHandle[LPSPI_GetInstance(base)] = handle; - - /* Set irq handler. */ - s_lpspiSlaveIsr = LPSPI_SlaveTransferHandleIRQ; - - handle->callback = callback; - handle->userData = userData; -} - -status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; - uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - uint32_t temp = 0U; - - if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == kLPSPI_Busy) - { - return kStatus_LPSPI_Busy; - } - handle->state = kLPSPI_Busy; - - bool isRxMask = false; - bool isTxMask = false; - - uint32_t whichPcs = (transfer->configFlags & LPSPI_SLAVE_PCS_MASK) >> LPSPI_SLAVE_PCS_SHIFT; - - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->txRemainingByteCount = transfer->dataSize; - handle->rxRemainingByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); - handle->readRegRemainingTimes = handle->writeRegRemainingTimes; - - /*The TX and RX FIFO sizes are always the same*/ - handle->fifoSize = LPSPI_GetRxFifoSize(base); - - handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_SlaveByteSwap); - - /*Set the RX and TX watermarks to reduce the ISR times.*/ - uint8_t txWatermark; - if (handle->fifoSize > 1) - { - txWatermark = 1; - handle->rxWatermark = handle->fifoSize - 2; - } - else - { - txWatermark = 0; - handle->rxWatermark = 0; - } - LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); - - /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ - temp = base->CFGR1; - temp &= LPSPI_CFGR1_PINCFG_MASK; - if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) - { - if (!handle->txData) - { - LPSPI_Enable(base, false); - base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; - LPSPI_Enable(base, true); - } - /* The 3-wire mode can't send and receive data at the same time. */ - if ((handle->txData) && (handle->rxData)) - { - return kStatus_InvalidArgument; - } - } - - /*Flush FIFO , clear status , disable all the inerrupts.*/ - LPSPI_FlushFifo(base, true, true); - LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - /*If there is not rxData , can mask the receive data (receive data is not stored in receive FIFO).*/ - if (handle->rxData == NULL) - { - isRxMask = true; - handle->rxRemainingByteCount = 0; - } - - /*If there is not txData , can mask the transmit data (no data is loaded from transmit FIFO and output pin - * is tristated). - */ - if (handle->txData == NULL) - { - isTxMask = true; - handle->txRemainingByteCount = 0; - } - - base->TCR = (base->TCR & - ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_TXMSK_MASK | - LPSPI_TCR_PCS_MASK)) | - LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) | - LPSPI_TCR_PCS(whichPcs); - - /*Calculate the bytes for write/read the TX/RX register each time*/ - if (bytesPerFrame <= 4) - { - handle->bytesEachWrite = bytesPerFrame; - handle->bytesEachRead = bytesPerFrame; - } - else - { - handle->bytesEachWrite = 4; - handle->bytesEachRead = 4; - } - - /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , - * and you should also enable the INTMUX interupt in your application. - */ - EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); - - /*TCR is also shared the FIFO , so wait for TCR written.*/ - while (LPSPI_GetTxFifoCount(base) != 0) - { - } - - /*Fill up the TX data in FIFO */ - if (handle->txData) - { - LPSPI_SlaveTransferFillUpTxFifo(base, handle); - } - - /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. - * The IRQ handler will get the status of RX and TX interrupt flags. - */ - if (handle->rxData) - { - /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there - *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. - */ - if ((handle->readRegRemainingTimes) <= handle->rxWatermark) - { - base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->readRegRemainingTimes - 1); - } - - LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable); - } - else - { - LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable); - } - - if (handle->rxData) - { - /* RX FIFO overflow request enable */ - LPSPI_EnableInterrupts(base, kLPSPI_ReceiveErrorInterruptEnable); - } - if (handle->txData) - { - /* TX FIFO underflow request enable */ - LPSPI_EnableInterrupts(base, kLPSPI_TransmitErrorInterruptEnable); - } - - return kStatus_Success; -} - -static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle) -{ - assert(handle); - - uint32_t wordToSend = 0; - - while (LPSPI_GetTxFifoCount(base) < (handle->fifoSize)) - { - if (handle->txRemainingByteCount < handle->bytesEachWrite) - { - handle->bytesEachWrite = handle->txRemainingByteCount; - } - - wordToSend = LPSPI_CombineWriteData(handle->txData, handle->bytesEachWrite, handle->isByteSwap); - handle->txData += handle->bytesEachWrite; - - /*Decrease the remaining TX byte count.*/ - handle->txRemainingByteCount -= handle->bytesEachWrite; - - /*Write the word to TX register*/ - LPSPI_WriteData(base, wordToSend); - - if (handle->txRemainingByteCount == 0) - { - break; - } - } -} - -static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle) -{ - assert(handle); - - status_t status = 0; - - /* Disable interrupt requests*/ - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - if (handle->state == kLPSPI_Error) - { - status = kStatus_LPSPI_Error; - } - else - { - status = kStatus_Success; - } - - handle->state = kLPSPI_Idle; - - if (handle->callback) - { - handle->callback(base, handle, status, handle->userData); - } -} - -status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kLPSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t remainingByte; - - if (handle->rxData) - { - remainingByte = handle->rxRemainingByteCount; - } - else - { - remainingByte = handle->txRemainingByteCount; - } - - *count = handle->totalByteCount - remainingByte; - - return kStatus_Success; -} - -void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle) -{ - assert(handle); - - /* Disable interrupt requests*/ - LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable); - - LPSPI_Reset(base); - - handle->state = kLPSPI_Idle; - handle->txRemainingByteCount = 0; - handle->rxRemainingByteCount = 0; -} - -void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle) -{ - assert(handle); - - uint32_t readData; /* variable to store word read from RX FIFO */ - uint32_t wordToSend; /* variable to store word to write to TX FIFO */ - - if (handle->rxData != NULL) - { - if (handle->rxRemainingByteCount > 0) - { - while (LPSPI_GetRxFifoCount(base)) - { - /*Read out the data*/ - readData = LPSPI_ReadData(base); - - /*Decrease the read RX register times.*/ - --handle->readRegRemainingTimes; - - if (handle->rxRemainingByteCount < handle->bytesEachRead) - { - handle->bytesEachRead = handle->rxRemainingByteCount; - } - - LPSPI_SeparateReadData(handle->rxData, readData, handle->bytesEachRead, handle->isByteSwap); - handle->rxData += handle->bytesEachRead; - - /*Decrease the remaining RX byte count.*/ - handle->rxRemainingByteCount -= handle->bytesEachRead; - - if ((handle->txRemainingByteCount > 0) && (handle->txData != NULL)) - { - if (handle->txRemainingByteCount < handle->bytesEachWrite) - { - handle->bytesEachWrite = handle->txRemainingByteCount; - } - - wordToSend = LPSPI_CombineWriteData(handle->txData, handle->bytesEachWrite, handle->isByteSwap); - handle->txData += handle->bytesEachWrite; - - /*Decrease the remaining TX byte count.*/ - handle->txRemainingByteCount -= handle->bytesEachWrite; - - /*Write the word to TX register*/ - LPSPI_WriteData(base, wordToSend); - } - - if (handle->rxRemainingByteCount == 0) - { - break; - } - } - } - - /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there - *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. - */ - if ((handle->readRegRemainingTimes) <= (handle->rxWatermark)) - { - base->FCR = - (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | - LPSPI_FCR_RXWATER((handle->readRegRemainingTimes > 1) ? (handle->readRegRemainingTimes - 1U) : (0U)); - } - } - else if ((handle->txRemainingByteCount) && (handle->txData != NULL)) - { - LPSPI_SlaveTransferFillUpTxFifo(base, handle); - } - else - { - __NOP(); - } - - if ((handle->txRemainingByteCount == 0) && (handle->rxRemainingByteCount == 0)) - { - /* If no RX buffer, then transfer is not complete until transfer complete flag sets and the TX FIFO empty*/ - if (handle->rxData == NULL) - { - if ((LPSPI_GetStatusFlags(base) & kLPSPI_FrameCompleteFlag) && (LPSPI_GetTxFifoCount(base) == 0)) - { - /* Complete the transfer and disable the interrupts */ - LPSPI_SlaveTransferComplete(base, handle); - } - else - { - LPSPI_ClearStatusFlags(base, kLPSPI_FrameCompleteFlag); - LPSPI_EnableInterrupts(base, kLPSPI_FrameCompleteInterruptEnable); - LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable); - } - } - else - { - /* Complete the transfer and disable the interrupts */ - LPSPI_SlaveTransferComplete(base, handle); - } - } - - /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */ - if ((LPSPI_GetStatusFlags(base) & kLPSPI_TransmitErrorFlag) && (base->IER & LPSPI_IER_TEIE_MASK)) - { - LPSPI_ClearStatusFlags(base, kLPSPI_TransmitErrorFlag); - /* Change state to error and clear flag */ - if (handle->txData) - { - handle->state = kLPSPI_Error; - } - handle->errorCount++; - } - /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */ - if ((LPSPI_GetStatusFlags(base) & kLPSPI_ReceiveErrorFlag) && (base->IER & LPSPI_IER_REIE_MASK)) - { - LPSPI_ClearStatusFlags(base, kLPSPI_ReceiveErrorFlag); - /* Change state to error and clear flag */ - if (handle->txData) - { - handle->state = kLPSPI_Error; - } - handle->errorCount++; - } -} - -static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint32_t bytesEachWrite, bool isByteSwap) -{ - assert(txData); - - uint32_t wordToSend = 0; - - switch (bytesEachWrite) - { - case 1: - wordToSend = *txData; - ++txData; - break; - - case 2: - if (!isByteSwap) - { - wordToSend = *txData; - ++txData; - wordToSend |= (unsigned)(*txData) << 8U; - ++txData; - } - else - { - wordToSend = (unsigned)(*txData) << 8U; - ++txData; - wordToSend |= *txData; - ++txData; - } - - break; - - case 3: - if (!isByteSwap) - { - wordToSend = *txData; - ++txData; - wordToSend |= (unsigned)(*txData) << 8U; - ++txData; - wordToSend |= (unsigned)(*txData) << 16U; - ++txData; - } - else - { - wordToSend = (unsigned)(*txData) << 16U; - ++txData; - wordToSend |= (unsigned)(*txData) << 8U; - ++txData; - wordToSend |= *txData; - ++txData; - } - break; - - case 4: - if (!isByteSwap) - { - wordToSend = *txData; - ++txData; - wordToSend |= (unsigned)(*txData) << 8U; - ++txData; - wordToSend |= (unsigned)(*txData) << 16U; - ++txData; - wordToSend |= (unsigned)(*txData) << 24U; - ++txData; - } - else - { - wordToSend = (unsigned)(*txData) << 24U; - ++txData; - wordToSend |= (unsigned)(*txData) << 16U; - ++txData; - wordToSend |= (unsigned)(*txData) << 8U; - ++txData; - wordToSend |= *txData; - ++txData; - } - break; - - default: - assert(false); - break; - } - return wordToSend; -} - -static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap) -{ - assert(rxData); - - switch (bytesEachRead) - { - case 1: - *rxData = readData; - ++rxData; - break; - - case 2: - if (!isByteSwap) - { - *rxData = readData; - ++rxData; - *rxData = readData >> 8; - ++rxData; - } - else - { - *rxData = readData >> 8; - ++rxData; - *rxData = readData; - ++rxData; - } - break; - - case 3: - if (!isByteSwap) - { - *rxData = readData; - ++rxData; - *rxData = readData >> 8; - ++rxData; - *rxData = readData >> 16; - ++rxData; - } - else - { - *rxData = readData >> 16; - ++rxData; - *rxData = readData >> 8; - ++rxData; - *rxData = readData; - ++rxData; - } - break; - - case 4: - if (!isByteSwap) - { - *rxData = readData; - ++rxData; - *rxData = readData >> 8; - ++rxData; - *rxData = readData >> 16; - ++rxData; - *rxData = readData >> 24; - ++rxData; - } - else - { - *rxData = readData >> 24; - ++rxData; - *rxData = readData >> 16; - ++rxData; - *rxData = readData >> 8; - ++rxData; - *rxData = readData; - ++rxData; - } - break; - - default: - assert(false); - break; - } -} - -static void LPSPI_CommonIRQHandler(LPSPI_Type *base, void *param) -{ - if (LPSPI_IsMaster(base)) - { - s_lpspiMasterIsr(base, (lpspi_master_handle_t *)param); - } - else - { - s_lpspiSlaveIsr(base, (lpspi_slave_handle_t *)param); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#if defined(LPSPI0) -void LPSPI0_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[0]); - LPSPI_CommonIRQHandler(LPSPI0, s_lpspiHandle[0]); -} -#endif - -#if defined(LPSPI1) -void LPSPI1_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[1]); - LPSPI_CommonIRQHandler(LPSPI1, s_lpspiHandle[1]); -} -#endif - -#if defined(LPSPI2) -void LPSPI2_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[2]); - LPSPI_CommonIRQHandler(LPSPI2, s_lpspiHandle[2]); -} -#endif - -#if defined(LPSPI3) -void LPSPI3_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[3]); - LPSPI_CommonIRQHandler(LPSPI3, s_lpspiHandle[3]); -} -#endif - -#if defined(LPSPI4) -void LPSPI4_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[4]); - LPSPI_CommonIRQHandler(LPSPI4, s_lpspiHandle[4]); -} -#endif - -#if defined(LPSPI5) -void LPSPI5_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[5]); - LPSPI_CommonIRQHandler(LPSPI5, s_lpspiHandle[5]); -} -#endif - -#if defined(DMA__LPSPI0) -void DMA_SPI0_INT_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)]); - LPSPI_CommonIRQHandler(DMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)]); -} -#endif - -#if defined(DMA__LPSPI1) -void DMA_SPI1_INT_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)]); - LPSPI_CommonIRQHandler(DMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)]); -} -#endif -#if defined(DMA__LPSPI2) -void DMA_SPI2_INT_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)]); - LPSPI_CommonIRQHandler(DMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)]); -} -#endif - -#if defined(DMA__LPSPI3) -void DMA_SPI3_INT_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)]); - LPSPI_CommonIRQHandler(DMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)]); -} -#endif - -#if defined(ADMA__LPSPI0) -void ADMA_SPI0_INT_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]); - LPSPI_CommonIRQHandler(ADMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]); -} -#endif - -#if defined(ADMA__LPSPI1) -void ADMA_SPI1_INT_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]); - LPSPI_CommonIRQHandler(ADMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]); -} -#endif -#if defined(ADMA__LPSPI2) -void ADMA_SPI2_INT_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]); - LPSPI_CommonIRQHandler(ADMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]); -} -#endif - -#if defined(ADMA__LPSPI3) -void ADMA_SPI3_INT_DriverIRQHandler(void) -{ - assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]); - LPSPI_CommonIRQHandler(ADMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]); -} -#endif diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi.h deleted file mode 100644 index 72895a225b..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi.h +++ /dev/null @@ -1,1145 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LPSPI_H_ -#define _FSL_LPSPI_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpspi_driver - * @{ - */ - -/********************************************************************************************************************** - * Definitions - *********************************************************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPSPI driver version 2.0.1. */ -#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -#ifndef LPSPI_DUMMY_DATA -/*! @brief LPSPI dummy data if no Tx data.*/ -#define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */ -#endif - -/*! @brief Global variable for dummy data value setting. */ -extern volatile uint8_t g_lpspiDummyData[]; - -/*! @brief Status for the LPSPI driver.*/ -enum _lpspi_status -{ - kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/ - kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */ - kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/ - kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3) /*!< LPSPI transfer out Of range. */ -}; - -/*! @brief LPSPI status flags in SPIx_SR register.*/ -enum _lpspi_flags -{ - kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */ - kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */ - kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */ - kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */ - kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */ - kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */ - kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */ - kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */ - kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */ - kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK | - LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK | - LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */ -}; - -/*! @brief LPSPI interrupt source.*/ -enum _lpspi_interrupt_enable -{ - kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */ - kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */ - kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */ - kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */ - kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */ - kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/ - kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */ - kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */ - kLPSPI_AllInterruptEnable = - (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK | - LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/ -}; - -/*! @brief LPSPI DMA source.*/ -enum _lpspi_dma_enable -{ - kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, /*!< Transmit data DMA enable */ - kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK /*!< Receive data DMA enable */ -}; - -/*! @brief LPSPI master or slave mode configuration.*/ -typedef enum _lpspi_master_slave_mode -{ - kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/ - kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/ -} lpspi_master_slave_mode_t; - -/*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/ -typedef enum _lpspi_which_pcs_config -{ - kLPSPI_Pcs0 = 0U, /*!< PCS[0] */ - kLPSPI_Pcs1 = 1U, /*!< PCS[1] */ - kLPSPI_Pcs2 = 2U, /*!< PCS[2] */ - kLPSPI_Pcs3 = 3U /*!< PCS[3] */ -} lpspi_which_pcs_t; - -/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity configuration.*/ -typedef enum _lpspi_pcs_polarity_config -{ - kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */ - kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */ -} lpspi_pcs_polarity_config_t; - -/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/ -enum _lpspi_pcs_polarity -{ - kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ - kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ - kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ - kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ - kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ -}; - -/*! @brief LPSPI clock polarity configuration.*/ -typedef enum _lpspi_clock_polarity -{ - kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/ - kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/ -} lpspi_clock_polarity_t; - -/*! @brief LPSPI clock phase configuration.*/ -typedef enum _lpspi_clock_phase -{ - kLPSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the - following edge.*/ - kLPSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the - following edge.*/ -} lpspi_clock_phase_t; - -/*! @brief LPSPI data shifter direction options.*/ -typedef enum _lpspi_shift_direction -{ - kLPSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ - kLPSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/ -} lpspi_shift_direction_t; - -/*! @brief LPSPI Host Request select configuration. */ -typedef enum _lpspi_host_request_select -{ - kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */ - kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */ -} lpspi_host_request_select_t; - -/*! @brief LPSPI Match configuration options. */ -typedef enum _lpspi_match_config -{ - kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */ - kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */ - kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */ - kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */ - kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */ - kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */ - kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */ -} lpspi_match_config_t; - -/*! @brief LPSPI pin (SDO and SDI) configuration. */ -typedef enum _lpspi_pin_config -{ - kLPSPI_SdiInSdoOut = 0U, /*!< LPSPI SDI input, SDO output. */ - kLPSPI_SdiInSdiOut = 1U, /*!< LPSPI SDI input, SDI output. */ - kLPSPI_SdoInSdoOut = 2U, /*!< LPSPI SDO input, SDO output. */ - kLPSPI_SdoInSdiOut = 3U /*!< LPSPI SDO input, SDI output. */ -} lpspi_pin_config_t; - -/*! @brief LPSPI data output configuration. */ -typedef enum _lpspi_data_out_config -{ - kLpspiDataOutRetained = 0U, /*!< Data out retains last value when chip select is de-asserted */ - kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */ -} lpspi_data_out_config_t; - -/*! @brief LPSPI transfer width configuration. */ -typedef enum _lpspi_transfer_width -{ - kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */ - kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */ - kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */ -} lpspi_transfer_width_t; - -/*! @brief LPSPI delay type selection.*/ -typedef enum _lpspi_delay_type -{ - kLPSPI_PcsToSck = 1U, /*!< PCS-to-SCK delay. */ - kLPSPI_LastSckToPcs, /*!< Last SCK edge to PCS delay. */ - kLPSPI_BetweenTransfer /*!< Delay between transfers. */ -} lpspi_delay_type_t; - -#define LPSPI_MASTER_PCS_SHIFT (4U) /*!< LPSPI master PCS shift macro , internal used. */ -#define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */ - -/*! @brief Use this enumeration for LPSPI master transfer configFlags. */ -enum _lpspi_transfer_config_flag_for_master -{ - kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS0 signal */ - kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */ - kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */ - kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */ - - kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */ - - kLPSPI_MasterByteSwap = - 1U << 22 /*!< Is master swap the byte. - * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set - * lpspi_shift_direction_t to MSB). - * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used - * or not, the waveform is 1 2 3 4 5 6 7 8. - * 2. If you set bitPerFrame = 16 : - * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. - * 3. If you set bitPerFrame = 32 : - * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. - */ -}; - -#define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */ -#define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */ - -/*! @brief Use this enumeration for LPSPI slave transfer configFlags. */ -enum _lpspi_transfer_config_flag_for_slave -{ - kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS0 signal */ - kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS1 signal */ - kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */ - kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */ - - kLPSPI_SlaveByteSwap = - 1U << 22 /*!< Is slave swap the byte. - * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set - * lpspi_shift_direction_t to MSB). - * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used - * or not, the waveform is 1 2 3 4 5 6 7 8. - * 2. If you set bitPerFrame = 16 : - * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. - * 3. If you set bitPerFrame = 32 : - * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. - */ -}; - -/*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */ -enum _lpspi_transfer_state -{ - kLPSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ - kLPSPI_Busy, /*!< Transfer queue is not finished. */ - kLPSPI_Error /*!< Transfer error. */ -}; - -/*! @brief LPSPI master configuration structure.*/ -typedef struct _lpspi_master_config -{ - uint32_t baudRate; /*!< Baud Rate for LPSPI. */ - uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ - lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ - lpspi_clock_phase_t cpha; /*!< Clock phase. */ - lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ - - uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. - It sets the boundary value if out of range.*/ - uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum - delay. It sets the boundary value if out of range.*/ - uint32_t - betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the minimum - delay. It sets the boundary value if out of range.*/ - - lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (PCS). */ - lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ - - lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data - *during single bit transfers.*/ - - lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated - * between accesses (LPSPI_PCS is negated). */ -} lpspi_master_config_t; - -/*! @brief LPSPI slave configuration structure.*/ -typedef struct _lpspi_slave_config -{ - uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ - lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ - lpspi_clock_phase_t cpha; /*!< Clock phase. */ - lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ - - lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */ - lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ - - lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data - *during single bit transfers.*/ - - lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated - * between accesses (LPSPI_PCS is negated). */ -} lpspi_slave_config_t; - -/*! -* @brief Forward declaration of the _lpspi_master_handle typedefs. -*/ -typedef struct _lpspi_master_handle lpspi_master_handle_t; - -/*! -* @brief Forward declaration of the _lpspi_slave_handle typedefs. -*/ -typedef struct _lpspi_slave_handle lpspi_slave_handle_t; - -/*! - * @brief Master completion callback function pointer type. - * - * @param base LPSPI peripheral address. - * @param handle Pointer to the handle for the LPSPI master. - * @param status Success or error code describing whether the transfer is completed. - * @param userData Arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, - lpspi_master_handle_t *handle, - status_t status, - void *userData); - -/*! - * @brief Slave completion callback function pointer type. - * - * @param base LPSPI peripheral address. - * @param handle Pointer to the handle for the LPSPI slave. - * @param status Success or error code describing whether the transfer is completed. - * @param userData Arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, - lpspi_slave_handle_t *handle, - status_t status, - void *userData); - -/*! @brief LPSPI master/slave transfer structure.*/ -typedef struct _lpspi_transfer -{ - uint8_t *txData; /*!< Send buffer. */ - uint8_t *rxData; /*!< Receive buffer. */ - volatile size_t dataSize; /*!< Transfer bytes. */ - - uint32_t - configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if the - transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the transfer - is used for slave.*/ -} lpspi_transfer_t; - -/*! @brief LPSPI master transfer handle structure used for transactional API. */ -struct _lpspi_master_handle -{ - volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ - volatile bool writeTcrInIsr; /*!< A flag that whether should write TCR in ISR. */ - - volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ - - volatile uint8_t fifoSize; /*!< FIFO dataSize. */ - - volatile uint8_t rxWatermark; /*!< Rx watermark. */ - - volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ - volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ - - uint8_t *volatile txData; /*!< Send buffer. */ - uint8_t *volatile rxData; /*!< Receive buffer. */ - volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ - volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ - - volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ - volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ - - uint32_t totalByteCount; /*!< Number of transfer bytes*/ - - uint32_t txBuffIfNull; /*!< Used if the txData is NULL. */ - - volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ - - lpspi_master_transfer_callback_t callback; /*!< Completion callback. */ - void *userData; /*!< Callback user data. */ -}; - -/*! @brief LPSPI slave transfer handle structure used for transactional API. */ -struct _lpspi_slave_handle -{ - volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ - - volatile uint8_t fifoSize; /*!< FIFO dataSize. */ - - volatile uint8_t rxWatermark; /*!< Rx watermark. */ - - volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ - volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ - - uint8_t *volatile txData; /*!< Send buffer. */ - uint8_t *volatile rxData; /*!< Receive buffer. */ - - volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ - volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ - - volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ - volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ - - uint32_t totalByteCount; /*!< Number of transfer bytes*/ - - volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ - - volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ - - lpspi_slave_transfer_callback_t callback; /*!< Completion callback. */ - void *userData; /*!< Callback user data. */ -}; - -/********************************************************************************************************************** - * API - *********************************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the LPSPI master. - * - * @param base LPSPI peripheral address. - * @param masterConfig Pointer to structure lpspi_master_config_t. - * @param srcClock_Hz Module source input clock in Hertz - */ -void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz); - -/*! - * @brief Sets the lpspi_master_config_t structure to default values. - * - * This API initializes the configuration structure for LPSPI_MasterInit(). - * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified - * before calling the LPSPI_MasterInit(). - * Example: - * @code - * lpspi_master_config_t masterConfig; - * LPSPI_MasterGetDefaultConfig(&masterConfig); - * @endcode - * @param masterConfig pointer to lpspi_master_config_t structure - */ -void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig); - -/*! - * @brief LPSPI slave configuration. - * - * @param base LPSPI peripheral address. - * @param slaveConfig Pointer to a structure lpspi_slave_config_t. - */ -void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig); - -/*! - * @brief Sets the lpspi_slave_config_t structure to default values. - * - * This API initializes the configuration structure for LPSPI_SlaveInit(). - * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified - * before calling the LPSPI_SlaveInit(). - * Example: - * @code - * lpspi_slave_config_t slaveConfig; - * LPSPI_SlaveGetDefaultConfig(&slaveConfig); - * @endcode - * @param slaveConfig pointer to lpspi_slave_config_t structure. - */ -void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig); - -/*! - * @brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. - * @param base LPSPI peripheral address. - */ -void LPSPI_Deinit(LPSPI_Type *base); - -/*! - * @brief Restores the LPSPI peripheral to reset state. Note that this function - * sets all registers to reset state. As a result, the LPSPI module can't work after calling - * this API. - * @param base LPSPI peripheral address. -*/ -void LPSPI_Reset(LPSPI_Type *base); - -/*! - * @brief Enables the LPSPI peripheral and sets the MCR MDIS to 0. - * - * @param base LPSPI peripheral address. - * @param enable Pass true to enable module, false to disable module. - */ -static inline void LPSPI_Enable(LPSPI_Type *base, bool enable) -{ - if (enable) - { - base->CR |= LPSPI_CR_MEN_MASK; - } - else - { - base->CR &= ~LPSPI_CR_MEN_MASK; - } -} - -/*! - *@} -*/ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the LPSPI status flag state. - * @param base LPSPI peripheral address. - * @return The LPSPI status(in SR register). - */ -static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base) -{ - return (base->SR); -} - -/*! - * @brief Gets the LPSPI Tx FIFO size. - * @param base LPSPI peripheral address. - * @return The LPSPI Tx FIFO size. - */ -static inline uint32_t LPSPI_GetTxFifoSize(LPSPI_Type *base) -{ - return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT)); -} - -/*! - * @brief Gets the LPSPI Rx FIFO size. - * @param base LPSPI peripheral address. - * @return The LPSPI Rx FIFO size. - */ -static inline uint32_t LPSPI_GetRxFifoSize(LPSPI_Type *base) -{ - return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT)); -} - -/*! - * @brief Gets the LPSPI Tx FIFO count. - * @param base LPSPI peripheral address. - * @return The number of words in the transmit FIFO. - */ -static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base) -{ - return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT); -} - -/*! - * @brief Gets the LPSPI Rx FIFO count. - * @param base LPSPI peripheral address. - * @return The number of words in the receive FIFO. - */ -static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base) -{ - return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT); -} - -/*! - * @brief Clears the LPSPI status flag. - * - * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the - * desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. - * Example usage: - * @code - * LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag); - * @endcode - * - * @param base LPSPI peripheral address. - * @param statusFlags The status flag used from type _lpspi_flags. - */ -static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags) -{ - base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ -} - -/*! - *@} -*/ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the LPSPI interrupts. - * - * This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. - * Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request. - * - * @code - * LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); - * @endcode - * - * @param base LPSPI peripheral address. - * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. - */ -static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask) -{ - base->IER |= mask; -} - -/*! - * @brief Disables the LPSPI interrupts. - * - * @code - * LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); - * @endcode - * - * @param base LPSPI peripheral address. - * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. - */ -static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask) -{ - base->IER &= ~mask; -} - -/*! - *@} -*/ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables the LPSPI DMA request. - * - * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. - * @code - * LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); - * @endcode - * - * @param base LPSPI peripheral address. - * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. - */ -static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask) -{ - base->DER |= mask; -} - -/*! - * @brief Disables the LPSPI DMA request. - * - * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. - * @code - * SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); - * @endcode - * - * @param base LPSPI peripheral address. - * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. - */ -static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask) -{ - base->DER &= ~mask; -} - -/*! - * @brief Gets the LPSPI Transmit Data Register address for a DMA operation. - * - * This function gets the LPSPI Transmit Data Register address because this value is needed - * for the DMA operation. - * This function can be used for either master or slave mode. - * - * @param base LPSPI peripheral address. - * @return The LPSPI Transmit Data Register address. - */ -static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base) -{ - return (uint32_t) & (base->TDR); -} - -/*! - * @brief Gets the LPSPI Receive Data Register address for a DMA operation. - * - * This function gets the LPSPI Receive Data Register address because this value is needed - * for the DMA operation. - * This function can be used for either master or slave mode. - * - * @param base LPSPI peripheral address. - * @return The LPSPI Receive Data Register address. - */ -static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base) -{ - return (uint32_t) & (base->RDR); -} - -/*! - *@} -*/ - -/*! - * @name Bus Operations - * @{ - */ - -/*! -* @brief Get instance number for LPSPI module. -* -* @param base LPSPI peripheral base address. -* @return Return the value of LPSPI instance. -*/ -uint32_t LPSPI_GetInstance(LPSPI_Type *base); - -/*! -* @brief Check the argument for transfer . -* -* @param transfer the transfer struct to be used. -* @param bitPerFrame The bit size of one frame. -* @param bytePerFrame The byte size of one frame. -* @return Return true for right and false for wrong. -*/ -bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame); - -/*! - * @brief Configures the LPSPI for either master or slave. - * - * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). - * - * @param base LPSPI peripheral address. - * @param mode Mode setting (master or slave) of type lpspi_master_slave_mode_t. - */ -static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode) -{ - base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); -} - -/*! - * @brief Returns whether the LPSPI module is in master mode. - * - * @param base LPSPI peripheral address. - * @return Returns true if the module is in master mode or false if the module is in slave mode. - */ -static inline bool LPSPI_IsMaster(LPSPI_Type *base) -{ - return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); -} - -/*! - * @brief Flushes the LPSPI FIFOs. - * - * @param base LPSPI peripheral address. - * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO. - * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO. - */ -static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo) -{ - base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT); -} - -/*! - * @brief Sets the transmit and receive FIFO watermark values. - * - * This function allows the user to set the receive and transmit FIFO watermarks. The function - * does not compare the watermark settings to the FIFO size. The FIFO watermark should not be - * equal to or greater than the FIFO size. It is up to the higher level driver to make this check. - * - * @param base LPSPI peripheral address. - * @param txWater The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. - * @param rxWater The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. - */ -static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater) -{ - base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater); -} - -/*! - * @brief Configures all LPSPI peripheral chip select polarities simultaneously. - * - * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). - * - * This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of - * PCS is device-specific. - * @code - * LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow); - * @endcode - * - * @param base LPSPI peripheral address. - * @param mask The PCS polarity mask; Use the enum _lpspi_pcs_polarity. - */ -static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask) -{ - base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); -} - -/*! - * @brief Configures the frame size. - * - * The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal - * to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word - * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not - * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported. - * - * Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although - * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command - * register - * should only be changed if the LPSPI is idle. - * - * Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That - * means the TCR register should be written to when the Tx FIFO is not full. - * - * @param base LPSPI peripheral address. - * @param frameSize The frame size in number of bits. - */ -static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize) -{ - base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1); -} - -/*! - * @brief Sets the LPSPI baud rate in bits per second. - * - * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest - * possible baud rate without exceeding the desired baud rate and returns the - * calculated baud rate in bits-per-second. It requires the caller to provide - * the frequency of the module source clock (in Hertz). Note that the baud rate - * does not go into effect until the Transmit Control Register (TCR) is programmed - * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue - * parameter for later programming in the TCR. The higher level - * peripheral driver should alert the user of an out of range baud rate input. - * - * Note that the LPSPI module must first be disabled before configuring this. - * Note that the LPSPI module must be configured for master mode before configuring this. - * - * @param base LPSPI peripheral address. - * @param baudRate_Bps The desired baud rate in bits per second. - * @param srcClock_Hz Module source input clock in Hertz. - * @param tcrPrescaleValue The TCR prescale value needed to program the TCR. - * @return The actual calculated baud rate. This function may also return a "0" if the - * LPSPI is not configured for master mode or if the LPSPI module is not disabled. - */ - -uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, - uint32_t baudRate_Bps, - uint32_t srcClock_Hz, - uint32_t *tcrPrescaleValue); - -/*! - * @brief Manually configures a specific LPSPI delay parameter (module must be disabled to - * change the delay values). - * - * This function configures the following: - * SCK to PCS delay, or - * PCS to SCK delay, or - * The configurations must occur between the transfer delay. - * - * The delay names are available in type lpspi_delay_type_t. - * - * The user passes the desired delay along with the delay value. - * This allows the user to directly set the delay values if they have - * pre-calculated them or if they simply wish to manually increment the value. - * - * Note that the LPSPI module must first be disabled before configuring this. - * Note that the LPSPI module must be configured for master mode before configuring this. - * - * @param base LPSPI peripheral address. - * @param scaler The 8-bit delay value 0x00 to 0xFF (255). - * @param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t. - */ -void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay); - -/*! - * @brief Calculates the delay based on the desired delay input in nanoseconds (module must be - * disabled to change the delay values). - * - * This function calculates the values for the following: - * SCK to PCS delay, or - * PCS to SCK delay, or - * The configurations must occur between the transfer delay. - * - * The delay names are available in type lpspi_delay_type_t. - * - * The user passes the desired delay and the desired delay value in - * nano-seconds. The function calculates the value needed for the desired delay parameter - * and returns the actual calculated delay because an exact delay match may not be possible. In this - * case, the closest match is calculated without going below the desired delay value input. - * It is possible to input a very large delay value that exceeds the capability of the part, in - * which case the maximum supported delay is returned. It is up to the higher level - * peripheral driver to alert the user of an out of range delay input. - * - * Note that the LPSPI module must be configured for master mode before configuring this. And note that - * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler). - * - * @param base LPSPI peripheral address. - * @param delayTimeInNanoSec The desired delay value in nano-seconds. - * @param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. - * @param srcClock_Hz Module source input clock in Hertz. - * @return actual Calculated delay value in nano-seconds. - */ -uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, - uint32_t delayTimeInNanoSec, - lpspi_delay_type_t whichDelay, - uint32_t srcClock_Hz); - -/*! - * @brief Writes data into the transmit data buffer. - * - * This function writes data passed in by the user to the Transmit Data Register (TDR). - * The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, - * the user has to manage sending the data one 32-bit word at a time. - * Any writes to the TDR result in an immediate push to the transmit FIFO. - * This function can be used for either master or slave modes. - * - * @param base LPSPI peripheral address. - * @param data The data word to be sent. - */ -static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data) -{ - base->TDR = data; -} - -/*! - * @brief Reads data from the data buffer. - * - * This function reads the data from the Receive Data Register (RDR). - * This function can be used for either master or slave mode. - * - * @param base LPSPI peripheral address. - * @return The data read from the data buffer. - */ -static inline uint32_t LPSPI_ReadData(LPSPI_Type *base) -{ - return (base->RDR); -} - -/*! - * @brief Set up the dummy data. - * - * @param base LPSPI peripheral address. - * @param dummyData Data to be transferred when tx buffer is NULL. - * Note: - * This API has no effect when LPSPI in slave interrupt mode, because driver - * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit - * FIFO and output pin is tristated. - */ -void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData); - -/*! - *@} -*/ - -/*! - * @name Transactional - * @{ - */ -/*Transactional APIs*/ - -/*! - * @brief Initializes the LPSPI master handle. - * - * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a - * specified LPSPI instance, call this API once to get the initialized handle. - - * @param base LPSPI peripheral address. - * @param handle LPSPI handle pointer to lpspi_master_handle_t. - * @param callback DSPI callback. - * @param userData callback function parameter. - */ -void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, - lpspi_master_handle_t *handle, - lpspi_master_transfer_callback_t callback, - void *userData); - -/*! - * @brief LPSPI master transfer data using a polling method. - * - * This function transfers data using a polling method. This is a blocking function, which does not return until all - * transfers have been - * completed. - * - * Note: - * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. - * For bytesPerFrame greater than 4: - * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. - * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. - * - * @param base LPSPI peripheral address. - * @param transfer pointer to lpspi_transfer_t structure. - * @return status of status_t. - */ -status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer); - -/*! - * @brief LPSPI master transfer data using an interrupt method. - * - * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. - * When all data - * is transferred, the callback function is called. - * - * Note: - * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. - * For bytesPerFrame greater than 4: - * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. - * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. - * @param transfer pointer to lpspi_transfer_t structure. - * @return status of status_t. - */ -status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer); - -/*! - * @brief Gets the master transfer remaining bytes. - * - * This function gets the master transfer remaining bytes. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @return status of status_t. - */ -status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count); - -/*! - * @brief LPSPI master abort transfer which uses an interrupt method. - * - * This function aborts a transfer which uses an interrupt method. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. - */ -void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle); - -/*! - * @brief LPSPI Master IRQ handler function. - * - * This function processes the LPSPI transmit and receive IRQ. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. - */ -void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle); - -/*! - * @brief Initializes the LPSPI slave handle. - * - * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a - * specified LPSPI instance, call this API once to get the initialized handle. - * - * @param base LPSPI peripheral address. - * @param handle LPSPI handle pointer to lpspi_slave_handle_t. - * @param callback DSPI callback. - * @param userData callback function parameter. - */ -void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, - lpspi_slave_handle_t *handle, - lpspi_slave_transfer_callback_t callback, - void *userData); - -/*! - * @brief LPSPI slave transfer data using an interrupt method. - * - * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. - * When all data - * is transferred, the callback function is called. - * - * Note: - * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. - * For bytesPerFrame greater than 4: - * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. - * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. - * @param transfer pointer to lpspi_transfer_t structure. - * @return status of status_t. - */ -status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer); - -/*! - * @brief Gets the slave transfer remaining bytes. - * - * This function gets the slave transfer remaining bytes. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. - * @param count Number of bytes transferred so far by the non-blocking transaction. - * @return status of status_t. - */ -status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count); - -/*! - * @brief LPSPI slave aborts a transfer which uses an interrupt method. - * - * This function aborts a transfer which uses an interrupt method. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. - */ -void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle); - -/*! - * @brief LPSPI Slave IRQ handler function. - * - * This function processes the LPSPI transmit and receives an IRQ. - * - * @param base LPSPI peripheral address. - * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. - */ -void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle); - -/*! - *@} -*/ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ - /*! - *@} - */ - -#endif /*_FSL_LPSPI_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi_edma.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi_edma.c deleted file mode 100644 index cbc7af7e76..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi_edma.c +++ /dev/null @@ -1,1056 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_lpspi_edma.h" - -/*********************************************************************************************************************** -* Definitions -***********************************************************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpspi_edma" -#endif - -/*! -* @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. -*/ -typedef struct _lpspi_master_edma_private_handle -{ - LPSPI_Type *base; /*!< LPSPI peripheral base address. */ - lpspi_master_edma_handle_t *handle; /*!< lpspi_master_edma_handle_t handle */ -} lpspi_master_edma_private_handle_t; - -/*! -* @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. -*/ -typedef struct _lpspi_slave_edma_private_handle -{ - LPSPI_Type *base; /*!< LPSPI peripheral base address. */ - lpspi_slave_edma_handle_t *handle; /*!< lpspi_slave_edma_handle_t handle */ -} lpspi_slave_edma_private_handle_t; - -/*********************************************************************************************************************** -* Prototypes -***********************************************************************************************************************/ -/*! -* @brief EDMA_LpspiMasterCallback after the LPSPI master transfer completed by using EDMA. -* This is not a public API. -*/ -static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, - void *g_lpspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds); - -/*! -* @brief EDMA_LpspiSlaveCallback after the LPSPI slave transfer completed by using EDMA. -* This is not a public API. -*/ -static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, - void *g_lpspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds); - -static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); - -/*********************************************************************************************************************** -* Variables -***********************************************************************************************************************/ - -/*! @brief Pointers to lpspi edma handles for each instance. */ -static lpspi_master_edma_private_handle_t s_lpspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_LPSPI_COUNT]; -static lpspi_slave_edma_private_handle_t s_lpspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_LPSPI_COUNT]; - -/*********************************************************************************************************************** -* Code -***********************************************************************************************************************/ -static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap) -{ - assert(rxData); - - switch (bytesEachRead) - { - case 1: - if (!isByteSwap) - { - *rxData = readData; - ++rxData; - } - else - { - *rxData = readData >> 24; - ++rxData; - } - break; - - case 2: - if (!isByteSwap) - { - *rxData = readData; - ++rxData; - *rxData = readData >> 8; - ++rxData; - } - else - { - *rxData = readData >> 16; - ++rxData; - *rxData = readData >> 24; - ++rxData; - } - break; - - case 4: - - *rxData = readData; - ++rxData; - *rxData = readData >> 8; - ++rxData; - *rxData = readData >> 16; - ++rxData; - *rxData = readData >> 24; - ++rxData; - - break; - - default: - assert(false); - break; - } -} - -void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, - lpspi_master_edma_handle_t *handle, - lpspi_master_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *edmaRxRegToRxDataHandle, - edma_handle_t *edmaTxDataToTxRegHandle) -{ - assert(handle); - assert(edmaRxRegToRxDataHandle); - assert(edmaTxDataToTxRegHandle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - uint32_t instance = LPSPI_GetInstance(base); - - s_lpspiMasterEdmaPrivateHandle[instance].base = base; - s_lpspiMasterEdmaPrivateHandle[instance].handle = handle; - - handle->callback = callback; - handle->userData = userData; - - handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; - handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; -} - -status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; - uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - uint32_t temp = 0U; - - if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) - { - return kStatus_InvalidArgument; - } - - /*And since the dma transfer can not support 3 bytes .*/ - if ((bytesPerFrame % 4U) == 3) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == kLPSPI_Busy) - { - return kStatus_LPSPI_Busy; - } - - handle->state = kLPSPI_Busy; - - uint32_t instance = LPSPI_GetInstance(base); - uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); - uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); - - uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; - - /*Because DMA is fast enough , so set the RX and TX watermarks to 0 .*/ - uint8_t txWatermark = 0; - uint8_t rxWatermark = 0; - - /*Used for byte swap*/ - uint32_t dif = 0; - - uint8_t bytesLastWrite = 0; - - bool isThereExtraTxBytes = false; - - uint8_t dummyData = g_lpspiDummyData[instance]; - - edma_transfer_config_t transferConfigRx; - edma_transfer_config_t transferConfigTx; - - edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); - edma_tcd_t *softwareTCD_pcsContinuous = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU)); - - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->txRemainingByteCount = transfer->dataSize; - handle->rxRemainingByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); - handle->readRegRemainingTimes = handle->writeRegRemainingTimes; - - handle->txBuffIfNull = - ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); - - /*The TX and RX FIFO sizes are always the same*/ - handle->fifoSize = LPSPI_GetRxFifoSize(base); - - handle->isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); - handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); - - LPSPI_SetFifoWatermarks(base, txWatermark, rxWatermark); - - /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ - LPSPI_Enable(base, false); - base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); - /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ - temp = base->CFGR1; - temp &= LPSPI_CFGR1_PINCFG_MASK; - if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) - { - if (!handle->txData) - { - base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; - } - /* The 3-wire mode can't send and receive data at the same time. */ - if ((handle->txData) && (handle->rxData)) - { - return kStatus_InvalidArgument; - } - } - - /*Flush FIFO , clear status , disable all the inerrupts.*/ - LPSPI_FlushFifo(base, true, true); - LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - /* For DMA transfer , we'd better not masked the transmit data and receive data in TCR since the transfer flow is - * hard to controlled by software. - */ - base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_PCS_MASK)) | - LPSPI_TCR_CONT(handle->isPcsContinuous) | LPSPI_TCR_CONTC(0U) | LPSPI_TCR_BYSW(handle->isByteSwap) | - LPSPI_TCR_PCS(whichPcs); - - isThereExtraTxBytes = false; - handle->isThereExtraRxBytes = false; - - /*Calculate the bytes for write/read the TX/RX register each time*/ - if (bytesPerFrame <= 4) - { - handle->bytesEachWrite = bytesPerFrame; - handle->bytesEachRead = bytesPerFrame; - - handle->bytesLastRead = bytesPerFrame; - } - else - { - handle->bytesEachWrite = 4; - handle->bytesEachRead = 4; - - handle->bytesLastRead = 4; - - if ((transfer->dataSize % 4) != 0) - { - bytesLastWrite = transfer->dataSize % 4; - handle->bytesLastRead = bytesLastWrite; - - isThereExtraTxBytes = true; - - --handle->writeRegRemainingTimes; - - --handle->readRegRemainingTimes; - handle->isThereExtraRxBytes = true; - } - } - - LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - - EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiMasterCallback, - &s_lpspiMasterEdmaPrivateHandle[instance]); - - /*Rx*/ - EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); - - if (handle->rxData) - { - transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); - transferConfigRx.destOffset = 1; - } - else - { - transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); - transferConfigRx.destOffset = 0; - } - transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; - - dif = 0; - switch (handle->bytesEachRead) - { - case (1U): - transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigRx.minorLoopBytes = 1; - if (handle->isByteSwap) - { - dif = 3; - } - break; - - case (2U): - transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; - transferConfigRx.minorLoopBytes = 2; - if (handle->isByteSwap) - { - dif = 2; - } - break; - - case (4U): - transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigRx.minorLoopBytes = 4; - break; - - default: - transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigRx.minorLoopBytes = 1; - assert(false); - break; - } - - transferConfigRx.srcAddr = (uint32_t)rxAddr + dif; - transferConfigRx.srcOffset = 0; - - transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; - - /* Store the initially configured eDMA minor byte transfer count into the LPSPI handle */ - handle->nbytes = transferConfigRx.minorLoopBytes; - - EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - &transferConfigRx, NULL); - EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - kEDMA_MajorInterruptEnable); - - /*Tx*/ - EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); - - if (isThereExtraTxBytes) - { - if (handle->txData) - { - transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); - transferConfigTx.srcOffset = 1; - } - else - { - transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); - transferConfigTx.srcOffset = 0; - } - - transferConfigTx.destOffset = 0; - - transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; - - dif = 0; - switch (bytesLastWrite) - { - case (1U): - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - if (handle->isByteSwap) - { - dif = 3; - } - break; - - case (2U): - transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigTx.minorLoopBytes = 2; - if (handle->isByteSwap) - { - dif = 2; - } - break; - - default: - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - assert(false); - break; - } - - transferConfigTx.destAddr = (uint32_t)txAddr + dif; - transferConfigTx.majorLoopCounts = 1; - - EDMA_TcdReset(softwareTCD_extraBytes); - - if (handle->isPcsContinuous) - { - EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, softwareTCD_pcsContinuous); - } - else - { - EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); - } - } - - if (handle->isPcsContinuous) - { - handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK); - - transferConfigTx.srcAddr = (uint32_t) & (handle->transmitCommand); - transferConfigTx.srcOffset = 0; - - transferConfigTx.destAddr = (uint32_t) & (base->TCR); - transferConfigTx.destOffset = 0; - - transferConfigTx.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigTx.minorLoopBytes = 4; - transferConfigTx.majorLoopCounts = 1; - - EDMA_TcdReset(softwareTCD_pcsContinuous); - EDMA_TcdSetTransferConfig(softwareTCD_pcsContinuous, &transferConfigTx, NULL); - } - - if (handle->txData) - { - transferConfigTx.srcAddr = (uint32_t)(handle->txData); - transferConfigTx.srcOffset = 1; - } - else - { - transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); - transferConfigTx.srcOffset = 0; - } - - transferConfigTx.destOffset = 0; - - transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; - - dif = 0; - switch (handle->bytesEachRead) - { - case (1U): - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - if (handle->isByteSwap) - { - dif = 3; - } - break; - - case (2U): - transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigTx.minorLoopBytes = 2; - - if (handle->isByteSwap) - { - dif = 2; - } - break; - - case (4U): - transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigTx.minorLoopBytes = 4; - break; - - default: - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - assert(false); - break; - } - - transferConfigTx.destAddr = (uint32_t)txAddr + dif; - - transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; - - if (isThereExtraTxBytes) - { - EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - &transferConfigTx, softwareTCD_extraBytes); - } - else if (handle->isPcsContinuous) - { - EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - &transferConfigTx, softwareTCD_pcsContinuous); - } - else - { - EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - &transferConfigTx, NULL); - } - - EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); - EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); - - LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - LPSPI_Enable(base, true); - - return kStatus_Success; -} - -static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, - void *g_lpspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds) -{ - assert(edmaHandle); - assert(g_lpspiEdmaPrivateHandle); - - uint32_t readData; - - lpspi_master_edma_private_handle_t *lpspiEdmaPrivateHandle; - - lpspiEdmaPrivateHandle = (lpspi_master_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; - - LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); - - if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) - { - while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0) - { - } - readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); - - if (lpspiEdmaPrivateHandle->handle->rxData) - { - LPSPI_SeparateEdmaReadData( - &(lpspiEdmaPrivateHandle->handle->rxData[lpspiEdmaPrivateHandle->handle->rxRemainingByteCount - - lpspiEdmaPrivateHandle->handle->bytesLastRead]), - readData, lpspiEdmaPrivateHandle->handle->bytesLastRead, lpspiEdmaPrivateHandle->handle->isByteSwap); - } - } - - lpspiEdmaPrivateHandle->handle->state = kLPSPI_Idle; - - if (lpspiEdmaPrivateHandle->handle->callback) - { - lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, - kStatus_Success, lpspiEdmaPrivateHandle->handle->userData); - } -} - -void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle) -{ - assert(handle); - - LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - - EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); - EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); - - handle->state = kLPSPI_Idle; -} - -status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kLPSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t remainingByte; - - remainingByte = - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, - handle->edmaRxRegToRxDataHandle->channel); - - *count = handle->totalByteCount - remainingByte; - - return kStatus_Success; -} - -void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, - lpspi_slave_edma_handle_t *handle, - lpspi_slave_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *edmaRxRegToRxDataHandle, - edma_handle_t *edmaTxDataToTxRegHandle) -{ - assert(handle); - assert(edmaRxRegToRxDataHandle); - assert(edmaTxDataToTxRegHandle); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - uint32_t instance = LPSPI_GetInstance(base); - - s_lpspiSlaveEdmaPrivateHandle[instance].base = base; - s_lpspiSlaveEdmaPrivateHandle[instance].handle = handle; - - handle->callback = callback; - handle->userData = userData; - - handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; - handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; -} - -status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; - uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - uint32_t temp = 0U; - - uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; - - if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) - { - return kStatus_InvalidArgument; - } - - /*And since the dma transfer can not support 3 bytes .*/ - if ((bytesPerFrame % 4U) == 3) - { - return kStatus_InvalidArgument; - } - - /* Check that we're not busy.*/ - if (handle->state == kLPSPI_Busy) - { - return kStatus_LPSPI_Busy; - } - - handle->state = kLPSPI_Busy; - - uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); - uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); - - edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); - - uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; - - /*Because DMA is fast enough , so set the RX and TX watermarks to 0 .*/ - uint8_t txWatermark = 0; - uint8_t rxWatermark = 0; - - /*Used for byte swap*/ - uint32_t dif = 0; - - uint8_t bytesLastWrite = 0; - - uint32_t instance = LPSPI_GetInstance(base); - - edma_transfer_config_t transferConfigRx; - edma_transfer_config_t transferConfigTx; - - bool isThereExtraTxBytes = false; - - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; - handle->txRemainingByteCount = transfer->dataSize; - handle->rxRemainingByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; - - handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); - handle->readRegRemainingTimes = handle->writeRegRemainingTimes; - - handle->txBuffIfNull = - ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); - - /*The TX and RX FIFO sizes are always the same*/ - handle->fifoSize = LPSPI_GetRxFifoSize(base); - - handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); - - LPSPI_SetFifoWatermarks(base, txWatermark, rxWatermark); - - /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ - LPSPI_Enable(base, false); - base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); - /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ - temp = base->CFGR1; - temp &= LPSPI_CFGR1_PINCFG_MASK; - if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) - { - if (!handle->txData) - { - base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; - } - /* The 3-wire mode can't send and receive data at the same time. */ - if ((handle->txData) && (handle->rxData)) - { - return kStatus_InvalidArgument; - } - } - - /*Flush FIFO , clear status , disable all the inerrupts.*/ - LPSPI_FlushFifo(base, true, true); - LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); - LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); - - /* For DMA transfer , we'd better not masked the transmit data and receive data in TCR since the transfer flow is - * hard to controlled by software. - */ - base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK)) | - LPSPI_TCR_CONTC(0U) | LPSPI_TCR_BYSW(handle->isByteSwap) | LPSPI_TCR_PCS(whichPcs); - - isThereExtraTxBytes = false; - handle->isThereExtraRxBytes = false; - - /*Calculate the bytes for write/read the TX/RX register each time*/ - if (bytesPerFrame <= 4) - { - handle->bytesEachWrite = bytesPerFrame; - handle->bytesEachRead = bytesPerFrame; - - handle->bytesLastRead = bytesPerFrame; - } - else - { - handle->bytesEachWrite = 4; - handle->bytesEachRead = 4; - - handle->bytesLastRead = 4; - - if ((transfer->dataSize % 4) != 0) - { - bytesLastWrite = transfer->dataSize % 4; - handle->bytesLastRead = bytesLastWrite; - - isThereExtraTxBytes = true; - --handle->writeRegRemainingTimes; - - handle->isThereExtraRxBytes = true; - --handle->readRegRemainingTimes; - } - } - - LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - - EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiSlaveCallback, - &s_lpspiSlaveEdmaPrivateHandle[instance]); - - /*Rx*/ - if (handle->readRegRemainingTimes > 0) - { - EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); - - if (handle->rxData) - { - transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); - transferConfigRx.destOffset = 1; - } - else - { - transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); - transferConfigRx.destOffset = 0; - } - transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; - - dif = 0; - switch (handle->bytesEachRead) - { - case (1U): - transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigRx.minorLoopBytes = 1; - if (handle->isByteSwap) - { - dif = 3; - } - break; - - case (2U): - transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; - transferConfigRx.minorLoopBytes = 2; - if (handle->isByteSwap) - { - dif = 2; - } - break; - - case (4U): - transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigRx.minorLoopBytes = 4; - break; - - default: - transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigRx.minorLoopBytes = 1; - assert(false); - break; - } - - transferConfigRx.srcAddr = (uint32_t)rxAddr + dif; - transferConfigRx.srcOffset = 0; - - transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; - - /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ - handle->nbytes = transferConfigRx.minorLoopBytes; - - EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - &transferConfigRx, NULL); - EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, - kEDMA_MajorInterruptEnable); - } - - /*Tx*/ - EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); - - if (isThereExtraTxBytes) - { - if (handle->txData) - { - transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); - transferConfigTx.srcOffset = 1; - } - else - { - transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); - transferConfigTx.srcOffset = 0; - } - - transferConfigTx.destOffset = 0; - - transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; - - dif = 0; - switch (bytesLastWrite) - { - case (1U): - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - if (handle->isByteSwap) - { - dif = 3; - } - break; - - case (2U): - transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigTx.minorLoopBytes = 2; - if (handle->isByteSwap) - { - dif = 2; - } - break; - - default: - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - assert(false); - break; - } - - transferConfigTx.destAddr = (uint32_t)txAddr + dif; - transferConfigTx.majorLoopCounts = 1; - - EDMA_TcdReset(softwareTCD_extraBytes); - - EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); - } - - if (handle->txData) - { - transferConfigTx.srcAddr = (uint32_t)(handle->txData); - transferConfigTx.srcOffset = 1; - } - else - { - transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); - transferConfigTx.srcOffset = 0; - } - - transferConfigTx.destOffset = 0; - - transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; - - dif = 0; - switch (handle->bytesEachRead) - { - case (1U): - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - if (handle->isByteSwap) - { - dif = 3; - } - break; - - case (2U): - transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigTx.minorLoopBytes = 2; - - if (handle->isByteSwap) - { - dif = 2; - } - break; - - case (4U): - transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigTx.minorLoopBytes = 4; - break; - - default: - transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; - assert(false); - break; - } - - transferConfigTx.destAddr = (uint32_t)txAddr + dif; - - transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; - - if (isThereExtraTxBytes) - { - EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - &transferConfigTx, softwareTCD_extraBytes); - } - else - { - EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, - &transferConfigTx, NULL); - } - - EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); - EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); - - LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - LPSPI_Enable(base, true); - - return kStatus_Success; -} - -static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, - void *g_lpspiEdmaPrivateHandle, - bool transferDone, - uint32_t tcds) -{ - assert(edmaHandle); - assert(g_lpspiEdmaPrivateHandle); - - uint32_t readData; - - lpspi_slave_edma_private_handle_t *lpspiEdmaPrivateHandle; - - lpspiEdmaPrivateHandle = (lpspi_slave_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; - - LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); - - if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) - { - while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0) - { - } - readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); - - if (lpspiEdmaPrivateHandle->handle->rxData) - { - LPSPI_SeparateEdmaReadData( - &(lpspiEdmaPrivateHandle->handle->rxData[lpspiEdmaPrivateHandle->handle->rxRemainingByteCount - - lpspiEdmaPrivateHandle->handle->bytesLastRead]), - readData, lpspiEdmaPrivateHandle->handle->bytesLastRead, lpspiEdmaPrivateHandle->handle->isByteSwap); - } - } - - lpspiEdmaPrivateHandle->handle->state = kLPSPI_Idle; - - if (lpspiEdmaPrivateHandle->handle->callback) - { - lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, - kStatus_Success, lpspiEdmaPrivateHandle->handle->userData); - } -} - -void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle) -{ - assert(handle); - - LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - - EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); - EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); - - handle->state = kLPSPI_Idle; -} - -status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - if (!count) - { - return kStatus_InvalidArgument; - } - - /* Catch when there is not an active transfer. */ - if (handle->state != kLPSPI_Busy) - { - *count = 0; - return kStatus_NoTransferInProgress; - } - - size_t remainingByte; - - remainingByte = - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, - handle->edmaRxRegToRxDataHandle->channel); - - *count = handle->totalByteCount - remainingByte; - - return kStatus_Success; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi_edma.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi_edma.h deleted file mode 100644 index 54b71bed43..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi_edma.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LPSPI_EDMA_H_ -#define _FSL_LPSPI_EDMA_H_ - -#include "fsl_lpspi.h" -#include "fsl_edma.h" - -/*! - * @addtogroup lpspi_edma_driver - * @{ - */ - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -/*! @name Driver version */ -/*@{*/ -/*! @brief LPSPI EDMA driver version 2.0.2. */ -#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! -* @brief Forward declaration of the _lpspi_master_edma_handle typedefs. -*/ -typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t; - -/*! -* @brief Forward declaration of the _lpspi_slave_edma_handle typedefs. -*/ -typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t; - -/*! - * @brief Completion callback function pointer type. - * - * @param base LPSPI peripheral base address. - * @param handle Pointer to the handle for the LPSPI master. - * @param status Success or error code describing whether the transfer completed. - * @param userData Arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, - lpspi_master_edma_handle_t *handle, - status_t status, - void *userData); -/*! - * @brief Completion callback function pointer type. - * - * @param base LPSPI peripheral base address. - * @param handle Pointer to the handle for the LPSPI slave. - * @param status Success or error code describing whether the transfer completed. - * @param userData Arbitrary pointer-dataSized value passed from the application. - */ -typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, - lpspi_slave_edma_handle_t *handle, - status_t status, - void *userData); - -/*! @brief LPSPI master eDMA transfer handle structure used for transactional API. */ -struct _lpspi_master_edma_handle -{ - volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ - - volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ - - volatile uint8_t fifoSize; /*!< FIFO dataSize. */ - - volatile uint8_t rxWatermark; /*!< Rx watermark. */ - - volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ - volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ - - volatile uint8_t bytesLastRead; /*!< Bytes for last read RDR. */ - volatile uint8_t isThereExtraRxBytes; /*!< Is there extra RX byte. */ - - uint8_t *volatile txData; /*!< Send buffer. */ - uint8_t *volatile rxData; /*!< Receive buffer. */ - volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ - volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ - - volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ - volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ - - uint32_t totalByteCount; /*!< Number of transfer bytes*/ - - uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/ - uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/ - - uint32_t transmitCommand; /*!< Used to write TCR for DMA purpose.*/ - - volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ - - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - - lpspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */ - void *userData; /*!< Callback user data. */ - - edma_handle_t *edmaRxRegToRxDataHandle; /*!rxRingBufferTail > handle->rxRingBufferHead) - { - size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); - } - else - { - size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); - } - - return size; -} - -static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - bool full; - - if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - return full; -} - -static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) -{ - assert(data); - - size_t i; - - /* The Non Blocking write data API assume user have ensured there is enough space in - peripheral to write. */ - for (i = 0; i < length; i++) - { - base->DATA = data[i]; - } -} - -static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) -{ - assert(data); - - size_t i; -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - uint32_t ctrl = base->CTRL; - bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); -#endif - - /* The Non Blocking read data API assume user have ensured there is enough space in - peripheral to write. */ - for (i = 0; i < length; i++) - { -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - if (isSevenDataBits) - { - data[i] = (base->DATA & 0x7F); - } - else - { - data[i] = base->DATA; - } -#else - data[i] = base->DATA; -#endif - } -} - -status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) -{ - assert(config); - assert(config->baudRate_Bps); -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark); - assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark); -#endif - - uint32_t temp; - uint16_t sbr, sbrTemp; - uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; - - /* This LPUART instantiation uses a slightly different baud rate calculation - * The idea is to use the best OSR (over-sampling rate) possible - * Note, OSR is typically hard-set to 16 in other LPUART instantiations - * loop to find the best OSR value possible, one that generates minimum baudDiff - * iterate through the rest of the supported values of OSR */ - - baudDiff = config->baudRate_Bps; - osr = 0; - sbr = 0; - for (osrTemp = 4; osrTemp <= 32; osrTemp++) - { - /* calculate the temporary sbr value */ - sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp)); - /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ - if (sbrTemp == 0) - { - sbrTemp = 1; - } - /* Calculate the baud rate based on the temporary OSR and SBR values */ - calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); - - tempDiff = calculatedBaud - config->baudRate_Bps; - - /* Select the better value between srb and (sbr + 1) */ - if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) - { - tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); - sbrTemp++; - } - - if (tempDiff <= baudDiff) - { - baudDiff = tempDiff; - osr = osrTemp; /* update and store the best OSR value calculated */ - sbr = sbrTemp; /* update store the best SBR value calculated */ - } - } - - /* Check to see if actual baud rate is within 3% of desired baud rate - * based on the best calculate OSR value */ - if (baudDiff > ((config->baudRate_Bps / 100) * 3)) - { - /* Unacceptable baud rate difference of more than 3%*/ - return kStatus_LPUART_BaudrateNotSupport; - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - - uint32_t instance = LPUART_GetInstance(base); - - /* Enable lpuart clock */ - CLOCK_EnableClock(s_lpuartClock[instance]); -#if defined(LPUART_PERIPH_CLOCKS) - CLOCK_EnableClock(s_lpuartPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL - /*Reset all internal logic and registers, except the Global Register */ - LPUART_SoftwareReset(base); -#else - /* Disable LPUART TX RX before setting. */ - base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); -#endif - - temp = base->BAUD; - - /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. - * If so, then "BOTHEDGE" sampling must be turned on */ - if ((osr > 3) && (osr < 8)) - { - temp |= LPUART_BAUD_BOTHEDGE_MASK; - } - - /* program the osr value (bit value is one less than actual value) */ - temp &= ~LPUART_BAUD_OSR_MASK; - temp |= LPUART_BAUD_OSR(osr - 1); - - /* write the sbr value to the BAUD registers */ - temp &= ~LPUART_BAUD_SBR_MASK; - base->BAUD = temp | LPUART_BAUD_SBR(sbr); - - /* Set bit count and parity mode. */ - base->BAUD &= ~LPUART_BAUD_M10_MASK; - - temp = base->CTRL & - ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | - LPUART_CTRL_IDLECFG_MASK); - - temp |= - (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | LPUART_CTRL_ILT(config->rxIdleType); - -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - if (kLPUART_SevenDataBits == config->dataBitsCount) - { - if (kLPUART_ParityDisabled != config->parityMode) - { - temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */ - } - else - { - temp |= LPUART_CTRL_M7_MASK; - } - } - else -#endif - { - if (kLPUART_ParityDisabled != config->parityMode) - { - temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */ - } - } - - base->CTRL = temp; - -#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT - /* set stop bit per char */ - temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; - base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); -#endif - -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - /* Set tx/rx WATER watermark - Note: - Take care of the RX FIFO, RX interrupt request only assert when received bytes - equal or more than RX water mark, there is potential issue if RX water - mark larger than 1. - For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and - 5 bytes are received. the last byte will be saved in FIFO but not trigger - RX interrupt because the water mark is 2. - */ - base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark); - - /* Enable tx/rx FIFO */ - base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); - - /* Flush FIFO */ - base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); -#endif - - /* Clear all status flags */ - temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | - LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); - -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - temp |= LPUART_STAT_LBKDIF_MASK; -#endif - -#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); -#endif - -#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT - /* Set the CTS configuration/TX CTS source. */ - base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource); - if (config->enableRxRTS) - { - /* Enable the receiver RTS(request-to-send) function. */ - base->MODIR |= LPUART_MODIR_RXRTSE_MASK; - } - if (config->enableTxCTS) - { - /* Enable the CTS(clear-to-send) function. */ - base->MODIR |= LPUART_MODIR_TXCTSE_MASK; - } -#endif - - /* Set data bits order. */ - if (config->isMsb) - { - temp |= LPUART_STAT_MSBF_MASK; - } - else - { - temp &= ~LPUART_STAT_MSBF_MASK; - } - - base->STAT |= temp; - - /* Enable TX/RX base on configure structure. */ - temp = base->CTRL; - if (config->enableTx) - { - temp |= LPUART_CTRL_TE_MASK; - } - - if (config->enableRx) - { - temp |= LPUART_CTRL_RE_MASK; - } - - base->CTRL = temp; - - return kStatus_Success; -} -void LPUART_Deinit(LPUART_Type *base) -{ - uint32_t temp; - -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - /* Wait tx FIFO send out*/ - while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) - { - } -#endif - /* Wait last char shoft out */ - while (0 == (base->STAT & LPUART_STAT_TC_MASK)) - { - } - - /* Clear all status flags */ - temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | - LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); - -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - temp |= LPUART_STAT_LBKDIF_MASK; -#endif - -#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); -#endif - - base->STAT |= temp; - - /* Disable the module. */ - base->CTRL = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - uint32_t instance = LPUART_GetInstance(base); - - /* Disable lpuart clock */ - CLOCK_DisableClock(s_lpuartClock[instance]); - -#if defined(LPUART_PERIPH_CLOCKS) - CLOCK_DisableClock(s_lpuartPeriphClocks[instance]); -#endif - -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void LPUART_GetDefaultConfig(lpuart_config_t *config) -{ - assert(config); - - config->baudRate_Bps = 115200U; - config->parityMode = kLPUART_ParityDisabled; - config->dataBitsCount = kLPUART_EightDataBits; - config->isMsb = false; -#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT - config->stopBitCount = kLPUART_OneStopBit; -#endif -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - config->txFifoWatermark = 0; - config->rxFifoWatermark = 0; -#endif -#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT - config->enableRxRTS = false; - config->enableTxCTS = false; - config->txCtsConfig = kLPUART_CtsSampleAtStart; - config->txCtsSource = kLPUART_CtsSourcePin; -#endif - config->rxIdleType = kLPUART_IdleTypeStartBit; - config->rxIdleConfig = kLPUART_IdleCharacter1; - config->enableTx = false; - config->enableRx = false; -} - -status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) -{ - assert(baudRate_Bps); - - uint32_t temp, oldCtrl; - uint16_t sbr, sbrTemp; - uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; - - /* This LPUART instantiation uses a slightly different baud rate calculation - * The idea is to use the best OSR (over-sampling rate) possible - * Note, OSR is typically hard-set to 16 in other LPUART instantiations - * loop to find the best OSR value possible, one that generates minimum baudDiff - * iterate through the rest of the supported values of OSR */ - - baudDiff = baudRate_Bps; - osr = 0; - sbr = 0; - for (osrTemp = 4; osrTemp <= 32; osrTemp++) - { - /* calculate the temporary sbr value */ - sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp)); - /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ - if (sbrTemp == 0) - { - sbrTemp = 1; - } - /* Calculate the baud rate based on the temporary OSR and SBR values */ - calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); - - tempDiff = calculatedBaud - baudRate_Bps; - - /* Select the better value between srb and (sbr + 1) */ - if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) - { - tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); - sbrTemp++; - } - - if (tempDiff <= baudDiff) - { - baudDiff = tempDiff; - osr = osrTemp; /* update and store the best OSR value calculated */ - sbr = sbrTemp; /* update store the best SBR value calculated */ - } - } - - /* Check to see if actual baud rate is within 3% of desired baud rate - * based on the best calculate OSR value */ - if (baudDiff < ((baudRate_Bps / 100) * 3)) - { - /* Store CTRL before disable Tx and Rx */ - oldCtrl = base->CTRL; - - /* Disable LPUART TX RX before setting. */ - base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); - - temp = base->BAUD; - - /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. - * If so, then "BOTHEDGE" sampling must be turned on */ - if ((osr > 3) && (osr < 8)) - { - temp |= LPUART_BAUD_BOTHEDGE_MASK; - } - - /* program the osr value (bit value is one less than actual value) */ - temp &= ~LPUART_BAUD_OSR_MASK; - temp |= LPUART_BAUD_OSR(osr - 1); - - /* write the sbr value to the BAUD registers */ - temp &= ~LPUART_BAUD_SBR_MASK; - base->BAUD = temp | LPUART_BAUD_SBR(sbr); - - /* Restore CTRL. */ - base->CTRL = oldCtrl; - - return kStatus_Success; - } - else - { - /* Unacceptable baud rate difference of more than 3%*/ - return kStatus_LPUART_BaudrateNotSupport; - } -} - -void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) -{ - base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | - ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); -#endif - mask &= 0xFFFFFF00U; - base->CTRL |= mask; -} - -void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) -{ - base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & - ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); -#endif - mask &= 0xFFFFFF00U; - base->CTRL &= ~mask; -} - -uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) -{ - uint32_t temp; - temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8; -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8; -#endif - temp |= (base->CTRL & 0xFF0C000); - - return temp; -} - -uint32_t LPUART_GetStatusFlags(LPUART_Type *base) -{ - uint32_t temp; - temp = base->STAT; -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - temp |= (base->FIFO & - (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> - 16; -#endif - return temp; -} - -status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) -{ - uint32_t temp; - status_t status; -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - temp = (uint32_t)base->FIFO; - temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)); - temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); - base->FIFO = temp; -#endif - temp = (uint32_t)base->STAT; -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK)); - temp |= mask & LPUART_STAT_LBKDIF_MASK; -#endif - temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | - LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK)); - temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | - LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); -#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK)); - temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK); -#endif - base->STAT = temp; - /* If some flags still pending. */ - if (mask & LPUART_GetStatusFlags(base)) - { - /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag, - kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, - kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, - kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */ - status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */ - } - else - { - status = kStatus_Success; - } - - return status; -} - -void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) -{ - assert(data); - - /* This API can only ensure that the data is written into the data buffer but can't - ensure all data in the data buffer are sent into the transmit shift buffer. */ - while (length--) - { - while (!(base->STAT & LPUART_STAT_TDRE_MASK)) - { - } - base->DATA = *(data++); - } -} - -status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) -{ - assert(data); - - uint32_t statusFlag; -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - uint32_t ctrl = base->CTRL; - bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); -#endif - - while (length--) - { -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) -#else - while (!(base->STAT & LPUART_STAT_RDRF_MASK)) -#endif - { - statusFlag = LPUART_GetStatusFlags(base); - - if (statusFlag & kLPUART_RxOverrunFlag) - { - LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); - return kStatus_LPUART_RxHardwareOverrun; - } - - if (statusFlag & kLPUART_NoiseErrorFlag) - { - LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag); - return kStatus_LPUART_NoiseError; - } - - if (statusFlag & kLPUART_FramingErrorFlag) - { - LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag); - return kStatus_LPUART_FramingError; - } - - if (statusFlag & kLPUART_ParityErrorFlag) - { - LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag); - return kStatus_LPUART_ParityError; - } - } -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - if (isSevenDataBits) - { - *(data++) = (base->DATA & 0x7F); - } - else - { - *(data++) = base->DATA; - } -#else - *(data++) = base->DATA; -#endif - } - - return kStatus_Success; -} - -void LPUART_TransferCreateHandle(LPUART_Type *base, - lpuart_handle_t *handle, - lpuart_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - uint32_t instance; -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - uint32_t ctrl = base->CTRL; - bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); -#endif - - /* Zero the handle. */ - memset(handle, 0, sizeof(lpuart_handle_t)); - - /* Set the TX/RX state. */ - handle->rxState = kLPUART_RxIdle; - handle->txState = kLPUART_TxIdle; - - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - /* Initial seven data bits flag */ - handle->isSevenDataBits = isSevenDataBits; -#endif - - /* Get instance from peripheral base address. */ - instance = LPUART_GetInstance(base); - - /* Save the handle in global variables to support the double weak mechanism. */ - s_lpuartHandle[instance] = handle; - - s_lpuartIsr = LPUART_TransferHandleIRQ; - -/* Enable interrupt in NVIC. */ -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ - EnableIRQ(s_lpuartRxIRQ[instance]); - EnableIRQ(s_lpuartTxIRQ[instance]); -#else - EnableIRQ(s_lpuartIRQ[instance]); -#endif -} - -void LPUART_TransferStartRingBuffer(LPUART_Type *base, - lpuart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize) -{ - assert(handle); - assert(ringBuffer); - - /* Setup the ring buffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - - /* Enable the interrupt to accept the data when user need the ring buffer. */ - LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); -} - -void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - if (handle->rxState == kLPUART_RxIdle) - { - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) -{ - assert(handle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - status_t status; - - /* Return error if current TX busy. */ - if (kLPUART_TxBusy == handle->txState) - { - status = kStatus_LPUART_TxBusy; - } - else - { - handle->txData = xfer->data; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = kLPUART_TxBusy; - - /* Enable transmiter interrupt. */ - LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable); - - status = kStatus_Success; - } - - return status; -} - -void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable); - - handle->txDataSize = 0; - handle->txState = kLPUART_TxIdle; -} - -status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(count); - - if (kLPUART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize; - - return kStatus_Success; -} - -status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, - lpuart_handle_t *handle, - lpuart_transfer_t *xfer, - size_t *receivedBytes) -{ - assert(handle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - uint32_t i; - status_t status; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to lpuart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to lpuart handle, receive data - to this empty space and trigger callback when finished. */ - - if (kLPUART_RxBusy == handle->rxState) - { - status = kStatus_LPUART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0; - - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer) - { - /* Disable LPUART RX IRQ, protect ring buffer. */ - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable); - - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); - - if (bytesToCopy) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - - bytesToReceive -= bytesToCopy; - - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive) - { - /* No data in ring buffer, save the request to LPUART handle. */ - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kLPUART_RxBusy; - } - /* Enable LPUART RX IRQ if previously enabled. */ - LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable); - - /* Call user callback since all data are received. */ - if (0 == bytesToReceive) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kLPUART_RxBusy; - - /* Enable RX interrupt. */ - LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable | - kLPUART_IdleLineInterruptEnable); - } - - /* Return the how many bytes have read. */ - if (receivedBytes) - { - *receivedBytes = bytesCurrentReceived; - } - - status = kStatus_Success; - } - - return status; -} - -void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (!handle->rxRingBuffer) - { - /* Disable RX interrupt. */ - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable | - kLPUART_IdleLineInterruptEnable); - } - - handle->rxDataSize = 0U; - handle->rxState = kLPUART_RxIdle; -} - -status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(count); - - if (kLPUART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) -{ - assert(handle); - - uint8_t count; - uint8_t tempCount; - - /* If RX overrun. */ - if (LPUART_STAT_OR_MASK & base->STAT) - { - /* Clear overrun flag, otherwise the RX does not work. */ - base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); - - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); - } - } - - /* If IDLE flag is set and the IDLE interrupt is enabled. */ - if ((LPUART_STAT_IDLE_MASK & base->STAT) && (LPUART_CTRL_ILIE_MASK & base->CTRL)) - { -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); - - while ((count) && (handle->rxDataSize)) - { - tempCount = MIN(handle->rxDataSize, count); - - /* Using non block API to read the data from the registers. */ - LPUART_ReadNonBlocking(base, handle->rxData, tempCount); - handle->rxData += tempCount; - handle->rxDataSize -= tempCount; - count -= tempCount; - - /* If rxDataSize is 0, disable idle line interrupt.*/ - if (!(handle->rxDataSize)) - { - handle->rxState = kLPUART_RxIdle; - - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); - } - } - } -#endif - /* Clear IDLE flag.*/ - base->STAT |= LPUART_STAT_IDLE_MASK; - - /* If rxDataSize is 0, disable idle line interrupt.*/ - if (!(handle->rxDataSize)) - { - LPUART_DisableInterrupts(base, kLPUART_IdleLineInterruptEnable); - } - /* If callback is not NULL and rxDataSize is not 0. */ - if ((handle->callback) && (handle->rxDataSize)) - { - handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData); - } - } - /* Receive data register full */ - if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL)) - { -/* Get the size that can be stored into buffer for this interrupt. */ -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); -#else - count = 1; -#endif - - /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ - while ((count) && (handle->rxDataSize)) - { -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - tempCount = MIN(handle->rxDataSize, count); -#else - tempCount = 1; -#endif - - /* Using non block API to read the data from the registers. */ - LPUART_ReadNonBlocking(base, handle->rxData, tempCount); - handle->rxData += tempCount; - handle->rxDataSize -= tempCount; - count -= tempCount; - - /* If all the data required for upper layer is ready, trigger callback. */ - if (!handle->rxDataSize) - { - handle->rxState = kLPUART_RxIdle; - - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); - } - } - } - - /* If use RX ring buffer, receive data to ring buffer. */ - if (handle->rxRingBuffer) - { - while (count--) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (LPUART_TransferIsRxRingBufferFull(base, handle)) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); - } - } - - /* If ring buffer is still full after callback function, the oldest data is overrided. */ - if (LPUART_TransferIsRxRingBufferFull(base, handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - -/* Read data. */ -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - if (handle->isSevenDataBits) - { - handle->rxRingBuffer[handle->rxRingBufferHead] = (base->DATA & 0x7F); - } - else - { - handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA; - } -#else - handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA; -#endif - - /* Increase handle->rxRingBufferHead. */ - if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - /* If no receive requst pending, stop RX interrupt. */ - else if (!handle->rxDataSize) - { - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - } - else - { - } - } - - /* Send data register empty and the interrupt is enabled. */ - if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK)) - { -/* Get the bytes that available at this moment. */ -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) - - ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); -#else - count = 1; -#endif - - while ((count) && (handle->txDataSize)) - { -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - tempCount = MIN(handle->txDataSize, count); -#else - tempCount = 1; -#endif - - /* Using non block API to write the data to the registers. */ - LPUART_WriteNonBlocking(base, handle->txData, tempCount); - handle->txData += tempCount; - handle->txDataSize -= tempCount; - count -= tempCount; - - /* If all the data are written to data register, notify user with the callback, then TX finished. */ - if (!handle->txDataSize) - { - handle->txState = kLPUART_TxIdle; - - /* Disable TX register empty interrupt. */ - base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK); - - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); - } - } - } - } -} - -void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle) -{ - /* To be implemented by User. */ -} -#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART0_LPUART1_RX_DriverIRQHandler(void) -{ - if (CLOCK_isEnabledClock(s_lpuartClock[0])) - { - if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || - ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL))) - { - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); - } - } - if (CLOCK_isEnabledClock(s_lpuartClock[1])) - { - if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || - ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL))) - { - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); - } - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -void LPUART0_LPUART1_TX_DriverIRQHandler(void) -{ - if (CLOCK_isEnabledClock(s_lpuartClock[0])) - { - if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || - ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK))) - { - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); - } - } - if (CLOCK_isEnabledClock(s_lpuartClock[1])) - { - if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || - ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK))) - { - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); - } - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#else -void LPUART0_LPUART1_DriverIRQHandler(void) -{ - if (CLOCK_isEnabledClock(s_lpuartClock[0])) - { - if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || - ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)) || - ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK))) - { - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); - } - } - if (CLOCK_isEnabledClock(s_lpuartClock[1])) - { - if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || - ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)) || - ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK))) - { - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); - } - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif - -#if defined(LPUART0) -#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART0_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -void LPUART0_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#else -void LPUART0_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif -#endif - -#if defined(LPUART1) -#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART1_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -void LPUART1_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#else -void LPUART1_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif -#endif - -#if defined(LPUART2) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART2_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART2, s_lpuartHandle[2]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -void LPUART2_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART2, s_lpuartHandle[2]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#else -void LPUART2_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART2, s_lpuartHandle[2]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif - -#if defined(LPUART3) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART3_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART3, s_lpuartHandle[3]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -void LPUART3_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART3, s_lpuartHandle[3]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#else -void LPUART3_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART3, s_lpuartHandle[3]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif - -#if defined(LPUART4) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART4_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART4, s_lpuartHandle[4]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -void LPUART4_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART4, s_lpuartHandle[4]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#else -void LPUART4_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART4, s_lpuartHandle[4]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif - -#if defined(LPUART5) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART5_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART5, s_lpuartHandle[5]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -void LPUART5_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART5, s_lpuartHandle[5]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#else -void LPUART5_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART5, s_lpuartHandle[5]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif - -#if defined(LPUART6) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART6_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART6, s_lpuartHandle[6]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -void LPUART6_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART6, s_lpuartHandle[6]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#else -void LPUART6_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART6, s_lpuartHandle[6]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif - -#if defined(LPUART7) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART7_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART7, s_lpuartHandle[7]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -void LPUART7_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART7, s_lpuartHandle[7]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#else -void LPUART7_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART7, s_lpuartHandle[7]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif - -#if defined(LPUART8) -#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ -void LPUART8_TX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART8, s_lpuartHandle[8]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -void LPUART8_RX_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART8, s_lpuartHandle[8]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#else -void LPUART8_DriverIRQHandler(void) -{ - s_lpuartIsr(LPUART8, s_lpuartHandle[8]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif -#endif - -#if defined(CM4_0__LPUART) -void M4_0_LPUART_DriverIRQHandler(void) -{ - s_lpuartIsr(CM4_0__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0__LPUART)]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CM4_1__LPUART) -void M4_1_LPUART_DriverIRQHandler(void) -{ - s_lpuartIsr(CM4_1__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1__LPUART)]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CM4__LPUART) -void M4_LPUART_DriverIRQHandler(void) -{ - s_lpuartIsr(CM4__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4__LPUART)]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(DMA__LPUART0) -void DMA_UART0_INT_DriverIRQHandler(void) -{ - s_lpuartIsr(DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(DMA__LPUART1) -void DMA_UART1_INT_DriverIRQHandler(void) -{ - s_lpuartIsr(DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(DMA__LPUART2) -void DMA_UART2_INT_DriverIRQHandler(void) -{ - s_lpuartIsr(DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(DMA__LPUART3) -void DMA_UART3_INT_DriverIRQHandler(void) -{ - s_lpuartIsr(DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(DMA__LPUART4) -void DMA_UART4_INT_DriverIRQHandler(void) -{ - s_lpuartIsr(DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(ADMA__LPUART0) -void ADMA_UART0_INT_DriverIRQHandler(void) -{ - s_lpuartIsr(ADMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART0)]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(ADMA__LPUART1) -void ADMA_UART1_INT_DriverIRQHandler(void) -{ - s_lpuartIsr(ADMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART1)]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(ADMA__LPUART2) -void ADMA_UART2_INT_DriverIRQHandler(void) -{ - s_lpuartIsr(ADMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART2)]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(ADMA__LPUART3) -void ADMA_UART3_INT_DriverIRQHandler(void) -{ - s_lpuartIsr(ADMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART3)]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpuart.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpuart.h deleted file mode 100644 index 395c27a68d..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpuart.h +++ /dev/null @@ -1,880 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LPUART_H_ -#define _FSL_LPUART_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpuart_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPUART driver version 2.2.5. */ -#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 5)) -/*@}*/ - -/*! @brief Error codes for the LPUART driver. */ -enum _lpuart_status -{ - kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ - kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ - kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ - kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ - kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ - kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ - kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ - kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ - kStatus_LPUART_RxRingBufferOverrun = - MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ - kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ - kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ - kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ - kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ - kStatus_LPUART_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ - kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */ -}; - -/*! @brief LPUART parity mode. */ -typedef enum _lpuart_parity_mode -{ - kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ -} lpuart_parity_mode_t; - -/*! @brief LPUART data bits count. */ -typedef enum _lpuart_data_bits -{ - kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */ -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */ -#endif -} lpuart_data_bits_t; - -/*! @brief LPUART stop bit count. */ -typedef enum _lpuart_stop_bit_count -{ - kLPUART_OneStopBit = 0U, /*!< One stop bit */ - kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ -} lpuart_stop_bit_count_t; - -#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT -/*! @brief LPUART transmit CTS source. */ -typedef enum _lpuart_transmit_cts_source -{ - kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ - kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */ -} lpuart_transmit_cts_source_t; - -/*! @brief LPUART transmit CTS configure. */ -typedef enum _lpuart_transmit_cts_config -{ - kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */ - kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ -} lpuart_transmit_cts_config_t; -#endif - -/*! @brief LPUART idle flag type defines when the receiver starts counting. */ -typedef enum _lpuart_idle_type_select -{ - kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ - kLPUART_IdleTypeStopBit = 1U, /*!< Start conuting after a stop bit. */ -} lpuart_idle_type_select_t; - -/*! @brief LPUART idle detected configuration. - * This structure defines the number of idle characters that must be received before - * the IDLE flag is set. - */ -typedef enum _lpuart_idle_config -{ - kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */ -} lpuart_idle_config_t; - -/*! - * @brief LPUART interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all LPUART interrupt configurations. - */ -enum _lpuart_interrupt_enable -{ -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */ -#endif - kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */ - kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */ - kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */ - kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */ - kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */ - kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */ - kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */ - kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */ - kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */ -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */ - kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */ -#endif -}; - -/*! - * @brief LPUART status flags. - * - * This provides constants for the LPUART status flags for use in the LPUART functions. - */ -enum _lpuart_flags -{ - kLPUART_TxDataRegEmptyFlag = - (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */ - kLPUART_TransmissionCompleteFlag = - (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */ - kLPUART_RxDataRegFullFlag = - (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */ - kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */ - kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is - read from receive register */ - kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these - samples differ, noise flag sets */ - kLPUART_FramingErrorFlag = - (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ - kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ -#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char - detected and LIN circuit enabled */ -#endif - kLPUART_RxActiveEdgeFlag = - (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */ - kLPUART_RxActiveFlag = - (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ -#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING - kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/ - kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/ -#endif -#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS - kLPUART_NoiseErrorInRxDataRegFlag = - (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */ - kLPUART_ParityErrorInRxDataRegFlag = - (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */ -#endif -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */ - kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */ - kLPUART_TxFifoOverflowFlag = - (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */ - kLPUART_RxFifoUnderflowFlag = - (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */ -#endif -}; - -/*! @brief LPUART configuration structure. */ -typedef struct _lpuart_config -{ - uint32_t baudRate_Bps; /*!< LPUART baud rate */ - lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ - bool isMsb; /*!< Data bits order, LSB (default), MSB */ -#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT - lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ -#endif -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - uint8_t txFifoWatermark; /*!< TX FIFO watermark */ - uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ -#endif -#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT - bool enableRxRTS; /*!< RX RTS enable */ - bool enableTxCTS; /*!< TX CTS enable */ - lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ - lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ -#endif - lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ - lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ - bool enableTx; /*!< Enable TX */ - bool enableRx; /*!< Enable RX */ -} lpuart_config_t; - -/*! @brief LPUART transfer structure. */ -typedef struct _lpuart_transfer -{ - uint8_t *data; /*!< The buffer of data to be transfer.*/ - size_t dataSize; /*!< The byte count to be transfer. */ -} lpuart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _lpuart_handle lpuart_handle_t; - -/*! @brief LPUART transfer callback function. */ -typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); - -/*! @brief LPUART handle structure. */ -struct _lpuart_handle -{ - uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - lpuart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< LPUART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state. */ - -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - bool isSevenDataBits; /*!< Seven data bits flag. */ -#endif -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL - -/*! - * @name Software Reset - * @{ - */ - -/*! - * @brief Resets the LPUART using software. - * - * This function resets all internal logic and registers except the Global Register. - * Remains set until cleared by software. - * - * @param base LPUART peripheral base address. - */ -static inline void LPUART_SoftwareReset(LPUART_Type *base) -{ - base->GLOBAL |= LPUART_GLOBAL_RST_MASK; - base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; -} -/* @} */ -#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. - * - * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function - * to configure the configuration structure and get the default configuration. - * The example below shows how to use this API to configure the LPUART. - * @code - * lpuart_config_t lpuartConfig; - * lpuartConfig.baudRate_Bps = 115200U; - * lpuartConfig.parityMode = kLPUART_ParityDisabled; - * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; - * lpuartConfig.isMsb = false; - * lpuartConfig.stopBitCount = kLPUART_OneStopBit; - * lpuartConfig.txFifoWatermark = 0; - * lpuartConfig.rxFifoWatermark = 1; - * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); - * @endcode - * - * @param base LPUART peripheral base address. - * @param config Pointer to a user-defined configuration structure. - * @param srcClock_Hz LPUART clock source frequency in HZ. - * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success LPUART initialize succeed - */ -status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes a LPUART instance. - * - * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. - * - * @param base LPUART peripheral base address. - */ -void LPUART_Deinit(LPUART_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the LPUART configuration structure to a default value. The default - * values are: - * lpuartConfig->baudRate_Bps = 115200U; - * lpuartConfig->parityMode = kLPUART_ParityDisabled; - * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; - * lpuartConfig->isMsb = false; - * lpuartConfig->stopBitCount = kLPUART_OneStopBit; - * lpuartConfig->txFifoWatermark = 0; - * lpuartConfig->rxFifoWatermark = 1; - * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; - * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; - * lpuartConfig->enableTx = false; - * lpuartConfig->enableRx = false; - * - * @param config Pointer to a configuration structure. - */ -void LPUART_GetDefaultConfig(lpuart_config_t *config); - -/*! - * @brief Sets the LPUART instance baudrate. - * - * This function configures the LPUART module baudrate. This function is used to update - * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. - * @code - * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); - * @endcode - * - * @param base LPUART peripheral base address. - * @param baudRate_Bps LPUART baudrate to be set. - * @param srcClock_Hz LPUART clock source frequency in HZ. - * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. - * @retval kStatus_Success Set baudrate succeeded. - */ -status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets LPUART status flags. - * - * This function gets all LPUART status flags. The flags are returned as the logical - * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, - * compare the return value with enumerators in the @ref _lpuart_flags. - * For example, to check whether the TX is empty: - * @code - * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) - * { - * ... - * } - * @endcode - * - * @param base LPUART peripheral base address. - * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. - */ -uint32_t LPUART_GetStatusFlags(LPUART_Type *base); - -/*! - * @brief Clears status flags with a provided mask. - * - * This function clears LPUART status flags with a provided mask. Automatically cleared flags - * can't be cleared by this function. - * Flags that can only cleared or set by hardware are: - * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, - * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, - * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag - * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. - * - * @param base LPUART peripheral base address. - * @param mask the status flags to be cleared. The user can use the enumerators in the - * _lpuart_status_flag_t to do the OR operation and get the mask. - * @return 0 succeed, others failed. - * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but - * it is cleared automatically by hardware. - * @retval kStatus_Success Status in the mask are cleared. - */ -status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables LPUART interrupts according to a provided mask. - * - * This function enables the LPUART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. - * This examples shows how to enable TX empty interrupt and RX full interrupt: - * @code - * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); - * @endcode - * - * @param base LPUART peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. - */ -void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); - -/*! - * @brief Disables LPUART interrupts according to a provided mask. - * - * This function disables the LPUART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. - * This example shows how to disable the TX empty interrupt and RX full interrupt: - * @code - * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); - * @endcode - * - * @param base LPUART peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. - */ -void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); - -/*! - * @brief Gets enabled LPUART interrupts. - * - * This function gets the enabled LPUART interrupts. The enabled interrupts are returned - * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check - * a specific interrupt enable status, compare the return value with enumerators - * in @ref _lpuart_interrupt_enable. - * For example, to check whether the TX empty interrupt is enabled: - * @code - * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); - * - * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) - * { - * ... - * } - * @endcode - * - * @param base LPUART peripheral base address. - * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. - */ -uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); - -#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE -/*! - * @brief Gets the LPUART data register address. - * - * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. - * - * @param base LPUART peripheral base address. - * @return LPUART data register addresses which are used both by the transmitter and receiver. - */ -static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base) -{ - return (uint32_t) & (base->DATA); -} - -/*! - * @brief Enables or disables the LPUART transmitter DMA request. - * - * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. - * - * @param base LPUART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) -{ - if (enable) - { - base->BAUD |= LPUART_BAUD_TDMAE_MASK; - } - else - { - base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; - } -} - -/*! - * @brief Enables or disables the LPUART receiver DMA. - * - * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. - * - * @param base LPUART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) -{ - if (enable) - { - base->BAUD |= LPUART_BAUD_RDMAE_MASK; - } - else - { - base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; - } -} - -/* @} */ -#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Get the LPUART instance from peripheral base address. - * - * @param base LPUART peripheral base address. - * @return LPUART instance. - */ -uint32_t LPUART_GetInstance(LPUART_Type *base); - -/*! - * @brief Enables or disables the LPUART transmitter. - * - * This function enables or disables the LPUART transmitter. - * - * @param base LPUART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= LPUART_CTRL_TE_MASK; - } - else - { - base->CTRL &= ~LPUART_CTRL_TE_MASK; - } -} - -/*! - * @brief Enables or disables the LPUART receiver. - * - * This function enables or disables the LPUART receiver. - * - * @param base LPUART peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= LPUART_CTRL_RE_MASK; - } - else - { - base->CTRL &= ~LPUART_CTRL_RE_MASK; - } -} - -/*! - * @brief Writes to the transmitter register. - * - * This function writes data to the transmitter register directly. The upper layer must - * ensure that the TX register is empty or that the TX FIFO has room before calling this function. - * - * @param base LPUART peripheral base address. - * @param data Data write to the TX register. - */ -static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) -{ - base->DATA = data; -} - -/*! - * @brief Reads the receiver register. - * - * This function reads data from the receiver register directly. The upper layer must - * ensure that the receiver register is full or that the RX FIFO has data before calling this function. - * - * @param base LPUART peripheral base address. - * @return Data read from data register. - */ -static inline uint8_t LPUART_ReadByte(LPUART_Type *base) -{ -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT - uint32_t ctrl = base->CTRL; - bool isSevenDataBits = - ((ctrl & LPUART_CTRL_M7_MASK) || - ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); - - if (isSevenDataBits) - { - return (base->DATA & 0x7F); - } - else - { - return base->DATA; - } -#else - return base->DATA; -#endif -} - -/*! - * @brief Writes to the transmitter register using a blocking method. - * - * This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have - * room, and writes data to the transmitter buffer. - * - * @note This function does not check whether all data has been sent out to the bus. - * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is - * finished. - * - * @param base LPUART peripheral base address. - * @param data Start address of the data to write. - * @param length Size of the data to write. - */ -void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); - -/*! -* @brief Reads the receiver data register using a blocking method. - * - * This function polls the receiver register, waits for the receiver register full or receiver FIFO - * has data, and reads data from the TX register. - * - * @param base LPUART peripheral base address. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. - * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. - * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. - * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. - * @retval kStatus_Success Successfully received all data. - */ -status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the LPUART handle. - * - * This function initializes the LPUART handle, which can be used for other LPUART - * transactional APIs. Usually, for a specified LPUART instance, - * call this API once to get the initialized handle. - * - * The LPUART driver supports the "background" receiving, which means that user can set up - * an RX ring buffer optionally. Data received is stored into the ring buffer even when the - * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * The ring buffer is disabled if passing NULL as @p ringBuffer. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param callback Callback function. - * @param userData User data. - */ -void LPUART_TransferCreateHandle(LPUART_Type *base, - lpuart_handle_t *handle, - lpuart_transfer_callback_t callback, - void *userData); -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function send data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data written to the transmitter register. When - * all data is written to the TX register in the ISR, the LPUART driver calls the callback - * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. - * - * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written - * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, - * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param xfer LPUART transfer structure, see #lpuart_transfer_t. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific UART handle. - * - * When the RX ring buffer is used, data received is stored into the ring buffer even when - * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * @note When using RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize size of the ring buffer. - */ -void LPUART_TransferStartRingBuffer(LPUART_Type *base, - lpuart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Get the length of received data in RX ring buffer. - * - * @userData handle LPUART handle pointer. - * @return Length of received data in RX ring buffer. - */ -size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are not sent out. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Gets the number of bytes that have been written to the LPUART transmitter register. - * - * This function gets the number of bytes that have been written to LPUART TX - * register by an interrupt method. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); - -/*! - * @brief Receives a buffer of data using the interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function - * which returns without waiting to ensure that all data are received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough for read, the receive - * request is saved by the LPUART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the LPUART driver notifies the upper layer - * through a callback function and passes a status parameter @ref kStatus_UART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. - * The 5 bytes are copied to xfer->data, which returns with the - * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is - * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to xfer->data. When all data is received, the upper layer is notified. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param xfer LPUART transfer structure, see #uart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into the transmit queue. - * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, - lpuart_handle_t *handle, - lpuart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief Gets the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); - -/*! - * @brief LPUART IRQ handle function. - * - * This function handles the LPUART transmit and receive IRQ request. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle); - -/*! - * @brief LPUART Error IRQ handle function. - * - * This function handles the LPUART error IRQ request. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - */ -void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_LPUART_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpuart_edma.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpuart_edma.c deleted file mode 100644 index add9488179..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpuart_edma.c +++ /dev/null @@ -1,380 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_lpuart_edma.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpuart_edma" -#endif - -/*base, lpuartPrivateHandle->handle); - - if (lpuartPrivateHandle->handle->callback) - { - lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, - kStatus_LPUART_TxIdle, lpuartPrivateHandle->handle->userData); - } - } -} - -static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) -{ - assert(param); - - lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param; - - /* Avoid warning for unused parameters. */ - handle = handle; - tcds = tcds; - - if (transferDone) - { - /* Disable transfer. */ - LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle); - - if (lpuartPrivateHandle->handle->callback) - { - lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, - kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); - } - } -} - -void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, - lpuart_edma_handle_t *handle, - lpuart_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txEdmaHandle, - edma_handle_t *rxEdmaHandle) -{ - assert(handle); - - uint32_t instance = LPUART_GetInstance(base); - - s_edmaPrivateHandle[instance].base = base; - s_edmaPrivateHandle[instance].handle = handle; - - memset(handle, 0, sizeof(*handle)); - - handle->rxState = kLPUART_RxIdle; - handle->txState = kLPUART_TxIdle; - - handle->rxEdmaHandle = rxEdmaHandle; - handle->txEdmaHandle = txEdmaHandle; - - handle->callback = callback; - handle->userData = userData; - -#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - /* Note: - Take care of the RX FIFO, EDMA request only assert when received bytes - equal or more than RX water mark, there is potential issue if RX water - mark larger than 1. - For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and - 5 bytes are received. the last byte will be saved in FIFO but not trigger - EDMA transfer because the water mark is 2. - */ - if (rxEdmaHandle) - { - base->WATER &= (~LPUART_WATER_RXWATER_MASK); - } -#endif - - /* Configure TX. */ - if (txEdmaHandle) - { - EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_edmaPrivateHandle[instance]); - } - - /* Configure RX. */ - if (rxEdmaHandle) - { - EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]); - } -} - -status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) -{ - assert(handle); - assert(handle->txEdmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - edma_transfer_config_t xferConfig; - status_t status; - - /* If previous TX not finished. */ - if (kLPUART_TxBusy == handle->txState) - { - status = kStatus_LPUART_TxBusy; - } - else - { - handle->txState = kLPUART_TxBusy; - handle->txDataSizeAll = xfer->dataSize; - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)LPUART_GetDataRegisterAddress(base), - sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral); - - /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ - handle->nbytes = sizeof(uint8_t); - - /* Submit transfer. */ - EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); - EDMA_StartTransfer(handle->txEdmaHandle); - - /* Enable LPUART TX EDMA. */ - LPUART_EnableTxDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) -{ - assert(handle); - assert(handle->rxEdmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); - - edma_transfer_config_t xferConfig; - status_t status; - - /* If previous RX not finished. */ - if (kLPUART_RxBusy == handle->rxState) - { - status = kStatus_LPUART_RxBusy; - } - else - { - handle->rxState = kLPUART_RxBusy; - handle->rxDataSizeAll = xfer->dataSize; - - /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data, - sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); - - /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ - handle->nbytes = sizeof(uint8_t); - - /* Submit transfer. */ - EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); - EDMA_StartTransfer(handle->rxEdmaHandle); - - /* Enable LPUART RX EDMA. */ - LPUART_EnableRxDMA(base, true); - - status = kStatus_Success; - } - - return status; -} - -void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) -{ - assert(handle); - assert(handle->txEdmaHandle); - - /* Disable LPUART TX EDMA. */ - LPUART_EnableTxDMA(base, false); - - /* Stop transfer. */ - EDMA_AbortTransfer(handle->txEdmaHandle); - - handle->txState = kLPUART_TxIdle; -} - -void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) -{ - assert(handle); - assert(handle->rxEdmaHandle); - - /* Disable LPUART RX EDMA. */ - LPUART_EnableRxDMA(base, false); - - /* Stop transfer. */ - EDMA_AbortTransfer(handle->rxEdmaHandle); - - handle->rxState = kLPUART_RxIdle; -} - -status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(handle->rxEdmaHandle); - assert(count); - - if (kLPUART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); - - return kStatus_Success; -} - -status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) -{ - assert(handle); - assert(handle->txEdmaHandle); - assert(count); - - if (kLPUART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); - - return kStatus_Success; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpuart_edma.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpuart_edma.h deleted file mode 100644 index a6f240147a..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_lpuart_edma.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_LPUART_EDMA_H_ -#define _FSL_LPUART_EDMA_H_ - -#include "fsl_lpuart.h" -#include "fsl_edma.h" - -/*! - * @addtogroup lpuart_edma_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPUART EDMA driver version 2.2.5. */ -#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 5)) -/*@}*/ - -/* Forward declaration of the handle typedef. */ -typedef struct _lpuart_edma_handle lpuart_edma_handle_t; - -/*! @brief LPUART transfer callback function. */ -typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, - lpuart_edma_handle_t *handle, - status_t status, - void *userData); - -/*! -* @brief LPUART eDMA handle -*/ -struct _lpuart_edma_handle -{ - lpuart_edma_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< LPUART callback function parameter.*/ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - - edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ - edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ - - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name eDMA transactional - * @{ - */ - -/*! - * @brief Initializes the LPUART handle which is used in transactional functions. - * @param base LPUART peripheral base address. - * @param handle Pointer to lpuart_edma_handle_t structure. - * @param callback Callback function. - * @param userData User data. - * @param txEdmaHandle User requested DMA handle for TX DMA transfer. - * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. - */ -void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, - lpuart_edma_handle_t *handle, - lpuart_edma_transfer_callback_t callback, - void *userData, - edma_handle_t *txEdmaHandle, - edma_handle_t *rxEdmaHandle); - -/*! - * @brief Sends data using eDMA. - * - * This function sends data using eDMA. This is a non-blocking function, which returns - * right away. When all data is sent, the send callback function is called. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. - * @retval kStatus_Success if succeed, others failed. - * @retval kStatus_LPUART_TxBusy Previous transfer on going. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); - -/*! - * @brief Receives data using eDMA. - * - * This function receives data using eDMA. This is non-blocking function, which returns - * right away. When all data is received, the receive callback function is called. - * - * @param base LPUART peripheral base address. - * @param handle Pointer to lpuart_edma_handle_t structure. - * @param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. - * @retval kStatus_Success if succeed, others fail. - * @retval kStatus_LPUART_RxBusy Previous transfer ongoing. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); - -/*! - * @brief Aborts the sent data using eDMA. - * - * This function aborts the sent data using eDMA. - * - * @param base LPUART peripheral base address. - * @param handle Pointer to lpuart_edma_handle_t structure. - */ -void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); - -/*! - * @brief Aborts the received data using eDMA. - * - * This function aborts the received data using eDMA. - * - * @param base LPUART peripheral base address. - * @param handle Pointer to lpuart_edma_handle_t structure. - */ -void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); - -/*! - * @brief Gets the number of bytes written to the LPUART TX register. - * - * This function gets the number of bytes written to the LPUART TX - * register by DMA. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); - -/*! - * @brief Gets the number of received bytes. - * - * This function gets the number of received bytes. - * - * @param base LPUART peripheral base address. - * @param handle LPUART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_LPUART_EDMA_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pit.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_pit.c deleted file mode 100644 index e6ff9c8745..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pit.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_pit.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.pit" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address to be used to gate or ungate the module clock - * - * @param base PIT peripheral base address - * - * @return The PIT instance - */ -static uint32_t PIT_GetInstance(PIT_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to PIT bases for each instance. */ -static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to PIT clocks for each instance. */ -static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t PIT_GetInstance(PIT_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_pitBases); instance++) - { - if (s_pitBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_pitBases)); - - return instance; -} - -void PIT_Init(PIT_Type *base, const pit_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the PIT clock*/ - CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS - /* Enable PIT timers */ - base->MCR &= ~PIT_MCR_MDIS_MASK; -#endif - /* Config timer operation when in debug mode */ - if (config->enableRunInDebug) - { - base->MCR &= ~PIT_MCR_FRZ_MASK; - } - else - { - base->MCR |= PIT_MCR_FRZ_MASK; - } -} - -void PIT_Deinit(PIT_Type *base) -{ -#if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS - /* Disable PIT timers */ - base->MCR |= PIT_MCR_MDIS_MASK; -#endif - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the PIT clock*/ - CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER - -uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base) -{ - uint32_t valueH = 0U; - uint32_t valueL = 0U; - - /* LTMR64H should be read before LTMR64L */ - valueH = base->LTMR64H; - valueL = base->LTMR64L; - - return (((uint64_t)valueH << 32U) + (uint64_t)(valueL)); -} - -#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pit.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_pit.h deleted file mode 100644 index 55abdd5db8..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pit.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_PIT_H_ -#define _FSL_PIT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pit - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! - * @brief List of PIT channels - * @note Actual number of available channels is SoC dependent - */ -typedef enum _pit_chnl -{ - kPIT_Chnl_0 = 0U, /*!< PIT channel number 0*/ - kPIT_Chnl_1, /*!< PIT channel number 1 */ - kPIT_Chnl_2, /*!< PIT channel number 2 */ - kPIT_Chnl_3, /*!< PIT channel number 3 */ -} pit_chnl_t; - -/*! @brief List of PIT interrupts */ -typedef enum _pit_interrupt_enable -{ - kPIT_TimerInterruptEnable = PIT_TCTRL_TIE_MASK, /*!< Timer interrupt enable*/ -} pit_interrupt_enable_t; - -/*! @brief List of PIT status flags */ -typedef enum _pit_status_flags -{ - kPIT_TimerFlag = PIT_TFLG_TIF_MASK, /*!< Timer flag */ -} pit_status_flags_t; - -/*! - * @brief PIT configuration structure - * - * This structure holds the configuration settings for the PIT peripheral. To initialize this - * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The configuration structure can be made constant so it resides in flash. - */ -typedef struct _pit_config -{ - bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */ -} pit_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations. - * - * @note This API should be called at the beginning of the application using the PIT driver. - * - * @param base PIT peripheral base address - * @param config Pointer to the user's PIT config structure - */ -void PIT_Init(PIT_Type *base, const pit_config_t *config); - -/*! - * @brief Gates the PIT clock and disables the PIT module. - * - * @param base PIT peripheral base address - */ -void PIT_Deinit(PIT_Type *base); - -/*! - * @brief Fills in the PIT configuration structure with the default settings. - * - * The default values are as follows. - * @code - * config->enableRunInDebug = false; - * @endcode - * @param config Pointer to the onfiguration structure. - */ -static inline void PIT_GetDefaultConfig(pit_config_t *config) -{ - assert(config); - - /* Timers are stopped in Debug mode */ - config->enableRunInDebug = false; -} - -#if defined(FSL_FEATURE_PIT_HAS_CHAIN_MODE) && FSL_FEATURE_PIT_HAS_CHAIN_MODE - -/*! - * @brief Enables or disables chaining a timer with the previous timer. - * - * When a timer has a chain mode enabled, it only counts after the previous - * timer has expired. If the timer n-1 has counted down to 0, counter n - * decrements the value by one. Each timer is 32-bits, which allows the developers - * to chain timers together and form a longer timer (64-bits and larger). The first timer - * (timer 0) can't be chained to any other timer. - * - * @param base PIT peripheral base address - * @param channel Timer channel number which is chained with the previous timer - * @param enable Enable or disable chain. - * true: Current timer is chained with the previous timer. - * false: Timer doesn't chain with other timers. - */ -static inline void PIT_SetTimerChainMode(PIT_Type *base, pit_chnl_t channel, bool enable) -{ - if (enable) - { - base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; - } - else - { - base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; - } -} - -#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */ - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected PIT interrupts. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::pit_interrupt_enable_t - */ -static inline void PIT_EnableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) -{ - base->CHANNEL[channel].TCTRL |= mask; -} - -/*! - * @brief Disables the selected PIT interrupts. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * @param mask The interrupts to disable. This is a logical OR of members of the - * enumeration ::pit_interrupt_enable_t - */ -static inline void PIT_DisableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) -{ - base->CHANNEL[channel].TCTRL &= ~mask; -} - -/*! - * @brief Gets the enabled PIT interrupts. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::pit_interrupt_enable_t - */ -static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t channel) -{ - return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK); -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the PIT status flags. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::pit_status_flags_t - */ -static inline uint32_t PIT_GetStatusFlags(PIT_Type *base, pit_chnl_t channel) -{ - return (base->CHANNEL[channel].TFLG & PIT_TFLG_TIF_MASK); -} - -/*! - * @brief Clears the PIT status flags. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::pit_status_flags_t - */ -static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint32_t mask) -{ - base->CHANNEL[channel].TFLG = mask; -} - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Sets the timer period in units of count. - * - * Timers begin counting from the value set by this function until it reaches 0, - * then it generates an interrupt and load this register value again. - * Writing a new value to this register does not restart the timer. Instead, the value - * is loaded after the timer expires. - * - * @note Users can call the utility macros provided in fsl_common.h to convert to ticks. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * @param count Timer period in units of ticks - */ -static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count) -{ - base->CHANNEL[channel].LDVAL = count; -} - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec. - * - * @param base PIT peripheral base address - * @param channel Timer channel number - * - * @return Current timer counting value in ticks - */ -static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base, pit_chnl_t channel) -{ - return base->CHANNEL[channel].CVAL; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the timer counting. - * - * After calling this function, timers load period value, count down to 0 and - * then load the respective start value again. Each time a timer reaches 0, - * it generates a trigger pulse and sets the timeout interrupt flag. - * - * @param base PIT peripheral base address - * @param channel Timer channel number. - */ -static inline void PIT_StartTimer(PIT_Type *base, pit_chnl_t channel) -{ - base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; -} - -/*! - * @brief Stops the timer counting. - * - * This function stops every timer counting. Timers reload their periods - * respectively after the next time they call the PIT_DRV_StartTimer. - * - * @param base PIT peripheral base address - * @param channel Timer channel number. - */ -static inline void PIT_StopTimer(PIT_Type *base, pit_chnl_t channel) -{ - base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; -} - -/*! @}*/ - -#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER - -/*! - * @brief Reads the current lifetime counter value. - * - * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. - * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer. - * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1". - * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit - * has the value of timer 0. - * - * @param base PIT peripheral base address - * - * @return Current lifetime timer value - */ -uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base); - -#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PIT_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pmu.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_pmu.c deleted file mode 100644 index 717f5f8a69..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pmu.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_pmu.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.pmu" -#endif - - -uint32_t PMU_GetStatusFlags(PMU_Type *base) -{ - uint32_t ret = 0U; - - /* For 1P1. */ - if (PMU_REG_1P1_OK_VDD1P1_MASK == (PMU_REG_1P1_OK_VDD1P1_MASK & base->REG_1P1)) - { - ret |= kPMU_1P1RegulatorOutputOK; - } - if (PMU_REG_1P1_BO_VDD1P1_MASK == (PMU_REG_1P1_BO_VDD1P1_MASK & base->REG_1P1)) - { - ret |= kPMU_1P1BrownoutOnOutput; - } - - /* For 3P0. */ - if (PMU_REG_3P0_OK_VDD3P0_MASK == (PMU_REG_3P0_OK_VDD3P0_MASK & base->REG_3P0)) - { - ret |= kPMU_3P0RegulatorOutputOK; - } - if (PMU_REG_3P0_BO_VDD3P0_MASK == (PMU_REG_3P0_BO_VDD3P0_MASK & base->REG_3P0)) - { - ret |= kPMU_3P0BrownoutOnOutput; - } - - /* For 2P5. */ - if (PMU_REG_2P5_OK_VDD2P5_MASK == (PMU_REG_2P5_OK_VDD2P5_MASK & base->REG_2P5)) - { - ret |= kPMU_2P5RegulatorOutputOK; - } - if (PMU_REG_2P5_BO_VDD2P5_MASK == (PMU_REG_2P5_BO_VDD2P5_MASK & base->REG_2P5)) - { - ret |= kPMU_2P5BrownoutOnOutput; - } - - return ret; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pmu.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_pmu.h deleted file mode 100644 index b7108941de..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pmu.h +++ /dev/null @@ -1,690 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_PMU_H_ -#define _FSL_PMU_H_ - -#include "fsl_common.h" - -/*! @addtogroup pmu */ -/*! @{ */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief PMU driver version */ -#define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - /*@}*/ - -/*! - * @brief Status flags. - */ -enum _pmu_status_flags -{ - kPMU_1P1RegulatorOutputOK = (1U << 0U), /*!< Status bit that signals when the 1p1 regulator output - is ok. 1 = regulator output > brownout target. */ - kPMU_1P1BrownoutOnOutput = (1U << 1U), /*!< Status bit that signals when a 1p1 brownout is detected - on the regulator output. */ - kPMU_3P0RegulatorOutputOK = (1U << 2U), /*!< Status bit that signals when the 3p0 regulator output - is ok. 1 = regulator output > brownout target. */ - kPMU_3P0BrownoutOnOutput = (1U << 3U), /*!< Status bit that signals when a 3p0 brownout is detected - on the regulator output. */ - kPMU_2P5RegulatorOutputOK = (1U << 4U), /*!< Status bit that signals when the 2p5 regulator output - is ok. 1 = regulator output > brownout target. */ - kPMU_2P5BrownoutOnOutput = (1U << 5U), /*!< Status bit that signals when a 2p5 brownout is detected - on the regulator output. */ -}; - -/*! - * @brief The source for the reference voltage of the weak 1P1 regulator. - */ -typedef enum _pmu_1p1_weak_reference_source -{ - kPMU_1P1WeakReferenceSourceAlt0 = 0U, /*!< Weak-linreg output tracks low-power-bandgap voltage. */ - kPMU_1P1WeakReferenceSourceAlt1 = 1U, /*!< Weak-linreg output tracks VDD_SOC_CAP voltage. */ -} pmu_1p1_weak_reference_source_t; - -/*! - * @brief Input voltage source for LDO_3P0 from USB VBus. - */ -typedef enum _pmu_3p0_vbus_voltage_source -{ - kPMU_3P0VBusVoltageSourceAlt0 = 0U, /*!< USB_OTG1_VBUS - Utilize VBUS OTG1 for power. */ - kPMU_3P0VBusVoltageSourceAlt1 = 1U, /*!< USB_OTG2_VBUS - Utilize VBUS OTG2 for power. */ -} pmu_3p0_vbus_voltage_source_t; - -/*! - * @brief Regulator voltage ramp rate. - */ -typedef enum _pmu_core_reg_voltage_ramp_rate -{ - kPMU_CoreRegVoltageRampRateFast = 0U, /*!< Fast. */ - kPMU_CoreRegVoltageRampRateMediumFast = 1U, /*!< Medium Fast. */ - kPMU_CoreRegVoltageRampRateMediumSlow = 2U, /*!< Medium Slow. */ - kPMU_CoreRegVoltageRampRateSlow = 0U, /*!< Slow. */ -} pmu_core_reg_voltage_ramp_rate_t; - -#if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL -/*! - * @brief Mask values of power gate. - */ -enum _pmu_power_gate -{ - kPMU_PowerGateDisplay = PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK, /*!< Display power gate control. */ - kPMU_PowerGateDisplayLogic = PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK, /*!< Display logic power gate control. */ - kPMU_PowerGateL2 = PMU_LOWPWR_CTRL_L2_PWRGATE_MASK, /*!< L2 power gate control. */ - kPMU_PowerGateL1 = PMU_LOWPWR_CTRL_L1_PWRGATE_MASK, /*!< L1 power gate control. */ - kPMU_PowerGateRefTopIBias = PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK, /*!< Low power reftop ibias disable. */ -}; -#endif /* FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */ - -/*! - * @brief Bandgap select. - */ -typedef enum _pmu_power_bandgap -{ - kPMU_NormalPowerBandgap = 0U, /*!< Normal power bandgap. */ - kPMU_LowPowerBandgap = 1U, /*!< Low power bandgap. */ -} pmu_power_bandgap_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @name Status. - * @{ - */ - -uint32_t PMU_GetStatusFlags(PMU_Type *base); - -/*@}*/ - -/*! - * @name 1P1 Regular - * @{ - */ - -/*! - * @brief Selects the source for the reference voltage of the weak 1P1 regulator. - * - * @param base PMU peripheral base address. - * @param option The option for reference voltage source, see to #pmu_1p1_weak_reference_source_t. - */ -static inline void PMU_1P1SetWeakReferenceSource(PMU_Type *base, pmu_1p1_weak_reference_source_t option) -{ - base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) | PMU_REG_1P1_SELREF_WEAK_LINREG(option); -} - -/*! - * @brief Enables the weak 1P1 regulator. - * - * This regulator can be used when the main 1P1 regulator is disabled, under low-power conditions. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_1P1EnableWeakRegulator(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_1P1 |= PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK; - } - else - { - base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK; - } -} - -/*! - * @brief Adjust the 1P1 regulator output voltage. - * - * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages - * may be interpolated from these examples. Choices must be in this range: - * - 0x1b(1.375V) >= output_trg >= 0x04(0.8V) - * - 0x04 : 0.8V - * - 0x10 : 1.1V (typical) - * - 0x1b : 1.375V - * NOTE: There may be reduced chip functionality or reliability at the extremes of the programming range. - * - * @param base PMU peripheral base address. - * @param value Setting value for the output. - */ -static inline void PMU_1P1SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value) -{ - base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_OUTPUT_TRG_MASK) | PMU_REG_1P1_OUTPUT_TRG(value); -} - -/*! - * @brief Adjust the 1P1 regulator brownout offset voltage. - * - * Control bits to adjust the regulator brownout offset voltage in 25mV steps. The reset - * brown-offset is 175mV below the programmed target code. - * Brownout target = OUTPUT_TRG - BO_OFFSET. - * Some steps may be irrelevant because of input supply limitations or load operation. - * - * @param base PMU peripheral base address. - * @param value Setting value for the brownout offset. The available range is in 3-bit. - */ -static inline void PMU_1P1SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value) -{ - base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_BO_OFFSET_MASK) | PMU_REG_1P1_BO_OFFSET(value); -} - -/*! - * @brief Enable the pull-down circuitry in the regulator. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_1P1EnablePullDown(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_1P1 |= PMU_REG_1P1_ENABLE_PULLDOWN_MASK; - } - else - { - base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_PULLDOWN_MASK; - } -} - -/*! - * @brief Enable the current-limit circuitry in the regulator. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_1P1EnableCurrentLimit(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_1P1 |= PMU_REG_1P1_ENABLE_ILIMIT_MASK; - } - else - { - base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_ILIMIT_MASK; - } -} - -/*! - * @brief Enable the brownout circuitry in the regulator. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_1P1EnableBrownout(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_1P1 |= PMU_REG_1P1_ENABLE_BO_MASK; - } - else - { - base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_BO_MASK; - } -} - -/*! - * @brief Enable the regulator output. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_1P1EnableOutput(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_1P1 |= PMU_REG_1P1_ENABLE_LINREG_MASK; - } - else - { - base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_LINREG_MASK; - } -} - -/*@}*/ - -/*! - * @name 3P0 Regular - * @{ - */ - -/*! - * @brief Adjust the 3P0 regulator output voltage. - * - * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages - * may be interpolated from these examples. Choices must be in this range: - * - 0x00(2.625V) >= output_trg >= 0x1f(3.4V) - * - 0x00 : 2.625V - * - 0x0f : 3.0V (typical) - * - 0x1f : 3.4V - * - * @param base PMU peripheral base address. - * @param value Setting value for the output. - */ -static inline void PMU_3P0SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value) -{ - base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_OUTPUT_TRG_MASK) | PMU_REG_3P0_OUTPUT_TRG(value); -} - -/*! - * @brief Select input voltage source for LDO_3P0. - * - * Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS. If only - * one of the two VBUS voltages is present, it is automatically selected. - * - * @param base PMU peripheral base address. - * @param option User-defined input voltage source for LDO_3P0. - */ -static inline void PMU_3P0SetVBusVoltageSource(PMU_Type *base, pmu_3p0_vbus_voltage_source_t option) -{ - base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_VBUS_SEL_MASK) | PMU_REG_3P0_VBUS_SEL(option); -} - -/*! - * @brief Adjust the 3P0 regulator brownout offset voltage. - * - * Control bits to adjust the 3P0 regulator brownout offset voltage in 25mV steps. The reset - * brown-offset is 175mV below the programmed target code. - * Brownout target = OUTPUT_TRG - BO_OFFSET. - * Some steps may be irrelevant because of input supply limitations or load operation. - * - * @param base PMU peripheral base address. - * @param value Setting value for the brownout offset. The available range is in 3-bit. - */ -static inline void PMU_3P0SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value) -{ - base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_BO_OFFSET_MASK) | PMU_REG_3P0_BO_OFFSET(value); -} - -/*! - * @brief Enable the current-limit circuitry in the 3P0 regulator. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_3P0EnableCurrentLimit(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_3P0 |= PMU_REG_3P0_ENABLE_ILIMIT_MASK; - } - else - { - base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_ILIMIT_MASK; - } -} - -/*! - * @brief Enable the brownout circuitry in the 3P0 regulator. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_3P0EnableBrownout(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_3P0 |= PMU_REG_3P0_ENABLE_BO_MASK; - } - else - { - base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_BO_MASK; - } -} - -/*! - * @brief Enable the 3P0 regulator output. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_3P0EnableOutput(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_3P0 |= PMU_REG_3P0_ENABLE_LINREG_MASK; - } - else - { - base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_LINREG_MASK; - } -} - -/* @} */ - -/*! - * @name 2P5 Regulator - * @{ - */ - -/*! - * @brief Enables the weak 2P5 regulator. - * - * This low power regulator is used when the main 2P5 regulator is disabled - * to keep the 2.5V output roughly at 2.5V. Scales directly with the value of VDDHIGH_IN. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_2P5EnableWeakRegulator(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_2P5 |= PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; - } - else - { - base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; - } -} - -/*! - * @brief Adjust the 1P1 regulator output voltage. - * - * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages - * may be interpolated from these examples. Choices must be in this range: - * - 0x00(2.1V) >= output_trg >= 0x1f(2.875V) - * - 0x00 : 2.1V - * - 0x10 : 2.5V (typical) - * - 0x1f : 2.875V - * NOTE: There may be reduced chip functionality or reliability at the extremes of the programming range. - * - * @param base PMU peripheral base address. - * @param value Setting value for the output. - */ -static inline void PMU_2P5SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value) -{ - base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_OUTPUT_TRG_MASK) | PMU_REG_2P5_OUTPUT_TRG(value); -} - -/*! - * @brief Adjust the 2P5 regulator brownout offset voltage. - * - * Adjust the regulator brownout offset voltage in 25mV steps. The reset - * brown-offset is 175mV below the programmed target code. - * Brownout target = OUTPUT_TRG - BO_OFFSET. - * Some steps may be irrelevant because of input supply limitations or load operation. - * - * @param base PMU peripheral base address. - * @param value Setting value for the brownout offset. The available range is in 3-bit. - */ -static inline void PMU_2P5SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value) -{ - base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_BO_OFFSET_MASK) | PMU_REG_2P5_BO_OFFSET(value); -} - -/*! - * @brief Enable the pull-down circuitry in the 2P5 regulator. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_2P5EnablePullDown(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK; - } - else - { - base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK; - } -} - -/*! - * @brief Enable the pull-down circuitry in the 2P5 regulator. - * @deprecated Do not use this function. It has been superceded by @ref PMU_2P5EnablePullDown. - */ -static inline void PMU_2P1EnablePullDown(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK; - } - else - { - base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK; - } -} - -/*! - * @brief Enable the current-limit circuitry in the 2P5 regulator. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_2P5EnableCurrentLimit(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_2P5 |= PMU_REG_2P5_ENABLE_ILIMIT_MASK; - } - else - { - base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_ILIMIT_MASK; - } -} - -/*! - * @brief Enable the brownout circuitry in the 2P5 regulator. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_2P5nableBrownout(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_2P5 |= PMU_REG_2P5_ENABLE_BO_MASK; - } - else - { - base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_BO_MASK; - } -} - -/*! - * @brief Enable the 2P5 regulator output. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_2P5EnableOutput(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_2P5 |= PMU_REG_2P5_ENABLE_LINREG_MASK; - } - else - { - base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_LINREG_MASK; - } -} - -/* @} */ - -/*! - * @name Core Regulator - * @{ - */ - -/*! - * @brief Increase the gate drive on power gating FETs. - * - * If set, increases the gate drive on power gating FETs to reduce leakage in the off state. - * Care must be taken to apply this bit only when the input supply voltage to the power FET - * is less than 1.1V. - * NOTE: This bit should only be used in low-power modes where the external input supply voltage - * is nominally 0.9V. - * - * @param base PMU peripheral base address. - * @param enable Enable the feature or not. - */ -static inline void PMU_CoreEnableIncreaseGateDrive(PMU_Type *base, bool enable) -{ - if (enable) - { - base->REG_CORE |= PMU_REG_CORE_FET_ODRIVE_MASK; - } - else - { - base->REG_CORE &= ~PMU_REG_CORE_FET_ODRIVE_MASK; - } -} - -/*! - * @brief Set the CORE regulator voltage ramp rate. - * - * @param base PMU peripheral base address. - * @param option User-defined option for voltage ramp rate, see to #pmu_core_reg_voltage_ramp_rate_t. - */ -static inline void PMU_CoreSetRegulatorVoltageRampRate(PMU_Type *base, pmu_core_reg_voltage_ramp_rate_t option) -{ - base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_RAMP_RATE_MASK) | PMU_REG_CORE_RAMP_RATE(option); -} - -/*! - * @brief Define the target voltage for the SOC power domain. - * - * Define the target voltage for the SOC power domain. Single-bit increments reflect 25mV core - * voltage steps. Some steps may not be relevant because of input supply limitations or load operation. - * - 0x00 : Power gated off. - * - 0x01 : Target core voltage = 0.725V - * - 0x02 : Target core voltage = 0.750V - * - ... - * - 0x10 : Target core voltage = 1.100V - * - ... - * - 0x1e : Target core voltage = 1.450V - * - 0x1F : Power FET switched full on. No regulation. - * NOTE: This register is capable of programming an over-voltage condition on the device. Consult the - * datasheet Operating Ranges table for the allowed voltages. - * - * @param base PMU peripheral base address. - * @param value Setting value for target voltage. 5-bit available - */ -static inline void PMU_CoreSetSOCDomainVoltage(PMU_Type *base, uint32_t value) -{ - base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_REG2_TARG_MASK) | PMU_REG_CORE_REG2_TARG(value); -} - -/*! - * @brief Define the target voltage for the ARM Core power domain. - * - * Define the target voltage for the ARM Core power domain. Single-bit increments reflect 25mV core - * voltage steps. Some steps may not be relevant because of input supply limitations or load operation. - * - 0x00 : Power gated off. - * - 0x01 : Target core voltage = 0.725V - * - 0x02 : Target core voltage = 0.750V - * - ... - * - 0x10 : Target core voltage = 1.100V - * - ... - * - 0x1e : Target core voltage = 1.450V - * - 0x1F : Power FET switched full on. No regulation. - * NOTE: This register is capable of programming an over-voltage condition on the device. Consult the - * datasheet Operating Ranges table for the allowed voltages. - * - * @param base PMU peripheral base address. - * @param value Setting value for target voltage. 5-bit available - */ -static inline void PMU_CoreSetARMCoreDomainVoltage(PMU_Type *base, uint32_t value) -{ - base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_REG0_TARG_MASK) | PMU_REG_CORE_REG0_TARG(value); -} - -/* @} */ - -#if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL -/*! - * @name Power Gate Controller & other - * @{ - */ - -/*! - * @brief Gate the power to modules. - * - * @param base PMU peripheral base address. - * @param gates Mask value for the module to be gated. See to #_pmu_power_gate. - */ -static inline void PMU_GatePower(PMU_Type *base, uint32_t gates) -{ - base->LOWPWR_CTRL_SET = gates; -} - -/*! - * @brief Ungate the power to modules. - * - * @param base PMU peripheral base address. - * @param gates Mask value for the module to be gated. See to #_pmu_power_gate. - */ -static inline void PMU_UngatePower(PMU_Type *base, uint32_t gates) -{ - base->LOWPWR_CTRL_CLR = gates; -} - -/*! - * @brief Enable the low power bandgap. - * - * @param base PMU peripheral base address. - * @param enable Enable the low power bandgap or use the normal power bandgap. - * @ - */ -static inline void PMU_EnableLowPowerBandgap(PMU_Type *base, bool enable) -{ - if (enable) - { - base->LOWPWR_CTRL_SET = PMU_LOWPWR_CTRL_LPBG_SEL_MASK; /* Use the low power bandgap. */ - } - else - { - base->LOWPWR_CTRL_CLR = PMU_LOWPWR_CTRL_LPBG_SEL_MASK; /* Use the normal power bandgap. */ - } -} -#endif /* FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */ -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* _FSL_PMU_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pwm.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_pwm.c deleted file mode 100644 index a244750f80..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pwm.c +++ /dev/null @@ -1,693 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_pwm.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.pwm" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance from the base address - * - * @param base PWM peripheral base address - * - * @return The PWM module instance - */ -static uint32_t PWM_GetInstance(PWM_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to PWM bases for each instance. */ -static PWM_Type *const s_pwmBases[] = PWM_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to PWM clocks for each PWM submodule. */ -static const clock_ip_name_t s_pwmClocks[][FSL_FEATURE_PWM_SUBMODULE_COUNT] = PWM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t PWM_GetInstance(PWM_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_pwmBases); instance++) - { - if (s_pwmBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_pwmBases)); - - return instance; -} - -status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config) -{ - assert(config); - - uint16_t reg; - - /* Source clock for submodule 0 cannot be itself */ - if ((config->clockSource == kPWM_Submodule0Clock) && (subModule == kPWM_Module_0)) - { - return kStatus_Fail; - } - - /* Reload source select clock for submodule 0 cannot be master reload */ - if ((config->reloadSelect == kPWM_MasterReload) && (subModule == kPWM_Module_0)) - { - return kStatus_Fail; - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Ungate the PWM submodule clock*/ - CLOCK_EnableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Clear the fault status flags */ - base->FSTS |= PWM_FSTS_FFLAG_MASK; - - reg = base->SM[subModule].CTRL2; - - /* Setup the submodule clock-source, control source of the INIT signal, - * source of the force output signal, operation in debug & wait modes and reload source select - */ - reg &= ~(PWM_CTRL2_CLK_SEL_MASK | PWM_CTRL2_FORCE_SEL_MASK | PWM_CTRL2_INIT_SEL_MASK | PWM_CTRL2_INDEP_MASK | - PWM_CTRL2_WAITEN_MASK | PWM_CTRL2_DBGEN_MASK | PWM_CTRL2_RELOAD_SEL_MASK); - reg |= (PWM_CTRL2_CLK_SEL(config->clockSource) | PWM_CTRL2_FORCE_SEL(config->forceTrigger) | - PWM_CTRL2_INIT_SEL(config->initializationControl) | PWM_CTRL2_DBGEN(config->enableDebugMode) | - PWM_CTRL2_WAITEN(config->enableWait) | PWM_CTRL2_RELOAD_SEL(config->reloadSelect)); - - /* Setup PWM A & B to be independent or a complementary-pair */ - switch (config->pairOperation) - { - case kPWM_Independent: - reg |= PWM_CTRL2_INDEP_MASK; - break; - case kPWM_ComplementaryPwmA: - base->MCTRL &= ~(1U << (PWM_MCTRL_IPOL_SHIFT + subModule)); - break; - case kPWM_ComplementaryPwmB: - base->MCTRL |= (1U << (PWM_MCTRL_IPOL_SHIFT + subModule)); - break; - default: - break; - } - base->SM[subModule].CTRL2 = reg; - - reg = base->SM[subModule].CTRL; - - /* Setup the clock prescale, load mode and frequency */ - reg &= ~(PWM_CTRL_PRSC_MASK | PWM_CTRL_LDFQ_MASK | PWM_CTRL_LDMOD_MASK); - reg |= (PWM_CTRL_PRSC(config->prescale) | PWM_CTRL_LDFQ(config->reloadFrequency)); - - /* Setup register reload logic */ - switch (config->reloadLogic) - { - case kPWM_ReloadImmediate: - reg |= PWM_CTRL_LDMOD_MASK; - break; - case kPWM_ReloadPwmHalfCycle: - reg |= PWM_CTRL_HALF_MASK; - reg &= ~PWM_CTRL_FULL_MASK; - break; - case kPWM_ReloadPwmFullCycle: - reg &= ~PWM_CTRL_HALF_MASK; - reg |= PWM_CTRL_FULL_MASK; - break; - case kPWM_ReloadPwmHalfAndFullCycle: - reg |= PWM_CTRL_HALF_MASK; - reg |= PWM_CTRL_FULL_MASK; - break; - default: - break; - } - base->SM[subModule].CTRL = reg; - - /* Setup the fault filter */ - if (base->FFILT & PWM_FFILT_FILT_PER_MASK) - { - /* When changing values for fault period from a non-zero value, first write a value of 0 - * to clear the filter - */ - base->FFILT &= ~(PWM_FFILT_FILT_PER_MASK); - } - - base->FFILT = (PWM_FFILT_FILT_CNT(config->faultFilterCount) | PWM_FFILT_FILT_PER(config->faultFilterPeriod)); - - /* Issue a Force trigger event when configured to trigger locally */ - if (config->forceTrigger == kPWM_Force_Local) - { - base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE(1U); - } - - return kStatus_Success; -} - -void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule) -{ - /* Stop the submodule */ - base->MCTRL &= ~(1U << (PWM_MCTRL_RUN_SHIFT + subModule)); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Gate the PWM submodule clock*/ - CLOCK_DisableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void PWM_GetDefaultConfig(pwm_config_t *config) -{ - assert(config); - - /* PWM is paused in debug mode */ - config->enableDebugMode = false; - /* PWM is paused in wait mode */ - config->enableWait = false; - /* PWM module uses the local reload signal to reload registers */ - config->reloadSelect = kPWM_LocalReload; - /* Fault filter count is set to 0 */ - config->faultFilterCount = 0; - /* Fault filter period is set to 0 which disables the fault filter */ - config->faultFilterPeriod = 0; - /* Use the IP Bus clock as source clock for the PWM submodule */ - config->clockSource = kPWM_BusClock; - /* Clock source prescale is set to divide by 1*/ - config->prescale = kPWM_Prescale_Divide_1; - /* Local sync causes initialization */ - config->initializationControl = kPWM_Initialize_LocalSync; - /* The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ - config->forceTrigger = kPWM_Force_Local; - /* PWM reload frequency, reload opportunity is PWM half cycle or full cycle. - * This field is not used in Immediate reload mode - */ - config->reloadFrequency = kPWM_LoadEveryOportunity; - /* Buffered-registers get loaded with new values as soon as LDOK bit is set */ - config->reloadLogic = kPWM_ReloadImmediate; - /* PWM A & PWM B operate as 2 independent channels */ - config->pairOperation = kPWM_Independent; -} - -status_t PWM_SetupPwm(PWM_Type *base, - pwm_submodule_t subModule, - const pwm_signal_param_t *chnlParams, - uint8_t numOfChnls, - pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz) -{ - assert(chnlParams); - assert(pwmFreq_Hz); - assert(numOfChnls); - assert(srcClock_Hz); - - uint32_t pwmClock; - uint16_t pulseCnt = 0, pwmHighPulse = 0; - int16_t modulo = 0; - uint8_t i, polarityShift = 0, outputEnableShift = 0; - - if (numOfChnls > 2) - { - /* Each submodule has 2 signals; PWM A & PWM B */ - return kStatus_Fail; - } - - /* Divide the clock by the prescale value */ - pwmClock = (srcClock_Hz / (1U << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT))); - pulseCnt = (pwmClock / pwmFreq_Hz); - - /* Setup each PWM channel */ - for (i = 0; i < numOfChnls; i++) - { - /* Calculate pulse width */ - pwmHighPulse = (pulseCnt * chnlParams->dutyCyclePercent) / 100; - - /* Setup the different match registers to generate the PWM signal */ - switch (mode) - { - case kPWM_SignedCenterAligned: - /* Setup the PWM period for a signed center aligned signal */ - modulo = pulseCnt >> 1; - /* Indicates the start of the PWM period */ - base->SM[subModule].INIT = (-modulo); - /* Indicates the center value */ - base->SM[subModule].VAL0 = 0; - /* Indicates the end of the PWM period */ - base->SM[subModule].VAL1 = modulo; - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = (-(pwmHighPulse / 2)); - base->SM[subModule].VAL3 = (pwmHighPulse / 2); - } - else - { - base->SM[subModule].VAL4 = (-(pwmHighPulse / 2)); - base->SM[subModule].VAL5 = (pwmHighPulse / 2); - } - break; - case kPWM_CenterAligned: - /* Setup the PWM period for an unsigned center aligned signal */ - /* Indicates the start of the PWM period */ - base->SM[subModule].INIT = 0; - /* Indicates the center value */ - base->SM[subModule].VAL0 = (pulseCnt / 2); - /* Indicates the end of the PWM period */ - base->SM[subModule].VAL1 = pulseCnt; - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2); - base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2); - } - else - { - base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2); - base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2); - } - break; - case kPWM_SignedEdgeAligned: - /* Setup the PWM period for a signed edge aligned signal */ - modulo = pulseCnt >> 1; - /* Indicates the start of the PWM period */ - base->SM[subModule].INIT = (-modulo); - /* Indicates the center value */ - base->SM[subModule].VAL0 = 0; - /* Indicates the end of the PWM period */ - base->SM[subModule].VAL1 = modulo; - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = (-modulo); - base->SM[subModule].VAL3 = (-modulo + pwmHighPulse); - } - else - { - base->SM[subModule].VAL4 = (-modulo); - base->SM[subModule].VAL5 = (-modulo + pwmHighPulse); - } - break; - case kPWM_EdgeAligned: - /* Setup the PWM period for a unsigned edge aligned signal */ - /* Indicates the start of the PWM period */ - base->SM[subModule].INIT = 0; - /* Indicates the center value */ - base->SM[subModule].VAL0 = (pulseCnt / 2); - /* Indicates the end of the PWM period */ - base->SM[subModule].VAL1 = pulseCnt; - - /* Setup the PWM dutycycle */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - base->SM[subModule].VAL2 = 0; - base->SM[subModule].VAL3 = pwmHighPulse; - } - else - { - base->SM[subModule].VAL4 = 0; - base->SM[subModule].VAL5 = pwmHighPulse; - } - break; - default: - break; - } - /* Setup register shift values based on the channel being configured. - * Also setup the deadtime value - */ - if (chnlParams->pwmChannel == kPWM_PwmA) - { - polarityShift = PWM_OCTRL_POLA_SHIFT; - outputEnableShift = PWM_OUTEN_PWMA_EN_SHIFT; - base->SM[subModule].DTCNT0 = PWM_DTCNT0_DTCNT0(chnlParams->deadtimeValue); - } - else - { - polarityShift = PWM_OCTRL_POLB_SHIFT; - outputEnableShift = PWM_OUTEN_PWMB_EN_SHIFT; - base->SM[subModule].DTCNT1 = PWM_DTCNT1_DTCNT1(chnlParams->deadtimeValue); - } - - /* Setup signal active level */ - if (chnlParams->level == kPWM_HighTrue) - { - base->SM[subModule].OCTRL &= ~(1U << polarityShift); - } - else - { - base->SM[subModule].OCTRL |= (1U << polarityShift); - } - /* Enable PWM output */ - base->OUTEN |= (1U << (outputEnableShift + subModule)); - - /* Get the next channel parameters */ - chnlParams++; - } - - return kStatus_Success; -} - -void PWM_UpdatePwmDutycycle(PWM_Type *base, - pwm_submodule_t subModule, - pwm_channels_t pwmSignal, - pwm_mode_t currPwmMode, - uint8_t dutyCyclePercent) -{ - assert(dutyCyclePercent <= 100); - assert(pwmSignal < 2); - uint16_t pulseCnt = 0, pwmHighPulse = 0; - int16_t modulo = 0; - - switch (currPwmMode) - { - case kPWM_SignedCenterAligned: - modulo = base->SM[subModule].VAL1; - pulseCnt = modulo * 2; - /* Calculate pulse width */ - pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = (-(pwmHighPulse / 2)); - base->SM[subModule].VAL3 = (pwmHighPulse / 2); - } - else - { - base->SM[subModule].VAL4 = (-(pwmHighPulse / 2)); - base->SM[subModule].VAL5 = (pwmHighPulse / 2); - } - break; - case kPWM_CenterAligned: - pulseCnt = base->SM[subModule].VAL1; - /* Calculate pulse width */ - pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2); - base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2); - } - else - { - base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2); - base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2); - } - break; - case kPWM_SignedEdgeAligned: - modulo = base->SM[subModule].VAL1; - pulseCnt = modulo * 2; - /* Calculate pulse width */ - pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = (-modulo); - base->SM[subModule].VAL3 = (-modulo + pwmHighPulse); - } - else - { - base->SM[subModule].VAL4 = (-modulo); - base->SM[subModule].VAL5 = (-modulo + pwmHighPulse); - } - break; - case kPWM_EdgeAligned: - pulseCnt = base->SM[subModule].VAL1; - /* Calculate pulse width */ - pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; - - /* Setup the PWM dutycycle */ - if (pwmSignal == kPWM_PwmA) - { - base->SM[subModule].VAL2 = 0; - base->SM[subModule].VAL3 = pwmHighPulse; - } - else - { - base->SM[subModule].VAL4 = 0; - base->SM[subModule].VAL5 = pwmHighPulse; - } - break; - default: - break; - } -} - -void PWM_SetupInputCapture(PWM_Type *base, - pwm_submodule_t subModule, - pwm_channels_t pwmChannel, - const pwm_input_capture_param_t *inputCaptureParams) -{ - uint32_t reg = 0; - switch (pwmChannel) - { - case kPWM_PwmA: - /* Setup the capture paramters for PWM A pin */ - reg = (PWM_CAPTCTRLA_INP_SELA(inputCaptureParams->captureInputSel) | - PWM_CAPTCTRLA_EDGA0(inputCaptureParams->edge0) | PWM_CAPTCTRLA_EDGA1(inputCaptureParams->edge1) | - PWM_CAPTCTRLA_ONESHOTA(inputCaptureParams->enableOneShotCapture) | - PWM_CAPTCTRLA_CFAWM(inputCaptureParams->fifoWatermark)); - /* Enable the edge counter if using the output edge counter */ - if (inputCaptureParams->captureInputSel) - { - reg |= PWM_CAPTCTRLA_EDGCNTA_EN_MASK; - } - /* Enable input capture operation */ - reg |= PWM_CAPTCTRLA_ARMA_MASK; - - base->SM[subModule].CAPTCTRLA = reg; - - /* Setup the compare value when using the edge counter as source */ - base->SM[subModule].CAPTCOMPA = PWM_CAPTCOMPA_EDGCMPA(inputCaptureParams->edgeCompareValue); - /* Setup PWM A pin for input capture */ - base->OUTEN &= ~(1U << (PWM_OUTEN_PWMA_EN_SHIFT + subModule)); - - break; - case kPWM_PwmB: - /* Setup the capture paramters for PWM B pin */ - reg = (PWM_CAPTCTRLB_INP_SELB(inputCaptureParams->captureInputSel) | - PWM_CAPTCTRLB_EDGB0(inputCaptureParams->edge0) | PWM_CAPTCTRLB_EDGB1(inputCaptureParams->edge1) | - PWM_CAPTCTRLB_ONESHOTB(inputCaptureParams->enableOneShotCapture) | - PWM_CAPTCTRLB_CFBWM(inputCaptureParams->fifoWatermark)); - /* Enable the edge counter if using the output edge counter */ - if (inputCaptureParams->captureInputSel) - { - reg |= PWM_CAPTCTRLB_EDGCNTB_EN_MASK; - } - /* Enable input capture operation */ - reg |= PWM_CAPTCTRLB_ARMB_MASK; - - base->SM[subModule].CAPTCTRLB = reg; - - /* Setup the compare value when using the edge counter as source */ - base->SM[subModule].CAPTCOMPB = PWM_CAPTCOMPB_EDGCMPB(inputCaptureParams->edgeCompareValue); - /* Setup PWM B pin for input capture */ - base->OUTEN &= ~(1U << (PWM_OUTEN_PWMB_EN_SHIFT + subModule)); - break; - case kPWM_PwmX: - reg = (PWM_CAPTCTRLX_INP_SELX(inputCaptureParams->captureInputSel) | - PWM_CAPTCTRLX_EDGX0(inputCaptureParams->edge0) | PWM_CAPTCTRLX_EDGX1(inputCaptureParams->edge1) | - PWM_CAPTCTRLX_ONESHOTX(inputCaptureParams->enableOneShotCapture) | - PWM_CAPTCTRLX_CFXWM(inputCaptureParams->fifoWatermark)); - /* Enable the edge counter if using the output edge counter */ - if (inputCaptureParams->captureInputSel) - { - reg |= PWM_CAPTCTRLX_EDGCNTX_EN_MASK; - } - /* Enable input capture operation */ - reg |= PWM_CAPTCTRLX_ARMX_MASK; - - base->SM[subModule].CAPTCTRLX = reg; - - /* Setup the compare value when using the edge counter as source */ - base->SM[subModule].CAPTCOMPX = PWM_CAPTCOMPX_EDGCMPX(inputCaptureParams->edgeCompareValue); - /* Setup PWM X pin for input capture */ - base->OUTEN &= ~(1U << (PWM_OUTEN_PWMX_EN_SHIFT + subModule)); - break; - default: - break; - } -} - -void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams) -{ - assert(faultParams); - uint16_t reg; - - reg = base->FCTRL; - /* Set the faults level-settting */ - if (faultParams->faultLevel) - { - reg |= (1U << (PWM_FCTRL_FLVL_SHIFT + faultNum)); - } - else - { - reg &= ~(1U << (PWM_FCTRL_FLVL_SHIFT + faultNum)); - } - /* Set the fault clearing mode */ - if (faultParams->faultClearingMode) - { - /* Use manual fault clearing */ - reg &= ~(1U << (PWM_FCTRL_FAUTO_SHIFT + faultNum)); - if (faultParams->faultClearingMode == kPWM_ManualSafety) - { - /* Use manual fault clearing with safety mode enabled */ - reg |= (1U << (PWM_FCTRL_FSAFE_SHIFT + faultNum)); - } - else - { - /* Use manual fault clearing with safety mode disabled */ - reg &= ~(1U << (PWM_FCTRL_FSAFE_SHIFT + faultNum)); - } - } - else - { - /* Use automatic fault clearing */ - reg |= (1U << (PWM_FCTRL_FAUTO_SHIFT + faultNum)); - } - base->FCTRL = reg; - - /* Set the combinational path option */ - if (faultParams->enableCombinationalPath) - { - /* Combinational path from the fault input to the PWM output is available */ - base->FCTRL2 &= ~(1U << faultNum); - } - else - { - /* No combinational path available, only fault filter & latch signal can disable PWM output */ - base->FCTRL2 |= (1U << faultNum); - } - - /* Initially clear both recovery modes */ - reg = base->FSTS; - reg &= ~((1U << (PWM_FSTS_FFULL_SHIFT + faultNum)) | (1U << (PWM_FSTS_FHALF_SHIFT + faultNum))); - /* Setup fault recovery */ - switch (faultParams->recoverMode) - { - case kPWM_NoRecovery: - break; - case kPWM_RecoverHalfCycle: - reg |= (1U << (PWM_FSTS_FHALF_SHIFT + faultNum)); - break; - case kPWM_RecoverFullCycle: - reg |= (1U << (PWM_FSTS_FFULL_SHIFT + faultNum)); - break; - case kPWM_RecoverHalfAndFullCycle: - reg |= (1U << (PWM_FSTS_FHALF_SHIFT + faultNum)); - reg |= (1U << (PWM_FSTS_FFULL_SHIFT + faultNum)); - break; - default: - break; - } - base->FSTS = reg; -} - -void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode) - -{ - uint16_t shift; - uint16_t reg; - - /* DTSRCSEL register has 4 bits per submodule; 2 bits for PWM A and 2 bits for PWM B */ - shift = subModule * 4 + pwmChannel * 2; - - /* Setup the signal to be passed upon occurrence of a FORCE_OUT signal */ - reg = base->DTSRCSEL; - reg &= ~(0x3U << shift); - reg |= (uint16_t)((uint16_t)mode << shift); - base->DTSRCSEL = reg; -} - -void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) -{ - /* Upper 16 bits are for related to the submodule */ - base->SM[subModule].INTEN |= (mask & 0xFFFFU); - /* Fault related interrupts */ - base->FCTRL |= ((mask >> 16U) & PWM_FCTRL_FIE_MASK); -} - -void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) -{ - base->SM[subModule].INTEN &= ~(mask & 0xFFFF); - base->FCTRL &= ~((mask >> 16U) & PWM_FCTRL_FIE_MASK); -} - -uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule) -{ - uint32_t enabledInterrupts; - - enabledInterrupts = base->SM[subModule].INTEN; - enabledInterrupts |= ((uint32_t)(base->FCTRL & PWM_FCTRL_FIE_MASK) << 16U); - return enabledInterrupts; -} - -uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule) -{ - uint32_t statusFlags; - - statusFlags = base->SM[subModule].STS; - statusFlags |= ((uint32_t)(base->FSTS & PWM_FSTS_FFLAG_MASK) << 16U); - - return statusFlags; -} - -void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) -{ - uint16_t reg; - - base->SM[subModule].STS = (mask & 0xFFFFU); - reg = base->FSTS; - /* Clear the fault flags and set only the ones we wish to clear as the fault flags are cleared - * by writing a login one - */ - reg &= ~(PWM_FSTS_FFLAG_MASK); - reg |= ((mask >> 16U) & PWM_FSTS_FFLAG_MASK); - base->FSTS = reg; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pwm.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_pwm.h deleted file mode 100644 index 26619202d9..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pwm.h +++ /dev/null @@ -1,696 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_PWM_H_ -#define _FSL_PWM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pwm_driver - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! Number of bits per submodule for software output control */ -#define PWM_SUBMODULE_SWCONTROL_WIDTH 2 - -/*! @brief List of PWM submodules */ -typedef enum _pwm_submodule -{ - kPWM_Module_0 = 0U, /*!< Submodule 0 */ - kPWM_Module_1, /*!< Submodule 1 */ - kPWM_Module_2, /*!< Submodule 2 */ - kPWM_Module_3 /*!< Submodule 3 */ -} pwm_submodule_t; - -/*! @brief List of PWM channels in each module */ -typedef enum _pwm_channels -{ - kPWM_PwmB = 0U, - kPWM_PwmA, - kPWM_PwmX -} pwm_channels_t; - -/*! @brief List of PWM value registers */ -typedef enum _pwm_value_register -{ - kPWM_ValueRegister_0 = 0U, /*!< PWM Value0 register */ - kPWM_ValueRegister_1, /*!< PWM Value1 register */ - kPWM_ValueRegister_2, /*!< PWM Value2 register */ - kPWM_ValueRegister_3, /*!< PWM Value3 register */ - kPWM_ValueRegister_4, /*!< PWM Value4 register */ - kPWM_ValueRegister_5 /*!< PWM Value5 register */ -} pwm_value_register_t; - -/*! @brief PWM clock source selection.*/ -typedef enum _pwm_clock_source -{ - kPWM_BusClock = 0U, /*!< The IPBus clock is used as the clock */ - kPWM_ExternalClock, /*!< EXT_CLK is used as the clock */ - kPWM_Submodule0Clock /*!< Clock of the submodule 0 (AUX_CLK) is used as the source clock */ -} pwm_clock_source_t; - -/*! @brief PWM prescaler factor selection for clock source*/ -typedef enum _pwm_clock_prescale -{ - kPWM_Prescale_Divide_1 = 0U, /*!< PWM clock frequency = fclk/1 */ - kPWM_Prescale_Divide_2, /*!< PWM clock frequency = fclk/2 */ - kPWM_Prescale_Divide_4, /*!< PWM clock frequency = fclk/4 */ - kPWM_Prescale_Divide_8, /*!< PWM clock frequency = fclk/8 */ - kPWM_Prescale_Divide_16, /*!< PWM clock frequency = fclk/16 */ - kPWM_Prescale_Divide_32, /*!< PWM clock frequency = fclk/32 */ - kPWM_Prescale_Divide_64, /*!< PWM clock frequency = fclk/64 */ - kPWM_Prescale_Divide_128 /*!< PWM clock frequency = fclk/128 */ -} pwm_clock_prescale_t; - -/*! @brief Options that can trigger a PWM FORCE_OUT */ -typedef enum _pwm_force_output_trigger -{ - kPWM_Force_Local = 0U, /*!< The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ - kPWM_Force_Master, /*!< The master force signal from submodule 0 is used to force updates */ - kPWM_Force_LocalReload, /*!< The local reload signal from this submodule is used to force updates without regard to - the state of LDOK */ - kPWM_Force_MasterReload, /*!< The master reload signal from submodule 0 is used to force updates if LDOK is set */ - kPWM_Force_LocalSync, /*!< The local sync signal from this submodule is used to force updates */ - kPWM_Force_MasterSync, /*!< The master sync signal from submodule0 is used to force updates */ - kPWM_Force_External, /*!< The external force signal, EXT_FORCE, from outside the PWM module causes updates */ - kPWM_Force_ExternalSync /*!< The external sync signal, EXT_SYNC, from outside the PWM module causes updates */ -} pwm_force_output_trigger_t; - -/*! @brief PWM counter initialization options */ -typedef enum _pwm_init_source -{ - kPWM_Initialize_LocalSync = 0U, /*!< Local sync causes initialization */ - kPWM_Initialize_MasterReload, /*!< Master reload from submodule 0 causes initialization */ - kPWM_Initialize_MasterSync, /*!< Master sync from submodule 0 causes initialization */ - kPWM_Initialize_ExtSync /*!< EXT_SYNC causes initialization */ -} pwm_init_source_t; - -/*! @brief PWM load frequency selection */ -typedef enum _pwm_load_frequency -{ - kPWM_LoadEveryOportunity = 0U, /*!< Every PWM opportunity */ - kPWM_LoadEvery2Oportunity, /*!< Every 2 PWM opportunities */ - kPWM_LoadEvery3Oportunity, /*!< Every 3 PWM opportunities */ - kPWM_LoadEvery4Oportunity, /*!< Every 4 PWM opportunities */ - kPWM_LoadEvery5Oportunity, /*!< Every 5 PWM opportunities */ - kPWM_LoadEvery6Oportunity, /*!< Every 6 PWM opportunities */ - kPWM_LoadEvery7Oportunity, /*!< Every 7 PWM opportunities */ - kPWM_LoadEvery8Oportunity, /*!< Every 8 PWM opportunities */ - kPWM_LoadEvery9Oportunity, /*!< Every 9 PWM opportunities */ - kPWM_LoadEvery10Oportunity, /*!< Every 10 PWM opportunities */ - kPWM_LoadEvery11Oportunity, /*!< Every 11 PWM opportunities */ - kPWM_LoadEvery12Oportunity, /*!< Every 12 PWM opportunities */ - kPWM_LoadEvery13Oportunity, /*!< Every 13 PWM opportunities */ - kPWM_LoadEvery14Oportunity, /*!< Every 14 PWM opportunities */ - kPWM_LoadEvery15Oportunity, /*!< Every 15 PWM opportunities */ - kPWM_LoadEvery16Oportunity /*!< Every 16 PWM opportunities */ -} pwm_load_frequency_t; - -/*! @brief List of PWM fault selections */ -typedef enum _pwm_fault_input -{ - kPWM_Fault_0 = 0U, /*!< Fault 0 input pin */ - kPWM_Fault_1, /*!< Fault 1 input pin */ - kPWM_Fault_2, /*!< Fault 2 input pin */ - kPWM_Fault_3 /*!< Fault 3 input pin */ -} pwm_fault_input_t; - -/*! @brief PWM capture edge select */ -typedef enum _pwm_input_capture_edge -{ - kPWM_Disable = 0U, /*!< Disabled */ - kPWM_FallingEdge, /*!< Capture on falling edge only */ - kPWM_RisingEdge, /*!< Capture on rising edge only */ - kPWM_RiseAndFallEdge /*!< Capture on rising or falling edge */ -} pwm_input_capture_edge_t; - -/*! @brief PWM output options when a FORCE_OUT signal is asserted */ -typedef enum _pwm_force_signal -{ - kPWM_UsePwm = 0U, /*!< Generated PWM signal is used by the deadtime logic.*/ - kPWM_InvertedPwm, /*!< Inverted PWM signal is used by the deadtime logic.*/ - kPWM_SoftwareControl, /*!< Software controlled value is used by the deadtime logic. */ - kPWM_UseExternal /*!< PWM_EXTA signal is used by the deadtime logic. */ -} pwm_force_signal_t; - -/*! @brief Options available for the PWM A & B pair operation */ -typedef enum _pwm_chnl_pair_operation -{ - kPWM_Independent = 0U, /*!< PWM A & PWM B operate as 2 independent channels */ - kPWM_ComplementaryPwmA, /*!< PWM A & PWM B are complementary channels, PWM A generates the signal */ - kPWM_ComplementaryPwmB /*!< PWM A & PWM B are complementary channels, PWM B generates the signal */ -} pwm_chnl_pair_operation_t; - -/*! @brief Options available on how to load the buffered-registers with new values */ -typedef enum _pwm_register_reload -{ - kPWM_ReloadImmediate = 0U, /*!< Buffered-registers get loaded with new values as soon as LDOK bit is set */ - kPWM_ReloadPwmHalfCycle, /*!< Registers loaded on a PWM half cycle */ - kPWM_ReloadPwmFullCycle, /*!< Registers loaded on a PWM full cycle */ - kPWM_ReloadPwmHalfAndFullCycle /*!< Registers loaded on a PWM half & full cycle */ -} pwm_register_reload_t; - -/*! @brief Options available on how to re-enable the PWM output when recovering from a fault */ -typedef enum _pwm_fault_recovery_mode -{ - kPWM_NoRecovery = 0U, /*!< PWM output will stay inactive */ - kPWM_RecoverHalfCycle, /*!< PWM output re-enabled at the first half cycle */ - kPWM_RecoverFullCycle, /*!< PWM output re-enabled at the first full cycle */ - kPWM_RecoverHalfAndFullCycle /*!< PWM output re-enabled at the first half or full cycle */ -} pwm_fault_recovery_mode_t; - -/*! @brief List of PWM interrupt options */ -typedef enum _pwm_interrupt_enable -{ - kPWM_CompareVal0InterruptEnable = (1U << 0), /*!< PWM VAL0 compare interrupt */ - kPWM_CompareVal1InterruptEnable = (1U << 1), /*!< PWM VAL1 compare interrupt */ - kPWM_CompareVal2InterruptEnable = (1U << 2), /*!< PWM VAL2 compare interrupt */ - kPWM_CompareVal3InterruptEnable = (1U << 3), /*!< PWM VAL3 compare interrupt */ - kPWM_CompareVal4InterruptEnable = (1U << 4), /*!< PWM VAL4 compare interrupt */ - kPWM_CompareVal5InterruptEnable = (1U << 5), /*!< PWM VAL5 compare interrupt */ - kPWM_CaptureX0InterruptEnable = (1U << 6), /*!< PWM capture X0 interrupt */ - kPWM_CaptureX1InterruptEnable = (1U << 7), /*!< PWM capture X1 interrupt */ - kPWM_CaptureB0InterruptEnable = (1U << 8), /*!< PWM capture B0 interrupt */ - kPWM_CaptureB1InterruptEnable = (1U << 9), /*!< PWM capture B1 interrupt */ - kPWM_CaptureA0InterruptEnable = (1U << 10), /*!< PWM capture A0 interrupt */ - kPWM_CaptureA1InterruptEnable = (1U << 11), /*!< PWM capture A1 interrupt */ - kPWM_ReloadInterruptEnable = (1U << 12), /*!< PWM reload interrupt */ - kPWM_ReloadErrorInterruptEnable = (1U << 13), /*!< PWM reload error interrupt */ - kPWM_Fault0InterruptEnable = (1U << 16), /*!< PWM fault 0 interrupt */ - kPWM_Fault1InterruptEnable = (1U << 17), /*!< PWM fault 1 interrupt */ - kPWM_Fault2InterruptEnable = (1U << 18), /*!< PWM fault 2 interrupt */ - kPWM_Fault3InterruptEnable = (1U << 19) /*!< PWM fault 3 interrupt */ -} pwm_interrupt_enable_t; - -/*! @brief List of PWM status flags */ -typedef enum _pwm_status_flags -{ - kPWM_CompareVal0Flag = (1U << 0), /*!< PWM VAL0 compare flag */ - kPWM_CompareVal1Flag = (1U << 1), /*!< PWM VAL1 compare flag */ - kPWM_CompareVal2Flag = (1U << 2), /*!< PWM VAL2 compare flag */ - kPWM_CompareVal3Flag = (1U << 3), /*!< PWM VAL3 compare flag */ - kPWM_CompareVal4Flag = (1U << 4), /*!< PWM VAL4 compare flag */ - kPWM_CompareVal5Flag = (1U << 5), /*!< PWM VAL5 compare flag */ - kPWM_CaptureX0Flag = (1U << 6), /*!< PWM capture X0 flag */ - kPWM_CaptureX1Flag = (1U << 7), /*!< PWM capture X1 flag */ - kPWM_CaptureB0Flag = (1U << 8), /*!< PWM capture B0 flag */ - kPWM_CaptureB1Flag = (1U << 9), /*!< PWM capture B1 flag */ - kPWM_CaptureA0Flag = (1U << 10), /*!< PWM capture A0 flag */ - kPWM_CaptureA1Flag = (1U << 11), /*!< PWM capture A1 flag */ - kPWM_ReloadFlag = (1U << 12), /*!< PWM reload flag */ - kPWM_ReloadErrorFlag = (1U << 13), /*!< PWM reload error flag */ - kPWM_RegUpdatedFlag = (1U << 14), /*!< PWM registers updated flag */ - kPWM_Fault0Flag = (1U << 16), /*!< PWM fault 0 flag */ - kPWM_Fault1Flag = (1U << 17), /*!< PWM fault 1 flag */ - kPWM_Fault2Flag = (1U << 18), /*!< PWM fault 2 flag */ - kPWM_Fault3Flag = (1U << 19) /*!< PWM fault 3 flag */ -} pwm_status_flags_t; - -/*! @brief PWM operation mode */ -typedef enum _pwm_mode -{ - kPWM_SignedCenterAligned = 0U, /*!< Signed center-aligned */ - kPWM_CenterAligned, /*!< Unsigned cente-aligned */ - kPWM_SignedEdgeAligned, /*!< Signed edge-aligned */ - kPWM_EdgeAligned /*!< Unsigned edge-aligned */ -} pwm_mode_t; - -/*! @brief PWM output pulse mode, high-true or low-true */ -typedef enum _pwm_level_select -{ - kPWM_HighTrue = 0U, /*!< High level represents "on" or "active" state */ - kPWM_LowTrue /*!< Low level represents "on" or "active" state */ -} pwm_level_select_t; - -/*! @brief PWM reload source select */ -typedef enum _pwm_reload_source_select -{ - kPWM_LocalReload = 0U, /*!< The local reload signal is used to reload registers */ - kPWM_MasterReload /*!< The master reload signal (from submodule 0) is used to reload */ -} pwm_reload_source_select_t; - -/*! @brief PWM fault clearing options */ -typedef enum _pwm_fault_clear -{ - kPWM_Automatic = 0U, /*!< Automatic fault clearing */ - kPWM_ManualNormal, /*!< Manual fault clearing with no fault safety mode */ - kPWM_ManualSafety /*!< Manual fault clearing with fault safety mode */ -} pwm_fault_clear_t; - -/*! @brief Options for submodule master control operation */ -typedef enum _pwm_module_control -{ - kPWM_Control_Module_0 = (1U << 0), /*!< Control submodule 0's start/stop,buffer reload operation */ - kPWM_Control_Module_1 = (1U << 1), /*!< Control submodule 1's start/stop,buffer reload operation */ - kPWM_Control_Module_2 = (1U << 2), /*!< Control submodule 2's start/stop,buffer reload operation */ - kPWM_Control_Module_3 = (1U << 3) /*!< Control submodule 3's start/stop,buffer reload operation */ -} pwm_module_control_t; - -/*! @brief Structure for the user to define the PWM signal characteristics */ -typedef struct _pwm_signal_param -{ - pwm_channels_t pwmChannel; /*!< PWM channel being configured; PWM A or PWM B */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 - 0=inactive signal(0% duty cycle)... - 100=always active signal (100% duty cycle)*/ - pwm_level_select_t level; /*!< PWM output active level select */ - uint16_t deadtimeValue; /*!< The deadtime value; only used if channel pair is operating in complementary mode */ -} pwm_signal_param_t; - -/*! - * @brief PWM config structure - * - * This structure holds the configuration settings for the PWM peripheral. To initialize this - * structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _pwm_config -{ - bool enableDebugMode; /*!< true: PWM continues to run in debug mode; - false: PWM is paused in debug mode */ - bool enableWait; /*!< true: PWM continues to run in WAIT mode; - false: PWM is paused in WAIT mode */ - uint8_t faultFilterCount; /*!< Fault filter count */ - uint8_t faultFilterPeriod; /*!< Fault filter period;value of 0 will bypass the filter */ - pwm_init_source_t initializationControl; /*!< Option to initialize the counter */ - pwm_clock_source_t clockSource; /*!< Clock source for the counter */ - pwm_clock_prescale_t prescale; /*!< Pre-scaler to divide down the clock */ - pwm_chnl_pair_operation_t pairOperation; /*!< Channel pair in indepedent or complementary mode */ - pwm_register_reload_t reloadLogic; /*!< PWM Reload logic setup */ - pwm_reload_source_select_t reloadSelect; /*!< Reload source select */ - pwm_load_frequency_t reloadFrequency; /*!< Specifies when to reload, used when user's choice - is not immediate reload */ - pwm_force_output_trigger_t forceTrigger; /*!< Specify which signal will trigger a FORCE_OUT */ -} pwm_config_t; - -/*! @brief Structure is used to hold the parameters to configure a PWM fault */ -typedef struct _pwm_fault_param -{ - pwm_fault_clear_t faultClearingMode; /*!< Fault clearing mode to use */ - bool faultLevel; /*!< true: Logic 1 indicates fault; - false: Logic 0 indicates fault */ - bool enableCombinationalPath; /*!< true: Combinational Path from fault input is enabled; - false: No combination path is available */ - pwm_fault_recovery_mode_t recoverMode; /*!< Specify when to re-enable the PWM output */ -} pwm_fault_param_t; - -/*! - * @brief Structure is used to hold parameters to configure the capture capability of a signal pin - */ -typedef struct _pwm_input_capture_param -{ - bool captureInputSel; /*!< true: Use the edge counter signal as source - false: Use the raw input signal from the pin as source */ - uint8_t edgeCompareValue; /*!< Compare value, used only if edge counter is used as source */ - pwm_input_capture_edge_t edge0; /*!< Specify which edge causes a capture for input circuitry 0 */ - pwm_input_capture_edge_t edge1; /*!< Specify which edge causes a capture for input circuitry 1 */ - bool enableOneShotCapture; /*!< true: Use one-shot capture mode; - false: Use free-running capture mode */ - uint8_t fifoWatermark; /*!< Watermark level for capture FIFO. The capture flags in - the status register will set if the word count in the FIFO - is greater than this watermark level */ -} pwm_input_capture_param_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the PWM submodule clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the PWM driver. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param config Pointer to user's PWM config structure. - * - * @return kStatus_Success means success; else failed. - */ -status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config); - -/*! - * @brief Gate the PWM submodule clock - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to deinitialize - */ -void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule); - -/*! - * @brief Fill in the PWM config struct with the default settings - * - * The default values are: - * @code - * config->enableDebugMode = false; - * config->enableWait = false; - * config->reloadSelect = kPWM_LocalReload; - * config->faultFilterCount = 0; - * config->faultFilterPeriod = 0; - * config->clockSource = kPWM_BusClock; - * config->prescale = kPWM_Prescale_Divide_1; - * config->initializationControl = kPWM_Initialize_LocalSync; - * config->forceTrigger = kPWM_Force_Local; - * config->reloadFrequency = kPWM_LoadEveryOportunity; - * config->reloadLogic = kPWM_ReloadImmediate; - * config->pairOperation = kPWM_Independent; - * @endcode - * @param config Pointer to user's PWM config structure. - */ -void PWM_GetDefaultConfig(pwm_config_t *config); - -/*! @}*/ - -/*! - * @name Module PWM output - * @{ - */ -/*! - * @brief Sets up the PWM signals for a PWM submodule. - * - * The function initializes the submodule according to the parameters passed in by the user. The function - * also sets up the value compare registers to match the PWM signal requirements. - * If the dead time insertion logic is enabled, the pulse period is reduced by the - * dead time period specified by the user. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param chnlParams Array of PWM channel parameters to configure the channel(s) - * @param numOfChnls Number of channels to configure, this should be the size of the array passed in. - * Array size should not be more than 2 as each submodule has 2 pins to output PWM - * @param mode PWM operation mode, options available in enumeration ::pwm_mode_t - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz PWM main counter clock in Hz. - * - * @return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise - */ -status_t PWM_SetupPwm(PWM_Type *base, - pwm_submodule_t subModule, - const pwm_signal_param_t *chnlParams, - uint8_t numOfChnls, - pwm_mode_t mode, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz); - -/*! - * @brief Updates the PWM signal's dutycycle. - * - * The function updates the PWM dutycyle to the new value that is passed in. - * If the dead time insertion logic is enabled then the pulse period is reduced by the - * dead time period specified by the user. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param pwmSignal Signal (PWM A or PWM B) to update - * @param currPwmMode The current PWM mode set during PWM setup - * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 - * 0=inactive signal(0% duty cycle)... - * 100=active signal (100% duty cycle) - */ -void PWM_UpdatePwmDutycycle(PWM_Type *base, - pwm_submodule_t subModule, - pwm_channels_t pwmSignal, - pwm_mode_t currPwmMode, - uint8_t dutyCyclePercent); - -/*! @}*/ - -/*! - * @brief Sets up the PWM input capture - * - * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function - * sets up the capture parameters for each pin and enables the pin for input capture operation. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param pwmChannel Channel in the submodule to setup - * @param inputCaptureParams Parameters passed in to set up the input pin - */ -void PWM_SetupInputCapture(PWM_Type *base, - pwm_submodule_t subModule, - pwm_channels_t pwmChannel, - const pwm_input_capture_param_t *inputCaptureParams); - -/*! - * @brief Sets up the PWM fault protection. - * - * PWM has 4 fault inputs. - * - * @param base PWM peripheral base address - * @param faultNum PWM fault to configure. - * @param faultParams Pointer to the PWM fault config structure - */ -void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams); - -/*! - * @brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. - * - * The user specifies which channel to configure by supplying the submodule number and whether - * to modify PWM A or PWM B within that submodule. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param pwmChannel Channel to configure - * @param mode Signal to output when a FORCE_OUT is triggered - */ -void PWM_SetupForceSignal(PWM_Type *base, - pwm_submodule_t subModule, - pwm_channels_t pwmChannel, - pwm_force_signal_t mode); - -/*! - * @name Interrupts Interface - * @{ - */ - -/*! - * @brief Enables the selected PWM interrupts - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::pwm_interrupt_enable_t - */ -void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); - -/*! - * @brief Disables the selected PWM interrupts - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::pwm_interrupt_enable_t - */ -void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); - -/*! - * @brief Gets the enabled PWM interrupts - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::pwm_interrupt_enable_t - */ -uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule); - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the PWM status flags - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::pwm_status_flags_t - */ -uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule); - -/*! - * @brief Clears the PWM status flags - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::pwm_status_flags_t - */ -void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the PWM counter for a single or multiple submodules. - * - * Sets the Run bit which enables the clocks to the PWM submodule. This function can start multiple - * submodules at the same time. - * - * @param base PWM peripheral base address - * @param subModulesToStart PWM submodules to start. This is a logical OR of members of the - * enumeration ::pwm_module_control_t - */ -static inline void PWM_StartTimer(PWM_Type *base, uint8_t subModulesToStart) -{ - base->MCTRL |= PWM_MCTRL_RUN(subModulesToStart); -} - -/*! - * @brief Stops the PWM counter for a single or multiple submodules. - * - * Clears the Run bit which resets the submodule's counter. This function can stop multiple - * submodules at the same time. - * - * @param base PWM peripheral base address - * @param subModulesToStop PWM submodules to stop. This is a logical OR of members of the - * enumeration ::pwm_module_control_t - */ -static inline void PWM_StopTimer(PWM_Type *base, uint8_t subModulesToStop) -{ - base->MCTRL &= ~(PWM_MCTRL_RUN(subModulesToStop)); -} - -/*! @}*/ - -/*! - * @brief Enables or disables the PWM output trigger. - * - * This function allows the user to enable or disable the PWM trigger. The PWM has 2 triggers. Trigger 0 - * is activated when the counter matches VAL 0, VAL 2, or VAL 4 register. Trigger 1 is activated - * when the counter matches VAL 1, VAL 3, or VAL 5 register. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param valueRegister Value register that will activate the trigger - * @param activate true: Enable the trigger; false: Disable the trigger - */ -static inline void PWM_OutputTriggerEnable(PWM_Type *base, - pwm_submodule_t subModule, - pwm_value_register_t valueRegister, - bool activate) -{ - if (activate) - { - base->SM[subModule].TCTRL |= (1U << valueRegister); - } - else - { - base->SM[subModule].TCTRL &= ~(1U << valueRegister); - } -} - -/*! - * @brief Sets the software control output for a pin to high or low. - * - * The user specifies which channel to modify by supplying the submodule number and whether - * to modify PWM A or PWM B within that submodule. - * - * @param base PWM peripheral base address - * @param subModule PWM submodule to configure - * @param pwmChannel Channel to configure - * @param value true: Supply a logic 1, false: Supply a logic 0. - */ -static inline void PWM_SetupSwCtrlOut(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool value) -{ - if (value) - { - base->SWCOUT |= (1U << ((subModule * PWM_SUBMODULE_SWCONTROL_WIDTH) + pwmChannel)); - } - else - { - base->SWCOUT &= ~(1U << ((subModule * PWM_SUBMODULE_SWCONTROL_WIDTH) + pwmChannel)); - } -} - -/*! - * @brief Sets or clears the PWM LDOK bit on a single or multiple submodules - * - * Set LDOK bit to load buffered values into CTRL[PRSC] and the INIT, FRACVAL and VAL registers. The - * values are loaded immediately if kPWM_ReloadImmediate option was choosen during config. Else the - * values are loaded at the next PWM reload point. - * This function can issue the load command to multiple submodules at the same time. - * - * @param base PWM peripheral base address - * @param subModulesToUpdate PWM submodules to update with buffered values. This is a logical OR of - * members of the enumeration ::pwm_module_control_t - * @param value true: Set LDOK bit for the submodule list; false: Clear LDOK bit - */ -static inline void PWM_SetPwmLdok(PWM_Type *base, uint8_t subModulesToUpdate, bool value) -{ - if (value) - { - base->MCTRL |= PWM_MCTRL_LDOK(subModulesToUpdate); - } - else - { - base->MCTRL |= PWM_MCTRL_CLDOK(subModulesToUpdate); - } -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PWM_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pxp.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_pxp.c deleted file mode 100644 index 4bc424c967..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pxp.c +++ /dev/null @@ -1,533 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2017, NXP Semiconductors, Inc. - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_pxp.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.pxp" -#endif - -/* The CSC2 coefficient is ###.####_#### */ -#define PXP_CSC2_COEF_INT_WIDTH 2 -#define PXP_CSC2_COEF_FRAC_WIDTH 8 - -/* Compatibility map macro. */ -#if defined(PXP_PS_CLRKEYLOW_0_PIXEL_MASK) && (!defined(PXP_PS_CLRKEYLOW_PIXEL_MASK)) -#define PS_CLRKEYLOW PS_CLRKEYLOW_0 -#define PS_CLRKEYHIGH PS_CLRKEYHIGH_0 -#endif -#if defined(PXP_AS_CLRKEYLOW_0_PIXEL_MASK) && (!defined(PXP_AS_CLRKEYLOW_PIXEL_MASK)) -#define AS_CLRKEYLOW AS_CLRKEYLOW_0 -#define AS_CLRKEYHIGH AS_CLRKEYHIGH_0 -#endif - -typedef union _u32_f32 -{ - float f32; - uint32_t u32; -} u32_f32_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance from the base address - * - * @param base PXP peripheral base address - * - * @return The PXP module instance - */ -static uint32_t PXP_GetInstance(PXP_Type *base); - -#if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2) -/*! - * @brief Convert IEEE 754 float value to the value could be written to registers. - * - * This function converts the float value to integer value to set the scaler - * and CSC parameters. - * - * This function is an alternative implemention of the following code with no - * MISRA 2004 rule 10.4 error: - * - * @code - return (uint32_t)(floatValue * (float)(1 << fracBits)); - @endcode - * - * @param floatValue The float value to convert. - * @param intBits Bits number of integer part in result. - * @param fracBits Bits number of fractional part in result. - * @return The value to set to register. - */ -static uint32_t PXP_ConvertFloat(float floatValue, uint8_t intBits, uint8_t fracBits); -#endif - -/*! - * @brief Convert the desired scale fact to DEC and PS_SCALE. - * - * @param inputDimension Input dimension. - * @param outputDimension Output dimension. - * @param dec The decimation filter contr0l value. - * @param scale The scale value set to register PS_SCALE. - */ -static void PXP_GetScalerParam(uint16_t inputDimension, uint16_t outputDimension, uint8_t *dec, uint32_t *scale); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to PXP bases for each instance. */ -static PXP_Type *const s_pxpBases[] = PXP_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to PXP clocks for each PXP submodule. */ -static const clock_ip_name_t s_pxpClocks[] = PXP_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t PXP_GetInstance(PXP_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_pxpBases); instance++) - { - if (s_pxpBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_pxpBases)); - - return instance; -} - -#if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2) -static uint32_t PXP_ConvertFloat(float floatValue, uint8_t intBits, uint8_t fracBits) -{ - /* One bit reserved for sign bit. */ - assert(intBits + fracBits < 32); - - u32_f32_t u32_f32; - uint32_t ret; - - u32_f32.f32 = floatValue; - uint32_t floatBits = u32_f32.u32; - int32_t expValue = (int32_t)((floatBits & 0x7F800000U) >> 23U) - 127; - - ret = (floatBits & 0x007FFFFFU) | 0x00800000U; - expValue += fracBits; - - if (expValue < 0) - { - return 0U; - } - else if (expValue > 23) - { - /* should not exceed 31-bit when left shift. */ - assert((expValue - 23) <= 7); - ret <<= (expValue - 23); - } - else - { - ret >>= (23 - expValue); - } - - /* Set the sign bit. */ - if (floatBits & 0x80000000U) - { - ret = ((~ret) + 1U) & ~(((uint32_t)-1) << (intBits + fracBits + 1)); - } - - return ret; -} -#endif - -static void PXP_GetScalerParam(uint16_t inputDimension, uint16_t outputDimension, uint8_t *dec, uint32_t *scale) -{ - uint32_t scaleFact = ((uint32_t)inputDimension << 12U) / outputDimension; - - if (scaleFact >= (16U << 12U)) - { - /* Desired fact is two large, use the largest support value. */ - *dec = 3U; - *scale = 0x2000U; - } - else - { - if (scaleFact > (8U << 12U)) - { - *dec = 3U; - } - else if (scaleFact > (4U << 12U)) - { - *dec = 2U; - } - else if (scaleFact > (2U << 12U)) - { - *dec = 1U; - } - else - { - *dec = 0U; - } - - *scale = scaleFact >> (*dec); - - if (0U == *scale) - { - *scale = 1U; - } - } -} - -void PXP_Init(PXP_Type *base) -{ - uint32_t ctrl = 0U; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - uint32_t instance = PXP_GetInstance(base); - CLOCK_EnableClock(s_pxpClocks[instance]); -#endif - - PXP_Reset(base); - -/* Enable the process engine in primary processing flow. */ -#if defined(PXP_CTRL_ENABLE_ROTATE0_MASK) - ctrl |= PXP_CTRL_ENABLE_ROTATE0_MASK; -#endif -#if defined(PXP_CTRL_ENABLE_ROTATE1_MASK) - ctrl |= PXP_CTRL_ENABLE_ROTATE1_MASK; -#endif -#if defined(PXP_CTRL_ENABLE_CSC2_MASK) - ctrl |= PXP_CTRL_ENABLE_CSC2_MASK; -#endif -#if defined(PXP_CTRL_ENABLE_LUT_MASK) - ctrl |= PXP_CTRL_ENABLE_LUT_MASK; -#endif -#if defined(PXP_CTRL_ENABLE_PS_AS_OUT_MASK) - ctrl |= PXP_CTRL_ENABLE_PS_AS_OUT_MASK; -#endif - - base->CTRL = ctrl; -} - -void PXP_Deinit(PXP_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - uint32_t instance = PXP_GetInstance(base); - CLOCK_DisableClock(s_pxpClocks[instance]); -#endif -} - -void PXP_Reset(PXP_Type *base) -{ - base->CTRL_SET = PXP_CTRL_SFTRST_MASK; - base->CTRL_CLR = (PXP_CTRL_SFTRST_MASK | PXP_CTRL_CLKGATE_MASK); -} - -void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config) -{ - assert(config); - - base->AS_CTRL = (base->AS_CTRL & ~PXP_AS_CTRL_FORMAT_MASK) | PXP_AS_CTRL_FORMAT(config->pixelFormat); - - base->AS_BUF = config->bufferAddr; - base->AS_PITCH = config->pitchBytes; -} - -void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config) -{ - assert(config); - uint32_t reg; - - reg = base->AS_CTRL; - reg &= - ~(PXP_AS_CTRL_ALPHA0_INVERT_MASK | PXP_AS_CTRL_ROP_MASK | PXP_AS_CTRL_ALPHA_MASK | PXP_AS_CTRL_ALPHA_CTRL_MASK); - reg |= (PXP_AS_CTRL_ROP(config->ropMode) | PXP_AS_CTRL_ALPHA(config->alpha) | - PXP_AS_CTRL_ALPHA_CTRL(config->alphaMode)); - - if (config->invertAlpha) - { - reg |= PXP_AS_CTRL_ALPHA0_INVERT_MASK; - } - - base->AS_CTRL = reg; -} - -void PXP_SetAlphaSurfacePosition( - PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY) -{ - base->OUT_AS_ULC = PXP_OUT_AS_ULC_Y(upperLeftY) | PXP_OUT_AS_ULC_X(upperLeftX); - base->OUT_AS_LRC = PXP_OUT_AS_LRC_Y(lowerRightY) | PXP_OUT_AS_LRC_X(lowerRightX); -} - -void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh) -{ - base->AS_CLRKEYLOW = colorKeyLow; - base->AS_CLRKEYHIGH = colorKeyHigh; -} - -void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config) -{ - assert(config); - - base->PS_CTRL = ((base->PS_CTRL & ~(PXP_PS_CTRL_FORMAT_MASK | PXP_PS_CTRL_WB_SWAP_MASK)) | - PXP_PS_CTRL_FORMAT(config->pixelFormat) | PXP_PS_CTRL_WB_SWAP(config->swapByte)); - - base->PS_BUF = config->bufferAddr; - base->PS_UBUF = config->bufferAddrU; - base->PS_VBUF = config->bufferAddrV; - base->PS_PITCH = config->pitchBytes; -} - -void PXP_SetProcessSurfaceScaler( - PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight) -{ - uint8_t decX, decY; - uint32_t scaleX, scaleY; - - PXP_GetScalerParam(inputWidth, outputWidth, &decX, &scaleX); - PXP_GetScalerParam(inputHeight, outputHeight, &decY, &scaleY); - - base->PS_CTRL = (base->PS_CTRL & ~(PXP_PS_CTRL_DECX_MASK | PXP_PS_CTRL_DECY_MASK)) | PXP_PS_CTRL_DECX(decX) | - PXP_PS_CTRL_DECY(decY); - - base->PS_SCALE = PXP_PS_SCALE_XSCALE(scaleX) | PXP_PS_SCALE_YSCALE(scaleY); -} - -void PXP_SetProcessSurfacePosition( - PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY) -{ - base->OUT_PS_ULC = PXP_OUT_PS_ULC_Y(upperLeftY) | PXP_OUT_PS_ULC_X(upperLeftX); - base->OUT_PS_LRC = PXP_OUT_PS_LRC_Y(lowerRightY) | PXP_OUT_PS_LRC_X(lowerRightX); -} - -void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh) -{ - base->PS_CLRKEYLOW = colorKeyLow; - base->PS_CLRKEYHIGH = colorKeyHigh; -} - -void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config) -{ - assert(config); - - base->OUT_CTRL = (base->OUT_CTRL & ~(PXP_OUT_CTRL_FORMAT_MASK | PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)) | - PXP_OUT_CTRL_FORMAT(config->pixelFormat) | PXP_OUT_CTRL_INTERLACED_OUTPUT(config->interlacedMode); - - base->OUT_BUF = config->buffer0Addr; - base->OUT_BUF2 = config->buffer1Addr; - - base->OUT_PITCH = config->pitchBytes; - base->OUT_LRC = PXP_OUT_LRC_Y(config->height - 1U) | PXP_OUT_LRC_X(config->width - 1U); - -/* - * The dither store size must be set to the same with the output buffer size, - * otherwise the dither engine could not work. - */ -#if defined(PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK) - base->DITHER_STORE_SIZE_CH0 = PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(config->width - 1U) | - PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(config->height - 1U); -#endif -} - -#if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2) -void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config) -{ - assert(config); - - base->CSC2_CTRL = (base->CSC2_CTRL & ~PXP_CSC2_CTRL_CSC_MODE_MASK) | PXP_CSC2_CTRL_CSC_MODE(config->mode); - - base->CSC2_COEF0 = - (PXP_ConvertFloat(config->A1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF0_A1_SHIFT) | - (PXP_ConvertFloat(config->A2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF0_A2_SHIFT); - - base->CSC2_COEF1 = - (PXP_ConvertFloat(config->A3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF1_A3_SHIFT) | - (PXP_ConvertFloat(config->B1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF1_B1_SHIFT); - - base->CSC2_COEF2 = - (PXP_ConvertFloat(config->B2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF2_B2_SHIFT) | - (PXP_ConvertFloat(config->B3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF2_B3_SHIFT); - - base->CSC2_COEF3 = - (PXP_ConvertFloat(config->C1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF3_C1_SHIFT) | - (PXP_ConvertFloat(config->C2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF3_C2_SHIFT); - - base->CSC2_COEF4 = - (PXP_ConvertFloat(config->C3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF4_C3_SHIFT) | - PXP_CSC2_COEF4_D1(config->D1); - - base->CSC2_COEF5 = PXP_CSC2_COEF5_D2(config->D2) | PXP_CSC2_COEF5_D3(config->D3); -} -#endif - -void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode) -{ - /* - * The equations used for Colorspace conversion are: - * - * R = C0*(Y+Y_OFFSET) + C1(V+UV_OFFSET) - * G = C0*(Y+Y_OFFSET) + C3(U+UV_OFFSET) + C2(V+UV_OFFSET) - * B = C0*(Y+Y_OFFSET) + C4(U+UV_OFFSET) - */ - - if (kPXP_Csc1YUV2RGB == mode) - { - base->CSC1_COEF0 = (base->CSC1_COEF0 & - ~(PXP_CSC1_COEF0_C0_MASK | PXP_CSC1_COEF0_Y_OFFSET_MASK | PXP_CSC1_COEF0_UV_OFFSET_MASK | - PXP_CSC1_COEF0_YCBCR_MODE_MASK)) | - PXP_CSC1_COEF0_C0(0x100U) /* 1.00. */ - | PXP_CSC1_COEF0_Y_OFFSET(0x0U) /* 0. */ - | PXP_CSC1_COEF0_UV_OFFSET(0x0U); /* 0. */ - base->CSC1_COEF1 = PXP_CSC1_COEF1_C1(0x0123U) /* 1.140. */ - | PXP_CSC1_COEF1_C4(0x0208U); /* 2.032. */ - base->CSC1_COEF2 = PXP_CSC1_COEF2_C2(0x076BU) /* -0.851. */ - | PXP_CSC1_COEF2_C3(0x079BU); /* -0.394. */ - } - else - { - base->CSC1_COEF0 = (base->CSC1_COEF0 & - ~(PXP_CSC1_COEF0_C0_MASK | PXP_CSC1_COEF0_Y_OFFSET_MASK | PXP_CSC1_COEF0_UV_OFFSET_MASK)) | - PXP_CSC1_COEF0_YCBCR_MODE_MASK | PXP_CSC1_COEF0_C0(0x12AU) /* 1.164. */ - | PXP_CSC1_COEF0_Y_OFFSET(0x1F0U) /* -16. */ - | PXP_CSC1_COEF0_UV_OFFSET(0x180U); /* -128. */ - base->CSC1_COEF1 = PXP_CSC1_COEF1_C1(0x0198U) /* 1.596. */ - | PXP_CSC1_COEF1_C4(0x0204U); /* 2.017. */ - base->CSC1_COEF2 = PXP_CSC1_COEF2_C2(0x0730U) /* -0.813. */ - | PXP_CSC1_COEF2_C3(0x079CU); /* -0.392. */ - } -} - -#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) -void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config) -{ - base->LUT_CTRL = (base->LUT_CTRL & ~(PXP_LUT_CTRL_OUT_MODE_MASK | PXP_LUT_CTRL_LOOKUP_MODE_MASK)) | - PXP_LUT_CTRL_LRU_UPD_MASK | /* Use Least Recently Used Policy Update Control. */ - PXP_LUT_CTRL_OUT_MODE(config->outMode) | PXP_LUT_CTRL_LOOKUP_MODE(config->lookupMode); - - if (kPXP_LutOutRGBW4444CFA == config->outMode) - { - base->CFA = config->cfaValue; - } -} - -status_t PXP_LoadLutTable( - PXP_Type *base, pxp_lut_lookup_mode_t lookupMode, uint32_t bytesNum, uint32_t memAddr, uint16_t lutStartAddr) -{ - if (kPXP_LutCacheRGB565 == lookupMode) - { - /* Make sure the previous memory write is finished, especially the LUT data memory. */ - __DSB(); - - base->LUT_EXTMEM = memAddr; - /* Invalid cache. */ - base->LUT_CTRL |= PXP_LUT_CTRL_INVALID_MASK; - } - else - { - /* Number of bytes must be divisable by 8. */ - if ((bytesNum & 0x07U) || (bytesNum < 8U) || (lutStartAddr & 0x07U) || - (bytesNum + lutStartAddr > PXP_LUT_TABLE_BYTE)) - { - return kStatus_InvalidArgument; - } - - base->LUT_EXTMEM = memAddr; - base->LUT_ADDR = PXP_LUT_ADDR_ADDR(lutStartAddr) | PXP_LUT_ADDR_NUM_BYTES(bytesNum); - - base->STAT_CLR = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK; - - /* Start DMA transfer. */ - base->LUT_CTRL |= PXP_LUT_CTRL_DMA_START_MASK; - - __DSB(); - - /* Wait for transfer completed. */ - while (!(base->STAT & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)) - { - } - } - - return kStatus_Success; -} -#endif /* FSL_FEATURE_PXP_HAS_NO_LUT */ - -#if (defined(FSL_FEATURE_PXP_HAS_DITHER) && FSL_FEATURE_PXP_HAS_DITHER) -void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr) -{ - assert((memStartAddr + bytesNum) <= PXP_INTERNAL_RAM_LUT_BYTE); - - base->INIT_MEM_CTRL = - PXP_INIT_MEM_CTRL_ADDR(memStartAddr) | PXP_INIT_MEM_CTRL_SELECT(ram) | PXP_INIT_MEM_CTRL_START_MASK; - - while (bytesNum--) - { - base->INIT_MEM_DATA = (uint32_t)(*data); - data++; - } - - base->INIT_MEM_CTRL = 0U; -} - -void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data) -{ - base->DITHER_FINAL_LUT_DATA0 = data->data_3_0; - base->DITHER_FINAL_LUT_DATA1 = data->data_7_4; - base->DITHER_FINAL_LUT_DATA2 = data->data_11_8; - base->DITHER_FINAL_LUT_DATA3 = data->data_15_12; -} - -void PXP_EnableDither(PXP_Type *base, bool enable) -{ - if (enable) - { - base->CTRL_SET = PXP_CTRL_ENABLE_DITHER_MASK; - /* Route dither output to output buffer. */ - base->DATA_PATH_CTRL0 &= ~PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK; - } - else - { - base->CTRL_CLR = PXP_CTRL_ENABLE_DITHER_MASK; - /* Route MUX 12 output to output buffer. */ - base->DATA_PATH_CTRL0 |= PXP_DATA_PATH_CTRL0_MUX14_SEL(1U); - } -} -#endif /* FSL_FEATURE_PXP_HAS_DITHER */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pxp.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_pxp.h deleted file mode 100644 index 98f9d22cb8..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_pxp.h +++ /dev/null @@ -1,1235 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2017, NXP Semiconductors, Inc. - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_PXP_H_ -#define _FSL_PXP_H_ - -#include "fsl_common.h" - -/* Compatibility macro map. */ -#if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA0_INVERT_MASK)) -#define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK -#endif - -#if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA_INVERT_MASK)) -#define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK -#endif - -#if defined(PXP_STAT_IRQ_MASK) && (!defined(PXP_STAT_IRQ0_MASK)) -#define PXP_STAT_IRQ0_MASK PXP_STAT_IRQ_MASK -#endif - -#if defined(PXP_STAT_AXI_READ_ERROR_MASK) && (!defined(PXP_STAT_AXI_READ_ERROR_0_MASK)) -#define PXP_STAT_AXI_READ_ERROR_0_MASK PXP_STAT_AXI_READ_ERROR_MASK -#endif - -#if defined(PXP_STAT_AXI_WRITE_ERROR_MASK) && (!defined(PXP_STAT_AXI_WRITE_ERROR_0_MASK)) -#define PXP_STAT_AXI_WRITE_ERROR_0_MASK PXP_STAT_AXI_WRITE_ERROR_MASK -#endif - -/*! - * @addtogroup pxp_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* PXP global LUT table is 16K. */ -#define PXP_LUT_TABLE_BYTE (16 * 1024) -/* Intenral memory for LUT, the size is 256 bytes. */ -#define PXP_INTERNAL_RAM_LUT_BYTE (256) - -/*! @name Driver version */ -/*@{*/ -#define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/* This macto indicates whether the rotate sub module is shared by process surface and output buffer. */ -#if defined(PXP_CTRL_ROT_POS_MASK) -#define PXP_SHARE_ROTATE 1 -#else -#define PXP_SHARE_ROTATE 0 -#endif - -/*! @brief PXP interrupts to enable. */ -enum _pxp_interrupt_enable -{ - kPXP_CommandLoadInterruptEnable = PXP_CTRL_NEXT_IRQ_ENABLE_MASK, /*!< Interrupt to show that the command set - by @ref PXP_SetNextCommand has been loaded. */ - kPXP_CompleteInterruptEnable = PXP_CTRL_IRQ_ENABLE_MASK, /*!< PXP process completed. */ -#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) - kPXP_LutDmaLoadInterruptEnable = PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK, /*!< The LUT table has been loaded by DMA. */ -#endif -}; - -/*! - * @brief PXP status flags. - * - * @note These enumerations are meant to be OR'd together to form a bit mask. - */ -enum _pxp_flags -{ - kPXP_CommandLoadFlag = PXP_STAT_NEXT_IRQ_MASK, /*!< The command set by @ref PXP_SetNextCommand - has been loaded, could set new command. */ - kPXP_CompleteFlag = PXP_STAT_IRQ0_MASK, /*!< PXP process completed. */ -#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) - kPXP_LutDmaLoadFlag = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK, /*!< The LUT table has been loaded by DMA. */ -#endif - kPXP_Axi0ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_0_MASK, /*!< PXP encountered an AXI read error - and processing has been terminated. */ - kPXP_Axi0WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_0_MASK, /*!< PXP encountered an AXI write error - and processing has been terminated. */ -#if defined(PXP_STAT_AXI_READ_ERROR_1_MASK) - kPXP_Axi1ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_1_MASK, /*!< PXP encountered an AXI read error - and processing has been terminated. */ - kPXP_Axi1WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_1_MASK, /*!< PXP encountered an AXI write error - and processing has been terminated. */ -#endif -}; - -/*! @brief PXP output flip mode. */ -typedef enum _pxp_flip_mode -{ - kPXP_FlipDisable = 0U, /*!< Flip disable. */ - kPXP_FlipHorizontal = 0x01U, /*!< Horizontal flip. */ - kPXP_FlipVertical = 0x02U, /*!< Vertical flip. */ - kPXP_FlipBoth = 0x03U, /*!< Flip both directions. */ -} pxp_flip_mode_t; - -/*! @brief PXP rotate mode. */ -typedef enum _pxp_rotate_position -{ - kPXP_RotateOutputBuffer = 0U, /*!< Rotate the output buffer. */ - kPXP_RotateProcessSurface, /*!< Rotate the process surface. */ -} pxp_rotate_position_t; - -/*! @brief PXP rotate degree. */ -typedef enum _pxp_rotate_degree -{ - kPXP_Rotate0 = 0U, /*!< Clock wise rotate 0 deg. */ - kPXP_Rotate90, /*!< Clock wise rotate 90 deg. */ - kPXP_Rotate180, /*!< Clock wise rotate 180 deg. */ - kPXP_Rotate270, /*!< Clock wise rotate 270 deg. */ -} pxp_rotate_degree_t; - -/*! @brief PXP interlaced output mode. */ -typedef enum _pxp_interlaced_output_mode -{ - kPXP_OutputProgressive = 0U, /*!< All data written in progressive format to output buffer 0. */ - kPXP_OutputField0, /*!< Only write field 0 data to output buffer 0. */ - kPXP_OutputField1, /*!< Only write field 1 data to output buffer 0. */ - kPXP_OutputInterlaced, /*!< Field 0 write to buffer 0, field 1 write to buffer 1. */ -} pxp_interlaced_output_mode_t; - -/*! @brief PXP output buffer format. */ -typedef enum _pxp_output_pixel_format -{ - kPXP_OutputPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */ - kPXP_OutputPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */ - kPXP_OutputPixelFormatRGB888P = 0x5, /*!< 24-bit pixels without alpha (packed 24-bit format) */ - kPXP_OutputPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */ - kPXP_OutputPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */ - kPXP_OutputPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */ - kPXP_OutputPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */ - kPXP_OutputPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */ - kPXP_OutputPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */ - kPXP_OutputPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */ - kPXP_OutputPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */ - kPXP_OutputPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */ - kPXP_OutputPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */ - kPXP_OutputPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */ - kPXP_OutputPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */ - kPXP_OutputPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */ - kPXP_OutputPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */ -} pxp_output_pixel_format_t; - -/*! @brief PXP output buffer configuration. */ -typedef struct _pxp_output_buffer_config -{ - pxp_output_pixel_format_t pixelFormat; /*!< Output buffer pixel format. */ - pxp_interlaced_output_mode_t interlacedMode; /*!< Interlaced output mode. */ - uint32_t buffer0Addr; /*!< Output buffer 0 address. */ - uint32_t buffer1Addr; /*!< Output buffer 1 address, used for UV data in YUV 2-plane mode, or - field 1 in output interlaced mode. */ - uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */ - uint16_t width; /*!< Pixels per line. */ - uint16_t height; /*!< How many lines in output buffer. */ -} pxp_output_buffer_config_t; - -/*! @brief PXP process surface buffer pixel format. */ -typedef enum _pxp_ps_pixel_format -{ - kPXP_PsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */ - kPXP_PsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */ - kPXP_PsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */ - kPXP_PsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */ - kPXP_PsPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */ - kPXP_PsPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */ - kPXP_PsPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */ - kPXP_PsPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */ - kPXP_PsPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */ - kPXP_PsPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */ - kPXP_PsPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */ - kPXP_PsPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */ - kPXP_PsPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */ - kPXP_PsPixelFormatYVU422 = 0x1E, /*!< 16-bit pixels (3-plane) */ - kPXP_PsPixelFormatYVU420 = 0x1F, /*!< 16-bit pixels (3-plane) */ -} pxp_ps_pixel_format_t; - -/*! @brief PXP process surface buffer configuration. */ -typedef struct _pxp_ps_buffer_config -{ - pxp_ps_pixel_format_t pixelFormat; /*!< PS buffer pixel format. */ - bool swapByte; /*!< For each 16 bit word, set true to swap the two bytes. */ - uint32_t bufferAddr; /*!< Input buffer address for the first panel. */ - uint32_t bufferAddrU; /*!< Input buffer address for the second panel. */ - uint32_t bufferAddrV; /*!< Input buffer address for the third panel. */ - uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */ -} pxp_ps_buffer_config_t; - -/*! @brief PXP alpha surface buffer pixel format. */ -typedef enum _pxp_as_pixel_format -{ - kPXP_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */ - kPXP_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */ - kPXP_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */ - kPXP_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */ - kPXP_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */ - kPXP_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */ - kPXP_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */ -} pxp_as_pixel_format_t; - -/*! @brief PXP alphs surface buffer configuration. */ -typedef struct _pxp_as_buffer_config -{ - pxp_as_pixel_format_t pixelFormat; /*!< AS buffer pixel format. */ - uint32_t bufferAddr; /*!< Input buffer address. */ - uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */ -} pxp_as_buffer_config_t; - -/*! - * @brief PXP alpha mode during blending. - */ -typedef enum _pxp_alpha_mode -{ - kPXP_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */ - kPXP_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */ - kPXP_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined - alpha value will be used for blend, for example, pixel alpha set - set to 200, user defined alpha set to 100, then the reault alpha - is 200 * 100 / 255. */ - kPXP_AlphaRop /*!< Raster operation. */ -} pxp_alpha_mode_t; - -/*! - * @brief PXP ROP mode during blending. - * - * Explanation: - * - AS: Alpha surface - * - PS: Process surface - * - nAS: Alpha surface NOT value - * - nPS: Process surface NOT value - */ -typedef enum _pxp_rop_mode -{ - kPXP_RopMaskAs = 0x0, /*!< AS AND PS. */ - kPXP_RopMaskNotAs = 0x1, /*!< nAS AND PS. */ - kPXP_RopMaskAsNot = 0x2, /*!< AS AND nPS. */ - kPXP_RopMergeAs = 0x3, /*!< AS OR PS. */ - kPXP_RopMergeNotAs = 0x4, /*!< nAS OR PS. */ - kPXP_RopMergeAsNot = 0x5, /*!< AS OR nPS. */ - kPXP_RopNotCopyAs = 0x6, /*!< nAS. */ - kPXP_RopNot = 0x7, /*!< nPS. */ - kPXP_RopNotMaskAs = 0x8, /*!< AS NAND PS. */ - kPXP_RopNotMergeAs = 0x9, /*!< AS NOR PS. */ - kPXP_RopXorAs = 0xA, /*!< AS XOR PS. */ - kPXP_RopNotXorAs = 0xB /*!< AS XNOR PS. */ -} pxp_rop_mode_t; - -/*! - * @brief PXP alpha surface blending configuration. - */ -typedef struct _pxp_as_blend_config -{ - uint8_t alpha; /*!< User defined alpha value, only used when @ref alphaMode is @ref kPXP_AlphaOverride or @ref - kPXP_AlphaRop. */ - bool invertAlpha; /*!< Set true to invert the alpha. */ - pxp_alpha_mode_t alphaMode; /*!< Alpha mode. */ - pxp_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kPXP_AlphaRop. */ -} pxp_as_blend_config_t; - -/*! @brief PXP process block size. */ -typedef enum _pxp_block_size -{ - kPXP_BlockSize8 = 0U, /*!< Process 8x8 pixel blocks. */ - kPXP_BlockSize16, /*!< Process 16x16 pixel blocks. */ -} pxp_block_size_t; - -/*! @brief PXP CSC1 mode. */ -typedef enum _pxp_csc1_mode -{ - kPXP_Csc1YUV2RGB = 0U, /*!< YUV to RGB. */ - kPXP_Csc1YCbCr2RGB, /*!< YCbCr to RGB. */ -} pxp_csc1_mode_t; - -/*! @brief PXP CSC2 mode. */ -typedef enum _pxp_csc2_mode -{ - kPXP_Csc2YUV2RGB = 0U, /*!< YUV to RGB. */ - kPXP_Csc2YCbCr2RGB, /*!< YCbCr to RGB. */ - kPXP_Csc2RGB2YUV, /*!< RGB to YUV. */ - kPXP_Csc2RGB2YCbCr, /*!< RGB to YCbCr. */ -} pxp_csc2_mode_t; - -/*! - * @brief PXP CSC2 configuration. - * - * Converting from YUV/YCbCr color spaces to the RGB color space uses the - * following equation structure: - * - * R = A1(Y+D1) + A2(U+D2) + A3(V+D3) - * G = B1(Y+D1) + B2(U+D2) + B3(V+D3) - * B = C1(Y+D1) + C2(U+D2) + C3(V+D3) - * - * Converting from the RGB color space to YUV/YCbCr color spaces uses the - * following equation structure: - * - * Y = A1*R + A2*G + A3*B + D1 - * U = B1*R + B2*G + B3*B + D2 - * V = C1*R + C2*G + C3*B + D3 - */ -typedef struct _pxp_csc2_config -{ - pxp_csc2_mode_t mode; /*!< Convertion mode. */ - float A1; /*!< A1. */ - float A2; /*!< A2. */ - float A3; /*!< A3. */ - float B1; /*!< B1. */ - float B2; /*!< B2. */ - float B3; /*!< B3. */ - float C1; /*!< C1. */ - float C2; /*!< C2. */ - float C3; /*!< C3. */ - int16_t D1; /*!< D1. */ - int16_t D2; /*!< D2. */ - int16_t D3; /*!< D3. */ -} pxp_csc2_config_t; - -#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) -/*! @brief PXP LUT lookup mode. */ -typedef enum _pxp_lut_lookup_mode -{ - kPXP_LutCacheRGB565 = 0U, /*!< LUT ADDR = R[7:3],G[7:2],B[7:3]. Use all 16KB of LUT - for indirect cached 128KB lookup. */ - kPXP_LutDirectY8, /*!< LUT ADDR = 16'b0,Y[7:0]. Use the first 256 bytes of LUT. - Only third data path byte is tranformed. */ - kPXP_LutDirectRGB444, /*!< LUT ADDR = R[7:4],G[7:4],B[7:4]. Use one 8KB bank of LUT - selected by @ref PXP_Select8kLutBank. */ - kPXP_LutDirectRGB454, /*!< LUT ADDR = R[7:4],G[7:3],B[7:4]. Use all 16KB of LUT. */ -} pxp_lut_lookup_mode_t; - -/*! @brief PXP LUT output mode. */ -typedef enum _pxp_lut_out_mode -{ - kPXP_LutOutY8 = 1U, /*!< R/Y byte lane 2 lookup, bytes 1,0 bypassed. */ - kPXP_LutOutRGBW4444CFA, /*!< Byte lane 2 = CFA_Y8, byte lane 1,0 = RGBW4444. */ - kPXP_LutOutRGB888, /*!< RGB565->RGB888 conversion for Gamma correction. */ -} pxp_lut_out_mode_t; - -/*! @brief PXP LUT 8K bank index used when lookup mode is @ref kPXP_LutDirectRGB444. */ -typedef enum _pxp_lut_8k_bank -{ - kPXP_Lut8kBank0 = 0U, /*!< The first 8K bank used. */ - kPXP_Lut8kBank1, /*!< The second 8K bank used. */ -} pxp_lut_8k_bank_t; - -/*! @brief PXP LUT configuration. */ -typedef struct _pxp_lut_config -{ - pxp_lut_lookup_mode_t lookupMode; /*!< Look up mode. */ - pxp_lut_out_mode_t outMode; /*!< Out mode. */ - uint32_t cfaValue; /*!< The CFA value used when look up mode is @ref kPXP_LutOutRGBW4444CFA. */ -} pxp_lut_config_t; -#endif /* FSL_FEATURE_PXP_HAS_NO_LUT */ - -/*! @brief PXP internal memory. */ -typedef enum _pxp_ram -{ - kPXP_RamDither0Lut = 0U, /*!< Dither 0 LUT memory. */ - kPXP_RamDither1Lut = 3U, /*!< Dither 1 LUT memory. */ - kPXP_RamDither2Lut = 4U, /*!< Dither 2 LUT memory. */ -} pxp_ram_t; - -/*! @brief PXP dither mode. */ -enum _pxp_dither_mode -{ - kPXP_DitherPassThrough = 0U, /*!< Pass through, no dither. */ - kPXP_DitherOrdered = 3U, /*!< Ordered dither. */ - kPXP_DitherQuantOnly = 4U, /*!< No dithering, only quantization. */ -}; - -/*! @brief PXP dither LUT mode. */ -enum _pxp_dither_lut_mode -{ - kPXP_DitherLutOff = 0U, /*!< The LUT memory is not used for LUT, could be used as ordered dither index matrix. */ - kPXP_DitherLutPreDither, /*!< Use LUT at the pre-dither stage, The pre-dither LUT could only be used in Floyd mode - or Atkinson mode, which are not supported by current PXP module. */ - kPXP_DitherLutPostDither, /*!< Use LUT at the post-dither stage. */ -}; - -/*! @brief PXP dither matrix size. */ -enum _pxp_dither_matrix_size -{ - kPXP_DitherMatrix8 = 1, /*!< The dither index matrix is 8x8. */ - kPXP_DitherMatrix16, /*!< The dither index matrix is 16x16. */ -}; - -/*! @brief PXP dither final LUT data. */ -typedef struct _pxp_dither_final_lut_data -{ - uint32_t data_3_0; /*!< Data 3 to data 0. Data 0 is the least significant byte. */ - uint32_t data_7_4; /*!< Data 7 to data 4. Data 4 is the least significant byte. */ - uint32_t data_11_8; /*!< Data 11 to data 8. Data 8 is the least significant byte. */ - uint32_t data_15_12; /*!< Data 15 to data 12. Data 12 is the least significant byte. */ -} pxp_dither_final_lut_data_t; - -/*! @brief PXP dither configuration. */ -typedef struct _pxp_dither_config -{ - uint32_t enableDither0 : 1; /*!< Enable dither engine 0 or not, set 1 to enable, 0 to disable. */ - uint32_t enableDither1 : 1; /*!< Enable dither engine 1 or not, set 1 to enable, 0 to disable. */ - uint32_t enableDither2 : 1; /*!< Enable dither engine 2 or not, set 1 to enable, 0 to disable. */ - uint32_t ditherMode0 : 3; /*!< Dither mode for dither engine 0. See @ref _pxp_dither_mode. */ - uint32_t ditherMode1 : 3; /*!< Dither mode for dither engine 1. See @ref _pxp_dither_mode. */ - uint32_t ditherMode2 : 3; /*!< Dither mode for dither engine 2. See @ref _pxp_dither_mode. */ - uint32_t quantBitNum : 3; /*!< Number of bits quantize down to, the valid value is 1~7. */ - uint32_t lutMode : 2; /*!< How to use the memory LUT, see @ref _pxp_dither_lut_mode. This must be set to @ref - kPXP_DitherLutOff - if any dither engine uses @ref kPXP_DitherOrdered mode. */ - uint32_t idxMatrixSize0 : 2; /*!< Size of index matrix used for dither for dither engine 0, see @ref - _pxp_dither_matrix_size. */ - uint32_t idxMatrixSize1 : 2; /*!< Size of index matrix used for dither for dither engine 1, see @ref - _pxp_dither_matrix_size. */ - uint32_t idxMatrixSize2 : 2; /*!< Size of index matrix used for dither for dither engine 2, see @ref - _pxp_dither_matrix_size. */ - uint32_t enableFinalLut : 1; /*!< Enable the final LUT, set 1 to enable, 0 to disable. */ - uint32_t : 8; -} pxp_dither_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initialize the PXP. - * - * This function enables the PXP peripheral clock, and resets the PXP registers - * to default status. - * - * @param base PXP peripheral base address. - */ -void PXP_Init(PXP_Type *base); - -/*! - * @brief De-initialize the PXP. - * - * This function disables the PXP peripheral clock. - * - * @param base PXP peripheral base address. - */ -void PXP_Deinit(PXP_Type *base); - -/*! - * @brief Reset the PXP. - * - * This function resets the PXP peripheral registers to default status. - * - * @param base PXP peripheral base address. - */ -void PXP_Reset(PXP_Type *base); -/* @} */ - -/*! - * @name Global operations - * @{ - */ - -/*! - * @brief Start process. - * - * Start PXP process using current configuration. - * - * @param base PXP peripheral base address. - */ -static inline void PXP_Start(PXP_Type *base) -{ - base->CTRL_SET = PXP_CTRL_ENABLE_MASK; -} - -/*! - * @brief Enable or disable LCD hand shake. - * - * @param base PXP peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void PXP_EnableLcdHandShake(PXP_Type *base, bool enable) -{ -#if defined(PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK) - if (enable) - { - base->CTRL_SET = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK; - } - else - { - base->CTRL_CLR = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK; - } -#else - if (enable) - { - base->CTRL_SET = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK; - } - else - { - base->CTRL_CLR = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK; - } -#endif -} - -#if (defined(FSL_FEATURE_PXP_HAS_EN_REPEAT) && FSL_FEATURE_PXP_HAS_EN_REPEAT) -/*! - * @brief Enable or disable continous run. - * - * If continous run not enabled, @ref PXP_Start starts the PXP process. When completed, - * PXP enters idle mode and flag @ref kPXP_CompleteFlag asserts. - * - * If continous run enabled, the PXP will repeat based on the current configuration register - * settings. - * - * @param base PXP peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void PXP_EnableContinousRun(PXP_Type *base, bool enable) -{ - if (enable) - { - base->CTRL_SET = PXP_CTRL_EN_REPEAT_MASK; - } - else - { - base->CTRL_CLR = PXP_CTRL_EN_REPEAT_MASK; - } -} -#endif /* FSL_FEATURE_PXP_HAS_EN_REPEAT */ - -/*! - * @brief Set the PXP processing block size - * - * This function chooses the pixel block size that PXP using during process. - * Larger block size means better performace, but be careful that when PXP is - * rotating, the output must be divisible by the block size selected. - * - * @param base PXP peripheral base address. - * @param size The pixel block size. - */ -static inline void PXP_SetProcessBlockSize(PXP_Type *base, pxp_block_size_t size) -{ - base->CTRL = (base->CTRL & ~PXP_CTRL_BLOCK_SIZE_MASK) | PXP_CTRL_BLOCK_SIZE(size); -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets PXP status flags. - * - * This function gets all PXP status flags. The flags are returned as the logical - * OR value of the enumerators @ref _pxp_flags. To check a specific status, - * compare the return value with enumerators in @ref _pxp_flags. - * For example, to check whether the PXP has completed process, use like this: - * @code - if (kPXP_CompleteFlag & PXP_GetStatusFlags(PXP)) - { - ... - } - @endcode - * - * @param base PXP peripheral base address. - * @return PXP status flags which are OR'ed by the enumerators in the _pxp_flags. - */ -static inline uint32_t PXP_GetStatusFlags(PXP_Type *base) -{ -#if defined(PXP_STAT_AXI_READ_ERROR_1_MASK) - return base->STAT & - (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK | - PXP_STAT_AXI_WRITE_ERROR_0_MASK | PXP_STAT_AXI_READ_ERROR_1_MASK | PXP_STAT_AXI_WRITE_ERROR_1_MASK); -#else - return base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK | - PXP_STAT_AXI_WRITE_ERROR_0_MASK); -#endif -} - -/*! - * @brief Clears status flags with the provided mask. - * - * This function clears PXP status flags with a provided mask. - * - * @param base PXP peripheral base address. - * @param statusMask The status flags to be cleared; it is logical OR value of @ref _pxp_flags. - */ -static inline void PXP_ClearStatusFlags(PXP_Type *base, uint32_t statusMask) -{ - base->STAT_CLR = statusMask; -} - -/*! - * @brief Gets the AXI ID of the failing bus operation. - * - * @param base PXP peripheral base address. - * @param axiIndex Whitch AXI to get - * - 0: AXI0 - * - 1: AXI1 - * @return The AXI ID of the failing bus operation. - */ -static inline uint8_t PXP_GetAxiErrorId(PXP_Type *base, uint8_t axiIndex) -{ -#if defined(PXP_STAT_AXI_ERROR_ID_1_MASK) - if (0 == axiIndex) - { - return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_0_MASK) >> PXP_STAT_AXI_ERROR_ID_0_SHIFT); - } - else - { - return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_1_MASK) >> PXP_STAT_AXI_ERROR_ID_1_SHIFT); - } -#else - return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_MASK) >> PXP_STAT_AXI_ERROR_ID_SHIFT); -#endif -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables PXP interrupts according to the provided mask. - * - * This function enables the PXP interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref _pxp_interrupt_enable. - * For example, to enable PXP process complete interrupt and command loaded - * interrupt, do the following. - * @code - PXP_EnableInterrupts(PXP, kPXP_CommandLoadInterruptEnable | kPXP_CompleteInterruptEnable); - @endcode - * - * @param base PXP peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _pxp_interrupt_enable. - */ -static inline void PXP_EnableInterrupts(PXP_Type *base, uint32_t mask) -{ - base->CTRL_SET = mask; -} - -/*! - * @brief Disables PXP interrupts according to the provided mask. - * - * This function disables the PXP interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref _pxp_interrupt_enable. - * - * @param base PXP peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _pxp_interrupt_enable. - */ -static inline void PXP_DisableInterrupts(PXP_Type *base, uint32_t mask) -{ - base->CTRL_CLR = mask; -} - -/* @} */ - -/*! - * @name Alpha surface - * @{ - */ - -/*! - * @brief Set the alpha surface input buffer configuration. - * - * @param base PXP peripheral base address. - * @param config Pointer to the configuration. - */ -void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config); - -/*! - * @brief Set the alpha surface blending configuration. - * - * @param base PXP peripheral base address. - * @param config Pointer to the configuration structure. - */ -void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config); - -/*! - * @brief Set the alpha surface overlay color key. - * - * If a pixel in the current overlay image with a color that falls in the range - * from the @p colorKeyLow to @p colorKeyHigh range, it will use the process surface - * pixel value for that location. If no PS image is present or if the PS image also - * matches its colorkey range, the PS background color is used. - * - * @param base PXP peripheral base address. - * @param colorKeyLow Color key low range. - * @param colorKeyHigh Color key high range. - * - * @note Colorkey operations are higher priority than alpha or ROP operations - */ -void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh); - -/*! - * @brief Enable or disable the alpha surface color key. - * - * @param base PXP peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, bool enable) -{ - if (enable) - { - base->AS_CTRL |= PXP_AS_CTRL_ENABLE_COLORKEY_MASK; - } - { - base->AS_CTRL &= ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK; - } -} - -/*! - * @brief Set the alpha surface position in output buffer. - * - * @param base PXP peripheral base address. - * @param upperLeftX X of the upper left corner. - * @param upperLeftY Y of the upper left corner. - * @param lowerRightX X of the lower right corner. - * @param lowerRightY Y of the lower right corner. - */ -void PXP_SetAlphaSurfacePosition( - PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY); -/* @} */ - -/*! - * @name Process surface - * @{ - */ - -/*! - * @brief Set the back ground color of PS. - * - * @param base PXP peripheral base address. - * @param backGroundColor Pixel value of the background color. - */ -static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint32_t backGroundColor) -{ -#if defined(PXP_PS_BACKGROUND_0_COLOR_MASK) - base->PS_BACKGROUND_0 = backGroundColor; -#else - base->PS_BACKGROUND = backGroundColor; -#endif -} - -/*! - * @brief Set the process surface input buffer configuration. - * - * @param base PXP peripheral base address. - * @param config Pointer to the configuration. - */ -void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config); - -/*! - * @brief Set the process surface scaler configuration. - * - * The valid down scale fact is 1/(2^12) ~ 16. - * - * @param base PXP peripheral base address. - * @param inputWidth Input image width. - * @param inputHeight Input image height. - * @param outputWidth Output image width. - * @param outputHeight Output image height. - */ -void PXP_SetProcessSurfaceScaler( - PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight); - -/*! - * @brief Set the process surface position in output buffer. - * - * @param base PXP peripheral base address. - * @param upperLeftX X of the upper left corner. - * @param upperLeftY Y of the upper left corner. - * @param lowerRightX X of the lower right corner. - * @param lowerRightY Y of the lower right corner. - */ -void PXP_SetProcessSurfacePosition( - PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY); - -/*! - * @brief Set the process surface color key. - * - * If the PS image matches colorkey range, the PS background color is output. Set - * @p colorKeyLow to 0xFFFFFFFF and @p colorKeyHigh to 0 will disable the colorkeying. - * - * @param base PXP peripheral base address. - * @param colorKeyLow Color key low range. - * @param colorKeyHigh Color key high range. - */ -void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh); -/* @} */ - -/*! - * @name Output buffer - * @{ - */ - -/*! - * @brief Set the PXP outpt buffer configuration. - * - * @param base PXP peripheral base address. - * @param config Pointer to the configuration. - */ -void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config); - -/*! - * @brief Set the global overwritten alpha value. - * - * If global overwritten alpha is enabled, the alpha component in output buffer pixels - * will be overwritten, otherwise the computed alpha value is used. - * - * @param base PXP peripheral base address. - * @param alpha The alpha value. - */ -static inline void PXP_SetOverwrittenAlphaValue(PXP_Type *base, uint8_t alpha) -{ - base->OUT_CTRL = (base->OUT_CTRL & ~PXP_OUT_CTRL_ALPHA_MASK) | PXP_OUT_CTRL_ALPHA(alpha); -} - -/*! - * @brief Enable or disable the global overwritten alpha value. - * - * If global overwritten alpha is enabled, the alpha component in output buffer pixels - * will be overwritten, otherwise the computed alpha value is used. - * - * @param base PXP peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void PXP_EnableOverWrittenAlpha(PXP_Type *base, bool enable) -{ - if (enable) - { - base->OUT_CTRL_SET = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK; - } - else - { - base->OUT_CTRL_CLR = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK; - } -} - -/*! - * @brief Set the rotation configuration. - * - * The PXP could rotate the process surface or the output buffer. There are - * two PXP versions: - * - Version 1: Only has one rotate sub module, the output buffer and process - * surface share the same rotate sub module, which means the process surface - * and output buffer could not be rotate at the same time. When pass in - * @ref kPXP_RotateOutputBuffer, the process surface could not use the rotate, - * Also when pass in @ref kPXP_RotateProcessSurface, output buffer could not - * use the rotate. - * - Version 2: Has two seperate rotate sub modules, the output buffer and - * process surface could configure the rotation independently. - * - * Upper layer could use the macro PXP_SHARE_ROTATE to check which version is. - * PXP_SHARE_ROTATE=1 means version 1. - * - * @param base PXP peripheral base address. - * @param position Rotate process surface or output buffer. - * @param degree Rotate degree. - * @param flipMode Flip mode. - * - * @note This function is different depends on the macro PXP_SHARE_ROTATE. - */ -static inline void PXP_SetRotateConfig(PXP_Type *base, - pxp_rotate_position_t position, - pxp_rotate_degree_t degree, - pxp_flip_mode_t flipMode) -{ -#if PXP_SHARE_ROTATE - base->CTRL = - (base->CTRL & ~(PXP_CTRL_ROTATE_MASK | PXP_CTRL_ROT_POS_MASK | PXP_CTRL_VFLIP_MASK | PXP_CTRL_HFLIP_MASK)) | - PXP_CTRL_ROTATE(degree) | PXP_CTRL_ROT_POS(position) | ((uint32_t)flipMode << PXP_CTRL_HFLIP_SHIFT); -#else - uint32_t ctrl = base->CTRL; - - if (kPXP_RotateOutputBuffer == position) - { - ctrl &= ~(PXP_CTRL_HFLIP0_MASK | PXP_CTRL_VFLIP0_MASK | PXP_CTRL_ROTATE0_MASK); - ctrl |= (PXP_CTRL_ROTATE0(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP0_SHIFT)); - } - else - { - ctrl &= ~(PXP_CTRL_HFLIP1_MASK | PXP_CTRL_VFLIP1_MASK | PXP_CTRL_ROTATE1_MASK); - ctrl |= (PXP_CTRL_ROTATE1(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP1_SHIFT)); - } - - base->CTRL = ctrl; -#endif -} -/* @} */ - -/*! - * @name Command queue - * @{ - */ - -/*! - * @brief Set the next command. - * - * The PXP supports a primitive ability to queue up one operation while the current - * operation is running. Workflow: - * - * 1. Prepare the PXP register values except STAT, CSCCOEFn, NEXT in the memory - * in the order they appear in the register map. - * 2. Call this function sets the new operation to PXP. - * 3. There are two methods to check whether the PXP has loaded the new operation. - * The first method is using @ref PXP_IsNextCommandPending. If there is new operation - * not loaded by the PXP, this function returns true. The second method is checking - * the flag @ref kPXP_CommandLoadFlag, if command loaded, this flag asserts. User - * could enable interrupt @ref kPXP_CommandLoadInterruptEnable to get the loaded - * signal in interrupt way. - * 4. When command loaded by PXP, a new command could be set using this function. - * - * @code - uint32_t pxp_command1[48]; - uint32_t pxp_command2[48]; - - // Prepare the register values. - pxp_command1[0] = ...; - pxp_command1[1] = ...; - // ... - pxp_command2[0] = ...; - pxp_command2[1] = ...; - // ... - - // Make sure no new command pending. - while (PXP_IsNextCommandPending(PXP)) - { - } - - // Set new operation. - PXP_SetNextCommand(PXP, pxp_command1); - - // Wait for new command loaded. Here could check @ref kPXP_CommandLoadFlag too. - while (PXP_IsNextCommandPending(PXP)) - { - } - - PXP_SetNextCommand(PXP, pxp_command2); - @endcode - * - * @param base PXP peripheral base address. - * @param commandAddr Address of the new command. - */ -static inline void PXP_SetNextCommand(PXP_Type *base, void *commandAddr) -{ - /* Make sure commands have been saved to memory. */ - __DSB(); - - base->NEXT = (uint32_t)commandAddr & PXP_NEXT_POINTER_MASK; -} - -/*! - * @brief Check whether the next command is pending. - * - * @param base UART peripheral base address. - * @return True is pending, false is not. - */ -static inline bool PXP_IsNextCommandPending(PXP_Type *base) -{ - return (bool)(base->NEXT & PXP_NEXT_ENABLED_MASK); -} - -/*! - * @brief Cancel command set by @ref PXP_SetNextCommand - * - * @param base UART peripheral base address. - */ -static inline void PXP_CancelNextCommand(PXP_Type *base) -{ - /* Write PXP_NEXT_ENABLED_MASK to the register NEXT_CLR to canel the command. */ - *((volatile uint32_t *)(&(base->NEXT)) + 2U) = PXP_NEXT_ENABLED_MASK; -} - -/* @} */ - -/*! - * @name Color space conversion - * @{ - */ - -#if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2) -/*! - * @brief Set the CSC2 configuration. - * - * The CSC2 module receives pixels in any color space and can convert the pixels - * into any of RGB, YUV, or YCbCr color spaces. The output pixels are passed - * onto the LUT and rotation engine for further processing - * - * @param base PXP peripheral base address. - * @param config Pointer to the configuration. - */ -void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config); - -/*! - * @brief Enable or disable the CSC2. - * - * @param base PXP peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void PXP_EnableCsc2(PXP_Type *base, bool enable) -{ - if (enable) - { - base->CSC2_CTRL &= ~PXP_CSC2_CTRL_BYPASS_MASK; - } - else - { - base->CSC2_CTRL |= PXP_CSC2_CTRL_BYPASS_MASK; - } -} -#endif /* FSL_FEATURE_PXP_HAS_NO_CSC2 */ - -/*! - * @brief Set the CSC1 mode. - * - * The CSC1 module receives scaled YUV/YCbCr444 pixels from the scale engine and - * converts the pixels to the RGB888 color space. It could only be used by process - * surface. - * - * @param base PXP peripheral base address. - * @param mode The conversion mode. - */ -void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode); - -/*! - * @brief Enable or disable the CSC1. - * - * @param base PXP peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void PXP_EnableCsc1(PXP_Type *base, bool enable) -{ - if (enable) - { - base->CSC1_COEF0 &= ~PXP_CSC1_COEF0_BYPASS_MASK; - } - else - { - base->CSC1_COEF0 |= PXP_CSC1_COEF0_BYPASS_MASK; - } -} -/* @} */ - -#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) -/*! - * @name LUT operations - * @{ - */ - -/*! - * @brief Set the LUT configuration. - * - * The lookup table (LUT) is used to modify pixels in a manner that is not linear - * and that cannot be achieved by the color space conversion modules. To setup - * the LUT, the complete workflow is: - * 1. Use @ref PXP_SetLutConfig to set the configuration, such as the lookup mode. - * 2. Use @ref PXP_LoadLutTable to load the lookup table to PXP. - * 3. Use @ref PXP_EnableLut to enable the function. - * - * @param base PXP peripheral base address. - * @param config Pointer to the configuration. - */ -void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config); - -/*! - * @brief Set the look up table to PXP. - * - * If lookup mode is DIRECT mode, this function loads @p bytesNum of values - * from the address @p memAddr into PXP LUT address @p lutStartAddr. So this - * function allows only update part of the PXP LUT. - * - * If lookup mode is CACHE mode, this function sets the new address to @p memAddr - * and invalid the PXP LUT cache. - * - * @param base PXP peripheral base address. - * @param lookupMode Which lookup mode is used. Note that this parameter is only - * used to distinguish DIRECT mode and CACHE mode, it does not change the register - * value PXP_LUT_CTRL[LOOKUP_MODE]. To change that value, use function @ref PXP_SetLutConfig. - * @param bytesNum How many bytes to set. This value must be divisable by 8. - * @param memAddr Address of look up table to set. - * @param lutStartAddr The LUT value will be loaded to LUT from index lutAddr. It should - * be 8 bytes aligned. - * - * @retval kStatus_Success Load successfully. - * @retval kStatus_InvalidArgument Failed because of invalid argument. - */ -status_t PXP_LoadLutTable( - PXP_Type *base, pxp_lut_lookup_mode_t lookupMode, uint32_t bytesNum, uint32_t memAddr, uint16_t lutStartAddr); - -/*! - * @brief Enable or disable the LUT. - * - * @param base PXP peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void PXP_EnableLut(PXP_Type *base, bool enable) -{ - if (enable) - { - base->LUT_CTRL &= ~PXP_LUT_CTRL_BYPASS_MASK; - } - else - { - base->LUT_CTRL |= PXP_LUT_CTRL_BYPASS_MASK; - } -} - -/*! - * @brief Select the 8kB LUT bank in DIRECT_RGB444 mode. - * - * @param base PXP peripheral base address. - * @param bank The bank to select. - */ -static inline void PXP_Select8kLutBank(PXP_Type *base, pxp_lut_8k_bank_t bank) -{ - base->LUT_CTRL = (base->LUT_CTRL & ~PXP_LUT_CTRL_SEL_8KB_MASK) | PXP_LUT_CTRL_SEL_8KB(bank); -} -/* @} */ -#endif /* FSL_FEATURE_PXP_HAS_NO_LUT */ - -#if (defined(FSL_FEATURE_PXP_HAS_DITHER) && FSL_FEATURE_PXP_HAS_DITHER) -/*! - * @name Dither - * @{ - */ - -/*! - * @brief Write data to the PXP internal memory. - * - * @param base PXP peripheral base address. - * @param ram Which internal memory to write. - * @param bytesNum How many bytes to write. - * @param data Pointer to the data to write. - * @param memStartAddr The start address in the internal memory to write the data. - */ -void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr); - -/*! - * @brief Set the dither final LUT data. - * - * The dither final LUT is only applicble to dither engine 0. It takes the bits[7:4] - * of the output pixel and looks up and 8 bit value from the 16 value LUT to generate - * the final output pixel to the next process module. - * - * @param base PXP peripheral base address. - * @param data Pointer to the LUT data to set. - */ -void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data); - -/*! - * @brief Set the configuration for the dither block. - * - * If the pre-dither LUT, post-dither LUT or ordered dither is used, please call - * @ref PXP_SetInternalRamData to set the LUT data to internal memory. - * - * If the final LUT is used, please call @ref PXP_SetDitherFinalLutData to set - * the LUT data. - * - * @param base PXP peripheral base address. - * @param config Pointer to the configuration. - * - * @note When using ordered dithering, please set the PXP process block size same - * with the ordered dithering matrix size using function @ref PXP_SetProcessBlockSize. - */ -static inline void PXP_SetDitherConfig(PXP_Type *base, const pxp_dither_config_t *config) -{ - base->DITHER_CTRL = *((const uint32_t *)config) & 0x00FFFFFFU; -} - -/*! - * @brief Enable or disable dither engine in the PXP process path. - * - * After the initialize function @ref PXP_Init, the dither engine is disabled and not - * use in the PXP processing path. This function enables the dither engine and - * routes the dither engine output to the output buffer. When the dither engine - * is enabled using this function, @ref PXP_SetDitherConfig must be called to - * configure dither engine correctly, otherwise there is not output to the output - * buffer. - * - * @param base PXP peripheral base address. - * @param enable Pass in true to enable, false to disable. - */ -void PXP_EnableDither(PXP_Type *base, bool enable); - -/* @} */ - -#endif /* FSL_FEATURE_PXP_HAS_DITHER */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PXP_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_qtmr.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_qtmr.c deleted file mode 100644 index 8373fa0359..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_qtmr.c +++ /dev/null @@ -1,477 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_qtmr.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.qtmr" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address to be used to gate or ungate the module clock - * - * @param base Quad Timer peripheral base address - * - * @return The Quad Timer instance - */ -static uint32_t QTMR_GetInstance(TMR_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to Quad Timer bases for each instance. */ -static TMR_Type *const s_qtmrBases[] = TMR_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to Quad Timer clocks for each instance. */ -static const clock_ip_name_t s_qtmrClocks[] = TMR_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t QTMR_GetInstance(TMR_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_qtmrBases); instance++) - { - if (s_qtmrBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_qtmrBases)); - - return instance; -} - -void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the module clock */ - CLOCK_EnableClock(s_qtmrClocks[QTMR_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Setup the counter sources */ - base->CHANNEL[channel].CTRL = (TMR_CTRL_PCS(config->primarySource) | TMR_CTRL_SCS(config->secondarySource)); - - /* Setup the master mode operation */ - base->CHANNEL[channel].SCTRL = (TMR_SCTRL_EEOF(config->enableExternalForce) | TMR_SCTRL_MSTR(config->enableMasterMode)); - - /* Setup debug mode */ - base->CHANNEL[channel].CSCTRL = TMR_CSCTRL_DBG_EN(config->debugMode); - - base->CHANNEL[channel].FILT &= ~( TMR_FILT_FILT_CNT_MASK | TMR_FILT_FILT_PER_MASK); - /* Setup input filter */ - base->CHANNEL[channel].FILT = (TMR_FILT_FILT_CNT(config->faultFilterCount) | TMR_FILT_FILT_PER(config->faultFilterPeriod)); -} - -void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel) -{ - /* Stop the counter */ - base->CHANNEL[channel].CTRL &= ~TMR_CTRL_CM_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the module clock */ - CLOCK_DisableClock(s_qtmrClocks[QTMR_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void QTMR_GetDefaultConfig(qtmr_config_t *config) -{ - assert(config); - - /* Halt counter during debug mode */ - config->debugMode = kQTMR_RunNormalInDebug; - /* Another counter cannot force state of OFLAG signal */ - config->enableExternalForce = false; - /* Compare function's output from this counter is not broadcast to other counters */ - config->enableMasterMode = false; - /* Fault filter count is set to 0 */ - config->faultFilterCount = 0; - /* Fault filter period is set to 0 which disables the fault filter */ - config->faultFilterPeriod = 0; - /* Primary count source is IP bus clock divide by 2 */ - config->primarySource = kQTMR_ClockDivide_2; - /* Secondary count source is counter 0 input pin */ - config->secondarySource = kQTMR_Counter0InputPin; -} - -status_t QTMR_SetupPwm( - TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz) -{ - uint32_t periodCount, highCount, lowCount, reg; - - if (dutyCyclePercent > 100) - { - /* Invalid dutycycle */ - return kStatus_Fail; - } - - /* Set OFLAG pin for output mode and force out a low on the pin */ - base->CHANNEL[channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK); - - /* Counter values to generate a PWM signal */ - periodCount = (srcClock_Hz / pwmFreqHz); - highCount = (periodCount * dutyCyclePercent) / 100; - lowCount = periodCount - highCount; - - /* Setup the compare registers for PWM output */ - base->CHANNEL[channel].COMP1 = lowCount; - base->CHANNEL[channel].COMP2 = highCount; - - /* Setup the pre-load registers for PWM output */ - base->CHANNEL[channel].CMPLD1 = lowCount; - base->CHANNEL[channel].CMPLD2 = highCount; - - reg = base->CHANNEL[channel].CSCTRL; - /* Setup the compare load control for COMP1 and COMP2. - * Load COMP1 when CSCTRL[TCF2] is asserted, load COMP2 when CSCTRL[TCF1] is asserted - */ - reg &= ~(TMR_CSCTRL_CL1_MASK | TMR_CSCTRL_CL2_MASK); - reg |= (TMR_CSCTRL_CL1(kQTMR_LoadOnComp2) | TMR_CSCTRL_CL2(kQTMR_LoadOnComp1)); - base->CHANNEL[channel].CSCTRL = reg; - - if (outputPolarity) - { - /* Invert the polarity */ - base->CHANNEL[channel].SCTRL |= TMR_SCTRL_OPS_MASK; - } - else - { - /* True polarity, no inversion */ - base->CHANNEL[channel].SCTRL &= ~TMR_SCTRL_OPS_MASK; - } - - reg = base->CHANNEL[channel].CTRL; - reg &= ~(TMR_CTRL_OUTMODE_MASK); - /* Count until compare value is reached and re-initialize the counter, toggle OFLAG output - * using alternating compare register - */ - reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ToggleOnAltCompareReg)); - base->CHANNEL[channel].CTRL = reg; - - return kStatus_Success; -} - -void QTMR_SetupInputCapture(TMR_Type *base, - qtmr_channel_selection_t channel, - qtmr_input_source_t capturePin, - bool inputPolarity, - bool reloadOnCapture, - qtmr_input_capture_edge_t captureMode) -{ - uint16_t reg; - - /* Clear the prior value for the input source for capture */ - reg = base->CHANNEL[channel].CTRL & (~TMR_CTRL_SCS_MASK); - - /* Set the new input source */ - reg |= TMR_CTRL_SCS(capturePin); - base->CHANNEL[channel].CTRL = reg; - - /* Clear the prior values for input polarity, capture mode. Set the external pin as input */ - reg = base->CHANNEL[channel].SCTRL & (~(TMR_SCTRL_IPS_MASK | TMR_SCTRL_CAPTURE_MODE_MASK | TMR_SCTRL_OEN_MASK)); - /* Set the new values */ - reg |= (TMR_SCTRL_IPS(inputPolarity) | TMR_SCTRL_CAPTURE_MODE(captureMode)); - base->CHANNEL[channel].SCTRL = reg; - - /* Setup if counter should reload when a capture occurs */ - if (reloadOnCapture) - { - base->CHANNEL[channel].CSCTRL |= TMR_CSCTRL_ROC_MASK; - } - else - { - base->CHANNEL[channel].CSCTRL &= ~TMR_CSCTRL_ROC_MASK; - } -} - -void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) -{ - uint16_t reg; - - reg = base->CHANNEL[channel].SCTRL; - /* Compare interrupt */ - if (mask & kQTMR_CompareInterruptEnable) - { - reg |= TMR_SCTRL_TCFIE_MASK; - } - /* Overflow interrupt */ - if (mask & kQTMR_OverflowInterruptEnable) - { - reg |= TMR_SCTRL_TOFIE_MASK; - } - /* Input edge interrupt */ - if (mask & kQTMR_EdgeInterruptEnable) - { - /* Restriction: Do not set both SCTRL[IEFIE] and DMA[IEFDE] */ - base->CHANNEL[channel].DMA &= ~TMR_DMA_IEFDE_MASK; - reg |= TMR_SCTRL_IEFIE_MASK; - } - base->CHANNEL[channel].SCTRL = reg; - - reg = base->CHANNEL[channel].CSCTRL; - /* Compare 1 interrupt */ - if (mask & kQTMR_Compare1InterruptEnable) - { - reg |= TMR_CSCTRL_TCF1EN_MASK; - } - /* Compare 2 interrupt */ - if (mask & kQTMR_Compare2InterruptEnable) - { - reg |= TMR_CSCTRL_TCF2EN_MASK; - } - base->CHANNEL[channel].CSCTRL = reg; -} - -void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) -{ - uint16_t reg; - - reg = base->CHANNEL[channel].SCTRL; - /* Compare interrupt */ - if (mask & kQTMR_CompareInterruptEnable) - { - reg &= ~TMR_SCTRL_TCFIE_MASK; - } - /* Overflow interrupt */ - if (mask & kQTMR_OverflowInterruptEnable) - { - reg &= ~TMR_SCTRL_TOFIE_MASK; - } - /* Input edge interrupt */ - if (mask & kQTMR_EdgeInterruptEnable) - { - reg &= ~TMR_SCTRL_IEFIE_MASK; - } - base->CHANNEL[channel].SCTRL = reg; - - reg = base->CHANNEL[channel].CSCTRL; - /* Compare 1 interrupt */ - if (mask & kQTMR_Compare1InterruptEnable) - { - reg &= ~TMR_CSCTRL_TCF1EN_MASK; - } - /* Compare 2 interrupt */ - if (mask & kQTMR_Compare2InterruptEnable) - { - reg &= ~TMR_CSCTRL_TCF2EN_MASK; - } - base->CHANNEL[channel].CSCTRL = reg; -} - -uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel) -{ - uint32_t enabledInterrupts = 0; - uint16_t reg; - - reg = base->CHANNEL[channel].SCTRL; - /* Compare interrupt */ - if (reg & TMR_SCTRL_TCFIE_MASK) - { - enabledInterrupts |= kQTMR_CompareFlag; - } - /* Overflow interrupt */ - if (reg & TMR_SCTRL_TOFIE_MASK) - { - enabledInterrupts |= kQTMR_OverflowInterruptEnable; - } - /* Input edge interrupt */ - if (reg & TMR_SCTRL_IEFIE_MASK) - { - enabledInterrupts |= kQTMR_EdgeInterruptEnable; - } - - reg = base->CHANNEL[channel].CSCTRL; - /* Compare 1 interrupt */ - if (reg & TMR_CSCTRL_TCF1EN_MASK) - { - enabledInterrupts |= kQTMR_Compare1InterruptEnable; - } - /* Compare 2 interrupt */ - if (reg & TMR_CSCTRL_TCF2EN_MASK) - { - enabledInterrupts |= kQTMR_Compare2InterruptEnable; - } - - return enabledInterrupts; -} - -uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel) -{ - uint32_t statusFlags = 0; - uint16_t reg; - - reg = base->CHANNEL[channel].SCTRL; - /* Timer compare flag */ - if (reg & TMR_SCTRL_TCF_MASK) - { - statusFlags |= kQTMR_CompareFlag; - } - /* Timer overflow flag */ - if (reg & TMR_SCTRL_TOF_MASK) - { - statusFlags |= kQTMR_OverflowFlag; - } - /* Input edge flag */ - if (reg & TMR_SCTRL_IEF_MASK) - { - statusFlags |= kQTMR_EdgeFlag; - } - - reg = base->CHANNEL[channel].CSCTRL; - /* Compare 1 flag */ - if (reg & TMR_CSCTRL_TCF1_MASK) - { - statusFlags |= kQTMR_Compare1Flag; - } - /* Compare 2 flag */ - if (reg & TMR_CSCTRL_TCF2_MASK) - { - statusFlags |= kQTMR_Compare2Flag; - } - - return statusFlags; -} - -void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) -{ - uint16_t reg; - - reg = base->CHANNEL[channel].SCTRL; - /* Timer compare flag */ - if (mask & kQTMR_CompareFlag) - { - reg &= ~TMR_SCTRL_TCF_MASK; - } - /* Timer overflow flag */ - if (mask & kQTMR_OverflowFlag) - { - reg &= ~TMR_SCTRL_TOF_MASK; - } - /* Input edge flag */ - if (mask & kQTMR_EdgeFlag) - { - reg &= ~TMR_SCTRL_IEF_MASK; - } - base->CHANNEL[channel].SCTRL = reg; - - reg = base->CHANNEL[channel].CSCTRL; - /* Compare 1 flag */ - if (mask & kQTMR_Compare1Flag) - { - reg &= ~TMR_CSCTRL_TCF1_MASK; - } - /* Compare 2 flag */ - if (mask & kQTMR_Compare2Flag) - { - reg &= ~TMR_CSCTRL_TCF2_MASK; - } - base->CHANNEL[channel].CSCTRL = reg; -} - -void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks) -{ - /* Set the length bit to reinitialize the counters on a match */ - base->CHANNEL[channel].CTRL |= TMR_CTRL_LENGTH_MASK; - - if (base->CHANNEL[channel].CTRL & TMR_CTRL_DIR_MASK) - { - /* Counting down */ - base->CHANNEL[channel].COMP2 = ticks; - } - else - { - /* Counting up */ - base->CHANNEL[channel].COMP1 = ticks; - } -} - -void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) -{ - uint16_t reg; - - reg = base->CHANNEL[channel].DMA; - /* Input Edge Flag DMA Enable */ - if (mask & kQTMR_InputEdgeFlagDmaEnable) - { - /* Restriction: Do not set both DMA[IEFDE] and SCTRL[IEFIE] */ - base->CHANNEL[channel].SCTRL &= ~TMR_SCTRL_IEFIE_MASK; - reg |= TMR_DMA_IEFDE_MASK; - } - /* Comparator Preload Register 1 DMA Enable */ - if (mask & kQTMR_ComparatorPreload1DmaEnable) - { - reg |= TMR_DMA_CMPLD1DE_MASK; - } - /* Comparator Preload Register 2 DMA Enable */ - if (mask & kQTMR_ComparatorPreload2DmaEnable) - { - reg |= TMR_DMA_CMPLD2DE_MASK; - } - base->CHANNEL[channel].DMA = reg; -} - -void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) -{ - uint16_t reg; - - reg = base->CHANNEL[channel].DMA; - /* Input Edge Flag DMA Enable */ - if (mask & kQTMR_InputEdgeFlagDmaEnable) - { - reg &= ~TMR_DMA_IEFDE_MASK; - } - /* Comparator Preload Register 1 DMA Enable */ - if (mask & kQTMR_ComparatorPreload1DmaEnable) - { - reg &= ~TMR_DMA_CMPLD1DE_MASK; - } - /* Comparator Preload Register 2 DMA Enable */ - if (mask & kQTMR_ComparatorPreload2DmaEnable) - { - reg &= ~TMR_DMA_CMPLD2DE_MASK; - } - base->CHANNEL[channel].DMA = reg; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_qtmr.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_qtmr.h deleted file mode 100644 index ee23b4cca8..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_qtmr.h +++ /dev/null @@ -1,461 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_QTMR_H_ -#define _FSL_QTMR_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup qtmr - * @{ - */ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_QTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief Quad Timer primary clock source selection*/ -typedef enum _qtmr_primary_count_source -{ - kQTMR_ClockCounter0InputPin = 0, /*!< Use counter 0 input pin */ - kQTMR_ClockCounter1InputPin, /*!< Use counter 1 input pin */ - kQTMR_ClockCounter2InputPin, /*!< Use counter 2 input pin */ - kQTMR_ClockCounter3InputPin, /*!< Use counter 3 input pin */ - kQTMR_ClockCounter0Output, /*!< Use counter 0 output */ - kQTMR_ClockCounter1Output, /*!< Use counter 1 output */ - kQTMR_ClockCounter2Output, /*!< Use counter 2 output */ - kQTMR_ClockCounter3Output, /*!< Use counter 3 output */ - kQTMR_ClockDivide_1, /*!< IP bus clock divide by 1 prescaler */ - kQTMR_ClockDivide_2, /*!< IP bus clock divide by 2 prescaler */ - kQTMR_ClockDivide_4, /*!< IP bus clock divide by 4 prescaler */ - kQTMR_ClockDivide_8, /*!< IP bus clock divide by 8 prescaler */ - kQTMR_ClockDivide_16, /*!< IP bus clock divide by 16 prescaler */ - kQTMR_ClockDivide_32, /*!< IP bus clock divide by 32 prescaler */ - kQTMR_ClockDivide_64, /*!< IP bus clock divide by 64 prescaler */ - kQTMR_ClockDivide_128 /*!< IP bus clock divide by 128 prescaler */ -} qtmr_primary_count_source_t; - -/*! @brief Quad Timer input sources selection*/ -typedef enum _qtmr_input_source -{ - kQTMR_Counter0InputPin = 0, /*!< Use counter 0 input pin */ - kQTMR_Counter1InputPin, /*!< Use counter 1 input pin */ - kQTMR_Counter2InputPin, /*!< Use counter 2 input pin */ - kQTMR_Counter3InputPin /*!< Use counter 3 input pin */ -} qtmr_input_source_t; - -/*! @brief Quad Timer counting mode selection */ -typedef enum _qtmr_counting_mode -{ - kQTMR_NoOperation = 0, /*!< No operation */ - kQTMR_PriSrcRiseEdge, /*!< Count rising edges or primary source */ - kQTMR_PriSrcRiseAndFallEdge, /*!< Count rising and falling edges of primary source */ - kQTMR_PriSrcRiseEdgeSecInpHigh, /*!< Count rise edges of pri SRC while sec inp high active */ - kQTMR_QuadCountMode, /*!< Quadrature count mode, uses pri and sec sources */ - kQTMR_PriSrcRiseEdgeSecDir, /*!< Count rising edges of pri SRC; sec SRC specifies dir */ - kQTMR_SecSrcTrigPriCnt, /*!< Edge of sec SRC trigger primary count until compare*/ - kQTMR_CascadeCount /*!< Cascaded count mode (up/down) */ -} qtmr_counting_mode_t; - -/*! @brief Quad Timer output mode selection*/ -typedef enum _qtmr_output_mode -{ - kQTMR_AssertWhenCountActive = 0, /*!< Assert OFLAG while counter is active*/ - kQTMR_ClearOnCompare, /*!< Clear OFLAG on successful compare */ - kQTMR_SetOnCompare, /*!< Set OFLAG on successful compare */ - kQTMR_ToggleOnCompare, /*!< Toggle OFLAG on successful compare */ - kQTMR_ToggleOnAltCompareReg, /*!< Toggle OFLAG using alternating compare registers */ - kQTMR_SetOnCompareClearOnSecSrcInp, /*!< Set OFLAG on compare, clear on sec SRC input edge */ - kQTMR_SetOnCompareClearOnCountRoll, /*!< Set OFLAG on compare, clear on counter rollover */ - kQTMR_EnableGateClock /*!< Enable gated clock output while count is active */ -} qtmr_output_mode_t; - -/*! @brief Quad Timer input capture edge mode, rising edge, or falling edge */ -typedef enum _qtmr_input_capture_edge -{ - kQTMR_NoCapture = 0, /*!< Capture is disabled */ - kQTMR_RisingEdge, /*!< Capture on rising edge (IPS=0) or falling edge (IPS=1)*/ - kQTMR_FallingEdge, /*!< Capture on falling edge (IPS=0) or rising edge (IPS=1)*/ - kQTMR_RisingAndFallingEdge /*!< Capture on both edges */ -} qtmr_input_capture_edge_t; - -/*! @brief Quad Timer input capture edge mode, rising edge, or falling edge */ -typedef enum _qtmr_preload_control -{ - kQTMR_NoPreload = 0, /*!< Never preload */ - kQTMR_LoadOnComp1, /*!< Load upon successful compare with value in COMP1 */ - kQTMR_LoadOnComp2 /*!< Load upon successful compare with value in COMP2*/ -} qtmr_preload_control_t; - -/*! @brief List of Quad Timer run options when in Debug mode */ -typedef enum _qtmr_debug_action -{ - kQTMR_RunNormalInDebug = 0U, /*!< Continue with normal operation */ - kQTMR_HaltCounter, /*!< Halt counter */ - kQTMR_ForceOutToZero, /*!< Force output to logic 0 */ - kQTMR_HaltCountForceOutZero /*!< Halt counter and force output to logic 0 */ -} qtmr_debug_action_t; - -/*! @brief List of Quad Timer interrupts */ -typedef enum _qtmr_interrupt_enable -{ - kQTMR_CompareInterruptEnable = (1U << 0), /*!< Compare interrupt.*/ - kQTMR_Compare1InterruptEnable = (1U << 1), /*!< Compare 1 interrupt.*/ - kQTMR_Compare2InterruptEnable = (1U << 2), /*!< Compare 2 interrupt.*/ - kQTMR_OverflowInterruptEnable = (1U << 3), /*!< Timer overflow interrupt.*/ - kQTMR_EdgeInterruptEnable = (1U << 4) /*!< Input edge interrupt.*/ -} qtmr_interrupt_enable_t; - -/*! @brief List of Quad Timer flags */ -typedef enum _qtmr_status_flags -{ - kQTMR_CompareFlag = (1U << 0), /*!< Compare flag */ - kQTMR_Compare1Flag = (1U << 1), /*!< Compare 1 flag */ - kQTMR_Compare2Flag = (1U << 2), /*!< Compare 2 flag */ - kQTMR_OverflowFlag = (1U << 3), /*!< Timer overflow flag */ - kQTMR_EdgeFlag = (1U << 4) /*!< Input edge flag */ -} qtmr_status_flags_t; - -/*! @brief List of channel selection */ -typedef enum _qtmr_channel_selection -{ - kQTMR_Channel_0 = 0U, /*!< TMR Channel 0 */ - kQTMR_Channel_1, /*!< TMR Channel 1 */ - kQTMR_Channel_2, /*!< TMR Channel 2 */ - kQTMR_Channel_3, /*!< TMR Channel 3 */ -} qtmr_channel_selection_t; - -/*! @brief List of Quad Timer DMA enable */ -typedef enum _qtmr_dma_enable -{ - kQTMR_InputEdgeFlagDmaEnable = (1U << 0), /*!< Input Edge Flag DMA Enable.*/ - kQTMR_ComparatorPreload1DmaEnable = (1U << 1), /*!< Comparator Preload Register 1 DMA Enable.*/ - kQTMR_ComparatorPreload2DmaEnable = (1U << 2), /*!< Comparator Preload Register 2 DMA Enable.*/ -} qtmr_dma_enable_t; - -/*! - * @brief Quad Timer config structure - * - * This structure holds the configuration settings for the Quad Timer peripheral. To initialize this - * structure to reasonable defaults, call the QTMR_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _qtmr_config -{ - qtmr_primary_count_source_t primarySource; /*!< Specify the primary count source */ - qtmr_input_source_t secondarySource; /*!< Specify the secondary count source */ - bool enableMasterMode; /*!< true: Broadcast compare function output to other counters; - false no broadcast */ - bool enableExternalForce; /*!< true: Compare from another counter force state of OFLAG signal - false: OFLAG controlled by local counter */ - uint8_t faultFilterCount; /*!< Fault filter count */ - uint8_t faultFilterPeriod; /*!< Fault filter period;value of 0 will bypass the filter */ - qtmr_debug_action_t debugMode; /*!< Operation in Debug mode */ -} qtmr_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the Quad Timer clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the Quad Timer driver. - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - * @param config Pointer to user's Quad Timer config structure - */ -void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config); - -/*! - * @brief Stops the counter and gates the Quad Timer clock - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - */ -void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel); - -/*! - * @brief Fill in the Quad Timer config struct with the default settings - * - * The default values are: - * @code - * config->debugMode = kQTMR_RunNormalInDebug; - * config->enableExternalForce = false; - * config->enableMasterMode = false; - * config->faultFilterCount = 0; - * config->faultFilterPeriod = 0; - * config->primarySource = kQTMR_ClockDivide_2; - * config->secondarySource = kQTMR_Counter0InputPin; - * @endcode - * @param config Pointer to user's Quad Timer config structure. - */ -void QTMR_GetDefaultConfig(qtmr_config_t *config); - -/*! @}*/ - -/*! - * @brief Sets up Quad timer module for PWM signal output. - * - * The function initializes the timer module according to the parameters passed in by the user. The - * function also sets up the value compare registers to match the PWM signal requirements. - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - * @param pwmFreqHz PWM signal frequency in Hz - * @param dutyCyclePercent PWM pulse width, value should be between 0 to 100 - * 0=inactive signal(0% duty cycle)... - * 100=active signal (100% duty cycle) - * @param outputPolarity true: invert polarity of the output signal, false: no inversion - * @param srcClock_Hz Main counter clock in Hz. - * - * @return Returns an error if there was error setting up the signal. - */ -status_t QTMR_SetupPwm( - TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz); - -/*! - * @brief Allows the user to count the source clock cycles until a capture event arrives. - * - * The count is stored in the capture register. - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - * @param capturePin Pin through which we receive the input signal to trigger the capture - * @param inputPolarity true: invert polarity of the input signal, false: no inversion - * @param reloadOnCapture true: reload the counter when an input capture occurs, false: no reload - * @param captureMode Specifies which edge of the input signal triggers a capture - */ -void QTMR_SetupInputCapture(TMR_Type *base, - qtmr_channel_selection_t channel, - qtmr_input_source_t capturePin, - bool inputPolarity, - bool reloadOnCapture, - qtmr_input_capture_edge_t captureMode); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected Quad Timer interrupts - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::qtmr_interrupt_enable_t - */ -void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); - -/*! - * @brief Disables the selected Quad Timer interrupts - * - * @param base Quad Timer peripheral base addres - * @param channel Quad Timer channel number - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::qtmr_interrupt_enable_t - */ -void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); - -/*! - * @brief Gets the enabled Quad Timer interrupts - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::qtmr_interrupt_enable_t - */ -uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel); - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the Quad Timer status flags - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::qtmr_status_flags_t - */ -uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel); - -/*! - * @brief Clears the Quad Timer status flags. - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::qtmr_status_flags_t - */ -void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); - -/*! @}*/ - -/*! - * @name Read and Write the timer period - * @{ - */ - -/*! - * @brief Sets the timer period in ticks. - * - * Timers counts from initial value till it equals the count value set here. The counter - * will then reinitialize to the value specified in the Load register. - * - * @note - * 1. This function will write the time period in ticks to COMP1 or COMP2 register - * depending on the count direction - * 2. User can call the utility macros provided in fsl_common.h to convert to ticks - * 3. This function supports cases, providing only primary source clock without secondary source clock. - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - * @param ticks Timer period in units of ticks - */ -void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks); - -/*! - * @brief Reads the current timer counting value. - * - * This function returns the real-time timer counting value, in a range from 0 to a - * timer period. - * - * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - * - * @return Current counter value in ticks - */ -static inline uint16_t QTMR_GetCurrentTimerCount(TMR_Type *base, qtmr_channel_selection_t channel) -{ - return base->CHANNEL[channel].CNTR; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the Quad Timer counter. - * - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - * @param clockSource Quad Timer clock source - */ -static inline void QTMR_StartTimer(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_counting_mode_t clockSource) -{ - uint16_t reg = base->CHANNEL[channel].CTRL; - - reg &= ~(TMR_CTRL_CM_MASK); - reg |= TMR_CTRL_CM(clockSource); - base->CHANNEL[channel].CTRL = reg; -} - -/*! - * @brief Stops the Quad Timer counter. - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - */ -static inline void QTMR_StopTimer(TMR_Type *base, qtmr_channel_selection_t channel) -{ - base->CHANNEL[channel].CTRL &= ~TMR_CTRL_CM_MASK; -} - -/*! @}*/ - -/*! - * @name Enable and Disable the Quad Timer DMA - * @{ - */ - -/*! - * @brief Enable the Quad Timer DMA. - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - * @param mask The DMA to enable. This is a logical OR of members of the - * enumeration ::qtmr_dma_enable_t - */ -void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); - -/*! - * @brief Disable the Quad Timer DMA. - * - * @param base Quad Timer peripheral base address - * @param channel Quad Timer channel number - * @param mask The DMA to enable. This is a logical OR of members of the - * enumeration ::qtmr_dma_enable_t - */ -void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_QTMR_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_rtwdog.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_rtwdog.c deleted file mode 100644 index 54f2717a6f..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_rtwdog.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_rtwdog.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.rtwdog" -#endif - - -/******************************************************************************* - * Code - ******************************************************************************/ - -void RTWDOG_ClearStatusFlags(RTWDOG_Type *base, uint32_t mask) -{ - if (mask & kRTWDOG_InterruptFlag) - { - base->CS |= RTWDOG_CS_FLG_MASK; - } -} - -void RTWDOG_GetDefaultConfig(rtwdog_config_t *config) -{ - assert(config); - - config->enableRtwdog = true; - config->clockSource = kRTWDOG_ClockSource1; - config->prescaler = kRTWDOG_ClockPrescalerDivide1; - config->workMode.enableWait = true; - config->workMode.enableStop = false; - config->workMode.enableDebug = false; - config->testMode = kRTWDOG_TestModeDisabled; - config->enableUpdate = true; - config->enableInterrupt = false; - config->enableWindowMode = false; - config->windowValue = 0U; - config->timeoutValue = 0xFFFFU; -} - -void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config) -{ - assert(config); - - uint32_t value = 0U; - uint32_t primaskValue = 0U; - - value = RTWDOG_CS_EN(config->enableRtwdog) | RTWDOG_CS_CLK(config->clockSource) | RTWDOG_CS_INT(config->enableInterrupt) | - RTWDOG_CS_WIN(config->enableWindowMode) | RTWDOG_CS_UPDATE(config->enableUpdate) | - RTWDOG_CS_DBG(config->workMode.enableDebug) | RTWDOG_CS_STOP(config->workMode.enableStop) | - RTWDOG_CS_WAIT(config->workMode.enableWait) | RTWDOG_CS_PRES(config->prescaler) | RTWDOG_CS_CMD32EN(true) | - RTWDOG_CS_TST(config->testMode); - - /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence - * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ - primaskValue = DisableGlobalIRQ(); - RTWDOG_Unlock(base); - base->WIN = config->windowValue; - base->TOVAL = config->timeoutValue; - base->CS = value; - EnableGlobalIRQ(primaskValue); -} - -void RTWDOG_Deinit(RTWDOG_Type *base) -{ - uint32_t primaskValue = 0U; - - /* Disable the global interrupts */ - primaskValue = DisableGlobalIRQ(); - RTWDOG_Unlock(base); - RTWDOG_Disable(base); - EnableGlobalIRQ(primaskValue); -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_rtwdog.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_rtwdog.h deleted file mode 100644 index 76ba5b3b03..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_rtwdog.h +++ /dev/null @@ -1,404 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_RTWDOG_H_ -#define _FSL_RTWDOG_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup rtwdog - * @{ - */ - - -/******************************************************************************* - * Definitions - *******************************************************************************/ -/*! @name Unlock sequence */ -/*@{*/ -#define WDOG_FIRST_WORD_OF_UNLOCK (RTWDOG_UPDATE_KEY & 0xFFFFU) /*!< First word of unlock sequence */ -#define WDOG_SECOND_WORD_OF_UNLOCK ((RTWDOG_UPDATE_KEY >> 16U)& 0xFFFFU) /*!< Second word of unlock sequence */ -/*@}*/ - -/*! @name Refresh sequence */ -/*@{*/ -#define WDOG_FIRST_WORD_OF_REFRESH (RTWDOG_REFRESH_KEY & 0xFFFFU) /*!< First word of refresh sequence */ -#define WDOG_SECOND_WORD_OF_REFRESH ((RTWDOG_REFRESH_KEY >> 16U)& 0xFFFFU) /*!< Second word of refresh sequence */ -/*@}*/ -/*! @name Driver version */ -/*@{*/ -/*! @brief RTWDOG driver version 2.0.0. */ -#define FSL_RTWDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! @brief Describes RTWDOG clock source. */ -typedef enum _rtwdog_clock_source -{ - kRTWDOG_ClockSource0 = 0U, /*!< Clock source 0 */ - kRTWDOG_ClockSource1 = 1U, /*!< Clock source 1 */ - kRTWDOG_ClockSource2 = 2U, /*!< Clock source 2 */ - kRTWDOG_ClockSource3 = 3U, /*!< Clock source 3 */ -} rtwdog_clock_source_t; - -/*! @brief Describes the selection of the clock prescaler. */ -typedef enum _rtwdog_clock_prescaler -{ - kRTWDOG_ClockPrescalerDivide1 = 0x0U, /*!< Divided by 1 */ - kRTWDOG_ClockPrescalerDivide256 = 0x1U, /*!< Divided by 256 */ -} rtwdog_clock_prescaler_t; - -/*! @brief Defines RTWDOG work mode. */ -typedef struct _rtwdog_work_mode -{ - bool enableWait; /*!< Enables or disables RTWDOG in wait mode */ - bool enableStop; /*!< Enables or disables RTWDOG in stop mode */ - bool enableDebug; /*!< Enables or disables RTWDOG in debug mode */ -} rtwdog_work_mode_t; - -/*! @brief Describes RTWDOG test mode. */ -typedef enum _rtwdog_test_mode -{ - kRTWDOG_TestModeDisabled = 0U, /*!< Test Mode disabled */ - kRTWDOG_UserModeEnabled = 1U, /*!< User Mode enabled */ - kRTWDOG_LowByteTest = 2U, /*!< Test Mode enabled, only low byte is used */ - kRTWDOG_HighByteTest = 3U, /*!< Test Mode enabled, only high byte is used */ -} rtwdog_test_mode_t; - -/*! @brief Describes RTWDOG configuration structure. */ -typedef struct _rtwdog_config -{ - bool enableRtwdog; /*!< Enables or disables RTWDOG */ - rtwdog_clock_source_t clockSource; /*!< Clock source select */ - rtwdog_clock_prescaler_t prescaler; /*!< Clock prescaler value */ - rtwdog_work_mode_t workMode; /*!< Configures RTWDOG work mode in debug stop and wait mode */ - rtwdog_test_mode_t testMode; /*!< Configures RTWDOG test mode */ - bool enableUpdate; /*!< Update write-once register enable */ - bool enableInterrupt; /*!< Enables or disables RTWDOG interrupt */ - bool enableWindowMode; /*!< Enables or disables RTWDOG window mode */ - uint16_t windowValue; /*!< Window value */ - uint16_t timeoutValue; /*!< Timeout value */ -} rtwdog_config_t; - -/*! - * @brief RTWDOG interrupt configuration structure. - * - * This structure contains the settings for all of the RTWDOG interrupt configurations. - */ -enum _rtwdog_interrupt_enable_t -{ - kRTWDOG_InterruptEnable = RTWDOG_CS_INT_MASK, /*!< Interrupt is generated before forcing a reset */ -}; - -/*! - * @brief RTWDOG status flags. - * - * This structure contains the RTWDOG status flags for use in the RTWDOG functions. - */ -enum _rtwdog_status_flags_t -{ - kRTWDOG_RunningFlag = RTWDOG_CS_EN_MASK, /*!< Running flag, set when RTWDOG is enabled */ - kRTWDOG_InterruptFlag = RTWDOG_CS_FLG_MASK, /*!< Interrupt flag, set when interrupt occurs */ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name RTWDOG Initialization and De-initialization - * @{ - */ - -/*! - * @brief Initializes the RTWDOG configuration structure. - * - * This function initializes the RTWDOG configuration structure to default values. The default - * values are: - * @code - * rtwdogConfig->enableRtwdog = true; - * rtwdogConfig->clockSource = kRTWDOG_ClockSource1; - * rtwdogConfig->prescaler = kRTWDOG_ClockPrescalerDivide1; - * rtwdogConfig->workMode.enableWait = true; - * rtwdogConfig->workMode.enableStop = false; - * rtwdogConfig->workMode.enableDebug = false; - * rtwdogConfig->testMode = kRTWDOG_TestModeDisabled; - * rtwdogConfig->enableUpdate = true; - * rtwdogConfig->enableInterrupt = false; - * rtwdogConfig->enableWindowMode = false; - * rtwdogConfig->windowValue = 0U; - * rtwdogConfig->timeoutValue = 0xFFFFU; - * @endcode - * - * @param config Pointer to the RTWDOG configuration structure. - * @see rtwdog_config_t - */ -void RTWDOG_GetDefaultConfig(rtwdog_config_t *config); - -/*! - * @brief Initializes the RTWDOG module. - * - * This function initializes the RTWDOG. - * To reconfigure the RTWDOG without forcing a reset first, enableUpdate must be set to true - * in the configuration. - * - * Example: - * @code - * rtwdog_config_t config; - * RTWDOG_GetDefaultConfig(&config); - * config.timeoutValue = 0x7ffU; - * config.enableUpdate = true; - * RTWDOG_Init(wdog_base,&config); - * @endcode - * - * @param base RTWDOG peripheral base address. - * @param config The configuration of the RTWDOG. - */ -void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config); - -/*! - * @brief De-initializes the RTWDOG module. - * - * This function shuts down the RTWDOG. - * Ensure that the WDOG_CS.UPDATE is 1, which means that the register update is enabled. - * - * @param base RTWDOG peripheral base address. - */ -void RTWDOG_Deinit(RTWDOG_Type *base); - -/* @} */ - -/*! - * @name RTWDOG functional Operation - * @{ - */ - -/*! - * @brief Enables the RTWDOG module. - * - * This function writes a value into the WDOG_CS register to enable the RTWDOG. - * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and - * this register has not been written in this WCT while the function is called. - * - * @param base RTWDOG peripheral base address. - */ -static inline void RTWDOG_Enable(RTWDOG_Type *base) -{ - base->CS |= RTWDOG_CS_EN_MASK; -} - -/*! - * @brief Disables the RTWDOG module. - * - * This function writes a value into the WDOG_CS register to disable the RTWDOG. - * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and - * this register has not been written in this WCT while the function is called. - * - * @param base RTWDOG peripheral base address - */ -static inline void RTWDOG_Disable(RTWDOG_Type *base) -{ - base->CS &= ~RTWDOG_CS_EN_MASK; -} - -/*! - * @brief Enables the RTWDOG interrupt. - * - * This function writes a value into the WDOG_CS register to enable the RTWDOG interrupt. - * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and - * this register has not been written in this WCT while the function is called. - * - * @param base RTWDOG peripheral base address. - * @param mask The interrupts to enable. - * The parameter can be a combination of the following source if defined: - * @arg kRTWDOG_InterruptEnable - */ -static inline void RTWDOG_EnableInterrupts(RTWDOG_Type *base, uint32_t mask) -{ - base->CS |= mask; -} - -/*! - * @brief Disables the RTWDOG interrupt. - * - * This function writes a value into the WDOG_CS register to disable the RTWDOG interrupt. - * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and - * this register has not been written in this WCT while the function is called. - * - * @param base RTWDOG peripheral base address. - * @param mask The interrupts to disabled. - * The parameter can be a combination of the following source if defined: - * @arg kRTWDOG_InterruptEnable - */ -static inline void RTWDOG_DisableInterrupts(RTWDOG_Type *base, uint32_t mask) -{ - base->CS &= ~mask; -} - -/*! - * @brief Gets the RTWDOG all status flags. - * - * This function gets all status flags. - * - * Example to get the running flag: - * @code - * uint32_t status; - * status = RTWDOG_GetStatusFlags(wdog_base) & kRTWDOG_RunningFlag; - * @endcode - * @param base RTWDOG peripheral base address - * @return State of the status flag: asserted (true) or not-asserted (false). @see _rtwdog_status_flags_t - * - true: related status flag has been set. - * - false: related status flag is not set. - */ -static inline uint32_t RTWDOG_GetStatusFlags(RTWDOG_Type *base) -{ - return (base->CS & (RTWDOG_CS_EN_MASK | RTWDOG_CS_FLG_MASK)); -} - -/*! - * @brief Clears the RTWDOG flag. - * - * This function clears the RTWDOG status flag. - * - * Example to clear an interrupt flag: - * @code - * RTWDOG_ClearStatusFlags(wdog_base,kRTWDOG_InterruptFlag); - * @endcode - * @param base RTWDOG peripheral base address. - * @param mask The status flags to clear. - * The parameter can be any combination of the following values: - * @arg kRTWDOG_InterruptFlag - */ -void RTWDOG_ClearStatusFlags(RTWDOG_Type *base, uint32_t mask); - -/*! - * @brief Sets the RTWDOG timeout value. - * - * This function writes a timeout value into the WDOG_TOVAL register. - * The WDOG_TOVAL register is a write-once register. Ensure that the WCT window is still open and - * this register has not been written in this WCT while the function is called. - * - * @param base RTWDOG peripheral base address - * @param timeoutCount RTWDOG timeout value, count of RTWDOG clock ticks. - */ -static inline void RTWDOG_SetTimeoutValue(RTWDOG_Type *base, uint16_t timeoutCount) -{ - base->TOVAL = timeoutCount; -} - -/*! - * @brief Sets the RTWDOG window value. - * - * This function writes a window value into the WDOG_WIN register. - * The WDOG_WIN register is a write-once register. Ensure that the WCT window is still open and - * this register has not been written in this WCT while the function is called. - * - * @param base RTWDOG peripheral base address. - * @param windowValue RTWDOG window value. - */ -static inline void RTWDOG_SetWindowValue(RTWDOG_Type *base, uint16_t windowValue) -{ - base->WIN = windowValue; -} - -/*! - * @brief Unlocks the RTWDOG register written. - * - * This function unlocks the RTWDOG register written. - * - * Before starting the unlock sequence and following the configuration, disable the global interrupts. - * Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire. - * After the configuration finishes, re-enable the global interrupts. - * - * @param base RTWDOG peripheral base address - */ -static inline void RTWDOG_Unlock(RTWDOG_Type *base) -{ - if ((base->CS) & RTWDOG_CS_CMD32EN_MASK) - { - base->CNT = RTWDOG_UPDATE_KEY; - } - else - { - base->CNT = WDOG_FIRST_WORD_OF_UNLOCK; - base->CNT = WDOG_SECOND_WORD_OF_UNLOCK; - } -} - -/*! - * @brief Refreshes the RTWDOG timer. - * - * This function feeds the RTWDOG. - * This function should be called before the Watchdog timer is in timeout. Otherwise, a reset is asserted. - * - * @param base RTWDOG peripheral base address - */ -static inline void RTWDOG_Refresh(RTWDOG_Type *base) -{ - if ((base->CS) & RTWDOG_CS_CMD32EN_MASK) - { - base->CNT = RTWDOG_REFRESH_KEY; - } - else - { - base->CNT = WDOG_FIRST_WORD_OF_REFRESH; - base->CNT = WDOG_SECOND_WORD_OF_REFRESH; - } -} - -/*! - * @brief Gets the RTWDOG counter value. - * - * This function gets the RTWDOG counter value. - * - * @param base RTWDOG peripheral base address. - * @return Current RTWDOG counter value. - */ -static inline uint16_t RTWDOG_GetCounterValue(RTWDOG_Type *base) -{ - return base->CNT; -} - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_RTWDOG_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_sai.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_sai.c deleted file mode 100644 index db5d26a263..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_sai.c +++ /dev/null @@ -1,2104 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_sai.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sai" -#endif - -/******************************************************************************* - * Definitations - ******************************************************************************/ -enum _sai_transfer_state -{ - kSAI_Busy = 0x0U, /*!< SAI is busy */ - kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occured. */ -}; - -/*! @brief Typedef for sai tx interrupt handler. */ -typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); - -/*! @brief Typedef for sai rx interrupt handler. */ -typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - -/*! - * @brief Set the master clock divider. - * - * This API will compute the master clock divider according to master clock frequency and master - * clock source clock source frequency. - * - * @param base SAI base pointer. - * @param mclk_Hz Mater clock frequency in Hz. - * @param mclkSrcClock_Hz Master clock source frequency in Hz. - */ -static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz); -#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ - -/*! - * @brief Get the instance number for SAI. - * - * @param base SAI base pointer. - */ -static uint32_t SAI_GetInstance(I2S_Type *base); - -/*! - * @brief sends a piece of data in non-blocking way. - * - * @param base SAI base pointer - * @param channel Data channel used. - * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. - * @param buffer Pointer to the data to be written. - * @param size Bytes to be written. - */ -static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); - -/*! - * @brief Receive a piece of data in non-blocking way. - * - * @param base SAI base pointer - * @param channel Data channel used. - * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. - * @param buffer Pointer to the data to be read. - * @param size Bytes to be read. - */ -static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Base pointer array */ -static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; -/*!@brief SAI handle pointer */ -static sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2]; -/* IRQ number array */ -static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; -static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Clock name array */ -static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -/*! @brief Pointer to tx IRQ handler for each instance. */ -static sai_tx_isr_t s_saiTxIsr; -/*! @brief Pointer to tx IRQ handler for each instance. */ -static sai_rx_isr_t s_saiRxIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) -static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz) -{ - uint32_t freq = mclkSrcClock_Hz; - uint16_t fract, divide; - uint32_t remaind = 0; - uint32_t current_remainder = 0xFFFFFFFFU; - uint16_t current_fract = 0; - uint16_t current_divide = 0; - uint32_t mul_freq = 0; - uint32_t max_fract = 256; - - /*In order to prevent overflow */ - freq /= 100; - mclk_Hz /= 100; - - /* Compute the max fract number */ - max_fract = mclk_Hz * 4096 / freq + 1; - if (max_fract > 256) - { - max_fract = 256; - } - - /* Looking for the closet frequency */ - for (fract = 1; fract < max_fract; fract++) - { - mul_freq = freq * fract; - remaind = mul_freq % mclk_Hz; - divide = mul_freq / mclk_Hz; - - /* Find the exactly frequency */ - if (remaind == 0) - { - current_fract = fract; - current_divide = mul_freq / mclk_Hz; - break; - } - - /* Closer to next one, set the closest to next data */ - if (remaind > mclk_Hz / 2) - { - remaind = mclk_Hz - remaind; - divide += 1; - } - - /* Update the closest div and fract */ - if (remaind < current_remainder) - { - current_fract = fract; - current_divide = divide; - current_remainder = remaind; - } - } - - /* Fill the computed fract and divider to registers */ - base->MDR = I2S_MDR_DIVIDE(current_divide - 1) | I2S_MDR_FRACT(current_fract - 1); - - /* Waiting for the divider updated */ - while (base->MCR & I2S_MCR_DUF_MASK) - { - } -} -#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ - -static uint32_t SAI_GetInstance(I2S_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_saiBases); instance++) - { - if (s_saiBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_saiBases)); - - return instance; -} - -static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) -{ - uint32_t i = 0; - uint8_t j = 0; - uint8_t bytesPerWord = bitWidth / 8U; - uint32_t data = 0; - uint32_t temp = 0; - - for (i = 0; i < size / bytesPerWord; i++) - { - for (j = 0; j < bytesPerWord; j++) - { - temp = (uint32_t)(*buffer); - data |= (temp << (8U * j)); - buffer++; - } - base->TDR[channel] = data; - data = 0; - } -} - -static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) -{ - uint32_t i = 0; - uint8_t j = 0; - uint8_t bytesPerWord = bitWidth / 8U; - uint32_t data = 0; - - for (i = 0; i < size / bytesPerWord; i++) - { - data = base->RDR[channel]; - for (j = 0; j < bytesPerWord; j++) - { - *buffer = (data >> (8U * j)) & 0xFF; - buffer++; - } - } -} - -void SAI_TxInit(I2S_Type *base, const sai_config_t *config) -{ - uint32_t val = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SAI clock */ - CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Master clock source setting */ - val = (base->MCR & ~I2S_MCR_MICS_MASK); - base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); - - /* Configure Master clock output enable */ - val = (base->MCR & ~I2S_MCR_MOE_MASK); - base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - - SAI_TxReset(base); - - /* Configure audio protocol */ - switch (config->protocol) - { - case kSAI_BusLeftJustified: - base->TCR2 |= I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - break; - - case kSAI_BusRightJustified: - base->TCR2 |= I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - break; - - case kSAI_BusI2S: - base->TCR2 |= I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(1U) | I2S_TCR4_FRSZ(1U); - break; - - case kSAI_BusPCMA: - base->TCR2 &= ~I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - break; - - case kSAI_BusPCMB: - base->TCR2 &= ~I2S_TCR2_BCP_MASK; - base->TCR3 &= ~I2S_TCR3_WDFL_MASK; - base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); - break; - - default: - break; - } - - /* Set master or slave */ - if (config->masterSlave == kSAI_Master) - { - base->TCR2 |= I2S_TCR2_BCD_MASK; - base->TCR4 |= I2S_TCR4_FSD_MASK; - - /* Bit clock source setting */ - val = base->TCR2 & (~I2S_TCR2_MSEL_MASK); - base->TCR2 = (val | I2S_TCR2_MSEL(config->bclkSource)); - } - else - { - base->TCR2 &= ~I2S_TCR2_BCD_MASK; - base->TCR4 &= ~I2S_TCR4_FSD_MASK; - } - - /* Set Sync mode */ - switch (config->syncMode) - { - case kSAI_ModeAsync: - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(0U)); - break; - case kSAI_ModeSync: - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(1U)); - /* If sync with Rx, should set Rx to async mode */ - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(0U)); - break; - case kSAI_ModeSyncWithOtherTx: - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(2U)); - break; - case kSAI_ModeSyncWithOtherRx: - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(3U)); - break; - default: - break; - } - -#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR - SAI_TxSetFIFOErrorContinue(base, true); -#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ -} - -void SAI_RxInit(I2S_Type *base, const sai_config_t *config) -{ - uint32_t val = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable SAI clock first. */ - CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Master clock source setting */ - val = (base->MCR & ~I2S_MCR_MICS_MASK); - base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); - - /* Configure Master clock output enable */ - val = (base->MCR & ~I2S_MCR_MOE_MASK); - base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - - SAI_RxReset(base); - - /* Configure audio protocol */ - switch (config->protocol) - { - case kSAI_BusLeftJustified: - base->RCR2 |= I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - break; - - case kSAI_BusRightJustified: - base->RCR2 |= I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - break; - - case kSAI_BusI2S: - base->RCR2 |= I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(1U) | I2S_RCR4_FRSZ(1U); - break; - - case kSAI_BusPCMA: - base->RCR2 &= ~I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - break; - - case kSAI_BusPCMB: - base->RCR2 &= ~I2S_RCR2_BCP_MASK; - base->RCR3 &= ~I2S_RCR3_WDFL_MASK; - base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); - break; - - default: - break; - } - - /* Set master or slave */ - if (config->masterSlave == kSAI_Master) - { - base->RCR2 |= I2S_RCR2_BCD_MASK; - base->RCR4 |= I2S_RCR4_FSD_MASK; - - /* Bit clock source setting */ - val = base->RCR2 & (~I2S_RCR2_MSEL_MASK); - base->RCR2 = (val | I2S_RCR2_MSEL(config->bclkSource)); - } - else - { - base->RCR2 &= ~I2S_RCR2_BCD_MASK; - base->RCR4 &= ~I2S_RCR4_FSD_MASK; - } - - /* Set Sync mode */ - switch (config->syncMode) - { - case kSAI_ModeAsync: - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(0U)); - break; - case kSAI_ModeSync: - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(1U)); - /* If sync with Tx, should set Tx to async mode */ - val = base->TCR2; - val &= ~I2S_TCR2_SYNC_MASK; - base->TCR2 = (val | I2S_TCR2_SYNC(0U)); - break; - case kSAI_ModeSyncWithOtherTx: - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(2U)); - break; - case kSAI_ModeSyncWithOtherRx: - val = base->RCR2; - val &= ~I2S_RCR2_SYNC_MASK; - base->RCR2 = (val | I2S_RCR2_SYNC(3U)); - break; - default: - break; - } - -#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR - SAI_RxSetFIFOErrorContinue(base, true); -#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ -} - -void SAI_Deinit(I2S_Type *base) -{ - SAI_TxEnable(base, false); - SAI_RxEnable(base, false); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_saiClock[SAI_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void SAI_TxGetDefaultConfig(sai_config_t *config) -{ - config->bclkSource = kSAI_BclkSourceMclkDiv; - config->masterSlave = kSAI_Master; - config->mclkSource = kSAI_MclkSourceSysclk; - config->protocol = kSAI_BusI2S; - config->syncMode = kSAI_ModeAsync; -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - config->mclkOutputEnable = true; -#endif /* FSL_FEATURE_SAI_HAS_MCR */ -} - -void SAI_RxGetDefaultConfig(sai_config_t *config) -{ - config->bclkSource = kSAI_BclkSourceMclkDiv; - config->masterSlave = kSAI_Master; - config->mclkSource = kSAI_MclkSourceSysclk; - config->protocol = kSAI_BusI2S; - config->syncMode = kSAI_ModeSync; -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - config->mclkOutputEnable = true; -#endif /* FSL_FEATURE_SAI_HAS_MCR */ -} - -void SAI_TxReset(I2S_Type *base) -{ - /* Set the software reset and FIFO reset to clear internal state */ - base->TCSR = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK; - - /* Clear software reset bit, this should be done by software */ - base->TCSR &= ~I2S_TCSR_SR_MASK; - - /* Reset all Tx register values */ - base->TCR2 = 0; - base->TCR3 = 0; - base->TCR4 = 0; - base->TCR5 = 0; - base->TMR = 0; -} - -void SAI_RxReset(I2S_Type *base) -{ - /* Set the software reset and FIFO reset to clear internal state */ - base->RCSR = I2S_RCSR_SR_MASK | I2S_RCSR_FR_MASK; - - /* Clear software reset bit, this should be done by software */ - base->RCSR &= ~I2S_RCSR_SR_MASK; - - /* Reset all Rx register values */ - base->RCR2 = 0; - base->RCR3 = 0; - base->RCR4 = 0; - base->RCR5 = 0; - base->RMR = 0; -} - -void SAI_TxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - /* If clock is sync with Rx, should enable RE bit. */ - if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) == 0x1U) - { - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); - } - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); - /* Also need to clear the FIFO error flag before start */ - SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag); - } - else - { - /* If RE not sync with TE, than disable TE, otherwise, shall not disable TE */ - if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) != 0x1U) - { - /* Should not close RE even sync with Rx */ - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~I2S_TCSR_TE_MASK)); - } - } -} - -void SAI_RxEnable(I2S_Type *base, bool enable) -{ - if (enable) - { - /* If clock is sync with Tx, should enable TE bit. */ - if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) == 0x1U) - { - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); - } - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); - /* Also need to clear the FIFO error flag before start */ - SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag); - } - else - { - /* While TX is not sync with RX, close RX */ - if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) != 0x1U) - { - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~I2S_RCSR_RE_MASK)); - } - } -} - -void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type) -{ - base->TCSR |= (uint32_t)type; - - /* Clear the software reset */ - base->TCSR &= ~I2S_TCSR_SR_MASK; -} - -void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type) -{ - base->RCSR |= (uint32_t)type; - - /* Clear the software reset */ - base->RCSR &= ~I2S_RCSR_SR_MASK; -} - -void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) -{ - base->TCR3 &= ~I2S_TCR3_TCE_MASK; - base->TCR3 |= I2S_TCR3_TCE(mask); -} - -void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) -{ - base->RCR3 &= ~I2S_RCR3_RCE_MASK; - base->RCR3 |= I2S_RCR3_RCE(mask); -} - -void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order) -{ - uint32_t val = (base->TCR4) & (~I2S_TCR4_MF_MASK); - - val |= I2S_TCR4_MF(order); - base->TCR4 = val; -} - -void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order) -{ - uint32_t val = (base->RCR4) & (~I2S_RCR4_MF_MASK); - - val |= I2S_RCR4_MF(order); - base->RCR4 = val; -} - -void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) -{ - uint32_t val = (base->TCR2) & (~I2S_TCR2_BCP_MASK); - - val |= I2S_TCR2_BCP(polarity); - base->TCR2 = val; -} - -void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) -{ - uint32_t val = (base->RCR2) & (~I2S_RCR2_BCP_MASK); - - val |= I2S_RCR2_BCP(polarity); - base->RCR2 = val; -} - -void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) -{ - uint32_t val = (base->TCR4) & (~I2S_TCR4_FSP_MASK); - - val |= I2S_TCR4_FSP(polarity); - base->TCR4 = val; -} - -void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) -{ - uint32_t val = (base->RCR4) & (~I2S_RCR4_FSP_MASK); - - val |= I2S_RCR4_FSP(polarity); - base->RCR4 = val; -} - -#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING -void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) -{ - uint32_t val = base->TCR4; - - val &= ~I2S_TCR4_FPACK_MASK; - val |= I2S_TCR4_FPACK(pack); - base->TCR4 = val; -} - -void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) -{ - uint32_t val = base->RCR4; - - val &= ~I2S_RCR4_FPACK_MASK; - val |= I2S_RCR4_FPACK(pack); - base->RCR4 = val; -} -#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ - -void SAI_TxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - uint32_t bclk = 0; - uint32_t val = 0; - uint32_t channels = 2U; - - if (format->stereo != kSAI_Stereo) - { - channels = 1U; - } - - if (format->isFrameSyncCompact) - { - bclk = format->sampleRate_Hz * format->bitWidth * channels; - val = (base->TCR4 & (~I2S_TCR4_SYWD_MASK)); - val |= I2S_TCR4_SYWD(format->bitWidth - 1U); - base->TCR4 = val; - } - else - { - bclk = format->sampleRate_Hz * 32U * 2U; - } - -/* Compute the mclk */ -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - /* Check if master clock divider enabled, then set master clock divider */ - if (base->MCR & I2S_MCR_MOE_MASK) - { - SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); - } -#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ - - /* Set bclk if needed */ - if (base->TCR2 & I2S_TCR2_BCD_MASK) - { - base->TCR2 &= ~I2S_TCR2_DIV_MASK; - base->TCR2 |= I2S_TCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); - } - - /* Set bitWidth */ - val = (format->isFrameSyncCompact) ? (format->bitWidth - 1) : 31U; - if (format->protocol == kSAI_BusRightJustified) - { - base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(val); - } - else - { - if (base->TCR4 & I2S_TCR4_MF_MASK) - { - base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1); - } - else - { - base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(0); - } - } - - /* Set mono or stereo */ - base->TMR = (uint32_t)format->stereo; - - /* Set data channel */ - base->TCR3 &= ~I2S_TCR3_TCE_MASK; - base->TCR3 |= I2S_TCR3_TCE(1U << format->channel); - -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - /* Set watermark */ - base->TCR1 = format->watermark; -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ -} - -void SAI_RxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - uint32_t bclk = 0; - uint32_t val = 0; - uint32_t channels = 2U; - - if (format->stereo != kSAI_Stereo) - { - channels = 1U; - } - - if (format->isFrameSyncCompact) - { - bclk = format->sampleRate_Hz * format->bitWidth * channels; - val = (base->RCR4 & (~I2S_RCR4_SYWD_MASK)); - val |= I2S_RCR4_SYWD(format->bitWidth - 1U); - base->RCR4 = val; - } - else - { - bclk = format->sampleRate_Hz * 32U * 2U; - } - -/* Compute the mclk */ -#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) - /* Check if master clock divider enabled */ - if (base->MCR & I2S_MCR_MOE_MASK) - { - SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); - } -#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ - - /* Set bclk if needed */ - if (base->RCR2 & I2S_RCR2_BCD_MASK) - { - base->RCR2 &= ~I2S_RCR2_DIV_MASK; - base->RCR2 |= I2S_RCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); - } - - /* Set bitWidth */ - val = (format->isFrameSyncCompact) ? (format->bitWidth - 1) : 31U; - if (format->protocol == kSAI_BusRightJustified) - { - base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(val); - } - else - { - if (base->RCR4 & I2S_RCR4_MF_MASK) - { - base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1); - } - else - { - base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(0); - } - } - - /* Set mono or stereo */ - base->RMR = (uint32_t)format->stereo; - - /* Set data channel */ - base->RCR3 &= ~I2S_RCR3_RCE_MASK; - base->RCR3 |= I2S_RCR3_RCE(1U << format->channel); - -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - /* Set watermark */ - base->RCR1 = format->watermark; -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ -} - -void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) -{ - uint32_t i = 0; - uint8_t bytesPerWord = bitWidth / 8U; - - while (i < size) - { - /* Wait until it can write data */ - while (!(base->TCSR & I2S_TCSR_FWF_MASK)) - { - } - - SAI_WriteNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); - buffer += bytesPerWord; - i += bytesPerWord; - } - - /* Wait until the last data is sent */ - while (!(base->TCSR & I2S_TCSR_FWF_MASK)) - { - } -} - -void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) -{ - uint32_t i = 0; - uint8_t bytesPerWord = bitWidth / 8U; - - while (i < size) - { - /* Wait until data is received */ - while (!(base->RCSR & I2S_RCSR_FWF_MASK)) - { - } - - SAI_ReadNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); - buffer += bytesPerWord; - i += bytesPerWord; - } -} - -void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) -{ - assert(handle); - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - s_saiHandle[SAI_GetInstance(base)][0] = handle; - - handle->callback = callback; - handle->userData = userData; - - /* Set the isr pointer */ - s_saiTxIsr = SAI_TransferTxHandleIRQ; - - /* Enable Tx irq */ - EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); -} - -void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) -{ - assert(handle); - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - s_saiHandle[SAI_GetInstance(base)][1] = handle; - - handle->callback = callback; - handle->userData = userData; - - /* Set the isr pointer */ - s_saiRxIsr = SAI_TransferRxHandleIRQ; - - /* Enable Rx irq */ - EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); -} - -status_t SAI_TransferTxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(handle); - - if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) - { - return kStatus_InvalidArgument; - } - - /* Copy format to handle */ - handle->bitWidth = format->bitWidth; -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - handle->watermark = format->watermark; -#endif - handle->channel = format->channel; - - SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - return kStatus_Success; -} - -status_t SAI_TransferRxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(handle); - - if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) - { - return kStatus_InvalidArgument; - } - - /* Copy format to handle */ - handle->bitWidth = format->bitWidth; -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - handle->watermark = format->watermark; -#endif - handle->channel = format->channel; - - SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - return kStatus_Success; -} - -status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) -{ - assert(handle); - - /* Check if the queue is full */ - if (handle->saiQueue[handle->queueUser].data) - { - return kStatus_SAI_QueueFull; - } - - /* Add into queue */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->saiQueue[handle->queueUser].data = xfer->data; - handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; - - /* Set the state to busy */ - handle->state = kSAI_Busy; - -/* Enable interrupt */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - /* Use FIFO request interrupt and fifo error*/ - SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); -#else - SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - - /* Enable Tx transfer */ - SAI_TxEnable(base, true); - - return kStatus_Success; -} - -status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) -{ - assert(handle); - - /* Check if the queue is full */ - if (handle->saiQueue[handle->queueUser].data) - { - return kStatus_SAI_QueueFull; - } - - /* Add into queue */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->saiQueue[handle->queueUser].data = xfer->data; - handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; - - /* Set state to busy */ - handle->state = kSAI_Busy; - -/* Enable interrupt */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - /* Use FIFO request interrupt and fifo error*/ - SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); -#else - SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - - /* Enable Rx transfer */ - SAI_RxEnable(base, true); - - return kStatus_Success; -} - -status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSAI_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); - } - - return status; -} - -status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSAI_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); - } - - return status; -} - -void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) -{ - assert(handle); - - /* Stop Tx transfer and disable interrupt */ - SAI_TxEnable(base, false); -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - /* Use FIFO request interrupt and fifo error */ - SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); -#else - SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - - handle->state = kSAI_Idle; - - /* Clear the queue */ - memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); - handle->queueDriver = 0; - handle->queueUser = 0; -} - -void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) -{ - assert(handle); - - /* Stop Tx transfer and disable interrupt */ - SAI_RxEnable(base, false); -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - /* Use FIFO request interrupt and fifo error */ - SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); -#else - SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - - handle->state = kSAI_Idle; - - /* Clear the queue */ - memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); - handle->queueDriver = 0; - handle->queueUser = 0; -} - -void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle) -{ - assert(handle); - - /* Abort the current transfer */ - SAI_TransferAbortSend(base, handle); - - /* Clear all the internal information */ - memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); - memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; - handle->queueDriver = 0U; -} - -void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle) -{ - assert(handle); - - /* Abort the current transfer */ - SAI_TransferAbortReceive(base, handle); - - /* Clear all the internal information */ - memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); - memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; - handle->queueDriver = 0U; -} - -void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) -{ - assert(handle); - - uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; - uint8_t dataSize = handle->bitWidth / 8U; - - /* Handle Error */ - if (base->TCSR & I2S_TCSR_FEF_MASK) - { - /* Clear FIFO error flag to continue transfer */ - SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag); - - /* Reset FIFO for safety */ - SAI_TxSoftwareReset(base, kSAI_ResetTypeFIFO); - - /* Call the callback */ - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SAI_TxError, handle->userData); - } - } - -/* Handle transfer */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if (base->TCSR & I2S_TCSR_FRF_MASK) - { - /* Judge if the data need to transmit is less than space */ - uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), - (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - handle->watermark) * dataSize)); - - /* Copy the data from sai buffer to FIFO */ - SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); - - /* Update the internal counter */ - handle->saiQueue[handle->queueDriver].dataSize -= size; - handle->saiQueue[handle->queueDriver].data += size; - } -#else - if (base->TCSR & I2S_TCSR_FWF_MASK) - { - uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); - - SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); - - /* Update internal counter */ - handle->saiQueue[handle->queueDriver].dataSize -= size; - handle->saiQueue[handle->queueDriver].data += size; - } -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - - /* If finished a blcok, call the callback function */ - if (handle->saiQueue[handle->queueDriver].dataSize == 0U) - { - memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); - handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SAI_TxIdle, handle->userData); - } - } - - /* If all data finished, just stop the transfer */ - if (handle->saiQueue[handle->queueDriver].data == NULL) - { - SAI_TransferAbortSend(base, handle); - } -} - -void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) -{ - assert(handle); - - uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; - uint8_t dataSize = handle->bitWidth / 8U; - - /* Handle Error */ - if (base->RCSR & I2S_RCSR_FEF_MASK) - { - /* Clear FIFO error flag to continue transfer */ - SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag); - - /* Reset FIFO for safety */ - SAI_RxSoftwareReset(base, kSAI_ResetTypeFIFO); - - /* Call the callback */ - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SAI_RxError, handle->userData); - } - } - -/* Handle transfer */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if (base->RCSR & I2S_RCSR_FRF_MASK) - { - /* Judge if the data need to transmit is less than space */ - uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), (handle->watermark * dataSize)); - - /* Copy the data from sai buffer to FIFO */ - SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); - - /* Update the internal counter */ - handle->saiQueue[handle->queueDriver].dataSize -= size; - handle->saiQueue[handle->queueDriver].data += size; - } -#else - if (base->RCSR & I2S_RCSR_FWF_MASK) - { - uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); - - SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); - - /* Update internal state */ - handle->saiQueue[handle->queueDriver].dataSize -= size; - handle->saiQueue[handle->queueDriver].data += size; - } -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - - /* If finished a blcok, call the callback function */ - if (handle->saiQueue[handle->queueDriver].dataSize == 0U) - { - memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); - handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SAI_RxIdle, handle->userData); - } - } - - /* If all data finished, just stop the transfer */ - if (handle->saiQueue[handle->queueDriver].data == NULL) - { - SAI_TransferAbortReceive(base, handle); - } -} - -#if defined(I2S0) -void I2S0_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFORequestFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) && - ((I2S0->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) && - ((I2S0->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(I2S0, s_saiHandle[0][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFORequestFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) && - ((I2S0->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) && - ((I2S0->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(I2S0, s_saiHandle[0][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void I2S0_Tx_DriverIRQHandler(void) -{ - assert(s_saiHandle[0][0]); - s_saiTxIsr(I2S0, s_saiHandle[0][0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void I2S0_Rx_DriverIRQHandler(void) -{ - assert(s_saiHandle[0][1]); - s_saiRxIsr(I2S0, s_saiHandle[0][1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* I2S0*/ - -#if defined(I2S1) -void I2S1_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFORequestFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) && - ((I2S1->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFOWarningFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) && - ((I2S1->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(I2S1, s_saiHandle[1][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFORequestFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) && - ((I2S1->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFOWarningFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) && - ((I2S1->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(I2S1, s_saiHandle[1][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void I2S1_Tx_DriverIRQHandler(void) -{ - assert(s_saiHandle[1][0]); - s_saiTxIsr(I2S1, s_saiHandle[1][0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void I2S1_Rx_DriverIRQHandler(void) -{ - assert(s_saiHandle[1][1]); - s_saiRxIsr(I2S1, s_saiHandle[1][1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* I2S1*/ - -#if defined(I2S2) -void I2S2_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFORequestFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) && - ((I2S2->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFOWarningFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) && - ((I2S2->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(I2S2, s_saiHandle[2][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFORequestFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) && - ((I2S2->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFOWarningFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) && - ((I2S2->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(I2S2, s_saiHandle[2][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void I2S2_Tx_DriverIRQHandler(void) -{ - assert(s_saiHandle[2][0]); - s_saiTxIsr(I2S2, s_saiHandle[2][0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void I2S2_Rx_DriverIRQHandler(void) -{ - assert(s_saiHandle[2][1]); - s_saiRxIsr(I2S2, s_saiHandle[2][1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* I2S2*/ - -#if defined(I2S3) -void I2S3_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFORequestFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) && - ((I2S3->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFOWarningFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) && - ((I2S3->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(I2S3, s_saiHandle[3][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFORequestFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) && - ((I2S3->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFOWarningFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) && - ((I2S3->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(I2S3, s_saiHandle[3][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void I2S3_Tx_DriverIRQHandler(void) -{ - assert(s_saiHandle[3][0]); - s_saiTxIsr(I2S3, s_saiHandle[3][0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void I2S3_Rx_DriverIRQHandler(void) -{ - assert(s_saiHandle[3][1]); - s_saiRxIsr(I2S3, s_saiHandle[3][1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* I2S3*/ - -#if defined(AUDIO__SAI0) -void AUDIO_SAI0_INT_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[0][1]) && - ((AUDIO__SAI0->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI0->RCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI0->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[0][1]) && - ((AUDIO__SAI0->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI0->RCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI0->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(AUDIO__SAI0, s_saiHandle[0][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[0][0]) && - ((AUDIO__SAI0->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI0->TCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI0->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[0][0]) && - ((AUDIO__SAI0->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI0->TCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI0->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(AUDIO__SAI0, s_saiHandle[0][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* AUDIO__SAI0 */ - -#if defined(AUDIO__SAI1) -void AUDIO_SAI1_INT_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][1]) && - ((AUDIO__SAI1->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI1->RCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI1->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][1]) && - ((AUDIO__SAI1->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI1->RCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI1->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(AUDIO__SAI1, s_saiHandle[1][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][0]) && - ((AUDIO__SAI1->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI1->TCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI1->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][0]) && - ((AUDIO__SAI1->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI1->TCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI1->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(AUDIO__SAI1, s_saiHandle[1][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* AUDIO__SAI1 */ - -#if defined(AUDIO__SAI2) -void AUDIO_SAI2_INT_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[2][1]) && - ((AUDIO__SAI2->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI2->RCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI2->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[2][1]) && - ((AUDIO__SAI2->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI2->RCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI2->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(AUDIO__SAI2, s_saiHandle[2][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[2][0]) && - ((AUDIO__SAI2->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI2->TCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI2->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[2][0]) && - ((AUDIO__SAI2->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI2->TCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI2->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(AUDIO__SAI2, s_saiHandle[2][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* AUDIO__SAI2 */ - -#if defined(AUDIO__SAI3) -void AUDIO_SAI3_INT_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[3][1]) && - ((AUDIO__SAI3->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI3->RCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI3->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[3][1]) && - ((AUDIO__SAI3->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI3->RCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI3->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(AUDIO__SAI3, s_saiHandle[3][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[3][0]) && - ((AUDIO__SAI3->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI3->TCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI3->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[3][0]) && - ((AUDIO__SAI3->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI3->TCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI3->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(AUDIO__SAI3, s_saiHandle[3][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(AUDIO__SAI6) -void AUDIO_SAI6_INT_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[6][1]) && - ((AUDIO__SAI6->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI6->RCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI6->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI6->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[6][1]) && - ((AUDIO__SAI6->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI6->RCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI6->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI6->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(AUDIO__SAI6, s_saiHandle[6][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[6][0]) && - ((AUDIO__SAI6->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI6->TCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI6->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI6->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[6][0]) && - ((AUDIO__SAI6->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI6->TCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI6->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI6->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(AUDIO__SAI6, s_saiHandle[6][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* AUDIO__SAI6 */ - -#if defined(AUDIO__SAI7) -void AUDIO_SAI7_INT_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[7][1]) && - ((AUDIO__SAI7->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI7->RCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI7->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI7->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[7][1]) && - ((AUDIO__SAI7->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI7->RCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI7->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI7->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(AUDIO__SAI7, s_saiHandle[7][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[7][0]) && - ((AUDIO__SAI7->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI7->TCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI7->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI7->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[7][0]) && - ((AUDIO__SAI7->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI7->TCSR & kSAI_FIFOErrorFlag)) && - ((AUDIO__SAI7->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI7->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(AUDIO__SAI7, s_saiHandle[7][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* AUDIO__SAI7 */ - -#if defined(ADMA__SAI0) -void ADMA_SAI0_INT_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][1]) && ((ADMA__SAI0->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI0->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][1]) && ((ADMA__SAI0->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI0->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(ADMA__SAI0, s_saiHandle[1][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][0]) && ((ADMA__SAI0->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI0->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][0]) && ((ADMA__SAI0->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI0->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(ADMA__SAI0, s_saiHandle[1][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* ADMA__SAI0 */ - -#if defined(ADMA__SAI1) -void ADMA_SAI1_INT_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][1]) && ((ADMA__SAI1->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI1->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][1]) && ((ADMA__SAI1->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI1->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(ADMA__SAI1, s_saiHandle[1][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][0]) && ((ADMA__SAI1->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI1->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][0]) && ((ADMA__SAI1->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI1->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(ADMA__SAI1, s_saiHandle[1][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* ADMA__SAI1 */ - -#if defined(ADMA__SAI2) -void ADMA_SAI2_INT_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][1]) && ((ADMA__SAI2->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI2->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][1]) && ((ADMA__SAI2->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI2->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(ADMA__SAI2, s_saiHandle[1][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][0]) && ((ADMA__SAI2->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI2->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][0]) && ((ADMA__SAI2->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI2->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(ADMA__SAI2, s_saiHandle[1][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* ADMA__SAI2 */ - -#if defined(ADMA__SAI3) -void ADMA_SAI3_INT_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][1]) && ((ADMA__SAI3->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI3->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][1]) && ((ADMA__SAI3->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI3->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(ADMA__SAI3, s_saiHandle[1][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][0]) && ((ADMA__SAI3->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI3->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][0]) && ((ADMA__SAI3->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI3->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(ADMA__SAI3, s_saiHandle[1][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* ADMA__SAI3 */ - -#if defined(ADMA__SAI4) -void ADMA_SAI4_INT_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][1]) && ((ADMA__SAI4->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI4->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][1]) && ((ADMA__SAI4->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI4->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(ADMA__SAI4, s_saiHandle[1][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][0]) && ((ADMA__SAI4->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI4->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][0]) && ((ADMA__SAI4->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI4->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(ADMA__SAI4, s_saiHandle[1][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* ADMA__SAI4 */ - -#if defined(ADMA__SAI5) -void ADMA_SAI5_INT_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][1]) && ((ADMA__SAI5->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI5->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][1]) && ((ADMA__SAI5->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI5->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(ADMA__SAI5, s_saiHandle[1][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][0]) && ((ADMA__SAI5->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI5->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][0]) && ((ADMA__SAI5->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorFlag)) && - ((ADMA__SAI5->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(ADMA__SAI5, s_saiHandle[1][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* ADMA__SAI5 */ - -#if defined(SAI0) -void SAI0_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[0][1]) && ((SAI0->RCSR & kSAI_FIFORequestFlag) || (SAI0->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI0->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[0][1]) && ((SAI0->RCSR & kSAI_FIFOWarningFlag) || (SAI0->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI0->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(SAI0, s_saiHandle[0][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[0][0]) && ((SAI0->TCSR & kSAI_FIFORequestFlag) || (SAI0->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI0->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[0][0]) && ((SAI0->TCSR & kSAI_FIFOWarningFlag) || (SAI0->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI0->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(AUDIO__SAI0, s_saiHandle[0][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* SAI0 */ - -#if defined(SAI1) -void SAI1_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][1]) && ((SAI1->RCSR & kSAI_FIFORequestFlag) || (SAI1->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI1->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][1]) && ((SAI1->RCSR & kSAI_FIFOWarningFlag) || (SAI1->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI1->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(SAI1, s_saiHandle[1][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[1][0]) && ((SAI1->TCSR & kSAI_FIFORequestFlag) || (SAI1->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI1->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[1][0]) && ((SAI1->TCSR & kSAI_FIFOWarningFlag) || (SAI1->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI1->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(SAI1, s_saiHandle[1][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* SAI1 */ - -#if defined(SAI2) -void SAI2_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[2][1]) && ((SAI2->RCSR & kSAI_FIFORequestFlag) || (SAI2->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI2->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[2][1]) && ((SAI2->RCSR & kSAI_FIFOWarningFlag) || (SAI2->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI2->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(SAI2, s_saiHandle[2][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[2][0]) && ((SAI2->TCSR & kSAI_FIFORequestFlag) || (SAI2->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI2->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[2][0]) && ((SAI2->TCSR & kSAI_FIFOWarningFlag) || (SAI2->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI2->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(SAI2, s_saiHandle[2][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* SAI2 */ - -#if defined(SAI3) -void SAI3_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[3][1]) && ((SAI3->RCSR & kSAI_FIFORequestFlag) || (SAI3->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI3->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[3][1]) && ((SAI3->RCSR & kSAI_FIFOWarningFlag) || (SAI3->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI3->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(SAI3, s_saiHandle[3][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[3][0]) && ((SAI3->TCSR & kSAI_FIFORequestFlag) || (SAI3->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI3->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[3][0]) && ((SAI3->TCSR & kSAI_FIFOWarningFlag) || (SAI3->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI3->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(SAI3, s_saiHandle[3][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void SAI3_Tx_DriverIRQHandler(void) -{ - assert(s_saiHandle[3][0]); - s_saiTxIsr(SAI3, s_saiHandle[3][0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -void SAI3_Rx_DriverIRQHandler(void) -{ - assert(s_saiHandle[3][1]); - s_saiRxIsr(SAI3, s_saiHandle[3][1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* SAI3 */ - -#if defined(SAI4) -void SAI4_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[4][1]) && ((SAI4->RCSR & kSAI_FIFORequestFlag) || (SAI4->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI4->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[4][1]) && ((SAI4->RCSR & kSAI_FIFOWarningFlag) || (SAI4->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI4->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(SAI4, s_saiHandle[4][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[4][0]) && ((SAI4->TCSR & kSAI_FIFORequestFlag) || (SAI4->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI4->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[4][0]) && ((SAI4->TCSR & kSAI_FIFOWarningFlag) || (SAI4->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI4->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(SAI4, s_saiHandle[4][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* SAI4 */ - -#if defined(SAI5) -void SAI5_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[5][1]) && ((SAI5->RCSR & kSAI_FIFORequestFlag) || (SAI5->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI5->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[5][1]) && ((SAI5->RCSR & kSAI_FIFOWarningFlag) || (SAI5->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI5->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(SAI5, s_saiHandle[5][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[5][0]) && ((SAI5->TCSR & kSAI_FIFORequestFlag) || (SAI5->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI5->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[5][0]) && ((SAI5->TCSR & kSAI_FIFOWarningFlag) || (SAI5->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI5->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(SAI5, s_saiHandle[5][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* SAI5 */ - -#if defined(SAI6) -void SAI6_DriverIRQHandler(void) -{ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[6][1]) && ((SAI6->RCSR & kSAI_FIFORequestFlag) || (SAI6->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI6->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI6->RCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[6][1]) && ((SAI6->RCSR & kSAI_FIFOWarningFlag) || (SAI6->RCSR & kSAI_FIFOErrorFlag)) && - ((SAI6->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI6->RCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiRxIsr(SAI6, s_saiHandle[6][1]); - } -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - if ((s_saiHandle[6][0]) && ((SAI6->TCSR & kSAI_FIFORequestFlag) || (SAI6->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI6->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI6->TCSR & kSAI_FIFOErrorInterruptEnable))) -#else - if ((s_saiHandle[6][0]) && ((SAI6->TCSR & kSAI_FIFOWarningFlag) || (SAI6->TCSR & kSAI_FIFOErrorFlag)) && - ((SAI6->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI6->TCSR & kSAI_FIFOErrorInterruptEnable))) -#endif - { - s_saiTxIsr(SAI6, s_saiHandle[6][0]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* SAI6 */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_sai.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_sai.h deleted file mode 100644 index 82dd26bfa6..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_sai.h +++ /dev/null @@ -1,1043 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_SAI_H_ -#define _FSL_SAI_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup sai - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4 */ -/*@}*/ - -/*! @brief SAI return status*/ -enum _sai_status_t -{ - kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */ - kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */ - kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */ - kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */ - kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), /*!< SAI transfer queue is full. */ - kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */ - kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */ -}; - -/*! @brief Define the SAI bus type */ -typedef enum _sai_protocol -{ - kSAI_BusLeftJustified = 0x0U, /*!< Uses left justified format.*/ - kSAI_BusRightJustified, /*!< Uses right justified format. */ - kSAI_BusI2S, /*!< Uses I2S format. */ - kSAI_BusPCMA, /*!< Uses I2S PCM A format.*/ - kSAI_BusPCMB /*!< Uses I2S PCM B format. */ -} sai_protocol_t; - -/*! @brief Master or slave mode */ -typedef enum _sai_master_slave -{ - kSAI_Master = 0x0U, /*!< Master mode */ - kSAI_Slave = 0x1U /*!< Slave mode */ -} sai_master_slave_t; - -/*! @brief Mono or stereo audio format */ -typedef enum _sai_mono_stereo -{ - kSAI_Stereo = 0x0U, /*!< Stereo sound. */ - kSAI_MonoRight, /*!< Only Right channel have sound. */ - kSAI_MonoLeft /*!< Only left channel have sound. */ -} sai_mono_stereo_t; - -/*! @brief SAI data order, MSB or LSB */ -typedef enum _sai_data_order -{ - kSAI_DataLSB = 0x0U, /*!< LSB bit transferred first */ - kSAI_DataMSB /*!< MSB bit transferred first */ -} sai_data_order_t; - -/*! @brief SAI clock polarity, active high or low */ -typedef enum _sai_clock_polarity -{ - kSAI_PolarityActiveHigh = 0x0U, /*!< Clock active high */ - kSAI_PolarityActiveLow /*!< Clock active low */ -} sai_clock_polarity_t; - -/*! @brief Synchronous or asynchronous mode */ -typedef enum _sai_sync_mode -{ - kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */ - kSAI_ModeSync, /*!< Synchronous mode (with receiver or transmit) */ - kSAI_ModeSyncWithOtherTx, /*!< Synchronous with another SAI transmit */ - kSAI_ModeSyncWithOtherRx /*!< Synchronous with another SAI receiver */ -} sai_sync_mode_t; - -/*! @brief Mater clock source */ -typedef enum _sai_mclk_source -{ - kSAI_MclkSourceSysclk = 0x0U, /*!< Master clock from the system clock */ - kSAI_MclkSourceSelect1, /*!< Master clock from source 1 */ - kSAI_MclkSourceSelect2, /*!< Master clock from source 2 */ - kSAI_MclkSourceSelect3 /*!< Master clock from source 3 */ -} sai_mclk_source_t; - -/*! @brief Bit clock source */ -typedef enum _sai_bclk_source -{ - kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */ - kSAI_BclkSourceMclkDiv, /*!< Bit clock using master clock divider */ - kSAI_BclkSourceOtherSai0, /*!< Bit clock from other SAI device */ - kSAI_BclkSourceOtherSai1 /*!< Bit clock from other SAI device */ -} sai_bclk_source_t; - -/*! @brief The SAI interrupt enable flag */ -enum _sai_interrupt_enable_t -{ - kSAI_WordStartInterruptEnable = - I2S_TCSR_WSIE_MASK, /*!< Word start flag, means the first word in a frame detected */ - kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */ - kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, /*!< FIFO warning flag, means the FIFO is empty */ - kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK, /*!< FIFO request, means reached watermark */ -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ -}; - -/*! @brief The DMA request sources */ -enum _sai_dma_enable_t -{ - kSAI_FIFOWarningDMAEnable = I2S_TCSR_FWDE_MASK, /*!< FIFO warning caused by the DMA request */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - kSAI_FIFORequestDMAEnable = I2S_TCSR_FRDE_MASK, /*!< FIFO request caused by the DMA request */ -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ -}; - -/*! @brief The SAI status flag */ -enum _sai_flags -{ - kSAI_WordStartFlag = I2S_TCSR_WSF_MASK, /*!< Word start flag, means the first word in a frame detected */ - kSAI_SyncErrorFlag = I2S_TCSR_SEF_MASK, /*!< Sync error flag, means the sync error is detected */ - kSAI_FIFOErrorFlag = I2S_TCSR_FEF_MASK, /*!< FIFO error flag */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - kSAI_FIFORequestFlag = I2S_TCSR_FRF_MASK, /*!< FIFO request flag. */ -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - kSAI_FIFOWarningFlag = I2S_TCSR_FWF_MASK, /*!< FIFO warning flag */ -}; - -/*! @brief The reset type */ -typedef enum _sai_reset_type -{ - kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */ - kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */ - kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */ -} sai_reset_type_t; - -#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING -/*! - * @brief The SAI packing mode - * The mode includes 8 bit and 16 bit packing. - */ -typedef enum _sai_fifo_packing -{ - kSAI_FifoPackingDisabled = 0x0U, /*!< Packing disabled */ - kSAI_FifoPacking8bit = 0x2U, /*!< 8 bit packing enabled */ - kSAI_FifoPacking16bit = 0x3U /*!< 16bit packing enabled */ -} sai_fifo_packing_t; -#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ - -/*! @brief SAI user configuration structure */ -typedef struct _sai_config -{ - sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ - sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */ -#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */ -#endif /* FSL_FEATURE_SAI_HAS_MCR */ - sai_mclk_source_t mclkSource; /*!< Master Clock source */ - sai_bclk_source_t bclkSource; /*!< Bit Clock source */ - sai_master_slave_t masterSlave; /*!< Master or slave */ -} sai_config_t; - -/*!@brief SAI transfer queue size, user can refine it according to use case. */ -#define SAI_XFER_QUEUE_SIZE (4) - -/*! @brief Audio sample rate */ -typedef enum _sai_sample_rate -{ - kSAI_SampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */ - kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ - kSAI_SampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */ - kSAI_SampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */ - kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ - kSAI_SampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */ - kSAI_SampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ - kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ - kSAI_SampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ - kSAI_SampleRate96KHz = 96000U /*!< Sample rate 96000 Hz */ -} sai_sample_rate_t; - -/*! @brief Audio word width */ -typedef enum _sai_word_width -{ - kSAI_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ - kSAI_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ - kSAI_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ - kSAI_WordWidth32bits = 32U /*!< Audio data width 32 bits */ -} sai_word_width_t; - -/*! @brief sai transfer format */ -typedef struct _sai_transfer_format -{ - uint32_t sampleRate_Hz; /*!< Sample rate of audio data */ - uint32_t bitWidth; /*!< Data length of audio data, usually 8/16/24/32 bits */ - sai_mono_stereo_t stereo; /*!< Mono or stereo */ - uint32_t masterClockHz; /*!< Master clock frequency in Hz */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - uint8_t watermark; /*!< Watermark value */ -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - uint8_t channel; /*!< Data channel used in transfer.*/ - sai_protocol_t protocol; /*!< Which audio protocol used */ - bool isFrameSyncCompact; /*!< True means Frame sync length is configurable according to bitWidth, false means frame - sync length is 64 times of bit clock. */ -} sai_transfer_format_t; - -/*! @brief SAI transfer structure */ -typedef struct _sai_transfer -{ - uint8_t *data; /*!< Data start address to transfer. */ - size_t dataSize; /*!< Transfer size. */ -} sai_transfer_t; - -typedef struct _sai_handle sai_handle_t; - -/*! @brief SAI transfer callback prototype */ -typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData); - -/*! @brief SAI handle structure */ -struct _sai_handle -{ - uint32_t state; /*!< Transfer status */ - sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/ - void *userData; /*!< Callback parameter passed to callback function*/ - uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32 bits */ - uint8_t channel; /*!< Transfer channel */ - sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ - size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ - volatile uint8_t queueUser; /*!< Index for user to queue transfer */ - volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - uint8_t watermark; /*!< Watermark value */ -#endif -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the SAI Tx peripheral. - * - * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. - * The configuration structure can be custom filled or set with default values by - * SAI_TxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault - * because the clock is not enabled. - * - * @param base SAI base pointer - * @param config SAI configuration structure. -*/ -void SAI_TxInit(I2S_Type *base, const sai_config_t *config); - -/*! - * @brief Initializes the SAI Rx peripheral. - * - * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. - * The configuration structure can be custom filled or set with default values by - * SAI_RxGetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault - * because the clock is not enabled. - * - * @param base SAI base pointer - * @param config SAI configuration structure. - */ -void SAI_RxInit(I2S_Type *base, const sai_config_t *config); - -/*! - * @brief Sets the SAI Tx configuration structure to default values. - * - * This API initializes the configuration structure for use in SAI_TxConfig(). - * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified - * before calling SAI_TxConfig(). - * This is an example. - @code - sai_config_t config; - SAI_TxGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master configuration structure - */ -void SAI_TxGetDefaultConfig(sai_config_t *config); - -/*! - * @brief Sets the SAI Rx configuration structure to default values. - * - * This API initializes the configuration structure for use in SAI_RxConfig(). - * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified - * before calling SAI_RxConfig(). - * This is an example. - @code - sai_config_t config; - SAI_RxGetDefaultConfig(&config); - @endcode - * - * @param config pointer to master configuration structure - */ -void SAI_RxGetDefaultConfig(sai_config_t *config); - -/*! - * @brief De-initializes the SAI peripheral. - * - * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit - * or SAI_RxInit is called to enable the clock. - * - * @param base SAI base pointer -*/ -void SAI_Deinit(I2S_Type *base); - -/*! - * @brief Resets the SAI Tx. - * - * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. - * - * @param base SAI base pointer - */ -void SAI_TxReset(I2S_Type *base); - -/*! - * @brief Resets the SAI Rx. - * - * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. - * - * @param base SAI base pointer - */ -void SAI_RxReset(I2S_Type *base); - -/*! - * @brief Enables/disables the SAI Tx. - * - * @param base SAI base pointer - * @param enable True means enable SAI Tx, false means disable. - */ -void SAI_TxEnable(I2S_Type *base, bool enable); - -/*! - * @brief Enables/disables the SAI Rx. - * - * @param base SAI base pointer - * @param enable True means enable SAI Rx, false means disable. - */ -void SAI_RxEnable(I2S_Type *base, bool enable); - -/*! @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the SAI Tx status flag state. - * - * @param base SAI base pointer - * @return SAI Tx status flag value. Use the Status Mask to get the status value needed. - */ -static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base) -{ - return base->TCSR; -} - -/*! - * @brief Clears the SAI Tx status flag state. - * - * @param base SAI base pointer - * @param mask State mask. It can be a combination of the following source if defined: - * @arg kSAI_WordStartFlag - * @arg kSAI_SyncErrorFlag - * @arg kSAI_FIFOErrorFlag - */ -static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask) -{ - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); -} - -/*! - * @brief Gets the SAI Tx status flag state. - * - * @param base SAI base pointer - * @return SAI Rx status flag value. Use the Status Mask to get the status value needed. - */ -static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base) -{ - return base->RCSR; -} - -/*! - * @brief Clears the SAI Rx status flag state. - * - * @param base SAI base pointer - * @param mask State mask. It can be a combination of the following sources if defined. - * @arg kSAI_WordStartFlag - * @arg kSAI_SyncErrorFlag - * @arg kSAI_FIFOErrorFlag - */ -static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask) -{ - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); -} - -/*! - * @brief Do software reset or FIFO reset . - * - * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. - * Software reset means claer the Tx internal logic, including the bit clock, frame count etc. But software - * reset will not clear any configuration registers like TCR1~TCR5. - * This function will also clear all the error flags such as FIFO error, sync error etc. - * - * @param base SAI base pointer - * @param type Reset type, FIFO reset or software reset - */ -void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type); - -/*! - * @brief Do software reset or FIFO reset . - * - * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. - * Software reset means claer the Rx internal logic, including the bit clock, frame count etc. But software - * reset will not clear any configuration registers like RCR1~RCR5. - * This function will also clear all the error flags such as FIFO error, sync error etc. - * - * @param base SAI base pointer - * @param type Reset type, FIFO reset or software reset - */ -void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type); - -/*! - * @brief Set the Tx channel FIFO enable mask. - * - * @param base SAI base pointer - * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, - * 3 means both channel 0 and channel 1 enabled. - */ -void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); - -/*! - * @brief Set the Rx channel FIFO enable mask. - * - * @param base SAI base pointer - * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, - * 3 means both channel 0 and channel 1 enabled. - */ -void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); - -/*! - * @brief Set the Tx data order. - * - * @param base SAI base pointer - * @param order Data order MSB or LSB - */ -void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order); - -/*! - * @brief Set the Rx data order. - * - * @param base SAI base pointer - * @param order Data order MSB or LSB - */ -void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order); - -/*! - * @brief Set the Tx data order. - * - * @param base SAI base pointer - * @param order Data order MSB or LSB - */ -void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); - -/*! - * @brief Set the Rx data order. - * - * @param base SAI base pointer - * @param order Data order MSB or LSB - */ -void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); - -/*! - * @brief Set the Tx data order. - * - * @param base SAI base pointer - * @param order Data order MSB or LSB - */ -void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); - -/*! - * @brief Set the Rx data order. - * - * @param base SAI base pointer - * @param order Data order MSB or LSB - */ -void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); - -#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING -/*! - * @brief Set Tx FIFO packing feature. - * - * @param base SAI base pointer. - * @param pack FIFO pack type. It is element of sai_fifo_packing_t. - */ -void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); - -/*! -* @brief Set Rx FIFO packing feature. -* -* @param base SAI base pointer. -* @param pack FIFO pack type. It is element of sai_fifo_packing_t. -*/ -void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); -#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ - -#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR -/*! -* @brief Set Tx FIFO error continue. -* -* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature -* not enabled, SAI will hang and users need to clear FEF flag in TCSR register. -* -* @param base SAI base pointer. -* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. -*/ -static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) -{ - if (isEnabled) - { - base->TCR4 |= I2S_TCR4_FCONT_MASK; - } - else - { - base->TCR4 &= ~I2S_TCR4_FCONT_MASK; - } -} - -/*! -* @brief Set Rx FIFO error continue. -* -* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature -* not enabled, SAI will hang and users need to clear FEF flag in RCSR register. -* -* @param base SAI base pointer. -* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. -*/ -static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) -{ - if (isEnabled) - { - base->RCR4 |= I2S_RCR4_FCONT_MASK; - } - else - { - base->RCR4 &= ~I2S_RCR4_FCONT_MASK; - } -} -#endif -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the SAI Tx interrupt requests. - * - * @param base SAI base pointer - * @param mask interrupt source - * The parameter can be a combination of the following sources if defined. - * @arg kSAI_WordStartInterruptEnable - * @arg kSAI_SyncErrorInterruptEnable - * @arg kSAI_FIFOWarningInterruptEnable - * @arg kSAI_FIFORequestInterruptEnable - * @arg kSAI_FIFOErrorInterruptEnable - */ -static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask) -{ - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); -} - -/*! - * @brief Enables the SAI Rx interrupt requests. - * - * @param base SAI base pointer - * @param mask interrupt source - * The parameter can be a combination of the following sources if defined. - * @arg kSAI_WordStartInterruptEnable - * @arg kSAI_SyncErrorInterruptEnable - * @arg kSAI_FIFOWarningInterruptEnable - * @arg kSAI_FIFORequestInterruptEnable - * @arg kSAI_FIFOErrorInterruptEnable - */ -static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask) -{ - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); -} - -/*! - * @brief Disables the SAI Tx interrupt requests. - * - * @param base SAI base pointer - * @param mask interrupt source - * The parameter can be a combination of the following sources if defined. - * @arg kSAI_WordStartInterruptEnable - * @arg kSAI_SyncErrorInterruptEnable - * @arg kSAI_FIFOWarningInterruptEnable - * @arg kSAI_FIFORequestInterruptEnable - * @arg kSAI_FIFOErrorInterruptEnable - */ -static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask) -{ - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); -} - -/*! - * @brief Disables the SAI Rx interrupt requests. - * - * @param base SAI base pointer - * @param mask interrupt source - * The parameter can be a combination of the following sources if defined. - * @arg kSAI_WordStartInterruptEnable - * @arg kSAI_SyncErrorInterruptEnable - * @arg kSAI_FIFOWarningInterruptEnable - * @arg kSAI_FIFORequestInterruptEnable - * @arg kSAI_FIFOErrorInterruptEnable - */ -static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask) -{ - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); -} - -/*! @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables/disables the SAI Tx DMA requests. - * @param base SAI base pointer - * @param mask DMA source - * The parameter can be combination of the following sources if defined. - * @arg kSAI_FIFOWarningDMAEnable - * @arg kSAI_FIFORequestDMAEnable - * @param enable True means enable DMA, false means disable DMA. - */ -static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) -{ - if (enable) - { - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); - } - else - { - base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); - } -} - -/*! - * @brief Enables/disables the SAI Rx DMA requests. - * @param base SAI base pointer - * @param mask DMA source - * The parameter can be a combination of the following sources if defined. - * @arg kSAI_FIFOWarningDMAEnable - * @arg kSAI_FIFORequestDMAEnable - * @param enable True means enable DMA, false means disable DMA. - */ -static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) -{ - if (enable) - { - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); - } - else - { - base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); - } -} - -/*! - * @brief Gets the SAI Tx data register address. - * - * This API is used to provide a transfer address for the SAI DMA transfer configuration. - * - * @param base SAI base pointer. - * @param channel Which data channel used. - * @return data register address. - */ -static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) -{ - return (uint32_t)(&(base->TDR)[channel]); -} - -/*! - * @brief Gets the SAI Rx data register address. - * - * This API is used to provide a transfer address for the SAI DMA transfer configuration. - * - * @param base SAI base pointer. - * @param channel Which data channel used. - * @return data register address. - */ -static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) -{ - return (uint32_t)(&(base->RDR)[channel]); -} - -/*! @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Configures the SAI Tx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param format Pointer to the SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master - * clock, this value should equal the masterClockHz. -*/ -void SAI_TxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Configures the SAI Rx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param format Pointer to the SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master - * clock, this value should equal the masterClockHz. -*/ -void SAI_RxSetFormat(I2S_Type *base, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Sends data using a blocking method. - * - * @note This function blocks by polling until data is ready to be sent. - * - * @param base SAI base pointer. - * @param channel Data channel used. - * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. - * @param buffer Pointer to the data to be written. - * @param size Bytes to be written. - */ -void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); - -/*! - * @brief Writes data into SAI FIFO. - * - * @param base SAI base pointer. - * @param channel Data channel used. - * @param data Data needs to be written. - */ -static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data) -{ - base->TDR[channel] = data; -} - -/*! - * @brief Receives data using a blocking method. - * - * @note This function blocks by polling until data is ready to be sent. - * - * @param base SAI base pointer. - * @param channel Data channel used. - * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. - * @param buffer Pointer to the data to be read. - * @param size Bytes to be read. - */ -void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); - -/*! - * @brief Reads data from the SAI FIFO. - * - * @param base SAI base pointer. - * @param channel Data channel used. - * @return Data in SAI FIFO. - */ -static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel) -{ - return base->RDR[channel]; -} - -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the SAI Tx handle. - * - * This function initializes the Tx handle for the SAI Tx transactional APIs. Call - * this function once to get the handle initialized. - * - * @param base SAI base pointer - * @param handle SAI handle pointer. - * @param callback Pointer to the user callback function. - * @param userData User parameter passed to the callback function - */ -void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); - -/*! - * @brief Initializes the SAI Rx handle. - * - * This function initializes the Rx handle for the SAI Rx transactional APIs. Call - * this function once to get the handle initialized. - * - * @param base SAI base pointer. - * @param handle SAI handle pointer. - * @param callback Pointer to the user callback function. - * @param userData User parameter passed to the callback function. - */ -void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); - -/*! - * @brief Configures the SAI Tx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param handle SAI handle pointer. - * @param format Pointer to the SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master - * clock, this value should equal the masterClockHz in format. - * @return Status of this function. Return value is the status_t. -*/ -status_t SAI_TransferTxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Configures the SAI Rx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SAI base pointer. - * @param handle SAI handle pointer. - * @param format Pointer to the SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master - * clock, this value should equal the masterClockHz in format. - * @return Status of this function. Return value is one of status_t. -*/ -status_t SAI_TransferRxSetFormat(I2S_Type *base, - sai_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Performs an interrupt non-blocking send transfer on SAI. - * - * @note This API returns immediately after the transfer initiates. - * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether - * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer - * is finished. - * - * @param base SAI base pointer. - * @param handle Pointer to the sai_handle_t structure which stores the transfer state. - * @param xfer Pointer to the sai_transfer_t structure. - * @retval kStatus_Success Successfully started the data receive. - * @retval kStatus_SAI_TxBusy Previous receive still not finished. - * @retval kStatus_InvalidArgument The input parameter is invalid. - */ -status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); - -/*! - * @brief Performs an interrupt non-blocking receive transfer on SAI. - * - * @note This API returns immediately after the transfer initiates. - * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether - * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer - * is finished. - * - * @param base SAI base pointer - * @param handle Pointer to the sai_handle_t structure which stores the transfer state. - * @param xfer Pointer to the sai_transfer_t structure. - * @retval kStatus_Success Successfully started the data receive. - * @retval kStatus_SAI_RxBusy Previous receive still not finished. - * @retval kStatus_InvalidArgument The input parameter is invalid. - */ -status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); - -/*! - * @brief Gets a set byte count. - * - * @param base SAI base pointer. - * @param handle Pointer to the sai_handle_t structure which stores the transfer state. - * @param count Bytes count sent. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count); - -/*! - * @brief Gets a received byte count. - * - * @param base SAI base pointer. - * @param handle Pointer to the sai_handle_t structure which stores the transfer state. - * @param count Bytes count received. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count); - -/*! - * @brief Aborts the current send. - * - * @note This API can be called any time when an interrupt non-blocking transfer initiates - * to abort the transfer early. - * - * @param base SAI base pointer. - * @param handle Pointer to the sai_handle_t structure which stores the transfer state. - */ -void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle); - -/*! - * @brief Aborts the current IRQ receive. - * - * @note This API can be called when an interrupt non-blocking transfer initiates - * to abort the transfer early. - * - * @param base SAI base pointer - * @param handle Pointer to the sai_handle_t structure which stores the transfer state. - */ -void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle); - -/*! - * @brief Terminate all SAI send. - * - * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the - * current transfer slot, please call SAI_TransferAbortSend. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - */ -void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle); - -/*! - * @brief Terminate all SAI receive. - * - * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the - * current transfer slot, please call SAI_TransferAbortReceive. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - */ -void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle); - -/*! - * @brief Tx interrupt handler. - * - * @param base SAI base pointer. - * @param handle Pointer to the sai_handle_t structure. - */ -void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle); - -/*! - * @brief Tx interrupt handler. - * - * @param base SAI base pointer. - * @param handle Pointer to the sai_handle_t structure. - */ -void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle); - -/*! @} */ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ - -/*! @} */ - -#endif /* _FSL_SAI_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_sai_edma.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_sai_edma.c deleted file mode 100644 index 0d9ec7b39f..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_sai_edma.c +++ /dev/null @@ -1,509 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_sai_edma.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.sai_edma" -#endif - -/******************************************************************************* - * Definitations - ******************************************************************************/ -/* Used for 32byte aligned */ -#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU) - -static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; - -/*handle; - - /* If finished a blcok, call the callback function */ - saiHandle->saiQueue[saiHandle->queueDriver].dataSize = 0; - if (saiHandle->callback) - { - (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_TxIdle, saiHandle->userData); - } - saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; - - /* If all data finished, just stop the transfer */ - if (saiHandle->saiQueue[saiHandle->queueDriver].dataSize == 0) - { - /* Disable DMA enable bit */ - SAI_TxEnableDMA(privHandle->base, kSAI_FIFORequestDMAEnable, false); - EDMA_AbortTransfer(handle); - } -} - -static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) -{ - sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData; - sai_edma_handle_t *saiHandle = privHandle->handle; - - /* If finished a blcok, call the callback function */ - memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); - saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; - if (saiHandle->callback) - { - (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_RxIdle, saiHandle->userData); - } - - /* If all data finished, just stop the transfer */ - if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) - { - /* Disable DMA enable bit */ - SAI_RxEnableDMA(privHandle->base, kSAI_FIFORequestDMAEnable, false); - EDMA_AbortTransfer(handle); - } -} - -void SAI_TransferTxCreateHandleEDMA( - I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) -{ - assert(handle && dmaHandle); - - uint32_t instance = SAI_GetInstance(base); - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - /* Set sai base to handle */ - handle->dmaHandle = dmaHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set SAI state to idle */ - handle->state = kSAI_Idle; - - s_edmaPrivateHandle[instance][0].base = base; - s_edmaPrivateHandle[instance][0].handle = handle; - - /* Need to use scatter gather */ - EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); - - /* Install callback for Tx dma channel */ - EDMA_SetCallback(dmaHandle, SAI_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); -} - -void SAI_TransferRxCreateHandleEDMA( - I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) -{ - assert(handle && dmaHandle); - - uint32_t instance = SAI_GetInstance(base); - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - /* Set sai base to handle */ - handle->dmaHandle = dmaHandle; - handle->callback = callback; - handle->userData = userData; - - /* Set SAI state to idle */ - handle->state = kSAI_Idle; - - s_edmaPrivateHandle[instance][1].base = base; - s_edmaPrivateHandle[instance][1].handle = handle; - - /* Need to use scatter gather */ - EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); - - /* Install callback for Tx dma channel */ - EDMA_SetCallback(dmaHandle, SAI_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); -} - -void SAI_TransferTxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(handle && format); - - /* Configure the audio format to SAI registers */ - SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - /* Get the tranfer size from format, this should be used in EDMA configuration */ - if (format->bitWidth == 24U) - { - handle->bytesPerFrame = 4U; - } - else - { - handle->bytesPerFrame = format->bitWidth / 8U; - } - - /* Update the data channel SAI used */ - handle->channel = format->channel; - - /* Clear the channel enable bits unitl do a send/receive */ - base->TCR3 &= ~I2S_TCR3_TCE_MASK; -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - handle->count = FSL_FEATURE_SAI_FIFO_COUNT - format->watermark; -#else - handle->count = 1U; -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ -} - -void SAI_TransferRxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz) -{ - assert(handle && format); - - /* Configure the audio format to SAI registers */ - SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - - /* Get the tranfer size from format, this should be used in EDMA configuration */ - if (format->bitWidth == 24U) - { - handle->bytesPerFrame = 4U; - } - else - { - handle->bytesPerFrame = format->bitWidth / 8U; - } - - /* Update the data channel SAI used */ - handle->channel = format->channel; - - /* Clear the channel enable bits unitl do a send/receive */ - base->RCR3 &= ~I2S_RCR3_RCE_MASK; -#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) - handle->count = format->watermark; -#else - handle->count = 1U; -#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ -} - -status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) -{ - assert(handle && xfer); - - edma_transfer_config_t config = {0}; - uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); - - /* Check if input parameter invalid */ - if ((xfer->data == NULL) || (xfer->dataSize == 0U)) - { - return kStatus_InvalidArgument; - } - - if (handle->saiQueue[handle->queueUser].dataSize) - { - return kStatus_SAI_QueueFull; - } - - /* Change the state of handle */ - handle->state = kSAI_Busy; - - /* Update the queue state */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->saiQueue[handle->queueUser].data = xfer->data; - handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; - - /* Prepare edma configure */ - EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame, - handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_MemoryToPeripheral); - - /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ - handle->nbytes = handle->count * handle->bytesPerFrame; - - EDMA_SubmitTransfer(handle->dmaHandle, &config); - - /* Start DMA transfer */ - EDMA_StartTransfer(handle->dmaHandle); - - /* Enable DMA enable bit */ - SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); - - /* Enable SAI Tx clock */ - SAI_TxEnable(base, true); - - /* Enable the channel FIFO */ - base->TCR3 |= I2S_TCR3_TCE(1U << handle->channel); - - return kStatus_Success; -} - -status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) -{ - assert(handle && xfer); - - edma_transfer_config_t config = {0}; - uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); - - /* Check if input parameter invalid */ - if ((xfer->data == NULL) || (xfer->dataSize == 0U)) - { - return kStatus_InvalidArgument; - } - - if (handle->saiQueue[handle->queueUser].data) - { - return kStatus_SAI_QueueFull; - } - - /* Change the state of handle */ - handle->state = kSAI_Busy; - - /* Update queue state */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->saiQueue[handle->queueUser].data = xfer->data; - handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; - - /* Prepare edma configure */ - EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame, - handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory); - - /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ - handle->nbytes = handle->count * handle->bytesPerFrame; - - EDMA_SubmitTransfer(handle->dmaHandle, &config); - - /* Start DMA transfer */ - EDMA_StartTransfer(handle->dmaHandle); - - /* Enable DMA enable bit */ - SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); - - /* Enable the channel FIFO */ - base->RCR3 |= I2S_RCR3_RCE(1U << handle->channel); - - /* Enable SAI Rx clock */ - SAI_RxEnable(base, true); - - return kStatus_Success; -} - -void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) -{ - assert(handle); - - /* Disable dma */ - EDMA_AbortTransfer(handle->dmaHandle); - - /* Disable the channel FIFO */ - base->TCR3 &= ~I2S_TCR3_TCE_MASK; - - /* Disable DMA enable bit */ - SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); - - /* Disable Tx */ - SAI_TxEnable(base, false); - - /* Reset the FIFO pointer, at the same time clear all error flags if set */ - base->TCSR |= (I2S_TCSR_FR_MASK | I2S_TCSR_SR_MASK); - base->TCSR &= ~I2S_TCSR_SR_MASK; - - /* Handle the queue index */ - memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); - handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; - - /* Set the handle state */ - handle->state = kSAI_Idle; -} - -void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) -{ - assert(handle); - - /* Disable dma */ - EDMA_AbortTransfer(handle->dmaHandle); - - /* Disable the channel FIFO */ - base->RCR3 &= ~I2S_RCR3_RCE_MASK; - - /* Disable DMA enable bit */ - SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); - - /* Disable Rx */ - SAI_RxEnable(base, false); - - /* Reset the FIFO pointer, at the same time clear all error flags if set */ - base->RCSR |= (I2S_RCSR_FR_MASK | I2S_RCSR_SR_MASK); - base->RCSR &= ~I2S_RCSR_SR_MASK; - - /* Handle the queue index */ - memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); - handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; - - /* Set the handle state */ - handle->state = kSAI_Idle; -} - -void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) -{ - assert(handle); - - /* Abort the current transfer */ - SAI_TransferAbortSendEDMA(base, handle); - - /* Clear all the internal information */ - memset(handle->tcd, 0U, sizeof(handle->tcd)); - memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); - memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; - handle->queueDriver = 0U; -} - -void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) -{ - assert(handle); - - /* Abort the current transfer */ - SAI_TransferAbortReceiveEDMA(base, handle); - - /* Clear all the internal information */ - memset(handle->tcd, 0U, sizeof(handle->tcd)); - memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); - memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; - handle->queueDriver = 0U; -} - -status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSAI_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); - } - - return status; -} - -status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSAI_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); - } - - return status; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_sai_edma.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_sai_edma.h deleted file mode 100644 index 0b806d246b..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_sai_edma.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SAI_EDMA_H_ -#define _FSL_SAI_EDMA_H_ - -#include "fsl_sai.h" -#include "fsl_edma.h" - -/*! - * @addtogroup sai_edma - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4 */ -/*@}*/ - -typedef struct _sai_edma_handle sai_edma_handle_t; - -/*! @brief SAI eDMA transfer callback function for finish and error */ -typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData); - -/*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/ -struct _sai_edma_handle -{ - edma_handle_t *dmaHandle; /*!< DMA handler for SAI send */ - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - uint8_t bytesPerFrame; /*!< Bytes in a frame */ - uint8_t channel; /*!< Which data channel */ - uint8_t count; /*!< The transfer data count in a DMA request */ - uint32_t state; /*!< Internal state for SAI eDMA transfer */ - sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ - void *userData; /*!< User callback parameter */ - uint8_t tcd[(SAI_XFER_QUEUE_SIZE + 1U) * sizeof(edma_tcd_t)]; /*!< TCD pool for eDMA transfer. */ - sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ - size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ - volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ - volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name eDMA Transactional - * @{ - */ - -/*! - * @brief Initializes the SAI eDMA handle. - * - * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. - * Usually, for a specified SAI instance, call this API once to get the initialized handle. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param base SAI peripheral base address. - * @param callback Pointer to user callback function. - * @param userData User parameter passed to the callback function. - * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. - */ -void SAI_TransferTxCreateHandleEDMA( - I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); - -/*! - * @brief Initializes the SAI Rx eDMA handle. - * - * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. - * Usually, for a specified SAI instance, call this API once to get the initialized handle. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param base SAI peripheral base address. - * @param callback Pointer to user callback function. - * @param userData User parameter passed to the callback function. - * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. - */ -void SAI_TransferRxCreateHandleEDMA( - I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); - -/*! - * @brief Configures the SAI Tx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param format Pointer to SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master - * clock, this value should equals to masterClockHz in format. - * @retval kStatus_Success Audio format set successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. -*/ -void SAI_TransferTxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Configures the SAI Rx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param format Pointer to SAI audio data format structure. - * @param mclkSourceClockHz SAI master clock source frequency in Hz. - * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master - * clock, this value should equal to masterClockHz in format. - * @retval kStatus_Success Audio format set successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. -*/ -void SAI_TransferRxSetFormatEDMA(I2S_Type *base, - sai_edma_handle_t *handle, - sai_transfer_format_t *format, - uint32_t mclkSourceClockHz, - uint32_t bclkSourceClockHz); - -/*! - * @brief Performs a non-blocking SAI transfer using DMA. - * - * @note This interface returns immediately after the transfer initiates. Call - * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param xfer Pointer to the DMA transfer structure. - * @retval kStatus_Success Start a SAI eDMA send successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. - * @retval kStatus_TxBusy SAI is busy sending data. - */ -status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SAI receive using eDMA. - * - * @note This interface returns immediately after the transfer initiates. Call - * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. - * - * @param base SAI base pointer - * @param handle SAI eDMA handle pointer. - * @param xfer Pointer to DMA transfer structure. - * @retval kStatus_Success Start a SAI eDMA receive successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. - * @retval kStatus_RxBusy SAI is busy receiving data. - */ -status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); - -/*! - * @brief Terminate all SAI send. - * - * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the - * current transfer slot, please call SAI_TransferAbortSendEDMA. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - */ -void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle); - -/*! - * @brief Terminate all SAI receive. - * - * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the - * current transfer slot, please call SAI_TransferAbortReceiveEDMA. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - */ -void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle); - -/*! - * @brief Aborts a SAI transfer using eDMA. - * - * This function only aborts the current transfer slots, the other transfer slots' information still kept - * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - */ -void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle); - -/*! - * @brief Aborts a SAI receive using eDMA. - * - * This function only aborts the current transfer slots, the other transfer slots' information still kept - * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA. - * - * @param base SAI base pointer - * @param handle SAI eDMA handle pointer. - */ -void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle); - -/*! - * @brief Gets byte count sent by SAI. - * - * @param base SAI base pointer. - * @param handle SAI eDMA handle pointer. - * @param count Bytes count sent by SAI. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. - */ -status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); - -/*! - * @brief Gets byte count received by SAI. - * - * @param base SAI base pointer - * @param handle SAI eDMA handle pointer. - * @param count Bytes count received by SAI. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. - */ -status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_semc.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_semc.c deleted file mode 100644 index 31dbe76495..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_semc.c +++ /dev/null @@ -1,986 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_semc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.semc" -#endif - - -/*! @brief Define macros for SEMC driver. */ -#define SEMC_IPCOMMANDDATASIZEBYTEMAX (4U) -#define SEMC_IPCOMMANDMAGICKEY (0xA55A) -#define SEMC_IOCR_PINMUXBITWIDTH (0x3U) -#define SEMC_IOCR_NAND_CE (4U) -#define SEMC_IOCR_NOR_CE (5U) -#define SEMC_IOCR_NOR_CE_A8 (2U) -#define SEMC_IOCR_PSRAM_CE (6U) -#define SEMC_IOCR_PSRAM_CE_A8 (3U) -#define SEMC_IOCR_DBI_CSX (7U) -#define SEMC_IOCR_DBI_CSX_A8 (4U) -#define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE (24U) -#define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX (28U) -#define SEMC_BMCR0_TYPICAL_WQOS (5U) -#define SEMC_BMCR0_TYPICAL_WAGE (8U) -#define SEMC_BMCR0_TYPICAL_WSH (0x40U) -#define SEMC_BMCR0_TYPICAL_WRWS (0x10U) -#define SEMC_BMCR1_TYPICAL_WQOS (5U) -#define SEMC_BMCR1_TYPICAL_WAGE (8U) -#define SEMC_BMCR1_TYPICAL_WPH (0x60U) -#define SEMC_BMCR1_TYPICAL_WBR (0x40U) -#define SEMC_BMCR1_TYPICAL_WRWS (0x24U) -#define SEMC_STARTADDRESS (0x80000000U) -#define SEMC_ENDADDRESS (0xDFFFFFFFU) -#define SEMC_BR_MEMSIZE_MIN (4) -#define SEMC_BR_MEMSIZE_OFFSET (2) -#define SEMC_BR_MEMSIZE_MAX (4 * 1024 * 1024) -#define SEMC_SDRAM_MODESETCAL_OFFSET (4) -#define SEMC_BR_REG_NUM (9) -#define SEMC_BYTE_NUMBIT (8) -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for SEMC module. - * - * @param base SEMC peripheral base address - */ -static uint32_t SEMC_GetInstance(SEMC_Type *base); - -/*! - * @brief Covert the input memory size to internal register set value. - * - * @param base SEMC peripheral base address - * @param size_kbytes SEMC memory size in unit of kbytes. - * @param sizeConverted SEMC converted memory size to 0 ~ 0x1F. - * @return Execution status. - */ -static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted); - -/*! - * @brief Covert the external timing nanosecond to internal clock cycle. - * - * @param time_ns SEMC external time interval in unit of nanosecond. - * @param clkSrc_Hz SEMC clock source frequency. - * @return The changed internal clock cycle. - */ -static uint8_t SEMC_ConvertTiming(uint32_t time_ns, uint32_t clkSrc_Hz); - -/*! - * @brief Configure IP command. - * - * @param base SEMC peripheral base address. - * @param size_bytes SEMC IP command data size. - * @return Execution status. - */ -static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes); - -/*! - * @brief Check if the IP command has finished. - * - * @param base SEMC peripheral base address. - * @return Execution status. - */ -static status_t SEMC_IsIPCommandDone(SEMC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to SEMC clocks for each instance. */ -static const clock_ip_name_t s_semcClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_CLOCKS; -static const clock_ip_name_t s_semcExtClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_EXSC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/*! @brief Pointers to SEMC bases for each instance. */ -static SEMC_Type *const s_semcBases[] = SEMC_BASE_PTRS; -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t SEMC_GetInstance(SEMC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_semcBases); instance++) - { - if (s_semcBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_semcBases)); - - return instance; -} - -static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted) -{ - assert(sizeConverted); - uint32_t memsize; - - if ((size_kbytes < SEMC_BR_MEMSIZE_MIN) || (size_kbytes > SEMC_BR_MEMSIZE_MAX)) - { - return kStatus_SEMC_InvalidMemorySize; - } - - *sizeConverted = 0; - memsize = size_kbytes / 8; - while (memsize) - { - memsize >>= 1; - (*sizeConverted)++; - } - return kStatus_Success; -} - -static uint8_t SEMC_ConvertTiming(uint32_t time_ns, uint32_t clkSrc_Hz) -{ - assert(clkSrc_Hz); - - uint8_t clockCycles = 0; - uint32_t tClk_us; - - clkSrc_Hz /= 1000000; - tClk_us = 1000000 / clkSrc_Hz; - - while (tClk_us * clockCycles < (time_ns * 1000)) - { - clockCycles++; - } - - return clockCycles; -} - -static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes) -{ - if ((size_bytes > SEMC_IPCOMMANDDATASIZEBYTEMAX) || (!size_bytes)) - { - return kStatus_SEMC_InvalidIpcmdDataSize; - } - - /* Set data size. */ - /* Note: It is better to set data size as the device data port width when transfering - * device command data. but for device memory data transfer, it can be set freely. - * Note: If the data size is greater than data port width, for example, datsz = 4, data port = 16bit, - * then the 4-byte data transfer will be split into two 2-byte transfer, the slave address - * will be switched automatically according to connected device type*/ - base->IPCR1 = SEMC_IPCR1_DATSZ(size_bytes); - /* Clear data size. */ - base->IPCR2 = 0; - /* Set data size. */ - if (size_bytes < 4) - { - base->IPCR2 |= SEMC_IPCR2_BM3_MASK; - } - if (size_bytes < 3) - { - base->IPCR2 |= SEMC_IPCR2_BM2_MASK; - } - if (size_bytes < 2) - { - base->IPCR2 |= SEMC_IPCR2_BM1_MASK; - } - return kStatus_Success; -} - -static status_t SEMC_IsIPCommandDone(SEMC_Type *base) -{ - /* Poll status bit till command is done*/ - while (!(base->INTR & SEMC_INTR_IPCMDDONE_MASK)) - { - }; - - /* Clear status bit */ - base->INTR |= SEMC_INTR_IPCMDDONE_MASK; - - /* Check error status */ - if (base->INTR & SEMC_INTR_IPCMDERR_MASK) - { - base->INTR |= SEMC_INTR_IPCMDERR_MASK; - return kStatus_SEMC_IpCommandExecutionError; - } - - return kStatus_Success; -} - -void SEMC_GetDefaultConfig(semc_config_t *config) -{ - assert(config); - - semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */ - semc_queuea_weight_t queueaWeight; - semc_queueb_weight_t queuebWeight; - - /* Get default settings. */ - config->dqsMode = kSEMC_Loopbackinternal; - config->cmdTimeoutCycles = 0; - config->busTimeoutCycles = 0x1F; - - /* Set a typical weight settings. */ - memset((void *)&queueWeight, 0, sizeof(semc_axi_queueweight_t)); - - queueaWeight.qos = SEMC_BMCR0_TYPICAL_WQOS; - queueaWeight.aging = SEMC_BMCR0_TYPICAL_WAGE; - queueaWeight.slaveHitSwith = SEMC_BMCR0_TYPICAL_WSH; - queueaWeight.slaveHitNoswitch = SEMC_BMCR0_TYPICAL_WRWS; - queuebWeight.qos = SEMC_BMCR1_TYPICAL_WQOS; - queuebWeight.aging = SEMC_BMCR1_TYPICAL_WAGE; - queuebWeight.slaveHitSwith = SEMC_BMCR1_TYPICAL_WRWS; - queuebWeight.weightPagehit = SEMC_BMCR1_TYPICAL_WPH; - queuebWeight.bankRotation = SEMC_BMCR1_TYPICAL_WBR; - - config->queueWeight.queueaWeight = &queueaWeight; - config->queueWeight.queuebWeight = &queuebWeight; -} - -void SEMC_Init(SEMC_Type *base, semc_config_t *configure) -{ - assert(configure); - - uint8_t index = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Un-gate sdram controller clock. */ - CLOCK_EnableClock(s_semcClock[SEMC_GetInstance(base)]); - CLOCK_EnableClock(s_semcExtClock[SEMC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Initialize all BR to zero due to the default base address set. */ - for (index = 0; index < SEMC_BR_REG_NUM; index++) - { - base->BR[index] = 0; - } - - /* Software reset for SEMC internal logical . */ - base->MCR = SEMC_MCR_SWRST_MASK; - while (base->MCR & SEMC_MCR_SWRST_MASK) - { - } - - /* Configure, disable module first. */ - base->MCR |= SEMC_MCR_MDIS_MASK | SEMC_MCR_BTO(configure->busTimeoutCycles) | - SEMC_MCR_CTO(configure->cmdTimeoutCycles) | SEMC_MCR_DQSMD(configure->dqsMode); - - /* Configure Queue 0/1 for AXI bus. */ - if (configure->queueWeight.queueaWeight) - { - base->BMCR0 = (uint32_t)(configure->queueWeight.queueaWeight); - } - if (configure->queueWeight.queuebWeight) - { - base->BMCR1 = (uint32_t)(configure->queueWeight.queuebWeight); - } - /* Enable SEMC. */ - base->MCR &= ~SEMC_MCR_MDIS_MASK; -} - -void SEMC_Deinit(SEMC_Type *base) -{ - /* Disable module. Check there is no pending command before disable module. */ - while (!(base->STS0 & SEMC_STS0_IDLE_MASK)) - { - ; - } - - base->MCR |= SEMC_MCR_MDIS_MASK | SEMC_MCR_SWRST_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable SDRAM clock. */ - CLOCK_DisableClock(s_semcClock[SEMC_GetInstance(base)]); - CLOCK_DisableClock(s_semcExtClock[SEMC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz) -{ - assert(config); - assert(clkSrc_Hz); - assert(config->refreshBurstLen); - - uint8_t memsize; - status_t result = kStatus_Success; - uint16_t prescale = config->tPrescalePeriod_Ns / 16 / (1000000000 / clkSrc_Hz); - uint16_t refresh; - uint16_t urgentRef; - uint16_t idle; - uint16_t mode; - - if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) - { - return kStatus_SEMC_InvalidBaseAddress; - } - - if (config->csxPinMux == kSEMC_MUXA8) - { - return kStatus_SEMC_InvalidSwPinmuxSelection; - } - - if (prescale > 256) - { - return kStatus_SEMC_InvalidTimerSetting; - } - - refresh = config->refreshPeriod_nsPerRow / config->tPrescalePeriod_Ns; - urgentRef = config->refreshUrgThreshold / config->tPrescalePeriod_Ns; - idle = config->tIdleTimeout_Ns / config->tPrescalePeriod_Ns; - - uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->csxPinMux); - - /* Base control. */ - result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); - if (result != kStatus_Success) - { - return result; - } - - base->BR[cs] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; - base->SDRAMCR0 = SEMC_SDRAMCR0_PS(config->portSize) | SEMC_SDRAMCR0_BL(config->burstLen) | - SEMC_SDRAMCR0_COL(config->columnAddrBitNum) | SEMC_SDRAMCR0_CL(config->casLatency); - /* IOMUX setting. */ - if (cs) - { - base->IOCR = iocReg | (cs << config->csxPinMux); - } - - base->IOCR &= ~SEMC_IOCR_MUX_A8_MASK; - - /* Timing setting. */ - base->SDRAMCR1 = SEMC_SDRAMCR1_PRE2ACT(SEMC_ConvertTiming(config->tPrecharge2Act_Ns, clkSrc_Hz) - 1) | - SEMC_SDRAMCR1_ACT2RW(SEMC_ConvertTiming(config->tAct2ReadWrite_Ns, clkSrc_Hz) - 1) | - SEMC_SDRAMCR1_RFRC(SEMC_ConvertTiming(config->tRefreshRecovery_Ns, clkSrc_Hz) - 1) | - SEMC_SDRAMCR1_WRC(SEMC_ConvertTiming(config->tWriteRecovery_Ns, clkSrc_Hz) - 1) | - SEMC_SDRAMCR1_CKEOFF(SEMC_ConvertTiming(config->tCkeOff_Ns, clkSrc_Hz) - 1) | - SEMC_SDRAMCR1_ACT2PRE(SEMC_ConvertTiming(config->tAct2Prechage_Ns, clkSrc_Hz) - 1); - base->SDRAMCR2 = - SEMC_SDRAMCR2_SRRC(SEMC_ConvertTiming(config->tSelfRefRecovery_Ns, clkSrc_Hz) - 1) | - SEMC_SDRAMCR2_REF2REF( - SEMC_ConvertTiming(config->tRefresh2Refresh_Ns, clkSrc_Hz)) | /* No Minus one to keep with RM */ - SEMC_SDRAMCR2_ACT2ACT(SEMC_ConvertTiming(config->tAct2Act_Ns, clkSrc_Hz)) | /* No Minus one to keep with RM */ - SEMC_SDRAMCR2_ITO(idle); - base->SDRAMCR3 = SEMC_SDRAMCR3_REBL(config->refreshBurstLen - 1) | - /* N * 16 * 1s / clkSrc_Hz = config->tPrescalePeriod_Ns */ - SEMC_SDRAMCR3_PRESCALE(prescale) | SEMC_SDRAMCR3_RT(refresh) | SEMC_SDRAMCR3_UT(urgentRef); - - SEMC->IPCR1 = 0x2; - SEMC->IPCR2 = 0; - - result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_Prechargeall, 0, NULL); - if (result != kStatus_Success) - { - return result; - } - result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_AutoRefresh, 0, NULL); - if (result != kStatus_Success) - { - return result; - } - result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_AutoRefresh, 0, NULL); - if (result != kStatus_Success) - { - return result; - } - /* Mode setting value. */ - mode = (uint16_t)config->burstLen | (uint16_t)(config->casLatency << SEMC_SDRAM_MODESETCAL_OFFSET); - result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_Modeset, mode, NULL); - if (result != kStatus_Success) - { - return result; - } - /* Enables refresh */ - base->SDRAMCR3 |= SEMC_SDRAMCR3_REN_MASK; - - return kStatus_Success; -} - -status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz) -{ - assert(config); - assert(config->timingConfig); - - uint8_t memsize; - status_t result; - - if ((config->axiAddress < SEMC_STARTADDRESS) || (config->axiAddress > SEMC_ENDADDRESS)) - { - return kStatus_SEMC_InvalidBaseAddress; - } - - if (config->cePinMux == kSEMC_MUXRDY) - { - return kStatus_SEMC_InvalidSwPinmuxSelection; - } - - uint32_t iocReg = base->IOCR & ~((SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux) | SEMC_IOCR_MUX_RDY_MASK); - - /* Base control. */ - if (config->rdyactivePolarity == kSEMC_RdyActivehigh) - { - base->MCR |= SEMC_MCR_WPOL1_MASK; - } - else - { - base->MCR &= ~SEMC_MCR_WPOL1_MASK; - } - result = SEMC_CovertMemorySize(base, config->axiMemsize_kbytes, &memsize); - if (result != kStatus_Success) - { - return result; - } - base->BR[4] = (config->axiAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; - - result = SEMC_CovertMemorySize(base, config->ipgMemsize_kbytes, &memsize); - if (result != kStatus_Success) - { - return result; - } - base->BR[8] = (config->ipgAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; - - /* IOMUX setting. */ - if (config->cePinMux) - { - base->IOCR = iocReg | (SEMC_IOCR_NAND_CE << config->cePinMux); - } - else - { - base->IOCR = iocReg | (1U << config->cePinMux); - } - - base->NANDCR0 = SEMC_NANDCR0_PS(config->portSize) | SEMC_NANDCR0_BL(config->burstLen) | - SEMC_NANDCR0_EDO(config->edoModeEnabled) | SEMC_NANDCR0_COL(config->columnAddrBitNum); - - /* Timing setting. */ - base->NANDCR1 = SEMC_NANDCR1_CES(SEMC_ConvertTiming(config->timingConfig->tCeSetup_Ns, clkSrc_Hz) - 1) | - SEMC_NANDCR1_CEH(SEMC_ConvertTiming(config->timingConfig->tCeHold_Ns, clkSrc_Hz) - 1) | - SEMC_NANDCR1_WEL(SEMC_ConvertTiming(config->timingConfig->tWeLow_Ns, clkSrc_Hz) - 1) | - SEMC_NANDCR1_WEH(SEMC_ConvertTiming(config->timingConfig->tWeHigh_Ns, clkSrc_Hz) - 1) | - SEMC_NANDCR1_REL(SEMC_ConvertTiming(config->timingConfig->tReLow_Ns, clkSrc_Hz) - 1) | - SEMC_NANDCR1_REH(SEMC_ConvertTiming(config->timingConfig->tReHigh_Ns, clkSrc_Hz) - 1) | - SEMC_NANDCR1_TA(SEMC_ConvertTiming(config->timingConfig->tTurnAround_Ns, clkSrc_Hz) - 1) | - SEMC_NANDCR1_CEITV(SEMC_ConvertTiming(config->timingConfig->tCeInterval_Ns, clkSrc_Hz) - 1); - base->NANDCR2 = SEMC_NANDCR2_TWHR(SEMC_ConvertTiming(config->timingConfig->tWehigh2Relow_Ns, clkSrc_Hz) - 1) | - SEMC_NANDCR2_TRHW(SEMC_ConvertTiming(config->timingConfig->tRehigh2Welow_Ns, clkSrc_Hz) - 1) | - SEMC_NANDCR2_TADL(SEMC_ConvertTiming(config->timingConfig->tAle2WriteStart_Ns, clkSrc_Hz) - 1) | - SEMC_NANDCR2_TRR(SEMC_ConvertTiming(config->timingConfig->tReady2Relow_Ns, clkSrc_Hz) - 1) | - SEMC_NANDCR2_TWB(SEMC_ConvertTiming(config->timingConfig->tWehigh2Busy_Ns, clkSrc_Hz) - 1); - base->NANDCR3 = config->arrayAddrOption; - return kStatus_Success; -} - -status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz) -{ - assert(config); - - uint8_t memsize; - status_t result; - - if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) - { - return kStatus_SEMC_InvalidBaseAddress; - } - - uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux); - uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ? - SEMC_IOCR_NOR_CE - 1 : - ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_NOR_CE_A8 : SEMC_IOCR_NOR_CE); - - /* IOMUX setting. */ - base->IOCR = iocReg | (muxCe << config->cePinMux); - /* Address bit setting. */ - if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE) - { - if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 1) - { - /* Address bit 24 (A24) */ - base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX0_MASK; - if (config->cePinMux == kSEMC_MUXCSX0) - { - return kStatus_SEMC_InvalidSwPinmuxSelection; - } - } - if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 2) - { - /* Address bit 25 (A25) */ - base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX1_MASK; - if (config->cePinMux == kSEMC_MUXCSX1) - { - return kStatus_SEMC_InvalidSwPinmuxSelection; - } - } - if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 3) - { - /* Address bit 26 (A26) */ - base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX2_MASK; - if (config->cePinMux == kSEMC_MUXCSX2) - { - return kStatus_SEMC_InvalidSwPinmuxSelection; - } - } - if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 4) - { - if (config->addr27 == kSEMC_NORA27_MUXCSX3) - { - /* Address bit 27 (A27) */ - base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX3_MASK; - } - else if (config->addr27 == kSEMC_NORA27_MUXRDY) - { - base->IOCR |= SEMC_IOCR_MUX_RDY_MASK; - } - else - { - return kStatus_SEMC_InvalidSwPinmuxSelection; - } - if (config->cePinMux == kSEMC_MUXCSX3) - { - return kStatus_SEMC_InvalidSwPinmuxSelection; - } - } - if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX) - { - return kStatus_SEMC_InvalidAddressPortWidth; - } - } - - /* Base control. */ - if (config->rdyactivePolarity == kSEMC_RdyActivehigh) - { - base->MCR |= SEMC_MCR_WPOL0_MASK; - } - else - { - base->MCR &= ~SEMC_MCR_WPOL0_MASK; - } - result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); - if (result != kStatus_Success) - { - return result; - } - base->BR[5] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; - base->NORCR0 = SEMC_NORCR0_PS(config->portSize) | SEMC_NORCR0_BL(config->burstLen) | - SEMC_NORCR0_AM(config->addrMode) | SEMC_NORCR0_ADVP(config->advActivePolarity) | - SEMC_NORCR0_COL(config->columnAddrBitNum); - - /* Timing setting. */ - base->NORCR1 = SEMC_NORCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz)) | - SEMC_NORCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz)) | - SEMC_NORCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz)) | - SEMC_NORCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz)) | - SEMC_NORCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz)) | - SEMC_NORCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz)) | - SEMC_NORCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz)) | - SEMC_NORCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz)); - base->NORCR2 = SEMC_NORCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz)) | - SEMC_NORCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz)) | - SEMC_NORCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) | - SEMC_NORCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 1) | - SEMC_NORCR2_LC(config->latencyCount) | SEMC_NORCR2_RD(config->readCycle) | - SEMC_NORCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz)); - - return SEMC_ConfigureIPCommand(base, (config->portSize + 1)); -} - -status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz) -{ - assert(config); - - uint8_t memsize; - status_t result = kStatus_Success; - - if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) - { - return kStatus_SEMC_InvalidBaseAddress; - } - - uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux); - uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ? - SEMC_IOCR_PSRAM_CE - 1 : - ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_PSRAM_CE_A8 : SEMC_IOCR_PSRAM_CE); - - /* IOMUX setting. */ - base->IOCR = iocReg | (muxCe << config->cePinMux); - /* Address bit setting. */ - if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE) - { - if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 1) - { - /* Address bit 24 (A24) */ - base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX0_MASK; - if (config->cePinMux == kSEMC_MUXCSX0) - { - return kStatus_SEMC_InvalidSwPinmuxSelection; - } - } - if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 2) - { - /* Address bit 25 (A25) */ - base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX1_MASK; - if (config->cePinMux == kSEMC_MUXCSX1) - { - return kStatus_SEMC_InvalidSwPinmuxSelection; - } - } - if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 3) - { - /* Address bit 26 (A26) */ - base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX2_MASK; - if (config->cePinMux == kSEMC_MUXCSX2) - { - return kStatus_SEMC_InvalidSwPinmuxSelection; - } - } - if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 4) - { - if (config->addr27 == kSEMC_NORA27_MUXCSX3) - { - /* Address bit 27 (A27) */ - base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX3_MASK; - } - else if (config->addr27 == kSEMC_NORA27_MUXRDY) - { - base->IOCR |= SEMC_IOCR_MUX_RDY_MASK; - } - else - { - return kStatus_SEMC_InvalidSwPinmuxSelection; - } - - if (config->cePinMux == kSEMC_MUXCSX3) - { - return kStatus_SEMC_InvalidSwPinmuxSelection; - } - } - if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX) - { - return kStatus_SEMC_InvalidAddressPortWidth; - } - } - /* Base control. */ - result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); - if (result != kStatus_Success) - { - return result; - } - base->BR[6] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; - base->SRAMCR0 = SEMC_SRAMCR0_PS(config->portSize) | SEMC_SRAMCR0_BL(config->burstLen) | - SEMC_SRAMCR0_AM(config->addrMode) | SEMC_SRAMCR0_ADVP(config->advActivePolarity) | - SEMC_SRAMCR0_COL_MASK; - - /* Timing setting. */ - base->SRAMCR1 = SEMC_SRAMCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz)) | - SEMC_SRAMCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz)) | - SEMC_SRAMCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz)) | - SEMC_SRAMCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz)) | - SEMC_SRAMCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz)) | - SEMC_SRAMCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz)) | - SEMC_SRAMCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz)) | - SEMC_SRAMCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz)); - - base->SRAMCR2 = SEMC_SRAMCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz)) | - SEMC_SRAMCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz)) | - SEMC_SRAMCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) | - SEMC_SRAMCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 1) | - SEMC_SRAMCR2_LC(config->latencyCount) | SEMC_SRAMCR2_RD(config->readCycle) | - SEMC_SRAMCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz)); - - return result; -} - -status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz) -{ - assert(config); - - uint8_t memsize; - status_t result; - - if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) - { - return kStatus_SEMC_InvalidBaseAddress; - } - - uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->csxPinMux); - uint32_t muxCsx = (config->csxPinMux == kSEMC_MUXRDY) ? - SEMC_IOCR_DBI_CSX - 1 : - ((config->csxPinMux == kSEMC_MUXA8) ? SEMC_IOCR_DBI_CSX_A8 : SEMC_IOCR_DBI_CSX); - - /* IOMUX setting. */ - base->IOCR = iocReg | (muxCsx << config->csxPinMux); - /* Base control. */ - result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); - if (result != kStatus_Success) - { - return result; - } - base->BR[7] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; - base->DBICR0 = - SEMC_DBICR0_PS(config->portSize) | SEMC_DBICR0_BL(config->burstLen) | SEMC_DBICR0_COL(config->columnAddrBitNum); - - /* Timing setting. */ - base->DBICR1 = SEMC_DBICR1_CES(SEMC_ConvertTiming(config->tCsxSetup_Ns, clkSrc_Hz)) | - SEMC_DBICR1_CEH(SEMC_ConvertTiming(config->tCsxHold_Ns, clkSrc_Hz)) | - SEMC_DBICR1_WEL(SEMC_ConvertTiming(config->tWexLow_Ns, clkSrc_Hz)) | - SEMC_DBICR1_WEH(SEMC_ConvertTiming(config->tWexHigh_Ns, clkSrc_Hz)) | - SEMC_DBICR1_REL(SEMC_ConvertTiming(config->tRdxLow_Ns, clkSrc_Hz)) | - SEMC_DBICR1_REH(SEMC_ConvertTiming(config->tRdxHigh_Ns, clkSrc_Hz)) | - SEMC_DBICR1_CEITV(SEMC_ConvertTiming(config->tCsxInterval_Ns, clkSrc_Hz)); - return SEMC_ConfigureIPCommand(base, (config->portSize + 1)); -} - -status_t SEMC_SendIPCommand( - SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read) -{ - uint32_t cmdMode; - bool readCmd = 0; - bool writeCmd = 0; - status_t result; - - /* Clear status bit */ - base->INTR |= SEMC_INTR_IPCMDDONE_MASK; - /* Set address. */ - base->IPCR0 = address; - - /* Check command mode. */ - cmdMode = command & 0xFU; - switch (type) - { - case kSEMC_MemType_NAND: - readCmd = (cmdMode == kSEMC_NANDCM_CommandAddressRead) || - (cmdMode == kSEMC_NANDCM_CommandRead) || (cmdMode == kSEMC_NANDCM_Read); - writeCmd = (cmdMode == kSEMC_NANDCM_CommandAddressWrite) || - (cmdMode == kSEMC_NANDCM_CommandWrite) || (cmdMode == kSEMC_NANDCM_Write); - break; - case kSEMC_MemType_NOR: - case kSEMC_MemType_8080: - readCmd = (cmdMode == kSEMC_NORDBICM_Read); - writeCmd = (cmdMode == kSEMC_NORDBICM_Write); - break; - case kSEMC_MemType_SRAM: - readCmd = (cmdMode == kSEMC_SRAMCM_ArrayRead) || (cmdMode == kSEMC_SRAMCM_RegRead); - writeCmd = (cmdMode == kSEMC_SRAMCM_ArrayWrite) || (cmdMode == kSEMC_SRAMCM_RegWrite); - break; - case kSEMC_MemType_SDRAM: - readCmd = (cmdMode == kSEMC_SDRAMCM_Read); - writeCmd = (cmdMode == kSEMC_SDRAMCM_Write) || (cmdMode == kSEMC_SDRAMCM_Modeset); - break; - default: - break; - } - - if (writeCmd) - { - /* Set data. */ - base->IPTXDAT = write; - } - - /* Set command code. */ - base->IPCMD = command | SEMC_IPCMD_KEY(SEMC_IPCOMMANDMAGICKEY); - /* Wait for command done. */ - result = SEMC_IsIPCommandDone(base); - if (result != kStatus_Success) - { - return result; - } - - if (readCmd) - { - /* Get the read data */ - *read = base->IPRXDAT; - } - - return kStatus_Success; -} - -status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) -{ - assert(data); - - status_t result = kStatus_Success; - uint16_t ipCmd; - uint32_t tempData = 0; - - /* Write command built */ - ipCmd = SEMC_BuildNandIPCommand(0, kSEMC_NANDAM_ColumnRow, kSEMC_NANDCM_Write); - while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) - { - /* Configure IP command data size. */ - SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); - result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, *(uint32_t *)data, NULL); - if (result != kStatus_Success) - { - break; - } - - data += SEMC_IPCOMMANDDATASIZEBYTEMAX; - size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; - } - - if ((result == kStatus_Success) && size_bytes) - { - SEMC_ConfigureIPCommand(base, size_bytes); - - while (size_bytes) - { - tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); - size_bytes--; - } - - result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, tempData, NULL); - } - - return result; -} - -status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) -{ - assert(data); - - status_t result = kStatus_Success; - uint16_t ipCmd; - uint32_t tempData = 0; - - /* Configure IP command data size. */ - SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); - /* Read command built */ - ipCmd = SEMC_BuildNandIPCommand(0, kSEMC_NANDAM_ColumnRow, kSEMC_NANDCM_Read); - - while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) - { - result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, 0, (uint32_t *)data); - if (result != kStatus_Success) - { - break; - } - - data += SEMC_IPCOMMANDDATASIZEBYTEMAX; - size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; - } - - if ((result == kStatus_Success) && size_bytes) - { - SEMC_ConfigureIPCommand(base, size_bytes); - result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, 0, &tempData); - - while (size_bytes) - { - size_bytes--; - *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU; - } - } - - return result; -} - -status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) -{ - assert(data); - - uint32_t tempData = 0; - status_t result = kStatus_Success; - uint8_t dataSize = base->NORCR0 & SEMC_NORCR0_PS_MASK; - - /* Configure IP command data size. */ - SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); - - while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) - { - result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Read, 0, (uint32_t *)data); - if (result != kStatus_Success) - { - break; - } - - data += SEMC_IPCOMMANDDATASIZEBYTEMAX; - size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; - } - - if ((result == kStatus_Success) && size_bytes) - { - SEMC_ConfigureIPCommand(base, size_bytes); - result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Read, 0, &tempData); - while (size_bytes) - { - size_bytes--; - *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU; - } - } - - SEMC_ConfigureIPCommand(base, dataSize); - return result; -} - -status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) -{ - assert(data); - - uint32_t tempData = 0; - status_t result = kStatus_Success; - uint8_t dataSize = base->NORCR0 & SEMC_NORCR0_PS_MASK; - - /* Write command built */ - while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) - { - /* Configure IP command data size. */ - SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); - result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Write, *(uint32_t *)data, NULL); - if (result != kStatus_Success) - { - break; - } - size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; - data += SEMC_IPCOMMANDDATASIZEBYTEMAX; - } - - if ((result == kStatus_Success) && size_bytes) - { - SEMC_ConfigureIPCommand(base, size_bytes); - - while (size_bytes) - { - tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); - size_bytes--; - } - - result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Write, tempData, NULL); - } - SEMC_ConfigureIPCommand(base, dataSize); - - return result; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_semc.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_semc.h deleted file mode 100644 index a6937e12ee..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_semc.h +++ /dev/null @@ -1,807 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SEMC_H_ -#define _FSL_SEMC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup semc - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SEMC driver version 2.0.1. */ -#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! @brief SEMC status. */ -enum _semc_status -{ - kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), - kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), - kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), - kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), - kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), - kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), - kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), - kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), - kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), - kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9), - kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), - kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11), -}; - -/*! @brief SEMC memory device type. */ -typedef enum _semc_mem_type { - kSEMC_MemType_SDRAM = 0, /*!< SDRAM */ - kSEMC_MemType_SRAM, /*!< SRAM */ - kSEMC_MemType_NOR, /*!< NOR */ - kSEMC_MemType_NAND, /*!< NAND */ - kSEMC_MemType_8080 /*!< 8080. */ -} semc_mem_type_t; - -/*! @brief SEMC WAIT/RDY polarity. */ -typedef enum _semc_waitready_polarity { - kSEMC_LowActive = 0, /*!< Low active. */ - kSEMC_HighActive, /*!< High active. */ -} semc_waitready_polarity_t; - -/*! @brief SEMC SDRAM Chip selection . */ -typedef enum _semc_sdram_cs { - kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */ - kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */ - kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */ - kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */ -} semc_sdram_cs_t; - -/*! @brief SEMC NAND device type. */ -typedef enum _semc_nand_access_type { - kSEMC_NAND_ACCESS_BY_AXI = 0, - kSEMC_NAND_ACCESS_BY_IPCMD, -} semc_nand_access_type_t; - -/*! @brief SEMC interrupts . */ -typedef enum _semc_interrupt_enable { - kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */ - kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */ - kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */ - kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */ -} semc_interrupt_enable_t; - -/*! @brief SEMC IP command data size in bytes. */ -typedef enum _semc_ipcmd_datasize { - kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */ - kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */ - kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */ - kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */ -} semc_ipcmd_datasize_t; - -/*! @brief SEMC auto-refresh timing. */ -typedef enum _semc_refresh_time { - kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */ - kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */ - kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */ -} semc_refresh_time_t; - -/*! @brief CAS latency */ -typedef enum _semc_caslatency { - kSEMC_LatencyOne = 1, /*!< Latency 1. */ - kSEMC_LatencyTwo, /*!< Latency 2. */ - kSEMC_LatencyThree, /*!< Latency 3. */ -} semc_caslatency_t; - -/*! @brief SEMC sdram column address bit number. */ -typedef enum _semc_sdram_column_bit_num { - kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */ - kSEMC_SdramColunm_11bit, /*!< 11 bit. */ - kSEMC_SdramColunm_10bit, /*!< 10 bit. */ - kSEMC_SdramColunm_9bit, /*!< 9 bit. */ -} semc_sdram_column_bit_num_t; - -/*! @brief SEMC sdram burst length. */ -typedef enum _semc_sdram_burst_len { - kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/ - kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/ - kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/ - kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/ -} sem_sdram_burst_len_t; - -/*! @brief SEMC nand column address bit number. */ -typedef enum _semc_nand_column_bit_num { - kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */ - kSEMC_NandColum_15bit, /*!< 15 bit. */ - kSEMC_NandColum_14bit, /*!< 14 bit. */ - kSEMC_NandColum_13bit, /*!< 13 bit. */ - kSEMC_NandColum_12bit, /*!< 12 bit. */ - kSEMC_NandColum_11bit, /*!< 11 bit. */ - kSEMC_NandColum_10bit, /*!< 10 bit. */ - kSEMC_NandColum_9bit, /*!< 9 bit. */ -} semc_nand_column_bit_num_t; - -/*! @brief SEMC nand burst length. */ -typedef enum _semc_nand_burst_len { - kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/ - kSEMC_Nand_BurstLen2, /*!< Burst length 2*/ - kSEMC_Nand_BurstLen4, /*!< Burst length 4*/ - kSEMC_Nand_BurstLen8, /*!< Burst length 8*/ - kSEMC_Nand_BurstLen16, /*!< Burst length 16*/ - kSEMC_Nand_BurstLen32, /*!< Burst length 32*/ - kSEMC_Nand_BurstLen64 /*!< Burst length 64*/ -} sem_nand_burst_len_t; - -/*! @brief SEMC nor/sram column address bit number. */ -typedef enum _semc_norsram_column_bit_num { - kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */ - kSEMC_NorColum_11bit, /*!< 11 bit. */ - kSEMC_NorColum_10bit, /*!< 10 bit. */ - kSEMC_NorColum_9bit, /*!< 9 bit. */ - kSEMC_NorColum_8bit, /*!< 8 bit. */ - kSEMC_NorColum_7bit, /*!< 7 bit. */ - kSEMC_NorColum_6bit, /*!< 6 bit. */ - kSEMC_NorColum_5bit, /*!< 5 bit. */ - kSEMC_NorColum_4bit, /*!< 4 bit. */ - kSEMC_NorColum_3bit, /*!< 3 bit. */ - kSEMC_NorColum_2bit /*!< 2 bit. */ -} semc_norsram_column_bit_num_t; - -/*! @brief SEMC nor/sram burst length. */ -typedef enum _semc_norsram_burst_len { - kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/ - kSEMC_Nor_BurstLen2, /*!< Burst length 2*/ - kSEMC_Nor_BurstLen4, /*!< Burst length 4*/ - kSEMC_Nor_BurstLen8, /*!< Burst length 8*/ - kSEMC_Nor_BurstLen16, /*!< Burst length 16*/ - kSEMC_Nor_BurstLen32, /*!< Burst length 32*/ - kSEMC_Nor_BurstLen64 /*!< Burst length 64*/ -} sem_norsram_burst_len_t; - -/*! @brief SEMC dbi column address bit number. */ -typedef enum _semc_dbi_column_bit_num { - kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */ - kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */ - kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */ - kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */ - kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */ - kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */ - kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */ - kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */ - kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */ - kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */ - kSEMC_Dbi_Colum_2bit /*!< 2 bit. */ -} semc_dbi_column_bit_num_t; - -/*! @brief SEMC dbi burst length. */ -typedef enum _semc_dbi_burst_len { - kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/ - kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/ - kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/ - kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/ - kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/ - kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/ - kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/ -} sem_dbi_burst_len_t; - -/*! @brief SEMC IOMUXC. */ -typedef enum _semc_iomux_pin { - kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */ - kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */ - kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/ - kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */ - kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ - kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ -} semc_iomux_pin; - -/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */ -typedef enum _semc_iomux_nora27_pin { - kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */ - kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ - kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ -} semc_iomux_nora27_pin; - -/*! @brief SEMC port size. */ -typedef enum _semc_port_size { - kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */ - kSEMC_PortSize16Bit /*!< 16-Bit port size. */ -} smec_port_size_t; - -/*! @brief SEMC address mode. */ -typedef enum _semc_addr_mode { - kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */ - kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */ - kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */ -} semc_addr_mode_t; - -/*! @brief SEMC DQS read strobe mode. */ -typedef enum _semc_dqs_mode { - kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */ - kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */ -} semc_dqs_mode_t; - -/*! @brief SEMC ADV signal active polarity. */ -typedef enum _semc_adv_polarity { - kSEMC_AdvActiveLow = 0, /*!< Adv active low. */ - kSEMC_AdvActivehigh, /*!< Adv active low. */ -} semc_adv_polarity_t; - -/*! @brief SEMC RDY signal active polarity. */ -typedef enum _semc_rdy_polarity { - kSEMC_RdyActiveLow = 0, /*!< Adv active low. */ - kSEMC_RdyActivehigh, /*!< Adv active low. */ -} semc_rdy_polarity_t; - -/*! @brief SEMC IP command for NAND: address mode. */ -typedef enum _semc_ipcmd_nand_addrmode { - kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */ - kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */ - kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */ - kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */ - kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */ - kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */ -} semc_ipcmd_nand_addrmode_t; - -/*! @brief SEMC IP command for NAND： command mode. */ -typedef enum _semc_ipcmd_nand_cmdmode { - kSEMC_NANDCM_Command = 0x2U, /*!< command. */ - kSEMC_NANDCM_CommandHold, /*!< Command hold. */ - kSEMC_NANDCM_CommandAddress, /*!< Command address. */ - kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */ - kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */ - kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */ - kSEMC_NANDCM_CommandRead, /*!< Command read. */ - kSEMC_NANDCM_CommandWrite, /*!< Command write. */ - kSEMC_NANDCM_Read, /*!< Read. */ - kSEMC_NANDCM_Write /*!< Write. */ -} semc_ipcmd_nand_cmdmode_t; - -/*! @brief SEMC NAND address option. */ -typedef enum _semc_nand_address_option { - kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */ - kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */ - kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */ - kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */ - kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */ - kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */ -} semc_nand_address_option_t; - -/*! @brief SEMC IP command for NOR. */ -typedef enum _semc_ipcmd_nor_dbi { - kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */ - kSEMC_NORDBICM_Write /*!< NOR write. */ -} semc_ipcmd_nor_dbi_t; - -/*! @brief SEMC IP command for SRAM. */ -typedef enum _semc_ipcmd_sram { - kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */ - kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */ - kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */ - kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */ -} semc_ipcmd_sram_t; - -/*! @brief SEMC IP command for SDARM. */ -typedef enum _semc_ipcmd_sdram { - kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */ - kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */ - kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */ - kSEMC_SDRAMCM_Active, /*!< SDRAM active. */ - kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */ - kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */ - kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */ - kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */ -} semc_ipcmd_sdram_t; - -/*! @brief SEMC SDRAM configuration structure. - * - * 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes - * should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. - * Take refer to BR0~BR3 register in RM for details. - * 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, - * it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, - * The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. - * idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are - * similar to prescalePeriod_N16Cycle. - * - */ -typedef struct _semc_sdram_config -{ - semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */ - uint32_t address; /*!< The base address. */ - uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ - smec_port_size_t portSize; /*!< Port size. */ - sem_sdram_burst_len_t burstLen; /*!< Burst length. */ - semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ - semc_caslatency_t casLatency; /*!< CAS latency. */ - uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */ - uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */ - uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */ - uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */ - uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */ - uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */ - uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */ - uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */ - uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */ - uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */ - uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */ - uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */ - uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */ - uint8_t refreshBurstLen; /*!< Refresh burst length. */ -} semc_sdram_config_t; - - -/*! @brief SEMC NAND device timing configuration structure. */ -typedef struct _semc_nand_timing_config -{ - uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */ - uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */ - uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */ - uint8_t tWeLow_Ns; /*!< WE low time: tWP. */ - uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */ - uint8_t tReLow_Ns; /*!< RE low time: tRP. */ - uint8_t tReHigh_Ns; /*!< RE high time: tREH. */ - uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */ - uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */ - uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */ - uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */ - uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */ - uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */ -} semc_nand_timing_config_t; - - -/*! @brief SEMC NAND configuration structure. */ -typedef struct _semc_nand_config -{ - semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */ - uint32_t axiAddress; /*!< The base address for AXI nand. */ - uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */ - uint32_t ipgAddress; /*!< The base address for IPG nand . */ - uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */ - semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ - bool edoModeEnabled; /*!< EDO mode enabled. */ - semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ - semc_nand_address_option_t arrayAddrOption; /*!< Address option. */ - sem_nand_burst_len_t burstLen; /*!< Burst length. */ - smec_port_size_t portSize; /*!< Port size. */ - semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */ -} semc_nand_config_t; - -/*! @brief SEMC NOR configuration structure. */ -typedef struct _semc_nor_config -{ - semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ - semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ - uint32_t address; /*!< The base address. */ - uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ - uint8_t addrPortWidth; /*!< The address port width. */ - semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ - semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */ - semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ - semc_addr_mode_t addrMode; /*!< Address mode. */ - sem_norsram_burst_len_t burstLen; /*!< Burst length. */ - smec_port_size_t portSize; /*!< Port size. */ - uint8_t tCeSetup_Ns; /*!< The CE setup time. */ - uint8_t tCeHold_Ns; /*!< The CE hold time. */ - uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ - uint8_t tAddrSetup_Ns; /*!< The address setup time. */ - uint8_t tAddrHold_Ns; /*!< The address hold time. */ - uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ - uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ - uint8_t tReLow_Ns; /*!< RE low time for async mode. */ - uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ - uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ - uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ - uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ - uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ - uint8_t latencyCount; /*!< Latency count for sync mode. */ - uint8_t readCycle; /*!< Read cycle time for sync mode. */ -} semc_nor_config_t; - -/*! @brief SEMC SRAM configuration structure. */ -typedef struct _semc_sram_config -{ - semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ - semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ - uint32_t address; /*!< The base address. */ - uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ - uint8_t addrPortWidth; /*!< The address port width. */ - semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */ - semc_addr_mode_t addrMode; /*!< Address mode. */ - sem_norsram_burst_len_t burstLen; /*!< Burst length. */ - smec_port_size_t portSize; /*!< Port size. */ - uint8_t tCeSetup_Ns; /*!< The CE setup time. */ - uint8_t tCeHold_Ns; /*!< The CE hold time. */ - uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ - uint8_t tAddrSetup_Ns; /*!< The address setup time. */ - uint8_t tAddrHold_Ns; /*!< The address hold time. */ - uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ - uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ - uint8_t tReLow_Ns; /*!< RE low time for async mode. */ - uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ - uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ - uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ - uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ - uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ - uint8_t latencyCount; /*!< Latency count for sync mode. */ - uint8_t readCycle; /*!< Read cycle time for sync mode. */ -} semc_sram_config_t; - -/*! @brief SEMC DBI configuration structure. */ -typedef struct _semc_dbi_config -{ - semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */ - uint32_t address; /*!< The base address. */ - uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */ - semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ - sem_dbi_burst_len_t burstLen; /*!< Burst length. */ - smec_port_size_t portSize; /*!< Port size. */ - uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */ - uint8_t tCsxHold_Ns; /*!< The CSX hold time. */ - uint8_t tWexLow_Ns; /*!< WEX low time. */ - uint8_t tWexHigh_Ns; /*!< WEX high time. */ - uint8_t tRdxLow_Ns; /*!< RDX low time. */ - uint8_t tRdxHigh_Ns; /*!< RDX high time. */ - uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/ -} semc_dbi_config_t; - -/*! @brief SEMC AXI queue a weight setting. */ -typedef struct _semc_queuea_weight -{ - uint32_t qos : 4; /*!< weight of qos for queue 0 . */ - uint32_t aging : 4; /*!< weight of aging for queue 0.*/ - uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/ - uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/ -} semc_queuea_weight_t; - -/*! @brief SEMC AXI queue b weight setting. */ -typedef struct _semc_queueb_weight -{ - uint32_t qos : 4; /*!< weight of qos for queue 1. */ - uint32_t aging : 4; /*!< weight of aging for queue 1.*/ - uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/ - uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/ - uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/ -} semc_queueb_weight_t; - -/*! @brief SEMC AXI queue weight setting. */ -typedef struct _semc_axi_queueweight -{ - semc_queuea_weight_t *queueaWeight; /*!< Weight settings for queue a. */ - semc_queueb_weight_t *queuebWeight; /*!< Weight settings for queue b. */ -} semc_axi_queueweight_t; - -/*! - * @brief SEMC configuration structure. - * - * busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is - * 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. - * cmdTimeoutCycles: is used for command execution timeout cycles. it's - * similar to the busTimeoutCycles. - */ -typedef struct _semc_config_t -{ - semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */ - uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */ - uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */ - semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */ -} semc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name SEMC Initialization and De-initialization - * @{ - */ - -/*! - * @brief Gets the SEMC default basic configuration structure. - * - * The purpose of this API is to get the default SEMC - * configure structure for SEMC_Init(). User may use the initialized - * structure unchanged in SEMC_Init(), or modify some fields of the - * structure before calling SEMC_Init(). - * Example: - @code - semc_config_t config; - SEMC_GetDefaultConfig(&config); - @endcode - * @param config The SEMC configuration structure pointer. - */ -void SEMC_GetDefaultConfig(semc_config_t *config); - -/*! - * @brief Initializes SEMC. - * This function ungates the SEMC clock and initializes SEMC. - * This function must be called before calling any other SEMC driver functions. - * - * @param base SEMC peripheral base address. - * @param configure The SEMC configuration structure pointer. - */ -void SEMC_Init(SEMC_Type *base, semc_config_t *configure); - -/*! - * @brief Deinitializes the SEMC module and gates the clock. - * This function gates the SEMC clock. As a result, the SEMC - * module doesn't work after calling this function. - * - * @param base SEMC peripheral base address. - */ -void SEMC_Deinit(SEMC_Type *base); - -/* @} */ - -/*! - * @name SEMC Configuration Operation For Each Memory Type - * @{ - */ - -/*! - * @brief Configures SDRAM controller in SEMC. - * - * @param base SEMC peripheral base address. - * @param cs The chip selection. - * @param config The sdram configuration. - * @param clkSrc_Hz The SEMC clock frequency. - */ -status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz); - -/*! - * @brief Configures NAND controller in SEMC. - * - * @param base SEMC peripheral base address. - * @param config The nand configuration. - * @param clkSrc_Hz The SEMC clock frequency. - */ -status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz); - -/*! - * @brief Configures NOR controller in SEMC. - * - * @param base SEMC peripheral base address. - * @param config The nor configuration. - * @param clkSrc_Hz The SEMC clock frequency. - */ -status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz); - -/*! - * @brief Configures SRAM controller in SEMC. - * - * @param base SEMC peripheral base address. - * @param config The sram configuration. - * @param clkSrc_Hz The SEMC clock frequency. - */ -status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz); - -/*! - * @brief Configures DBI controller in SEMC. - * - * @param base SEMC peripheral base address. - * @param config The dbi configuration. - * @param clkSrc_Hz The SEMC clock frequency. - */ -status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz); - -/* @} */ - -/*! - * @name SEMC Interrupt Operation - * @{ - */ - -/*! - * @brief Enables the SEMC interrupt. - * - * This function enables the SEMC interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. - * For example, to enable the IP command done and error interrupt, do the following. - * @code - * SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); - * @endcode - * - * @param base SEMC peripheral base address. - * @param mask SEMC interrupts to enable. This is a logical OR of the - * enumeration :: semc_interrupt_enable_t. - */ -static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask) -{ - base->INTEN |= mask; -} - -/*! - * @brief Disables the SEMC interrupt. - * - * This function disables the SEMC interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. - * For example, to disable the IP command done and error interrupt, do the following. - * @code - * SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); - * @endcode - * - * @param base SEMC peripheral base address. - * @param mask SEMC interrupts to disable. This is a logical OR of the - * enumeration :: semc_interrupt_enable_t. - */ -static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask) -{ - base->INTEN &= ~mask; -} - -/*! - * @brief Gets the SEMC status. - * - * This function gets the SEMC interrupts event status. - * User can use the a logical OR of enumeration member as a mask. - * See @ref semc_interrupt_enable_t. - * - * @param base SEMC peripheral base address. - * @return status flag, use status flag in semc_interrupt_enable_t to get the related status. - */ -static inline bool SEMC_GetStatusFlag(SEMC_Type *base) -{ - return base->INTR; -} - -/*! - * @brief Clears the SEMC status flag state. - * - * The following status register flags can be cleared SEMC interrupt status. - * - * @param base SEMC base pointer - * @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t. - */ -static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask) -{ - base->INTR |= mask; -} - -/* @} */ - -/*! - * @name SEMC Memory Access Operation - * @{ - */ - -/*! - * @brief Check if SEMC is in idle. - * - * @param base SEMC peripheral base address. - * @return True SEMC is in idle, false is not in idle. - */ -static inline bool SEMC_IsInIdle(SEMC_Type *base) -{ - return (base->STS0 & SEMC_STS0_IDLE_MASK) ? true : false; -} - -/*! - * @brief SEMC IP command access. - * - * @param base SEMC peripheral base address. - * @param type SEMC memory type. refer to "semc_mem_type_t" - * @param address SEMC device address. - * @param command SEMC IP command. - * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. - * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". - * For SRAM device, take refer to "semc_ipcmd_sram_t". - * For SDRAM device, take refer to "semc_ipcmd_sdram_t". - * @param write Data for write access. - * @param read Data pointer for read data out. - */ -status_t SEMC_SendIPCommand( - SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read); - -/*! - * @brief Build SEMC IP command for NAND. - * - * This function build SEMC NAND IP command. The command is build of user command code, - * SEMC address mode and SEMC command mode. - * - * @param userCommand NAND device normal command. - * @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t". - * @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t". - */ -static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand, - semc_ipcmd_nand_addrmode_t addrMode, - semc_ipcmd_nand_cmdmode_t cmdMode) -{ - return (uint16_t)((uint16_t)userCommand << 8) | (uint16_t)(addrMode << 4) | ((uint8_t)cmdMode & 0x0Fu); -} - -/*! - * @brief Check if the NAND device is ready. - * - * @param base SEMC peripheral base address. - * @return True NAND is ready, false NAND is not ready. - */ -static inline bool SEMC_IsNandReady(SEMC_Type *base) -{ - return (base->STS0 & SEMC_STS0_NARDY_MASK) ? true : false; -} - -/*! - * @brief SEMC NAND device memory write through IP command. - * - * @param base SEMC peripheral base address. - * @param address SEMC NAND device address. - * @param data Data for write access. - * @param size_bytes Data length. - */ -status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); - -/*! - * @brief SEMC NAND device memory read through IP command. - * - * @param base SEMC peripheral base address. - * @param address SEMC NAND device address. - * @param data Data pointer for data read out. - * @param size_bytes Data length. - */ -status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); - -/*! - * @brief SEMC NOR device memory write through IP command. - * - * @param base SEMC peripheral base address. - * @param address SEMC NOR device address. - * @param data Data for write access. - * @param size_bytes Data length. - */ -status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); - -/*! - * @brief SEMC NOR device memory read through IP command. - * - * @param base SEMC peripheral base address. - * @param address SEMC NOR device address. - * @param data Data pointer for data read out. - * @param size_bytes Data length. - */ -status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SEMC_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_snvs_hp.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_snvs_hp.c deleted file mode 100644 index 0e6efab131..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_snvs_hp.c +++ /dev/null @@ -1,463 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2017, NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_snvs_hp.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.snvs_hp" -#endif - -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) -#define SECONDS_IN_A_MINUTE (60U) -#define DAYS_IN_A_YEAR (365U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) - -#if !(defined(SNVS_HPCOMR_SW_SV_MASK)) -#define SNVS_HPCOMR_SW_SV_MASK (0x100U) -#endif -#if !(defined(SNVS_HPSR_PI_MASK)) -#define SNVS_HPSR_PI_MASK (0x2U) -#endif -#if !(defined(SNVS_HPSR_HPTA_MASK)) -#define SNVS_HPSR_HPTA_MASK (0x1U) -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Checks whether the date and time passed in is valid - * - * @param datetime Pointer to structure where the date and time details are stored - * - * @return Returns false if the date & time details are out of range; true if in range - */ -static bool SNVS_HP_CheckDatetimeFormat(const snvs_hp_rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from datetime to seconds - * - * @param datetime Pointer to datetime structure where the date and time details are stored - * - * @return The result of the conversion in seconds - */ -static uint32_t SNVS_HP_ConvertDatetimeToSeconds(const snvs_hp_rtc_datetime_t *datetime); - -/*! - * @brief Converts time data from seconds to a datetime structure - * - * @param seconds Seconds value that needs to be converted to datetime format - * @param datetime Pointer to the datetime structure where the result of the conversion is stored - */ -static void SNVS_HP_ConvertSecondsToDatetime(uint32_t seconds, snvs_hp_rtc_datetime_t *datetime); - -/*! - * @brief Returns RTC time in seconds. - * - * This function is used internally to get actual RTC time in seconds. - * - * @param base SNVS peripheral base address - * - * @return RTC time in seconds - */ -static uint32_t SNVS_HP_RTC_GetSeconds(SNVS_Type *base); - -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_HP_CLOCKS)) -/*! - * @brief Get the SNVS instance from peripheral base address. - * - * @param base SNVS peripheral base address. - * - * @return SNVS instance. - */ -static uint32_t SNVS_HP_GetInstance(SNVS_Type *base); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_HP_CLOCKS)) -/*! @brief Pointer to snvs_hp clock. */ -const clock_ip_name_t s_snvsHpClock[] = SNVS_HP_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static bool SNVS_HP_CheckDatetimeFormat(const snvs_hp_rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Check year, month, hour, minute, seconds */ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || - (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) - { - /* If not correct then error*/ - return false; - } - - /* Adjust the days in February for a leap year */ - if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) - { - daysPerMonth[2] = 29U; - } - - /* Check the validity of the day */ - if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) - { - return false; - } - - return true; -} - -static uint32_t SNVS_HP_ConvertDatetimeToSeconds(const snvs_hp_rtc_datetime_t *datetime) -{ - assert(datetime); - - /* Number of days from begin of the non Leap-year*/ - /* Number of days from begin of the non Leap-year*/ - uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; - uint32_t seconds; - - /* Compute number of days from 1970 till given year*/ - seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; - /* Add leap year days */ - seconds += ((datetime->year / 4) - (1970U / 4)); - /* Add number of days till given month*/ - seconds += monthDays[datetime->month]; - /* Add days in given month. We subtract the current day as it is - * represented in the hours, minutes and seconds field*/ - seconds += (datetime->day - 1); - /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) - { - seconds--; - } - - seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + - (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; - - return seconds; -} - -static void SNVS_HP_ConvertSecondsToDatetime(uint32_t seconds, snvs_hp_rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t x; - uint32_t secondsRemaining, days; - uint16_t daysInYear; - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Start with the seconds value that is passed in to be converted to date time format */ - secondsRemaining = seconds; - - /* Calcuate the number of days, we add 1 for the current day which is represented in the - * hours and seconds field - */ - days = secondsRemaining / SECONDS_IN_A_DAY + 1; - - /* Update seconds left*/ - secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; - - /* Calculate the datetime hour, minute and second fields */ - datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; - secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; - datetime->minute = secondsRemaining / 60U; - datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; - - /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; - datetime->year = YEAR_RANGE_START; - while (days > daysInYear) - { - /* Decrease day count by a year and increment year by 1 */ - days -= daysInYear; - datetime->year++; - - /* Adjust the number of days for a leap year */ - if (datetime->year & 3U) - { - daysInYear = DAYS_IN_A_YEAR; - } - else - { - daysInYear = DAYS_IN_A_YEAR + 1; - } - } - - /* Adjust the days in February for a leap year */ - if (!(datetime->year & 3U)) - { - daysPerMonth[2] = 29U; - } - - for (x = 1U; x <= 12U; x++) - { - if (days <= daysPerMonth[x]) - { - datetime->month = x; - break; - } - else - { - days -= daysPerMonth[x]; - } - } - - datetime->day = days; -} - -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_HP_CLOCKS)) -static uint32_t SNVS_HP_GetInstance(SNVS_Type *base) -{ - return 0U; -} -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config) -{ - assert(config); - -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_HP_CLOCKS)) - uint32_t instance = SNVS_HP_GetInstance(base); - CLOCK_EnableClock(s_snvsHpClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - base->HPCOMR |= SNVS_HPCOMR_NPSWA_EN_MASK | SNVS_HPCOMR_SW_SV_MASK; - - base->HPCR = SNVS_HPCR_PI_FREQ(config->periodicInterruptFreq); - - if (config->rtcCalEnable) - { - base->HPCR = SNVS_HPCR_HPCALB_VAL_MASK & (config->rtcCalValue << SNVS_HPCR_HPCALB_VAL_SHIFT); - base->HPCR |= SNVS_HPCR_HPCALB_EN_MASK; - } -} - -void SNVS_HP_RTC_Deinit(SNVS_Type *base) -{ - base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK; - -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_HP_CLOCKS)) - uint32_t instance = SNVS_HP_GetInstance(base); - CLOCK_DisableClock(s_snvsHpClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config) -{ - assert(config); - - config->rtcCalEnable = false; - config->rtcCalValue = 0U; - config->periodicInterruptFreq = 0U; -} - -static uint32_t SNVS_HP_RTC_GetSeconds(SNVS_Type *base) -{ - uint32_t seconds = 0; - uint32_t tmp = 0; - - /* Do consecutive reads until value is correct */ - do - { - seconds = tmp; - tmp = (base->HPRTCMR << 17U) | (base->HPRTCLR >> 15U); - } while (tmp != seconds); - - return seconds; -} - -status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t seconds = 0U; - uint32_t tmp = base->HPCR; - - /* disable RTC */ - SNVS_HP_RTC_StopTimer(base); - - /* Return error if the time provided is not valid */ - if (!(SNVS_HP_CheckDatetimeFormat(datetime))) - { - return kStatus_InvalidArgument; - } - - /* Set time in seconds */ - seconds = SNVS_HP_ConvertDatetimeToSeconds(datetime); - - base->HPRTCMR = (uint32_t)(seconds >> 17U); - base->HPRTCLR = (uint32_t)(seconds << 15U); - - /* reenable RTC in case that it was enabled before */ - if (tmp & SNVS_HPCR_RTC_EN_MASK) - { - SNVS_HP_RTC_StartTimer(base); - } - - return kStatus_Success; -} - -void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) -{ - assert(datetime); - - SNVS_HP_ConvertSecondsToDatetime(SNVS_HP_RTC_GetSeconds(base), datetime); -} - -status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime) -{ - assert(alarmTime); - - uint32_t alarmSeconds = 0U; - uint32_t currSeconds = 0U; - uint32_t tmp = base->HPCR; - - /* Return error if the alarm time provided is not valid */ - if (!(SNVS_HP_CheckDatetimeFormat(alarmTime))) - { - return kStatus_InvalidArgument; - } - - alarmSeconds = SNVS_HP_ConvertDatetimeToSeconds(alarmTime); - currSeconds = SNVS_HP_RTC_GetSeconds(base); - - /* Return error if the alarm time has passed */ - if (alarmSeconds < currSeconds) - { - return kStatus_Fail; - } - - /* disable RTC alarm interrupt */ - base->HPCR &= ~SNVS_HPCR_HPTA_EN_MASK; - while (base->HPCR & SNVS_HPCR_HPTA_EN_MASK) - { - } - - /* Set alarm in seconds*/ - base->HPTAMR = (uint32_t)(alarmSeconds >> 17U); - base->HPTALR = (uint32_t)(alarmSeconds << 15U); - - /* reenable RTC alarm interrupt in case that it was enabled before */ - base->HPCR = tmp; - - return kStatus_Success; -} - -void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t alarmSeconds = 0U; - - /* Get alarm in seconds */ - alarmSeconds = (base->HPTAMR << 17U) | (base->HPTALR >> 15U); - - SNVS_HP_ConvertSecondsToDatetime(alarmSeconds, datetime); -} - -#if (defined(FSL_FEATURE_SNVS_HAS_SRTC) && (FSL_FEATURE_SNVS_HAS_SRTC > 0)) -void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base) -{ - uint32_t tmp = base->HPCR; - - /* disable RTC */ - SNVS_HP_RTC_StopTimer(base); - - base->HPCR |= SNVS_HPCR_HP_TS_MASK; - - /* reenable RTC in case that it was enabled before */ - if (tmp & SNVS_HPCR_RTC_EN_MASK) - { - SNVS_HP_RTC_StartTimer(base); - } -} -#endif /* FSL_FEATURE_SNVS_HAS_SRTC */ - -uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base) -{ - uint32_t flags = 0U; - - if (base->HPSR & SNVS_HPSR_PI_MASK) - { - flags |= kSNVS_RTC_PeriodicInterruptFlag; - } - - if (base->HPSR & SNVS_HPSR_HPTA_MASK) - { - flags |= kSNVS_RTC_AlarmInterruptFlag; - } - - return flags; -} - -uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base) -{ - uint32_t val = 0U; - - if (base->HPCR & SNVS_HPCR_PI_EN_MASK) - { - val |= kSNVS_RTC_PeriodicInterrupt; - } - - if (base->HPCR & SNVS_HPCR_HPTA_EN_MASK) - { - val |= kSNVS_RTC_AlarmInterrupt; - } - - return val; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_snvs_hp.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_snvs_hp.h deleted file mode 100644 index 27bf7e6625..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_snvs_hp.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2017, NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_SNVS_HP_H_ -#define _FSL_SNVS_HP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup snvs_hp - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief List of SNVS interrupts */ -typedef enum _snvs_hp_interrupts -{ - kSNVS_RTC_AlarmInterrupt = SNVS_HPCR_HPTA_EN_MASK, /*!< RTC time alarm */ - kSNVS_RTC_PeriodicInterrupt = SNVS_HPCR_PI_EN_MASK, /*!< RTC periodic interrupt */ -} snvs_hp_interrupts_t; - -/*! @brief List of SNVS flags */ -typedef enum _snvs_hp_status_flags -{ - kSNVS_RTC_AlarmInterruptFlag = SNVS_HPSR_HPTA_MASK, /*!< RTC time alarm flag */ - kSNVS_RTC_PeriodicInterruptFlag = SNVS_HPSR_PI_MASK, /*!< RTC periodic interrupt flag */ -} snvs_hp_status_flags_t; - -/*! @brief Structure is used to hold the date and time */ -typedef struct _snvs_hp_rtc_datetime -{ - uint16_t year; /*!< Range from 1970 to 2099.*/ - uint8_t month; /*!< Range from 1 to 12.*/ - uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint8_t hour; /*!< Range from 0 to 23.*/ - uint8_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} snvs_hp_rtc_datetime_t; - -/*! - * @brief SNVS config structure - * - * This structure holds the configuration settings for the SNVS peripheral. To initialize this - * structure to reasonable defaults, call the SNVS_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _snvs_hp_rtc_config -{ - bool rtcCalEnable; /*!< true: RTC calibration mechanism is enabled; - false:No calibration is used */ - uint32_t rtcCalValue; /*!< Defines signed calibration value for nonsecure RTC; - This is a 5-bit 2's complement value, range from -16 to +15 */ - uint32_t periodicInterruptFreq; /*!< Defines frequency of the periodic interrupt; - Range from 0 to 15 */ -} snvs_hp_rtc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the SNVS clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the SNVS driver. - * - * @param base SNVS peripheral base address - * @param config Pointer to the user's SNVS configuration structure. - */ -void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config); - -/*! - * @brief Stops the RTC and SRTC timers. - * - * @param base SNVS peripheral base address - */ -void SNVS_HP_RTC_Deinit(SNVS_Type *base); - -/*! - * @brief Fills in the SNVS config struct with the default settings. - * - * The default values are as follows. - * @code - * config->rtccalenable = false; - * config->rtccalvalue = 0U; - * config->PIFreq = 0U; - * @endcode - * @param config Pointer to the user's SNVS configuration structure. - */ -void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config); - -/*! @}*/ - -/*! - * @name Non secure RTC current Time & Alarm - * @{ - */ - -/*! - * @brief Sets the SNVS RTC date and time according to the given time structure. - * - * @param base SNVS peripheral base address - * @param datetime Pointer to the structure where the date and time details are stored. - * - * @return kStatus_Success: Success in setting the time and starting the SNVS RTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime); - -/*! - * @brief Gets the SNVS RTC time and stores it in the given time structure. - * - * @param base SNVS peripheral base address - * @param datetime Pointer to the structure where the date and time details are stored. - */ -void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime); - -/*! - * @brief Sets the SNVS RTC alarm time. - * - * The function sets the RTC alarm. It also checks whether the specified alarm time - * is greater than the present time. If not, the function does not set the alarm - * and returns an error. - * - * @param base SNVS peripheral base address - * @param alarmTime Pointer to the structure where the alarm time is stored. - * - * @return kStatus_Success: success in setting the SNVS RTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed - */ -status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime); - -/*! - * @brief Returns the SNVS RTC alarm time. - * - * @param base SNVS peripheral base address - * @param datetime Pointer to the structure where the alarm date and time details are stored. - */ -void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime); - -#if (defined(FSL_FEATURE_SNVS_HAS_SRTC) && (FSL_FEATURE_SNVS_HAS_SRTC > 0)) -/*! - * @brief The function synchronizes RTC counter value with SRTC. - * - * @param base SNVS peripheral base address - */ -void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base); -#endif /* FSL_FEATURE_SNVS_HAS_SRTC */ - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected SNVS interrupts. - * - * @param base SNVS peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::snvs_interrupt_enable_t - */ -static inline void SNVS_HP_RTC_EnableInterrupts(SNVS_Type *base, uint32_t mask) -{ - base->HPCR |= mask; -} - -/*! - * @brief Disables the selected SNVS interrupts. - * - * @param base SNVS peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::snvs_interrupt_enable_t - */ -static inline void SNVS_HP_RTC_DisableInterrupts(SNVS_Type *base, uint32_t mask) -{ - base->HPCR &= ~mask; -} - -/*! - * @brief Gets the enabled SNVS interrupts. - * - * @param base SNVS peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::snvs_interrupt_enable_t - */ -uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base); - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the SNVS status flags. - * - * @param base SNVS peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::snvs_status_flags_t - */ -uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base); - -/*! - * @brief Clears the SNVS status flags. - * - * @param base SNVS peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::snvs_status_flags_t - */ -static inline void SNVS_HP_RTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask) -{ - base->HPSR |= mask; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the SNVS RTC time counter. - * - * @param base SNVS peripheral base address - */ -static inline void SNVS_HP_RTC_StartTimer(SNVS_Type *base) -{ - base->HPCR |= SNVS_HPCR_RTC_EN_MASK; - while (!(base->HPCR & SNVS_HPCR_RTC_EN_MASK)) - { - } -} - -/*! - * @brief Stops the SNVS RTC time counter. - * - * @param base SNVS peripheral base address - */ -static inline void SNVS_HP_RTC_StopTimer(SNVS_Type *base) -{ - base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK; - while (base->HPCR & SNVS_HPCR_RTC_EN_MASK) - { - } -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SNVS_HP_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_snvs_lp.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_snvs_lp.c deleted file mode 100644 index c9f539630e..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_snvs_lp.c +++ /dev/null @@ -1,609 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2017, NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_snvs_lp.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.snvs_lp" -#endif - -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) -#define SECONDS_IN_A_MINUTE (60U) -#define DAYS_IN_A_YEAR (365U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Checks whether the date and time passed in is valid - * - * @param datetime Pointer to structure where the date and time details are stored - * - * @return Returns false if the date & time details are out of range; true if in range - */ -static bool SNVS_LP_CheckDatetimeFormat(const snvs_lp_srtc_datetime_t *datetime); - -/*! - * @brief Converts time data from datetime to seconds - * - * @param datetime Pointer to datetime structure where the date and time details are stored - * - * @return The result of the conversion in seconds - */ -static uint32_t SNVS_LP_ConvertDatetimeToSeconds(const snvs_lp_srtc_datetime_t *datetime); - -/*! - * @brief Converts time data from seconds to a datetime structure - * - * @param seconds Seconds value that needs to be converted to datetime format - * @param datetime Pointer to the datetime structure where the result of the conversion is stored - */ -static void SNVS_LP_ConvertSecondsToDatetime(uint32_t seconds, snvs_lp_srtc_datetime_t *datetime); - -/*! - * @brief Returns SRTC time in seconds. - * - * This function is used internally to get actual SRTC time in seconds. - * - * @param base SNVS peripheral base address - * - * @return SRTC time in seconds - */ -static uint32_t SNVS_LP_SRTC_GetSeconds(SNVS_Type *base); - -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_LP_CLOCKS)) -/*! - * @brief Get the SNVS instance from peripheral base address. - * - * @param base SNVS peripheral base address. - * - * @return SNVS instance. - */ -static uint32_t SNVS_LP_GetInstance(SNVS_Type *base); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_LP_CLOCKS)) -/*! @brief Pointer to snvs_lp clock. */ -const clock_ip_name_t s_snvsLpClock[] = SNVS_LP_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static bool SNVS_LP_CheckDatetimeFormat(const snvs_lp_srtc_datetime_t *datetime) -{ - assert(datetime); - - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Check year, month, hour, minute, seconds */ - if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || - (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) - { - /* If not correct then error*/ - return false; - } - - /* Adjust the days in February for a leap year */ - if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) - { - daysPerMonth[2] = 29U; - } - - /* Check the validity of the day */ - if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) - { - return false; - } - - return true; -} - -static uint32_t SNVS_LP_ConvertDatetimeToSeconds(const snvs_lp_srtc_datetime_t *datetime) -{ - assert(datetime); - - /* Number of days from begin of the non Leap-year*/ - /* Number of days from begin of the non Leap-year*/ - uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; - uint32_t seconds; - - /* Compute number of days from 1970 till given year*/ - seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; - /* Add leap year days */ - seconds += ((datetime->year / 4) - (1970U / 4)); - /* Add number of days till given month*/ - seconds += monthDays[datetime->month]; - /* Add days in given month. We subtract the current day as it is - * represented in the hours, minutes and seconds field*/ - seconds += (datetime->day - 1); - /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) - { - seconds--; - } - - seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + - (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; - - return seconds; -} - -static void SNVS_LP_ConvertSecondsToDatetime(uint32_t seconds, snvs_lp_srtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t x; - uint32_t secondsRemaining, days; - uint16_t daysInYear; - /* Table of days in a month for a non leap year. First entry in the table is not used, - * valid months start from 1 - */ - uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; - - /* Start with the seconds value that is passed in to be converted to date time format */ - secondsRemaining = seconds; - - /* Calcuate the number of days, we add 1 for the current day which is represented in the - * hours and seconds field - */ - days = secondsRemaining / SECONDS_IN_A_DAY + 1; - - /* Update seconds left*/ - secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; - - /* Calculate the datetime hour, minute and second fields */ - datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; - secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; - datetime->minute = secondsRemaining / 60U; - datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; - - /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; - datetime->year = YEAR_RANGE_START; - while (days > daysInYear) - { - /* Decrease day count by a year and increment year by 1 */ - days -= daysInYear; - datetime->year++; - - /* Adjust the number of days for a leap year */ - if (datetime->year & 3U) - { - daysInYear = DAYS_IN_A_YEAR; - } - else - { - daysInYear = DAYS_IN_A_YEAR + 1; - } - } - - /* Adjust the days in February for a leap year */ - if (!(datetime->year & 3U)) - { - daysPerMonth[2] = 29U; - } - - for (x = 1U; x <= 12U; x++) - { - if (days <= daysPerMonth[x]) - { - datetime->month = x; - break; - } - else - { - days -= daysPerMonth[x]; - } - } - - datetime->day = days; -} - -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_LP_CLOCKS)) -static uint32_t SNVS_LP_GetInstance(SNVS_Type *base) -{ - return 0U; -} -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config) -{ - assert(config); - -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_LP_CLOCKS)) - uint32_t instance = SNVS_LP_GetInstance(base); - CLOCK_EnableClock(s_snvsLpClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - int pin; - - if (config->srtcCalEnable) - { - base->LPCR = SNVS_LPCR_LPCALB_VAL_MASK & (config->srtcCalValue << SNVS_LPCR_LPCALB_VAL_SHIFT); - base->LPCR |= SNVS_LPCR_LPCALB_EN_MASK; - } - - for (pin = kSNVS_ExternalTamper1; pin <= SNVS_LP_MAX_TAMPER; pin++) - { - SNVS_LP_DisableExternalTamper(SNVS, (snvs_lp_external_tamper_t)pin); - SNVS_LP_ClearExternalTamperStatus(SNVS, (snvs_lp_external_tamper_t)pin); - } -} - -void SNVS_LP_SRTC_Deinit(SNVS_Type *base) -{ - base->LPCR &= ~SNVS_LPCR_SRTC_ENV_MASK; - -#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ - defined(SNVS_LP_CLOCKS)) - uint32_t instance = SNVS_LP_GetInstance(base); - CLOCK_DisableClock(s_snvsLpClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void SNVS_LP_SRTC_GetDefaultConfig(snvs_lp_srtc_config_t *config) -{ - assert(config); - - config->srtcCalEnable = false; - config->srtcCalValue = 0U; -} - -static uint32_t SNVS_LP_SRTC_GetSeconds(SNVS_Type *base) -{ - uint32_t seconds = 0; - uint32_t tmp = 0; - - /* Do consecutive reads until value is correct */ - do - { - seconds = tmp; - tmp = (base->LPSRTCMR << 17U) | (base->LPSRTCLR >> 15U); - } while (tmp != seconds); - - return seconds; -} - -status_t SNVS_LP_SRTC_SetDatetime(SNVS_Type *base, const snvs_lp_srtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t seconds = 0U; - uint32_t tmp = base->LPCR; - - /* disable RTC */ - SNVS_LP_SRTC_StopTimer(base); - - /* Return error if the time provided is not valid */ - if (!(SNVS_LP_CheckDatetimeFormat(datetime))) - { - return kStatus_InvalidArgument; - } - - /* Set time in seconds */ - seconds = SNVS_LP_ConvertDatetimeToSeconds(datetime); - - base->LPSRTCMR = (uint32_t)(seconds >> 17U); - base->LPSRTCLR = (uint32_t)(seconds << 15U); - - /* reenable SRTC in case that it was enabled before */ - if (tmp & SNVS_LPCR_SRTC_ENV_MASK) - { - SNVS_LP_SRTC_StartTimer(base); - } - - return kStatus_Success; -} - -void SNVS_LP_SRTC_GetDatetime(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime) -{ - assert(datetime); - - SNVS_LP_ConvertSecondsToDatetime(SNVS_LP_SRTC_GetSeconds(base), datetime); -} - -status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *alarmTime) -{ - assert(alarmTime); - - uint32_t alarmSeconds = 0U; - uint32_t currSeconds = 0U; - uint32_t tmp = base->LPCR; - - /* Return error if the alarm time provided is not valid */ - if (!(SNVS_LP_CheckDatetimeFormat(alarmTime))) - { - return kStatus_InvalidArgument; - } - - alarmSeconds = SNVS_LP_ConvertDatetimeToSeconds(alarmTime); - currSeconds = SNVS_LP_SRTC_GetSeconds(base); - - /* Return error if the alarm time has passed */ - if (alarmSeconds <= currSeconds) - { - return kStatus_Fail; - } - - /* disable SRTC alarm interrupt */ - base->LPCR &= ~SNVS_LPCR_LPTA_EN_MASK; - while (base->LPCR & SNVS_LPCR_LPTA_EN_MASK) - { - } - - /* Set alarm in seconds*/ - base->LPTAR = alarmSeconds; - - /* reenable SRTC alarm interrupt in case that it was enabled before */ - base->LPCR = tmp; - - return kStatus_Success; -} - -void SNVS_LP_SRTC_GetAlarm(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime) -{ - assert(datetime); - - uint32_t alarmSeconds = 0U; - - /* Get alarm in seconds */ - alarmSeconds = base->LPTAR; - - SNVS_LP_ConvertSecondsToDatetime(alarmSeconds, datetime); -} - -uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base) -{ - uint32_t flags = 0U; - - if (base->LPSR & SNVS_LPSR_LPTA_MASK) - { - flags |= kSNVS_SRTC_AlarmInterruptFlag; - } - - return flags; -} - -uint32_t SNVS_LP_SRTC_GetEnabledInterrupts(SNVS_Type *base) -{ - uint32_t val = 0U; - - if (base->LPCR & SNVS_LPCR_LPTA_EN_MASK) - { - val |= kSNVS_SRTC_AlarmInterrupt; - } - - return val; -} - -void SNVS_LP_EnableExternalTamper(SNVS_Type *base, - snvs_lp_external_tamper_t pin, - snvs_lp_external_tamper_polarity_t polarity) -{ - switch (pin) - { - case (kSNVS_ExternalTamper1): - base->LPTDCR = (base->LPTDCR & ~(1U << SNVS_LPTDCR_ET1P_SHIFT)) | (polarity << SNVS_LPTDCR_ET1P_SHIFT); - base->LPTDCR |= SNVS_LPTDCR_ET1_EN_MASK; - break; -#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) - case (kSNVS_ExternalTamper2): - base->LPTDCR = (base->LPTDCR & ~(1U << SNVS_LPTDCR_ET2P_SHIFT)) | (polarity << SNVS_LPTDCR_ET2P_SHIFT); - base->LPTDCR |= SNVS_LPTDCR_ET2_EN_MASK; - break; - case (kSNVS_ExternalTamper3): - base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET3P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET3P_SHIFT); - base->LPTDC2R |= SNVS_LPTDC2R_ET3_EN_MASK; - break; - case (kSNVS_ExternalTamper4): - base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET4P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET4P_SHIFT); - base->LPTDC2R |= SNVS_LPTDC2R_ET4_EN_MASK; - break; - case (kSNVS_ExternalTamper5): - base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET5P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET5P_SHIFT); - base->LPTDC2R |= SNVS_LPTDC2R_ET5_EN_MASK; - break; - case (kSNVS_ExternalTamper6): - base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET6P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET6P_SHIFT); - base->LPTDC2R |= SNVS_LPTDC2R_ET6_EN_MASK; - break; - case (kSNVS_ExternalTamper7): - base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET7P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET7P_SHIFT); - base->LPTDC2R |= SNVS_LPTDC2R_ET7_EN_MASK; - break; - case (kSNVS_ExternalTamper8): - base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET8P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET8P_SHIFT); - base->LPTDC2R |= SNVS_LPTDC2R_ET8_EN_MASK; - break; - case (kSNVS_ExternalTamper9): - base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET9P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET9P_SHIFT); - base->LPTDC2R |= SNVS_LPTDC2R_ET9_EN_MASK; - break; - case (kSNVS_ExternalTamper10): - base->LPTDC2R = - (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET10P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET10P_SHIFT); - base->LPTDC2R |= SNVS_LPTDC2R_ET10_EN_MASK; - break; -#endif - default: - break; - } -} - -void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin) -{ - switch (pin) - { - case (kSNVS_ExternalTamper1): - base->LPTDCR &= ~SNVS_LPTDCR_ET1_EN_MASK; - break; -#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) - case (kSNVS_ExternalTamper2): - base->LPTDCR &= ~SNVS_LPTDCR_ET2_EN_MASK; - break; - case (kSNVS_ExternalTamper3): - base->LPTDC2R &= ~SNVS_LPTDC2R_ET3_EN_MASK; - break; - case (kSNVS_ExternalTamper4): - base->LPTDC2R &= ~SNVS_LPTDC2R_ET4_EN_MASK; - break; - case (kSNVS_ExternalTamper5): - base->LPTDC2R &= ~SNVS_LPTDC2R_ET5_EN_MASK; - break; - case (kSNVS_ExternalTamper6): - base->LPTDC2R &= ~SNVS_LPTDC2R_ET6_EN_MASK; - break; - case (kSNVS_ExternalTamper7): - base->LPTDC2R &= ~SNVS_LPTDC2R_ET7_EN_MASK; - break; - case (kSNVS_ExternalTamper8): - base->LPTDC2R &= ~SNVS_LPTDC2R_ET8_EN_MASK; - break; - case (kSNVS_ExternalTamper9): - base->LPTDC2R &= ~SNVS_LPTDC2R_ET9_EN_MASK; - break; - case (kSNVS_ExternalTamper10): - base->LPTDC2R &= ~SNVS_LPTDC2R_ET10_EN_MASK; - break; -#endif - default: - break; - } -} - -snvs_lp_external_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin) -{ - snvs_lp_external_tamper_status_t status = kSNVS_TamperNotDetected; - - switch (pin) - { - case (kSNVS_ExternalTamper1): - status = (base->LPSR & SNVS_LPSR_ET1D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; - break; -#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) - case (kSNVS_ExternalTamper2): - status = (base->LPSR & SNVS_LPSR_ET2D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; - break; - case (kSNVS_ExternalTamper3): - status = (base->LPTDSR & SNVS_LPTDSR_ET3D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; - break; - case (kSNVS_ExternalTamper4): - status = (base->LPTDSR & SNVS_LPTDSR_ET4D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; - break; - case (kSNVS_ExternalTamper5): - status = (base->LPTDSR & SNVS_LPTDSR_ET5D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; - break; - case (kSNVS_ExternalTamper6): - status = (base->LPTDSR & SNVS_LPTDSR_ET6D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; - break; - case (kSNVS_ExternalTamper7): - status = (base->LPTDSR & SNVS_LPTDSR_ET7D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; - break; - case (kSNVS_ExternalTamper8): - status = (base->LPTDSR & SNVS_LPTDSR_ET8D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; - break; - case (kSNVS_ExternalTamper9): - status = (base->LPTDSR & SNVS_LPTDSR_ET9D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; - break; - case (kSNVS_ExternalTamper10): - status = (base->LPTDSR & SNVS_LPTDSR_ET10D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; - break; -#endif - default: - break; - } - return status; -} - -void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin) -{ - base->LPSR |= SNVS_LPSR_ET1D_MASK; - - switch (pin) - { - case (kSNVS_ExternalTamper1): - base->LPSR |= SNVS_LPSR_ET1D_MASK; - break; -#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) - case (kSNVS_ExternalTamper2): - base->LPSR |= SNVS_LPSR_ET2D_MASK; - break; - case (kSNVS_ExternalTamper3): - base->LPTDSR |= SNVS_LPTDSR_ET3D_MASK; - break; - case (kSNVS_ExternalTamper4): - base->LPTDSR |= SNVS_LPTDSR_ET4D_MASK; - break; - case (kSNVS_ExternalTamper5): - base->LPTDSR |= SNVS_LPTDSR_ET5D_MASK; - break; - case (kSNVS_ExternalTamper6): - base->LPTDSR |= SNVS_LPTDSR_ET6D_MASK; - break; - case (kSNVS_ExternalTamper7): - base->LPTDSR |= SNVS_LPTDSR_ET7D_MASK; - break; - case (kSNVS_ExternalTamper8): - base->LPTDSR |= SNVS_LPTDSR_ET8D_MASK; - break; - case (kSNVS_ExternalTamper9): - base->LPTDSR |= SNVS_LPTDSR_ET9D_MASK; - break; - case (kSNVS_ExternalTamper10): - base->LPTDSR |= SNVS_LPTDSR_ET10D_MASK; - break; -#endif - default: - break; - } -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_snvs_lp.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_snvs_lp.h deleted file mode 100644 index bd61d52ddb..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_snvs_lp.h +++ /dev/null @@ -1,381 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2017, NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_SNVS_LP_H_ -#define _FSL_SNVS_LP_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup snvs_lp - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SNVS_LP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief List of SNVS_LP interrupts */ -typedef enum _snvs_lp_srtc_interrupts -{ - kSNVS_SRTC_AlarmInterrupt = SNVS_LPCR_LPTA_EN_MASK, /*!< SRTC time alarm.*/ -} snvs_lp_srtc_interrupts_t; - -/*! @brief List of SNVS_LP flags */ -typedef enum _snvs_lp_srtc_status_flags -{ - kSNVS_SRTC_AlarmInterruptFlag = SNVS_LPSR_LPTA_MASK, /*!< SRTC time alarm flag */ -} snvs_lp_srtc_status_flags_t; - -/*! @brief List of SNVS_LP external tampers */ -typedef enum _snvs_lp_external_tamper -{ - kSNVS_ExternalTamper1 = 1U, -#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) - kSNVS_ExternalTamper2 = 2U, - kSNVS_ExternalTamper3 = 3U, - kSNVS_ExternalTamper4 = 4U, - kSNVS_ExternalTamper5 = 5U, - kSNVS_ExternalTamper6 = 6U, - kSNVS_ExternalTamper7 = 7U, - kSNVS_ExternalTamper8 = 8U, - kSNVS_ExternalTamper9 = 9U, - kSNVS_ExternalTamper10 = 10U -#endif -} snvs_lp_external_tamper_t; - -/* define max possible tamper present */ -#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) -#define SNVS_LP_MAX_TAMPER kSNVS_ExternalTamper10 -#else -#define SNVS_LP_MAX_TAMPER kSNVS_ExternalTamper1 -#endif - -/*! @brief List of SNVS_LP external tampers status */ -typedef enum _snvs_lp_external_tamper_status -{ - kSNVS_TamperNotDetected = 0U, - kSNVS_TamperDetected = 1U -} snvs_lp_external_tamper_status_t; - -/*! @brief SNVS_LP external tamper polarity */ -typedef enum _snvs_lp_external_tamper_polarity -{ - kSNVS_ExternalTamperActiveLow = 0U, - kSNVS_ExternalTamperActiveHigh = 1U -} snvs_lp_external_tamper_polarity_t; - -/*! @brief Structure is used to hold the date and time */ -typedef struct _snvs_lp_srtc_datetime -{ - uint16_t year; /*!< Range from 1970 to 2099.*/ - uint8_t month; /*!< Range from 1 to 12.*/ - uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ - uint8_t hour; /*!< Range from 0 to 23.*/ - uint8_t minute; /*!< Range from 0 to 59.*/ - uint8_t second; /*!< Range from 0 to 59.*/ -} snvs_lp_srtc_datetime_t; - -/*! - * @brief SNVS_LP config structure - * - * This structure holds the configuration settings for the SNVS_LP peripheral. To initialize this - * structure to reasonable defaults, call the SNVS_LP_GetDefaultConfig() function and pass a - * pointer to your config structure instance. - * - * The config struct can be made const so it resides in flash - */ -typedef struct _snvs_lp_srtc_config -{ - bool srtcCalEnable; /*!< true: SRTC calibration mechanism is enabled; - false: No calibration is used */ - uint32_t srtcCalValue; /*!< Defines signed calibration value for SRTC; - This is a 5-bit 2's complement value, range from -16 to +15 */ -} snvs_lp_srtc_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the SNVS clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application using the SNVS driver. - * - * @param base SNVS peripheral base address - * @param config Pointer to the user's SNVS configuration structure. - */ -void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config); - -/*! - * @brief Stops the SRTC timer. - * - * @param base SNVS peripheral base address - */ -void SNVS_LP_SRTC_Deinit(SNVS_Type *base); - -/*! - * @brief Fills in the SNVS_LP config struct with the default settings. - * - * The default values are as follows. - * @code - * config->srtccalenable = false; - * config->srtccalvalue = 0U; - * @endcode - * @param config Pointer to the user's SNVS configuration structure. - */ -void SNVS_LP_SRTC_GetDefaultConfig(snvs_lp_srtc_config_t *config); - -/*! @}*/ - -/*! - * @name Secure RTC (SRTC) current Time & Alarm - * @{ - */ - -/*! - * @brief Sets the SNVS SRTC date and time according to the given time structure. - * - * @param base SNVS peripheral base address - * @param datetime Pointer to the structure where the date and time details are stored. - * - * @return kStatus_Success: Success in setting the time and starting the SNVS SRTC - * kStatus_InvalidArgument: Error because the datetime format is incorrect - */ -status_t SNVS_LP_SRTC_SetDatetime(SNVS_Type *base, const snvs_lp_srtc_datetime_t *datetime); - -/*! - * @brief Gets the SNVS SRTC time and stores it in the given time structure. - * - * @param base SNVS peripheral base address - * @param datetime Pointer to the structure where the date and time details are stored. - */ -void SNVS_LP_SRTC_GetDatetime(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime); - -/*! - * @brief Sets the SNVS SRTC alarm time. - * - * The function sets the SRTC alarm. It also checks whether the specified alarm - * time is greater than the present time. If not, the function does not set the alarm - * and returns an error. - * Please note, that SRTC alarm has limited resolution because only 32 most - * significant bits of SRTC counter are compared to SRTC Alarm register. - * If the alarm time is beyond SRTC resolution, the function does not set the alarm - * and returns an error. - * - * @param base SNVS peripheral base address - * @param alarmTime Pointer to the structure where the alarm time is stored. - * - * @return kStatus_Success: success in setting the SNVS SRTC alarm - * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect - * kStatus_Fail: Error because the alarm time has already passed or is beyond resolution - */ -status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *alarmTime); - -/*! - * @brief Returns the SNVS SRTC alarm time. - * - * @param base SNVS peripheral base address - * @param datetime Pointer to the structure where the alarm date and time details are stored. - */ -void SNVS_LP_SRTC_GetAlarm(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime); - -/*! @}*/ - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected SNVS interrupts. - * - * @param base SNVS peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::snvs_interrupt_enable_t - */ -static inline void SNVS_LP_SRTC_EnableInterrupts(SNVS_Type *base, uint32_t mask) -{ - base->LPCR |= mask; -} - -/*! - * @brief Disables the selected SNVS interrupts. - * - * @param base SNVS peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::snvs_interrupt_enable_t - */ -static inline void SNVS_LP_SRTC_DisableInterrupts(SNVS_Type *base, uint32_t mask) -{ - base->LPCR &= ~mask; -} - -/*! - * @brief Gets the enabled SNVS interrupts. - * - * @param base SNVS peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::snvs_interrupt_enable_t - */ -uint32_t SNVS_LP_SRTC_GetEnabledInterrupts(SNVS_Type *base); - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the SNVS status flags. - * - * @param base SNVS peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::snvs_status_flags_t - */ -uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base); - -/*! - * @brief Clears the SNVS status flags. - * - * @param base SNVS peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::snvs_status_flags_t - */ -static inline void SNVS_LP_SRTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask) -{ - base->LPSR |= mask; -} - -/*! @}*/ - -/*! - * @name Timer Start and Stop - * @{ - */ - -/*! - * @brief Starts the SNVS SRTC time counter. - * - * @param base SNVS peripheral base address - */ -static inline void SNVS_LP_SRTC_StartTimer(SNVS_Type *base) -{ - base->LPCR |= SNVS_LPCR_SRTC_ENV_MASK; - while (!(base->LPCR & SNVS_LPCR_SRTC_ENV_MASK)) - { - } -} - -/*! - * @brief Stops the SNVS SRTC time counter. - * - * @param base SNVS peripheral base address - */ -static inline void SNVS_LP_SRTC_StopTimer(SNVS_Type *base) -{ - base->LPCR &= ~SNVS_LPCR_SRTC_ENV_MASK; - while (base->LPCR & SNVS_LPCR_SRTC_ENV_MASK) - { - } -} - -/*! @}*/ - -/*! - * @name External tampering - * @{ - */ - -/*! - * @brief Enables the specified SNVS external tamper. - * - * @param base SNVS peripheral base address - * @param pin SNVS external tamper pin - * @param polarity Polarity of external tamper - */ -void SNVS_LP_EnableExternalTamper(SNVS_Type *base, - snvs_lp_external_tamper_t pin, - snvs_lp_external_tamper_polarity_t polarity); - -/*! - * @brief Disables the specified SNVS external tamper. - * - * @param base SNVS peripheral base address - * @param pin SNVS external tamper pin - */ -void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin); - -/*! - * @brief Returns status of the specified external tamper. - * - * @param base SNVS peripheral base address - * @param pin SNVS external tamper pin - * - * @return The status flag. This is the enumeration ::snvs_external_tamper_status_t - */ -snvs_lp_external_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin); - -/*! - * @brief Clears status of the specified external tamper. - * - * @param base SNVS peripheral base address - * @param pin SNVS external tamper pin - */ -void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin); - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SNVS_LP_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_spdif.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_spdif.c deleted file mode 100644 index 80b3229e20..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_spdif.c +++ /dev/null @@ -1,678 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2017, NXP Semiconductor, Inc. - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_spdif.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.spdif" -#endif - - -/******************************************************************************* - * Definitations - ******************************************************************************/ -enum _spdif_transfer_state -{ - kSPDIF_Busy = 0x0U, /*!< SPDIF is busy */ - kSPDIF_Idle, /*!< Transfer is done. */ - kSPDIF_Error /*!< Transfer error occured. */ -}; - -/*! @brief Typedef for spdif tx interrupt handler. */ -typedef void (*spdif_isr_t)(SPDIF_Type *base, spdif_handle_t *handle); -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the instance number for SPDIF. - * - * @param base SPDIF base pointer. - */ -uint32_t SPDIF_GetInstance(SPDIF_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Base pointer array */ -static SPDIF_Type *const s_spdifBases[] = SPDIF_BASE_PTRS; -/*! @brief SPDIF handle pointer */ -spdif_handle_t *s_spdifHandle[ARRAY_SIZE(s_spdifBases)][2]; -/* IRQ number array */ -static const IRQn_Type s_spdifIRQ[] = SPDIF_IRQS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Clock name array */ -static const clock_ip_name_t s_spdifClock[] = SPDIF_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -/*! @brief Pointer to IRQ handler for each instance. */ -static spdif_isr_t s_spdifTxIsr; -/*! @brief Pointer to IRQ handler for each instance. */ -static spdif_isr_t s_spdifRxIsr; -/*! @brief Used for spdif gain */ -static uint8_t s_spdif_gain[8] = {24U, 16U, 12U, 8U, 6U, 4U, 3U, 1U}; -static uint8_t s_spdif_tx_watermark[4] = {16, 12, 8, 4}; -static uint8_t s_spdif_rx_watermark[4] = {1, 4, 8, 16}; - -/******************************************************************************* - * Code - ******************************************************************************/ -uint32_t SPDIF_GetInstance(SPDIF_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_spdifBases); instance++) - { - if (s_spdifBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_spdifBases)); - - return instance; -} - -void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config) -{ - uint32_t val = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the SPDIF clock */ - CLOCK_EnableClock(s_spdifClock[SPDIF_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the internal logic */ - base->SCR |= SPDIF_SCR_SOFT_RESET_MASK; - - /* Waiting for reset finish */ - while (base->SCR & SPDIF_SCR_SOFT_RESET_MASK) - { - } - - /* Setting the SPDIF settings */ - base->SCR = SPDIF_SCR_RXFIFOFULL_SEL(config->rxFullSelect) | SPDIF_SCR_RXAUTOSYNC(config->isRxAutoSync) | - SPDIF_SCR_TXAUTOSYNC(config->isRxAutoSync) | SPDIF_SCR_TXFIFOEMPTY_SEL(config->txFullSelect) | - SPDIF_SCR_TXFIFO_CTRL(1U) | SPDIF_SCR_VALCTRL(config->validityConfig) | - SPDIF_SCR_TXSEL(config->txSource) | SPDIF_SCR_USRC_SEL(config->uChannelSrc); - - /* Set DPLL clock source */ - base->SRPC = SPDIF_SRPC_CLKSRC_SEL(config->DPLLClkSource) | SPDIF_SRPC_GAINSEL(config->gain); - - /* Set SPDIF tx clock source */ - val = base->STC & ~SPDIF_STC_TXCLK_SOURCE_MASK; - val |= SPDIF_STC_TXCLK_SOURCE(config->txClkSource); - base->STC = val; -} - -void SPDIF_Deinit(SPDIF_Type *base) -{ - SPDIF_TxEnable(base, false); - SPDIF_RxEnable(base, false); -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - CLOCK_DisableClock(s_spdifClock[SPDIF_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void SPDIF_GetDefaultConfig(spdif_config_t *config) -{ - config->isTxAutoSync = true; - config->isRxAutoSync = true; - config->DPLLClkSource = 1; - config->txClkSource = 1; - config->rxFullSelect = kSPDIF_RxFull8Samples; - config->txFullSelect = kSPDIF_TxEmpty8Samples; - config->uChannelSrc = kSPDIF_UChannelFromTx; - config->txSource = kSPDIF_txNormal; - config->validityConfig = kSPDIF_validityFlagAlwaysClear; - config->gain = kSPDIF_GAIN_8; -} - -void SPDIF_TxEnable(SPDIF_Type *base, bool enable) -{ - uint32_t val = 0; - - if (enable) - { - /* Open Tx FIFO */ - val = base->SCR & (~SPDIF_SCR_TXFIFO_CTRL_MASK); - val |= SPDIF_SCR_TXFIFO_CTRL(1U); - base->SCR = val; - /* Enable transfer clock */ - base->STC |= SPDIF_STC_TX_ALL_CLK_EN_MASK; - } - else - { - base->SCR &= ~(SPDIF_SCR_TXFIFO_CTRL_MASK | SPDIF_SCR_TXSEL_MASK); - /* Disable transfer clock */ - base->STC &= ~SPDIF_STC_TX_ALL_CLK_EN_MASK; - } -} - -void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz) -{ - uint32_t clkDiv = sourceClockFreq_Hz / (sampleRate_Hz * 64); - uint32_t mod = sourceClockFreq_Hz % (sampleRate_Hz * 64); - uint32_t val = 0; - uint8_t clockSource = (((base->STC) & SPDIF_STC_TXCLK_SOURCE_MASK) >> SPDIF_STC_TXCLK_SOURCE_SHIFT); - - /* Compute the nearest divider */ - if (mod > ((sampleRate_Hz * 64) / 2)) - { - clkDiv += 1U; - } - - /* If use divided systeme clock */ - if (clockSource == 5U) - { - if (clkDiv > 256) - { - val = base->STC & (~(SPDIF_STC_TXCLK_DF_MASK | SPDIF_STC_SYSCLK_DF_MASK)); - val |= SPDIF_STC_SYSCLK_DF(clkDiv / 128U - 1U) | SPDIF_STC_TXCLK_DF(127U); - base->STC = val; - } - else - { - val = base->STC & (~(SPDIF_STC_TXCLK_DF_MASK | SPDIF_STC_SYSCLK_DF_MASK)); - val |= SPDIF_STC_SYSCLK_DF(1U) | SPDIF_STC_TXCLK_DF(clkDiv - 1U); - base->STC = val; - } - } - else - { - /* Other clock only uses txclk div */ - val = base->STC & (~(SPDIF_STC_TXCLK_DF_MASK | SPDIF_STC_SYSCLK_DF_MASK)); - val |= SPDIF_STC_TXCLK_DF(clkDiv - 1U); - base->STC = val; - } -} - -uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz) -{ - uint32_t gain = s_spdif_gain[((base->SRPC & SPDIF_SRPC_GAINSEL_MASK) >> SPDIF_SRPC_GAINSEL_SHIFT)]; - uint32_t measure = 0, sampleRate = 0; - uint64_t temp = 0; - - /* Wait the DPLL locked */ - while ((base->SRPC & SPDIF_SRPC_LOCK_MASK) == 0U) - { - } - - /* Get the measure value */ - measure = base->SRFM; - temp = (uint64_t)measure * (uint64_t)clockSourceFreq_Hz; - temp /= (uint64_t)(1024 * 1024 * 128 * gain); - sampleRate = (uint32_t)temp; - - return sampleRate; -} - -void SPDIF_WriteBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size) -{ - assert(buffer); - assert(size / 6U == 0U); - - uint32_t i = 0, j = 0, data = 0; - - while (i < size) - { - /* Wait until it can write data */ - while ((SPDIF_GetStatusFlag(base) & kSPDIF_TxFIFOEmpty) == 0U) - { - } - - /* Write left channel data */ - for (j = 0; j < 3U; j++) - { - data |= ((uint32_t)(*buffer) << (j * 8U)); - buffer++; - } - SPDIF_WriteLeftData(base, data); - - /* Write right channel data */ - data = 0; - for (j = 0; j < 3U; j++) - { - data |= ((uint32_t)(*buffer) << (j * 8U)); - buffer++; - } - SPDIF_WriteRightData(base, data); - - i += 6U; - } -} - -void SPDIF_ReadBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size) -{ - assert(buffer); - assert(size / 6U == 0U); - - uint32_t i = 0, j = 0, data = 0; - - while (i < size) - { - /* Wait until it can write data */ - while ((SPDIF_GetStatusFlag(base) & kSPDIF_RxFIFOFull) == 0U) - { - } - - /* Write left channel data */ - data = SPDIF_ReadLeftData(base); - for (j = 0; j < 3U; j++) - { - *buffer = ((data >> (j * 8U)) & 0xFFU); - buffer++; - } - - /* Write right channel data */ - data = SPDIF_ReadRightData(base); - for (j = 0; j < 3U; j++) - { - *buffer = ((data >> (j * 8U)) & 0xFFU); - buffer++; - } - - i += 6U; - } -} - -void SPDIF_TransferTxCreateHandle(SPDIF_Type *base, - spdif_handle_t *handle, - spdif_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - s_spdifHandle[SPDIF_GetInstance(base)][0] = handle; - - handle->callback = callback; - handle->userData = userData; - handle->watermark = - s_spdif_tx_watermark[(base->SCR & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) >> SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT]; - - /* Set the isr pointer */ - s_spdifTxIsr = SPDIF_TransferTxHandleIRQ; - - /* Enable Tx irq */ - EnableIRQ(s_spdifIRQ[SPDIF_GetInstance(base)]); -} - -void SPDIF_TransferRxCreateHandle(SPDIF_Type *base, - spdif_handle_t *handle, - spdif_transfer_callback_t callback, - void *userData) -{ - assert(handle); - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - s_spdifHandle[SPDIF_GetInstance(base)][1] = handle; - - handle->callback = callback; - handle->userData = userData; - handle->watermark = - s_spdif_rx_watermark[(base->SCR & SPDIF_SCR_RXFIFOFULL_SEL_MASK) >> SPDIF_SCR_RXFIFOFULL_SEL_SHIFT]; - - /* Set the isr pointer */ - s_spdifRxIsr = SPDIF_TransferRxHandleIRQ; - - /* Enable Rx irq */ - EnableIRQ(s_spdifIRQ[SPDIF_GetInstance(base)]); -} - -status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer) -{ - assert(handle); - - /* Check if the queue is full */ - if (handle->spdifQueue[handle->queueUser].data) - { - return kStatus_SPDIF_QueueFull; - } - - /* Add into queue */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->spdifQueue[handle->queueUser].data = xfer->data; - handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; - - /* Set the state to busy */ - handle->state = kSPDIF_Busy; - - /* Enable interrupt */ - SPDIF_EnableInterrupts(base, kSPDIF_TxFIFOEmpty); - - /* Enable Tx transfer */ - SPDIF_TxEnable(base, true); - - return kStatus_Success; -} - -status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer) -{ - assert(handle); - - /* Check if the queue is full */ - if (handle->spdifQueue[handle->queueUser].data) - { - return kStatus_SPDIF_QueueFull; - } - - /* Add into queue */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->spdifQueue[handle->queueUser].data = xfer->data; - handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->spdifQueue[handle->queueUser].udata = xfer->udata; - handle->spdifQueue[handle->queueUser].qdata = xfer->qdata; - handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; - - /* Set state to busy */ - handle->state = kSPDIF_Busy; - - /* Enable interrupt */ - SPDIF_EnableInterrupts(base, kSPDIF_UChannelReceiveRegisterFull | kSPDIF_QChannelReceiveRegisterFull | - kSPDIF_RxFIFOFull | kSPDIF_RxControlChannelChange); - - /* Enable Rx transfer */ - SPDIF_RxEnable(base, true); - - return kStatus_Success; -} - -status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSPDIF_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - handle->spdifQueue[handle->queueDriver].dataSize); - } - - return status; -} - -status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSPDIF_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - handle->spdifQueue[handle->queueDriver].dataSize); - } - - return status; -} - -void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle) -{ - assert(handle); - - /* Use FIFO request interrupt and fifo error */ - SPDIF_DisableInterrupts(base, kSPDIF_TxFIFOEmpty); - - handle->state = kSPDIF_Idle; - - /* Clear the queue */ - memset(handle->spdifQueue, 0, sizeof(spdif_transfer_t) * SPDIF_XFER_QUEUE_SIZE); - handle->queueDriver = 0; - handle->queueUser = 0; -} - -void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle) -{ - assert(handle); - - /* Disable interrupt */ - SPDIF_DisableInterrupts(base, kSPDIF_UChannelReceiveRegisterFull | kSPDIF_QChannelReceiveRegisterFull | - kSPDIF_RxFIFOFull | kSPDIF_RxControlChannelChange); - - handle->state = kSPDIF_Idle; - - /* Clear the queue */ - memset(handle->spdifQueue, 0, sizeof(spdif_transfer_t) * SPDIF_XFER_QUEUE_SIZE); - handle->queueDriver = 0; - handle->queueUser = 0; -} - -void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) -{ - assert(handle); - - uint8_t *buffer = handle->spdifQueue[handle->queueDriver].data; - uint8_t dataSize = 0; - uint32_t i = 0, j = 0, data = 0; - - /* Do Transfer */ - if ((SPDIF_GetStatusFlag(base) & kSPDIF_TxFIFOEmpty) && (base->SIE & kSPDIF_TxFIFOEmpty)) - { - dataSize = handle->watermark; - while (i < dataSize) - { - data = 0; - /* Write left channel data */ - for (j = 0; j < 3U; j++) - { - data |= ((uint32_t)(*buffer) << (j * 8U)); - buffer++; - } - SPDIF_WriteLeftData(base, data); - - /* Write right channel data */ - data = 0; - for (j = 0; j < 3U; j++) - { - data |= ((uint32_t)(*buffer) << (j * 8U)); - buffer++; - } - SPDIF_WriteRightData(base, data); - - i++; - } - handle->spdifQueue[handle->queueDriver].dataSize -= dataSize * 6U; - handle->spdifQueue[handle->queueDriver].data += dataSize * 6U; - - /* If finished a blcok, call the callback function */ - if (handle->spdifQueue[handle->queueDriver].dataSize == 0U) - { - memset(&handle->spdifQueue[handle->queueDriver], 0, sizeof(spdif_transfer_t)); - handle->queueDriver = (handle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SPDIF_TxIdle, handle->userData); - } - } - - /* If all data finished, just stop the transfer */ - if (handle->spdifQueue[handle->queueDriver].data == NULL) - { - SPDIF_TransferAbortSend(base, handle); - } - } -} - -void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) -{ - assert(handle); - - uint8_t *buffer = NULL; - uint8_t dataSize = 0; - uint32_t i = 0, j = 0, data = 0; - - /* Handle Cnew flag */ - if (SPDIF_GetStatusFlag(base) & kSPDIF_RxControlChannelChange) - { - /* Clear the interrupt flag */ - SPDIF_ClearStatusFlags(base, SPDIF_SIE_CNEW_MASK); - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SPDIF_RxCnew, handle->userData); - } - } - - /* Handle illegal symbol */ - if (SPDIF_GetStatusFlag(base) & kSPDIF_RxIllegalSymbol) - { - SPDIF_ClearStatusFlags(base, kSPDIF_RxIllegalSymbol); - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SPDIF_RxIllegalSymbol, handle->userData); - } - } - - /* Handle Parity Bit Error */ - if (SPDIF_GetStatusFlag(base) & kSPDIF_RxParityBitError) - { - SPDIF_ClearStatusFlags(base, kSPDIF_RxParityBitError); - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SPDIF_RxParityBitError, handle->userData); - } - } - - /* Handle DPlocked */ - if (SPDIF_GetStatusFlag(base) & kSPDIF_RxDPLLLocked) - { - SPDIF_ClearStatusFlags(base, kSPDIF_RxDPLLLocked); - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SPDIF_RxDPLLLocked, handle->userData); - } - } - - /* Handle Q channel full flag */ - if ((SPDIF_GetStatusFlag(base) & kSPDIF_QChannelReceiveRegisterFull) && - (base->SIE & kSPDIF_QChannelReceiveRegisterFull)) - { - buffer = handle->spdifQueue[handle->queueDriver].qdata; - data = SPDIF_ReadQChannel(base); - buffer[0] = data & 0xFFU; - buffer[1] = (data >> 8U) & 0xFFU; - buffer[2] = (data >> 16U) & 0xFFU; - } - - /* Handle U channel full flag */ - if ((SPDIF_GetStatusFlag(base) & kSPDIF_UChannelReceiveRegisterFull) && - (base->SIE & kSPDIF_UChannelReceiveRegisterFull)) - { - buffer = handle->spdifQueue[handle->queueDriver].udata; - data = SPDIF_ReadUChannel(base); - buffer[0] = data & 0xFFU; - buffer[1] = (data >> 8U) & 0xFFU; - buffer[2] = (data >> 16U) & 0xFFU; - } - - /* Handle audio data transfer */ - if ((SPDIF_GetStatusFlag(base) & kSPDIF_RxFIFOFull) && (base->SIE & kSPDIF_RxFIFOFull)) - { - dataSize = handle->watermark; - buffer = handle->spdifQueue[handle->queueDriver].data; - while (i < dataSize) - { - /* Read left channel data */ - data = SPDIF_ReadLeftData(base); - for (j = 0; j < 3U; j++) - { - *buffer = ((data >> (j * 8U)) & 0xFFU); - buffer++; - } - - /* Read right channel data */ - data = SPDIF_ReadRightData(base); - for (j = 0; j < 3U; j++) - { - *buffer = ((data >> (j * 8U)) & 0xFFU); - buffer++; - } - - i++; - } - handle->spdifQueue[handle->queueDriver].dataSize -= dataSize * 6U; - handle->spdifQueue[handle->queueDriver].data += dataSize * 6U; - - /* If finished a blcok, call the callback function */ - if (handle->spdifQueue[handle->queueDriver].dataSize == 0U) - { - memset(&handle->spdifQueue[handle->queueDriver], 0, sizeof(spdif_transfer_t)); - handle->queueDriver = (handle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; - if (handle->callback) - { - (handle->callback)(base, handle, kStatus_SPDIF_RxIdle, handle->userData); - } - } - - /* If all data finished, just stop the transfer */ - if (handle->spdifQueue[handle->queueDriver].data == NULL) - { - SPDIF_TransferAbortReceive(base, handle); - } - } -} - -#if defined(SPDIF) -void SPDIF_DriverIRQHandler(void) -{ - if ((s_spdifHandle[0][0]) && s_spdifTxIsr) - { - s_spdifTxIsr(SPDIF, s_spdifHandle[0][0]); - } - - if ((s_spdifHandle[0][1]) && s_spdifRxIsr) - { - s_spdifRxIsr(SPDIF, s_spdifHandle[0][1]); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_spdif.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_spdif.h deleted file mode 100644 index ce852af544..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_spdif.h +++ /dev/null @@ -1,767 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_SPDIF_H_ -#define _FSL_SPDIF_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup spdif - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SPDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -/*! @brief SPDIF return status*/ -enum _spdif_status_t -{ - kStatus_SPDIF_RxDPLLLocked = MAKE_STATUS(kStatusGroup_SPDIF, 0), /*!< SPDIF Rx PLL locked. */ - kStatus_SPDIF_TxFIFOError = MAKE_STATUS(kStatusGroup_SPDIF, 1), /*!< SPDIF Tx FIFO error. */ - kStatus_SPDIF_TxFIFOResync = MAKE_STATUS(kStatusGroup_SPDIF, 2), /*!< SPDIF Tx left and right FIFO resync. */ - kStatus_SPDIF_RxCnew = MAKE_STATUS(kStatusGroup_SPDIF, 3), /*!< SPDIF Rx status channel value updated. */ - kStatus_SPDIF_ValidatyNoGood = MAKE_STATUS(kStatusGroup_SPDIF, 4), /*!< SPDIF validaty flag not good. */ - kStatus_SPDIF_RxIllegalSymbol = MAKE_STATUS(kStatusGroup_SPDIF, 5), /*!< SPDIF Rx receive illegal symbol. */ - kStatus_SPDIF_RxParityBitError = MAKE_STATUS(kStatusGroup_SPDIF, 6), /*!< SPDIF Rx parity bit error. */ - kStatus_SPDIF_UChannelOverrun = MAKE_STATUS(kStatusGroup_SPDIF, 7), /*!< SPDIF receive U channel overrun. */ - kStatus_SPDIF_QChannelOverrun = MAKE_STATUS(kStatusGroup_SPDIF, 8), /*!< SPDIF receive Q channel overrun. */ - kStatus_SPDIF_UQChannelSync = MAKE_STATUS(kStatusGroup_SPDIF, 9), /*!< SPDIF U/Q channel sync found. */ - kStatus_SPDIF_UQChannelFrameError = MAKE_STATUS(kStatusGroup_SPDIF, 10), /*!< SPDIF U/Q channel frame error. */ - kStatus_SPDIF_RxFIFOError = MAKE_STATUS(kStatusGroup_SPDIF, 11), /*!< SPDIF Rx FIFO error. */ - kStatus_SPDIF_RxFIFOResync = MAKE_STATUS(kStatusGroup_SPDIF, 12), /*!< SPDIF Rx left and right FIFO resync. */ - kStatus_SPDIF_LockLoss = MAKE_STATUS(kStatusGroup_SPDIF, 13), /*!< SPDIF Rx PLL clock lock loss. */ - kStatus_SPDIF_TxIdle = MAKE_STATUS(kStatusGroup_SPDIF, 14), /*!< SPDIF Tx is idle */ - kStatus_SPDIF_RxIdle = MAKE_STATUS(kStatusGroup_SPDIF, 15), /*!< SPDIF Rx is idle */ - kStatus_SPDIF_QueueFull = MAKE_STATUS(kStatusGroup_SPDIF, 16) /*!< SPDIF queue full */ -}; - -/*! @brief SPDIF Rx FIFO full falg select, it decides when assert the rx full flag */ -typedef enum _spdif_rxfull_select -{ - kSPDIF_RxFull1Sample = 0x0u, /*!< Rx full at least 1 sample in left and right FIFO */ - kSPDIF_RxFull4Samples, /*!< Rx full at least 4 sample in left and right FIFO*/ - kSPDIF_RxFull8Samples, /*!< Rx full at least 8 sample in left and right FIFO*/ - kSPDIF_RxFull16Samples, /*!< Rx full at least 16 sample in left and right FIFO*/ -} spdif_rxfull_select_t; - -/*! @brief SPDIF tx FIFO EMPTY falg select, it decides when assert the tx empty flag */ -typedef enum _spdif_txempty_select -{ - kSPDIF_TxEmpty0Sample = 0x0u, /*!< Tx empty at most 0 sample in left and right FIFO */ - kSPDIF_TxEmpty4Samples, /*!< Tx empty at most 4 sample in left and right FIFO*/ - kSPDIF_TxEmpty8Samples, /*!< Tx empty at most 8 sample in left and right FIFO*/ - kSPDIF_TxEmpty12Samples, /*!< Tx empty at most 12 sample in left and right FIFO*/ -} spdif_txempty_select_t; - -/*! @brief SPDIF U channel source */ -typedef enum _spdif_uchannel_source -{ - kSPDIF_NoUChannel = 0x0U, /*!< No embedded U channel */ - kSPDIF_UChannelFromRx = 0x1U, /*!< U channel from receiver, it is CD mode */ - kSPDIF_UChannelFromTx = 0x3U, /*!< U channel from on chip tx */ -} spdif_uchannel_source_t; - -/*! @brief SPDIF clock gain*/ -typedef enum _spdif_gain_select -{ - kSPDIF_GAIN_24 = 0x0U, /*!< Gain select is 24 */ - kSPDIF_GAIN_16, /*!< Gain select is 16 */ - kSPDIF_GAIN_12, /*!< Gain select is 12 */ - kSPDIF_GAIN_8, /*!< Gain select is 8 */ - kSPDIF_GAIN_6, /*!< Gain select is 6 */ - kSPDIF_GAIN_4, /*!< Gain select is 4 */ - kSPDIF_GAIN_3, /*!< Gain select is 3 */ -} spdif_gain_select_t; - -/*! @brief SPDIF tx data source */ -typedef enum _spdif_tx_source -{ - kSPDIF_txFromReceiver = 0x1U, /*!< Tx data directly through SPDIF receiver */ - kSPDIF_txNormal = 0x5U, /*!< Normal operation, data from processor */ -} spdif_tx_source_t; - -/*! @brief SPDIF tx data source */ -typedef enum _spdif_validity_config -{ - kSPDIF_validityFlagAlwaysSet = 0x0U, /*!< Outgoing validity flags always set */ - kSPDIF_validityFlagAlwaysClear, /*!< Outgoing validity flags always clear */ -} spdif_validity_config_t; - -/*! @brief The SPDIF interrupt enable flag */ -enum _spdif_interrupt_enable_t -{ - kSPDIF_RxDPLLLocked = SPDIF_SIE_LOCK_MASK, /*!< SPDIF DPLL locked */ - kSPDIF_TxFIFOError = SPDIF_SIE_TXUNOV_MASK, /*!< Tx FIFO underrun or overrun */ - kSPDIF_TxFIFOResync = SPDIF_SIE_TXRESYN_MASK, /*!< Tx FIFO left and right channel resync */ - kSPDIF_RxControlChannelChange = SPDIF_SIE_CNEW_MASK, /*!< SPDIF Rx control channel value changed */ - kSPDIF_ValidityFlagNoGood = SPDIF_SIE_VALNOGOOD_MASK, /*!< SPDIF validity flag no good */ - kSPDIF_RxIllegalSymbol = SPDIF_SIE_SYMERR_MASK, /*!< SPDIF receiver found illegal symbol */ - kSPDIF_RxParityBitError = SPDIF_SIE_BITERR_MASK, /*!< SPDIF receiver found parity bit error */ - kSPDIF_UChannelReceiveRegisterFull = SPDIF_SIE_URXFUL_MASK, /*!< SPDIF U channel revceive register full */ - kSPDIF_UChannelReceiveRegisterOverrun = SPDIF_SIE_URXOV_MASK, /*!< SPDIF U channel receive register overrun */ - kSPDIF_QChannelReceiveRegisterFull = SPDIF_SIE_QRXFUL_MASK, /*!< SPDIF Q channel receive reigster full */ - kSPDIF_QChannelReceiveRegisterOverrun = SPDIF_SIE_QRXOV_MASK, /*!< SPDIF Q channel receive register overrun */ - kSPDIF_UQChannelSync = SPDIF_SIE_UQSYNC_MASK, /*!< SPDIF U/Q channel sync found */ - kSPDIF_UQChannelFrameError = SPDIF_SIE_UQERR_MASK, /*!< SPDIF U/Q channel frame error */ - kSPDIF_RxFIFOError = SPDIF_SIE_RXFIFOUNOV_MASK, /*!< SPDIF Rx FIFO underrun/overrun */ - kSPDIF_RxFIFOResync = SPDIF_SIE_RXFIFORESYN_MASK, /*!< SPDIF Rx left and right FIFO resync */ - kSPDIF_LockLoss = SPDIF_SIE_LOCKLOSS_MASK, /*!< SPDIF receiver loss of lock */ - kSPDIF_TxFIFOEmpty = SPDIF_SIE_TXEM_MASK, /*!< SPDIF Tx FIFO empty */ - kSPDIF_RxFIFOFull = SPDIF_SIE_RXFIFOFUL_MASK /*!< SPDIF Rx FIFO full */ -}; - -/*! @brief The DMA request sources */ -enum _spdif_dma_enable_t -{ - kSPDIF_RxDMAEnable = SPDIF_SCR_DMA_RX_EN_MASK, /*!< Rx FIFO full */ - kSPDIF_TxDMAEnable = SPDIF_SCR_DMA_TX_EN_MASK, /*!< Tx FIFO empty */ -}; - -/*! @brief SPDIF user configuration structure */ -typedef struct _spdif_config -{ - bool isTxAutoSync; /*!< If auto sync mechanism open */ - bool isRxAutoSync; /*!< If auto sync mechanism open */ - uint8_t DPLLClkSource; /*!< SPDIF DPLL clock source, range from 0~15, meaning is chip-specific */ - uint8_t txClkSource; /*!< SPDIF tx clock source, range from 0~7, meaning is chip-specific */ - spdif_rxfull_select_t rxFullSelect; /*!< SPDIF rx buffer full select */ - spdif_txempty_select_t txFullSelect; /*!< SPDIF tx buffer empty select */ - spdif_uchannel_source_t uChannelSrc; /*!< U channel source */ - spdif_tx_source_t txSource; /*!< SPDIF tx data source */ - spdif_validity_config_t validityConfig; /*!< Validity flag config */ - spdif_gain_select_t gain; /*!< Rx receive clock measure gain parameter. */ -} spdif_config_t; - -/*!@brief SPDIF transfer queue size, user can refine it according to use case. */ -#define SPDIF_XFER_QUEUE_SIZE (4) - -/*! @brief SPDIF transfer structure */ -typedef struct _spdif_transfer -{ - uint8_t *data; /*!< Data start address to transfer. */ - uint8_t *qdata; /*!< Data buffer for Q channel */ - uint8_t *udata; /*!< Data buffer for C channel */ - size_t dataSize; /*!< Transfer size. */ -} spdif_transfer_t; - -typedef struct _spdif_handle spdif_handle_t; - -/*! @brief SPDIF transfer callback prototype */ -typedef void (*spdif_transfer_callback_t)(SPDIF_Type *base, spdif_handle_t *handle, status_t status, void *userData); - -/*! @brief SPDIF handle structure */ -struct _spdif_handle -{ - uint32_t state; /*!< Transfer status */ - spdif_transfer_callback_t callback; /*!< Callback function called at transfer event*/ - void *userData; /*!< Callback parameter passed to callback function*/ - spdif_transfer_t spdifQueue[SPDIF_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ - size_t transferSize[SPDIF_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ - volatile uint8_t queueUser; /*!< Index for user to queue transfer */ - volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ - uint8_t watermark; /*!< Watermark value */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus*/ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes the SPDIF peripheral. - * - * Ungates the SPDIF clock, resets the module, and configures SPDIF with a configuration structure. - * The configuration structure can be custom filled or set with default values by - * SPDIF_GetDefaultConfig(). - * - * @note This API should be called at the beginning of the application to use - * the SPDIF driver. Otherwise, accessing the SPDIF module can cause a hard fault - * because the clock is not enabled. - * - * @param base SPDIF base pointer - * @param config SPDIF configuration structure. -*/ -void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config); - -/*! - * @brief Sets the SPDIF configuration structure to default values. - * - * This API initializes the configuration structure for use in SPDIF_Init. - * The initialized structure can remain unchanged in SPDIF_Init, or it can be modified - * before calling SPDIF_Init. - * This is an example. - @code - spdif_config_t config; - SPDIF_GetDefaultConfig(&config); - @endcode - * - * @param config pointer to master configuration structure - */ -void SPDIF_GetDefaultConfig(spdif_config_t *config); - -/*! - * @brief De-initializes the SPDIF peripheral. - * - * This API gates the SPDIF clock. The SPDIF module can't operate unless SPDIF_Init is called to enable the clock. - * - * @param base SPDIF base pointer -*/ -void SPDIF_Deinit(SPDIF_Type *base); - -/*! - * @brief Resets the SPDIF Tx. - * - * This function makes Tx FIFO in reset mode. - * - * @param base SPDIF base pointer - */ -static inline void SPDIF_TxFIFOReset(SPDIF_Type *base) -{ - base->SCR |= SPDIF_SCR_RXFIFO_RST_MASK; -} - -/*! - * @brief Resets the SPDIF Rx. - * - * This function enables the software reset and FIFO reset of SPDIF Rx. After reset, clear the reset bit. - * - * @param base SPDIF base pointer - */ -static inline void SPDIF_RxFIFOReset(SPDIF_Type *base) -{ - base->SCR |= SPDIF_SCR_RXFIFO_RST_MASK; -} - -/*! - * @brief Enables/disables the SPDIF Tx. - * - * @param base SPDIF base pointer - * @param enable True means enable SPDIF Tx, false means disable. - */ -void SPDIF_TxEnable(SPDIF_Type *base, bool enable); - -/*! - * @brief Enables/disables the SPDIF Rx. - * - * @param base SPDIF base pointer - * @param enable True means enable SPDIF Rx, false means disable. - */ -static inline void SPDIF_RxEnable(SPDIF_Type *base, bool enable) -{ - if (enable) - { - /* Open Rx FIFO */ - base->SCR &= ~(SPDIF_SCR_RXFIFO_CTRL_MASK | SPDIF_SCR_RXFIFO_OFF_ON_MASK); - } - else - { - base->SCR |= SPDIF_SCR_RXFIFO_OFF_ON_MASK; - } -} - -/*! @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the SPDIF status flag state. - * - * @param base SPDIF base pointer - * @return SPDIF status flag value. Use the _spdif_interrupt_enable_t to get the status value needed. - */ -static inline uint32_t SPDIF_GetStatusFlag(SPDIF_Type *base) -{ - return base->SIS; -} - -/*! - * @brief Clears the SPDIF status flag state. - * - * @param base SPDIF base pointer - * @param mask State mask. It can be a combination of the _spdif_interrupt_enable_t member. Notice these members - * cannot be included, as these flags cannot be cleared by writing 1 to these bits: - * @arg kSPDIF_UChannelReceiveRegisterFull - * @arg kSPDIF_QChannelReceiveRegisterFull - * @arg kSPDIF_TxFIFOEmpty - * @arg kSPDIF_RxFIFOFull - */ -static inline void SPDIF_ClearStatusFlags(SPDIF_Type *base, uint32_t mask) -{ - base->SIC = mask; -} - -/*! @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the SPDIF Tx interrupt requests. - * - * @param base SPDIF base pointer - * @param mask interrupt source - * The parameter can be a combination of the following sources if defined. - * @arg kSPDIF_WordStartInterruptEnable - * @arg kSPDIF_SyncErrorInterruptEnable - * @arg kSPDIF_FIFOWarningInterruptEnable - * @arg kSPDIF_FIFORequestInterruptEnable - * @arg kSPDIF_FIFOErrorInterruptEnable - */ -static inline void SPDIF_EnableInterrupts(SPDIF_Type *base, uint32_t mask) -{ - base->SIE |= mask; -} - -/*! - * @brief Disables the SPDIF Tx interrupt requests. - * - * @param base SPDIF base pointer - * @param mask interrupt source - * The parameter can be a combination of the following sources if defined. - * @arg kSPDIF_WordStartInterruptEnable - * @arg kSPDIF_SyncErrorInterruptEnable - * @arg kSPDIF_FIFOWarningInterruptEnable - * @arg kSPDIF_FIFORequestInterruptEnable - * @arg kSPDIF_FIFOErrorInterruptEnable - */ -static inline void SPDIF_DisableInterrupts(SPDIF_Type *base, uint32_t mask) -{ - base->SIE &= ~mask; -} - -/*! @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Enables/disables the SPDIF DMA requests. - * @param base SPDIF base pointer - * @param mask SPDIF DMA enable mask, The parameter can be a combination of the following sources if defined - * @arg kSPDIF_RxDMAEnable - * @arg kSPDIF_TxDMAEnable - * @param enable True means enable DMA, false means disable DMA. - */ -static inline void SPDIF_EnableDMA(SPDIF_Type *base, uint32_t mask, bool enable) -{ - if (enable) - { - base->SCR |= mask; - } - else - { - base->SCR &= ~mask; - } -} - -/*! - * @brief Gets the SPDIF Tx left data register address. - * - * This API is used to provide a transfer address for the SPDIF DMA transfer configuration. - * - * @param base SPDIF base pointer. - * @return data register address. - */ -static inline uint32_t SPDIF_TxGetLeftDataRegisterAddress(SPDIF_Type *base) -{ - return (uint32_t)(&(base->STL)); -} - -/*! - * @brief Gets the SPDIF Tx right data register address. - * - * This API is used to provide a transfer address for the SPDIF DMA transfer configuration. - * - * @param base SPDIF base pointer. - * @return data register address. - */ -static inline uint32_t SPDIF_TxGetRightDataRegisterAddress(SPDIF_Type *base) -{ - return (uint32_t)(&(base->STR)); -} - -/*! - * @brief Gets the SPDIF Rx left data register address. - * - * This API is used to provide a transfer address for the SPDIF DMA transfer configuration. - * - * @param base SPDIF base pointer. - * @return data register address. - */ -static inline uint32_t SPDIF_RxGetLeftDataRegisterAddress(SPDIF_Type *base) -{ - return (uint32_t)(&(base->SRL)); -} - -/*! - * @brief Gets the SPDIF Rx right data register address. - * - * This API is used to provide a transfer address for the SPDIF DMA transfer configuration. - * - * @param base SPDIF base pointer. - * @return data register address. - */ -static inline uint32_t SPDIF_RxGetRightDataRegisterAddress(SPDIF_Type *base) -{ - return (uint32_t)(&(base->SRR)); -} - -/*! @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Configures the SPDIF Tx sample rate. - * - * The audio format can be changed at run-time. This function configures the sample rate. - * - * @param base SPDIF base pointer. - * @param sampleRate_Hz SPDIF sample rate frequency in Hz. - * @param sourceClockFreq_Hz SPDIF tx clock source frequency in Hz. -*/ -void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz); - -/*! - * @brief Configures the SPDIF Rx audio format. - * - * The audio format can be changed at run-time. This function configures the sample rate and audio data - * format to be transferred. - * - * @param base SPDIF base pointer. - * @param clockSourceFreq_Hz SPDIF system clock frequency in hz. - */ -uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz); - -/*! - * @brief Sends data using a blocking method. - * - * @note This function blocks by polling until data is ready to be sent. - * - * @param base SPDIF base pointer. - * @param buffer Pointer to the data to be written. - * @param size Bytes to be written. - */ -void SPDIF_WriteBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size); - -/*! - * @brief Writes data into SPDIF FIFO. - * - * @param base SPDIF base pointer. - * @param data Data needs to be written. - */ -static inline void SPDIF_WriteLeftData(SPDIF_Type *base, uint32_t data) -{ - base->STL = data; -} - -/*! - * @brief Writes data into SPDIF FIFO. - * - * @param base SPDIF base pointer. - * @param data Data needs to be written. - */ -static inline void SPDIF_WriteRightData(SPDIF_Type *base, uint32_t data) -{ - base->STR = data; -} - -/*! - * @brief Writes data into SPDIF FIFO. - * - * @param base SPDIF base pointer. - * @param data Data needs to be written. - */ -static inline void SPDIF_WriteChannelStatusHigh(SPDIF_Type *base, uint32_t data) -{ - base->STCSCH = data; -} - -/*! - * @brief Writes data into SPDIF FIFO. - * - * @param base SPDIF base pointer. - * @param data Data needs to be written. - */ -static inline void SPDIF_WriteChannelStatusLow(SPDIF_Type *base, uint32_t data) -{ - base->STCSCL = data; -} - -/*! - * @brief Receives data using a blocking method. - * - * @note This function blocks by polling until data is ready to be sent. - * - * @param base SPDIF base pointer. - * @param buffer Pointer to the data to be read. - * @param size Bytes to be read. - */ -void SPDIF_ReadBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size); - -/*! - * @brief Reads data from the SPDIF FIFO. - * - * @param base SPDIF base pointer. - * @return Data in SPDIF FIFO. - */ -static inline uint32_t SPDIF_ReadLeftData(SPDIF_Type *base) -{ - return base->SRL; -} - -/*! - * @brief Reads data from the SPDIF FIFO. - *. - - * @param base SPDIF base pointer. - * @return Data in SPDIF FIFO. - */ -static inline uint32_t SPDIF_ReadRightData(SPDIF_Type *base) -{ - return base->SRR; -} - -/*! - * @brief Reads data from the SPDIF FIFO. - * - * @param base SPDIF base pointer. - * @return Data in SPDIF FIFO. - */ -static inline uint32_t SPDIF_ReadChannelStatusHigh(SPDIF_Type *base) -{ - return base->SRCSH; -} - -/*! - * @brief Reads data from the SPDIF FIFO. - *. - - * @param base SPDIF base pointer. - * @return Data in SPDIF FIFO. - */ -static inline uint32_t SPDIF_ReadChannelStatusLow(SPDIF_Type *base) -{ - return base->SRCSL; -} - -/*! - * @brief Reads data from the SPDIF FIFO. - * - * @param base SPDIF base pointer. - * @return Data in SPDIF FIFO. - */ -static inline uint32_t SPDIF_ReadQChannel(SPDIF_Type *base) -{ - return base->SRQ; -} - -/*! - * @brief Reads data from the SPDIF FIFO. - *. - - * @param base SPDIF base pointer. - * @return Data in SPDIF FIFO. - */ -static inline uint32_t SPDIF_ReadUChannel(SPDIF_Type *base) -{ - return base->SRU; -} - -/*! @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the SPDIF Tx handle. - * - * This function initializes the Tx handle for the SPDIF Tx transactional APIs. Call - * this function once to get the handle initialized. - * - * @param base SPDIF base pointer - * @param handle SPDIF handle pointer. - * @param callback Pointer to the user callback function. - * @param userData User parameter passed to the callback function - */ -void SPDIF_TransferTxCreateHandle(SPDIF_Type *base, - spdif_handle_t *handle, - spdif_transfer_callback_t callback, - void *userData); - -/*! - * @brief Initializes the SPDIF Rx handle. - * - * This function initializes the Rx handle for the SPDIF Rx transactional APIs. Call - * this function once to get the handle initialized. - * - * @param base SPDIF base pointer. - * @param handle SPDIF handle pointer. - * @param callback Pointer to the user callback function. - * @param userData User parameter passed to the callback function. - */ -void SPDIF_TransferRxCreateHandle(SPDIF_Type *base, - spdif_handle_t *handle, - spdif_transfer_callback_t callback, - void *userData); - -/*! - * @brief Performs an interrupt non-blocking send transfer on SPDIF. - * - * @note This API returns immediately after the transfer initiates. - * Call the SPDIF_TxGetTransferStatusIRQ to poll the transfer status and check whether - * the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer - * is finished. - * - * @param base SPDIF base pointer. - * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. - * @param xfer Pointer to the spdif_transfer_t structure. - * @retval kStatus_Success Successfully started the data receive. - * @retval kStatus_SPDIF_TxBusy Previous receive still not finished. - * @retval kStatus_InvalidArgument The input parameter is invalid. - */ -status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer); - -/*! - * @brief Performs an interrupt non-blocking receive transfer on SPDIF. - * - * @note This API returns immediately after the transfer initiates. - * Call the SPDIF_RxGetTransferStatusIRQ to poll the transfer status and check whether - * the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer - * is finished. - * - * @param base SPDIF base pointer - * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. - * @param xfer Pointer to the spdif_transfer_t structure. - * @retval kStatus_Success Successfully started the data receive. - * @retval kStatus_SPDIF_RxBusy Previous receive still not finished. - * @retval kStatus_InvalidArgument The input parameter is invalid. - */ -status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer); - -/*! - * @brief Gets a set byte count. - * - * @param base SPDIF base pointer. - * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. - * @param count Bytes count sent. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count); - -/*! - * @brief Gets a received byte count. - * - * @param base SPDIF base pointer. - * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. - * @param count Bytes count received. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. - */ -status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count); - -/*! - * @brief Aborts the current send. - * - * @note This API can be called any time when an interrupt non-blocking transfer initiates - * to abort the transfer early. - * - * @param base SPDIF base pointer. - * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. - */ -void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle); - -/*! - * @brief Aborts the current IRQ receive. - * - * @note This API can be called when an interrupt non-blocking transfer initiates - * to abort the transfer early. - * - * @param base SPDIF base pointer - * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. - */ -void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle); - -/*! - * @brief Tx interrupt handler. - * - * @param base SPDIF base pointer. - * @param handle Pointer to the spdif_handle_t structure. - */ -void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle); - -/*! - * @brief Tx interrupt handler. - * - * @param base SPDIF base pointer. - * @param handle Pointer to the spdif_handle_t structure. - */ -void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle); - -/*! @} */ - -#if defined(__cplusplus) -} -#endif /*_cplusplus*/ - -/*! @} */ - -#endif /* _FSL_SPDIF_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_spdif_edma.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_spdif_edma.c deleted file mode 100644 index 79cc2ff05d..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_spdif_edma.c +++ /dev/null @@ -1,521 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_spdif_edma.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.spdif_edma" -#endif - - -/******************************************************************************* - * Definitations - ******************************************************************************/ -/* Used for 32byte aligned */ -#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)address + 32) & ~0x1FU) - -/*handle; - - /* If finished a blcok, call the callback function */ - memset(&spdifHandle->spdifQueue[spdifHandle->queueDriver], 0, sizeof(spdif_edma_transfer_t)); - spdifHandle->queueDriver = (spdifHandle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; - if (spdifHandle->callback) - { - (spdifHandle->callback)(privHandle->base, spdifHandle, kStatus_SPDIF_TxIdle, spdifHandle->userData); - } - - /* If all data finished, just stop the transfer */ - if (spdifHandle->spdifQueue[spdifHandle->queueDriver].rightData == NULL) - { - SPDIF_TransferAbortSendEDMA(privHandle->base, spdifHandle); - } -} - -static void SPDIF_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) -{ - spdif_edma_private_handle_t *privHandle = (spdif_edma_private_handle_t *)userData; - spdif_edma_handle_t *spdifHandle = privHandle->handle; - - /* If finished a blcok, call the callback function */ - memset(&spdifHandle->spdifQueue[spdifHandle->queueDriver], 0, sizeof(spdif_edma_transfer_t)); - spdifHandle->queueDriver = (spdifHandle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; - if (spdifHandle->callback) - { - (spdifHandle->callback)(privHandle->base, spdifHandle, kStatus_SPDIF_RxIdle, spdifHandle->userData); - } - - /* If all data finished, just stop the transfer */ - if (spdifHandle->spdifQueue[spdifHandle->queueDriver].rightData == NULL) - { - SPDIF_TransferAbortReceiveEDMA(privHandle->base, spdifHandle); - } -} - -static status_t SPDIF_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config, uint32_t rightChannel) -{ - edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - uint32_t primask; - uint32_t csr; - int8_t currentTcd; - int8_t previousTcd; - int8_t nextTcd; - - /* Check if tcd pool is full. */ - primask = DisableGlobalIRQ(); - if (handle->tcdUsed >= handle->tcdSize) - { - EnableGlobalIRQ(primask); - - return kStatus_EDMA_QueueFull; - } - currentTcd = handle->tail; - handle->tcdUsed++; - /* Calculate index of next TCD */ - nextTcd = currentTcd + 1U; - if (nextTcd == handle->tcdSize) - { - nextTcd = 0U; - } - /* Advance queue tail index */ - handle->tail = nextTcd; - EnableGlobalIRQ(primask); - /* Calculate index of previous TCD */ - previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U; - /* Configure current TCD block. */ - EDMA_TcdReset(&handle->tcdPool[currentTcd]); - EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); - /* Set channel link */ - EDMA_TcdSetChannelLink(&handle->tcdPool[currentTcd], kEDMA_MinorLink, rightChannel); - EDMA_TcdSetChannelLink(&handle->tcdPool[currentTcd], kEDMA_MajorLink, rightChannel); - /* Enable major interrupt */ - handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; - /* Link current TCD with next TCD for identification of current TCD */ - handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd]; - /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ - if (currentTcd != previousTcd) - { - /* Enable scatter/gather feature in the previous TCD block. */ - csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; - handle->tcdPool[previousTcd].CSR = csr; - /* - Check if the TCD blcok in the registers is the previous one (points to current TCD block). It - is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to - link the TCD register in case link the current TCD with the dead chain when TCD loading occurs - before link the previous TCD block. - */ - if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) - { - /* Enable scatter/gather also in the TCD registers. */ - csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; - /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ - tcdRegs->CSR = csr; - /* - It is very important to check the ESG bit! - Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can - be used to check if the dynamic TCD link operation is successful. If ESG bit is not set - and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and - the current TCD block has been loaded into TCD registers), it means transfer finished - and TCD link operation fail, so must install TCD content into TCD registers and enable - transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic - link succeed. - */ - if (tcdRegs->CSR & DMA_CSR_ESG_MASK) - { - return kStatus_Success; - } - /* - Check whether the current TCD block is already loaded in the TCD registers. It is another - condition when ESG bit is not set: it means the dynamic TCD link succeed and the current - TCD block has been loaded into TCD registers. - */ - if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd]) - { - return kStatus_Success; - } - /* - If go to this, means the previous transfer finished, and the DONE bit is set. - So shall configure TCD registers. - */ - } - else if (tcdRegs->DLAST_SGA != 0) - { - /* The current TCD block has been linked successfully. */ - return kStatus_Success; - } - else - { - /* - DLAST_SGA is 0 and it means the first submit transfer, so shall configure - TCD registers. - */ - } - } - /* There is no live chain, TCD block need to be installed in TCD registers. */ - EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); - /* Enable channel request again. */ - if (handle->flags & 0x80) - { - handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); - } - - return kStatus_Success; -} - -void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base, - spdif_edma_handle_t *handle, - spdif_edma_callback_t callback, - void *userData, - edma_handle_t *dmaLeftHandle, - edma_handle_t *dmaRightHandle) -{ - assert(handle && dmaLeftHandle && dmaRightHandle); - - uint32_t instance = SPDIF_GetInstance(base); - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - /* Set spdif base to handle */ - handle->dmaLeftHandle = dmaLeftHandle; - handle->dmaRightHandle = dmaRightHandle; - handle->callback = callback; - handle->userData = userData; - handle->count = - s_spdif_tx_watermark[(base->SCR & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) >> SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT]; - - /* Set SPDIF state to idle */ - handle->state = kSPDIF_Idle; - - s_edmaPrivateHandle[instance][0].base = base; - s_edmaPrivateHandle[instance][0].handle = handle; - - /* Need to use scatter gather */ - EDMA_InstallTCDMemory(dmaLeftHandle, STCD_ADDR(handle->leftTcd), SPDIF_XFER_QUEUE_SIZE); - EDMA_InstallTCDMemory(dmaRightHandle, STCD_ADDR(handle->rightTcd), SPDIF_XFER_QUEUE_SIZE); - - /* Install callback for Tx dma channel, only right channel finished, a transfer finished */ - EDMA_SetCallback(dmaRightHandle, SPDIF_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); -} - -void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base, - spdif_edma_handle_t *handle, - spdif_edma_callback_t callback, - void *userData, - edma_handle_t *dmaLeftHandle, - edma_handle_t *dmaRightHandle) -{ - assert(handle && dmaLeftHandle && dmaRightHandle); - - uint32_t instance = SPDIF_GetInstance(base); - - /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); - - /* Set spdif base to handle */ - handle->dmaLeftHandle = dmaLeftHandle; - handle->dmaRightHandle = dmaRightHandle; - handle->callback = callback; - handle->userData = userData; - handle->count = s_spdif_rx_watermark[(base->SCR & SPDIF_SCR_RXFIFOFULL_SEL_MASK) >> SPDIF_SCR_RXFIFOFULL_SEL_SHIFT]; - - /* Set SPDIF state to idle */ - handle->state = kSPDIF_Idle; - - s_edmaPrivateHandle[instance][1].base = base; - s_edmaPrivateHandle[instance][1].handle = handle; - - /* Need to use scatter gather */ - EDMA_InstallTCDMemory(dmaLeftHandle, STCD_ADDR(handle->leftTcd), SPDIF_XFER_QUEUE_SIZE); - EDMA_InstallTCDMemory(dmaRightHandle, STCD_ADDR(handle->rightTcd), SPDIF_XFER_QUEUE_SIZE); - - /* Install callback for Tx dma channel */ - EDMA_SetCallback(dmaRightHandle, SPDIF_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); -} - -status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer) -{ - assert(handle && xfer); - - edma_transfer_config_t config = {0}; - uint32_t destAddr = SPDIF_TxGetLeftDataRegisterAddress(base); - - /* Check if input parameter invalid */ - if ((xfer->leftData == NULL) || (xfer->dataSize == 0U) || (xfer->rightData == NULL)) - { - return kStatus_InvalidArgument; - } - - if ((handle->spdifQueue[handle->queueUser].leftData) || (handle->spdifQueue[handle->queueUser].rightData)) - { - return kStatus_SPDIF_QueueFull; - } - - /* Change the state of handle */ - handle->state = kSPDIF_Busy; - - /* Update the queue state */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->spdifQueue[handle->queueUser].leftData = xfer->leftData; - handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->spdifQueue[handle->queueUser].rightData = xfer->rightData; - handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; - - /* Store the initially configured eDMA minor byte transfer count into the SPDIF handle */ - handle->nbytes = handle->count * 8U; - - /* Prepare edma configure */ - EDMA_PrepareTransfer(&config, xfer->leftData, 4U, (void *)destAddr, 4U, handle->count * 4U, xfer->dataSize, - kEDMA_MemoryToPeripheral); - SPDIF_SubmitTransfer(handle->dmaLeftHandle, &config, handle->dmaRightHandle->channel); - - /* Prepare right channel */ - destAddr = SPDIF_TxGetRightDataRegisterAddress(base); - EDMA_PrepareTransfer(&config, xfer->rightData, 4U, (void *)destAddr, 4U, handle->count * 4U, xfer->dataSize, - kEDMA_MemoryToPeripheral); - EDMA_SubmitTransfer(handle->dmaRightHandle, &config); - - /* Start DMA transfer */ - EDMA_StartTransfer(handle->dmaLeftHandle); - EDMA_StartTransfer(handle->dmaRightHandle); - - /* Enable DMA enable bit */ - SPDIF_EnableDMA(base, kSPDIF_TxDMAEnable, true); - - /* Enable SPDIF Tx clock */ - SPDIF_TxEnable(base, true); - - return kStatus_Success; -} - -status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer) -{ - assert(handle && xfer); - - edma_transfer_config_t config = {0}; - uint32_t srcAddr = SPDIF_RxGetLeftDataRegisterAddress(base); - - /* Check if input parameter invalid */ - if ((xfer->leftData == NULL) || (xfer->dataSize == 0U) || (xfer->rightData == NULL)) - { - return kStatus_InvalidArgument; - } - - if ((handle->spdifQueue[handle->queueUser].leftData) || (handle->spdifQueue[handle->queueUser].rightData)) - { - return kStatus_SPDIF_QueueFull; - } - - /* Change the state of handle */ - handle->state = kSPDIF_Busy; - - /* Update the queue state */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->spdifQueue[handle->queueUser].leftData = xfer->leftData; - handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->spdifQueue[handle->queueUser].rightData = xfer->rightData; - handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; - - /* Store the initially configured eDMA minor byte transfer count into the SPDIF handle */ - handle->nbytes = handle->count * 8U; - - /* Prepare edma configure */ - EDMA_PrepareTransfer(&config, (void *)srcAddr, 4U, xfer->leftData, 4U, handle->count * 4U, xfer->dataSize, - kEDMA_PeripheralToMemory); - /* Use specific submit function to enable channel link */ - SPDIF_SubmitTransfer(handle->dmaLeftHandle, &config, handle->dmaRightHandle->channel); - - /* Prepare right channel */ - srcAddr = SPDIF_RxGetRightDataRegisterAddress(base); - EDMA_PrepareTransfer(&config, (void *)srcAddr, 4U, xfer->rightData, 4U, handle->count * 4U, xfer->dataSize, - kEDMA_PeripheralToMemory); - EDMA_SubmitTransfer(handle->dmaRightHandle, &config); - - /* Start DMA transfer */ - EDMA_StartTransfer(handle->dmaLeftHandle); - EDMA_StartTransfer(handle->dmaRightHandle); - - /* Enable DMA enable bit */ - SPDIF_EnableDMA(base, kSPDIF_RxDMAEnable, true); - - /* Enable SPDIF Rx clock */ - SPDIF_RxEnable(base, true); - - return kStatus_Success; -} - -void SPDIF_TransferAbortSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle) -{ - assert(handle); - - /* Disable dma */ - EDMA_AbortTransfer(handle->dmaLeftHandle); - EDMA_AbortTransfer(handle->dmaRightHandle); - - /* Disable DMA enable bit */ - SPDIF_EnableDMA(base, kSPDIF_TxDMAEnable, false); - - /* Set internal state */ - memset(handle->spdifQueue, 0U, sizeof(handle->spdifQueue)); - memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; - handle->queueDriver = 0U; - - /* Set the handle state */ - handle->state = kSPDIF_Idle; -} - -void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle) -{ - assert(handle); - - /* Disable dma */ - EDMA_AbortTransfer(handle->dmaLeftHandle); - EDMA_AbortTransfer(handle->dmaRightHandle); - - /* Disable DMA enable bit */ - SPDIF_EnableDMA(base, kSPDIF_RxDMAEnable, false); - - /* Set internal state */ - memset(handle->spdifQueue, 0U, sizeof(handle->spdifQueue)); - memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; - handle->queueDriver = 0U; - - /* Set the handle state */ - handle->state = kSPDIF_Idle; -} - -status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSPDIF_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->dmaRightHandle->base, handle->dmaRightHandle->channel)); - } - - return status; -} - -status_t SPDIF_TransferGetReceiveCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count) -{ - assert(handle); - - status_t status = kStatus_Success; - - if (handle->state != kSPDIF_Busy) - { - status = kStatus_NoTransferInProgress; - } - else - { - *count = (handle->transferSize[handle->queueDriver] - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->dmaRightHandle->base, handle->dmaRightHandle->channel)); - } - - return status; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_spdif_edma.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_spdif_edma.h deleted file mode 100644 index 2815616f26..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_spdif_edma.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * All rights reserved. - * - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_SPDIF_EDMA_H_ -#define _FSL_SPDIF_EDMA_H_ - -#include "fsl_spdif.h" -#include "fsl_edma.h" - -/*! - * @addtogroup spdif_edma - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_SPDIF_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ -/*@}*/ - -typedef struct _spdif_edma_handle spdif_edma_handle_t; - -/*! @brief SPDIF eDMA transfer callback function for finish and error */ -typedef void (*spdif_edma_callback_t)(SPDIF_Type *base, spdif_edma_handle_t *handle, status_t status, void *userData); - -/*! @brief SPDIF transfer structure */ -typedef struct _spdif_edma_transfer -{ - uint8_t *leftData; /*!< Data start address to transfer. */ - uint8_t *rightData; /*!< Data start address to transfer. */ - size_t dataSize; /*!< Transfer size. */ -} spdif_edma_transfer_t; - -/*! @brief SPDIF DMA transfer handle, users should not touch the content of the handle.*/ -struct _spdif_edma_handle -{ - edma_handle_t *dmaLeftHandle; /*!< DMA handler for SPDIF left channel */ - edma_handle_t *dmaRightHandle; /*!< DMA handler for SPDIF right channel */ - uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ - uint8_t count; /*!< The transfer data count in a DMA request */ - uint32_t state; /*!< Internal state for SPDIF eDMA transfer */ - spdif_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ - void *userData; /*!< User callback parameter */ - edma_tcd_t leftTcd[SPDIF_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ - edma_tcd_t rightTcd[SPDIF_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ - spdif_edma_transfer_t spdifQueue[SPDIF_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ - size_t transferSize[SPDIF_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer, left and right are the same, so use - one */ - volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ - volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ -}; - -/******************************************************************************* - * APIs - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name eDMA Transactional - * @{ - */ - -/*! - * @brief Initializes the SPDIF eDMA handle. - * - * This function initializes the SPDIF master DMA handle, which can be used for other SPDIF master transactional APIs. - * Usually, for a specified SPDIF instance, call this API once to get the initialized handle. - * - * @param base SPDIF base pointer. - * @param handle SPDIF eDMA handle pointer. - * @param base SPDIF peripheral base address. - * @param callback Pointer to user callback function. - * @param userData User parameter passed to the callback function. - * @param dmaLeftHandle eDMA handle pointer for left channel, this handle shall be static allocated by users. - * @param dmaRightHandle eDMA handle pointer for right channel, this handle shall be static allocated by users. - */ -void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base, - spdif_edma_handle_t *handle, - spdif_edma_callback_t callback, - void *userData, - edma_handle_t *dmaLeftHandle, - edma_handle_t *dmaRightHandle); - -/*! - * @brief Initializes the SPDIF Rx eDMA handle. - * - * This function initializes the SPDIF slave DMA handle, which can be used for other SPDIF master transactional APIs. - * Usually, for a specified SPDIF instance, call this API once to get the initialized handle. - * - * @param base SPDIF base pointer. - * @param handle SPDIF eDMA handle pointer. - * @param base SPDIF peripheral base address. - * @param callback Pointer to user callback function. - * @param userData User parameter passed to the callback function. - * @param dmaLeftHandle eDMA handle pointer for left channel, this handle shall be static allocated by users. - * @param dmaRightHandle eDMA handle pointer for right channel, this handle shall be static allocated by users. - */ -void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base, - spdif_edma_handle_t *handle, - spdif_edma_callback_t callback, - void *userData, - edma_handle_t *dmaLeftHandle, - edma_handle_t *dmaRightHandle); - -/*! - * @brief Performs a non-blocking SPDIF transfer using DMA. - * - * @note This interface returns immediately after the transfer initiates. Call - * SPDIF_GetTransferStatus to poll the transfer status and check whether the SPDIF transfer is finished. - * - * @param base SPDIF base pointer. - * @param handle SPDIF eDMA handle pointer. - * @param xfer Pointer to the DMA transfer structure. - * @retval kStatus_Success Start a SPDIF eDMA send successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. - * @retval kStatus_TxBusy SPDIF is busy sending data. - */ -status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer); - -/*! - * @brief Performs a non-blocking SPDIF receive using eDMA. - * - * @note This interface returns immediately after the transfer initiates. Call - * the SPDIF_GetReceiveRemainingBytes to poll the transfer status and check whether the SPDIF transfer is finished. - * - * @param base SPDIF base pointer - * @param handle SPDIF eDMA handle pointer. - * @param xfer Pointer to DMA transfer structure. - * @retval kStatus_Success Start a SPDIF eDMA receive successfully. - * @retval kStatus_InvalidArgument The input argument is invalid. - * @retval kStatus_RxBusy SPDIF is busy receiving data. - */ -status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer); - -/*! - * @brief Aborts a SPDIF transfer using eDMA. - * - * @param base SPDIF base pointer. - * @param handle SPDIF eDMA handle pointer. - */ -void SPDIF_TransferAbortSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle); - -/*! - * @brief Aborts a SPDIF receive using eDMA. - * - * @param base SPDIF base pointer - * @param handle SPDIF eDMA handle pointer. - */ -void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle); - -/*! - * @brief Gets byte count sent by SPDIF. - * - * @param base SPDIF base pointer. - * @param handle SPDIF eDMA handle pointer. - * @param count Bytes count sent by SPDIF. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. - */ -status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count); - -/*! - * @brief Gets byte count received by SPDIF. - * - * @param base SPDIF base pointer - * @param handle SPDIF eDMA handle pointer. - * @param count Bytes count received by SPDIF. - * @retval kStatus_Success Succeed get the transfer count. - * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. - */ -status_t SPDIF_TransferGetReceiveCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count); - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_src.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_src.c deleted file mode 100644 index 7672586d32..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_src.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_src.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.src" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -void SRC_ClearResetStatusFlags(SRC_Type *base, uint32_t flags) -{ - uint32_t tmp32 = base->SRSR; - - if (0U != (SRC_SRSR_TSR_MASK & flags)) - { - tmp32 &= ~SRC_SRSR_TSR_MASK; /* Write 0 to clear. */ - } - - if (0U != (SRC_SRSR_W1C_BITS_MASK & flags)) - { - tmp32 |= (SRC_SRSR_W1C_BITS_MASK & flags); /* Write 1 to clear. */ - } - - base->SRSR = tmp32; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_src.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_src.h deleted file mode 100644 index bf25582051..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_src.h +++ /dev/null @@ -1,623 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_SRC_H_ -#define _FSL_SRC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup src - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SRC driver version 2.0.0. */ -#define FSL_SRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/*! - * @brief SRC reset status flags. - */ -enum _src_reset_status_flags -{ -#if (defined(FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT) && FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT) - kSRC_ResetOutputEnableFlag = SRC_SRSR_RESET_OUT_MASK, /*!< This bit indicates if RESET status is - driven out on PTE0 pin. */ -#endif /* FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT */ -#if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) - kSRC_WarmBootIndicationFlag = SRC_SRSR_WBI_MASK, /*!< WARM boot indication shows that WARM boot - was initiated by software. */ -#endif /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */ - kSRC_TemperatureSensorResetFlag = SRC_SRSR_TSR_MASK, /*!< Indicates whether the reset was the - result of software reset from on-chip - Temperature Sensor. Temperature Sensor - Interrupt need be served before this - bit can be cleaned.*/ -#if (defined(FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) && FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) - kSRC_Wdog3ResetFlag = SRC_SRSR_WDOG3_RST_B_MASK, /*!< IC Watchdog3 Time-out reset. Indicates - whether the reset was the result of the - watchdog3 time-out event. */ -#endif /* FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B */ -#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SW) && FSL_FEATURE_SRC_HAS_SRSR_SW) - kSRC_SoftwareResetFlag = SRC_SRSR_SW_MASK, /*!< Indicates a reset has been caused by software - setting of SYSRESETREQ bit in Application - Interrupt and Reset Control Register in the - ARM core. */ -#endif /* FSL_FEATURE_SRC_HAS_SRSR_SW */ - kSRC_JTAGSoftwareResetFlag = SRC_SRSR_SJC_MASK, /*!< Indicates whether the reset was the result of - setting SJC_GPCCR bit 31. */ - kSRC_JTAGGeneratedResetFlag = SRC_SRSR_JTAG_MASK, /*!< Indicates a reset has been caused by JTAG - selection of certain IR codes: EXTEST or - HIGHZ. */ - kSRC_WatchdogResetFlag = SRC_SRSR_WDOG_MASK, /*!< Indicates a reset has been caused by the - watchdog timer timing out. This reset source - can be blocked by disabling the watchdog. */ -#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B) - kSRC_IppUserResetFlag = SRC_SRSR_IPP_USER_RESET_B_MASK, /*!< Indicates whether the reset was the - result of the ipp_user_reset_b - qualified reset. */ -#endif /* FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B */ -#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SNVS) && FSL_FEATURE_SRC_HAS_SRSR_SNVS) - kSRC_SNVSFailResetFlag = SRC_SRSR_SNVS_MASK, /*!< SNVS hardware failure will always cause a cold - reset. This flag indicates whether the reset - is a result of SNVS hardware failure. */ -#endif /* FSL_FEATURE_SRC_HAS_SRSR_SNVS */ -#if (defined(FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B) - kSRC_CsuResetFlag = SRC_SRSR_CSU_RESET_B_MASK, /*!< Indicates whether the reset was the result - of the csu_reset_b input. */ -#endif /* FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B */ -#if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP) - kSRC_CoreLockupResetFlag = SRC_SRSR_LOCKUP_MASK, /*!< Indicates a reset has been caused by the - ARM core indication of a LOCKUP event. */ -#endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP */ -#if (defined(FSL_FEATURE_SRC_HAS_SRSR_POR) && FSL_FEATURE_SRC_HAS_SRSR_POR) - kSRC_PowerOnResetFlag = SRC_SRSR_POR_MASK, /*!< Indicates a reset has been caused by the - power-on detection logic. */ -#endif /* FSL_FEATURE_SRC_HAS_SRSR_POR */ -#if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) - kSRC_LockupSysResetFlag = SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software - setting of SYSRESETREQ bit in Application Interrupt and - Reset Control Register of the ARM core. */ -#endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ */ -#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) - kSRC_IppResetPinFlag = SRC_SRSR_IPP_RESET_B_MASK, /*!< Indicates whether reset was the result of - ipp_reset_b pin (Power-up sequence). */ -#endif /* FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B */ -}; - -#if (defined(FSL_FEATURE_SRC_HAS_SISR) && FSL_FEATURE_SRC_HAS_SISR) -/*! - * @brief SRC interrupt status flag. - */ -enum _src_status_flags -{ - kSRC_Core0WdogResetReqFlag = - SRC_SISR_CORE0_WDOG_RST_REQ_MASK, /*!< WDOG reset request from core0. Read-only status bit. */ -}; -#endif /* FSL_FEATURE_SRC_HAS_SISR */ - -#if (defined(FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) && FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) -/*! - * @brief Selection of SoC mix power reset stretch. - * - * This type defines the SoC mix (Audio, ENET, uSDHC, EIM, QSPI, OCRAM, MMDC, etc) power up reset - * stretch mix reset width with the optional count of cycles - */ -typedef enum _src_mix_reset_stretch_cycles -{ - kSRC_MixResetStretchCycleAlt0 = 0U, /*!< mix reset width is 1 x 88 ipg_cycle cycles. */ - kSRC_MixResetStretchCycleAlt1 = 1U, /*!< mix reset width is 2 x 88 ipg_cycle cycles. */ - kSRC_MixResetStretchCycleAlt2 = 2U, /*!< mix reset width is 3 x 88 ipg_cycle cycles. */ - kSRC_MixResetStretchCycleAlt3 = 3U, /*!< mix reset width is 4 x 88 ipg_cycle cycles. */ -} src_mix_reset_stretch_cycles_t; -#endif /* FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH */ - -#if (defined(FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) && FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) -/*! - * @brief Selection of WDOG3 reset option. - */ -typedef enum _src_wdog3_reset_option -{ - kSRC_Wdog3ResetOptionAlt0 = 0U, /*!< Wdog3_rst_b asserts M4 reset (default). */ - kSRC_Wdog3ResetOptionAlt1 = 1U, /*!< Wdog3_rst_b asserts global reset. */ -} src_wdog3_reset_option_t; -#endif /* FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN */ - -/*! - * @brief Selection of WARM reset bypass count. - * - * This type defines the 32KHz clock cycles to count before bypassing the MMDC acknowledge for WARM - * reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD reset will - * be initiated. - */ -typedef enum _src_warm_reset_bypass_count -{ - kSRC_WarmResetWaitAlways = 0U, /*!< System will wait until MMDC acknowledge is asserted. */ - kSRC_WarmResetWaitClk16 = 1U, /*!< Wait 16 32KHz clock cycles before switching the reset. */ - kSRC_WarmResetWaitClk32 = 2U, /*!< Wait 32 32KHz clock cycles before switching the reset. */ - kSRC_WarmResetWaitClk64 = 3U, /*!< Wait 64 32KHz clock cycles before switching the reset. */ -} src_warm_reset_bypass_count_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if (defined(FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST) && FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST) -/*! - * @brief Enable the WDOG3 reset. - * - * The WDOG3 reset is enabled by default. - * - * @param base SRC peripheral base address. - * @param enable Enable the reset or not. - */ -static inline void SRC_EnableWDOG3Reset(SRC_Type *base, bool enable) -{ - if (enable) - { - base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0xA); - } - else - { - base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0x5); - } -} -#endif /* FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST */ - -#if (defined(FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) && FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) -/*! - * @brief Set the mix power up reset stretch mix reset width. - * - * @param base SRC peripheral base address. - * @param option Setting option, see to #src_mix_reset_stretch_cycles_t. - */ -static inline void SRC_SetMixResetStretchCycles(SRC_Type *base, src_mix_reset_stretch_cycles_t option) -{ - base->SCR = (base->SCR & ~SRC_SCR_MIX_RST_STRCH_MASK) | SRC_SCR_MIX_RST_STRCH(option); -} -#endif /* FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH */ - -#if (defined(FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG) && FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG) -/*! - * @brief Debug reset would be asserted after power gating event. - * - * @param base SRC peripheral base address. - * @param enable Enable the reset or not. - */ -static inline void SRC_EnableCoreDebugResetAfterPowerGate(SRC_Type *base, bool enable) -{ - if (enable) - { - base->SCR &= ~SRC_SCR_DBG_RST_MSK_PG_MASK; - } - else - { - base->SCR |= SRC_SCR_DBG_RST_MSK_PG_MASK; - } -} -#endif /* FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG */ - -#if (defined(FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) && FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) -/*! - * @brief Set the Wdog3_rst_b option. - * - * @param base SRC peripheral base address. - * @param option Setting option, see to #src_wdog3_reset_option_t. - */ -static inline void SRC_SetWdog3ResetOption(SRC_Type *base, src_wdog3_reset_option_t option) -{ - base->SCR = (base->SCR & ~SRC_SCR_WDOG3_RST_OPTN_MASK) | SRC_SCR_WDOG3_RST_OPTN(option); -} -#endif /* FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN */ - -#if (defined(FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST) && FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST) -/*! - * @brief Software reset for debug of arm platform only. - * - * @param base SRC peripheral base address. - */ -static inline void SRC_DoSoftwareResetARMCoreDebug(SRC_Type *base) -{ - base->SCR |= SRC_SCR_CORES_DBG_RST_MASK; -} - -/*! - * @brief Check if the software reset for debug of arm platform only is done. - * - * @param base SRC peripheral base address. - */ -static inline bool SRC_GetSoftwareResetARMCoreDebugDone(SRC_Type *base) -{ - return (0U == (base->SCR & SRC_SCR_CORES_DBG_RST_MASK)); -} -#endif /* FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST */ - -#if (defined(FSL_FEATURE_SRC_HAS_SCR_MTSR) && FSL_FEATURE_SRC_HAS_SCR_MTSR) -/*! - * @brief Enable the temperature sensor reset. - * - * The temperature sersor reset is enabled by default. When the sensor reset happens, an flag bit - * would be asserted. This flag bit can be cleared only by the hardware reset. - * - * @param base SRC peripheral base address. - * @param enable Enable the reset or not. - */ -static inline void SRC_EnableTemperatureSensorReset(SRC_Type *base, bool enable) -{ - if (enable) /* Temperature sensor reset is not masked. (default) */ - { - base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x2); - } - else /* The on-chip temperature sensor interrupt will not create a reset to the chip. */ - { - base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x5); - } -} -#endif /* FSL_FEATURE_SRC_HAS_SCR_MTSR */ - -#if (defined(FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST) && FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST) -/*! - * @brief Do assert the core0 debug reset. - * - * @param base SRC peripheral base address. - */ -static inline void SRC_DoAssertCore0DebugReset(SRC_Type *base) -{ - base->SCR |= SRC_SCR_CORE0_DBG_RST_MASK; -} - -/*! - * @brief Check if the core0 debug reset is done. - * - * @param base SRC peripheral base address. - */ -static inline bool SRC_GetAssertCore0DebugResetDone(SRC_Type *base) -{ - return (0U == (base->SCR & SRC_SCR_CORE0_DBG_RST_MASK)); -} -#endif /* FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST */ - -#if (defined(FSL_FEATURE_SRC_HAS_SCR_CORE0_RST) && FSL_FEATURE_SRC_HAS_SCR_CORE0_RST) -/*! - * @brief Do software reset the ARM core0 only. - * - * @param base SRC peripheral base address. - */ -static inline void SRC_DoSoftwareResetARMCore0(SRC_Type *base) -{ - base->SCR |= SRC_SCR_CORE0_RST_MASK; -} - -/*! - * @brief Check if the software for ARM core0 is done. - * - * @param base SRC peripheral base address. - * @return If the reset is done. - */ -static inline bool SRC_GetSoftwareResetARMCore0Done(SRC_Type *base) -{ - return (0U == (base->SCR & SRC_SCR_CORE0_RST_MASK)); -} -#endif /* FSL_FEATURE_SRC_HAS_SCR_CORE0_RST */ - -#if (defined(FSL_FEATURE_SRC_HAS_SCR_SWRC) && FSL_FEATURE_SRC_HAS_SCR_SWRC) -/*! - * @brief Do software reset for ARM core. - * - * This function can be used to assert the ARM core reset. Once it is called, the reset process will - * begin. After the reset process is finished, the command bit would be self cleared. - * - * @param base SRC peripheral base address. - */ -static inline void SRC_DoSoftwareResetARMCore(SRC_Type *base) -{ - base->SCR |= SRC_SCR_SWRC_MASK; -} - -/*! - * @brief Check if the software for ARM core is done. - * - * @param base SRC peripheral base address. - * @return If the reset is done. - */ -static inline bool SRC_GetSoftwareResetARMCoreDone(SRC_Type *base) -{ - return (0U == (base->SCR & SRC_SCR_SWRC_MASK)); -} -#endif /* FSL_FEATURE_SRC_HAS_SCR_SWRC */ - -#if (defined(FSL_FEATURE_SRC_HAS_SCR_EIM_RST) && FSL_FEATURE_SRC_HAS_SCR_EIM_RST) -/*! - * @brief Assert the EIM reset. - * - * EIM reset is needed in order to reconfigure the EIM chip select. - * The software reset bit must de-asserted since this is not self-refresh. - * - * @param base SRC peripheral base address. - * @param enable Make the assertion or not. - */ -static inline void SRC_AssertEIMReset(SRC_Type *base, bool enable) -{ - if (enable) - { - base->SCR |= SRC_SCR_EIM_RST_MASK; - } - else - { - base->SCR &= ~SRC_SCR_EIM_RST_MASK; - } -} -#endif /* FSL_FEATURE_SRC_HAS_SCR_EIM_RST */ - -/*! - * @brief Enable the WDOG Reset in SRC. - * - * WDOG Reset is enabled in SRC by default. If the WDOG event to SRC is masked, it would not create - * a reset to the chip. During the time the WDOG event is masked, when the WDOG event flag is - * asserted, it would remain asserted regardless of servicing the WDOG module. The only way to clear - * that bit is the hardware reset. - * - * @param base SRC peripheral base address. - * @param enable Enable the reset or not. - */ -static inline void SRC_EnableWDOGReset(SRC_Type *base, bool enable) -{ - if (enable) /* WDOG Reset is not masked in SRC (default). */ - { - base->SCR = (base->SCR & ~SRC_SCR_MWDR_MASK) | SRC_SCR_MWDR(0xA); - } - else /* WDOG Reset is masked in SRC. */ - { - base->SCR = (base->SCR & ~SRC_SCR_MWDR_MASK) | SRC_SCR_MWDR(0x5); - } -} - -#if !(defined(FSL_FEATURE_SRC_HAS_NO_SCR_WRBC) && FSL_FEATURE_SRC_HAS_NO_SCR_WRBC) -/*! - * @brief Set the delay count of waiting MMDC's acknowledge. - * - * This function would define the 32KHz clock cycles to count before bypassing the MMDC acknowledge - * for WARM reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD - * reset will be initiated. - * - * @param base SRC peripheral base address. - * @param option The option of setting mode, see to #src_warm_reset_bypass_count_t. - */ -static inline void SRC_SetWarmResetBypassCount(SRC_Type *base, src_warm_reset_bypass_count_t option) -{ - base->SCR = (base->SCR & ~SRC_SCR_WRBC_MASK) | SRC_SCR_WRBC(option); -} -#endif /* FSL_FEATURE_SRC_HAS_NO_SCR_WRBC */ - -#if (defined(FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST) && FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST) -/*! - * @brief Enable the lockup reset. - * - * @param base SRC peripheral base address. - * @param enable Enable the reset or not. - */ -static inline void SRC_EnableLockupReset(SRC_Type *base, bool enable) -{ - if (enable) /* Enable lockup reset. */ - { - base->SCR |= SRC_SCR_LOCKUP_RST_MASK; - } - else /* Disable lockup reset. */ - { - base->SCR &= ~SRC_SCR_LOCKUP_RST_MASK; - } -} -#endif /* FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST */ - -#if (defined(FSL_FEATURE_SRC_HAS_SCR_LUEN) && FSL_FEATURE_SRC_HAS_SCR_LUEN) -/*! - * @brief Enable the core lockup reset. - * - * When enable the core luckup reset, the system would be reset when core luckup event happens. - * - * @param base SRC peripheral base address. - * @param enable Enable the reset or not. - */ -static inline void SRC_EnableCoreLockupReset(SRC_Type *base, bool enable) -{ - if (enable) /* Core lockup will cause system reset. */ - { - base->SCR |= SRC_SCR_LUEN_MASK; - } - else /* Core lockup will not cause system reset. */ - { - base->SCR &= ~SRC_SCR_LUEN_MASK; - } -} -#endif /* FSL_FEATURE_SRC_HAS_SCR_LUEN */ - -#if !(defined(FSL_FEATURE_SRC_HAS_NO_SCR_WRE) && FSL_FEATURE_SRC_HAS_NO_SCR_WRE) -/*! - * @brief Enable the WARM reset. - * - * Only when the WARM reset is enabled, the WARM reset requests would be served by WARM reset. - * Otherwise, all the WARM reset sources would generate COLD reset. - * - * @param base SRC peripheral base address. - * @param enable Enable the WARM reset or not. - */ -static inline void SRC_EnableWarmReset(SRC_Type *base, bool enable) -{ - if (enable) - { - base->SCR |= SRC_SCR_WRE_MASK; - } - else - { - base->SCR &= ~SRC_SCR_WRE_MASK; - } -} -#endif /* FSL_FEATURE_SRC_HAS_NO_SCR_WRE */ - -#if (defined(FSL_FEATURE_SRC_HAS_SISR) && FSL_FEATURE_SRC_HAS_SISR) -/*! - * @brief Get interrupt status flags. - * - * @param base SRC peripheral base address. - * @return Mask value of status flags. See to $_src_status_flags. - */ -static inline uint32_t SRC_GetStatusFlags(SRC_Type *base) -{ - return base->SISR; -} -#endif /* FSL_FEATURE_SRC_HAS_SISR */ - -/*! - * @brief Get the boot mode register 1 value. - * - * The Boot Mode register contains bits that reflect the status of BOOT_CFGx pins of the chip. - * See to chip-specific document for detail information about value. - * - * @param base SRC peripheral base address. - * @return status of BOOT_CFGx pins of the chip. - */ -static inline uint32_t SRC_GetBootModeWord1(SRC_Type *base) -{ - return base->SBMR1; -} - -/*! - * @brief Get the boot mode register 2 value. - * - * The Boot Mode register contains bits that reflect the status of BOOT_MODEx Pins and fuse values - * that controls boot of the chip. See to chip-specific document for detail information about value. - * - * @param base SRC peripheral base address. - * @return status of BOOT_MODEx Pins and fuse values that controls boot of the chip. - */ -static inline uint32_t SRC_GetBootModeWord2(SRC_Type *base) -{ - return base->SBMR2; -} - -#if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) -/*! - * @brief Set the warm boot indication flag. - * - * WARM boot indication shows that WARM boot was initiated by software. This indicates to the - * software that it saved the needed information in the memory before initiating the WARM reset. - * In this case, software will set this bit to '1', before initiating the WARM reset. The warm_boot - * bit should be used as indication only after a warm_reset sequence. Software should clear this bit - * after warm_reset to indicate that the next warm_reset is not performed with warm_boot. - * - * @param base SRC peripheral base address. - * @param enable Assert the flag or not. - */ -static inline void SRC_SetWarmBootIndication(SRC_Type *base, bool enable) -{ - if (enable) - { - base->SRSR = (base->SRSR & ~SRC_SRSR_W1C_BITS_MASK) | SRC_SRSR_WBI_MASK; - } - else - { - base->SRSR = (base->SRSR & ~SRC_SRSR_W1C_BITS_MASK) & ~SRC_SRSR_WBI_MASK; - } -} -#endif /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */ - -/*! - * @brief Get the status flags of SRC. - * - * @param base SRC peripheral base address. - * @return Mask value of status flags, see to #_src_reset_status_flags. - */ -static inline uint32_t SRC_GetResetStatusFlags(SRC_Type *base) -{ - return base->SRSR; -} - -/*! - * @brief Clear the status flags of SRC. - * - * @param base SRC peripheral base address. - * @param Mask value of status flags to be cleared, see to #_src_reset_status_flags. - */ -void SRC_ClearResetStatusFlags(SRC_Type *base, uint32_t flags); - -/*! - * @brief Set value to general purpose registers. - * - * General purpose registers (GPRx) would hold the value during reset process. Wakeup function could - * be kept in these register. For example, the GPR1 holds the entry function for waking-up from - * Partial SLEEP mode while the GPR2 holds the argument. Other GPRx register would store the - * arbitray values. - * - * @param base SRC peripheral base address. - * @param index The index of GPRx register array. Note index 0 reponses the GPR1 register. - * @param value Setting value for GPRx register. - */ -static inline void SRC_SetGeneralPurposeRegister(SRC_Type *base, uint32_t index, uint32_t value) -{ - assert(index < SRC_GPR_COUNT); - - base->GPR[index] = value; -} - -/*! - * @brief Get the value from general purpose registers. - * - * @param base SRC peripheral base address. - * @param index The index of GPRx register array. Note index 0 reponses the GPR1 register. - * @return The setting value for GPRx register. - */ -static inline uint32_t SRC_GetGeneralPurposeRegister(SRC_Type *base, uint32_t index) -{ - assert(index < SRC_GPR_COUNT); - - return base->GPR[index]; -} - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_SRC_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_trng.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_trng.c deleted file mode 100644 index 68864316fe..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_trng.c +++ /dev/null @@ -1,1664 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_trng.h" - -#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.trng" -#endif - -/* Default values for user configuration structure.*/ -#if (defined(KW40Z4_SERIES) || defined(KW41Z4_SERIES) || defined(KW31Z4_SERIES) || defined(KW21Z4_SERIES) || \ - defined(MCIMX7U5_M4_SERIES) || defined(KW36Z4_SERIES)) -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv8 -#elif(defined(KV56F24_SERIES) || defined(KV58F24_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \ - defined(KL82Z7_SERIES)) -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv4 -#elif defined(K81F25615_SERIES) -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv2 -#else -#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv0 -#endif - -#define TRNG_USER_CONFIG_DEFAULT_LOCK 0 -#define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 3200 -#define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 2500 -#define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 63 -#define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1 -#define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 34 - -#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 1384 -#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 268) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 405 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 178) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 220 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 122) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 125 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 88) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 75 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM - 64) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 47 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM - 46) -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 47 -#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 46) -#define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 26912 -#define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM (TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM - 2467) -#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 25600 -#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM 1600 - -/*! @brief TRNG work mode */ -typedef enum _trng_work_mode -{ - kTRNG_WorkModeRun = 0U, /*!< Run Mode. */ - kTRNG_WorkModeProgram = 1U /*!< Program Mode. */ -} trng_work_mode_t; - -/*! @brief TRNG statistical check type*/ -typedef enum _trng_statistical_check -{ - kTRNG_StatisticalCheckMonobit = - 1U, /*!< Statistical check of number of ones/zero detected during entropy generation. */ - kTRNG_StatisticalCheckRunBit1, /*!< Statistical check of number of runs of length 1 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit2, /*!< Statistical check of number of runs of length 2 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit3, /*!< Statistical check of number of runs of length 3 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit4, /*!< Statistical check of number of runs of length 4 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit5, /*!< Statistical check of number of runs of length 5 detected during entropy - generation. */ - kTRNG_StatisticalCheckRunBit6Plus, /*!< Statistical check of number of runs of length 6 or more detected during - entropy generation. */ - kTRNG_StatisticalCheckPoker, /*!< Statistical check of "Poker Test". */ - kTRNG_StatisticalCheckFrequencyCount /*!< Statistical check of entropy sample frequency count. */ -} trng_statistical_check_t; - -/******************************************************************************* - * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register - ******************************************************************************/ -/*! - * @name Register TRNG_SCMISC, field RTY_CT[19:16] (RW) - * - * RETRY COUNT. If a statistical check fails during the TRNG Entropy Generation, - * the RTY_CT value indicates the number of times a retry should occur before - * generating an error. This field is writable only if MCTL[PRGM] bit is 1. This - * field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 1h by writing - * the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCMISC_RTY_CT field. */ -#define TRNG_RD_SCMISC_RTY_CT(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_RTY_CT_MASK) >> TRNG_SCMISC_RTY_CT_SHIFT) - -/*! @brief Set the RTY_CT field to a new value. */ -#define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCMISC_RTY_CT(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCML - RNG Statistical Check Monobit Limit Register - ******************************************************************************/ -/*! - * @brief TRNG_SCML - RNG Statistical Check Monobit Limit Register (RW) - * - * Reset value: 0x010C0568U - * - * The RNG Statistical Check Monobit Limit Register defines the allowable - * maximum and minimum number of ones/zero detected during entropy generation. To pass - * the test, the number of ones/zeroes generated must be less than the programmed - * maximum value, and the number of ones/zeroes generated must be greater than - * (maximum - range). If this test fails, the Retry Counter in SCMISC will be - * decremented, and a retry will occur if the Retry Count has not reached zero. If - * the Retry Count has reached zero, an error will be generated. Note that this - * offset (0xBASE_0620) is used as SCML only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, - * this offset is used as SCMC readback register. - */ -/*! - * @name Constants and macros for entire TRNG_SCML register - */ -/*@{*/ -#define TRNG_SCML_REG(base) ((base)->SCML) -#define TRNG_RD_SCML(base) (TRNG_SCML_REG(base)) -#define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value)) -#define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (value))) -/*@}*/ -/*! - * @name Register TRNG_SCML, field MONO_MAX[15:0] (RW) - * - * Monobit Maximum Limit. Defines the maximum allowable count taken during - * entropy generation. The number of ones/zeroes detected during entropy generation - * must be less than MONO_MAX, else a retry or error will occur. This register is - * cleared to 00056Bh (decimal 1387) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCML_MONO_MAX field. */ -#define TRNG_RD_SCML_MONO_MAX(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_MAX_MASK) >> TRNG_SCML_MONO_MAX_SHIFT) - -/*! @brief Set the MONO_MAX field to a new value. */ -#define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_MONO_MAX(value))) -/*@}*/ -/*! - * @name Register TRNG_SCML, field MONO_RNG[31:16] (RW) - * - * Monobit Range. The number of ones/zeroes detected during entropy generation - * must be greater than MONO_MAX - MONO_RNG, else a retry or error will occur. - * This register is cleared to 000112h (decimal 274) by writing the MCTL[RST_DEF] - * bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCML_MONO_RNG field. */ -#define TRNG_RD_SCML_MONO_RNG(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_RNG_MASK) >> TRNG_SCML_MONO_RNG_SHIFT) - -/*! @brief Set the MONO_RNG field to a new value. */ -#define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_MONO_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register (RW) - * - * Reset value: 0x00B20195U - * - * The RNG Statistical Check Run Length 1 Limit Register defines the allowable - * maximum and minimum number of runs of length 1 detected during entropy - * generation. To pass the test, the number of runs of length 1 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 1 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0624) is used as SCR1L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR1C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR1L register - */ -/*@{*/ -#define TRNG_SCR1L_REG(base) ((base)->SCR1L) -#define TRNG_RD_SCR1L(base) (TRNG_SCR1L_REG(base)) -#define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value)) -#define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR1L, field RUN1_MAX[14:0] (RW) - * - * Run Length 1 Maximum Limit. Defines the maximum allowable runs of length 1 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 1 detected during entropy generation must be less than RUN1_MAX, else a - * retry or error will occur. This register is cleared to 01E5h (decimal 485) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR1L_RUN1_MAX field. */ -#define TRNG_RD_SCR1L_RUN1_MAX(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_MAX_MASK) >> TRNG_SCR1L_RUN1_MAX_SHIFT) - -/*! @brief Set the RUN1_MAX field to a new value. */ -#define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SCR1L_RUN1_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR1L, field RUN1_RNG[30:16] (RW) - * - * Run Length 1 Range. The number of runs of length 1 (for both 0 and 1) - * detected during entropy generation must be greater than RUN1_MAX - RUN1_RNG, else a - * retry or error will occur. This register is cleared to 0102h (decimal 258) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR1L_RUN1_RNG field. */ -#define TRNG_RD_SCR1L_RUN1_RNG(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_RNG_MASK) >> TRNG_SCR1L_RUN1_RNG_SHIFT) - -/*! @brief Set the RUN1_RNG field to a new value. */ -#define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SCR1L_RUN1_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register (RW) - * - * Reset value: 0x007A00DCU - * - * The RNG Statistical Check Run Length 2 Limit Register defines the allowable - * maximum and minimum number of runs of length 2 detected during entropy - * generation. To pass the test, the number of runs of length 2 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 2 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0628) is used as SCR2L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR2C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR2L register - */ -/*@{*/ -#define TRNG_SCR2L_REG(base) ((base)->SCR2L) -#define TRNG_RD_SCR2L(base) (TRNG_SCR2L_REG(base)) -#define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value)) -#define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR2L bitfields - */ - -/*! - * @name Register TRNG_SCR2L, field RUN2_MAX[13:0] (RW) - * - * Run Length 2 Maximum Limit. Defines the maximum allowable runs of length 2 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 2 detected during entropy generation must be less than RUN2_MAX, else a - * retry or error will occur. This register is cleared to 00DCh (decimal 220) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR2L_RUN2_MAX field. */ -#define TRNG_RD_SCR2L_RUN2_MAX(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_MAX_MASK) >> TRNG_SCR2L_RUN2_MAX_SHIFT) - -/*! @brief Set the RUN2_MAX field to a new value. */ -#define TRNG_WR_SCR2L_RUN2_MAX(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_MAX_MASK, TRNG_SCR2L_RUN2_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR2L, field RUN2_RNG[29:16] (RW) - * - * Run Length 2 Range. The number of runs of length 2 (for both 0 and 1) - * detected during entropy generation must be greater than RUN2_MAX - RUN2_RNG, else a - * retry or error will occur. This register is cleared to 007Ah (decimal 122) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR2L_RUN2_RNG field. */ -#define TRNG_RD_SCR2L_RUN2_RNG(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_RNG_MASK) >> TRNG_SCR2L_RUN2_RNG_SHIFT) - -/*! @brief Set the RUN2_RNG field to a new value. */ -#define TRNG_WR_SCR2L_RUN2_RNG(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_RNG_MASK, TRNG_SCR2L_RUN2_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register (RW) - * - * Reset value: 0x0058007DU - * - * The RNG Statistical Check Run Length 3 Limit Register defines the allowable - * maximum and minimum number of runs of length 3 detected during entropy - * generation. To pass the test, the number of runs of length 3 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 3 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_062C) is used as SCR3L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR3C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR3L register - */ -/*@{*/ -#define TRNG_SCR3L_REG(base) ((base)->SCR3L) -#define TRNG_RD_SCR3L(base) (TRNG_SCR3L_REG(base)) -#define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value)) -#define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR3L bitfields - */ - -/*! - * @name Register TRNG_SCR3L, field RUN3_MAX[12:0] (RW) - * - * Run Length 3 Maximum Limit. Defines the maximum allowable runs of length 3 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 3 detected during entropy generation must be less than RUN3_MAX, else a - * retry or error will occur. This register is cleared to 007Dh (decimal 125) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR3L_RUN3_MAX field. */ -#define TRNG_RD_SCR3L_RUN3_MAX(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_MAX_MASK) >> TRNG_SCR3L_RUN3_MAX_SHIFT) - -/*! @brief Set the RUN3_MAX field to a new value. */ -#define TRNG_WR_SCR3L_RUN3_MAX(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_MAX_MASK, TRNG_SCR3L_RUN3_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR3L, field RUN3_RNG[28:16] (RW) - * - * Run Length 3 Range. The number of runs of length 3 (for both 0 and 1) - * detected during entropy generation must be greater than RUN3_MAX - RUN3_RNG, else a - * retry or error will occur. This register is cleared to 0058h (decimal 88) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR3L_RUN3_RNG field. */ -#define TRNG_RD_SCR3L_RUN3_RNG(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_RNG_MASK) >> TRNG_SCR3L_RUN3_RNG_SHIFT) - -/*! @brief Set the RUN3_RNG field to a new value. */ -#define TRNG_WR_SCR3L_RUN3_RNG(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_RNG_MASK, TRNG_SCR3L_RUN3_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register (RW) - * - * Reset value: 0x0040004BU - * - * The RNG Statistical Check Run Length 4 Limit Register defines the allowable - * maximum and minimum number of runs of length 4 detected during entropy - * generation. To pass the test, the number of runs of length 4 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 4 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0630) is used as SCR4L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR4C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR4L register - */ -/*@{*/ -#define TRNG_SCR4L_REG(base) ((base)->SCR4L) -#define TRNG_RD_SCR4L(base) (TRNG_SCR4L_REG(base)) -#define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value)) -#define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR4L bitfields - */ - -/*! - * @name Register TRNG_SCR4L, field RUN4_MAX[11:0] (RW) - * - * Run Length 4 Maximum Limit. Defines the maximum allowable runs of length 4 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 4 detected during entropy generation must be less than RUN4_MAX, else a - * retry or error will occur. This register is cleared to 004Bh (decimal 75) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR4L_RUN4_MAX field. */ -#define TRNG_RD_SCR4L_RUN4_MAX(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_MAX_MASK) >> TRNG_SCR4L_RUN4_MAX_SHIFT) - -/*! @brief Set the RUN4_MAX field to a new value. */ -#define TRNG_WR_SCR4L_RUN4_MAX(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_MAX_MASK, TRNG_SCR4L_RUN4_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR4L, field RUN4_RNG[27:16] (RW) - * - * Run Length 4 Range. The number of runs of length 4 (for both 0 and 1) - * detected during entropy generation must be greater than RUN4_MAX - RUN4_RNG, else a - * retry or error will occur. This register is cleared to 0040h (decimal 64) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR4L_RUN4_RNG field. */ -#define TRNG_RD_SCR4L_RUN4_RNG(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_RNG_MASK) >> TRNG_SCR4L_RUN4_RNG_SHIFT) - -/*! @brief Set the RUN4_RNG field to a new value. */ -#define TRNG_WR_SCR4L_RUN4_RNG(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_RNG_MASK, TRNG_SCR4L_RUN4_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register (RW) - * - * Reset value: 0x002E002FU - * - * The RNG Statistical Check Run Length 5 Limit Register defines the allowable - * maximum and minimum number of runs of length 5 detected during entropy - * generation. To pass the test, the number of runs of length 5 (for samples of both 0 - * and 1) must be less than the programmed maximum value, and the number of runs of - * length 5 must be greater than (maximum - range). If this test fails, the - * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry - * Count has not reached zero. If the Retry Count has reached zero, an error will - * be generated. Note that this address (0xBASE_0634) is used as SCR5L only if - * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR5C readback - * register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR5L register - */ -/*@{*/ -#define TRNG_SCR5L_REG(base) ((base)->SCR5L) -#define TRNG_RD_SCR5L(base) (TRNG_SCR5L_REG(base)) -#define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value)) -#define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR5L bitfields - */ - -/*! - * @name Register TRNG_SCR5L, field RUN5_MAX[10:0] (RW) - * - * Run Length 5 Maximum Limit. Defines the maximum allowable runs of length 5 - * (for both 0 and 1) detected during entropy generation. The number of runs of - * length 5 detected during entropy generation must be less than RUN5_MAX, else a - * retry or error will occur. This register is cleared to 002Fh (decimal 47) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR5L_RUN5_MAX field. */ -#define TRNG_RD_SCR5L_RUN5_MAX(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_MAX_MASK) >> TRNG_SCR5L_RUN5_MAX_SHIFT) - -/*! @brief Set the RUN5_MAX field to a new value. */ -#define TRNG_WR_SCR5L_RUN5_MAX(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_MAX_MASK, TRNG_SCR5L_RUN5_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR5L, field RUN5_RNG[26:16] (RW) - * - * Run Length 5 Range. The number of runs of length 5 (for both 0 and 1) - * detected during entropy generation must be greater than RUN5_MAX - RUN5_RNG, else a - * retry or error will occur. This register is cleared to 002Eh (decimal 46) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR5L_RUN5_RNG field. */ -#define TRNG_RD_SCR5L_RUN5_RNG(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_RNG_MASK) >> TRNG_SCR5L_RUN5_RNG_SHIFT) - -/*! @brief Set the RUN5_RNG field to a new value. */ -#define TRNG_WR_SCR5L_RUN5_RNG(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_RNG_MASK, TRNG_SCR5L_RUN5_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register (RW) - * - * Reset value: 0x002E002FU - * - * The RNG Statistical Check Run Length 6+ Limit Register defines the allowable - * maximum and minimum number of runs of length 6 or more detected during entropy - * generation. To pass the test, the number of runs of length 6 or more (for - * samples of both 0 and 1) must be less than the programmed maximum value, and the - * number of runs of length 6 or more must be greater than (maximum - range). If - * this test fails, the Retry Counter in SCMISC will be decremented, and a retry - * will occur if the Retry Count has not reached zero. If the Retry Count has - * reached zero, an error will be generated. Note that this offset (0xBASE_0638) is - * used as SCR6PL only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is - * used as SCR6PC readback register. - */ -/*! - * @name Constants and macros for entire TRNG_SCR6PL register - */ -/*@{*/ -#define TRNG_SCR6PL_REG(base) ((base)->SCR6PL) -#define TRNG_RD_SCR6PL(base) (TRNG_SCR6PL_REG(base)) -#define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value)) -#define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCR6PL bitfields - */ - -/*! - * @name Register TRNG_SCR6PL, field RUN6P_MAX[10:0] (RW) - * - * Run Length 6+ Maximum Limit. Defines the maximum allowable runs of length 6 - * or more (for both 0 and 1) detected during entropy generation. The number of - * runs of length 6 or more detected during entropy generation must be less than - * RUN6P_MAX, else a retry or error will occur. This register is cleared to 002Fh - * (decimal 47) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_MAX field. */ -#define TRNG_RD_SCR6PL_RUN6P_MAX(base) \ - ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_MAX_MASK) >> TRNG_SCR6PL_RUN6P_MAX_SHIFT) - -/*! @brief Set the RUN6P_MAX field to a new value. */ -#define TRNG_WR_SCR6PL_RUN6P_MAX(base, value) \ - (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_MAX_MASK, TRNG_SCR6PL_RUN6P_MAX(value))) -/*@}*/ - -/*! - * @name Register TRNG_SCR6PL, field RUN6P_RNG[26:16] (RW) - * - * Run Length 6+ Range. The number of runs of length 6 or more (for both 0 and - * 1) detected during entropy generation must be greater than RUN6P_MAX - - * RUN6P_RNG, else a retry or error will occur. This register is cleared to 002Eh - * (decimal 46) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_RNG field. */ -#define TRNG_RD_SCR6PL_RUN6P_RNG(base) \ - ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_RNG_MASK) >> TRNG_SCR6PL_RUN6P_RNG_SHIFT) - -/*! @brief Set the RUN6P_RNG field to a new value. */ -#define TRNG_WR_SCR6PL_RUN6P_RNG(base, value) \ - (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_RNG_MASK, TRNG_SCR6PL_RUN6P_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_PKRMAX - RNG Poker Maximum Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_PKRMAX - RNG Poker Maximum Limit Register (RW) - * - * Reset value: 0x00006920U - * - * The RNG Poker Maximum Limit Register defines Maximum Limit allowable during - * the TRNG Statistical Check Poker Test. Note that this offset (0xBASE_060C) is - * used as PKRMAX only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used - * as the PKRSQ readback register. - */ -/*! - * @name Constants and macros for entire TRNG_PKRMAX register - */ -/*@{*/ -#define TRNG_PKRMAX_REG(base) ((base)->PKRMAX) -#define TRNG_RD_PKRMAX(base) (TRNG_PKRMAX_REG(base)) -#define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value)) -#define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_PKRMAX bitfields - */ - -/*! - * @name Register TRNG_PKRMAX, field PKR_MAX[23:0] (RW) - * - * Poker Maximum Limit. During the TRNG Statistical Checks, a "Poker Test" is - * run which requires a maximum and minimum limit. The maximum allowable result is - * programmed in the PKRMAX[PKR_MAX] register. This field is writable only if - * MCTL[PRGM] bit is 1. This register is cleared to 006920h (decimal 26912) by - * writing the MCTL[RST_DEF] bit to 1. Note that the PKRMAX and PKRRNG registers - * combined are used to define the minimum allowable Poker result, which is PKR_MAX - - * PKR_RNG + 1. Note that if MCTL[PRGM] bit is 0, this register address is used - * to read the Poker Test Square Calculation result in register PKRSQ, as defined - * in the following section. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_PKRMAX_PKR_MAX field. */ -#define TRNG_RD_PKRMAX_PKR_MAX(base) ((TRNG_PKRMAX_REG(base) & TRNG_PKRMAX_PKR_MAX_MASK) >> TRNG_PKRMAX_PKR_MAX_SHIFT) - -/*! @brief Set the PKR_MAX field to a new value. */ -#define TRNG_WR_PKRMAX_PKR_MAX(base, value) \ - (TRNG_RMW_PKRMAX(base, TRNG_PKRMAX_PKR_MAX_MASK, TRNG_PKRMAX_PKR_MAX(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_PKRRNG - RNG Poker Range Register - ******************************************************************************/ - -/*! - * @brief TRNG_PKRRNG - RNG Poker Range Register (RW) - * - * Reset value: 0x000009A3U - * - * The RNG Poker Range Register defines the difference between the TRNG Poker - * Maximum Limit and the minimum limit. These limits are used during the TRNG - * Statistical Check Poker Test. - */ -/*! - * @name Constants and macros for entire TRNG_PKRRNG register - */ -/*@{*/ -#define TRNG_PKRRNG_REG(base) ((base)->PKRRNG) -#define TRNG_RD_PKRRNG(base) (TRNG_PKRRNG_REG(base)) -#define TRNG_WR_PKRRNG(base, value) (TRNG_PKRRNG_REG(base) = (value)) -#define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_PKRRNG bitfields - */ - -/*! - * @name Register TRNG_PKRRNG, field PKR_RNG[15:0] (RW) - * - * Poker Range. During the TRNG Statistical Checks, a "Poker Test" is run which - * requires a maximum and minimum limit. The maximum is programmed in the - * RTPKRMAX[PKR_MAX] register, and the minimum is derived by subtracting the PKR_RNG - * value from the programmed maximum value. This field is writable only if - * MCTL[PRGM] bit is 1. This field will read zeroes if MCTL[PRGM] = 0. This field is - * cleared to 09A3h (decimal 2467) by writing the MCTL[RST_DEF] bit to 1. Note that - * the minimum allowable Poker result is PKR_MAX - PKR_RNG + 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_PKRRNG_PKR_RNG field. */ -#define TRNG_RD_PKRRNG_PKR_RNG(base) ((TRNG_PKRRNG_REG(base) & TRNG_PKRRNG_PKR_RNG_MASK) >> TRNG_PKRRNG_PKR_RNG_SHIFT) - -/*! @brief Set the PKR_RNG field to a new value. */ -#define TRNG_WR_PKRRNG_PKR_RNG(base, value) \ - (TRNG_RMW_PKRRNG(base, TRNG_PKRRNG_PKR_RNG_MASK, TRNG_PKRRNG_PKR_RNG(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register (RW) - * - * Reset value: 0x00006400U - * - * The RNG Frequency Count Maximum Limit Register defines the maximum allowable - * count taken by the Entropy sample counter during each Entropy sample. During - * any sample period, if the count is greater than this programmed maximum, a - * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. Note - * that this address (061C) is used as FRQMAX only if MCTL[PRGM] is 1. If - * MCTL[PRGM] is 0, this address is used as FRQCNT readback register. - */ -/*! - * @name Constants and macros for entire TRNG_FRQMAX register - */ -/*@{*/ -#define TRNG_FRQMAX_REG(base) ((base)->FRQMAX) -#define TRNG_RD_FRQMAX(base) (TRNG_FRQMAX_REG(base)) -#define TRNG_WR_FRQMAX(base, value) (TRNG_FRQMAX_REG(base) = (value)) -#define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_FRQMAX bitfields - */ - -/*! - * @name Register TRNG_FRQMAX, field FRQ_MAX[21:0] (RW) - * - * Frequency Counter Maximum Limit. Defines the maximum allowable count taken - * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1. - * This register is cleared to 000640h by writing the MCTL[RST_DEF] bit to 1. - * Note that if MCTL[PRGM] bit is 0, this register address is used to read the - * Frequency Count result in register FRQCNT, as defined in the following section. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_FRQMAX_FRQ_MAX field. */ -#define TRNG_RD_FRQMAX_FRQ_MAX(base) ((TRNG_FRQMAX_REG(base) & TRNG_FRQMAX_FRQ_MAX_MASK) >> TRNG_FRQMAX_FRQ_MAX_SHIFT) - -/*! @brief Set the FRQ_MAX field to a new value. */ -#define TRNG_WR_FRQMAX_FRQ_MAX(base, value) \ - (TRNG_RMW_FRQMAX(base, TRNG_FRQMAX_FRQ_MAX_MASK, TRNG_FRQMAX_FRQ_MAX(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register (RW) - * - * Reset value: 0x00000640U - * - * The RNG Frequency Count Minimum Limit Register defines the minimum allowable - * count taken by the Entropy sample counter during each Entropy sample. During - * any sample period, if the count is less than this programmed minimum, a - * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. - */ -/*! - * @name Constants and macros for entire TRNG_FRQMIN register - */ -/*@{*/ -#define TRNG_FRQMIN_REG(base) ((base)->FRQMIN) -#define TRNG_RD_FRQMIN(base) (TRNG_FRQMIN_REG(base)) -#define TRNG_WR_FRQMIN(base, value) (TRNG_FRQMIN_REG(base) = (value)) -#define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_FRQMIN bitfields - */ - -/*! - * @name Register TRNG_FRQMIN, field FRQ_MIN[21:0] (RW) - * - * Frequency Count Minimum Limit. Defines the minimum allowable count taken - * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1. - * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 0000h64 - * by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_FRQMIN_FRQ_MIN field. */ -#define TRNG_RD_FRQMIN_FRQ_MIN(base) ((TRNG_FRQMIN_REG(base) & TRNG_FRQMIN_FRQ_MIN_MASK) >> TRNG_FRQMIN_FRQ_MIN_SHIFT) - -/*! @brief Set the FRQ_MIN field to a new value. */ -#define TRNG_WR_FRQMIN_FRQ_MIN(base, value) \ - (TRNG_RMW_FRQMIN(base, TRNG_FRQMIN_FRQ_MIN_MASK, TRNG_FRQMIN_FRQ_MIN(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_MCTL - RNG Miscellaneous Control Register - ******************************************************************************/ - -/*! - * @brief TRNG_MCTL - RNG Miscellaneous Control Register (RW) - * - * Reset value: 0x00012001U - * - * This register is intended to be used for programming, configuring and testing - * the RNG. It is the main register to read/write, in order to enable Entropy - * generation, to stop entropy generation and to block access to entropy registers. - * This is done via the special TRNG_ACC and PRGM bits below. The RNG - * Miscellaneous Control Register is a read/write register used to control the RNG's True - * Random Number Generator (TRNG) access, operation and test. Note that in many - * cases two RNG registers share the same address, and a particular register at the - * shared address is selected based upon the value in the PRGM field of the MCTL - * register. - */ -/*! - * @name Constants and macros for entire TRNG_MCTL register - */ -/*@{*/ -#define TRNG_MCTL_REG(base) ((base)->MCTL) -#define TRNG_RD_MCTL(base) (TRNG_MCTL_REG(base)) -#define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value)) -#define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) | (value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field FOR_SCLK[7] (RW) - * - * Force System Clock. If set, the system clock is used to operate the TRNG, - * instead of the ring oscillator. This is for test use only, and indeterminate - * results may occur. This bit is writable only if PRGM bit is 1, or PRGM bit is - * being written to 1 simultaneously to writing this bit. This bit is cleared by - * writing the RST_DEF bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_FOR_SCLK field. */ -#define TRNG_RD_MCTL_FOR_SCLK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FOR_SCLK_MASK) >> TRNG_MCTL_FOR_SCLK_SHIFT) - -/*! @brief Set the FOR_SCLK field to a new value. */ -#define TRNG_WR_MCTL_FOR_SCLK(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_FOR_SCLK_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_FOR_SCLK(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field OSC_DIV[3:2] (RW) - * - * Oscillator Divide. Determines the amount of dividing done to the ring - * oscillator before it is used by the TRNG.This field is writable only if PRGM bit is - * 1, or PRGM bit is being written to 1 simultaneously to writing this field. This - * field is cleared to 00 by writing the RST_DEF bit to 1. - * - * Values: - * - 0b00 - use ring oscillator with no divide - * - 0b01 - use ring oscillator divided-by-2 - * - 0b10 - use ring oscillator divided-by-4 - * - 0b11 - use ring oscillator divided-by-8 - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_OSC_DIV field. */ -#define TRNG_RD_MCTL_OSC_DIV(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_OSC_DIV_MASK) >> TRNG_MCTL_OSC_DIV_SHIFT) - -/*! @brief Set the OSC_DIV field to a new value. */ -#define TRNG_WR_MCTL_OSC_DIV(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_OSC_DIV_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_OSC_DIV(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field SAMP_MODE[1:0] (RW) - * - * Sample Mode. Determines the method of sampling the ring oscillator while - * generating the Entropy value:This field is writable only if PRGM bit is 1, or PRGM - * bit is being written to 1 simultaneously with writing this field. This field - * is cleared to 01 by writing the RST_DEF bit to 1. - * - * Values: - * - 0b00 - use Von Neumann data into both Entropy shifter and Statistical - * Checker - * - 0b01 - use raw data into both Entropy shifter and Statistical Checker - * - 0b10 - use Von Neumann data into Entropy shifter. Use raw data into - * Statistical Checker - * - 0b11 - reserved. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_SAMP_MODE field. */ -#define TRNG_RD_MCTL_SAMP_MODE(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_SAMP_MODE_MASK) >> TRNG_MCTL_SAMP_MODE_SHIFT) - -/*! @brief Set the SAMP_MODE field to a new value. */ -#define TRNG_WR_MCTL_SAMP_MODE(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_SAMP_MODE_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_SAMP_MODE(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field PRGM[16] (RW) - * - * Programming Mode Select. When this bit is 1, the TRNG is in Program Mode, - * otherwise it is in Run Mode. No Entropy value will be generated while the TRNG is - * in Program Mode. Note that different RNG registers are accessible at the same - * address depending on whether PRGM is set to 1 or 0. This is noted in the RNG - * register descriptions. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_PRGM field. */ -#define TRNG_RD_MCTL_PRGM(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_PRGM_MASK) >> TRNG_MCTL_PRGM_SHIFT) - -/*! @brief Set the PRGM field to a new value. */ -#define TRNG_WR_MCTL_PRGM(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_PRGM(value))) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field RST_DEF[6] (WO) - * - * Reset Defaults. Writing a 1 to this bit clears various TRNG registers, and - * bits within registers, to their default state. This bit is writable only if PRGM - * bit is 1, or PRGM bit is being written to 1 simultaneously to writing this - * bit. Reading this bit always produces a 0. - */ -/*@{*/ -/*! @brief Set the RST_DEF field to a new value. */ -#define TRNG_WR_MCTL_RST_DEF(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_RST_DEF_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_RST_DEF(value))) -/*@}*/ - -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0)) -/*! - * @name Register TRNG_MCTL, field TRNG_ACC[5] (RW) - * - * TRNG Access Mode. If this bit is set to 1, the TRNG will generate an Entropy - * value that can be read via the ENT0-ENT15 registers. The Entropy value may be - * read once the ENT VAL bit is asserted. Also see ENTa register descriptions - * (For a = 0 to 15). - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_TRNG_ACC field. */ -#define TRNG_RD_MCTL_TRNG_ACC(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TRNG_ACC_MASK) >> TRNG_MCTL_TRNG_ACC_SHIFT) - -/*! @brief Set the TRNG_ACC field to a new value. */ -#define TRNG_WR_MCTL_TRNG_ACC(base, value) \ - (TRNG_RMW_MCTL(base, (TRNG_MCTL_TRNG_ACC_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_TRNG_ACC(value))) -/*@}*/ -#endif - -/*! - * @name Register TRNG_MCTL, field TSTOP_OK[13] (RO) - * - * TRNG_OK_TO_STOP. Software should check that this bit is a 1 before - * transitioning RNG to low power mode (RNG clock stopped). RNG turns on the TRNG - * free-running ring oscillator whenever new entropy is being generated and turns off the - * ring oscillator when entropy generation is complete. If the RNG clock is - * stopped while the TRNG ring oscillator is running, the oscillator will continue - * running even though the RNG clock is stopped. TSTOP_OK is asserted when the TRNG - * ring oscillator is not running. and therefore it is ok to stop the RNG clock. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_TSTOP_OK field. */ -#define TRNG_RD_MCTL_TSTOP_OK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TSTOP_OK_MASK) >> TRNG_MCTL_TSTOP_OK_SHIFT) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field ENT_VAL[10] (RO) - * - * Read only: Entropy Valid. Will assert only if TRNG ACC bit is set, and then - * after an entropy value is generated. Will be cleared when ENT15 is read. (ENT0 - * through ENT14 should be read before reading ENT15). - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_ENT_VAL field. */ -#define TRNG_RD_MCTL_ENT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ENT_VAL_MASK) >> TRNG_MCTL_ENT_VAL_SHIFT) -/*@}*/ - -/*! - * @name Register TRNG_MCTL, field ERR[12] (W1C) - * - * Read: Error status. 1 = error detected. 0 = no error.Write: Write 1 to clear - * errors. Writing 0 has no effect. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_MCTL_ERR field. */ -#define TRNG_RD_MCTL_ERR(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ERR_MASK) >> TRNG_MCTL_ERR_SHIFT) - -/*! @brief Set the ERR field to a new value. */ -#define TRNG_WR_MCTL_ERR(base, value) (TRNG_RMW_MCTL(base, TRNG_MCTL_ERR_MASK, TRNG_MCTL_ERR(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SDCTL - RNG Seed Control Register - ******************************************************************************/ - -/*! - * @brief TRNG_SDCTL - RNG Seed Control Register (RW) - * - * Reset value: 0x0C8009C4U - * - * The RNG Seed Control Register contains two fields. One field defines the - * length (in system clocks) of each Entropy sample (ENT_DLY), and the other field - * indicates the number of samples that will taken during each TRNG Entropy - * generation (SAMP_SIZE). - */ -/*! - * @name Constants and macros for entire TRNG_SDCTL register - */ -/*@{*/ -#define TRNG_SDCTL_REG(base) ((base)->SDCTL) -#define TRNG_RD_SDCTL(base) (TRNG_SDCTL_REG(base)) -#define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value)) -#define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SDCTL bitfields - */ - -/*! - * @name Register TRNG_SDCTL, field SAMP_SIZE[15:0] (RW) - * - * Sample Size. Defines the total number of Entropy samples that will be taken - * during Entropy generation. This field is writable only if MCTL[PRGM] bit is 1. - * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 09C4h - * (decimal 2500) by writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SDCTL_SAMP_SIZE field. */ -#define TRNG_RD_SDCTL_SAMP_SIZE(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_SAMP_SIZE_MASK) >> TRNG_SDCTL_SAMP_SIZE_SHIFT) - -/*! @brief Set the SAMP_SIZE field to a new value. */ -#define TRNG_WR_SDCTL_SAMP_SIZE(base, value) \ - (TRNG_RMW_SDCTL(base, TRNG_SDCTL_SAMP_SIZE_MASK, TRNG_SDCTL_SAMP_SIZE(value))) -/*@}*/ - -/*! - * @name Register TRNG_SDCTL, field ENT_DLY[31:16] (RW) - * - * Entropy Delay. Defines the length (in system clocks) of each Entropy sample - * taken. This field is writable only if MCTL[PRGM] bit is 1. This field will read - * zeroes if MCTL[PRGM] = 0. This field is cleared to 0C80h (decimal 3200) by - * writing the MCTL[RST_DEF] bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SDCTL_ENT_DLY field. */ -#define TRNG_RD_SDCTL_ENT_DLY(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_ENT_DLY_MASK) >> TRNG_SDCTL_ENT_DLY_SHIFT) - -/*! @brief Set the ENT_DLY field to a new value. */ -#define TRNG_WR_SDCTL_ENT_DLY(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_ENT_DLY_MASK, TRNG_SDCTL_ENT_DLY(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SBLIM - RNG Sparse Bit Limit Register - ******************************************************************************/ - -/*! - * @brief TRNG_SBLIM - RNG Sparse Bit Limit Register (RW) - * - * Reset value: 0x0000003FU - * - * The RNG Sparse Bit Limit Register is used when Von Neumann sampling is - * selected during Entropy Generation. It defines the maximum number of consecutive Von - * Neumann samples which may be discarded before an error is generated. Note - * that this address (0xBASE_0614) is used as SBLIM only if MCTL[PRGM] is 1. If - * MCTL[PRGM] is 0, this address is used as TOTSAM readback register. - */ -/*! - * @name Constants and macros for entire TRNG_SBLIM register - */ -/*@{*/ -#define TRNG_SBLIM_REG(base) ((base)->SBLIM) -#define TRNG_RD_SBLIM(base) (TRNG_SBLIM_REG(base)) -#define TRNG_WR_SBLIM(base, value) (TRNG_SBLIM_REG(base) = (value)) -#define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SBLIM bitfields - */ - -/*! - * @name Register TRNG_SBLIM, field SB_LIM[9:0] (RW) - * - * Sparse Bit Limit. During Von Neumann sampling (if enabled by MCTL[SAMP_MODE], - * samples are discarded if two consecutive raw samples are both 0 or both 1. If - * this discarding occurs for a long period of time, it indicates that there is - * insufficient Entropy. The Sparse Bit Limit defines the maximum number of - * consecutive samples that may be discarded before an error is generated. This field - * is writable only if MCTL[PRGM] bit is 1. This register is cleared to 03hF by - * writing the MCTL[RST_DEF] bit to 1. Note that if MCTL[PRGM] bit is 0, this - * register address is used to read the Total Samples count in register TOTSAM, as - * defined in the following section. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SBLIM_SB_LIM field. */ -#define TRNG_RD_SBLIM_SB_LIM(base) ((TRNG_SBLIM_REG(base) & TRNG_SBLIM_SB_LIM_MASK) >> TRNG_SBLIM_SB_LIM_SHIFT) - -/*! @brief Set the SB_LIM field to a new value. */ -#define TRNG_WR_SBLIM_SB_LIM(base, value) (TRNG_RMW_SBLIM(base, TRNG_SBLIM_SB_LIM_MASK, TRNG_SBLIM_SB_LIM(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register - ******************************************************************************/ - -/*! - * @brief TRNG_SCMISC - RNG Statistical Check Miscellaneous Register (RW) - * - * Reset value: 0x0001001FU - * - * The RNG Statistical Check Miscellaneous Register contains the Long Run - * Maximum Limit value and the Retry Count value. This register is accessible only when - * the MCTL[PRGM] bit is 1, otherwise this register will read zeroes, and cannot - * be written. - */ -/*! - * @name Constants and macros for entire TRNG_SCMISC register - */ -/*@{*/ -#define TRNG_SCMISC_REG(base) ((base)->SCMISC) -#define TRNG_RD_SCMISC(base) (TRNG_SCMISC_REG(base)) -#define TRNG_WR_SCMISC(base, value) (TRNG_SCMISC_REG(base) = (value)) -#define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) | (value))) -/*@}*/ - -/* - * Constants & macros for individual TRNG_SCMISC bitfields - */ - -/*! - * @name Register TRNG_SCMISC, field LRUN_MAX[7:0] (RW) - * - * LONG RUN MAX LIMIT. This value is the largest allowable number of consecutive - * samples of all 1, or all 0, that is allowed during the Entropy generation. - * This field is writable only if MCTL[PRGM] bit is 1. This field will read zeroes - * if MCTL[PRGM] = 0. This field is cleared to 22h by writing the MCTL[RST_DEF] - * bit to 1. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SCMISC_LRUN_MAX field. */ -#define TRNG_RD_SCMISC_LRUN_MAX(base) \ - ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_LRUN_MAX_MASK) >> TRNG_SCMISC_LRUN_MAX_SHIFT) - -/*! @brief Set the LRUN_MAX field to a new value. */ -#define TRNG_WR_SCMISC_LRUN_MAX(base, value) \ - (TRNG_RMW_SCMISC(base, TRNG_SCMISC_LRUN_MAX_MASK, TRNG_SCMISC_LRUN_MAX(value))) -/*@}*/ - -/******************************************************************************* - * TRNG_ENT - RNG TRNG Entropy Read Register - ******************************************************************************/ - -/*! - * @brief TRNG_ENT - RNG TRNG Entropy Read Register (RO) - * - * Reset value: 0x00000000U - * - * The RNG TRNG can be programmed to generate an entropy value that is readable - * via the SkyBlue bus. To do this, set the MCTL[TRNG_ACC] bit to 1. Once the - * entropy value has been generated, the MCTL[ENT_VAL] bit will be set to 1. At this - * point, ENT0 through ENT15 may be read to retrieve the 512-bit entropy value. - * Note that once ENT15 is read, the entropy value will be cleared and a new - * value will begin generation, so it is important that ENT15 be read last. These - * registers are readable only when MCTL[PRGM] = 0 (Run Mode), MCTL[TRNG_ACC] = 1 - * (TRNG access mode) and MCTL[ENT_VAL] = 1, otherwise zeroes will be read. - */ -/*! - * @name Constants and macros for entire TRNG_ENT register - */ -/*@{*/ -#define TRNG_ENT_REG(base, index) ((base)->ENT[index]) -#define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index)) -/*@}*/ - -/******************************************************************************* - * TRNG_SEC_CFG - RNG Security Configuration Register - ******************************************************************************/ - -/*! - * @brief TRNG_SEC_CFG - RNG Security Configuration Register (RW) - * - * Reset value: 0x00000000U - * - * The RNG Security Configuration Register is a read/write register used to - * control the test mode, programmability and state modes of the RNG. Many bits are - * place holders for this version. More configurability will be added here. Clears - * on asynchronous reset. For SA-TRNG releases before 2014/July/01, offsets 0xA0 - * to 0xAC used to be 0xB0 to 0xBC respectively. So, update newer tests that use - * these registers, if hard coded. - */ -/*! - * @name Constants and macros for entire TRNG_SEC_CFG register - */ -/*@{*/ -#define TRNG_SEC_CFG_REG(base) ((base)->SEC_CFG) -#define TRNG_RD_SEC_CFG(base) (TRNG_SEC_CFG_REG(base)) -#define TRNG_WR_SEC_CFG(base, value) (TRNG_SEC_CFG_REG(base) = (value)) -#define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)) | (value))) -/*@}*/ - -/*! - * @name Register TRNG_SEC_CFG, field NO_PRGM[1] (RW) - * - * If set the TRNG registers cannot be programmed. That is, regardless of the - * TRNG access mode in the SA-TRNG Miscellaneous Control Register. - * - * Values: - * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous - * Control Register's access mode bit. - * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents - * TRNG register programming. - */ -/*@{*/ -/*! @brief Read current value of the TRNG_SEC_CFG_NO_PRGM field. */ -#define TRNG_RD_SEC_CFG_NO_PRGM(base) \ - ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_NO_PRGM_MASK) >> TRNG_SEC_CFG_NO_PRGM_SHIFT) - -/*! @brief Set the NO_PRGM field to a new value. */ -#define TRNG_WR_SEC_CFG_NO_PRGM(base, value) \ - (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_NO_PRGM_MASK, TRNG_SEC_CFG_NO_PRGM(value))) -/*@}*/ - -/*! @brief Array to map TRNG instance number to base pointer. */ -static TRNG_Type *const s_trngBases[] = TRNG_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Clock array name */ -static const clock_ip_name_t s_trngClock[] = TRNG_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Prototypes - *******************************************************************************/ -static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig); -static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count); -static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base, - trng_statistical_check_t statistical_check, - const trng_statistical_check_limit_t *limit); -static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index); -static uint32_t trng_GetInstance(TRNG_Type *base); - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t trng_GetInstance(TRNG_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_trngBases); instance++) - { - if (s_trngBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_trngBases)); - - return instance; -} - -/*FUNCTION********************************************************************* - * - * Function Name : TRNG_InitUserConfigDefault - * Description : Initializes user configuration structure to default settings. - * - *END*************************************************************************/ -status_t TRNG_GetDefaultConfig(trng_config_t *userConfig) -{ - status_t result; - - if (userConfig != NULL) - { - userConfig->lock = TRNG_USER_CONFIG_DEFAULT_LOCK; - userConfig->clockMode = kTRNG_ClockModeRingOscillator; - userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV; - userConfig->sampleMode = kTRNG_SampleModeRaw; - userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY; - userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE; - userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; - - /* Statistical Check Parameters.*/ - userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT; - userConfig->longRunMaxLimit = TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT; - - userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM; - userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM; - userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM; - userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM; - userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM; - userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM; - userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM; - userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM; - userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM; - userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM; - userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM; - userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM; - userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM; - userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM; - userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM; - userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM; - userConfig->frequencyCountLimit.maximum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM; - userConfig->frequencyCountLimit.minimum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM; - - result = kStatus_Success; - } - else - { - result = kStatus_InvalidArgument; - } - - return result; -} - -/*! - * @brief Sets the TRNG retry count. - * - * This function sets the retry counter which defines the number of times a - * statistical check may fails during the TRNG Entropy Generation before - * generating an error. -*/ -static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count) -{ - status_t status; - - if ((retry_count >= 1u) && (retry_count <= 15u)) - { - /* Set retry count.*/ - TRNG_WR_SCMISC_RTY_CT(base, retry_count); - status = kStatus_Success; - } - else - { - status = kStatus_InvalidArgument; - } - return status; -} - -/*! - * @brief Sets statistical check limits. - * - * This function is used to set minimum and maximum limits of statistical checks. - * - */ -static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base, - trng_statistical_check_t statistical_check, - const trng_statistical_check_limit_t *limit) -{ - uint32_t range; - status_t status = kStatus_Success; - - if (limit && (limit->maximum > limit->minimum)) - { - range = limit->maximum - limit->minimum; /* Registers use range instead of minimum value.*/ - - switch (statistical_check) - { - case kTRNG_StatisticalCheckMonobit: /* Allowable maximum and minimum number of ones/zero detected during - entropy generation. */ - if ((range <= 0xffffu) && (limit->maximum <= 0xffffu)) - { - TRNG_WR_SCML_MONO_MAX(base, limit->maximum); - TRNG_WR_SCML_MONO_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit1: /* Allowable maximum and minimum number of runs of length 1 detected - during entropy generation. */ - if ((range <= 0x7fffu) && (limit->maximum <= 0x7fffu)) - { - TRNG_WR_SCR1L_RUN1_MAX(base, limit->maximum); - TRNG_WR_SCR1L_RUN1_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit2: /* Allowable maximum and minimum number of runs of length 2 detected - during entropy generation. */ - if ((range <= 0x3fffu) && (limit->maximum <= 0x3fffu)) - { - TRNG_WR_SCR2L_RUN2_MAX(base, limit->maximum); - TRNG_WR_SCR2L_RUN2_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit3: /* Allowable maximum and minimum number of runs of length 3 detected - during entropy generation. */ - if ((range <= 0x1fffu) && (limit->maximum <= 0x1fffu)) - { - TRNG_WR_SCR3L_RUN3_MAX(base, limit->maximum); - TRNG_WR_SCR3L_RUN3_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit4: /* Allowable maximum and minimum number of runs of length 4 detected - during entropy generation. */ - if ((range <= 0xfffu) && (limit->maximum <= 0xfffu)) - { - TRNG_WR_SCR4L_RUN4_MAX(base, limit->maximum); - TRNG_WR_SCR4L_RUN4_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit5: /* Allowable maximum and minimum number of runs of length 5 detected - during entropy generation. */ - if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) - { - TRNG_WR_SCR5L_RUN5_MAX(base, limit->maximum); - TRNG_WR_SCR5L_RUN5_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit6Plus: /* Allowable maximum and minimum number of length 6 or more detected - during entropy generation */ - if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) - { - TRNG_WR_SCR6PL_RUN6P_MAX(base, limit->maximum); - TRNG_WR_SCR6PL_RUN6P_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckPoker: /* Allowable maximum and minimum limit of "Poker Test" detected during - entropy generation . */ - if ((range <= 0xffffu) && (limit->maximum <= 0xffffffu)) - { - TRNG_WR_PKRMAX_PKR_MAX(base, limit->maximum); - TRNG_WR_PKRRNG_PKR_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckFrequencyCount: /* Allowable maximum and minimum limit of entropy sample frquency - count during entropy generation . */ - if ((limit->minimum <= 0x3fffffu) && (limit->maximum <= 0x3fffffu)) - { - TRNG_WR_FRQMAX_FRQ_MAX(base, limit->maximum); - TRNG_WR_FRQMIN_FRQ_MIN(base, limit->minimum); - } - else - { - status = kStatus_InvalidArgument; - } - break; - default: - status = kStatus_InvalidArgument; - break; - } - } - - return status; -} - -/*FUNCTION********************************************************************* - * - * Function Name : trng_ApplyUserConfig - * Description : Apply user configuration settings to TRNG module. - * - *END*************************************************************************/ -static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig) -{ - status_t status; - - if (((status = trng_SetRetryCount(base, userConfig->retryCount)) == kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus, - &userConfig->runBit6PlusLimit)) == kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount, - &userConfig->frequencyCountLimit)) == kStatus_Success)) - { - TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode); - TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv); - TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode); - TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay); - TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize); - TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit); - TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit); - } - - return status; -} - -/*! - * @brief Gets a entry data from the TRNG. - * - * This function gets an entropy data from TRNG. - * Entropy data is spread over TRNG_ENT_COUNT registers. - * Read register number is defined by index parameter. -*/ -static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index) -{ - uint32_t data; - - index = index % TRNG_ENT_COUNT; /* This way we can use incremental index without limit control from application.*/ - - data = TRNG_RD_ENT(base, index); - - if (index == (TRNG_ENT_COUNT - 1)) - { - /* Dummy read. Defect workaround. - * TRNG could not clear ENT_VAL flag automatically, application - * had to do a dummy reading operation for anyone TRNG register - * to clear it firstly, then to read the RTENT0 to RTENT15 again */ - index = TRNG_RD_ENT(base, 0); - } - - return data; -} - -status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig) -{ - status_t result; - - /* Check input parameters.*/ - if ((base != NULL) && (userConfig != NULL)) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock gate. */ - CLOCK_EnableClock(s_trngClock[trng_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Reset the registers of TRNG module to reset state. */ - /* Must be in program mode.*/ - TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram); - /* Reset Defaults.*/ - TRNG_WR_MCTL_RST_DEF(base, 1); - - /* Set configuration.*/ - if ((result = trng_ApplyUserConfig(base, userConfig)) == kStatus_Success) - { - /* Start entropy generation.*/ - /* Set to Run mode.*/ - TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeRun); -#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0)) - /* Enable TRNG Access Mode. To generate an Entropy - * value that can be read via the true0-true15 registers.*/ - TRNG_WR_MCTL_TRNG_ACC(base, 1); -#endif /* !FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC */ - - if (userConfig->lock == 1) /* Disable programmability of TRNG registers. */ - { - TRNG_WR_SEC_CFG_NO_PRGM(base, 1); - } - - result = kStatus_Success; - } - } - else - { - result = kStatus_InvalidArgument; - } - - return result; -} - -void TRNG_Deinit(TRNG_Type *base) -{ - /* Check input parameters.*/ - if (base) - { - /* Move to program mode. Stop entropy generation.*/ - TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram); - - /* Check before clock stop. - TRNG turns on the TRNG free-running ring oscillator whenever new entropy - is being generated and turns off the ring oscillator when entropy generation - is complete. If the TRNG clock is stopped while the TRNG ring oscillator - is running, the oscillator continues running though the RNG clock. - is stopped. */ - while (TRNG_RD_MCTL_TSTOP_OK(base) == 0) - { - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable Clock*/ - CLOCK_DisableClock(s_trngClock[trng_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - } -} - -status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize) -{ - status_t result = kStatus_Success; - uint32_t random_32; - uint8_t *random_p; - uint32_t random_size; - uint8_t *data_p = (uint8_t *)data; - uint32_t i; - int index = 0; - - /* Check input parameters.*/ - if (base && data && dataSize) - { - do - { - /* Wait for Valid or Error flag*/ - while ((TRNG_RD_MCTL_ENT_VAL(base) == 0) && (TRNG_RD_MCTL_ERR(base) == 0)) - { - } - - /* Check HW error.*/ - if (TRNG_RD_MCTL_ERR(base)) - { - result = kStatus_Fail; /* TRNG module error occurred */ - /* Clear error.*/ - TRNG_WR_MCTL_ERR(base, 1); - break; /* No sense stay here.*/ - } - - /* Read Entropy.*/ - random_32 = trng_ReadEntropy(base, index++); - - random_p = (uint8_t *)&random_32; - - if (dataSize < sizeof(random_32)) - { - random_size = dataSize; - } - else - { - random_size = sizeof(random_32); - } - - for (i = 0U; i < random_size; i++) - { - *data_p++ = *random_p++; - } - - dataSize -= random_size; - } while (dataSize > 0); - - /* Start a new entropy generation. - It is done by reading of the last entropy register.*/ - if ((index % TRNG_ENT_COUNT) != (TRNG_ENT_COUNT - 1)) - { - trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1)); - } - } - else - { - result = kStatus_InvalidArgument; - } - - return result; -} - -#endif /* FSL_FEATURE_SOC_TRNG_COUNT */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_trng.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_trng.h deleted file mode 100644 index de844e892e..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_trng.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_TRNG_DRIVER_H_ -#define _FSL_TRNG_DRIVER_H_ - -#include "fsl_common.h" - -#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT - -/*! - * @addtogroup trng - * @{ - */ - - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief TRNG driver version 2.0.2. - * - * Current version: 2.0.2 - * - * Change log: - * - Version 2.0.2 - * - fix MISRA issues - * - Version 2.0.1 - * - add support for KL8x and KL28Z - * - update default OSCDIV for K81 to divide by 2 - */ -#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) -/*@}*/ - -/*! @brief TRNG sample mode. Used by trng_config_t. */ -typedef enum _trng_sample_mode -{ - kTRNG_SampleModeVonNeumann = 0U, /*!< Use von Neumann data in both Entropy shifter and Statistical Checker. */ - kTRNG_SampleModeRaw = 1U, /*!< Use raw data into both Entropy shifter and Statistical Checker. */ - kTRNG_SampleModeVonNeumannRaw = - 2U /*!< Use von Neumann data in Entropy shifter. Use raw data into Statistical Checker. */ -} trng_sample_mode_t; - -/*! @brief TRNG clock mode. Used by trng_config_t. */ -typedef enum _trng_clock_mode -{ - kTRNG_ClockModeRingOscillator = 0U, /*!< Ring oscillator is used to operate the TRNG (default). */ - kTRNG_ClockModeSystem = 1U /*!< System clock is used to operate the TRNG. This is for test use only, and - indeterminate results may occur. */ -} trng_clock_mode_t; - -/*! @brief TRNG ring oscillator divide. Used by trng_config_t. */ -typedef enum _trng_ring_osc_div -{ - kTRNG_RingOscDiv0 = 0U, /*!< Ring oscillator with no divide */ - kTRNG_RingOscDiv2 = 1U, /*!< Ring oscillator divided-by-2. */ - kTRNG_RingOscDiv4 = 2U, /*!< Ring oscillator divided-by-4. */ - kTRNG_RingOscDiv8 = 3U /*!< Ring oscillator divided-by-8. */ -} trng_ring_osc_div_t; - -/*! @brief Data structure for definition of statistical check limits. Used by trng_config_t. */ -typedef struct _trng_statistical_check_limit -{ - uint32_t maximum; /*!< Maximum limit.*/ - uint32_t minimum; /*!< Minimum limit.*/ -} trng_statistical_check_limit_t; - -/*! - * @brief Data structure for the TRNG initialization - * - * This structure initializes the TRNG by calling the TRNG_Init() function. - * It contains all TRNG configurations. - */ -typedef struct _trng_user_config -{ - bool lock; /*!< @brief Disable programmability of TRNG registers. */ - trng_clock_mode_t clockMode; /*!< @brief Clock mode used to operate TRNG.*/ - trng_ring_osc_div_t ringOscDiv; /*!< @brief Ring oscillator divide used by TRNG. */ - trng_sample_mode_t sampleMode; /*!< @brief Sample mode of the TRNG ring oscillator. */ - /* Seed Control*/ - uint16_t - entropyDelay; /*!< @brief Entropy Delay. Defines the length (in system clocks) of each Entropy sample taken. */ - uint16_t sampleSize; /*!< @brief Sample Size. Defines the total number of Entropy samples that will be taken during - Entropy generation. */ - uint16_t - sparseBitLimit; /*!< @brief Sparse Bit Limit which defines the maximum number of - * consecutive samples that may be discarded before an error is generated. - * This limit is used only for during von Neumann sampling (enabled by TRNG_HAL_SetSampleMode()). - * Samples are discarded if two consecutive raw samples are both 0 or both 1. If - * this discarding occurs for a long period of time, it indicates that there is - * insufficient Entropy. */ - /* Statistical Check Parameters.*/ - uint8_t retryCount; /*!< @brief Retry count. It defines the number of times a statistical check may fails - * during the TRNG Entropy Generation before generating an error. */ - uint8_t longRunMaxLimit; /*!< @brief Largest allowable number of consecutive samples of all 1, or all 0, - * that is allowed during the Entropy generation. */ - trng_statistical_check_limit_t - monobitLimit; /*!< @brief Maximum and minimum limits for statistical check of number of ones/zero detected - during entropy generation. */ - trng_statistical_check_limit_t - runBit1Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 1 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit2Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 2 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit3Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 3 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit4Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 4 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit5Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 5 - detected during entropy generation. */ - trng_statistical_check_limit_t runBit6PlusLimit; /*!< @brief Maximum and minimum limits for statistical check of - number of runs of length 6 or more detected during entropy - generation. */ - trng_statistical_check_limit_t - pokerLimit; /*!< @brief Maximum and minimum limits for statistical check of "Poker Test". */ - trng_statistical_check_limit_t - frequencyCountLimit; /*!< @brief Maximum and minimum limits for statistical check of entropy sample frequency - count. */ -} trng_config_t; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initializes the user configuration structure to default values. - * - * This function initializes the configuration structure to default values. The default - * values are as follows. - * @code - * user_config->lock = 0; - * user_config->clockMode = kTRNG_ClockModeRingOscillator; - * user_config->ringOscDiv = kTRNG_RingOscDiv0; Or to other kTRNG_RingOscDiv[2|8] depending on the platform. - * user_config->sampleMode = kTRNG_SampleModeRaw; - * user_config->entropyDelay = 3200; - * user_config->sampleSize = 2500; - * user_config->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; - * user_config->retryCount = 63; - * user_config->longRunMaxLimit = 34; - * user_config->monobitLimit.maximum = 1384; - * user_config->monobitLimit.minimum = 1116; - * user_config->runBit1Limit.maximum = 405; - * user_config->runBit1Limit.minimum = 227; - * user_config->runBit2Limit.maximum = 220; - * user_config->runBit2Limit.minimum = 98; - * user_config->runBit3Limit.maximum = 125; - * user_config->runBit3Limit.minimum = 37; - * user_config->runBit4Limit.maximum = 75; - * user_config->runBit4Limit.minimum = 11; - * user_config->runBit5Limit.maximum = 47; - * user_config->runBit5Limit.minimum = 1; - * user_config->runBit6PlusLimit.maximum = 47; - * user_config->runBit6PlusLimit.minimum = 1; - * user_config->pokerLimit.maximum = 26912; - * user_config->pokerLimit.minimum = 24445; - * user_config->frequencyCountLimit.maximum = 25600; - * user_config->frequencyCountLimit.minimum = 1600; - * @endcode - * - * @param user_config User configuration structure. - * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. - */ -status_t TRNG_GetDefaultConfig(trng_config_t *userConfig); - -/*! - * @brief Initializes the TRNG. - * - * This function initializes the TRNG. - * When called, the TRNG entropy generation starts immediately. - * - * @param base TRNG base address - * @param userConfig Pointer to the initialization configuration structure. - * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. - */ -status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig); - -/*! - * @brief Shuts down the TRNG. - * - * This function shuts down the TRNG. - * - * @param base TRNG base address. - */ -void TRNG_Deinit(TRNG_Type *base); - -/*! - * @brief Gets random data. - * - * This function gets random data from the TRNG. - * - * @param base TRNG base address. - * @param data Pointer address used to store random data. - * @param dataSize Size of the buffer pointed by the data parameter. - * @return random data - */ -status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize); - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* FSL_FEATURE_SOC_TRNG_COUNT */ -#endif /*_FSL_TRNG_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_tsc.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_tsc.c deleted file mode 100644 index 75f5c62d21..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_tsc.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_tsc.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.tsc" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get instance number for TSC module. - * - * @param base TSC peripheral base address - */ -static uint32_t TSC_GetInstance(TSC_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to TSC bases for each instance. */ -static TSC_Type *const s_tscBases[] = TSC_BASE_PTRS; - -/*! @brief Pointers to ADC clocks for each instance. */ -static const clock_ip_name_t s_tscClocks[] = TSC_CLOCKS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t TSC_GetInstance(TSC_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_tscBases); instance++) - { - if (s_tscBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_tscBases)); - - return instance; -} - -void TSC_Init(TSC_Type *base, const tsc_config_t *config) -{ - assert(NULL != config); - assert(config->measureDelayTime <= 0xFFFFFFU); - - uint32_t tmp32; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the TSC clock. */ - CLOCK_EnableClock(s_tscClocks[TSC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Configure TSC_BASIC_SETTING register. */ - tmp32 = TSC_BASIC_SETTING_MEASURE_DELAY_TIME(config->measureDelayTime) | - TSC_BASIC_SETTING__4_5_WIRE(config->detectionMode); - if (config->enableAutoMeasure) - { - tmp32 |= TSC_BASIC_SETTING_AUTO_MEASURE_MASK; - } - base->BASIC_SETTING = tmp32; - /* Configure TSC_PS_INPUT_BUFFER_ADDR register. */ - base->PRE_CHARGE_TIME = TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(config->prechargeTime); -} - -void TSC_Deinit(TSC_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the TSC clcok. */ - CLOCK_DisableClock(s_tscClocks[TSC_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void TSC_GetDefaultConfig(tsc_config_t *config) -{ - config->enableAutoMeasure = false; - config->measureDelayTime = 0xFFFFU; - config->prechargeTime = 0xFFFFU; - config->detectionMode = kTSC_Detection4WireMode; -} - -uint32_t TSC_GetMeasureValue(TSC_Type *base, tsc_corrdinate_value_selection_t selection) -{ - uint32_t tmp32 = 0; - - if (selection == kTSC_XCoordinateValueSelection) - { - tmp32 = ((base->MEASEURE_VALUE) & TSC_MEASEURE_VALUE_X_VALUE_MASK) >> TSC_MEASEURE_VALUE_X_VALUE_SHIFT; - } - else if (selection == kTSC_YCoordinateValueSelection) - { - tmp32 = ((base->MEASEURE_VALUE) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) >> TSC_MEASEURE_VALUE_Y_VALUE_SHIFT; - } - else - { - } - return tmp32; -} - -void TSC_DebugTriggerSignalToADC(TSC_Type *base, tsc_trigger_signal_t hwts, bool enable) -{ - if (enable) - { - /* TSC_DEBUG_MODE_EXT_HWTS field should be writed before writing TSC_DEBUG_MODE_TRIGGER field. - If the two fields are writed at the same time, the trigger couldn't work as expect. */ - base->DEBUG_MODE &= ~TSC_DEBUG_MODE_EXT_HWTS_MASK; - base->DEBUG_MODE |= TSC_DEBUG_MODE_EXT_HWTS(hwts); - base->DEBUG_MODE |= TSC_DEBUG_MODE_TRIGGER_MASK; - } - else - { - base->DEBUG_MODE &= ~TSC_DEBUG_MODE_TRIGGER_MASK; - } -} - -void TSC_DebugEnableDetection(TSC_Type *base, tsc_detection_mode_t detectionMode, bool enable) -{ - if (detectionMode == kTSC_Detection4WireMode) - { - if (enable) - { - base->DEBUG_MODE2 |= TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK; - } - else - { - base->DEBUG_MODE2 &= ~TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK; - } - } - else if (detectionMode == kTSC_Detection5WireMode) - { - if (enable) - { - base->DEBUG_MODE2 |= TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK; - } - else - { - base->DEBUG_MODE2 &= ~TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK; - } - } - else - { - } -} - -void TSC_DebugSetPortMode(TSC_Type *base, tsc_port_source_t port, tsc_port_mode_t mode) -{ - uint32_t tmp32; - - tmp32 = base->DEBUG_MODE2; - switch (port) - { - case kTSC_WiperPortSource: - tmp32 &= ~(TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK | - TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK); - tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT); - break; - case kTSC_YnlrPortSource: - tmp32 &= ~(TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK | - TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK); - tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT); - break; - case kTSC_YpllPortSource: - tmp32 &= ~(TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK | - TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK); - tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT); - break; - case kTSC_XnurPortSource: - tmp32 &= ~(TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK | - TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK); - tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT); - break; - case kTSC_XpulPortSource: - tmp32 &= ~(TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK | - TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK); - tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT); - break; - default: - break; - } - base->DEBUG_MODE2 = tmp32; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_tsc.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_tsc.h deleted file mode 100644 index 84ea320633..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_tsc.h +++ /dev/null @@ -1,548 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_TSC_H_ -#define _FSL_TSC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup tsc - * @{ - */ - -/******************************************************************************* -* Definitions -******************************************************************************/ -/*! @brief TSC driver version */ -#define FSL_TSC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - -/*! -* @ Controller detection mode. -*/ -typedef enum _tsc_detection_mode -{ - kTSC_Detection4WireMode = 0U, /*!< 4-Wire Detection Mode. */ - kTSC_Detection5WireMode = 1U, /*!< 5-Wire Detection Mode. */ -} tsc_detection_mode_t; - -/*! -* @ Coordinate value mask. -*/ -typedef enum _tsc_corrdinate_value_selection -{ - kTSC_XCoordinateValueSelection = 0U, /*!< X coordinate value is selected. */ - kTSC_YCoordinateValueSelection = 1U, /*!< Y coordinate value is selected. */ -} tsc_corrdinate_value_selection_t; - -/*! -* @ Interrupt signal enable/disable mask. -*/ -enum _tsc_interrupt_signal_mask -{ - kTSC_IdleSoftwareSignalEnable = TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK, /*!< Enable the interrupt signal when the - controller has return to idle status. - The signal is only valid after using - TSC_ReturnToIdleStatus API. */ - kTSC_ValidSignalEnable = - TSC_INT_SIG_EN_VALID_SIG_EN_MASK, /*!< Enable the interrupt signal when controller receives a detect signal - after measurement. */ - kTSC_DetectSignalEnable = - TSC_INT_SIG_EN_DETECT_SIG_EN_MASK, /*!< Enable the interrupt signal when controller receives a detect signal. */ - kTSC_MeasureSignalEnable = TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK, /*!< Enable the interrupt signal after the touch - detection which follows measurement. */ -}; - -/*! -* @ Interrupt enable/disable mask. -*/ -enum _tsc_interrupt_mask -{ - kTSC_IdleSoftwareInterruptEnable = - TSC_INT_EN_IDLE_SW_INT_EN_MASK, /*!< Enable the interrupt when the controller has return to idle status. - The interrupt is only valid after using TSC_ReturnToIdleStatus API. */ - kTSC_DetectInterruptEnable = - TSC_INT_EN_DETECT_INT_EN_MASK, /*!< Enable the interrupt when controller receive a detect signal. */ - kTSC_MeasureInterruptEnable = TSC_INT_EN_MEASURE_INT_EN_MASK, /*!< Enable the interrupt after the touch detection - which follows measurement. */ -}; - -/*! -* @ Interrupt Status flag mask. -*/ -enum _tsc_interrupt_status_flag_mask -{ - kTSC_IdleSoftwareFlag = - TSC_INT_STATUS_IDLE_SW_MASK, /*!< This flag is set if the controller has return to idle status. - The flag is only valid after using TSC_ReturnToIdleStatus API. */ - kTSC_ValidSignalFlag = - TSC_INT_STATUS_VALID_MASK, /*!< This flag is set if controller receives a detect signal after measurement. */ - kTSC_DetectSignalFlag = TSC_INT_STATUS_DETECT_MASK, /*!< This flag is set if controller receives a detect signal. */ - kTSC_MeasureSignalFlag = - TSC_INT_STATUS_MEASURE_MASK, /*!< This flag is set after the touch detection which follows measurement. - Note: Valid signal falg will be cleared along with measure signal flag. */ -}; - -/*! -* @ ADC status flag mask. -*/ -enum _tsc_adc_status_flag_mask -{ - kTSC_ADCCOCOSignalFlag = - TSC_DEBUG_MODE_ADC_COCO_MASK, /*!< This signal is generated by ADC when a conversion is completed. */ - kTSC_ADCConversionValueFlag = - TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK, /*!< This signal is generated by ADC and indicates the result of an ADC - conversion. */ -}; - -/*! -* @ TSC status flag mask. -*/ -enum _tsc_status_flag_mask -{ - kTSC_IntermediateStateFlag = TSC_DEBUG_MODE2_INTERMEDIATE_MASK, /*!< This flag is set if TSC is in intermediate - state, between two state machine states. */ - kTSC_DetectFiveWireFlag = TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK, /*!< This flag is set if TSC receives a 5-wire - detect signal. It is only valid when the TSC in - detect state and DETECT_ENABLE_FIVE_WIRE bit is - set. */ - kTSC_DetectFourWireFlag = TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK, /*!< This flag is set if TSC receives a 4-wire - detect signal. It is only valid when the TSC in - detect state and DETECT_ENABLE_FOUR_WIRE bit is - set. */ - kTSC_GlitchThresholdFlag = TSC_DEBUG_MODE2_DE_GLITCH_MASK, /*!< This field indicates glitch threshold.The threshold - is defined by number of clock cycles. See - "tsc_glitch_threshold_t". - If value = 00, Normal function: 0x1fff ipg clock - cycles, Low power mode: 0x9 low power clock cycles. - If value = 01, Normal function: 0xfff ipg clock - cycles, Low power mode: :0x7 low power clock cycles. - If value = 10, Normal function: 0x7ff ipg clock - cycles, Low power mode:0x5 low power clock cycles. - If value = 11, Normal function: 0x3 ipg clock - cycles, Low power mode:0x3 low power clock cycles. */ - kTSC_StateMachineFlag = - TSC_DEBUG_MODE2_STATE_MACHINE_MASK, /*!< This field indicates the state of TSC. See "tsc_state_machine_t"; - if value = 000, Controller is in idle state. - if value = 001, Controller is in 1st-Pre-charge state. - if value = 010, Controller is in 1st-detect state. - if value = 011, Controller is in x-measure state. - if value = 100, Controller is in y-measure state. - if value = 101, Controller is in 2nd-Pre-charge state. - if value = 110, Controller is in 2nd-detect state. */ -}; - -/*! -* @brief TSC state machine. These seven states are TSC complete workflow. -*/ -typedef enum _tsc_state_machine -{ - kTSC_IdleState = 0U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in idle state. */ - kTSC_1stPreChargeState = 1U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 1st-Pre-charge state. */ - kTSC_1stDetectState = 2U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 1st-detect state. */ - kTSC_XMeasureState = 3U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in x-measure state. */ - kTSC_YMeasureState = 4U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in y-measure state. */ - kTSC_2ndPreChargeState = 5U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 2nd-Pre-charge state. */ - kTSC_2ndDetectState = 6U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 2nd-detect state. */ -} tsc_state_machine_t; - -/*! -* @brief TSC glitch threshold. -*/ -typedef enum _tsc_glitch_threshold -{ - kTSC_glitchThresholdALT0 = - 0U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x1fff ipg clock cycles, Low power mode: 0x9 low - power clock cycles. */ - kTSC_glitchThresholdALT1 = - 1U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0xfff ipg clock cycles, Low power mode: :0x7 low - power clock cycles. */ - kTSC_glitchThresholdALT2 = - 2U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x7ff ipg clock cycles, Low power mode: :0x5 low - power clock cycles. */ - kTSC_glitchThresholdALT3 = - 3U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x3 ipg clock cycles, Low - power mode: :0x3 low power clock cycles. */ -} tsc_glitch_threshold_t; - -/*! -* @ Hardware trigger select signal, select which ADC channel to start conversion. -*/ -typedef enum _tsc_trigger_signal -{ - kTSC_TriggerToChannel0 = 1U << 0U, /*!< Trigger to ADC channel0. ADC_HC0 register will be used to conversion. */ - kTSC_TriggerToChannel1 = 1U << 1U, /*!< Trigger to ADC channel1. ADC_HC1 register will be used to conversion. */ - kTSC_TriggerToChannel2 = 1U << 2U, /*!< Trigger to ADC channel2. ADC_HC2 register will be used to conversion. */ - kTSC_TriggerToChannel3 = 1U << 3U, /*!< Trigger to ADC channel3. ADC_HC3 register will be used to conversion. */ - kTSC_TriggerToChannel4 = 1U << 4U, /*!< Trigger to ADC channel4. ADC_HC4 register will be used to conversion. */ -} tsc_trigger_signal_t; - -/*! -* @ TSC controller ports. -*/ -typedef enum _tsc_port_source -{ - kTSC_WiperPortSource = 0U, /*!< TSC controller wiper port. */ - kTSC_YnlrPortSource = 1U, /*!< TSC controller ynlr port. */ - kTSC_YpllPortSource = 2U, /*!< TSC controller ypll port. */ - kTSC_XnurPortSource = 3U, /*!< TSC controller xnur port. */ - kTSC_XpulPortSource = 4U, /*!< TSC controller xpul port. */ -} tsc_port_source_t; - -/*! -* @ TSC port mode. -*/ -typedef enum _tsc_port_mode -{ - kTSC_PortOffMode = 0U, /*!< Disable pull up/down mode. */ - kTSC_Port200k_PullUpMode = 1U << 2U, /*!< 200k-pull up mode. */ - kTSC_PortPullUpMode = 1U << 1U, /*!< Pull up mode. */ - kTSC_PortPullDownMode = 1U << 0U, /*!< Pull down mode. */ -} tsc_port_mode_t; - -/*! -* @ Controller configuration. -*/ -typedef struct _tsc_config -{ - bool enableAutoMeasure; /*!< Enable the auto-measure. It indicates after detect touch, whether automatic start - measurement */ - uint32_t measureDelayTime; /*!< Set delay time(0U~0xFFFFFFU) to even potential distribution ready.It is a - preparation for measure stage. If measure dalay time is too short, maybe it would - have an undesired effect on measure value. */ - uint32_t prechargeTime; /*!< Set pre-charge time(1U~0xFFFFFFFFU) to make the upper layer of - screen to charge to positive high. It is a preparation for detection stage. - Pre-charge time must is greater than 0U, otherwise TSC could not work normally. - If pre-charge dalay time is too short, maybe it would have an undesired effect on - generation of valid signal(kTSC_ValidSignalFlag).*/ - tsc_detection_mode_t detectionMode; /*!< Select the detection mode. See "tsc_detection_mode_t". */ -} tsc_config_t; - -/******************************************************************************* -* API -******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! -* @brief Initialize the TSC module. -* -* @param base TSC peripheral base address. -* @param config Pointer to "tsc_config_t" structure. -*/ -void TSC_Init(TSC_Type *base, const tsc_config_t *config); - -/*! -* @brief De-initializes the TSC module. -* -* @param base TSC peripheral base address. -*/ -void TSC_Deinit(TSC_Type *base); - -/*! -* @brief Gets an available pre-defined settings for the controller's configuration. -* -* This function initializes the converter configuration structure with available settings. -* The default values of measureDelayTime and prechargeTime is tested on LCD8000-43T screen and work normally. -* The default values are: -* @code -* config->enableAutoMeausre = false; -* config->measureDelayTime = 0xFFFFU; -* config->prechargeTime = 0xFFFFU; -* config->detectionMode = kTSC_4WireDetectionMode; -* @endCode -* @param config Pointer to "tsc_config_t" structure. -*/ -void TSC_GetDefaultConfig(tsc_config_t *config); - -/*! -* @brief Make the TSC module return to idle status after finish the current state operation. -* Application could check TSC status to confirm that the controller has return to idle status. -* -* @param base TSC peripheral base address. -*/ -static inline void TSC_ReturnToIdleStatus(TSC_Type *base) -{ - /* TSC_FLOW_CONTROL_DISABLE_MASK is a HW self-clean bit. */ - base->FLOW_CONTROL |= TSC_FLOW_CONTROL_DISABLE_MASK; -} - -/*! -* @brief Start sense detection and (if work in auto-measure mode) measure after detect a touch. -* -* @param base TSC peripheral base address. -*/ -static inline void TSC_StartSenseDetection(TSC_Type *base) -{ - /* TSC_FLOW_CONTROL_START_SENSE_MASK is a HW self-clean bit. */ - base->FLOW_CONTROL |= TSC_FLOW_CONTROL_START_SENSE_MASK; -} - -/*! -* @brief start measure X/Y coordinate value after detect a touch. -* -* @param base TSC peripheral base address. -*/ -static inline void TSC_StartMeasure(TSC_Type *base) -{ - /* TSC_FLOW_CONTROL_START_MEASURE_MASK is a HW self-clean bit. */ - base->FLOW_CONTROL |= TSC_FLOW_CONTROL_START_MEASURE_MASK; -} - -/*! -* @brief Drop measure X/Y coordinate value after detect a touch and controller return to idle status. -* -* @param base TSC peripheral base address. -*/ -static inline void TSC_DropMeasure(TSC_Type *base) -{ - /* TSC_FLOW_CONTROL_DROP_MEASURE_MASK is a HW self-clean bit. */ - base->FLOW_CONTROL |= TSC_FLOW_CONTROL_DROP_MEASURE_MASK; -} - -/*! -* @brief This is a synchronization reset, which resets every register except IPS directly access ones. -* -* @param base TSC peripheral base address. -*/ -static inline void TSC_SoftwareReset(TSC_Type *base) -{ - /* TSC_FLOW_CONTROL_SW_RST_MASK is a HW self-clean bit. */ - base->FLOW_CONTROL |= TSC_FLOW_CONTROL_SW_RST_MASK; -} - -/*! -* @brief Get Y coordinate value or X coordinate value. The value is an ADC conversion value. -* -* @param base TSC peripheral base address. -* @param selection Select alternative measure value which is Y coordinate value or X coordinate value. -* See "tsc_corrdinate_value_selection_t". -* @return If selection is "kTSC_XCoordinateValueSelection", the API returns x-coordinate vlaue. -* If selection is "kTSC_YCoordinateValueSelection", the API returns y-coordinate vlaue. -*/ -uint32_t TSC_GetMeasureValue(TSC_Type *base, tsc_corrdinate_value_selection_t selection); - -/*! -* @brief Enable the interrupt signals. Interrupt signal will be set when corresponding event happens. -* Specific events point to "_tsc_interrupt_signal_mask" . -* Specific interrupt signal point to "_tsc_interrupt_status_flag_mask"; -* -* @param base TSC peripheral base address. -* @param mask Interrupt signals mask. See "_tsc_interrupt_signal_mask". -*/ -static inline void TSC_EnableInterruptSignals(TSC_Type *base, uint32_t mask) -{ - base->INT_SIG_EN |= mask; -} - -/*! -* @brief Disable the interrupt signals. Interrupt signal will be set when corresponding event happens. -* Specific events point to "_tsc_interrupt_signal_mask". -* Specific interrupt signal point to "_tsc_interrupt_status_flag_mask"; -* -* @param base TSC peripheral base address. -* @param mask Interrupt signals mask. See "_tsc_interrupt_signal_mask". -*/ -static inline void TSC_DisableInterruptSignals(TSC_Type *base, uint32_t mask) -{ - base->INT_SIG_EN &= ~mask; -} - -/*! -* @brief Enable the interrupts. Notice: Only interrupts and signals are all enabled, interrupts -* could work normally. -* -* @param base TSC peripheral base address. -* @param mask Interrupts mask. See "_tsc_interrupt_mask". -*/ -static inline void TSC_EnableInterrupts(TSC_Type *base, uint32_t mask) -{ - base->INT_EN |= mask; -} - -/*! -* @brief Disable the interrupts. -* -* @param base TSC peripheral base address. -* @param mask Interrupts mask. See "_tsc_interrupt_mask". -*/ -static inline void TSC_DisableInterrupts(TSC_Type *base, uint32_t mask) -{ - base->INT_EN &= ~mask; -} - -/*! -* @brief Get interrupt status flags. Interrupt status falgs are valid when corresponding -* interrupt signals are enabled. -* -* @param base TSC peripheral base address. -* @return Status flags asserted mask. See "_tsc_interrupt_status_flag_mask". -*/ -static inline uint32_t TSC_GetInterruptStatusFlags(TSC_Type *base) -{ - return base->INT_STATUS; -} - -/*! -* @brief Clear interrupt status flags. Interrupt status falgs are valid when corresponding -* interrupt signals are enabled. -* -* @param base TSC peripheral base address. -* @param mask Status flags mask. See "_tsc_interrupt_status_flag_mask". -*/ -static inline void TSC_ClearInterruptStatusFlags(TSC_Type *base, uint32_t mask) -{ - base->INT_STATUS = mask; -} - -/*! -* @brief Get the status flags of ADC working with TSC. -* -* @param base TSC peripheral base address. -* @return Status flags asserted mask. See "_tsc_adc_status_flag_mask". -*/ -static inline uint32_t TSC_GetADCStatusFlags(TSC_Type *base) -{ - return base->DEBUG_MODE; -} - -/*! -* @brief Get the status flags of TSC. -* -* @param base TSC peripheral base address. -* @return Status flags asserted mask. See "_tsc_status_flag_mask". -*/ -static inline uint32_t TSC_GetStatusFlags(TSC_Type *base) -{ - return base->DEBUG_MODE2; -} - -/*! - *@} - */ - -/******************************************************************************* - * Debug API - ******************************************************************************/ - -/*! -* @brief Enable/Disable debug mode. Once work in debug mode, then all -* TSC outputs will be controlled by software. Software can also observe all TSC inputs -* through debug interface. Furthermore, the debug registers also provides current state -* machine states. Software can always check the current hardware state. -* -* @param base TSC peripheral base address. -* @param enable Switcher of the debug mode. "true" means debug mode,"false" means non-debug mode. -*/ -static inline void TSC_EnableDebugMode(TSC_Type *base, bool enable) -{ - if (enable) - { - base->DEBUG_MODE |= TSC_DEBUG_MODE_DEBUG_EN_MASK; - } - else - { - base->DEBUG_MODE &= ~TSC_DEBUG_MODE_DEBUG_EN_MASK; - } -} - -/*! -* @brief Send hardware trigger signal to ADC in debug mode. The trigger signal must last at least 1 ips clock period. -* -* @param base TSC peripheral base address. -* @param hwts Hardware trigger select signal, select which channel to start conversion. See "tsc_trigger_signal_t". -* On ADC side, HWTS = 1 << x indicates the x logic channel is selected to start hardware ADC conversion. -* @param enable Switcher of the trigger signal. "true" means generate trigger signal, "false" means don't generate -* trigger signal. -*/ -void TSC_DebugTriggerSignalToADC(TSC_Type *base, tsc_trigger_signal_t hwts, bool enable); - -/*! -* @brief Enable/Disable hardware generates an ADC COCO clear signal in debug mode. -* -* @param base TSC peripheral base address. -* @param enable Switcher of the function of hardware generating an ADC COCO clear signal. -* "true" means prevent TSC from generate ADC COCO clear signal. -* "false" means allow TSC hardware generates ADC COCO clear. -*/ -static inline void TSC_DebugDisableHWClear(TSC_Type *base, bool enable) -{ - if (enable) - { - base->DEBUG_MODE |= TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK; - } - else - { - base->DEBUG_MODE &= ~TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK; - } -} - -/*! -* @brief Send clear ADC COCO signal to ADC in debug mode. The signal must hold a while. -* -* @param base TSC peripheral base address. -* @param enable Switcher of the clear signal."true" means generate clear signal, "false" means don't generate -* clear signal. -*/ -static inline void TSC_DebugClearSignalToADC(TSC_Type *base, bool enable) -{ - if (enable) - { - base->DEBUG_MODE |= TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK; - } - else - { - base->DEBUG_MODE &= ~TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK; - } -} - -/*! -* @brief Enable/Disable detection in debug mode. -* -* @param base TSC peripheral base address. -* @param detectionMode Set detect mode. See "tsc_detection_mode_t" -* @param enable Switcher of detect enable. "true" means enable detection, "false" means disable detection. -*/ -void TSC_DebugEnableDetection(TSC_Type *base, tsc_detection_mode_t detectionMode, bool enable); - -/*! -* @brief Set TSC port mode in debug mode.(pull down, pull up and 200k-pull up) -* -* @param base TSC peripheral base address. -* @param port TSC controller ports. -* @param mode TSC port mode.(pull down, pull up and 200k-pull up) -*/ -void TSC_DebugSetPortMode(TSC_Type *base, tsc_port_source_t port, tsc_port_mode_t mode); -#endif /* _FSL_TSC_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_usdhc.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_usdhc.c deleted file mode 100644 index d5145ff5cf..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_usdhc.c +++ /dev/null @@ -1,1796 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_usdhc.h" -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL -#include "fsl_cache.h" -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.usdhc" -#endif - -/*! @brief Clock setting */ -/* Max SD clock divisor from base clock */ -#define USDHC_MAX_DVS ((USDHC_SYS_CTRL_DVS_MASK >> USDHC_SYS_CTRL_DVS_SHIFT) + 1U) -#define USDHC_MAX_CLKFS ((USDHC_SYS_CTRL_SDCLKFS_MASK >> USDHC_SYS_CTRL_SDCLKFS_SHIFT) + 1U) -#define USDHC_PREV_DVS(x) ((x) -= 1U) -#define USDHC_PREV_CLKFS(x, y) ((x) >>= (y)) - -/* Typedef for interrupt handler. */ -typedef void (*usdhc_isr_t)(USDHC_Type *base, usdhc_handle_t *handle); -/*! @brief Dummy data buffer for mmc boot mode */ -AT_NONCACHEABLE_SECTION_ALIGN(uint32_t s_usdhcBootDummy, USDHC_ADMA2_ADDRESS_ALIGN); -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get the instance. - * - * @param base USDHC peripheral base address. - * @return Instance number. - */ -static uint32_t USDHC_GetInstance(USDHC_Type *base); - -/*! - * @brief Set transfer interrupt. - * - * @param base USDHC peripheral base address. - * @param usingInterruptSignal True to use IRQ signal. - */ -static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSignal); - -/*! - * @brief Start transfer according to current transfer state - * - * @param base USDHC peripheral base address. - * @param data Data to be transferred. - * @param flag data present flag - */ -static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data, uint32_t *dataPresentFlag); - -/*! - * @brief Receive command response - * - * @param base USDHC peripheral base address. - * @param command Command to be sent. - */ -static status_t USDHC_ReceiveCommandResponse(USDHC_Type *base, usdhc_command_t *command); - -/*! - * @brief Read DATAPORT when buffer enable bit is set. - * - * @param base USDHC peripheral base address. - * @param data Data to be read. - * @param transferredWords The number of data words have been transferred last time transaction. - * @return The number of total data words have been transferred after this time transaction. - */ -static uint32_t USDHC_ReadDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords); - -/*! - * @brief Read data by using DATAPORT polling way. - * - * @param base USDHC peripheral base address. - * @param data Data to be read. - * @retval kStatus_Fail Read DATAPORT failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data); - -/*! - * @brief Write DATAPORT when buffer enable bit is set. - * - * @param base USDHC peripheral base address. - * @param data Data to be read. - * @param transferredWords The number of data words have been transferred last time. - * @return The number of total data words have been transferred after this time transaction. - */ -static uint32_t USDHC_WriteDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords); - -/*! - * @brief Write data by using DATAPORT polling way. - * - * @param base USDHC peripheral base address. - * @param data Data to be transferred. - * @retval kStatus_Fail Write DATAPORT failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data); - -/*! - * @brief Transfer data by polling way. - * - * @param base USDHC peripheral base address. - * @param data Data to be transferred. - * @param use DMA flag. - * @retval kStatus_Fail Transfer data failed. - * @retval kStatus_InvalidArgument Argument is invalid. - * @retval kStatus_Success Operate successfully. - */ -static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, bool enDMA); - -/*! - * @brief Handle card detect interrupt. - * - * @param base USDHC peripheral base address. - * @param handle USDHC handle. - * @param interruptFlags Card detect related interrupt flags. - */ -static void USDHC_TransferHandleCardDetect(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); - -/*! - * @brief Handle command interrupt. - * - * @param base USDHC peripheral base address. - * @param handle USDHC handle. - * @param interruptFlags Command related interrupt flags. - */ -static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); - -/*! - * @brief Handle data interrupt. - * - * @param base USDHC peripheral base address. - * @param handle USDHC handle. - * @param interruptFlags Data related interrupt flags. - */ -static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); - -/*! - * @brief Handle SDIO card interrupt signal. - * - * @param base USDHC peripheral base address. - * @param handle USDHC handle. - */ -static void USDHC_TransferHandleSdioInterrupt(USDHC_Type *base, usdhc_handle_t *handle); - -/*! - * @brief Handle SDIO block gap event. - * - * @param base USDHC peripheral base address. - * @param handle USDHC handle. - */ -static void USDHC_TransferHandleBlockGap(USDHC_Type *base, usdhc_handle_t *handle); - -/*! -* @brief Handle retuning -* -* @param base USDHC peripheral base address. -* @param handle USDHC handle. -* @param interrupt flags -*/ -static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); - -/*! -* @brief wait command done -* -* @param base USDHC peripheral base address. -* @param command configuration -* @param pollingCmdDone polling command done flag -*/ -static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command, bool pollingCmdDone); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief USDHC base pointer array */ -static USDHC_Type *const s_usdhcBase[] = USDHC_BASE_PTRS; - -/*! @brief USDHC internal handle pointer array */ -static usdhc_handle_t *s_usdhcHandle[ARRAY_SIZE(s_usdhcBase)] = {NULL}; - -/*! @brief USDHC IRQ name array */ -static const IRQn_Type s_usdhcIRQ[] = USDHC_IRQS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief USDHC clock array name */ -static const clock_ip_name_t s_usdhcClock[] = USDHC_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/* USDHC ISR for transactional APIs. */ -static usdhc_isr_t s_usdhcIsr; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t USDHC_GetInstance(USDHC_Type *base) -{ - uint8_t instance = 0; - - while ((instance < ARRAY_SIZE(s_usdhcBase)) && (s_usdhcBase[instance] != base)) - { - instance++; - } - - assert(instance < ARRAY_SIZE(s_usdhcBase)); - - return instance; -} - -static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSignal) -{ - uint32_t interruptEnabled; /* The Interrupt status flags to be enabled */ - - /* Disable all interrupts */ - USDHC_DisableInterruptStatus(base, (uint32_t)kUSDHC_AllInterruptFlags); - USDHC_DisableInterruptSignal(base, (uint32_t)kUSDHC_AllInterruptFlags); - DisableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]); - - interruptEnabled = (kUSDHC_CommandFlag | kUSDHC_CardInsertionFlag | kUSDHC_DataFlag | kUSDHC_CardRemovalFlag | - kUSDHC_SDR104TuningFlag | kUSDHC_BlockGapEventFlag); - - USDHC_EnableInterruptStatus(base, interruptEnabled); - - if (usingInterruptSignal) - { - USDHC_EnableInterruptSignal(base, interruptEnabled); - } -} - -static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data, uint32_t *dataPresentFlag) -{ - uint32_t mixCtrl = base->MIX_CTRL; - - if (data != NULL) - { - /* if transfer boot continous, only need set the CREQ bit, leave others as it is */ - if (data->dataType == kUSDHC_TransferDataBootcontinous) - { - /* clear stop at block gap request */ - base->PROT_CTRL &= ~USDHC_PROT_CTRL_SABGREQ_MASK; - /* continous transfer data */ - base->PROT_CTRL |= USDHC_PROT_CTRL_CREQ_MASK; - return kStatus_Success; - } - - /* check data inhibit flag */ - if (base->PRES_STATE & kUSDHC_DataInhibitFlag) - { - return kStatus_USDHC_BusyTransferring; - } - /* check transfer block count */ - if ((data->blockCount > USDHC_MAX_BLOCK_COUNT) || ((data->txData == NULL) && (data->rxData == NULL))) - { - return kStatus_InvalidArgument; - } - - /* config mix parameter */ - mixCtrl &= ~(USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | - USDHC_MIX_CTRL_AC12EN_MASK); - - if (data->rxData) - { - mixCtrl |= USDHC_MIX_CTRL_DTDSEL_MASK; - } - if (data->blockCount > 1U) - { - mixCtrl |= USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK; - /* auto command 12 */ - if (data->enableAutoCommand12) - { - mixCtrl |= USDHC_MIX_CTRL_AC12EN_MASK; - } - } - - /* auto command 23, auto send set block count cmd before multiple read/write */ - if ((data->enableAutoCommand23)) - { - mixCtrl |= USDHC_MIX_CTRL_AC23EN_MASK; - base->VEND_SPEC2 |= USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK; - /* config the block count to DS_ADDR */ - base->DS_ADDR = data->blockCount; - } - else - { - mixCtrl &= ~USDHC_MIX_CTRL_AC23EN_MASK; - base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK; - } - - /* if transfer boot data, leave the block count to USDHC_SetMmcBootConfig function */ - if (data->dataType != kUSDHC_TransferDataBoot) - { - /* config data block size/block count */ - base->BLK_ATT = ((base->BLK_ATT & ~(USDHC_BLK_ATT_BLKSIZE_MASK | USDHC_BLK_ATT_BLKCNT_MASK)) | - (USDHC_BLK_ATT_BLKSIZE(data->blockSize) | USDHC_BLK_ATT_BLKCNT(data->blockCount))); - } - else - { - mixCtrl |= USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK; - base->PROT_CTRL |= USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK; - } - - /* data present flag */ - *dataPresentFlag |= kUSDHC_DataPresentFlag; - } - else - { - /* clear data flags */ - mixCtrl &= ~(USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | - USDHC_MIX_CTRL_AC12EN_MASK); - - if (base->PRES_STATE & kUSDHC_CommandInhibitFlag) - { - return kStatus_USDHC_BusyTransferring; - } - } - - /* config the mix parameter */ - base->MIX_CTRL = mixCtrl; - - return kStatus_Success; -} - -static status_t USDHC_ReceiveCommandResponse(USDHC_Type *base, usdhc_command_t *command) -{ - uint32_t i; - - if (command->responseType != kCARD_ResponseTypeNone) - { - command->response[0U] = base->CMD_RSP0; - if (command->responseType == kCARD_ResponseTypeR2) - { - command->response[1U] = base->CMD_RSP1; - command->response[2U] = base->CMD_RSP2; - command->response[3U] = base->CMD_RSP3; - - i = 4U; - /* R3-R2-R1-R0(lowest 8 bit is invalid bit) has the same format as R2 format in SD specification document - after removed internal CRC7 and end bit. */ - do - { - command->response[i - 1U] <<= 8U; - if (i > 1U) - { - command->response[i - 1U] |= ((command->response[i - 2U] & 0xFF000000U) >> 24U); - } - } while (i--); - } - } - /* check response error flag */ - if ((command->responseErrorFlags != 0U) && - ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) || - (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5))) - { - if (((command->responseErrorFlags) & (command->response[0U])) != 0U) - { - return kStatus_USDHC_SendCommandFailed; - } - } - - return kStatus_Success; -} - -static uint32_t USDHC_ReadDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords) -{ - uint32_t i; - uint32_t totalWords; - uint32_t wordsCanBeRead; /* The words can be read at this time. */ - uint32_t readWatermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_RD_WML_MASK) >> USDHC_WTMK_LVL_RD_WML_SHIFT); - - /* If DMA is enable, do not need to polling data port */ - if ((base->MIX_CTRL & USDHC_MIX_CTRL_DMAEN_MASK) == 0U) - { - /* - * Add non aligned access support ,user need make sure your buffer size is big - * enough to hold the data,in other words,user need make sure the buffer size - * is 4 byte aligned - */ - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ - if (readWatermark >= totalWords) - { - wordsCanBeRead = totalWords; - } - /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark, - transfers watermark level words. */ - else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark)) - { - wordsCanBeRead = readWatermark; - } - /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers - left - words. */ - else - { - wordsCanBeRead = (totalWords - transferredWords); - } - - i = 0U; - while (i < wordsCanBeRead) - { - data->rxData[transferredWords++] = USDHC_ReadData(base); - i++; - } - } - - return transferredWords; -} - -static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data) -{ - uint32_t totalWords; - uint32_t transferredWords = 0U, interruptStatus = 0U; - status_t error = kStatus_Success; - - /* - * Add non aligned access support ,user need make sure your buffer size is big - * enough to hold the data,in other words,user need make sure the buffer size - * is 4 byte aligned - */ - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - while ((error == kStatus_Success) && (transferredWords < totalWords)) - { - while (!(interruptStatus & (kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) - { - interruptStatus = USDHC_GetInterruptStatusFlags(base); - } - - /* during std tuning process, software do not need to read data, but wait BRR is enough */ - if ((data->dataType == kUSDHC_TransferDataTuning) && (interruptStatus & kUSDHC_BufferReadReadyFlag)) - { - USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag | kUSDHC_TuningPassFlag); - - return kStatus_Success; - } - else if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) - { - USDHC_ClearInterruptStatusFlags(base, kUSDHC_TuningErrorFlag); - /* if tuning error occur ,return directly */ - error = kStatus_USDHC_TuningError; - } - else if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - /* clear data error flag */ - USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataErrorFlag); - } - else - { - } - - if (error == kStatus_Success) - { - transferredWords = USDHC_ReadDataPort(base, data, transferredWords); - /* clear buffer read ready */ - USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag); - interruptStatus = 0U; - } - } - - /* Clear data complete flag after the last read operation. */ - USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataCompleteFlag); - - return error; -} - -static uint32_t USDHC_WriteDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords) -{ - uint32_t i; - uint32_t totalWords; - uint32_t wordsCanBeWrote; /* Words can be wrote at this time. */ - uint32_t writeWatermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_WR_WML_MASK) >> USDHC_WTMK_LVL_WR_WML_SHIFT); - - /* If DMA is enable, do not need to polling data port */ - if ((base->MIX_CTRL & USDHC_MIX_CTRL_DMAEN_MASK) == 0U) - { - /* - * Add non aligned access support ,user need make sure your buffer size is big - * enough to hold the data,in other words,user need make sure the buffer size - * is 4 byte aligned - */ - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); - - /* If watermark level is equal or bigger than totalWords, transfers totalWords data.*/ - if (writeWatermark >= totalWords) - { - wordsCanBeWrote = totalWords; - } - /* If watermark level is less than totalWords and left words to be sent is equal or bigger than watermark, - transfers watermark level words. */ - else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark)) - { - wordsCanBeWrote = writeWatermark; - } - /* If watermark level is less than totalWords and left words to be sent is less than watermark, transfers left - words. */ - else - { - wordsCanBeWrote = (totalWords - transferredWords); - } - - i = 0U; - while (i < wordsCanBeWrote) - { - USDHC_WriteData(base, data->txData[transferredWords++]); - i++; - } - } - - return transferredWords; -} - -static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data) -{ - uint32_t totalWords; - - uint32_t transferredWords = 0U, interruptStatus = 0U; - status_t error = kStatus_Success; - - /* - * Add non aligned access support ,user need make sure your buffer size is big - * enough to hold the data,in other words,user need make sure the buffer size - * is 4 byte aligned - */ - if (data->blockSize % sizeof(uint32_t) != 0U) - { - data->blockSize += - sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ - } - - totalWords = (data->blockCount * data->blockSize) / sizeof(uint32_t); - - while ((error == kStatus_Success) && (transferredWords < totalWords)) - { - while (!(interruptStatus & (kUSDHC_BufferWriteReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) - { - interruptStatus = USDHC_GetInterruptStatusFlags(base); - } - - if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) - { - USDHC_ClearInterruptStatusFlags(base, kUSDHC_TuningErrorFlag); - /* if tuning error occur ,return directly */ - return kStatus_USDHC_TuningError; - } - else if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - /* clear data error flag */ - USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataErrorFlag); - } - else - { - } - - if (error == kStatus_Success) - { - transferredWords = USDHC_WriteDataPort(base, data, transferredWords); - /* clear buffer write ready */ - USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferWriteReadyFlag); - interruptStatus = 0U; - } - } - - /* Wait write data complete or data transfer error after the last writing operation. */ - while (!(interruptStatus & (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag))) - { - interruptStatus = USDHC_GetInterruptStatusFlags(base); - } - - if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) - { - if (!(data->enableIgnoreError)) - { - error = kStatus_Fail; - } - } - USDHC_ClearInterruptStatusFlags(base, (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag)); - - return error; -} - -void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command) -{ - assert(NULL != command); - - uint32_t xferType = base->CMD_XFR_TYP, flags = command->flags; - - if (((base->PRES_STATE & kUSDHC_CommandInhibitFlag) == 0U) && (command->type != kCARD_CommandTypeEmpty)) - { - /* Define the flag corresponding to each response type. */ - switch (command->responseType) - { - case kCARD_ResponseTypeNone: - break; - case kCARD_ResponseTypeR1: /* Response 1 */ - case kCARD_ResponseTypeR5: /* Response 5 */ - case kCARD_ResponseTypeR6: /* Response 6 */ - case kCARD_ResponseTypeR7: /* Response 7 */ - flags |= (kUSDHC_ResponseLength48Flag | kUSDHC_EnableCrcCheckFlag | kUSDHC_EnableIndexCheckFlag); - break; - - case kCARD_ResponseTypeR1b: /* Response 1 with busy */ - case kCARD_ResponseTypeR5b: /* Response 5 with busy */ - flags |= (kUSDHC_ResponseLength48BusyFlag | kUSDHC_EnableCrcCheckFlag | kUSDHC_EnableIndexCheckFlag); - break; - - case kCARD_ResponseTypeR2: /* Response 2 */ - flags |= (kUSDHC_ResponseLength136Flag | kUSDHC_EnableCrcCheckFlag); - break; - - case kCARD_ResponseTypeR3: /* Response 3 */ - case kCARD_ResponseTypeR4: /* Response 4 */ - flags |= (kUSDHC_ResponseLength48Flag); - break; - - default: - break; - } - - if (command->type == kCARD_CommandTypeAbort) - { - flags |= kUSDHC_CommandTypeAbortFlag; - } - - /* config cmd index */ - xferType &= ~(USDHC_CMD_XFR_TYP_CMDINX_MASK | USDHC_CMD_XFR_TYP_CMDTYP_MASK | USDHC_CMD_XFR_TYP_CICEN_MASK | - USDHC_CMD_XFR_TYP_CCCEN_MASK | USDHC_CMD_XFR_TYP_RSPTYP_MASK | USDHC_CMD_XFR_TYP_DPSEL_MASK); - - xferType |= - (((command->index << USDHC_CMD_XFR_TYP_CMDINX_SHIFT) & USDHC_CMD_XFR_TYP_CMDINX_MASK) | - ((flags) & (USDHC_CMD_XFR_TYP_CMDTYP_MASK | USDHC_CMD_XFR_TYP_CICEN_MASK | USDHC_CMD_XFR_TYP_CCCEN_MASK | - USDHC_CMD_XFR_TYP_RSPTYP_MASK | USDHC_CMD_XFR_TYP_DPSEL_MASK))); - - /* config the command xfertype and argument */ - base->CMD_ARG = command->argument; - base->CMD_XFR_TYP = xferType; - } - - if (command->type == kCARD_CommandTypeEmpty) - { - /* disable CMD done interrupt for empty command */ - base->INT_SIGNAL_EN &= ~USDHC_INT_SIGNAL_EN_CCIEN_MASK; - } -} - -static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command, bool pollingCmdDone) -{ - assert(NULL != command); - - status_t error = kStatus_Success; - uint32_t interruptStatus = 0U; - /* check if need polling command done or not */ - if (pollingCmdDone) - { - /* Wait command complete or USDHC encounters error. */ - while (!(interruptStatus & (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag))) - { - interruptStatus = USDHC_GetInterruptStatusFlags(base); - } - - if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) - { - error = kStatus_USDHC_TuningError; - } - else if ((interruptStatus & kUSDHC_CommandErrorFlag) != 0U) - { - error = kStatus_Fail; - } - else - { - } - /* Receive response when command completes successfully. */ - if (error == kStatus_Success) - { - error = USDHC_ReceiveCommandResponse(base, command); - } - - USDHC_ClearInterruptStatusFlags( - base, (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag | kUSDHC_TuningErrorFlag)); - } - - return error; -} - -static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, bool enDMA) -{ - status_t error = kStatus_Success; - uint32_t interruptStatus = 0U; - - if (enDMA) - { - /* Wait data complete or USDHC encounters error. */ - while (!((interruptStatus & - (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | kUSDHC_TuningErrorFlag)))) - { - interruptStatus = USDHC_GetInterruptStatusFlags(base); - } - - if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) - { - error = kStatus_USDHC_TuningError; - } - else if (((interruptStatus & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)) != 0U)) - { - if ((!(data->enableIgnoreError)) || (interruptStatus & kUSDHC_DataTimeoutFlag)) - { - error = kStatus_Fail; - } - } - else - { - } - /* load dummy data */ - if ((data->dataType == kUSDHC_TransferDataBootcontinous) && (error == kStatus_Success)) - { - *(data->rxData) = s_usdhcBootDummy; - } - - USDHC_ClearInterruptStatusFlags(base, (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | - kUSDHC_TuningPassFlag | kUSDHC_TuningErrorFlag)); - } - else - { - if (data->rxData) - { - error = USDHC_ReadByDataPortBlocking(base, data); - } - else - { - error = USDHC_WriteByDataPortBlocking(base, data); - } - } - - return error; -} - -void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config) -{ - assert(config); - assert((config->writeWatermarkLevel >= 1U) && (config->writeWatermarkLevel <= 128U)); - assert((config->readWatermarkLevel >= 1U) && (config->readWatermarkLevel <= 128U)); - assert(config->writeBurstLen <= 16U); - - uint32_t proctl, sysctl, wml; - - /* Enable USDHC clock. */ - CLOCK_EnableClock(s_usdhcClock[USDHC_GetInstance(base)]); - - /* Reset USDHC. */ - USDHC_Reset(base, kUSDHC_ResetAll, 100U); - - proctl = base->PROT_CTRL; - wml = base->WTMK_LVL; - sysctl = base->SYS_CTRL; - - proctl &= ~(USDHC_PROT_CTRL_EMODE_MASK | USDHC_PROT_CTRL_DMASEL_MASK); - /* Endian mode*/ - proctl |= USDHC_PROT_CTRL_EMODE(config->endianMode); - - /* Watermark level */ - wml &= ~(USDHC_WTMK_LVL_RD_WML_MASK | USDHC_WTMK_LVL_WR_WML_MASK | USDHC_WTMK_LVL_RD_BRST_LEN_MASK | - USDHC_WTMK_LVL_WR_BRST_LEN_MASK); - wml |= (USDHC_WTMK_LVL_RD_WML(config->readWatermarkLevel) | USDHC_WTMK_LVL_WR_WML(config->writeWatermarkLevel) | - USDHC_WTMK_LVL_RD_BRST_LEN(config->readBurstLen) | USDHC_WTMK_LVL_WR_BRST_LEN(config->writeBurstLen)); - - /* config the data timeout value */ - sysctl &= ~USDHC_SYS_CTRL_DTOCV_MASK; - sysctl |= USDHC_SYS_CTRL_DTOCV(config->dataTimeout); - - base->SYS_CTRL = sysctl; - base->WTMK_LVL = wml; - base->PROT_CTRL = proctl; - -#if FSL_FEATURE_USDHC_HAS_EXT_DMA - /* disable external DMA */ - base->VEND_SPEC &= ~USDHC_VEND_SPEC_EXT_DMA_EN_MASK; -#endif - /* disable internal DMA and DDR mode */ - base->MIX_CTRL &= ~(USDHC_MIX_CTRL_DMAEN_MASK | USDHC_MIX_CTRL_DDR_EN_MASK); - /* Enable interrupt status but doesn't enable interrupt signal. */ - USDHC_SetTransferInterrupt(base, false); -} - -void USDHC_Deinit(USDHC_Type *base) -{ - /* Disable clock. */ - CLOCK_DisableClock(s_usdhcClock[USDHC_GetInstance(base)]); -} - -bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout) -{ - base->SYS_CTRL |= (mask & (USDHC_SYS_CTRL_RSTA_MASK | USDHC_SYS_CTRL_RSTC_MASK | USDHC_SYS_CTRL_RSTD_MASK)); - /* Delay some time to wait reset success. */ - while ((base->SYS_CTRL & mask) != 0U) - { - if (timeout == 0U) - { - break; - } - timeout--; - } - - return ((!timeout) ? false : true); -} - -void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability) -{ - assert(capability); - - uint32_t htCapability; - uint32_t maxBlockLength; - - htCapability = base->HOST_CTRL_CAP; - - /* Get the capability of USDHC. */ - maxBlockLength = ((htCapability & USDHC_HOST_CTRL_CAP_MBL_MASK) >> USDHC_HOST_CTRL_CAP_MBL_SHIFT); - capability->maxBlockLength = (512U << maxBlockLength); - /* Other attributes not in HTCAPBLT register. */ - capability->maxBlockCount = USDHC_MAX_BLOCK_COUNT; - capability->flags = (htCapability & (kUSDHC_SupportAdmaFlag | kUSDHC_SupportHighSpeedFlag | kUSDHC_SupportDmaFlag | - kUSDHC_SupportSuspendResumeFlag | kUSDHC_SupportV330Flag)); - capability->flags |= (htCapability & kUSDHC_SupportV300Flag); - capability->flags |= (htCapability & kUSDHC_SupportV180Flag); - capability->flags |= - (htCapability & (kUSDHC_SupportDDR50Flag | kUSDHC_SupportSDR104Flag | kUSDHC_SupportSDR50Flag)); - /* USDHC support 4/8 bit data bus width. */ - capability->flags |= (kUSDHC_Support4BitFlag | kUSDHC_Support8BitFlag); -} - -uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz) -{ - assert(srcClock_Hz != 0U); - assert((busClock_Hz != 0U) && (busClock_Hz <= srcClock_Hz)); - - uint32_t totalDiv = 0U; - uint32_t divisor = 0U; - uint32_t prescaler = 0U; - uint32_t sysctl = 0U; - uint32_t nearestFrequency = 0U; - - /* calucate total divisor first */ - if ((totalDiv = srcClock_Hz / busClock_Hz) > (USDHC_MAX_CLKFS * USDHC_MAX_DVS)) - { - return 0U; - } - - if (totalDiv != 0U) - { - /* calucate the divisor (srcClock_Hz / divisor) <= busClock_Hz */ - if ((srcClock_Hz / totalDiv) > busClock_Hz) - { - totalDiv++; - } - - /* divide the total divisor to div and prescaler */ - if (totalDiv > USDHC_MAX_DVS) - { - prescaler = totalDiv / USDHC_MAX_DVS; - /* prescaler must be a value which equal 2^n and smaller than SDHC_MAX_CLKFS */ - while (((USDHC_MAX_CLKFS % prescaler) != 0U) || (prescaler == 1U)) - { - prescaler++; - } - /* calucate the divisor */ - divisor = totalDiv / prescaler; - /* fine tuning the divisor until divisor * prescaler >= totalDiv */ - while ((divisor * prescaler) < totalDiv) - { - divisor++; - } - - nearestFrequency = srcClock_Hz / (divisor == 0U ? 1U : divisor) / prescaler; - } - else - { - /* in this situation , divsior and SDCLKFS can generate same clock - use SDCLKFS*/ - if ((USDHC_MAX_DVS % totalDiv) == 0U) - { - divisor = 0U; - prescaler = totalDiv; - } - else - { - divisor = (totalDiv / 2U) + 1U; /* make sure the output frequency not bigger than target value */ - prescaler = 2U; - } - nearestFrequency = srcClock_Hz / totalDiv; - } - } - /* in this condition , srcClock_Hz = busClock_Hz, */ - else - { - /* in DDR mode , set SDCLKFS to 0, divisor = 0, actually the - totoal divider = 2U */ - divisor = 0U; - prescaler = 0U; - nearestFrequency = srcClock_Hz; - } - - /* calucate the value write to register */ - if (divisor != 0U) - { - USDHC_PREV_DVS(divisor); - } - /* calucate the value write to register */ - if (prescaler != 0U) - { - USDHC_PREV_CLKFS(prescaler, 1U); - } - - /* Set the SD clock frequency divisor, SD clock frequency select, data timeout counter value. */ - sysctl = base->SYS_CTRL; - sysctl &= ~(USDHC_SYS_CTRL_DVS_MASK | USDHC_SYS_CTRL_SDCLKFS_MASK); - sysctl |= (USDHC_SYS_CTRL_DVS(divisor) | USDHC_SYS_CTRL_SDCLKFS(prescaler)); - base->SYS_CTRL = sysctl; - - /* Wait until the SD clock is stable. */ - while (!(base->PRES_STATE & USDHC_PRES_STATE_SDSTB_MASK)) - { - } - - return nearestFrequency; -} - -bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout) -{ - base->SYS_CTRL |= USDHC_SYS_CTRL_INITA_MASK; - /* Delay some time to wait card become active state. */ - while ((base->SYS_CTRL & USDHC_SYS_CTRL_INITA_MASK) == USDHC_SYS_CTRL_INITA_MASK) - { - if (!timeout) - { - break; - } - timeout--; - } - - return ((!timeout) ? false : true); -} - -void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos) -{ - uint32_t prescaler = (base->SYS_CTRL & USDHC_SYS_CTRL_SDCLKFS_MASK) >> USDHC_SYS_CTRL_SDCLKFS_SHIFT; - - if (enable) - { - base->MIX_CTRL &= ~USDHC_MIX_CTRL_NIBBLE_POS_MASK; - base->MIX_CTRL |= (USDHC_MIX_CTRL_DDR_EN_MASK | USDHC_MIX_CTRL_NIBBLE_POS(nibblePos)); - prescaler >>= 1U; - } - else - { - base->MIX_CTRL &= ~USDHC_MIX_CTRL_DDR_EN_MASK; - - if (prescaler == 0U) - { - prescaler += 1U; - } - else - { - prescaler <<= 1U; - } - } - - base->SYS_CTRL = (base->SYS_CTRL & (~USDHC_SYS_CTRL_SDCLKFS_MASK)) | USDHC_SYS_CTRL_SDCLKFS(prescaler); -} - -void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config) -{ - assert(config); - assert(config->ackTimeoutCount <= (USDHC_MMC_BOOT_DTOCV_ACK_MASK >> USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)); - assert(config->blockCount <= (USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK >> USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)); - - uint32_t mmcboot = base->MMC_BOOT; - - mmcboot &= ~(USDHC_MMC_BOOT_DTOCV_ACK_MASK | USDHC_MMC_BOOT_BOOT_MODE_MASK | USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK); - mmcboot |= USDHC_MMC_BOOT_DTOCV_ACK(config->ackTimeoutCount) | USDHC_MMC_BOOT_BOOT_MODE(config->bootMode); - - if (config->enableBootAck) - { - mmcboot |= USDHC_MMC_BOOT_BOOT_ACK_MASK; - } - if (config->enableAutoStopAtBlockGap) - { - mmcboot |= - USDHC_MMC_BOOT_AUTO_SABG_EN_MASK | USDHC_MMC_BOOT_BOOT_BLK_CNT(USDHC_MAX_BLOCK_COUNT - config->blockCount); - /* always set the block count to USDHC_MAX_BLOCK_COUNT to use auto stop at block gap feature */ - base->BLK_ATT = ((base->BLK_ATT & ~(USDHC_BLK_ATT_BLKSIZE_MASK | USDHC_BLK_ATT_BLKCNT_MASK)) | - (USDHC_BLK_ATT_BLKSIZE(config->blockSize) | USDHC_BLK_ATT_BLKCNT(USDHC_MAX_BLOCK_COUNT))); - } - else - { - base->BLK_ATT = ((base->BLK_ATT & ~(USDHC_BLK_ATT_BLKSIZE_MASK | USDHC_BLK_ATT_BLKCNT_MASK)) | - (USDHC_BLK_ATT_BLKSIZE(config->blockSize) | USDHC_BLK_ATT_BLKCNT(config->blockCount))); - } - - base->MMC_BOOT = mmcboot; -} - -status_t USDHC_SetADMA1Descriptor( - uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags) -{ - assert(NULL != admaTable); - assert(NULL != dataBufferAddr); - - uint32_t miniEntries, startEntries = 0U, - maxEntries = (admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma1_descriptor_t); - usdhc_adma1_descriptor_t *adma1EntryAddress = (usdhc_adma1_descriptor_t *)(admaTable); - uint32_t i, dmaBufferLen = 0U; - const uint32_t *data = dataBufferAddr; - - if (((uint32_t)data % USDHC_ADMA1_ADDRESS_ALIGN) != 0U) - { - return kStatus_USDHC_DMADataAddrNotAlign; - } - - if (flags == kUSDHC_AdmaDescriptorMultipleFlag) - { - return kStatus_USDHC_NotSupport; - } - /* - * Add non aligned access support ,user need make sure your buffer size is big - * enough to hold the data,in other words,user need make sure the buffer size - * is 4 byte aligned - */ - if (dataBytes % sizeof(uint32_t) != 0U) - { - /* make the data length as word-aligned */ - dataBytes += sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); - } - - /* Check if ADMA descriptor's number is enough. */ - if ((dataBytes % USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) - { - miniEntries = dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; - } - else - { - miniEntries = ((dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); - } - - /* ADMA1 needs two descriptors to finish a transfer */ - miniEntries <<= 1U; - - if (miniEntries + startEntries > maxEntries) - { - return kStatus_OutOfRange; - } - - for (i = startEntries; i < (miniEntries + startEntries); i += 2U) - { - if (dataBytes > USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) - { - dmaBufferLen = USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; - } - else - { - dmaBufferLen = dataBytes; - } - - adma1EntryAddress[i] = (dmaBufferLen << USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT); - adma1EntryAddress[i] |= kUSDHC_Adma1DescriptorTypeSetLength; - adma1EntryAddress[i + 1U] = (uint32_t)(data); - adma1EntryAddress[i + 1U] |= kUSDHC_Adma1DescriptorTypeTransfer; - data += dmaBufferLen / sizeof(uint32_t); - dataBytes -= dmaBufferLen; - } - /* the end of the descriptor */ - adma1EntryAddress[i - 1U] |= kUSDHC_Adma1DescriptorEndFlag; - - return kStatus_Success; -} - -status_t USDHC_SetADMA2Descriptor( - uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags) -{ - assert(NULL != admaTable); - assert(NULL != dataBufferAddr); - - uint32_t miniEntries, startEntries = 0U, - maxEntries = (admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma2_descriptor_t); - usdhc_adma2_descriptor_t *adma2EntryAddress = (usdhc_adma2_descriptor_t *)(admaTable); - uint32_t i, dmaBufferLen = 0U; - const uint32_t *data = dataBufferAddr; - - if (((uint32_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0U) - { - return kStatus_USDHC_DMADataAddrNotAlign; - } - /* - * Add non aligned access support ,user need make sure your buffer size is big - * enough to hold the data,in other words,user need make sure the buffer size - * is 4 byte aligned - */ - if (dataBytes % sizeof(uint32_t) != 0U) - { - /* make the data length as word-aligned */ - dataBytes += sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); - } - - /* Check if ADMA descriptor's number is enough. */ - if ((dataBytes % USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) - { - miniEntries = dataBytes / USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; - } - else - { - miniEntries = ((dataBytes / USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); - } - /* calucate the start entry for multiple descriptor mode, ADMA engine is not stop, so update the descriptor - data adress and data size is enough */ - if (flags == kUSDHC_AdmaDescriptorMultipleFlag) - { - for (i = 0U; i < maxEntries; i++) - { - if ((adma2EntryAddress[i].attribute & kUSDHC_Adma2DescriptorValidFlag) == 0U) - { - break; - } - } - startEntries = i; - /* add one entry for dummy entry */ - miniEntries += 1U; - } - - if ((miniEntries + startEntries) > maxEntries) - { - return kStatus_OutOfRange; - } - - for (i = startEntries; i < (miniEntries + startEntries); i++) - { - if (dataBytes > USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) - { - dmaBufferLen = USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; - } - else - { - dmaBufferLen = (dataBytes == 0U ? sizeof(uint32_t) : - dataBytes); /* adma don't support 0 data length transfer descriptor */ - } - - /* Each descriptor for ADMA2 is 64-bit in length */ - adma2EntryAddress[i].address = (dataBytes == 0U) ? &s_usdhcBootDummy : data; - adma2EntryAddress[i].attribute = (dmaBufferLen << USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT); - adma2EntryAddress[i].attribute |= - (dataBytes == 0U) ? 0U : (kUSDHC_Adma2DescriptorTypeTransfer | kUSDHC_Adma2DescriptorInterruptFlag); - data += (dmaBufferLen / sizeof(uint32_t)); - - if (dataBytes != 0U) - { - dataBytes -= dmaBufferLen; - } - } - - /* add a dummy valid ADMA descriptor for multiple descriptor mode, this is useful when transfer boot data, the ADMA - engine - will not stop at block gap */ - if (flags == kUSDHC_AdmaDescriptorMultipleFlag) - { - adma2EntryAddress[startEntries + 1U].attribute |= kUSDHC_Adma2DescriptorTypeTransfer; - } - else - { - /* set the end bit */ - adma2EntryAddress[i - 1U].attribute |= kUSDHC_Adma2DescriptorEndFlag; - } - - return kStatus_Success; -} - -status_t USDHC_SetInternalDmaConfig(USDHC_Type *base, - usdhc_adma_config_t *dmaConfig, - const uint32_t *dataAddr, - bool enAutoCmd23) -{ - assert(dmaConfig); - assert(dataAddr); - -#if FSL_FEATURE_USDHC_HAS_EXT_DMA - /* disable the external DMA if support */ - base->VEND_SPEC &= ~USDHC_VEND_SPEC_EXT_DMA_EN_MASK; -#endif - - if (dmaConfig->dmaMode == kUSDHC_DmaModeSimple) - { - /* check DMA data buffer address align or not */ - if (((uint32_t)dataAddr % USDHC_ADMA2_ADDRESS_ALIGN) != 0U) - { - return kStatus_USDHC_DMADataAddrNotAlign; - } - /* in simple DMA mode if use auto CMD23, address should load to ADMA addr, - and block count should load to DS_ADDR*/ - if (enAutoCmd23) - { - base->ADMA_SYS_ADDR = (uint32_t)dataAddr; - } - else - { - base->DS_ADDR = (uint32_t)dataAddr; - } - } - else - { - /* When use ADMA, disable simple DMA */ - base->DS_ADDR = 0U; - base->ADMA_SYS_ADDR = (uint32_t)(dmaConfig->admaTable); - } - - /* select DMA mode and config the burst length */ - base->PROT_CTRL &= ~(USDHC_PROT_CTRL_DMASEL_MASK | USDHC_PROT_CTRL_BURST_LEN_EN_MASK); - base->PROT_CTRL |= USDHC_PROT_CTRL_DMASEL(dmaConfig->dmaMode) | USDHC_PROT_CTRL_BURST_LEN_EN(dmaConfig->burstLen); - /* enable DMA */ - base->MIX_CTRL |= USDHC_MIX_CTRL_DMAEN_MASK; - - return kStatus_Success; -} - -status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, - usdhc_adma_config_t *dmaConfig, - usdhc_data_t *dataConfig, - uint32_t flags) -{ - assert(NULL != dmaConfig); - assert(NULL != dmaConfig->admaTable); - assert(NULL != dataConfig); - - status_t error = kStatus_Fail; - uint32_t bootDummyOffset = dataConfig->dataType == kUSDHC_TransferDataBootcontinous ? sizeof(uint32_t) : 0U; - const uint32_t *data = - (const uint32_t *)((uint32_t)((dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData) + - bootDummyOffset); - uint32_t blockSize = dataConfig->blockSize * dataConfig->blockCount - bootDummyOffset; - - switch (dmaConfig->dmaMode) - { -#if FSL_FEATURE_USDHC_HAS_EXT_DMA - case kUSDHC_ExternalDMA: - /* enable the external DMA */ - base->VEND_SPEC |= USDHC_VEND_SPEC_EXT_DMA_EN_MASK; - break; -#endif - case kUSDHC_DmaModeSimple: - error = kStatus_Success; - break; - - case kUSDHC_DmaModeAdma1: - error = USDHC_SetADMA1Descriptor(dmaConfig->admaTable, dmaConfig->admaTableWords, data, blockSize, flags); - break; - - case kUSDHC_DmaModeAdma2: - error = USDHC_SetADMA2Descriptor(dmaConfig->admaTable, dmaConfig->admaTableWords, data, blockSize, flags); - break; - default: - return kStatus_USDHC_PrepareAdmaDescriptorFailed; - } - - /* for internal dma, internal DMA configurations should not update the configurations when continous transfer the - * boot data, only the DMA descriptor need update */ - if ((dmaConfig->dmaMode != kUSDHC_ExternalDMA) && (error == kStatus_Success) && - (dataConfig->dataType != kUSDHC_TransferDataBootcontinous)) - { - error = USDHC_SetInternalDmaConfig(base, dmaConfig, data, dataConfig->enableAutoCommand23); - } - - return error; -} - -status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer) -{ - assert(transfer); - - status_t error = kStatus_Fail; - usdhc_command_t *command = transfer->command; - usdhc_data_t *data = transfer->data; - bool enDMA = true; - bool executeTuning = ((data == NULL) ? false : data->dataType == kUSDHC_TransferDataTuning); - - /*check re-tuning request*/ - if ((USDHC_GetInterruptStatusFlags(base) & kUSDHC_ReTuningEventFlag) != 0U) - { - USDHC_ClearInterruptStatusFlags(base, kUSDHC_ReTuningEventFlag); - return kStatus_USDHC_ReTuningRequest; - } - - /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ - if ((data != NULL) && (dmaConfig != NULL) && (!executeTuning)) - { - error = USDHC_SetAdmaTableConfig(base, dmaConfig, data, (data->dataType & kUSDHC_TransferDataBoot) ? - kUSDHC_AdmaDescriptorMultipleFlag : - kUSDHC_AdmaDescriptorSingleFlag); - } - - /* if the DMA desciptor configure fail or not needed , disable it */ - if (error != kStatus_Success) - { - enDMA = false; - /* disable DMA, using polling mode in this situation */ - USDHC_EnableInternalDMA(base, false); - } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - else - { - if (data->txData != NULL) - { - /* clear the DCACHE */ - DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); - } - else - { - /* clear the DCACHE */ - DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); - } - } -#endif - - /* config the data transfer parameter */ - error = USDHC_SetDataTransferConfig(base, data, &(command->flags)); - if (kStatus_Success != error) - { - return error; - } - /* send command first */ - USDHC_SendCommand(base, command); - /* wait command done */ - error = USDHC_WaitCommandDone(base, command, (data == NULL) || (data->dataType == kUSDHC_TransferDataNormal)); - - /* wait transfer data finsih */ - if ((data != NULL) && (error == kStatus_Success)) - { - return USDHC_TransferDataBlocking(base, data, enDMA); - } - - return error; -} - -status_t USDHC_TransferNonBlocking(USDHC_Type *base, - usdhc_handle_t *handle, - usdhc_adma_config_t *dmaConfig, - usdhc_transfer_t *transfer) -{ - assert(handle); - assert(transfer); - - status_t error = kStatus_Fail; - usdhc_command_t *command = transfer->command; - usdhc_data_t *data = transfer->data; - bool executeTuning = ((data == NULL) ? false : data->dataType == kUSDHC_TransferDataTuning); - - /*check re-tuning request*/ - if ((USDHC_GetInterruptStatusFlags(base) & (kUSDHC_ReTuningEventFlag)) != 0U) - { - USDHC_ClearInterruptStatusFlags(base, kUSDHC_ReTuningEventFlag); - return kStatus_USDHC_ReTuningRequest; - } - - /* Save command and data into handle before transferring. */ - handle->command = command; - handle->data = data; - handle->interruptFlags = 0U; - /* transferredWords will only be updated in ISR when transfer way is DATAPORT. */ - handle->transferredWords = 0U; - - /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ - if ((data != NULL) && (dmaConfig != NULL) && (!executeTuning)) - { - error = USDHC_SetAdmaTableConfig(base, dmaConfig, data, (data->dataType & kUSDHC_TransferDataBoot) ? - kUSDHC_AdmaDescriptorMultipleFlag : - kUSDHC_AdmaDescriptorSingleFlag); - } - - /* if the DMA desciptor configure fail or not needed , disable it */ - if (error != kStatus_Success) - { - /* disable DMA, using polling mode in this situation */ - USDHC_EnableInternalDMA(base, false); - } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - else - { - if (data->txData != NULL) - { - /* clear the DCACHE */ - DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); - } - else - { - /* clear the DCACHE */ - DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); - } - } -#endif - - error = USDHC_SetDataTransferConfig(base, data, &(command->flags)); - if (kStatus_Success != error) - { - return error; - } - - /* send command first */ - USDHC_SendCommand(base, command); - - return kStatus_Success; -} - -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (FSL_FEATURE_USDHC_HAS_SDR50_MODE) -void USDHC_EnableManualTuning(USDHC_Type *base, bool enable) -{ - if (enable) - { - /* make sure std_tun_en bit is clear */ - base->TUNING_CTRL &= ~USDHC_TUNING_CTRL_STD_TUNING_EN_MASK; - /* disable auto tuning here */ - base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; - /* execute tuning for SDR104 mode */ - base->MIX_CTRL |= - USDHC_MIX_CTRL_EXE_TUNE_MASK | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK | USDHC_MIX_CTRL_FBCLK_SEL_MASK; - } - else - { /* abort the tuning */ - base->MIX_CTRL &= ~(USDHC_MIX_CTRL_EXE_TUNE_MASK | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK); - } -} - -status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay) -{ - uint32_t clkTuneCtrl = 0U; - - clkTuneCtrl = base->CLK_TUNE_CTRL_STATUS; - - clkTuneCtrl &= ~USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK; - - clkTuneCtrl |= USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(delay); - - /* load the delay setting */ - base->CLK_TUNE_CTRL_STATUS = clkTuneCtrl; - /* check delat setting error */ - if (base->CLK_TUNE_CTRL_STATUS & - (USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)) - { - return kStatus_Fail; - } - - return kStatus_Success; -} - -void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable) -{ - uint32_t tuningCtrl = 0U; - - if (enable) - { - /* feedback clock */ - base->MIX_CTRL |= USDHC_MIX_CTRL_FBCLK_SEL_MASK; - /* config tuning start and step */ - tuningCtrl = base->TUNING_CTRL; - tuningCtrl &= ~(USDHC_TUNING_CTRL_TUNING_START_TAP_MASK | USDHC_TUNING_CTRL_TUNING_STEP_MASK); - tuningCtrl |= (USDHC_TUNING_CTRL_TUNING_START_TAP(tuningStartTap) | USDHC_TUNING_CTRL_TUNING_STEP(step) | - USDHC_TUNING_CTRL_STD_TUNING_EN_MASK); - base->TUNING_CTRL = tuningCtrl; - - /* excute tuning */ - base->AUTOCMD12_ERR_STATUS |= - (USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); - } - else - { - /* disable the standard tuning */ - base->TUNING_CTRL &= ~USDHC_TUNING_CTRL_STD_TUNING_EN_MASK; - /* clear excute tuning */ - base->AUTOCMD12_ERR_STATUS &= - ~(USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); - } -} - -void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base) -{ - uint32_t busWidth = 0U; - - base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK; - busWidth = (base->PROT_CTRL & USDHC_PROT_CTRL_DTW_MASK) >> USDHC_PROT_CTRL_DTW_SHIFT; - if (busWidth == kUSDHC_DataBusWidth1Bit) - { - base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; - base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; - } - else if (busWidth == kUSDHC_DataBusWidth4Bit) - { - base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; - base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; - } - else if (busWidth == kUSDHC_DataBusWidth8Bit) - { - base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; - base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; - } - else - { - } -} -#endif /* FSL_FEATURE_USDHC_HAS_SDR50_MODE */ - -static void USDHC_TransferHandleCardDetect(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) -{ - if (interruptFlags & kUSDHC_CardInsertionFlag) - { - if (handle->callback.CardInserted) - { - handle->callback.CardInserted(base, handle->userData); - } - } - else - { - if (handle->callback.CardRemoved) - { - handle->callback.CardRemoved(base, handle->userData); - } - } -} - -static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->command); - - if ((interruptFlags & kUSDHC_CommandErrorFlag) && (!(handle->data))) - { - if (handle->callback.TransferComplete) - { - handle->callback.TransferComplete(base, handle, kStatus_USDHC_SendCommandFailed, handle->userData); - } - } - else - { - /* Receive response */ - if (kStatus_Success != USDHC_ReceiveCommandResponse(base, handle->command)) - { - if (handle->callback.TransferComplete) - { - handle->callback.TransferComplete(base, handle, kStatus_USDHC_SendCommandFailed, handle->userData); - } - } - else if ((!(handle->data)) && (handle->callback.TransferComplete)) - { - if (handle->callback.TransferComplete) - { - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); - } - } - else - { - } - } -} - -static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->data); - - if ((!(handle->data->enableIgnoreError)) && ((interruptFlags & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)))) - { - if (handle->callback.TransferComplete) - { - handle->callback.TransferComplete(base, handle, kStatus_USDHC_TransferDataFailed, handle->userData); - } - } - else - { - if (interruptFlags & kUSDHC_BufferReadReadyFlag) - { - /* std tuning process only need to wait BRR */ - if (handle->data->dataType == kUSDHC_TransferDataTuning) - { - if (handle->callback.TransferComplete) - { - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); - } - } - else - { - handle->transferredWords = USDHC_ReadDataPort(base, handle->data, handle->transferredWords); - } - } - else if (interruptFlags & kUSDHC_BufferWriteReadyFlag) - { - handle->transferredWords = USDHC_WriteDataPort(base, handle->data, handle->transferredWords); - } - else - { - if ((interruptFlags & kUSDHC_DmaCompleteFlag) && - (handle->data->dataType == kUSDHC_TransferDataBootcontinous)) - { - *(handle->data->rxData) = s_usdhcBootDummy; - } - - if ((handle->callback.TransferComplete) && (interruptFlags & kUSDHC_DataCompleteFlag)) - { - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); - } - } - } -} - -static void USDHC_TransferHandleSdioInterrupt(USDHC_Type *base, usdhc_handle_t *handle) -{ - if (handle->callback.SdioInterrupt) - { - handle->callback.SdioInterrupt(base, handle->userData); - } -} - -static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) -{ - assert(handle->callback.ReTuning); - /* retuning request */ - if ((interruptFlags & kUSDHC_TuningErrorFlag) == kUSDHC_TuningErrorFlag) - { - handle->callback.ReTuning(base, handle->userData); /* retuning fail */ - } -} - -static void USDHC_TransferHandleBlockGap(USDHC_Type *base, usdhc_handle_t *handle) -{ - if (handle->callback.BlockGap) - { - handle->callback.BlockGap(base, handle->userData); - } -} - -void USDHC_TransferCreateHandle(USDHC_Type *base, - usdhc_handle_t *handle, - const usdhc_transfer_callback_t *callback, - void *userData) -{ - assert(handle); - assert(callback); - - /* Zero the handle. */ - memset(handle, 0, sizeof(*handle)); - - /* Set the callback. */ - handle->callback.CardInserted = callback->CardInserted; - handle->callback.CardRemoved = callback->CardRemoved; - handle->callback.SdioInterrupt = callback->SdioInterrupt; - handle->callback.BlockGap = callback->BlockGap; - handle->callback.TransferComplete = callback->TransferComplete; - handle->callback.ReTuning = callback->ReTuning; - handle->userData = userData; - - /* Save the handle in global variables to support the double weak mechanism. */ - s_usdhcHandle[USDHC_GetInstance(base)] = handle; - - /* Enable interrupt in NVIC. */ - USDHC_SetTransferInterrupt(base, true); - /* disable the tuning pass interrupt */ - USDHC_DisableInterruptSignal(base, kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag); - /* save IRQ handler */ - s_usdhcIsr = USDHC_TransferHandleIRQ; - - EnableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]); -} - -void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle) -{ - assert(handle); - - uint32_t interruptFlags; - - interruptFlags = USDHC_GetInterruptStatusFlags(base); - handle->interruptFlags = interruptFlags; - - if (interruptFlags & kUSDHC_CardDetectFlag) - { - USDHC_TransferHandleCardDetect(base, handle, (interruptFlags & kUSDHC_CardDetectFlag)); - } - if (interruptFlags & kUSDHC_CommandFlag) - { - USDHC_TransferHandleCommand(base, handle, (interruptFlags & kUSDHC_CommandFlag)); - } - if (interruptFlags & kUSDHC_DataFlag) - { - USDHC_TransferHandleData(base, handle, (interruptFlags & kUSDHC_DataFlag)); - } - if (interruptFlags & kUSDHC_CardInterruptFlag) - { - USDHC_TransferHandleSdioInterrupt(base, handle); - } - if (interruptFlags & kUSDHC_BlockGapEventFlag) - { - USDHC_TransferHandleBlockGap(base, handle); - } - if (interruptFlags & kUSDHC_SDR104TuningFlag) - { - USDHC_TransferHandleReTuning(base, handle, (interruptFlags & kUSDHC_SDR104TuningFlag)); - } - USDHC_ClearInterruptStatusFlags(base, interruptFlags); -} - -#ifdef USDHC0 -void USDHC0_DriverIRQHandler(void) -{ - s_usdhcIsr(s_usdhcBase[0U], s_usdhcHandle[0U]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#ifdef USDHC1 -void USDHC1_DriverIRQHandler(void) -{ - s_usdhcIsr(s_usdhcBase[1U], s_usdhcHandle[1U]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#ifdef USDHC2 -void USDHC2_DriverIRQHandler(void) -{ - s_usdhcIsr(s_usdhcBase[2U], s_usdhcHandle[2U]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#endif diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_usdhc.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_usdhc.h deleted file mode 100644 index 4139dfd8bd..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_usdhc.h +++ /dev/null @@ -1,1505 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_USDHC_H_ -#define _FSL_USDHC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup usdhc - * @{ - */ - -/****************************************************************************** - * Definitions. - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief Driver version 2.2.3. */ -#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 3U)) -/*@}*/ - -/*! @brief Maximum block count can be set one time */ -#define USDHC_MAX_BLOCK_COUNT (USDHC_BLK_ATT_BLKCNT_MASK >> USDHC_BLK_ATT_BLKCNT_SHIFT) - -/*! @brief USDHC status */ -enum _usdhc_status -{ - kStatus_USDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_USDHC, 0U), /*!< Transfer is on-going */ - kStatus_USDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_USDHC, 1U), /*!< Set DMA descriptor failed */ - kStatus_USDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_USDHC, 2U), /*!< Send command failed */ - kStatus_USDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_USDHC, 3U), /*!< Transfer data failed */ - kStatus_USDHC_DMADataAddrNotAlign = MAKE_STATUS(kStatusGroup_USDHC, 4U), /*!< data address not align */ - kStatus_USDHC_ReTuningRequest = MAKE_STATUS(kStatusGroup_USDHC, 5U), /*!< re-tuning request */ - kStatus_USDHC_TuningError = MAKE_STATUS(kStatusGroup_USDHC, 6U), /*!< tuning error */ - kStatus_USDHC_NotSupport = MAKE_STATUS(kStatusGroup_USDHC, 7U), /*!< not support */ -}; - -/*! @brief Host controller capabilities flag mask */ -enum _usdhc_capability_flag -{ - kUSDHC_SupportAdmaFlag = USDHC_HOST_CTRL_CAP_ADMAS_MASK, /*!< Support ADMA */ - kUSDHC_SupportHighSpeedFlag = USDHC_HOST_CTRL_CAP_HSS_MASK, /*!< Support high-speed */ - kUSDHC_SupportDmaFlag = USDHC_HOST_CTRL_CAP_DMAS_MASK, /*!< Support DMA */ - kUSDHC_SupportSuspendResumeFlag = USDHC_HOST_CTRL_CAP_SRS_MASK, /*!< Support suspend/resume */ - kUSDHC_SupportV330Flag = USDHC_HOST_CTRL_CAP_VS33_MASK, /*!< Support voltage 3.3V */ - kUSDHC_SupportV300Flag = USDHC_HOST_CTRL_CAP_VS30_MASK, /*!< Support voltage 3.0V */ - kUSDHC_SupportV180Flag = USDHC_HOST_CTRL_CAP_VS18_MASK, /*!< Support voltage 1.8V */ - /* Put additional two flags in HTCAPBLT_MBL's position. */ - kUSDHC_Support4BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 0U), /*!< Support 4 bit mode */ - kUSDHC_Support8BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 1U), /*!< Support 8 bit mode */ - /* sd version 3.0 new feature */ - kUSDHC_SupportDDR50Flag = USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK, /*!< support DDR50 mode */ - -#if defined(FSL_FEATURE_USDHC_HAS_SDR104_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR104_MODE) - kUSDHC_SupportSDR104Flag = 0, /*!< not support SDR104 mode */ -#else - kUSDHC_SupportSDR104Flag = USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK, /*!< support SDR104 mode */ -#endif -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) - kUSDHC_SupportSDR50Flag = 0U, /*!< not support SDR50 mode */ -#else - kUSDHC_SupportSDR50Flag = USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK, /*!< support SDR50 mode */ -#endif -}; - -/*! @brief Wakeup event mask */ -enum _usdhc_wakeup_event -{ - kUSDHC_WakeupEventOnCardInt = USDHC_PROT_CTRL_WECINT_MASK, /*!< Wakeup on card interrupt */ - kUSDHC_WakeupEventOnCardInsert = USDHC_PROT_CTRL_WECINS_MASK, /*!< Wakeup on card insertion */ - kUSDHC_WakeupEventOnCardRemove = USDHC_PROT_CTRL_WECRM_MASK, /*!< Wakeup on card removal */ - - kUSDHC_WakeupEventsAll = (kUSDHC_WakeupEventOnCardInt | kUSDHC_WakeupEventOnCardInsert | - kUSDHC_WakeupEventOnCardRemove), /*!< All wakeup events */ -}; - -/*! @brief Reset type mask */ -enum _usdhc_reset -{ - kUSDHC_ResetAll = USDHC_SYS_CTRL_RSTA_MASK, /*!< Reset all except card detection */ - kUSDHC_ResetCommand = USDHC_SYS_CTRL_RSTC_MASK, /*!< Reset command line */ - kUSDHC_ResetData = USDHC_SYS_CTRL_RSTD_MASK, /*!< Reset data line */ - -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) - kUSDHC_ResetTuning = 0U, /*!< no reset tuning circuit bit */ -#else - kUSDHC_ResetTuning = USDHC_SYS_CTRL_RSTT_MASK, /*!< reset tuning circuit */ -#endif - - kUSDHC_ResetsAll = - (kUSDHC_ResetAll | kUSDHC_ResetCommand | kUSDHC_ResetData | kUSDHC_ResetTuning), /*!< All reset types */ -}; - -/*! @brief Transfer flag mask */ -enum _usdhc_transfer_flag -{ - kUSDHC_EnableDmaFlag = USDHC_MIX_CTRL_DMAEN_MASK, /*!< Enable DMA */ - - kUSDHC_CommandTypeSuspendFlag = (USDHC_CMD_XFR_TYP_CMDTYP(1U)), /*!< Suspend command */ - kUSDHC_CommandTypeResumeFlag = (USDHC_CMD_XFR_TYP_CMDTYP(2U)), /*!< Resume command */ - kUSDHC_CommandTypeAbortFlag = (USDHC_CMD_XFR_TYP_CMDTYP(3U)), /*!< Abort command */ - - kUSDHC_EnableBlockCountFlag = USDHC_MIX_CTRL_BCEN_MASK, /*!< Enable block count */ - kUSDHC_EnableAutoCommand12Flag = USDHC_MIX_CTRL_AC12EN_MASK, /*!< Enable auto CMD12 */ - kUSDHC_DataReadFlag = USDHC_MIX_CTRL_DTDSEL_MASK, /*!< Enable data read */ - kUSDHC_MultipleBlockFlag = USDHC_MIX_CTRL_MSBSEL_MASK, /*!< Multiple block data read/write */ - kUSDHC_EnableAutoCommand23Flag = USDHC_MIX_CTRL_AC23EN_MASK, /*!< Enable auto CMD23 */ - - kUSDHC_ResponseLength136Flag = USDHC_CMD_XFR_TYP_RSPTYP(1U), /*!< 136 bit response length */ - kUSDHC_ResponseLength48Flag = USDHC_CMD_XFR_TYP_RSPTYP(2U), /*!< 48 bit response length */ - kUSDHC_ResponseLength48BusyFlag = USDHC_CMD_XFR_TYP_RSPTYP(3U), /*!< 48 bit response length with busy status */ - - kUSDHC_EnableCrcCheckFlag = USDHC_CMD_XFR_TYP_CCCEN_MASK, /*!< Enable CRC check */ - kUSDHC_EnableIndexCheckFlag = USDHC_CMD_XFR_TYP_CICEN_MASK, /*!< Enable index check */ - kUSDHC_DataPresentFlag = USDHC_CMD_XFR_TYP_DPSEL_MASK, /*!< Data present flag */ -}; - -/*! @brief Present status flag mask */ -enum _usdhc_present_status_flag -{ - kUSDHC_CommandInhibitFlag = USDHC_PRES_STATE_CIHB_MASK, /*!< Command inhibit */ - kUSDHC_DataInhibitFlag = USDHC_PRES_STATE_CDIHB_MASK, /*!< Data inhibit */ - kUSDHC_DataLineActiveFlag = USDHC_PRES_STATE_DLA_MASK, /*!< Data line active */ - kUSDHC_SdClockStableFlag = USDHC_PRES_STATE_SDSTB_MASK, /*!< SD bus clock stable */ - kUSDHC_WriteTransferActiveFlag = USDHC_PRES_STATE_WTA_MASK, /*!< Write transfer active */ - kUSDHC_ReadTransferActiveFlag = USDHC_PRES_STATE_RTA_MASK, /*!< Read transfer active */ - kUSDHC_BufferWriteEnableFlag = USDHC_PRES_STATE_BWEN_MASK, /*!< Buffer write enable */ - kUSDHC_BufferReadEnableFlag = USDHC_PRES_STATE_BREN_MASK, /*!< Buffer read enable */ - -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) - kUSDHC_DelaySettingFinishedFlag = 0U, /*!< not support */ - kUSDHC_ReTuningRequestFlag = 0U, /*!< not support */ -#else - kUSDHC_ReTuningRequestFlag = USDHC_PRES_STATE_RTR_MASK, /*!< re-tuning request flag ,only used for SDR104 mode */ - kUSDHC_DelaySettingFinishedFlag = USDHC_PRES_STATE_TSCD_MASK, /*!< delay setting finished flag */ -#endif - - kUSDHC_CardInsertedFlag = USDHC_PRES_STATE_CINST_MASK, /*!< Card inserted */ - kUSDHC_CommandLineLevelFlag = USDHC_PRES_STATE_CLSL_MASK, /*!< Command line signal level */ - - kUSDHC_Data0LineLevelFlag = (1U << USDHC_PRES_STATE_DLSL_SHIFT), /*!< Data0 line signal level */ - kUSDHC_Data1LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 1U)), /*!< Data1 line signal level */ - kUSDHC_Data2LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 2U)), /*!< Data2 line signal level */ - kUSDHC_Data3LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 3U)), /*!< Data3 line signal level */ - kUSDHC_Data4LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 4U)), /*!< Data4 line signal level */ - kUSDHC_Data5LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 5U)), /*!< Data5 line signal level */ - kUSDHC_Data6LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 6U)), /*!< Data6 line signal level */ - kUSDHC_Data7LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 7U)), /*!< Data7 line signal level */ -}; - -/*! @brief Interrupt status flag mask */ -enum _usdhc_interrupt_status_flag -{ - kUSDHC_CommandCompleteFlag = USDHC_INT_STATUS_CC_MASK, /*!< Command complete */ - kUSDHC_DataCompleteFlag = USDHC_INT_STATUS_TC_MASK, /*!< Data complete */ - kUSDHC_BlockGapEventFlag = USDHC_INT_STATUS_BGE_MASK, /*!< Block gap event */ - kUSDHC_DmaCompleteFlag = USDHC_INT_STATUS_DINT_MASK, /*!< DMA interrupt */ - kUSDHC_BufferWriteReadyFlag = USDHC_INT_STATUS_BWR_MASK, /*!< Buffer write ready */ - kUSDHC_BufferReadReadyFlag = USDHC_INT_STATUS_BRR_MASK, /*!< Buffer read ready */ - kUSDHC_CardInsertionFlag = USDHC_INT_STATUS_CINS_MASK, /*!< Card inserted */ - kUSDHC_CardRemovalFlag = USDHC_INT_STATUS_CRM_MASK, /*!< Card removed */ - kUSDHC_CardInterruptFlag = USDHC_INT_STATUS_CINT_MASK, /*!< Card interrupt */ - -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) - kUSDHC_ReTuningEventFlag = 0U, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ - kUSDHC_TuningPassFlag = 0U, /*!< SDR104 mode tuning pass flag */ - kUSDHC_TuningErrorFlag = 0U, /*!< SDR104 tuning error flag */ -#else - kUSDHC_ReTuningEventFlag = USDHC_INT_STATUS_RTE_MASK, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ - kUSDHC_TuningPassFlag = USDHC_INT_STATUS_TP_MASK, /*!< SDR104 mode tuning pass flag */ - kUSDHC_TuningErrorFlag = USDHC_INT_STATUS_TNE_MASK, /*!< SDR104 tuning error flag */ -#endif - - kUSDHC_CommandTimeoutFlag = USDHC_INT_STATUS_CTOE_MASK, /*!< Command timeout error */ - kUSDHC_CommandCrcErrorFlag = USDHC_INT_STATUS_CCE_MASK, /*!< Command CRC error */ - kUSDHC_CommandEndBitErrorFlag = USDHC_INT_STATUS_CEBE_MASK, /*!< Command end bit error */ - kUSDHC_CommandIndexErrorFlag = USDHC_INT_STATUS_CIE_MASK, /*!< Command index error */ - kUSDHC_DataTimeoutFlag = USDHC_INT_STATUS_DTOE_MASK, /*!< Data timeout error */ - kUSDHC_DataCrcErrorFlag = USDHC_INT_STATUS_DCE_MASK, /*!< Data CRC error */ - kUSDHC_DataEndBitErrorFlag = USDHC_INT_STATUS_DEBE_MASK, /*!< Data end bit error */ - kUSDHC_AutoCommand12ErrorFlag = USDHC_INT_STATUS_AC12E_MASK, /*!< Auto CMD12 error */ - kUSDHC_DmaErrorFlag = USDHC_INT_STATUS_DMAE_MASK, /*!< DMA error */ - - kUSDHC_CommandErrorFlag = (kUSDHC_CommandTimeoutFlag | kUSDHC_CommandCrcErrorFlag | kUSDHC_CommandEndBitErrorFlag | - kUSDHC_CommandIndexErrorFlag), /*!< Command error */ - kUSDHC_DataErrorFlag = (kUSDHC_DataTimeoutFlag | kUSDHC_DataCrcErrorFlag | kUSDHC_DataEndBitErrorFlag | - kUSDHC_AutoCommand12ErrorFlag), /*!< Data error */ - kUSDHC_ErrorFlag = (kUSDHC_CommandErrorFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< All error */ - kUSDHC_DataFlag = (kUSDHC_DataCompleteFlag | kUSDHC_DmaCompleteFlag | kUSDHC_BufferWriteReadyFlag | - kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< Data interrupts */ - kUSDHC_CommandFlag = (kUSDHC_CommandErrorFlag | kUSDHC_CommandCompleteFlag), /*!< Command interrupts */ - kUSDHC_CardDetectFlag = (kUSDHC_CardInsertionFlag | kUSDHC_CardRemovalFlag), /*!< Card detection interrupts */ - kUSDHC_SDR104TuningFlag = (kUSDHC_TuningErrorFlag | kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag), - - kUSDHC_AllInterruptFlags = (kUSDHC_BlockGapEventFlag | kUSDHC_CardInterruptFlag | kUSDHC_CommandFlag | - kUSDHC_DataFlag | kUSDHC_ErrorFlag | kUSDHC_SDR104TuningFlag), /*!< All flags mask */ -}; - -/*! @brief Auto CMD12 error status flag mask */ -enum _usdhc_auto_command12_error_status_flag -{ - kUSDHC_AutoCommand12NotExecutedFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK, /*!< Not executed error */ - kUSDHC_AutoCommand12TimeoutFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK, /*!< Timeout error */ - kUSDHC_AutoCommand12EndBitErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK, /*!< End bit error */ - kUSDHC_AutoCommand12CrcErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK, /*!< CRC error */ - kUSDHC_AutoCommand12IndexErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK, /*!< Index error */ - kUSDHC_AutoCommand12NotIssuedFlag = USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK, /*!< Not issued error */ -}; - -/*! @brief standard tuning flag */ -enum _usdhc_standard_tuning -{ -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) - kUSDHC_ExecuteTuning = 0U, /*!< not support */ - kUSDHC_TuningSampleClockSel = 0U, /*!< not support */ -#else - kUSDHC_ExecuteTuning = USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK, /*!< used to start tuning procedure */ - kUSDHC_TuningSampleClockSel = - USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK, /*!< when std_tuning_en bit is set, this bit is used - select sampleing clock */ -#endif -}; - -/*! @brief ADMA error status flag mask */ -enum _usdhc_adma_error_status_flag -{ - kUSDHC_AdmaLenghMismatchFlag = USDHC_ADMA_ERR_STATUS_ADMALME_MASK, /*!< Length mismatch error */ - kUSDHC_AdmaDescriptorErrorFlag = USDHC_ADMA_ERR_STATUS_ADMADCE_MASK, /*!< Descriptor error */ -}; - -/*! - * @brief ADMA error state - * - * This state is the detail state when ADMA error has occurred. - */ -enum _usdhc_adma_error_state -{ - kUSDHC_AdmaErrorStateStopDma = - 0x00U, /*!< Stop DMA, previous location set in the ADMA system address is error address */ - kUSDHC_AdmaErrorStateFetchDescriptor = - 0x01U, /*!< Fetch descriptor, current location set in the ADMA system address is error address */ - kUSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address, no DMA error is occured */ - kUSDHC_AdmaErrorStateTransferData = - 0x03U, /*!< Transfer data, previous location set in the ADMA system address is error address */ - kUSDHC_AdmaErrorStateInvalidLength = 0x04U, /*!< Invalid length in ADMA descriptor */ - kUSDHC_AdmaErrorStateInvalidDescriptor = 0x08U, /*!< Invalid descriptor fetched by ADMA */ - - kUSDHC_AdmaErrorState = kUSDHC_AdmaErrorStateInvalidLength | kUSDHC_AdmaErrorStateInvalidDescriptor | - kUSDHC_AdmaErrorStateFetchDescriptor, /*!< ADMA error state */ -}; - -/*! @brief Force event mask */ -enum _usdhc_force_event -{ - kUSDHC_ForceEventAutoCommand12NotExecuted = USDHC_FORCE_EVENT_FEVTAC12NE_MASK, /*!< Auto CMD12 not executed error */ - kUSDHC_ForceEventAutoCommand12Timeout = USDHC_FORCE_EVENT_FEVTAC12TOE_MASK, /*!< Auto CMD12 timeout error */ - kUSDHC_ForceEventAutoCommand12CrcError = USDHC_FORCE_EVENT_FEVTAC12CE_MASK, /*!< Auto CMD12 CRC error */ - kUSDHC_ForceEventEndBitError = USDHC_FORCE_EVENT_FEVTAC12EBE_MASK, /*!< Auto CMD12 end bit error */ - kUSDHC_ForceEventAutoCommand12IndexError = USDHC_FORCE_EVENT_FEVTAC12IE_MASK, /*!< Auto CMD12 index error */ - kUSDHC_ForceEventAutoCommand12NotIssued = USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK, /*!< Auto CMD12 not issued error */ - kUSDHC_ForceEventCommandTimeout = USDHC_FORCE_EVENT_FEVTCTOE_MASK, /*!< Command timeout error */ - kUSDHC_ForceEventCommandCrcError = USDHC_FORCE_EVENT_FEVTCCE_MASK, /*!< Command CRC error */ - kUSDHC_ForceEventCommandEndBitError = USDHC_FORCE_EVENT_FEVTCEBE_MASK, /*!< Command end bit error */ - kUSDHC_ForceEventCommandIndexError = USDHC_FORCE_EVENT_FEVTCIE_MASK, /*!< Command index error */ - kUSDHC_ForceEventDataTimeout = USDHC_FORCE_EVENT_FEVTDTOE_MASK, /*!< Data timeout error */ - kUSDHC_ForceEventDataCrcError = USDHC_FORCE_EVENT_FEVTDCE_MASK, /*!< Data CRC error */ - kUSDHC_ForceEventDataEndBitError = USDHC_FORCE_EVENT_FEVTDEBE_MASK, /*!< Data end bit error */ - kUSDHC_ForceEventAutoCommand12Error = USDHC_FORCE_EVENT_FEVTAC12E_MASK, /*!< Auto CMD12 error */ - kUSDHC_ForceEventCardInt = USDHC_FORCE_EVENT_FEVTCINT_MASK, /*!< Card interrupt */ - kUSDHC_ForceEventDmaError = USDHC_FORCE_EVENT_FEVTDMAE_MASK, /*!< Dma error */ -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) - kUSDHC_ForceEventTuningError = 0U, /*!< not support */ -#else - kUSDHC_ForceEventTuningError = USDHC_FORCE_EVENT_FEVTTNE_MASK, /*!< Tuning error */ -#endif - kUSDHC_ForceEventsAll = - (kUSDHC_ForceEventAutoCommand12NotExecuted | kUSDHC_ForceEventAutoCommand12Timeout | - kUSDHC_ForceEventAutoCommand12CrcError | kUSDHC_ForceEventEndBitError | - kUSDHC_ForceEventAutoCommand12IndexError | kUSDHC_ForceEventAutoCommand12NotIssued | - kUSDHC_ForceEventCommandTimeout | kUSDHC_ForceEventCommandCrcError | kUSDHC_ForceEventCommandEndBitError | - kUSDHC_ForceEventCommandIndexError | kUSDHC_ForceEventDataTimeout | kUSDHC_ForceEventDataCrcError | - kUSDHC_ForceEventDataEndBitError | kUSDHC_ForceEventAutoCommand12Error | kUSDHC_ForceEventCardInt | - kUSDHC_ForceEventDmaError | kUSDHC_ForceEventTuningError), /*!< All force event flags mask */ -}; - -/*! @brief Data transfer width */ -typedef enum _usdhc_data_bus_width -{ - kUSDHC_DataBusWidth1Bit = 0U, /*!< 1-bit mode */ - kUSDHC_DataBusWidth4Bit = 1U, /*!< 4-bit mode */ - kUSDHC_DataBusWidth8Bit = 2U, /*!< 8-bit mode */ -} usdhc_data_bus_width_t; - -/*! @brief Endian mode */ -typedef enum _usdhc_endian_mode -{ - kUSDHC_EndianModeBig = 0U, /*!< Big endian mode */ - kUSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ - kUSDHC_EndianModeLittle = 2U, /*!< Little endian mode */ -} usdhc_endian_mode_t; - -/*! @brief DMA mode */ -typedef enum _usdhc_dma_mode -{ - kUSDHC_DmaModeSimple = 0U, /*!< external DMA */ - kUSDHC_DmaModeAdma1 = 1U, /*!< ADMA1 is selected */ - kUSDHC_DmaModeAdma2 = 2U, /*!< ADMA2 is selected */ - kUSDHC_ExternalDMA = 3U, /*!< external dma mode select */ -} usdhc_dma_mode_t; - -/*! @brief SDIO control flag mask */ -enum _usdhc_sdio_control_flag -{ - kUSDHC_StopAtBlockGapFlag = USDHC_PROT_CTRL_SABGREQ_MASK, /*!< Stop at block gap */ - kUSDHC_ReadWaitControlFlag = USDHC_PROT_CTRL_RWCTL_MASK, /*!< Read wait control */ - kUSDHC_InterruptAtBlockGapFlag = USDHC_PROT_CTRL_IABG_MASK, /*!< Interrupt at block gap */ - kUSDHC_ReadDoneNo8CLK = USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK, /*!< read done without 8 clk for block gap */ - kUSDHC_ExactBlockNumberReadFlag = USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK, /*!< Exact block number read */ -}; - -/*! @brief MMC card boot mode */ -typedef enum _usdhc_boot_mode -{ - kUSDHC_BootModeNormal = 0U, /*!< Normal boot */ - kUSDHC_BootModeAlternative = 1U, /*!< Alternative boot */ -} usdhc_boot_mode_t; - -/*! @brief The command type */ -typedef enum _usdhc_card_command_type -{ - kCARD_CommandTypeNormal = 0U, /*!< Normal command */ - kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ - kCARD_CommandTypeResume = 2U, /*!< Resume command */ - kCARD_CommandTypeAbort = 3U, /*!< Abort command */ - kCARD_CommandTypeEmpty = 4U, /*!< Empty command */ -} usdhc_card_command_type_t; - -/*! - * @brief The command response type. - * - * Define the command response type from card to host controller. - */ -typedef enum _usdhc_card_response_type -{ - kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ - kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ - kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */ - kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */ - kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */ - kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */ - kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */ - kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */ - kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */ - kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ -} usdhc_card_response_type_t; - -/*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */ -#define USDHC_ADMA1_ADDRESS_ALIGN (4096U) -/*! @brief The alignment size for LENGTH field in ADMA1's descriptor */ -#define USDHC_ADMA1_LENGTH_ALIGN (4096U) -/*! @brief The alignment size for ADDRESS field in ADMA2's descriptor */ -#define USDHC_ADMA2_ADDRESS_ALIGN (4U) -/*! @brief The alignment size for LENGTH filed in ADMA2's descriptor */ -#define USDHC_ADMA2_LENGTH_ALIGN (4U) - -/* ADMA1 descriptor table - * |------------------------|---------|--------------------------| - * | Address/page field |Reserved | Attribute | - * |------------------------|---------|--------------------------| - * |31 12|11 6|05 |04 |03|02 |01 |00 | - * |------------------------|---------|----|----|--|---|---|-----| - * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid| - * |------------------------|---------|----|----|--|---|---|-----| - * - * - * |------|------|-----------------|-------|-------------| - * | Act2 | Act1 | Comment | 31-28 | 27 - 12 | - * |------|------|-----------------|---------------------| - * | 0 | 0 | No op | Don't care | - * |------|------|-----------------|-------|-------------| - * | 0 | 1 | Set data length | 0000 | Data Length | - * |------|------|-----------------|-------|-------------| - * | 1 | 0 | Transfer data | Data address | - * |------|------|-----------------|---------------------| - * | 1 | 1 | Link descriptor | Descriptor address | - * |------|------|-----------------|---------------------| - */ -/*! @brief The bit shift for ADDRESS filed in ADMA1's descriptor */ -#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U) -/*! @brief The bit mask for ADDRESS field in ADMA1's descriptor */ -#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU) -/*! @brief The bit shift for LENGTH filed in ADMA1's descriptor */ -#define USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U) -/*! @brief The mask for LENGTH field in ADMA1's descriptor */ -#define USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU) -/*! @brief The maximum value of LENGTH filed in ADMA1's descriptor */ -#define USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK - 3U) - -/*! @brief The mask for the control/status field in ADMA1 descriptor */ -enum _usdhc_adma1_descriptor_flag -{ - kUSDHC_Adma1DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ - kUSDHC_Adma1DescriptorEndFlag = (1U << 1U), /*!< End flag */ - kUSDHC_Adma1DescriptorInterrupFlag = (1U << 2U), /*!< Interrupt flag */ - kUSDHC_Adma1DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 flag */ - kUSDHC_Adma1DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 flag */ - kUSDHC_Adma1DescriptorTypeNop = (kUSDHC_Adma1DescriptorValidFlag), /*!< No operation */ - kUSDHC_Adma1DescriptorTypeTransfer = - (kUSDHC_Adma1DescriptorActivity2Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */ - kUSDHC_Adma1DescriptorTypeLink = (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorActivity2Flag | - kUSDHC_Adma1DescriptorValidFlag), /*!< Link descriptor */ - kUSDHC_Adma1DescriptorTypeSetLength = - (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Set data length */ -}; - -/* ADMA2 descriptor table - * |----------------|---------------|-------------|--------------------------| - * | Address field | Length | Reserved | Attribute | - * |----------------|---------------|-------------|--------------------------| - * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 | - * |----------------|---------------|-------------|----|----|--|---|---|-----| - * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid| - * |----------------|---------------|-------------|----|----|--|---|---|-----| - * - * - * | Act2 | Act1 | Comment | Operation | - * |------|------|-----------------|-------------------------------------------------------------------| - * | 0 | 0 | No op | Don't care | - * |------|------|-----------------|-------------------------------------------------------------------| - * | 0 | 1 | Reserved | Read this line and go to next one | - * |------|------|-----------------|-------------------------------------------------------------------| - * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line | - * |------|------|-----------------|-------------------------------------------------------------------| - * | 1 | 1 | Link descriptor | Link to another descriptor | - * |------|------|-----------------|-------------------------------------------------------------------| - */ -/*! @brief The bit shift for LENGTH field in ADMA2's descriptor */ -#define USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U) -/*! @brief The bit mask for LENGTH field in ADMA2's descriptor */ -#define USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU) -/*! @brief The maximum value of LENGTH field in ADMA2's descriptor */ -#define USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK - 3U) - -/*! @brief ADMA1 descriptor control and status mask */ -enum _usdhc_adma2_descriptor_flag -{ - kUSDHC_Adma2DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ - kUSDHC_Adma2DescriptorEndFlag = (1U << 1U), /*!< End flag */ - kUSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */ - kUSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */ - kUSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */ - - kUSDHC_Adma2DescriptorTypeNop = (kUSDHC_Adma2DescriptorValidFlag), /*!< No operation */ - kUSDHC_Adma2DescriptorTypeReserved = - (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Reserved */ - kUSDHC_Adma2DescriptorTypeTransfer = - (kUSDHC_Adma2DescriptorActivity2Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Transfer type */ - kUSDHC_Adma2DescriptorTypeLink = (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorActivity2Flag | - kUSDHC_Adma2DescriptorValidFlag), /*!< Link type */ -}; - -/*! @brief ADMA descriptor configuration flag */ -enum _usdhc_adma_flag -{ - kUSDHC_AdmaDescriptorSingleFlag = - 0U, /*!< try to finish the transfer in a single ADMA descriptor, if transfer size is bigger than one - ADMA descriptor's ability, new another descriptor for data transfer */ - kUSDHC_AdmaDescriptorMultipleFlag = 1U, /*!< create multiple ADMA descriptor within the ADMA table, this is used for - mmc boot mode specifically, which need - to modify the ADMA descriptor on the fly, so the flag should be used - combine with stop at block gap feature */ -}; - -/*! @brief dma transfer burst len config. */ -typedef enum _usdhc_burst_len -{ - kUSDHC_EnBurstLenForINCR = 0x01U, /*!< enable burst len for INCR */ - kUSDHC_EnBurstLenForINCR4816 = 0x02U, /*!< enable burst len for INCR4/INCR8/INCR16 */ - kUSDHC_EnBurstLenForINCR4816WRAP = 0x04U, /*!< enable burst len for INCR4/8/16 WRAP */ -} usdhc_burst_len_t; - -/*! @brief transfer data type definition. */ -enum _usdhc_transfer_data_type -{ - kUSDHC_TransferDataNormal = 0U, /*!< transfer normal read/write data */ - kUSDHC_TransferDataTuning = 1U, /*!< transfer tuning data */ - kUSDHC_TransferDataBoot = 2U, /*!< transfer boot data */ - kUSDHC_TransferDataBootcontinous = 3U, /*!< transfer boot data continous */ -}; - -/*! @brief Defines the adma1 descriptor structure. */ -typedef uint32_t usdhc_adma1_descriptor_t; - -/*! @brief Defines the ADMA2 descriptor structure. */ -typedef struct _usdhc_adma2_descriptor -{ - uint32_t attribute; /*!< The control and status field */ - const uint32_t *address; /*!< The address field */ -} usdhc_adma2_descriptor_t; - -/*! - * @brief USDHC capability information. - * - * Defines a structure to save the capability information of USDHC. - */ -typedef struct _usdhc_capability -{ - uint32_t sdVersion; /*!< support SD card/sdio version */ - uint32_t mmcVersion; /*!< support emmc card version */ - uint32_t maxBlockLength; /*!< Maximum block length united as byte */ - uint32_t maxBlockCount; /*!< Maximum block count can be set one time */ - uint32_t flags; /*!< Capability flags to indicate the support information(_usdhc_capability_flag) */ -} usdhc_capability_t; - -/*! @brief Data structure to configure the MMC boot feature */ -typedef struct _usdhc_boot_config -{ - uint32_t ackTimeoutCount; /*!< Timeout value for the boot ACK. The available range is 0 ~ 15. */ - usdhc_boot_mode_t bootMode; /*!< Boot mode selection. */ - uint32_t blockCount; /*!< Stop at block gap value of automatic mode. Available range is 0 ~ 65535. */ - size_t blockSize; /*!< Block size */ - bool enableBootAck; /*!< Enable or disable boot ACK */ - bool enableAutoStopAtBlockGap; /*!< Enable or disable auto stop at block gap function in boot period */ -} usdhc_boot_config_t; - -/*! @brief Data structure to initialize the USDHC */ -typedef struct _usdhc_config -{ - uint32_t dataTimeout; /*!< Data timeout value */ - usdhc_endian_mode_t endianMode; /*!< Endian mode */ - uint8_t readWatermarkLevel; /*!< Watermark level for DMA read operation. Available range is 1 ~ 128. */ - uint8_t writeWatermarkLevel; /*!< Watermark level for DMA write operation. Available range is 1 ~ 128. */ - uint8_t readBurstLen; /*!< Read burst len */ - uint8_t writeBurstLen; /*!< Write burst len */ -} usdhc_config_t; - -/*! - * @brief Card data descriptor - * - * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card - * driver - * want to ignore the error event to read/write all the data not to stop read/write immediately when error event - * happen for example bus testing procedure for MMC card. - */ -typedef struct _usdhc_data -{ - bool enableAutoCommand12; /*!< Enable auto CMD12 */ - bool enableAutoCommand23; /*!< Enable auto CMD23 */ - bool enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */ - uint8_t dataType; /*!< this is used to distinguish the normal/tuning/boot data */ - size_t blockSize; /*!< Block size */ - uint32_t blockCount; /*!< Block count */ - uint32_t *rxData; /*!< Buffer to save data read */ - const uint32_t *txData; /*!< Data buffer to write */ -} usdhc_data_t; - -/*! - * @brief Card command descriptor - * - * Define card command-related attribute. - */ -typedef struct _usdhc_command -{ - uint32_t index; /*!< Command index */ - uint32_t argument; /*!< Command argument */ - usdhc_card_command_type_t type; /*!< Command type */ - usdhc_card_response_type_t responseType; /*!< Command response type */ - uint32_t response[4U]; /*!< Response for this command */ - uint32_t responseErrorFlags; /*!< response error flag, the flag which need to check - the command reponse*/ - uint32_t flags; /*!< Cmd flags */ -} usdhc_command_t; - -/*! @brief ADMA configuration */ -typedef struct _usdhc_adma_config -{ - usdhc_dma_mode_t dmaMode; /*!< DMA mode */ - - usdhc_burst_len_t burstLen; /*!< burst len config */ - - uint32_t *admaTable; /*!< ADMA table address, can't be null if transfer way is ADMA1/ADMA2 */ - uint32_t admaTableWords; /*!< ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2 */ -} usdhc_adma_config_t; - -/*! @brief Transfer state */ -typedef struct _usdhc_transfer -{ - usdhc_data_t *data; /*!< Data to transfer */ - usdhc_command_t *command; /*!< Command to send */ -} usdhc_transfer_t; - -/*! @brief USDHC handle typedef */ -typedef struct _usdhc_handle usdhc_handle_t; - -/*! @brief USDHC callback functions. */ -typedef struct _usdhc_transfer_callback -{ - void (*CardInserted)(USDHC_Type *base, - void *userData); /*!< Card inserted occurs when DAT3/CD pin is for card detect */ - void (*CardRemoved)(USDHC_Type *base, void *userData); /*!< Card removed occurs */ - void (*SdioInterrupt)(USDHC_Type *base, void *userData); /*!< SDIO card interrupt occurs */ - void (*BlockGap)(USDHC_Type *base, void *userData); /*!< stopped at block gap event */ - void (*TransferComplete)(USDHC_Type *base, - usdhc_handle_t *handle, - status_t status, - void *userData); /*!< Transfer complete callback */ - void (*ReTuning)(USDHC_Type *base, void *userData); /*!< handle the re-tuning */ -} usdhc_transfer_callback_t; - -/*! - * @brief USDHC handle - * - * Defines the structure to save the USDHC state information and callback function. The detailed interrupt status when - * sending a command or transfering data can be obtained from the interruptFlags field by using the mask defined in - * usdhc_interrupt_flag_t. - * - * @note All the fields except interruptFlags and transferredWords must be allocated by the user. - */ -struct _usdhc_handle -{ - /* Transfer parameter */ - usdhc_data_t *volatile data; /*!< Data to transfer */ - usdhc_command_t *volatile command; /*!< Command to send */ - - /* Transfer status */ - volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */ - volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */ - - /* Callback functions */ - usdhc_transfer_callback_t callback; /*!< Callback function */ - void *userData; /*!< Parameter for transfer complete callback */ -}; - -/*! @brief USDHC transfer function. */ -typedef status_t (*usdhc_transfer_function_t)(USDHC_Type *base, usdhc_transfer_t *content); - -/*! @brief USDHC host descriptor */ -typedef struct _usdhc_host -{ - USDHC_Type *base; /*!< USDHC peripheral base address */ - uint32_t sourceClock_Hz; /*!< USDHC source clock frequency united in Hz */ - usdhc_config_t config; /*!< USDHC configuration */ - usdhc_capability_t capability; /*!< USDHC capability information */ - usdhc_transfer_function_t transfer; /*!< USDHC transfer function */ -} usdhc_host_t; - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief USDHC module initialization function. - * - * Configures the USDHC according to the user configuration. - * - * Example: - @code - usdhc_config_t config; - config.cardDetectDat3 = false; - config.endianMode = kUSDHC_EndianModeLittle; - config.dmaMode = kUSDHC_DmaModeAdma2; - config.readWatermarkLevel = 128U; - config.writeWatermarkLevel = 128U; - USDHC_Init(USDHC, &config); - @endcode - * - * @param base USDHC peripheral base address. - * @param config USDHC configuration information. - * @retval kStatus_Success Operate successfully. - */ -void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config); - -/*! - * @brief Deinitializes the USDHC. - * - * @param base USDHC peripheral base address. - */ -void USDHC_Deinit(USDHC_Type *base); - -/*! - * @brief Resets the USDHC. - * - * @param base USDHC peripheral base address. - * @param mask The reset type mask(_usdhc_reset). - * @param timeout Timeout for reset. - * @retval true Reset successfully. - * @retval false Reset failed. - */ -bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout); - -/* @} */ - -/*! - * @name DMA Control - * @{ - */ - -/*! - * @brief Sets the DMA descriptor table configuration. - * A high level DMA descriptor configuration function. - * @param base USDHC peripheral base address. - * @param adma configuration - * @param data Data descriptor - * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please - * reference _usdhc_adma_flag - * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. - * @retval kStatus_Success Operate successfully. - */ -status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, - usdhc_adma_config_t *dmaConfig, - usdhc_data_t *dataConfig, - uint32_t flags); - -/*! - * @brief Internal DMA configuration. - * This function is used to config the USDHC DMA related registers. - * @param base USDHC peripheral base address. - * @param adma configuration - * @param dataAddr tranfer data address, a simple DMA parameter, if ADMA is used, leave it to NULL. - * @param enAutoCmd23 flag to indicate Auto CMD23 is enable or not, a simple DMA parameter,if ADMA is used, leave it to - * false. - * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. - * @retval kStatus_Success Operate successfully. - */ -status_t USDHC_SetInternalDmaConfig(USDHC_Type *base, - usdhc_adma_config_t *dmaConfig, - const uint32_t *dataAddr, - bool enAutoCmd23); - -/*! - * @brief Sets the ADMA2 descriptor table configuration. - * - * @param admaTable Adma table address. - * @param admaTableWords Adma table length. - * @param dataBufferAddr Data buffer address. - * @param dataBytes Data Data length. - * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please - * reference _usdhc_adma_flag. - * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. - * @retval kStatus_Success Operate successfully. - */ -status_t USDHC_SetADMA2Descriptor( - uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags); - -/*! - * @brief Sets the ADMA1 descriptor table configuration. - * - * @param admaTable Adma table address. - * @param admaTableWords Adma table length. - * @param dataBufferAddr Data buffer address. - * @param dataBytes Data length. - * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please - * reference _usdhc_adma_flag. - * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. - * @retval kStatus_Success Operate successfully. - */ -status_t USDHC_SetADMA1Descriptor( - uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags); - -/*! - * @brief enable internal DMA. - * - * @param base USDHC peripheral base address. - * @param enable enable or disable flag - */ -static inline void USDHC_EnableInternalDMA(USDHC_Type *base, bool enable) -{ - if (enable) - { - base->MIX_CTRL |= USDHC_MIX_CTRL_DMAEN_MASK; - } - else - { - base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; - base->PROT_CTRL &= ~USDHC_PROT_CTRL_DMASEL_MASK; - } -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables the interrupt status. - * - * @param base USDHC peripheral base address. - * @param mask Interrupt status flags mask(_usdhc_interrupt_status_flag). - */ -static inline void USDHC_EnableInterruptStatus(USDHC_Type *base, uint32_t mask) -{ - base->INT_STATUS_EN |= mask; -} - -/*! - * @brief Disables the interrupt status. - * - * @param base USDHC peripheral base address. - * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). - */ -static inline void USDHC_DisableInterruptStatus(USDHC_Type *base, uint32_t mask) -{ - base->INT_STATUS_EN &= ~mask; -} - -/*! - * @brief Enables the interrupt signal corresponding to the interrupt status flag. - * - * @param base USDHC peripheral base address. - * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). - */ -static inline void USDHC_EnableInterruptSignal(USDHC_Type *base, uint32_t mask) -{ - base->INT_SIGNAL_EN |= mask; -} - -/*! - * @brief Disables the interrupt signal corresponding to the interrupt status flag. - * - * @param base USDHC peripheral base address. - * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). - */ -static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask) -{ - base->INT_SIGNAL_EN &= ~mask; -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Gets the current interrupt status. - * - * @param base USDHC peripheral base address. - * @return Current interrupt status flags mask(_usdhc_interrupt_status_flag). - */ -static inline uint32_t USDHC_GetInterruptStatusFlags(USDHC_Type *base) -{ - return base->INT_STATUS; -} - -/*! - * @brief Clears a specified interrupt status. - * write 1 clears - * @param base USDHC peripheral base address. - * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). - */ -static inline void USDHC_ClearInterruptStatusFlags(USDHC_Type *base, uint32_t mask) -{ - base->INT_STATUS = mask; -} - -/*! - * @brief Gets the status of auto command 12 error. - * - * @param base USDHC peripheral base address. - * @return Auto command 12 error status flags mask(_usdhc_auto_command12_error_status_flag). - */ -static inline uint32_t USDHC_GetAutoCommand12ErrorStatusFlags(USDHC_Type *base) -{ - return base->AUTOCMD12_ERR_STATUS; -} - -/*! - * @brief Gets the status of the ADMA error. - * - * @param base USDHC peripheral base address. - * @return ADMA error status flags mask(_usdhc_adma_error_status_flag). - */ -static inline uint32_t USDHC_GetAdmaErrorStatusFlags(USDHC_Type *base) -{ - return base->ADMA_ERR_STATUS & 0xFU; -} - -/*! - * @brief Gets a present status. - * - * This function gets the present USDHC's status except for an interrupt status and an error status. - * - * @param base USDHC peripheral base address. - * @return Present USDHC's status flags mask(_usdhc_present_status_flag). - */ -static inline uint32_t USDHC_GetPresentStatusFlags(USDHC_Type *base) -{ - return base->PRES_STATE; -} - -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Gets the capability information. - * - * @param base USDHC peripheral base address. - * @param capability Structure to save capability information. - */ -void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability); - -/*! - * @brief force the card clock on. - * - * @param base USDHC peripheral base address. - * @param enable/disable flag. - */ -static inline void USDHC_ForceClockOn(USDHC_Type *base, bool enable) -{ - if (enable) - { - base->VEND_SPEC |= USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; - } - else - { - base->VEND_SPEC &= ~USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; - } -} - -/*! - * @brief Sets the SD bus clock frequency. - * - * @param base USDHC peripheral base address. - * @param srcClock_Hz USDHC source clock frequency united in Hz. - * @param busClock_Hz SD bus clock frequency united in Hz. - * - * @return The nearest frequency of busClock_Hz configured to SD bus. - */ -uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz); - -/*! - * @brief Sends 80 clocks to the card to set it to the active state. - * - * This function must be called each time the card is inserted to ensure that the card can receive the command - * correctly. - * - * @param base USDHC peripheral base address. - * @param timeout Timeout to initialize card. - * @retval true Set card active successfully. - * @retval false Set card active failed. - */ -bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout); - -/*! - * @brief trigger a hardware reset. - * - * @param base USDHC peripheral base address. - * @param 1 or 0 level - */ -static inline void USDHC_AssertHardwareReset(USDHC_Type *base, bool high) -{ - if (high) - { - base->SYS_CTRL |= USDHC_SYS_CTRL_IPP_RST_N_MASK; - } - else - { - base->SYS_CTRL &= ~USDHC_SYS_CTRL_IPP_RST_N_MASK; - } -} - -/*! - * @brief Sets the data transfer width. - * - * @param base USDHC peripheral base address. - * @param width Data transfer width. - */ -static inline void USDHC_SetDataBusWidth(USDHC_Type *base, usdhc_data_bus_width_t width) -{ - base->PROT_CTRL = ((base->PROT_CTRL & ~USDHC_PROT_CTRL_DTW_MASK) | USDHC_PROT_CTRL_DTW(width)); -} - -/*! - * @brief Fills the data port. - * - * This function is used to implement the data transfer by Data Port instead of DMA. - * - * @param base USDHC peripheral base address. - * @param data The data about to be sent. - */ -static inline void USDHC_WriteData(USDHC_Type *base, uint32_t data) -{ - base->DATA_BUFF_ACC_PORT = data; -} - -/*! - * @brief Retrieves the data from the data port. - * - * This function is used to implement the data transfer by Data Port instead of DMA. - * - * @param base USDHC peripheral base address. - * @return The data has been read. - */ -static inline uint32_t USDHC_ReadData(USDHC_Type *base) -{ - return base->DATA_BUFF_ACC_PORT; -} - -/*! -* @brief send command function -* -* @param base USDHC peripheral base address. -* @param command configuration -*/ -void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command); - -/*! - * @brief Enables or disables a wakeup event in low-power mode. - * - * @param base USDHC peripheral base address. - * @param mask Wakeup events mask(_usdhc_wakeup_event). - * @param enable True to enable, false to disable. - */ -static inline void USDHC_EnableWakeupEvent(USDHC_Type *base, uint32_t mask, bool enable) -{ - if (enable) - { - base->PROT_CTRL |= mask; - } - else - { - base->PROT_CTRL &= ~mask; - } -} - -/*! - * @brief detect card insert status. - * - * @param base USDHC peripheral base address. - * @param enable/disable flag - */ -static inline void USDHC_CardDetectByData3(USDHC_Type *base, bool enable) -{ - if (enable) - { - base->PROT_CTRL |= USDHC_PROT_CTRL_D3CD_MASK; - } - else - { - base->PROT_CTRL &= ~USDHC_PROT_CTRL_D3CD_MASK; - } -} - -/*! - * @brief detect card insert status. - * - * @param base USDHC peripheral base address. - */ -static inline bool USDHC_DetectCardInsert(USDHC_Type *base) -{ - return (base->PRES_STATE & kUSDHC_CardInsertedFlag) ? true : false; -} - -/*! - * @brief Enables or disables the SDIO card control. - * - * @param base USDHC peripheral base address. - * @param mask SDIO card control flags mask(_usdhc_sdio_control_flag). - * @param enable True to enable, false to disable. - */ -static inline void USDHC_EnableSdioControl(USDHC_Type *base, uint32_t mask, bool enable) -{ - if (enable) - { - base->PROT_CTRL |= mask; - } - else - { - base->PROT_CTRL &= ~mask; - } -} - -/*! - * @brief Restarts a transaction which has stopped at the block GAP for the SDIO card. - * - * @param base USDHC peripheral base address. - */ -static inline void USDHC_SetContinueRequest(USDHC_Type *base) -{ - base->PROT_CTRL |= USDHC_PROT_CTRL_CREQ_MASK; -} - -/*! - * @brief Request stop at block gap function. - * - * @param base USDHC peripheral base address. - * @param enable true to stop at block gap, false to normal transfer - */ -static inline void USDHC_RequestStopAtBlockGap(USDHC_Type *base, bool enable) -{ - if (enable) - { - base->PROT_CTRL |= USDHC_PROT_CTRL_SABGREQ_MASK; - } - else - { - base->PROT_CTRL &= ~USDHC_PROT_CTRL_SABGREQ_MASK; - } -} - -/*! - * @brief Configures the MMC boot feature. - * - * Example: - @code - usdhc_boot_config_t config; - config.ackTimeoutCount = 4; - config.bootMode = kUSDHC_BootModeNormal; - config.blockCount = 5; - config.enableBootAck = true; - config.enableBoot = true; - config.enableAutoStopAtBlockGap = true; - USDHC_SetMmcBootConfig(USDHC, &config); - @endcode - * - * @param base USDHC peripheral base address. - * @param config The MMC boot configuration information. - */ -void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config); - -/*! - * @brief Enables or disables the mmc boot mode. - * - * @param base USDHC peripheral base address. - * @param enable True to enable, false to disable. - */ -static inline void USDHC_EnableMmcBoot(USDHC_Type *base, bool enable) -{ - if (enable) - { - base->MMC_BOOT |= USDHC_MMC_BOOT_BOOT_EN_MASK; - } - else - { - base->MMC_BOOT &= ~USDHC_MMC_BOOT_BOOT_EN_MASK; - } -} - -/*! - * @brief Forces generating events according to the given mask. - * - * @param base USDHC peripheral base address. - * @param mask The force events mask(_usdhc_force_event). - */ -static inline void USDHC_SetForceEvent(USDHC_Type *base, uint32_t mask) -{ - base->FORCE_EVENT = mask; -} - -/*! - * @brief select the usdhc output voltage - * - * @param base USDHC peripheral base address. - * @param true 1.8V, false 3.0V - */ -static inline void UDSHC_SelectVoltage(USDHC_Type *base, bool en18v) -{ - if (en18v) - { - base->VEND_SPEC |= USDHC_VEND_SPEC_VSELECT_MASK; - } - else - { - base->VEND_SPEC &= ~USDHC_VEND_SPEC_VSELECT_MASK; - } -} - -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (FSL_FEATURE_USDHC_HAS_SDR50_MODE) -/*! -* @brief check the SDR50 mode request tuning bit -* When this bit set, user should call USDHC_StandardTuning function -* @param base USDHC peripheral base address. -*/ -static inline bool USDHC_RequestTuningForSDR50(USDHC_Type *base) -{ - return base->HOST_CTRL_CAP & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK ? true : false; -} - -/*! - * @brief check the request re-tuning bit - * When this bit is set, user should do manual tuning or standard tuning function - * @param base USDHC peripheral base address. - */ -static inline bool USDHC_RequestReTuning(USDHC_Type *base) -{ - return base->PRES_STATE & USDHC_PRES_STATE_RTR_MASK ? true : false; -} - -/*! - * @brief the SDR104 mode auto tuning enable and disable - * This function should call after tuning function execute pass, auto tuning will handle - * by hardware - * @param base USDHC peripheral base address. - * @param enable/disable flag - */ -static inline void USDHC_EnableAutoTuning(USDHC_Type *base, bool enable) -{ - if (enable) - { - base->MIX_CTRL |= USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; - } - else - { - base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; - } -} - -/*! - * @brief the config the re-tuning timer for mode 1 and mode 3 - * This timer is used for standard tuning auto re-tuning, - * @param base USDHC peripheral base address. - * @param timer counter value - */ -static inline void USDHC_SetRetuningTimer(USDHC_Type *base, uint32_t counter) -{ - base->HOST_CTRL_CAP &= ~USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK; - base->HOST_CTRL_CAP |= USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(counter); -} - -/*! - * @brief the auto tuning enbale for CMD/DATA line - * - * @param base USDHC peripheral base address. - */ -void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base); - -/*! - * @brief manual tuning trigger or abort - * User should handle the tuning cmd and find the boundary of the delay - * then calucate a average value which will be config to the CLK_TUNE_CTRL_STATUS - * This function should called before USDHC_AdjustDelayforSDR104 function - * @param base USDHC peripheral base address. - * @param tuning enable flag - */ -void USDHC_EnableManualTuning(USDHC_Type *base, bool enable); - -/*! - * @brief the SDR104 mode delay setting adjust - * This function should called after USDHC_ManualTuningForSDR104 - * @param base USDHC peripheral base address. - * @param delay setting configuration - * @retval kStatus_Fail config the delay setting fail - * @retval kStatus_Success config the delay setting success - */ -status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay); - -/*! - * @brief the enable standard tuning function - * The standard tuning window and tuning counter use the default config - * tuning cmd is send by the software, user need to check the tuning result - * can be used for SDR50,SDR104,HS200 mode tuning - * @param base USDHC peripheral base address. - * @param tuning start tap - * @param tuning step - * @param enable/disable flag - */ -void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable); - -/*! - * @brief Get execute std tuning status - * - * @param base USDHC peripheral base address. - */ -static inline uint32_t USDHC_GetExecuteStdTuningStatus(USDHC_Type *base) -{ - return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK); -} - -/*! - * @brief check std tuning result - * - * @param base USDHC peripheral base address. - */ -static inline uint32_t USDHC_CheckStdTuningResult(USDHC_Type *base) -{ - return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); -} - -/*! - * @brief check tuning error - * - * @param base USDHC peripheral base address. - */ -static inline uint32_t USDHC_CheckTuningError(USDHC_Type *base) -{ - return (base->CLK_TUNE_CTRL_STATUS & - (USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)); -} - -#endif -/*! - * @brief the enable/disable DDR mode - * - * @param base USDHC peripheral base address. - * @param enable/disable flag - * @param nibble position - */ -void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos); - -/*! - * @brief the enable/disable HS400 mode - * - * @param base USDHC peripheral base address. - * @param enable/disable flag - */ -#if FSL_FEATURE_USDHC_HAS_HS400_MODE -static inline void USDHC_EnableHS400Mode(USDHC_Type *base, bool enable) -{ - if (enable) - { - base->MIX_CTRL |= USDHC_MIX_CTRL_HS400_MODE_MASK; - } - else - { - base->MIX_CTRL &= ~USDHC_MIX_CTRL_HS400_MODE_MASK; - } -} - -/*! - * @brief reset the strobe DLL - * - * @param base USDHC peripheral base address. - */ -static inline void USDHC_ResetStrobeDLL(USDHC_Type *base) -{ - base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK; -} - -/*! - * @brief enable/disable the strobe DLL - * - * @param base USDHC peripheral base address. - * @param enable/disable flag - */ -static inline void USDHC_EnableStrobeDLL(USDHC_Type *base, bool enable) -{ - if (enable) - { - base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; - } - else - { - base->STROBE_DLL_CTRL &= ~USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; - } -} - -/*! - * @brief config the strobe DLL delay target and update interval - * - * @param base USDHC peripheral base address. - * @param delay target - * @param update interval - */ -static inline void USDHC_ConfigStrobeDLL(USDHC_Type *base, uint32_t delayTarget, uint32_t updateInterval) -{ - base->STROBE_DLL_CTRL &= (USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK | - USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK); - - base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(updateInterval) | - USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(delayTarget); -} - -/*! - * @brief get the strobe DLL status - * - * @param base USDHC peripheral base address. - */ -static inline uint32_t USDHC_GetStrobeDLLStatus(USDHC_Type *base) -{ - return base->STROBE_DLL_STATUS; -} - -#endif - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Transfers the command/data using a blocking method. - * - * This function waits until the command response/data is received or the USDHC encounters an error by polling the - * status - * flag. - * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support - * the re-entry mechanism. - * - * @note There is no need to call the API 'USDHC_TransferCreateHandle' when calling this API. - * - * @param base USDHC peripheral base address. - * @param adma configuration - * @param transfer Transfer content. - * @retval kStatus_InvalidArgument Argument is invalid. - * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. - * @retval kStatus_USDHC_SendCommandFailed Send command failed. - * @retval kStatus_USDHC_TransferDataFailed Transfer data failed. - * @retval kStatus_Success Operate successfully. - */ -status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer); - -/*! - * @brief Creates the USDHC handle. - * - * @param base USDHC peripheral base address. - * @param handle USDHC handle pointer. - * @param callback Structure pointer to contain all callback functions. - * @param userData Callback function parameter. - */ -void USDHC_TransferCreateHandle(USDHC_Type *base, - usdhc_handle_t *handle, - const usdhc_transfer_callback_t *callback, - void *userData); - -/*! - * @brief Transfers the command/data using an interrupt and an asynchronous method. - * - * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an - * error. - * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support - * the re-entry mechanism. - * - * @note Call the API 'USDHC_TransferCreateHandle' when calling this API. - * - * @param base USDHC peripheral base address. - * @param handle USDHC handle. - * @param adma configuration. - * @param transfer Transfer content. - * @retval kStatus_InvalidArgument Argument is invalid. - * @retval kStatus_USDHC_BusyTransferring Busy transferring. - * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. - * @retval kStatus_Success Operate successfully. - */ -status_t USDHC_TransferNonBlocking(USDHC_Type *base, - usdhc_handle_t *handle, - usdhc_adma_config_t *dmaConfig, - usdhc_transfer_t *transfer); - -/*! - * @brief IRQ handler for the USDHC. - * - * This function deals with the IRQs on the given host controller. - * - * @param base USDHC peripheral base address. - * @param handle USDHC handle. - */ -void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! @} */ - -#endif /* _FSL_USDHC_H_*/ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_wdog.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_wdog.c deleted file mode 100644 index b1cc4eb1fb..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_wdog.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_wdog.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.wdog01" -#endif - - -/******************************************************************************* - * Variables - ******************************************************************************/ -static WDOG_Type *const s_wdogBases[] = WDOG_BASE_PTRS; -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of WDOG clock name. */ -static const clock_ip_name_t s_wdogClock[] = WDOG_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t WDOG_GetInstance(WDOG_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_wdogBases); instance++) - { - if (s_wdogBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_wdogBases)); - - return instance; -} - -void WDOG_GetDefaultConfig(wdog_config_t *config) -{ - assert(config); - - config->enableWdog = true; - config->workMode.enableWait = false; - config->workMode.enableStop = false; - config->workMode.enableDebug = false; - config->enableInterrupt = false; - config->softwareResetExtension = false; - config->enablePowerDown = false; - config->softwareAssertion= true; - config->softwareResetSignal = true; - config->timeoutValue = 0xffu; - config->interruptTimeValue = 0x04u; -} - -void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) -{ - assert(config); - - uint16_t value = 0u; - - value = WDOG_WCR_WDE(config->enableWdog) | WDOG_WCR_WDW(config->workMode.enableWait) | - WDOG_WCR_WDZST(config->workMode.enableStop) | WDOG_WCR_WDBG(config->workMode.enableDebug) | - WDOG_WCR_SRE(config->softwareResetExtension) | WDOG_WCR_WT(config->timeoutValue) | - WDOG_WCR_WDA(config->softwareAssertion) | WDOG_WCR_SRS(config->softwareResetSignal); - - /* Set configruation */ - CLOCK_EnableClock(s_wdogClock[WDOG_GetInstance(base)]); - base->WICR = WDOG_WICR_WICT(config->interruptTimeValue) | WDOG_WICR_WIE(config->enableInterrupt); - base->WMCR = WDOG_WMCR_PDE(config->enablePowerDown); - base->WCR = value; -} - -void WDOG_Deinit(WDOG_Type *base) -{ - if (base->WCR & WDOG_WCR_WDBG_MASK) - { - WDOG_Disable(base); - } -} - -uint16_t WDOG_GetStatusFlags(WDOG_Type *base) -{ - uint16_t status_flag = 0U; - - status_flag |= (base->WCR & WDOG_WCR_WDE_MASK); - status_flag |= (base->WRSR & WDOG_WRSR_POR_MASK); - status_flag |= (base->WRSR & WDOG_WRSR_TOUT_MASK); - status_flag |= (base->WRSR & WDOG_WRSR_SFTW_MASK); - status_flag |= (base->WICR & WDOG_WICR_WTIS_MASK); - - return status_flag; -} - -void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask) -{ - if (mask & kWDOG_InterruptFlag) - { - base->WICR |= WDOG_WICR_WTIS_MASK; - } -} - -void WDOG_Refresh(WDOG_Type *base) -{ - base->WSR = WDOG_REFRESH_KEY & 0xFFFFU; - base->WSR = (WDOG_REFRESH_KEY >> 16U) & 0xFFFFU; -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_wdog.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_wdog.h deleted file mode 100644 index 508714bbe1..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_wdog.h +++ /dev/null @@ -1,303 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_WDOG_H_ -#define _FSL_WDOG_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup wdog - * @{ - */ - -/******************************************************************************* - * Definitions - *******************************************************************************/ -/*! @name Driver version */ -/*@{*/ -/*! @brief Defines WDOG driver version */ -#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ -/*! @name Refresh sequence */ -/*@{*/ -#define WDOG_REFRESH_KEY (0xAAAA5555U) -/*@}*/ - -/*! @brief Defines WDOG work mode. */ -typedef struct _wdog_work_mode -{ - bool enableWait; /*!< continue or suspend WDOG in wait mode */ - bool enableStop; /*!< continue or suspend WDOG in stop mode */ - bool enableDebug; /*!< continue or suspend WDOG in debug mode */ -} wdog_work_mode_t; - -/*! @brief Describes WDOG configuration structure. */ -typedef struct _wdog_config -{ - bool enableWdog; /*!< Enables or disables WDOG */ - wdog_work_mode_t workMode; /*!< Configures WDOG work mode in debug stop and wait mode */ - bool enableInterrupt; /*!< Enables or disables WDOG interrupt */ - uint16_t timeoutValue; /*!< Timeout value */ - uint16_t interruptTimeValue; /*!< Interrupt count timeout value */ - bool softwareResetExtension; /*!< software reset extension */ - bool enablePowerDown; /*!< power down enable bit */ - bool softwareAssertion; /*!< software assertion bit*/ - bool softwareResetSignal; /*!< software reset signalbit*/ -} wdog_config_t; - -/*! - * @brief WDOG interrupt configuration structure, default settings all disabled. - * - * This structure contains the settings for all of the WDOG interrupt configurations. - */ -enum _wdog_interrupt_enable -{ - kWDOG_InterruptEnable = WDOG_WICR_WIE_MASK /*!< WDOG timeout generates an interrupt before reset*/ -}; - -/*! - * @brief WDOG status flags. - * - * This structure contains the WDOG status flags for use in the WDOG functions. - */ -enum _wdog_status_flags -{ - kWDOG_RunningFlag = WDOG_WCR_WDE_MASK, /*!< Running flag, set when WDOG is enabled*/ - kWDOG_PowerOnResetFlag = WDOG_WRSR_POR_MASK, /*!< Power On flag, set when reset is the result of a powerOnReset*/ - kWDOG_TimeoutResetFlag = WDOG_WRSR_TOUT_MASK, /*!< Timeout flag, set when reset is the result of a timeout*/ - kWDOG_SoftwareResetFlag = WDOG_WRSR_SFTW_MASK, /*!< Software flag, set when reset is the result of a software*/ - kWDOG_InterruptFlag = WDOG_WICR_WTIS_MASK /*!< interrupt flag,whether interrupt has occurred or not*/ -}; - -/******************************************************************************* - * API - *******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name WDOG Initialization and De-initialization. - * @{ - */ - -/*! - * @brief Initializes the WDOG configuration sturcture. - * - * This function initializes the WDOG configuration structure to default values. The default - * values are as follows. - * @code - * wdogConfig->enableWdog = true; - * wdogConfig->workMode.enableWait = true; - * wdogConfig->workMode.enableStop = false; - * wdogConfig->workMode.enableDebug = false; - * wdogConfig->enableInterrupt = false; - * wdogConfig->enablePowerdown = false; - * wdogConfig->resetExtension = flase; - * wdogConfig->timeoutValue = 0xFFU; - * wdogConfig->interruptTimeValue = 0x04u; - * @endcode - * - * @param config Pointer to the WDOG configuration structure. - * @see wdog_config_t - */ -void WDOG_GetDefaultConfig(wdog_config_t *config); - -/*! - * @brief Initializes the WDOG. - * - * This function initializes the WDOG. When called, the WDOG runs according to the configuration. - * - * This is an example. - * @code - * wdog_config_t config; - * WDOG_GetDefaultConfig(&config); - * config.timeoutValue = 0xffU; - * config->interruptTimeValue = 0x04u; - * WDOG_Init(wdog_base,&config); - * @endcode - * - * @param base WDOG peripheral base address - * @param config The configuration of WDOG - */ -void WDOG_Init(WDOG_Type *base, const wdog_config_t *config); - -/*! - * @brief Shuts down the WDOG. - * - * This function shuts down the WDOG. - * Watchdog Enable bit is a write one once only bit. It is not - * possible to clear this bit by a software write, once the bit is set. - * This bit(WDE) can be set/reset only in debug mode(exception). - */ -void WDOG_Deinit(WDOG_Type *base); - -/*! - * @brief Enables the WDOG module. - * - * This function writes a value into the WDOG_WCR register to enable the WDOG. - * This is a write one once only bit. It is not possible to clear this bit by a software write, - * once the bit is set. only debug mode exception. - * @param base WDOG peripheral base address - */ -static inline void WDOG_Enable(WDOG_Type *base) -{ - base->WCR |= WDOG_WCR_WDE_MASK; -} - -/*! - * @brief Disables the WDOG module. - * - * This function writes a value into the WDOG_WCR register to disable the WDOG. - * This is a write one once only bit. It is not possible to clear this bit by a software write,once the bit is set. - * only debug mode exception - * @param base WDOG peripheral base address - */ -static inline void WDOG_Disable(WDOG_Type *base) -{ - base->WCR &= ~WDOG_WCR_WDE_MASK; -} - -/*! - * @brief Enables the WDOG interrupt. - * - *This bit is a write once only bit. Once the software does a write access to this bit, it will get - *locked and cannot be reprogrammed until the next system reset assertion - * - * @param base WDOG peripheral base address - * @param mask The interrupts to enable - * The parameter can be combination of the following source if defined. - * @arg kWDOG_InterruptEnable - */ -static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint16_t mask) -{ - base->WICR |= mask; -} - -/*! - * @brief Gets the WDOG all reset status flags. - * - * This function gets all reset status flags. - * - * @code - * uint16_t status; - * status = WDOG_GetStatusFlags (wdog_base); - * @endcode - * @param base WDOG peripheral base address - * @return State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags - * - true: a related status flag has been set. - * - false: a related status flag is not set. - */ -uint16_t WDOG_GetStatusFlags(WDOG_Type *base); - -/*! - * @brief Clears the WDOG flag. - * - * This function clears the WDOG status flag. - * - * This is an example for clearing the interrupt flag. - * @code - * WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag); - * @endcode - * @param base WDOG peripheral base address - * @param mask The status flags to clear. - * The parameter could be any combination of the following values. - * kWDOG_TimeoutFlag - */ -void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask); - -/*! - * @brief Sets the WDOG timeout value. - * - * This function sets the timeout value. - * This function writes a value into WCR registers. - * The time-out value can be written at any point of time but it is loaded to the counter at the time - * when WDOG is enabled or after the service routine has been performed. - * - * @param base WDOG peripheral base address - * @param timeoutCount WDOG timeout value; count of WDOG clock tick. - */ -static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) -{ - base->WCR = (base->WCR & ~WDOG_WCR_WT_MASK) | WDOG_WCR_WT(timeoutCount); -} - -/*! - * @brief Sets the WDOG interrupt count timeout value. - * - * This function sets the interrupt count timeout value. - * This function writes a value into WIC registers which are wirte-once. - * This field is write once only. Once the software does a write access to this field, it will get locked - * and cannot be reprogrammed until the next system reset assertion. - * @param base WDOG peripheral base address - * @param timeoutCount WDOG timeout value; count of WDOG clock tick. - */ -static inline void WDOG_SetInterrputTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) -{ - base->WICR = (base->WICR & ~WDOG_WICR_WICT_MASK) | WDOG_WICR_WICT(timeoutCount); -} - -/*! - * @brief Disable the WDOG power down enable bit. - * - * This function disable the WDOG power down enable(PDE). - * This function writes a value into WMCR registers which are wirte-once. - * This field is write once only. Once software sets this bit it cannot be reset until the next system reset. - * @param base WDOG peripheral base address - */ -static inline void WDOG_DisablePowerDownEnable(WDOG_Type *base) -{ - base->WMCR &= ~WDOG_WMCR_PDE_MASK; -} - -/*! - * @brief Refreshes the WDOG timer. - * - * This function feeds the WDOG. - * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted. - * - * @param base WDOG peripheral base address - */ -void WDOG_Refresh(WDOG_Type *base); - -/*@}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -#endif /* _FSL_WDOG_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_xbara.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_xbara.c deleted file mode 100644 index 3a8d903565..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_xbara.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xbara.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xbara" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the XBARA instance from peripheral base address. - * - * @param base XBARA peripheral base address. - * @return XBARA instance. - */ -static uint32_t XBARA_GetInstance(XBARA_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Array of XBARA peripheral base address. */ -static XBARA_Type *const s_xbaraBases[] = XBARA_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of XBARA clock name. */ -static const clock_ip_name_t s_xbaraClock[] = XBARA_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t XBARA_GetInstance(XBARA_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_xbaraBases); instance++) - { - if (s_xbaraBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_xbaraBases)); - - return instance; -} - -void XBARA_Init(XBARA_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable XBARA module clock. */ - CLOCK_EnableClock(s_xbaraClock[XBARA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void XBARA_Deinit(XBARA_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable XBARA module clock. */ - CLOCK_DisableClock(s_xbaraClock[XBARA_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xbar_output_signal_t output) -{ - XBARA_WR_SELx_SELx(base, (((uint16_t)input) & 0xFFU), (((uint16_t)output) & 0xFFU)); -} - -uint32_t XBARA_GetStatusFlags(XBARA_Type *base) -{ - uint32_t status_flag; - - status_flag = ((base->CTRL0 & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)) | - ((base->CTRL1 & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK)) << 16U)); - - return status_flag; -} - -void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask) -{ - uint16_t regVal; - - /* Assign regVal to CTRL0 register's value */ - regVal = (base->CTRL0); - /* Perform this command to avoid writing 1 into interrupt flag bits */ - regVal &= (uint16_t)(~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)); - /* Write 1 to interrupt flag bits corresponding to mask */ - regVal |= (uint16_t)(mask & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)); - /* Write regVal value into CTRL0 register */ - base->CTRL0 = regVal; - - /* Assign regVal to CTRL1 register's value */ - regVal = (base->CTRL1); - /* Perform this command to avoid writing 1 into interrupt flag bits */ - regVal &= (uint16_t)(~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK)); - /* Write 1 to interrupt flag bits corresponding to mask */ - regVal |= (uint16_t)((mask >> 16U) & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK)); - /* Write regVal value into CTRL1 register */ - base->CTRL1 = regVal; -} - -void XBARA_SetOutputSignalConfig(XBARA_Type *base, - xbar_output_signal_t output, - const xbara_control_config_t *controlConfig) -{ - uint16_t regVal; - /* Set active edge for edge detection, set interrupt or DMA function. */ - switch ((uint16_t)output) - { -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 - case kXBARA1_OutputDmaChMuxReq30: -#else - case kXBARA_OutputDmamux18: -#endif - /* Assign regVal to CTRL0 register's value */ - regVal = (base->CTRL0); - /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN0, IEN0 */ - regVal &= (uint16_t)( - ~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK | XBARA_CTRL0_DEN0_MASK | XBARA_CTRL0_IEN0_MASK)); - /* Configure edge and request type */ - regVal |= (uint16_t)(XBARA_CTRL0_EDGE0(controlConfig->activeEdge) | - ((controlConfig->requestType) << XBARA_CTRL0_DEN0_SHIFT)); - /* Write regVal value into CTRL0 register */ - base->CTRL0 = regVal; - break; -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 - case kXBARA1_OutputDmaChMuxReq31: -#else - case kXBARA_OutputDmamux19: -#endif - /* Assign regVal to CTRL0 register's value */ - regVal = (base->CTRL0); - /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN1, IEN1 */ - regVal &= (uint16_t)( - ~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK | XBARA_CTRL0_DEN1_MASK | XBARA_CTRL0_IEN1_MASK)); - /* Configure edge and request type */ - regVal |= (uint16_t)(XBARA_CTRL0_EDGE1(controlConfig->activeEdge) | - ((controlConfig->requestType) << XBARA_CTRL0_DEN1_SHIFT)); - /* Write regVal value into CTRL0 register */ - base->CTRL0 = regVal; - break; -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 - case kXBARA1_OutputDmaChMuxReq94: -#else - case kXBARA_OutputDmamux20: -#endif - /* Assign regVal to CTRL1 register's value */ - regVal = (base->CTRL1); - /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN2, IEN2 */ - regVal &= (uint16_t)( - ~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK | XBARA_CTRL1_DEN2_MASK | XBARA_CTRL1_IEN2_MASK)); - /* Configure edge and request type */ - regVal |= (uint16_t)(XBARA_CTRL1_EDGE2(controlConfig->activeEdge) | - ((controlConfig->requestType) << XBARA_CTRL1_DEN2_SHIFT)); - /* Write regVal value into CTRL1 register */ - base->CTRL1 = regVal; - break; -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 - case kXBARA1_OutputDmaChMuxReq95: -#else - case kXBARA_OutputDmamux21: -#endif - /* Assign regVal to CTRL1 register's value */ - regVal = (base->CTRL1); - /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN3, IEN3 */ - regVal &= (uint16_t)( - ~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK | XBARA_CTRL1_DEN3_MASK | XBARA_CTRL1_IEN3_MASK)); - /* Configure edge and request type */ - regVal |= (uint16_t)(XBARA_CTRL1_EDGE3(controlConfig->activeEdge) | - ((controlConfig->requestType) << XBARA_CTRL1_DEN3_SHIFT)); - /* Write regVal value into CTRL1 register */ - base->CTRL1 = regVal; - break; - default: - break; - } -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_xbara.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_xbara.h deleted file mode 100644 index 98410a198b..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_xbara.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_XBARA_H_ -#define _FSL_XBARA_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup xbara - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define FSL_XBARA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */ - -/* Macros for entire XBARA_SELx register. */ -#define XBARA_SELx(base, output) (*(volatile uint16_t *)((uintptr_t) & (base->SEL0) + ((output) / 2U) * 2U)) -/* Set the XBARA_SELx_SELx field to a new value. */ -#define XBARA_WR_SELx_SELx(base, input, output) \ - (XBARA_SELx((base), (output)) = \ - ((XBARA_SELx((base), (output)) & ~(0xFFU << (XBARA_SEL0_SEL1_SHIFT * ((output) % 2U)))) | \ - ((input) << (XBARA_SEL0_SEL1_SHIFT * ((output) % 2U))))) - -/*! - * @brief XBARA active edge for detection - */ -typedef enum _xbara_active_edge -{ - kXBARA_EdgeNone = 0U, /*!< Edge detection status bit never asserts. */ - kXBARA_EdgeRising = 1U, /*!< Edge detection status bit asserts on rising edges. */ - kXBARA_EdgeFalling = 2U, /*!< Edge detection status bit asserts on falling edges. */ - kXBARA_EdgeRisingAndFalling = 3U /*!< Edge detection status bit asserts on rising and falling edges. */ -} xbara_active_edge_t; - -/*! - * @brief Defines the XBARA DMA and interrupt configurations. - */ -typedef enum _xbar_request -{ - kXBARA_RequestDisable = 0U, /*!< Interrupt and DMA are disabled. */ - kXBARA_RequestDMAEnable = 1U, /*!< DMA enabled, interrupt disabled. */ - kXBARA_RequestInterruptEnalbe = 2U /*!< Interrupt enabled, DMA disabled. */ -} xbara_request_t; - -/*! - * @brief XBARA status flags. - * - * This provides constants for the XBARA status flags for use in the XBARA functions. - */ -typedef enum _xbara_status_flag_t -{ - kXBARA_EdgeDetectionOut0 = - (XBARA_CTRL0_STS0_MASK), /*!< XBAR_OUT0 active edge interrupt flag, sets when active edge detected. */ - kXBARA_EdgeDetectionOut1 = - (XBARA_CTRL0_STS1_MASK), /*!< XBAR_OUT1 active edge interrupt flag, sets when active edge detected. */ - kXBARA_EdgeDetectionOut2 = - (XBARA_CTRL1_STS2_MASK << 16U), /*!< XBAR_OUT2 active edge interrupt flag, sets when active edge detected. */ - kXBARA_EdgeDetectionOut3 = - (XBARA_CTRL1_STS3_MASK << 16U), /*!< XBAR_OUT3 active edge interrupt flag, sets when active edge detected. */ -} xbara_status_flag_t; - -/*! - * @brief Defines the configuration structure of the XBARA control register. - * - * This structure keeps the configuration of XBARA control register for one output. - * Control registers are available only for a few outputs. Not every XBARA module has - * control registers. - */ -typedef struct XBARAControlConfig -{ - xbara_active_edge_t activeEdge; /*!< Active edge to be detected. */ - xbara_request_t requestType; /*!< Selects DMA/Interrupt request. */ -} xbara_control_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name XBARA functional Operation. - * @{ - */ - -/*! - * @brief Initializes the XBARA module. - * - * This function un-gates the XBARA clock. - * - * @param base XBARA peripheral address. - */ -void XBARA_Init(XBARA_Type *base); - -/*! - * @brief Shuts down the XBARA module. - * - * This function disables XBARA clock. - * - * @param base XBARA peripheral address. - */ -void XBARA_Deinit(XBARA_Type *base); - -/*! - * @brief Sets a connection between the selected XBARA_IN[*] input and the XBARA_OUT[*] output signal. - * - * This function connects the XBARA input to the selected XBARA output. - * If more than one XBARA module is available, only the inputs and outputs from the same module - * can be connected. - * - * Example: - @code - XBARA_SetSignalsConnection(XBARA, kXBARA_InputPIT_TRG0, kXBARA_OutputDMAMUX18); - @endcode - * - * @param base XBARA peripheral address. - * @param input XBARA input signal. - * @param output XBARA output signal. - */ -void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xbar_output_signal_t output); - -/*! - * @brief Gets the active edge detection status. - * - * This function gets the active edge detect status of all XBARA_OUTs. If the - * active edge occurs, the return value is asserted. When the interrupt or the DMA - * functionality is enabled for the XBARA_OUTx, this field is 1 when the interrupt - * or DMA request is asserted and 0 when the interrupt or DMA request has been - * cleared. - * - * @param base XBARA peripheral address. - * @return the mask of these status flag bits. - */ -uint32_t XBARA_GetStatusFlags(XBARA_Type *base); - -/*! - * @brief Clears the edge detection status flags of relative mask. - * - * @param base XBARA peripheral address. - * @param mask the status flags to clear. - */ -void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask); - -/*! - * @brief Configures the XBARA control register. - * - * This function configures an XBARA control register. The active edge detection - * and the DMA/IRQ function on the corresponding XBARA output can be set. - * - * Example: - @code - xbara_control_config_t userConfig; - userConfig.activeEdge = kXBARA_EdgeRising; - userConfig.requestType = kXBARA_RequestInterruptEnalbe; - XBARA_SetOutputSignalConfig(XBARA, kXBARA_OutputDMAMUX18, &userConfig); - @endcode - * - * @param base XBARA peripheral address. - * @param output XBARA output number. - * @param controlConfig Pointer to structure that keeps configuration of control register. - */ -void XBARA_SetOutputSignalConfig(XBARA_Type *base, - xbar_output_signal_t output, - const xbara_control_config_t *controlConfig); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -/*!* @} */ - -#endif /* _FSL_XBARA_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_xbarb.c b/bsp/imxrt1052-evk/Libraries/drivers/fsl_xbarb.c deleted file mode 100644 index 627b0ab91f..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_xbarb.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_xbarb.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xbarb" -#endif - - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the XBARB instance from peripheral base address. - * - * @param base XBARB peripheral base address. - * @return XBARB instance. - */ -static uint32_t XBARB_GetInstance(XBARB_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Array of XBARB peripheral base address. */ -static XBARB_Type *const s_xbarbBases[] = XBARB_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/* Array of XBARB clock name. */ -static const clock_ip_name_t s_xbarbClock[] = XBARB_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t XBARB_GetInstance(XBARB_Type *base) -{ - uint32_t instance; - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ARRAY_SIZE(s_xbarbBases); instance++) - { - if (s_xbarbBases[instance] == base) - { - break; - } - } - - assert(instance < ARRAY_SIZE(s_xbarbBases)); - - return instance; -} - -void XBARB_Init(XBARB_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable XBARB module clock. */ - CLOCK_EnableClock(s_xbarbClock[XBARB_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void XBARB_Deinit(XBARB_Type *base) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable XBARB module clock. */ - CLOCK_DisableClock(s_xbarbClock[XBARB_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -void XBARB_SetSignalsConnection(XBARB_Type *base, xbar_input_signal_t input, xbar_output_signal_t output) -{ - XBARB_WR_SELx_SELx(base, (((uint16_t)input) & 0xFFU), (((uint16_t)output) & 0xFFU)); -} diff --git a/bsp/imxrt1052-evk/Libraries/drivers/fsl_xbarb.h b/bsp/imxrt1052-evk/Libraries/drivers/fsl_xbarb.h deleted file mode 100644 index 38e687fb06..0000000000 --- a/bsp/imxrt1052-evk/Libraries/drivers/fsl_xbarb.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_XBARB_H_ -#define _FSL_XBARB_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup xbarb - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define FSL_XBARB_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ - -/* Macros for entire XBARB_SELx register. */ -#define XBARB_SELx(base, output) (*(volatile uint16_t *)((uintptr_t) & (base->SEL0) + ((output) / 2U) * 2U)) -/* Set the SELx field to a new value. */ -#define XBARB_WR_SELx_SELx(base, input, output) \ - (XBARB_SELx((base), (output)) = \ - ((XBARB_SELx((base), (output)) & ~(0xFFU << (XBARB_SEL0_SEL1_SHIFT * ((output) % 2U)))) | \ - ((input) << (XBARB_SEL0_SEL1_SHIFT * ((output) % 2U))))) - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @name XBARB functional Operation. - * @{ - */ - -/*! - * @brief Initializes the XBARB module. - * - * This function un-gates the XBARB clock. - * - * @param base XBARB peripheral address. - */ -void XBARB_Init(XBARB_Type *base); - -/*! - * @brief Shuts down the XBARB module. - * - * This function disables XBARB clock. - * - * @param base XBARB peripheral address. - */ -void XBARB_Deinit(XBARB_Type *base); - -/*! - * @brief Configures a connection between the selected XBARB_IN[*] input and the XBARB_OUT[*] output signal. - * - * This function configures which XBARB input is connected to the selected XBARB output. - * If more than one XBARB module is available, only the inputs and outputs from the same module - * can be connected. - * - * @param base XBARB peripheral address. - * @param input XBARB input signal. - * @param output XBARB output signal. - */ -void XBARB_SetSignalsConnection(XBARB_Type *base, xbar_input_signal_t input, xbar_output_signal_t output); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @}*/ - -/*!* @} */ - -#endif /* _FSL_XBARB_H_ */ diff --git a/bsp/imxrt1052-evk/Libraries/fsl_device_registers.h b/bsp/imxrt1052-evk/Libraries/fsl_device_registers.h deleted file mode 100644 index f546a9df0e..0000000000 --- a/bsp/imxrt1052-evk/Libraries/fsl_device_registers.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_MIMXRT1052CVJ5B) || defined(CPU_MIMXRT1052CVL5B) || defined(CPU_MIMXRT1052DVJ6B) || \ - defined(CPU_MIMXRT1052DVL6B)) - -#define MIMXRT1052_SERIES - -/* CMSIS-style register definitions */ -#include "MIMXRT1052.h" -/* CPU specific feature definitions */ -#include "MIMXRT1052_features.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld b/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld deleted file mode 100644 index b8c229ae3c..0000000000 --- a/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld +++ /dev/null @@ -1,276 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: GNU C Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; - -/* Specify the memory areas */ -MEMORY -{ - m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 - m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 - - m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 - m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00 - - m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000 - m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 - m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 - - m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 - m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 -} - -/* Define output sections */ -SECTIONS -{ - .boot_data : - { - KEEP(*(.boot_hdr.conf)) - } > m_boot_data - - .image_vertor_table : - { - KEEP(*(.boot_hdr.ivt)) - KEEP(*(.boot_hdr.boot_data)) - KEEP(*(.boot_hdr.dcd_data)) - } > m_image_vertor_table - - /* The startup code goes first into internal RAM */ - .interrupts : - { - __VECTOR_TABLE = .; - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - __VECTOR_RAM = __VECTOR_TABLE; - __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; - - /* The program code and other data goes into internal RAM */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - PROVIDE(__ctors_start__ = .); - /* __CTOR_LIST__ = .; */ - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - /* __CTOR_END__ = .; */ - PROVIDE(__ctors_end__ = .); - } > m_text - - .dtors : - { - PROVIDE(__dtors_start__ = .); - /* __DTOR_LIST__ = .; */ - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* __DTOR_END__ = .; */ - PROVIDE(__dtors_end__ = .); - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(m_usb_dma_init_data) - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_dtcm - - __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); - .ncache.init : AT(__NDATA_ROM) - { - __noncachedata_start__ = .; /* create a global symbol at ncache data start */ - *(NonCacheable.init) - . = ALIGN(4); - __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ - } > m_nocache - . = __noncachedata_init_end__; - .ncache : - { - *(NonCacheable) - . = ALIGN(4); - __noncachedata_end__ = .; /* define a global symbol at ncache data end */ - } > m_nocache - - __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(m_usb_dma_noninit_data) - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_dtcm - - .stack : - { - . = ALIGN(8); - stack_start = .; - . += STACK_SIZE; - stack_end = .; - __StackTop = .; - } > m_dtcm - - .RTT_HEAP : - { - heap_start = .; - . = ALIGN(8); - } > m_dtcm - - PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm)); - - .ARM.attributes 0 : { *(.ARM.attributes) } - -} - diff --git a/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_ram.ld b/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_ram.ld deleted file mode 100644 index 9077f044ed..0000000000 --- a/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_ram.ld +++ /dev/null @@ -1,256 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: GNU C Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x00020000 - - /* m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000 */ - m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 - /* m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 */ - - /* m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 */ - /* m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 */ -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal RAM */ - .interrupts : - { - __VECTOR_TABLE = .; - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - __VECTOR_RAM = __VECTOR_TABLE; - __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; - - /* The program code and other data goes into internal RAM */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - PROVIDE(__ctors_start__ = .); - /* __CTOR_LIST__ = .; */ - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - /* __CTOR_END__ = .; */ - PROVIDE(__ctors_end__ = .); - } > m_text - - .dtors : - { - PROVIDE(__dtors_start__ = .); - /* __DTOR_LIST__ = .; */ - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* __DTOR_END__ = .; */ - PROVIDE(__dtors_end__ = .); - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(m_usb_dma_init_data) - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_dtcm - - __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); - .ncache.init : AT(__NDATA_ROM) - { - __noncachedata_start__ = .; /* create a global symbol at ncache data start */ - *(NonCacheable.init) - . = ALIGN(4); - __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ - } > m_dtcm - . = __noncachedata_init_end__; - .ncache : - { - *(NonCacheable) - . = ALIGN(4); - __noncachedata_end__ = .; /* define a global symbol at ncache data end */ - } > m_dtcm - - __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(m_usb_dma_noninit_data) - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_dtcm - - .stack : - { - . = ALIGN(8); - stack_start = .; - . += STACK_SIZE; - stack_end = .; - heap_start = .; - } > m_dtcm - - /* Initializes stack on the end of block */ - __StackTop = stack_end; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - diff --git a/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_sdram.ld b/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_sdram.ld deleted file mode 100644 index 100e6ed9f2..0000000000 --- a/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_sdram.ld +++ /dev/null @@ -1,245 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: GNU C Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00 - m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 - m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal RAM */ - .interrupts : - { - __VECTOR_TABLE = .; - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - __VECTOR_RAM = __VECTOR_TABLE; - __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; - - /* The program code and other data goes into internal RAM */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - PROVIDE(__ctors_start__ = .); - /* __CTOR_LIST__ = .; */ - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - /* __CTOR_END__ = .; */ - PROVIDE(__ctors_end__ = .); - } > m_text - - .dtors : - { - PROVIDE(__dtors_start__ = .); - /* __DTOR_LIST__ = .; */ - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* __DTOR_END__ = .; */ - PROVIDE(__dtors_end__ = .); - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(m_usb_dma_init_data) - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); - .ncache.init : AT(__NDATA_ROM) - { - __noncachedata_start__ = .; /* create a global symbol at ncache data start */ - *(NonCacheable.init) - . = ALIGN(4); - __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ - } > m_ncache - . = __noncachedata_init_end__; - .ncache : - { - *(NonCacheable) - . = ALIGN(4); - __noncachedata_end__ = .; /* define a global symbol at ncache data end */ - } > m_ncache - - __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(m_usb_dma_noninit_data) - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_sdram_txt.ld b/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_sdram_txt.ld deleted file mode 100644 index 9206f67501..0000000000 --- a/bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_sdram_txt.ld +++ /dev/null @@ -1,245 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: GNU C Compiler -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; - -/* Specify the memory areas */ -MEMORY -{ - m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000400 - m_text (RX) : ORIGIN = 0x80000400, LENGTH = 0x001FFC00 - m_data (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 - m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into internal RAM */ - .interrupts : - { - __VECTOR_TABLE = .; - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - __VECTOR_RAM = __VECTOR_TABLE; - __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; - - /* The program code and other data goes into internal RAM */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - PROVIDE(__ctors_start__ = .); - /* __CTOR_LIST__ = .; */ - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - /* __CTOR_END__ = .; */ - PROVIDE(__ctors_end__ = .); - } > m_text - - .dtors : - { - PROVIDE(__dtors_start__ = .); - /* __DTOR_LIST__ = .; */ - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* __DTOR_END__ = .; */ - PROVIDE(__dtors_end__ = .); - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(m_usb_dma_init_data) - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); - .ncache.init : AT(__NDATA_ROM) - { - __noncachedata_start__ = .; /* create a global symbol at ncache data start */ - *(NonCacheable.init) - . = ALIGN(4); - __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ - } > m_ncache - . = __noncachedata_init_end__; - .ncache : - { - *(NonCacheable) - . = ALIGN(4); - __noncachedata_end__ = .; /* define a global symbol at ncache data end */ - } > m_ncache - - __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(m_usb_dma_noninit_data) - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} - diff --git a/bsp/imxrt1052-evk/Libraries/gcc/startup_MIMXRT1052.S b/bsp/imxrt1052-evk/Libraries/gcc/startup_MIMXRT1052.S deleted file mode 100644 index d6df9135b9..0000000000 --- a/bsp/imxrt1052-evk/Libraries/gcc/startup_MIMXRT1052.S +++ /dev/null @@ -1,1090 +0,0 @@ -/* ---------------------------------------------------------------------------------------*/ -/* @file: startup_MIMXRT1052.s */ -/* @purpose: CMSIS Cortex-M7 Core Device Startup File */ -/* MIMXRT1052 */ -/* @version: 0.1 */ -/* @date: 2017-1-10 */ -/* @build: b170927 */ -/* ---------------------------------------------------------------------------------------*/ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2017 NXP */ -/* Redistribution and use in source and binary forms, with or without modification, */ -/* are permitted provided that the following conditions are met: */ -/* */ -/* 1. Redistributions of source code must retain the above copyright notice, this list */ -/* of conditions and the following disclaimer. */ -/* */ -/* 2. Redistributions in binary form must reproduce the above copyright notice, this */ -/* list of conditions and the following disclaimer in the documentation and/or */ -/* other materials provided with the distribution. */ -/* */ -/* 3. Neither the name of the copyright holder nor the names of its */ -/* contributors may be used to endorse or promote products derived from this */ -/* software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ -/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ -/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ -/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ -/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ -/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ -/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ -/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ -/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ -/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - -#define __STARTUP_INITIALIZE_NONCACHEDATA -#define __STARTUP_CLEAR_BSS - - .syntax unified - .arch armv7-m - - .section .isr_vector, "a" - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long DMA0_DMA16_IRQHandler /* DMA channel 0/16 transfer complete*/ - .long DMA1_DMA17_IRQHandler /* DMA channel 1/17 transfer complete*/ - .long DMA2_DMA18_IRQHandler /* DMA channel 2/18 transfer complete*/ - .long DMA3_DMA19_IRQHandler /* DMA channel 3/19 transfer complete*/ - .long DMA4_DMA20_IRQHandler /* DMA channel 4/20 transfer complete*/ - .long DMA5_DMA21_IRQHandler /* DMA channel 5/21 transfer complete*/ - .long DMA6_DMA22_IRQHandler /* DMA channel 6/22 transfer complete*/ - .long DMA7_DMA23_IRQHandler /* DMA channel 7/23 transfer complete*/ - .long DMA8_DMA24_IRQHandler /* DMA channel 8/24 transfer complete*/ - .long DMA9_DMA25_IRQHandler /* DMA channel 9/25 transfer complete*/ - .long DMA10_DMA26_IRQHandler /* DMA channel 10/26 transfer complete*/ - .long DMA11_DMA27_IRQHandler /* DMA channel 11/27 transfer complete*/ - .long DMA12_DMA28_IRQHandler /* DMA channel 12/28 transfer complete*/ - .long DMA13_DMA29_IRQHandler /* DMA channel 13/29 transfer complete*/ - .long DMA14_DMA30_IRQHandler /* DMA channel 14/30 transfer complete*/ - .long DMA15_DMA31_IRQHandler /* DMA channel 15/31 transfer complete*/ - .long DMA_ERROR_IRQHandler /* DMA error interrupt channels 0-15 / 16-31*/ - .long CTI0_ERROR_IRQHandler /* CTI0_Error*/ - .long CTI1_ERROR_IRQHandler /* CTI1_Error*/ - .long CORE_IRQHandler /* CorePlatform exception IRQ*/ - .long LPUART1_IRQHandler /* LPUART1 TX interrupt and RX interrupt*/ - .long LPUART2_IRQHandler /* LPUART2 TX interrupt and RX interrupt*/ - .long LPUART3_IRQHandler /* LPUART3 TX interrupt and RX interrupt*/ - .long LPUART4_IRQHandler /* LPUART4 TX interrupt and RX interrupt*/ - .long LPUART5_IRQHandler /* LPUART5 TX interrupt and RX interrupt*/ - .long LPUART6_IRQHandler /* LPUART6 TX interrupt and RX interrupt*/ - .long LPUART7_IRQHandler /* LPUART7 TX interrupt and RX interrupt*/ - .long LPUART8_IRQHandler /* LPUART8 TX interrupt and RX interrupt*/ - .long LPI2C1_IRQHandler /* LPI2C1 interrupt*/ - .long LPI2C2_IRQHandler /* LPI2C2 interrupt*/ - .long LPI2C3_IRQHandler /* LPI2C3 interrupt*/ - .long LPI2C4_IRQHandler /* LPI2C4 interrupt*/ - .long LPSPI1_IRQHandler /* LPSPI1 single interrupt vector for all sources*/ - .long LPSPI2_IRQHandler /* LPSPI2 single interrupt vector for all sources*/ - .long LPSPI3_IRQHandler /* LPSPI3 single interrupt vector for all sources*/ - .long LPSPI4_IRQHandler /* LPSPI4 single interrupt vector for all sources*/ - .long CAN1_IRQHandler /* CAN1 interrupt*/ - .long CAN2_IRQHandler /* CAN2 interrupt*/ - .long FLEXRAM_IRQHandler /* FlexRAM address out of range Or access hit IRQ*/ - .long KPP_IRQHandler /* Keypad nterrupt*/ - .long TSC_DIG_IRQHandler /* TSC interrupt*/ - .long GPR_IRQ_IRQHandler /* GPR interrupt*/ - .long LCDIF_IRQHandler /* LCDIF interrupt*/ - .long CSI_IRQHandler /* CSI interrupt*/ - .long PXP_IRQHandler /* PXP interrupt*/ - .long WDOG2_IRQHandler /* WDOG2 interrupt*/ - .long SNVS_HP_WRAPPER_IRQHandler /* SRTC Consolidated Interrupt. Non TZ*/ - .long SNVS_HP_WRAPPER_TZ_IRQHandler /* SRTC Security Interrupt. TZ*/ - .long SNVS_LP_WRAPPER_IRQHandler /* ON-OFF button press shorter than 5 secs (pulse event)*/ - .long CSU_IRQHandler /* CSU interrupt*/ - .long DCP_IRQHandler /* DCP_IRQ interrupt*/ - .long DCP_VMI_IRQHandler /* DCP_VMI_IRQ interrupt*/ - .long Reserved68_IRQHandler /* Reserved interrupt*/ - .long TRNG_IRQHandler /* TRNG interrupt*/ - .long SJC_IRQHandler /* SJC interrupt*/ - .long BEE_IRQHandler /* BEE interrupt*/ - .long SAI1_IRQHandler /* SAI1 interrupt*/ - .long SAI2_IRQHandler /* SAI1 interrupt*/ - .long SAI3_RX_IRQHandler /* SAI3 interrupt*/ - .long SAI3_TX_IRQHandler /* SAI3 interrupt*/ - .long SPDIF_IRQHandler /* SPDIF interrupt*/ - .long ANATOP_EVENT0_IRQHandler /* ANATOP interrupt*/ - .long ANATOP_EVENT1_IRQHandler /* ANATOP interrupt*/ - .long ANATOP_TAMP_LOW_HIGH_IRQHandler /* ANATOP interrupt*/ - .long ANATOP_TEMP_PANIC_IRQHandler /* ANATOP interrupt*/ - .long USB_PHY1_IRQHandler /* USBPHY (UTMI0), Interrupt*/ - .long USB_PHY2_IRQHandler /* USBPHY (UTMI0), Interrupt*/ - .long ADC1_IRQHandler /* ADC1 interrupt*/ - .long ADC2_IRQHandler /* ADC2 interrupt*/ - .long DCDC_IRQHandler /* DCDC interrupt*/ - .long Reserved86_IRQHandler /* Reserved interrupt*/ - .long Reserved87_IRQHandler /* Reserved interrupt*/ - .long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/ - .long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/ - .long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/ - .long GPIO1_INT3_IRQHandler /* Active HIGH Interrupt from INT3 from GPIO*/ - .long GPIO1_INT4_IRQHandler /* Active HIGH Interrupt from INT4 from GPIO*/ - .long GPIO1_INT5_IRQHandler /* Active HIGH Interrupt from INT5 from GPIO*/ - .long GPIO1_INT6_IRQHandler /* Active HIGH Interrupt from INT6 from GPIO*/ - .long GPIO1_INT7_IRQHandler /* Active HIGH Interrupt from INT7 from GPIO*/ - .long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/ - .long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/ - .long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/ - .long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/ - .long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/ - .long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/ - .long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/ - .long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/ - .long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/ - .long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/ - .long FLEXIO1_IRQHandler /* FLEXIO1 interrupt*/ - .long FLEXIO2_IRQHandler /* FLEXIO2 interrupt*/ - .long WDOG1_IRQHandler /* WDOG1 interrupt*/ - .long RTWDOG_IRQHandler /* RTWDOG interrupt*/ - .long EWM_IRQHandler /* EWM interrupt*/ - .long CCM_1_IRQHandler /* CCM IRQ1 interrupt*/ - .long CCM_2_IRQHandler /* CCM IRQ2 interrupt*/ - .long GPC_IRQHandler /* GPC interrupt*/ - .long SRC_IRQHandler /* SRC interrupt*/ - .long Reserved115_IRQHandler /* Reserved interrupt*/ - .long GPT1_IRQHandler /* GPT1 interrupt*/ - .long GPT2_IRQHandler /* GPT2 interrupt*/ - .long PWM1_0_IRQHandler /* PWM1 capture 0, compare 0, or reload 0 interrupt*/ - .long PWM1_1_IRQHandler /* PWM1 capture 1, compare 1, or reload 0 interrupt*/ - .long PWM1_2_IRQHandler /* PWM1 capture 2, compare 2, or reload 0 interrupt*/ - .long PWM1_3_IRQHandler /* PWM1 capture 3, compare 3, or reload 0 interrupt*/ - .long PWM1_FAULT_IRQHandler /* PWM1 fault or reload error interrupt*/ - .long Reserved123_IRQHandler /* Reserved interrupt*/ - .long FLEXSPI_IRQHandler /* FlexSPI0 interrupt*/ - .long SEMC_IRQHandler /* Reserved interrupt*/ - .long USDHC1_IRQHandler /* USDHC1 interrupt*/ - .long USDHC2_IRQHandler /* USDHC2 interrupt*/ - .long USB_OTG2_IRQHandler /* USBO2 USB OTG2*/ - .long USB_OTG1_IRQHandler /* USBO2 USB OTG1*/ - .long ENET_IRQHandler /* ENET interrupt*/ - .long ENET_1588_Timer_IRQHandler /* ENET_1588_Timer interrupt*/ - .long XBAR1_IRQ_0_1_IRQHandler /* XBAR1 interrupt*/ - .long XBAR1_IRQ_2_3_IRQHandler /* XBAR1 interrupt*/ - .long ADC_ETC_IRQ0_IRQHandler /* ADCETC IRQ0 interrupt*/ - .long ADC_ETC_IRQ1_IRQHandler /* ADCETC IRQ1 interrupt*/ - .long ADC_ETC_IRQ2_IRQHandler /* ADCETC IRQ2 interrupt*/ - .long ADC_ETC_ERROR_IRQ_IRQHandler /* ADCETC Error IRQ interrupt*/ - .long PIT_IRQHandler /* PIT interrupt*/ - .long ACMP1_IRQHandler /* ACMP interrupt*/ - .long ACMP2_IRQHandler /* ACMP interrupt*/ - .long ACMP3_IRQHandler /* ACMP interrupt*/ - .long ACMP4_IRQHandler /* ACMP interrupt*/ - .long Reserved143_IRQHandler /* Reserved interrupt*/ - .long Reserved144_IRQHandler /* Reserved interrupt*/ - .long ENC1_IRQHandler /* ENC1 interrupt*/ - .long ENC2_IRQHandler /* ENC2 interrupt*/ - .long ENC3_IRQHandler /* ENC3 interrupt*/ - .long ENC4_IRQHandler /* ENC4 interrupt*/ - .long TMR1_IRQHandler /* TMR1 interrupt*/ - .long TMR2_IRQHandler /* TMR2 interrupt*/ - .long TMR3_IRQHandler /* TMR3 interrupt*/ - .long TMR4_IRQHandler /* TMR4 interrupt*/ - .long PWM2_0_IRQHandler /* PWM2 capture 0, compare 0, or reload 0 interrupt*/ - .long PWM2_1_IRQHandler /* PWM2 capture 1, compare 1, or reload 0 interrupt*/ - .long PWM2_2_IRQHandler /* PWM2 capture 2, compare 2, or reload 0 interrupt*/ - .long PWM2_3_IRQHandler /* PWM2 capture 3, compare 3, or reload 0 interrupt*/ - .long PWM2_FAULT_IRQHandler /* PWM2 fault or reload error interrupt*/ - .long PWM3_0_IRQHandler /* PWM3 capture 0, compare 0, or reload 0 interrupt*/ - .long PWM3_1_IRQHandler /* PWM3 capture 1, compare 1, or reload 0 interrupt*/ - .long PWM3_2_IRQHandler /* PWM3 capture 2, compare 2, or reload 0 interrupt*/ - .long PWM3_3_IRQHandler /* PWM3 capture 3, compare 3, or reload 0 interrupt*/ - .long PWM3_FAULT_IRQHandler /* PWM3 fault or reload error interrupt*/ - .long PWM4_0_IRQHandler /* PWM4 capture 0, compare 0, or reload 0 interrupt*/ - .long PWM4_1_IRQHandler /* PWM4 capture 1, compare 1, or reload 0 interrupt*/ - .long PWM4_2_IRQHandler /* PWM4 capture 2, compare 2, or reload 0 interrupt*/ - .long PWM4_3_IRQHandler /* PWM4 capture 3, compare 3, or reload 0 interrupt*/ - .long PWM4_FAULT_IRQHandler /* PWM4 fault or reload error interrupt*/ - .long Reserved168_IRQHandler /* Reserved interrupt*/ - .long Reserved169_IRQHandler /* Reserved interrupt*/ - .long Reserved170_IRQHandler /* Reserved interrupt*/ - .long Reserved171_IRQHandler /* Reserved interrupt*/ - .long Reserved172_IRQHandler /* Reserved interrupt*/ - .long Reserved173_IRQHandler /* Reserved interrupt*/ - .long SJC_ARM_DEBUG_IRQHandler /* SJC ARM debug interrupt*/ - .long NMI_WAKEUP_IRQHandler /* NMI wake up*/ - .long DefaultISR /* 176*/ - .long DefaultISR /* 177*/ - .long DefaultISR /* 178*/ - .long DefaultISR /* 179*/ - .long DefaultISR /* 180*/ - .long DefaultISR /* 181*/ - .long DefaultISR /* 182*/ - .long DefaultISR /* 183*/ - .long DefaultISR /* 184*/ - .long DefaultISR /* 185*/ - .long DefaultISR /* 186*/ - .long DefaultISR /* 187*/ - .long DefaultISR /* 188*/ - .long DefaultISR /* 189*/ - .long DefaultISR /* 190*/ - .long DefaultISR /* 191*/ - .long DefaultISR /* 192*/ - .long DefaultISR /* 193*/ - .long DefaultISR /* 194*/ - .long DefaultISR /* 195*/ - .long DefaultISR /* 196*/ - .long DefaultISR /* 197*/ - .long DefaultISR /* 198*/ - .long DefaultISR /* 199*/ - .long DefaultISR /* 200*/ - .long DefaultISR /* 201*/ - .long DefaultISR /* 202*/ - .long DefaultISR /* 203*/ - .long DefaultISR /* 204*/ - .long DefaultISR /* 205*/ - .long DefaultISR /* 206*/ - .long DefaultISR /* 207*/ - .long DefaultISR /* 208*/ - .long DefaultISR /* 209*/ - .long DefaultISR /* 210*/ - .long DefaultISR /* 211*/ - .long DefaultISR /* 212*/ - .long DefaultISR /* 213*/ - .long DefaultISR /* 214*/ - .long DefaultISR /* 215*/ - .long DefaultISR /* 216*/ - .long DefaultISR /* 217*/ - .long DefaultISR /* 218*/ - .long DefaultISR /* 219*/ - .long DefaultISR /* 220*/ - .long DefaultISR /* 221*/ - .long DefaultISR /* 222*/ - .long DefaultISR /* 223*/ - .long DefaultISR /* 224*/ - .long DefaultISR /* 225*/ - .long DefaultISR /* 226*/ - .long DefaultISR /* 227*/ - .long DefaultISR /* 228*/ - .long DefaultISR /* 229*/ - .long DefaultISR /* 230*/ - .long DefaultISR /* 231*/ - .long DefaultISR /* 232*/ - .long DefaultISR /* 233*/ - .long DefaultISR /* 234*/ - .long DefaultISR /* 235*/ - .long DefaultISR /* 236*/ - .long DefaultISR /* 237*/ - .long DefaultISR /* 238*/ - .long DefaultISR /* 239*/ - .long DefaultISR /* 240*/ - .long DefaultISR /* 241*/ - .long DefaultISR /* 242*/ - .long DefaultISR /* 243*/ - .long DefaultISR /* 244*/ - .long DefaultISR /* 245*/ - .long DefaultISR /* 246*/ - .long DefaultISR /* 247*/ - .long DefaultISR /* 248*/ - .long DefaultISR /* 249*/ - .long DefaultISR /* 250*/ - .long DefaultISR /* 251*/ - .long DefaultISR /* 252*/ - .long DefaultISR /* 253*/ - .long DefaultISR /* 254*/ - .long 0xFFFFFFFF /* Reserved for user TRIM value*/ - - .size __isr_vector, . - __isr_vector - - .text - .thumb - -/* Reset Handler */ - - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__isr_vector - str r1, [r0] - ldr r2, [r1] - msr msp, r2 -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * __noncachedata_start__/__noncachedata_end__ : none cachable region - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: -#endif -#ifdef __STARTUP_INITIALIZE_NONCACHEDATA - ldr r2, =__noncachedata_start__ - ldr r3, =__noncachedata_init_end__ -#if 1 -.LC2: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC2 -#else - subs r3, r2 - ble .LC3 -.LC2: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC2 -.LC3: -#endif -/* zero inited ncache section initialization */ - ldr r3, =__noncachedata_end__ - movs r0,0 -.LC4: - cmp r2,r3 - itt lt - strlt r0,[r2],#4 - blt .LC4 -#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */ - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC5: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC5 -#endif /* __STARTUP_CLEAR_BSS */ - - cpsie i /* Unmask interrupts */ -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - ldr r0,=entry - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak NMI_WAKEUP_IRQHandler - .type NMI_WAKEUP_IRQHandler, %function -NMI_WAKEUP_IRQHandler: - ldr r0,=NMI_WAKEUP_IRQHandler - bx r0 - .size NMI_WAKEUP_IRQHandler, . - NMI_WAKEUP_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_DMA16_IRQHandler - .type DMA0_DMA16_IRQHandler, %function -DMA0_DMA16_IRQHandler: - ldr r0,=DMA0_DMA16_DriverIRQHandler - bx r0 - .size DMA0_DMA16_IRQHandler, . - DMA0_DMA16_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_DMA17_IRQHandler - .type DMA1_DMA17_IRQHandler, %function -DMA1_DMA17_IRQHandler: - ldr r0,=DMA1_DMA17_DriverIRQHandler - bx r0 - .size DMA1_DMA17_IRQHandler, . - DMA1_DMA17_IRQHandler - - .align 1 - .thumb_func - .weak DMA2_DMA18_IRQHandler - .type DMA2_DMA18_IRQHandler, %function -DMA2_DMA18_IRQHandler: - ldr r0,=DMA2_DMA18_DriverIRQHandler - bx r0 - .size DMA2_DMA18_IRQHandler, . - DMA2_DMA18_IRQHandler - - .align 1 - .thumb_func - .weak DMA3_DMA19_IRQHandler - .type DMA3_DMA19_IRQHandler, %function -DMA3_DMA19_IRQHandler: - ldr r0,=DMA3_DMA19_DriverIRQHandler - bx r0 - .size DMA3_DMA19_IRQHandler, . - DMA3_DMA19_IRQHandler - - .align 1 - .thumb_func - .weak DMA4_DMA20_IRQHandler - .type DMA4_DMA20_IRQHandler, %function -DMA4_DMA20_IRQHandler: - ldr r0,=DMA4_DMA20_DriverIRQHandler - bx r0 - .size DMA4_DMA20_IRQHandler, . - DMA4_DMA20_IRQHandler - - .align 1 - .thumb_func - .weak DMA5_DMA21_IRQHandler - .type DMA5_DMA21_IRQHandler, %function -DMA5_DMA21_IRQHandler: - ldr r0,=DMA5_DMA21_DriverIRQHandler - bx r0 - .size DMA5_DMA21_IRQHandler, . - DMA5_DMA21_IRQHandler - - .align 1 - .thumb_func - .weak DMA6_DMA22_IRQHandler - .type DMA6_DMA22_IRQHandler, %function -DMA6_DMA22_IRQHandler: - ldr r0,=DMA6_DMA22_DriverIRQHandler - bx r0 - .size DMA6_DMA22_IRQHandler, . - DMA6_DMA22_IRQHandler - - .align 1 - .thumb_func - .weak DMA7_DMA23_IRQHandler - .type DMA7_DMA23_IRQHandler, %function -DMA7_DMA23_IRQHandler: - ldr r0,=DMA7_DMA23_DriverIRQHandler - bx r0 - .size DMA7_DMA23_IRQHandler, . - DMA7_DMA23_IRQHandler - - .align 1 - .thumb_func - .weak DMA8_DMA24_IRQHandler - .type DMA8_DMA24_IRQHandler, %function -DMA8_DMA24_IRQHandler: - ldr r0,=DMA8_DMA24_DriverIRQHandler - bx r0 - .size DMA8_DMA24_IRQHandler, . - DMA8_DMA24_IRQHandler - - .align 1 - .thumb_func - .weak DMA9_DMA25_IRQHandler - .type DMA9_DMA25_IRQHandler, %function -DMA9_DMA25_IRQHandler: - ldr r0,=DMA9_DMA25_DriverIRQHandler - bx r0 - .size DMA9_DMA25_IRQHandler, . - DMA9_DMA25_IRQHandler - - .align 1 - .thumb_func - .weak DMA10_DMA26_IRQHandler - .type DMA10_DMA26_IRQHandler, %function -DMA10_DMA26_IRQHandler: - ldr r0,=DMA10_DMA26_DriverIRQHandler - bx r0 - .size DMA10_DMA26_IRQHandler, . - DMA10_DMA26_IRQHandler - - .align 1 - .thumb_func - .weak DMA11_DMA27_IRQHandler - .type DMA11_DMA27_IRQHandler, %function -DMA11_DMA27_IRQHandler: - ldr r0,=DMA11_DMA27_DriverIRQHandler - bx r0 - .size DMA11_DMA27_IRQHandler, . - DMA11_DMA27_IRQHandler - - .align 1 - .thumb_func - .weak DMA12_DMA28_IRQHandler - .type DMA12_DMA28_IRQHandler, %function -DMA12_DMA28_IRQHandler: - ldr r0,=DMA12_DMA28_DriverIRQHandler - bx r0 - .size DMA12_DMA28_IRQHandler, . - DMA12_DMA28_IRQHandler - - .align 1 - .thumb_func - .weak DMA13_DMA29_IRQHandler - .type DMA13_DMA29_IRQHandler, %function -DMA13_DMA29_IRQHandler: - ldr r0,=DMA13_DMA29_DriverIRQHandler - bx r0 - .size DMA13_DMA29_IRQHandler, . - DMA13_DMA29_IRQHandler - - .align 1 - .thumb_func - .weak DMA14_DMA30_IRQHandler - .type DMA14_DMA30_IRQHandler, %function -DMA14_DMA30_IRQHandler: - ldr r0,=DMA14_DMA30_DriverIRQHandler - bx r0 - .size DMA14_DMA30_IRQHandler, . - DMA14_DMA30_IRQHandler - - .align 1 - .thumb_func - .weak DMA15_DMA31_IRQHandler - .type DMA15_DMA31_IRQHandler, %function -DMA15_DMA31_IRQHandler: - ldr r0,=DMA15_DMA31_DriverIRQHandler - bx r0 - .size DMA15_DMA31_IRQHandler, . - DMA15_DMA31_IRQHandler - - .align 1 - .thumb_func - .weak DMA_ERROR_IRQHandler - .type DMA_ERROR_IRQHandler, %function -DMA_ERROR_IRQHandler: - ldr r0,=DMA_ERROR_DriverIRQHandler - bx r0 - .size DMA_ERROR_IRQHandler, . - DMA_ERROR_IRQHandler - - .align 1 - .thumb_func - .weak LPUART1_IRQHandler - .type LPUART1_IRQHandler, %function -LPUART1_IRQHandler: - ldr r0,=LPUART1_DriverIRQHandler - bx r0 - .size LPUART1_IRQHandler, . - LPUART1_IRQHandler - - .align 1 - .thumb_func - .weak LPUART2_IRQHandler - .type LPUART2_IRQHandler, %function -LPUART2_IRQHandler: - ldr r0,=LPUART2_DriverIRQHandler - bx r0 - .size LPUART2_IRQHandler, . - LPUART2_IRQHandler - - .align 1 - .thumb_func - .weak LPUART3_IRQHandler - .type LPUART3_IRQHandler, %function -LPUART3_IRQHandler: - ldr r0,=LPUART3_DriverIRQHandler - bx r0 - .size LPUART3_IRQHandler, . - LPUART3_IRQHandler - - .align 1 - .thumb_func - .weak LPUART4_IRQHandler - .type LPUART4_IRQHandler, %function -LPUART4_IRQHandler: - ldr r0,=LPUART4_DriverIRQHandler - bx r0 - .size LPUART4_IRQHandler, . - LPUART4_IRQHandler - - .align 1 - .thumb_func - .weak LPUART5_IRQHandler - .type LPUART5_IRQHandler, %function -LPUART5_IRQHandler: - ldr r0,=LPUART5_DriverIRQHandler - bx r0 - .size LPUART5_IRQHandler, . - LPUART5_IRQHandler - - .align 1 - .thumb_func - .weak LPUART6_IRQHandler - .type LPUART6_IRQHandler, %function -LPUART6_IRQHandler: - ldr r0,=LPUART6_DriverIRQHandler - bx r0 - .size LPUART6_IRQHandler, . - LPUART6_IRQHandler - - .align 1 - .thumb_func - .weak LPUART7_IRQHandler - .type LPUART7_IRQHandler, %function -LPUART7_IRQHandler: - ldr r0,=LPUART7_DriverIRQHandler - bx r0 - .size LPUART7_IRQHandler, . - LPUART7_IRQHandler - - .align 1 - .thumb_func - .weak LPUART8_IRQHandler - .type LPUART8_IRQHandler, %function -LPUART8_IRQHandler: - ldr r0,=LPUART8_DriverIRQHandler - bx r0 - .size LPUART8_IRQHandler, . - LPUART8_IRQHandler - - .align 1 - .thumb_func - .weak LPI2C1_IRQHandler - .type LPI2C1_IRQHandler, %function -LPI2C1_IRQHandler: - ldr r0,=LPI2C1_DriverIRQHandler - bx r0 - .size LPI2C1_IRQHandler, . - LPI2C1_IRQHandler - - .align 1 - .thumb_func - .weak LPI2C2_IRQHandler - .type LPI2C2_IRQHandler, %function -LPI2C2_IRQHandler: - ldr r0,=LPI2C2_DriverIRQHandler - bx r0 - .size LPI2C2_IRQHandler, . - LPI2C2_IRQHandler - - .align 1 - .thumb_func - .weak LPI2C3_IRQHandler - .type LPI2C3_IRQHandler, %function -LPI2C3_IRQHandler: - ldr r0,=LPI2C3_DriverIRQHandler - bx r0 - .size LPI2C3_IRQHandler, . - LPI2C3_IRQHandler - - .align 1 - .thumb_func - .weak LPI2C4_IRQHandler - .type LPI2C4_IRQHandler, %function -LPI2C4_IRQHandler: - ldr r0,=LPI2C4_DriverIRQHandler - bx r0 - .size LPI2C4_IRQHandler, . - LPI2C4_IRQHandler - - .align 1 - .thumb_func - .weak LPSPI1_IRQHandler - .type LPSPI1_IRQHandler, %function -LPSPI1_IRQHandler: - ldr r0,=LPSPI1_DriverIRQHandler - bx r0 - .size LPSPI1_IRQHandler, . - LPSPI1_IRQHandler - - .align 1 - .thumb_func - .weak LPSPI2_IRQHandler - .type LPSPI2_IRQHandler, %function -LPSPI2_IRQHandler: - ldr r0,=LPSPI2_DriverIRQHandler - bx r0 - .size LPSPI2_IRQHandler, . - LPSPI2_IRQHandler - - .align 1 - .thumb_func - .weak LPSPI3_IRQHandler - .type LPSPI3_IRQHandler, %function -LPSPI3_IRQHandler: - ldr r0,=LPSPI3_DriverIRQHandler - bx r0 - .size LPSPI3_IRQHandler, . - LPSPI3_IRQHandler - - .align 1 - .thumb_func - .weak LPSPI4_IRQHandler - .type LPSPI4_IRQHandler, %function -LPSPI4_IRQHandler: - ldr r0,=LPSPI4_DriverIRQHandler - bx r0 - .size LPSPI4_IRQHandler, . - LPSPI4_IRQHandler - - .align 1 - .thumb_func - .weak CAN1_IRQHandler - .type CAN1_IRQHandler, %function -CAN1_IRQHandler: - ldr r0,=CAN1_DriverIRQHandler - bx r0 - .size CAN1_IRQHandler, . - CAN1_IRQHandler - - .align 1 - .thumb_func - .weak CAN2_IRQHandler - .type CAN2_IRQHandler, %function -CAN2_IRQHandler: - ldr r0,=CAN2_DriverIRQHandler - bx r0 - .size CAN2_IRQHandler, . - CAN2_IRQHandler - - .align 1 - .thumb_func - .weak SAI1_IRQHandler - .type SAI1_IRQHandler, %function -SAI1_IRQHandler: - ldr r0,=SAI1_DriverIRQHandler - bx r0 - .size SAI1_IRQHandler, . - SAI1_IRQHandler - - .align 1 - .thumb_func - .weak SAI2_IRQHandler - .type SAI2_IRQHandler, %function -SAI2_IRQHandler: - ldr r0,=SAI2_DriverIRQHandler - bx r0 - .size SAI2_IRQHandler, . - SAI2_IRQHandler - - .align 1 - .thumb_func - .weak SAI3_RX_IRQHandler - .type SAI3_RX_IRQHandler, %function -SAI3_RX_IRQHandler: - ldr r0,=SAI3_RX_DriverIRQHandler - bx r0 - .size SAI3_RX_IRQHandler, . - SAI3_RX_IRQHandler - - .align 1 - .thumb_func - .weak SAI3_TX_IRQHandler - .type SAI3_TX_IRQHandler, %function -SAI3_TX_IRQHandler: - ldr r0,=SAI3_TX_DriverIRQHandler - bx r0 - .size SAI3_TX_IRQHandler, . - SAI3_TX_IRQHandler - - .align 1 - .thumb_func - .weak SPDIF_IRQHandler - .type SPDIF_IRQHandler, %function -SPDIF_IRQHandler: - ldr r0,=SPDIF_DriverIRQHandler - bx r0 - .size SPDIF_IRQHandler, . - SPDIF_IRQHandler - - .align 1 - .thumb_func - .weak FLEXIO1_IRQHandler - .type FLEXIO1_IRQHandler, %function -FLEXIO1_IRQHandler: - ldr r0,=FLEXIO1_DriverIRQHandler - bx r0 - .size FLEXIO1_IRQHandler, . - FLEXIO1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXIO2_IRQHandler - .type FLEXIO2_IRQHandler, %function -FLEXIO2_IRQHandler: - ldr r0,=FLEXIO2_DriverIRQHandler - bx r0 - .size FLEXIO2_IRQHandler, . - FLEXIO2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXSPI_IRQHandler - .type FLEXSPI_IRQHandler, %function -FLEXSPI_IRQHandler: - ldr r0,=FLEXSPI_DriverIRQHandler - bx r0 - .size FLEXSPI_IRQHandler, . - FLEXSPI_IRQHandler - - .align 1 - .thumb_func - .weak USDHC1_IRQHandler - .type USDHC1_IRQHandler, %function -USDHC1_IRQHandler: - ldr r0,=USDHC1_DriverIRQHandler - bx r0 - .size USDHC1_IRQHandler, . - USDHC1_IRQHandler - - .align 1 - .thumb_func - .weak USDHC2_IRQHandler - .type USDHC2_IRQHandler, %function -USDHC2_IRQHandler: - ldr r0,=USDHC2_DriverIRQHandler - bx r0 - .size USDHC2_IRQHandler, . - USDHC2_IRQHandler - - .align 1 - .thumb_func - .weak ENET_IRQHandler - .type ENET_IRQHandler, %function -ENET_IRQHandler: - ldr r0,=ENET_DriverIRQHandler - bx r0 - .size ENET_IRQHandler, . - ENET_IRQHandler - - .align 1 - .thumb_func - .weak ENET_1588_Timer_IRQHandler - .type ENET_1588_Timer_IRQHandler, %function -ENET_1588_Timer_IRQHandler: - ldr r0,=ENET_1588_Timer_DriverIRQHandler - bx r0 - .size ENET_1588_Timer_IRQHandler, . - ENET_1588_Timer_IRQHandler - - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm - -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler DMA0_DMA16_DriverIRQHandler - def_irq_handler DMA1_DMA17_DriverIRQHandler - def_irq_handler DMA2_DMA18_DriverIRQHandler - def_irq_handler DMA3_DMA19_DriverIRQHandler - def_irq_handler DMA4_DMA20_DriverIRQHandler - def_irq_handler DMA5_DMA21_DriverIRQHandler - def_irq_handler DMA6_DMA22_DriverIRQHandler - def_irq_handler DMA7_DMA23_DriverIRQHandler - def_irq_handler DMA8_DMA24_DriverIRQHandler - def_irq_handler DMA9_DMA25_DriverIRQHandler - def_irq_handler DMA10_DMA26_DriverIRQHandler - def_irq_handler DMA11_DMA27_DriverIRQHandler - def_irq_handler DMA12_DMA28_DriverIRQHandler - def_irq_handler DMA13_DMA29_DriverIRQHandler - def_irq_handler DMA14_DMA30_DriverIRQHandler - def_irq_handler DMA15_DMA31_DriverIRQHandler - def_irq_handler DMA_ERROR_DriverIRQHandler - def_irq_handler CTI0_ERROR_IRQHandler - def_irq_handler CTI1_ERROR_IRQHandler - def_irq_handler CORE_IRQHandler - def_irq_handler LPUART1_DriverIRQHandler - def_irq_handler LPUART2_DriverIRQHandler - def_irq_handler LPUART3_DriverIRQHandler - def_irq_handler LPUART4_DriverIRQHandler - def_irq_handler LPUART5_DriverIRQHandler - def_irq_handler LPUART6_DriverIRQHandler - def_irq_handler LPUART7_DriverIRQHandler - def_irq_handler LPUART8_DriverIRQHandler - def_irq_handler LPI2C1_DriverIRQHandler - def_irq_handler LPI2C2_DriverIRQHandler - def_irq_handler LPI2C3_DriverIRQHandler - def_irq_handler LPI2C4_DriverIRQHandler - def_irq_handler LPSPI1_DriverIRQHandler - def_irq_handler LPSPI2_DriverIRQHandler - def_irq_handler LPSPI3_DriverIRQHandler - def_irq_handler LPSPI4_DriverIRQHandler - def_irq_handler CAN1_DriverIRQHandler - def_irq_handler CAN2_DriverIRQHandler - def_irq_handler FLEXRAM_IRQHandler - def_irq_handler KPP_IRQHandler - def_irq_handler TSC_DIG_IRQHandler - def_irq_handler GPR_IRQ_IRQHandler - def_irq_handler LCDIF_IRQHandler - def_irq_handler CSI_IRQHandler - def_irq_handler PXP_IRQHandler - def_irq_handler WDOG2_IRQHandler - def_irq_handler SNVS_HP_WRAPPER_IRQHandler - def_irq_handler SNVS_HP_WRAPPER_TZ_IRQHandler - def_irq_handler SNVS_LP_WRAPPER_IRQHandler - def_irq_handler CSU_IRQHandler - def_irq_handler DCP_IRQHandler - def_irq_handler DCP_VMI_IRQHandler - def_irq_handler Reserved68_IRQHandler - def_irq_handler TRNG_IRQHandler - def_irq_handler SJC_IRQHandler - def_irq_handler BEE_IRQHandler - def_irq_handler SAI1_DriverIRQHandler - def_irq_handler SAI2_DriverIRQHandler - def_irq_handler SAI3_RX_DriverIRQHandler - def_irq_handler SAI3_TX_DriverIRQHandler - def_irq_handler SPDIF_DriverIRQHandler - def_irq_handler ANATOP_EVENT0_IRQHandler - def_irq_handler ANATOP_EVENT1_IRQHandler - def_irq_handler ANATOP_TAMP_LOW_HIGH_IRQHandler - def_irq_handler ANATOP_TEMP_PANIC_IRQHandler - def_irq_handler USB_PHY1_IRQHandler - def_irq_handler USB_PHY2_IRQHandler - def_irq_handler ADC1_IRQHandler - def_irq_handler ADC2_IRQHandler - def_irq_handler DCDC_IRQHandler - def_irq_handler Reserved86_IRQHandler - def_irq_handler Reserved87_IRQHandler - def_irq_handler GPIO1_INT0_IRQHandler - def_irq_handler GPIO1_INT1_IRQHandler - def_irq_handler GPIO1_INT2_IRQHandler - def_irq_handler GPIO1_INT3_IRQHandler - def_irq_handler GPIO1_INT4_IRQHandler - def_irq_handler GPIO1_INT5_IRQHandler - def_irq_handler GPIO1_INT6_IRQHandler - def_irq_handler GPIO1_INT7_IRQHandler - def_irq_handler GPIO1_Combined_0_15_IRQHandler - def_irq_handler GPIO1_Combined_16_31_IRQHandler - def_irq_handler GPIO2_Combined_0_15_IRQHandler - def_irq_handler GPIO2_Combined_16_31_IRQHandler - def_irq_handler GPIO3_Combined_0_15_IRQHandler - def_irq_handler GPIO3_Combined_16_31_IRQHandler - def_irq_handler GPIO4_Combined_0_15_IRQHandler - def_irq_handler GPIO4_Combined_16_31_IRQHandler - def_irq_handler GPIO5_Combined_0_15_IRQHandler - def_irq_handler GPIO5_Combined_16_31_IRQHandler - def_irq_handler FLEXIO1_DriverIRQHandler - def_irq_handler FLEXIO2_DriverIRQHandler - def_irq_handler WDOG1_IRQHandler - def_irq_handler RTWDOG_IRQHandler - def_irq_handler EWM_IRQHandler - def_irq_handler CCM_1_IRQHandler - def_irq_handler CCM_2_IRQHandler - def_irq_handler GPC_IRQHandler - def_irq_handler SRC_IRQHandler - def_irq_handler Reserved115_IRQHandler - def_irq_handler GPT1_IRQHandler - def_irq_handler GPT2_IRQHandler - def_irq_handler PWM1_0_IRQHandler - def_irq_handler PWM1_1_IRQHandler - def_irq_handler PWM1_2_IRQHandler - def_irq_handler PWM1_3_IRQHandler - def_irq_handler PWM1_FAULT_IRQHandler - def_irq_handler Reserved123_IRQHandler - def_irq_handler FLEXSPI_DriverIRQHandler - def_irq_handler SEMC_IRQHandler - def_irq_handler USDHC1_DriverIRQHandler - def_irq_handler USDHC2_DriverIRQHandler - def_irq_handler USB_OTG2_IRQHandler - def_irq_handler USB_OTG1_IRQHandler - def_irq_handler ENET_DriverIRQHandler - def_irq_handler ENET_1588_Timer_DriverIRQHandler - def_irq_handler XBAR1_IRQ_0_1_IRQHandler - def_irq_handler XBAR1_IRQ_2_3_IRQHandler - def_irq_handler ADC_ETC_IRQ0_IRQHandler - def_irq_handler ADC_ETC_IRQ1_IRQHandler - def_irq_handler ADC_ETC_IRQ2_IRQHandler - def_irq_handler ADC_ETC_ERROR_IRQ_IRQHandler - def_irq_handler PIT_IRQHandler - def_irq_handler ACMP1_IRQHandler - def_irq_handler ACMP2_IRQHandler - def_irq_handler ACMP3_IRQHandler - def_irq_handler ACMP4_IRQHandler - def_irq_handler Reserved143_IRQHandler - def_irq_handler Reserved144_IRQHandler - def_irq_handler ENC1_IRQHandler - def_irq_handler ENC2_IRQHandler - def_irq_handler ENC3_IRQHandler - def_irq_handler ENC4_IRQHandler - def_irq_handler TMR1_IRQHandler - def_irq_handler TMR2_IRQHandler - def_irq_handler TMR3_IRQHandler - def_irq_handler TMR4_IRQHandler - def_irq_handler PWM2_0_IRQHandler - def_irq_handler PWM2_1_IRQHandler - def_irq_handler PWM2_2_IRQHandler - def_irq_handler PWM2_3_IRQHandler - def_irq_handler PWM2_FAULT_IRQHandler - def_irq_handler PWM3_0_IRQHandler - def_irq_handler PWM3_1_IRQHandler - def_irq_handler PWM3_2_IRQHandler - def_irq_handler PWM3_3_IRQHandler - def_irq_handler PWM3_FAULT_IRQHandler - def_irq_handler PWM4_0_IRQHandler - def_irq_handler PWM4_1_IRQHandler - def_irq_handler PWM4_2_IRQHandler - def_irq_handler PWM4_3_IRQHandler - def_irq_handler PWM4_FAULT_IRQHandler - def_irq_handler Reserved168_IRQHandler - def_irq_handler Reserved169_IRQHandler - def_irq_handler Reserved170_IRQHandler - def_irq_handler Reserved171_IRQHandler - def_irq_handler Reserved172_IRQHandler - def_irq_handler Reserved173_IRQHandler - def_irq_handler SJC_ARM_DEBUG_IRQHandler - - .end diff --git a/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxx6A_ram.icf b/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxx6A_ram.icf deleted file mode 100644 index 72eedfec9b..0000000000 --- a/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxx6A_ram.icf +++ /dev/null @@ -1,94 +0,0 @@ -/* -** ################################################################### -** Processor: MIMXRT1052DVL6A -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT105XRM Rev.A, 04/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170705 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000003FF; - -define symbol m_text_start = 0x00000400; -define symbol m_text_end = 0x0001FFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2001FFFF; - -define symbol m_data_2_start = 0x20200000; -define symbol m_data_2_end = 0x2023FFFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; - diff --git a/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxx6A_sdram.icf b/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxx6A_sdram.icf deleted file mode 100644 index 3e77bf19dd..0000000000 --- a/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxx6A_sdram.icf +++ /dev/null @@ -1,91 +0,0 @@ -/* -** ################################################################### -** Processor: MIMXRT1052DVL6A -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: i.MX 6RT for ROM -** Version: rev. 0.1, 2017-01-10 -** Build: b170608 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x80000000; -define symbol m_interrupts_end = 0x800003FF; - -define symbol m_text_start = 0x80000400; -define symbol m_text_end = 0x8001FFFF; - -define symbol m_data_start = 0x80020000; -define symbol m_data_end = 0x800FFFFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; - diff --git a/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_flexspi_nor.icf b/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_flexspi_nor.icf deleted file mode 100644 index 04bea11a34..0000000000 --- a/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_flexspi_nor.icf +++ /dev/null @@ -1,117 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x60002000; -define symbol m_interrupts_end = 0x600023FF; - -define symbol m_itcm_start = 0x00000000; -define symbol m_itcm_end = 0x0001FFFF; - -define symbol m_spiflash_start = 0x60002400; -define symbol m_spiflash_end = 0x7F7FFFFF; - -define symbol m_dtcm_start = 0x20000000; -define symbol m_dtcm_end = 0x2001FFFF; - -define symbol m_ocram_start = 0x20200000; -define symbol m_ocram_end = 0x2023FFFF; - -define symbol m_sdram_start = 0x80000000; -define symbol m_sdram_end = 0x81DFFFFF; - -define symbol m_ncache_start = 0x81E00000; -define symbol m_ncache_end = 0x81FFFFFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; -define exported symbol __RTT_HEAP_END = m_dtcm_end; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_spiflash_start to m_spiflash_end]; - -define region ITCM_region = mem:[from m_itcm_start to m_itcm_end]; -define region DTCM_region = mem:[from m_dtcm_start to m_dtcm_end]; -define region OCRAM_region = mem:[from m_ocram_start to m_ocram_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; -define region SDRAM_region = mem:[from m_sdram_start to m_sdram_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -keep { section FSymTab }; -keep { section VSymTab }; -keep { section .rti_fn* }; - -place in TEXT_region { readonly }; -place in DTCM_region { block RW }; -place in DTCM_region { block ZI }; -place in DTCM_region { last block HEAP }; -place in DTCM_region { block CSTACK }; -place in NCACHE_region { block NCACHE_VAR }; - diff --git a/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_ram.icf b/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_ram.icf deleted file mode 100644 index 15e23d0a2c..0000000000 --- a/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_ram.icf +++ /dev/null @@ -1,101 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000003FF; - -define symbol m_text_start = 0x00000400; -define symbol m_text_end = 0x0001FFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2001FFFF; - -define symbol m_data2_start = 0x20200000; -define symbol m_data2_end = 0x2023FFFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in DATA_region { block NCACHE_VAR }; -place in CSTACK_region { block CSTACK }; - diff --git a/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_sdram.icf b/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_sdram.icf deleted file mode 100644 index 9689731ff9..0000000000 --- a/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_sdram.icf +++ /dev/null @@ -1,109 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000003FF; - -define symbol m_text_start = 0x00000400; -define symbol m_text_end = 0x0001FFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2001FFFF; - -define symbol m_data2_start = 0x20200000; -define symbol m_data2_end = 0x2023FFFF; - -define symbol m_data3_start = 0x80000000; -define symbol m_data3_end = 0x81DFFFFF; - -define symbol m_ncache_start = 0x81E00000; -define symbol m_ncache_end = 0x81FFFFFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end]; -define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { first readwrite, section m_usb_dma_init_data }; -define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; -define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place in TEXT_region { readonly }; -place in DATA3_region { block RW }; -place in DATA3_region { block ZI }; -place in DATA3_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -place in NCACHE_region { block NCACHE_VAR }; - diff --git a/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_sdram_txt.icf b/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_sdram_txt.icf deleted file mode 100644 index 4c2b91cec7..0000000000 --- a/bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_sdram_txt.icf +++ /dev/null @@ -1,109 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVL5A -** MIMXRT1052DVL6A -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1050RM Rev.C, 08/2017 -** Version: rev. 0.1, 2017-01-10 -** Build: b170927 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -define symbol m_interrupts_start = 0x80000000; -define symbol m_interrupts_end = 0x800003FF; - -define symbol m_text_start = 0x80000400; -define symbol m_text_end = 0x801FFFFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2001FFFF; - -define symbol m_data2_start = 0x20200000; -define symbol m_data2_end = 0x2023FFFF; - -define symbol m_data3_start = 0x80200000; -define symbol m_data3_end = 0x81DFFFFF; - -define symbol m_ncache_start = 0x81E00000; -define symbol m_ncache_end = 0x81FFFFFF; - -/* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_interrupts_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; - -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; - -define region DATA_region = mem:[from m_data_start to m_data_end]; -define region DATA2_region = mem:[from m_data2_start to m_data2_end]; -define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data2_end-__size_cstack__+1 to m_data2_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { first readwrite, section m_usb_dma_init_data }; -define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; -define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place in TEXT_region { readonly }; -place in DATA2_region { block RW }; -place in DATA2_region { block ZI }; -place in DATA2_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -place in NCACHE_region { block NCACHE_VAR }; - diff --git a/bsp/imxrt1052-evk/Libraries/iar/startup_MIMXRT1052.s b/bsp/imxrt1052-evk/Libraries/iar/startup_MIMXRT1052.s deleted file mode 100644 index 6662e38884..0000000000 --- a/bsp/imxrt1052-evk/Libraries/iar/startup_MIMXRT1052.s +++ /dev/null @@ -1,1009 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MIMXRT1052.s -; @purpose: CMSIS Cortex-M7 Core Device Startup File -; MIMXRT1052 -; @version: 0.1 -; @date: 2017-1-10 -; @build: b170927 -; --------------------------------------------------------------------------------------- -; -; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2017 NXP -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD MemManage_Handler ;MPU Fault Handler - DCD BusFault_Handler ;Bus Fault Handler - DCD UsageFault_Handler ;Usage Fault Handler -__vector_table_0x1c - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD DebugMon_Handler ;Debug Monitor Handler - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_DMA16_IRQHandler ;DMA channel 0/16 transfer complete - DCD DMA1_DMA17_IRQHandler ;DMA channel 1/17 transfer complete - DCD DMA2_DMA18_IRQHandler ;DMA channel 2/18 transfer complete - DCD DMA3_DMA19_IRQHandler ;DMA channel 3/19 transfer complete - DCD DMA4_DMA20_IRQHandler ;DMA channel 4/20 transfer complete - DCD DMA5_DMA21_IRQHandler ;DMA channel 5/21 transfer complete - DCD DMA6_DMA22_IRQHandler ;DMA channel 6/22 transfer complete - DCD DMA7_DMA23_IRQHandler ;DMA channel 7/23 transfer complete - DCD DMA8_DMA24_IRQHandler ;DMA channel 8/24 transfer complete - DCD DMA9_DMA25_IRQHandler ;DMA channel 9/25 transfer complete - DCD DMA10_DMA26_IRQHandler ;DMA channel 10/26 transfer complete - DCD DMA11_DMA27_IRQHandler ;DMA channel 11/27 transfer complete - DCD DMA12_DMA28_IRQHandler ;DMA channel 12/28 transfer complete - DCD DMA13_DMA29_IRQHandler ;DMA channel 13/29 transfer complete - DCD DMA14_DMA30_IRQHandler ;DMA channel 14/30 transfer complete - DCD DMA15_DMA31_IRQHandler ;DMA channel 15/31 transfer complete - DCD DMA_ERROR_IRQHandler ;DMA error interrupt channels 0-15 / 16-31 - DCD CTI0_ERROR_IRQHandler ;CTI0_Error - DCD CTI1_ERROR_IRQHandler ;CTI1_Error - DCD CORE_IRQHandler ;CorePlatform exception IRQ - DCD LPUART1_IRQHandler ;LPUART1 TX interrupt and RX interrupt - DCD LPUART2_IRQHandler ;LPUART2 TX interrupt and RX interrupt - DCD LPUART3_IRQHandler ;LPUART3 TX interrupt and RX interrupt - DCD LPUART4_IRQHandler ;LPUART4 TX interrupt and RX interrupt - DCD LPUART5_IRQHandler ;LPUART5 TX interrupt and RX interrupt - DCD LPUART6_IRQHandler ;LPUART6 TX interrupt and RX interrupt - DCD LPUART7_IRQHandler ;LPUART7 TX interrupt and RX interrupt - DCD LPUART8_IRQHandler ;LPUART8 TX interrupt and RX interrupt - DCD LPI2C1_IRQHandler ;LPI2C1 interrupt - DCD LPI2C2_IRQHandler ;LPI2C2 interrupt - DCD LPI2C3_IRQHandler ;LPI2C3 interrupt - DCD LPI2C4_IRQHandler ;LPI2C4 interrupt - DCD LPSPI1_IRQHandler ;LPSPI1 single interrupt vector for all sources - DCD LPSPI2_IRQHandler ;LPSPI2 single interrupt vector for all sources - DCD LPSPI3_IRQHandler ;LPSPI3 single interrupt vector for all sources - DCD LPSPI4_IRQHandler ;LPSPI4 single interrupt vector for all sources - DCD CAN1_IRQHandler ;CAN1 interrupt - DCD CAN2_IRQHandler ;CAN2 interrupt - DCD FLEXRAM_IRQHandler ;FlexRAM address out of range Or access hit IRQ - DCD KPP_IRQHandler ;Keypad nterrupt - DCD TSC_DIG_IRQHandler ;TSC interrupt - DCD GPR_IRQ_IRQHandler ;GPR interrupt - DCD LCDIF_IRQHandler ;LCDIF interrupt - DCD CSI_IRQHandler ;CSI interrupt - DCD PXP_IRQHandler ;PXP interrupt - DCD WDOG2_IRQHandler ;WDOG2 interrupt - DCD SNVS_HP_WRAPPER_IRQHandler ;SRTC Consolidated Interrupt. Non TZ - DCD SNVS_HP_WRAPPER_TZ_IRQHandler ;SRTC Security Interrupt. TZ - DCD SNVS_LP_WRAPPER_IRQHandler ;ON-OFF button press shorter than 5 secs (pulse event) - DCD CSU_IRQHandler ;CSU interrupt - DCD DCP_IRQHandler ;DCP_IRQ interrupt - DCD DCP_VMI_IRQHandler ;DCP_VMI_IRQ interrupt - DCD Reserved68_IRQHandler ;Reserved interrupt - DCD TRNG_IRQHandler ;TRNG interrupt - DCD SJC_IRQHandler ;SJC interrupt - DCD BEE_IRQHandler ;BEE interrupt - DCD SAI1_IRQHandler ;SAI1 interrupt - DCD SAI2_IRQHandler ;SAI1 interrupt - DCD SAI3_RX_IRQHandler ;SAI3 interrupt - DCD SAI3_TX_IRQHandler ;SAI3 interrupt - DCD SPDIF_IRQHandler ;SPDIF interrupt - DCD ANATOP_EVENT0_IRQHandler ;ANATOP interrupt - DCD ANATOP_EVENT1_IRQHandler ;ANATOP interrupt - DCD ANATOP_TAMP_LOW_HIGH_IRQHandler ;ANATOP interrupt - DCD ANATOP_TEMP_PANIC_IRQHandler ;ANATOP interrupt - DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt - DCD USB_PHY2_IRQHandler ;USBPHY (UTMI0), Interrupt - DCD ADC1_IRQHandler ;ADC1 interrupt - DCD ADC2_IRQHandler ;ADC2 interrupt - DCD DCDC_IRQHandler ;DCDC interrupt - DCD Reserved86_IRQHandler ;Reserved interrupt - DCD Reserved87_IRQHandler ;Reserved interrupt - DCD GPIO1_INT0_IRQHandler ;Active HIGH Interrupt from INT0 from GPIO - DCD GPIO1_INT1_IRQHandler ;Active HIGH Interrupt from INT1 from GPIO - DCD GPIO1_INT2_IRQHandler ;Active HIGH Interrupt from INT2 from GPIO - DCD GPIO1_INT3_IRQHandler ;Active HIGH Interrupt from INT3 from GPIO - DCD GPIO1_INT4_IRQHandler ;Active HIGH Interrupt from INT4 from GPIO - DCD GPIO1_INT5_IRQHandler ;Active HIGH Interrupt from INT5 from GPIO - DCD GPIO1_INT6_IRQHandler ;Active HIGH Interrupt from INT6 from GPIO - DCD GPIO1_INT7_IRQHandler ;Active HIGH Interrupt from INT7 from GPIO - DCD GPIO1_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO1 signal 0 throughout 15 - DCD GPIO1_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO1 signal 16 throughout 31 - DCD GPIO2_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO2 signal 0 throughout 15 - DCD GPIO2_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO2 signal 16 throughout 31 - DCD GPIO3_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO3 signal 0 throughout 15 - DCD GPIO3_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO3 signal 16 throughout 31 - DCD GPIO4_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO4 signal 0 throughout 15 - DCD GPIO4_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO4 signal 16 throughout 31 - DCD GPIO5_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO5 signal 0 throughout 15 - DCD GPIO5_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO5 signal 16 throughout 31 - DCD FLEXIO1_IRQHandler ;FLEXIO1 interrupt - DCD FLEXIO2_IRQHandler ;FLEXIO2 interrupt - DCD WDOG1_IRQHandler ;WDOG1 interrupt - DCD RTWDOG_IRQHandler ;RTWDOG interrupt - DCD EWM_IRQHandler ;EWM interrupt - DCD CCM_1_IRQHandler ;CCM IRQ1 interrupt - DCD CCM_2_IRQHandler ;CCM IRQ2 interrupt - DCD GPC_IRQHandler ;GPC interrupt - DCD SRC_IRQHandler ;SRC interrupt - DCD Reserved115_IRQHandler ;Reserved interrupt - DCD GPT1_IRQHandler ;GPT1 interrupt - DCD GPT2_IRQHandler ;GPT2 interrupt - DCD PWM1_0_IRQHandler ;PWM1 capture 0, compare 0, or reload 0 interrupt - DCD PWM1_1_IRQHandler ;PWM1 capture 1, compare 1, or reload 0 interrupt - DCD PWM1_2_IRQHandler ;PWM1 capture 2, compare 2, or reload 0 interrupt - DCD PWM1_3_IRQHandler ;PWM1 capture 3, compare 3, or reload 0 interrupt - DCD PWM1_FAULT_IRQHandler ;PWM1 fault or reload error interrupt - DCD Reserved123_IRQHandler ;Reserved interrupt - DCD FLEXSPI_IRQHandler ;FlexSPI0 interrupt - DCD SEMC_IRQHandler ;Reserved interrupt - DCD USDHC1_IRQHandler ;USDHC1 interrupt - DCD USDHC2_IRQHandler ;USDHC2 interrupt - DCD USB_OTG2_IRQHandler ;USBO2 USB OTG2 - DCD USB_OTG1_IRQHandler ;USBO2 USB OTG1 - DCD ENET_IRQHandler ;ENET interrupt - DCD ENET_1588_Timer_IRQHandler ;ENET_1588_Timer interrupt - DCD XBAR1_IRQ_0_1_IRQHandler ;XBAR1 interrupt - DCD XBAR1_IRQ_2_3_IRQHandler ;XBAR1 interrupt - DCD ADC_ETC_IRQ0_IRQHandler ;ADCETC IRQ0 interrupt - DCD ADC_ETC_IRQ1_IRQHandler ;ADCETC IRQ1 interrupt - DCD ADC_ETC_IRQ2_IRQHandler ;ADCETC IRQ2 interrupt - DCD ADC_ETC_ERROR_IRQ_IRQHandler ;ADCETC Error IRQ interrupt - DCD PIT_IRQHandler ;PIT interrupt - DCD ACMP1_IRQHandler ;ACMP interrupt - DCD ACMP2_IRQHandler ;ACMP interrupt - DCD ACMP3_IRQHandler ;ACMP interrupt - DCD ACMP4_IRQHandler ;ACMP interrupt - DCD Reserved143_IRQHandler ;Reserved interrupt - DCD Reserved144_IRQHandler ;Reserved interrupt - DCD ENC1_IRQHandler ;ENC1 interrupt - DCD ENC2_IRQHandler ;ENC2 interrupt - DCD ENC3_IRQHandler ;ENC3 interrupt - DCD ENC4_IRQHandler ;ENC4 interrupt - DCD TMR1_IRQHandler ;TMR1 interrupt - DCD TMR2_IRQHandler ;TMR2 interrupt - DCD TMR3_IRQHandler ;TMR3 interrupt - DCD TMR4_IRQHandler ;TMR4 interrupt - DCD PWM2_0_IRQHandler ;PWM2 capture 0, compare 0, or reload 0 interrupt - DCD PWM2_1_IRQHandler ;PWM2 capture 1, compare 1, or reload 0 interrupt - DCD PWM2_2_IRQHandler ;PWM2 capture 2, compare 2, or reload 0 interrupt - DCD PWM2_3_IRQHandler ;PWM2 capture 3, compare 3, or reload 0 interrupt - DCD PWM2_FAULT_IRQHandler ;PWM2 fault or reload error interrupt - DCD PWM3_0_IRQHandler ;PWM3 capture 0, compare 0, or reload 0 interrupt - DCD PWM3_1_IRQHandler ;PWM3 capture 1, compare 1, or reload 0 interrupt - DCD PWM3_2_IRQHandler ;PWM3 capture 2, compare 2, or reload 0 interrupt - DCD PWM3_3_IRQHandler ;PWM3 capture 3, compare 3, or reload 0 interrupt - DCD PWM3_FAULT_IRQHandler ;PWM3 fault or reload error interrupt - DCD PWM4_0_IRQHandler ;PWM4 capture 0, compare 0, or reload 0 interrupt - DCD PWM4_1_IRQHandler ;PWM4 capture 1, compare 1, or reload 0 interrupt - DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt - DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt - DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt - DCD Reserved168_IRQHandler ;Reserved interrupt - DCD Reserved169_IRQHandler ;Reserved interrupt - DCD Reserved170_IRQHandler ;Reserved interrupt - DCD Reserved171_IRQHandler ;Reserved interrupt - DCD Reserved172_IRQHandler ;Reserved interrupt - DCD Reserved173_IRQHandler ;Reserved interrupt - DCD SJC_ARM_DEBUG_IRQHandler ;SJC ARM debug interrupt - DCD NMI_WAKEUP_IRQHandler ;NMI wake up - DCD DefaultISR ;176 - DCD DefaultISR ;177 - DCD DefaultISR ;178 - DCD DefaultISR ;179 - DCD DefaultISR ;180 - DCD DefaultISR ;181 - DCD DefaultISR ;182 - DCD DefaultISR ;183 - DCD DefaultISR ;184 - DCD DefaultISR ;185 - DCD DefaultISR ;186 - DCD DefaultISR ;187 - DCD DefaultISR ;188 - DCD DefaultISR ;189 - DCD DefaultISR ;190 - DCD DefaultISR ;191 - DCD DefaultISR ;192 - DCD DefaultISR ;193 - DCD DefaultISR ;194 - DCD DefaultISR ;195 - DCD DefaultISR ;196 - DCD DefaultISR ;197 - DCD DefaultISR ;198 - DCD DefaultISR ;199 - DCD DefaultISR ;200 - DCD DefaultISR ;201 - DCD DefaultISR ;202 - DCD DefaultISR ;203 - DCD DefaultISR ;204 - DCD DefaultISR ;205 - DCD DefaultISR ;206 - DCD DefaultISR ;207 - DCD DefaultISR ;208 - DCD DefaultISR ;209 - DCD DefaultISR ;210 - DCD DefaultISR ;211 - DCD DefaultISR ;212 - DCD DefaultISR ;213 - DCD DefaultISR ;214 - DCD DefaultISR ;215 - DCD DefaultISR ;216 - DCD DefaultISR ;217 - DCD DefaultISR ;218 - DCD DefaultISR ;219 - DCD DefaultISR ;220 - DCD DefaultISR ;221 - DCD DefaultISR ;222 - DCD DefaultISR ;223 - DCD DefaultISR ;224 - DCD DefaultISR ;225 - DCD DefaultISR ;226 - DCD DefaultISR ;227 - DCD DefaultISR ;228 - DCD DefaultISR ;229 - DCD DefaultISR ;230 - DCD DefaultISR ;231 - DCD DefaultISR ;232 - DCD DefaultISR ;233 - DCD DefaultISR ;234 - DCD DefaultISR ;235 - DCD DefaultISR ;236 - DCD DefaultISR ;237 - DCD DefaultISR ;238 - DCD DefaultISR ;239 - DCD DefaultISR ;240 - DCD DefaultISR ;241 - DCD DefaultISR ;242 - DCD DefaultISR ;243 - DCD DefaultISR ;244 - DCD DefaultISR ;245 - DCD DefaultISR ;246 - DCD DefaultISR ;247 - DCD DefaultISR ;248 - DCD DefaultISR ;249 - DCD DefaultISR ;250 - DCD DefaultISR ;251 - DCD DefaultISR ;252 - DCD DefaultISR ;253 - DCD DefaultISR ;254 - DCD 0xFFFFFFFF ; Reserved for user TRIM value -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R2, [R1] - MSR MSP, R2 - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK DMA0_DMA16_IRQHandler - PUBWEAK DMA0_DMA16_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_DMA16_IRQHandler - LDR R0, =DMA0_DMA16_DriverIRQHandler - BX R0 - - PUBWEAK DMA1_DMA17_IRQHandler - PUBWEAK DMA1_DMA17_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_DMA17_IRQHandler - LDR R0, =DMA1_DMA17_DriverIRQHandler - BX R0 - - PUBWEAK DMA2_DMA18_IRQHandler - PUBWEAK DMA2_DMA18_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA2_DMA18_IRQHandler - LDR R0, =DMA2_DMA18_DriverIRQHandler - BX R0 - - PUBWEAK DMA3_DMA19_IRQHandler - PUBWEAK DMA3_DMA19_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA3_DMA19_IRQHandler - LDR R0, =DMA3_DMA19_DriverIRQHandler - BX R0 - - PUBWEAK DMA4_DMA20_IRQHandler - PUBWEAK DMA4_DMA20_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA4_DMA20_IRQHandler - LDR R0, =DMA4_DMA20_DriverIRQHandler - BX R0 - - PUBWEAK DMA5_DMA21_IRQHandler - PUBWEAK DMA5_DMA21_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA5_DMA21_IRQHandler - LDR R0, =DMA5_DMA21_DriverIRQHandler - BX R0 - - PUBWEAK DMA6_DMA22_IRQHandler - PUBWEAK DMA6_DMA22_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA6_DMA22_IRQHandler - LDR R0, =DMA6_DMA22_DriverIRQHandler - BX R0 - - PUBWEAK DMA7_DMA23_IRQHandler - PUBWEAK DMA7_DMA23_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA7_DMA23_IRQHandler - LDR R0, =DMA7_DMA23_DriverIRQHandler - BX R0 - - PUBWEAK DMA8_DMA24_IRQHandler - PUBWEAK DMA8_DMA24_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA8_DMA24_IRQHandler - LDR R0, =DMA8_DMA24_DriverIRQHandler - BX R0 - - PUBWEAK DMA9_DMA25_IRQHandler - PUBWEAK DMA9_DMA25_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA9_DMA25_IRQHandler - LDR R0, =DMA9_DMA25_DriverIRQHandler - BX R0 - - PUBWEAK DMA10_DMA26_IRQHandler - PUBWEAK DMA10_DMA26_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA10_DMA26_IRQHandler - LDR R0, =DMA10_DMA26_DriverIRQHandler - BX R0 - - PUBWEAK DMA11_DMA27_IRQHandler - PUBWEAK DMA11_DMA27_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA11_DMA27_IRQHandler - LDR R0, =DMA11_DMA27_DriverIRQHandler - BX R0 - - PUBWEAK DMA12_DMA28_IRQHandler - PUBWEAK DMA12_DMA28_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA12_DMA28_IRQHandler - LDR R0, =DMA12_DMA28_DriverIRQHandler - BX R0 - - PUBWEAK DMA13_DMA29_IRQHandler - PUBWEAK DMA13_DMA29_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA13_DMA29_IRQHandler - LDR R0, =DMA13_DMA29_DriverIRQHandler - BX R0 - - PUBWEAK DMA14_DMA30_IRQHandler - PUBWEAK DMA14_DMA30_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA14_DMA30_IRQHandler - LDR R0, =DMA14_DMA30_DriverIRQHandler - BX R0 - - PUBWEAK DMA15_DMA31_IRQHandler - PUBWEAK DMA15_DMA31_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA15_DMA31_IRQHandler - LDR R0, =DMA15_DMA31_DriverIRQHandler - BX R0 - - PUBWEAK DMA_ERROR_IRQHandler - PUBWEAK DMA_ERROR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA_ERROR_IRQHandler - LDR R0, =DMA_ERROR_DriverIRQHandler - BX R0 - - PUBWEAK CTI0_ERROR_IRQHandler - PUBWEAK CTI1_ERROR_IRQHandler - PUBWEAK CORE_IRQHandler - PUBWEAK LPUART1_IRQHandler - PUBWEAK LPUART1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART1_IRQHandler - LDR R0, =LPUART1_DriverIRQHandler - BX R0 - - PUBWEAK LPUART2_IRQHandler - PUBWEAK LPUART2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART2_IRQHandler - LDR R0, =LPUART2_DriverIRQHandler - BX R0 - - PUBWEAK LPUART3_IRQHandler - PUBWEAK LPUART3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART3_IRQHandler - LDR R0, =LPUART3_DriverIRQHandler - BX R0 - - PUBWEAK LPUART4_IRQHandler - PUBWEAK LPUART4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART4_IRQHandler - LDR R0, =LPUART4_DriverIRQHandler - BX R0 - - PUBWEAK LPUART5_IRQHandler - PUBWEAK LPUART5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART5_IRQHandler - LDR R0, =LPUART5_DriverIRQHandler - BX R0 - - PUBWEAK LPUART6_IRQHandler - PUBWEAK LPUART6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART6_IRQHandler - LDR R0, =LPUART6_DriverIRQHandler - BX R0 - - PUBWEAK LPUART7_IRQHandler - PUBWEAK LPUART7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART7_IRQHandler - LDR R0, =LPUART7_DriverIRQHandler - BX R0 - - PUBWEAK LPUART8_IRQHandler - PUBWEAK LPUART8_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART8_IRQHandler - LDR R0, =LPUART8_DriverIRQHandler - BX R0 - - PUBWEAK LPI2C1_IRQHandler - PUBWEAK LPI2C1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPI2C1_IRQHandler - LDR R0, =LPI2C1_DriverIRQHandler - BX R0 - - PUBWEAK LPI2C2_IRQHandler - PUBWEAK LPI2C2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPI2C2_IRQHandler - LDR R0, =LPI2C2_DriverIRQHandler - BX R0 - - PUBWEAK LPI2C3_IRQHandler - PUBWEAK LPI2C3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPI2C3_IRQHandler - LDR R0, =LPI2C3_DriverIRQHandler - BX R0 - - PUBWEAK LPI2C4_IRQHandler - PUBWEAK LPI2C4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPI2C4_IRQHandler - LDR R0, =LPI2C4_DriverIRQHandler - BX R0 - - PUBWEAK LPSPI1_IRQHandler - PUBWEAK LPSPI1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPSPI1_IRQHandler - LDR R0, =LPSPI1_DriverIRQHandler - BX R0 - - PUBWEAK LPSPI2_IRQHandler - PUBWEAK LPSPI2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPSPI2_IRQHandler - LDR R0, =LPSPI2_DriverIRQHandler - BX R0 - - PUBWEAK LPSPI3_IRQHandler - PUBWEAK LPSPI3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPSPI3_IRQHandler - LDR R0, =LPSPI3_DriverIRQHandler - BX R0 - - PUBWEAK LPSPI4_IRQHandler - PUBWEAK LPSPI4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPSPI4_IRQHandler - LDR R0, =LPSPI4_DriverIRQHandler - BX R0 - - PUBWEAK CAN1_IRQHandler - PUBWEAK CAN1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN1_IRQHandler - LDR R0, =CAN1_DriverIRQHandler - BX R0 - - PUBWEAK CAN2_IRQHandler - PUBWEAK CAN2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN2_IRQHandler - LDR R0, =CAN2_DriverIRQHandler - BX R0 - - PUBWEAK FLEXRAM_IRQHandler - PUBWEAK KPP_IRQHandler - PUBWEAK TSC_DIG_IRQHandler - PUBWEAK GPR_IRQ_IRQHandler - PUBWEAK LCDIF_IRQHandler - PUBWEAK CSI_IRQHandler - PUBWEAK PXP_IRQHandler - PUBWEAK WDOG2_IRQHandler - PUBWEAK SNVS_HP_WRAPPER_IRQHandler - PUBWEAK SNVS_HP_WRAPPER_TZ_IRQHandler - PUBWEAK SNVS_LP_WRAPPER_IRQHandler - PUBWEAK CSU_IRQHandler - PUBWEAK DCP_IRQHandler - PUBWEAK DCP_VMI_IRQHandler - PUBWEAK Reserved68_IRQHandler - PUBWEAK TRNG_IRQHandler - PUBWEAK SJC_IRQHandler - PUBWEAK BEE_IRQHandler - PUBWEAK SAI1_IRQHandler - PUBWEAK SAI1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SAI1_IRQHandler - LDR R0, =SAI1_DriverIRQHandler - BX R0 - - PUBWEAK SAI2_IRQHandler - PUBWEAK SAI2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SAI2_IRQHandler - LDR R0, =SAI2_DriverIRQHandler - BX R0 - - PUBWEAK SAI3_RX_IRQHandler - PUBWEAK SAI3_RX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SAI3_RX_IRQHandler - LDR R0, =SAI3_RX_DriverIRQHandler - BX R0 - - PUBWEAK SAI3_TX_IRQHandler - PUBWEAK SAI3_TX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SAI3_TX_IRQHandler - LDR R0, =SAI3_TX_DriverIRQHandler - BX R0 - - PUBWEAK SPDIF_IRQHandler - PUBWEAK SPDIF_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPDIF_IRQHandler - LDR R0, =SPDIF_DriverIRQHandler - BX R0 - - PUBWEAK ANATOP_EVENT0_IRQHandler - PUBWEAK ANATOP_EVENT1_IRQHandler - PUBWEAK ANATOP_TAMP_LOW_HIGH_IRQHandler - PUBWEAK ANATOP_TEMP_PANIC_IRQHandler - PUBWEAK USB_PHY1_IRQHandler - PUBWEAK USB_PHY2_IRQHandler - PUBWEAK ADC1_IRQHandler - PUBWEAK ADC2_IRQHandler - PUBWEAK DCDC_IRQHandler - PUBWEAK Reserved86_IRQHandler - PUBWEAK Reserved87_IRQHandler - PUBWEAK GPIO1_INT0_IRQHandler - PUBWEAK GPIO1_INT1_IRQHandler - PUBWEAK GPIO1_INT2_IRQHandler - PUBWEAK GPIO1_INT3_IRQHandler - PUBWEAK GPIO1_INT4_IRQHandler - PUBWEAK GPIO1_INT5_IRQHandler - PUBWEAK GPIO1_INT6_IRQHandler - PUBWEAK GPIO1_INT7_IRQHandler - PUBWEAK GPIO1_Combined_0_15_IRQHandler - PUBWEAK GPIO1_Combined_16_31_IRQHandler - PUBWEAK GPIO2_Combined_0_15_IRQHandler - PUBWEAK GPIO2_Combined_16_31_IRQHandler - PUBWEAK GPIO3_Combined_0_15_IRQHandler - PUBWEAK GPIO3_Combined_16_31_IRQHandler - PUBWEAK GPIO4_Combined_0_15_IRQHandler - PUBWEAK GPIO4_Combined_16_31_IRQHandler - PUBWEAK GPIO5_Combined_0_15_IRQHandler - PUBWEAK GPIO5_Combined_16_31_IRQHandler - PUBWEAK FLEXIO1_IRQHandler - PUBWEAK FLEXIO1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXIO1_IRQHandler - LDR R0, =FLEXIO1_DriverIRQHandler - BX R0 - - PUBWEAK FLEXIO2_IRQHandler - PUBWEAK FLEXIO2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXIO2_IRQHandler - LDR R0, =FLEXIO2_DriverIRQHandler - BX R0 - - PUBWEAK WDOG1_IRQHandler - PUBWEAK RTWDOG_IRQHandler - PUBWEAK EWM_IRQHandler - PUBWEAK CCM_1_IRQHandler - PUBWEAK CCM_2_IRQHandler - PUBWEAK GPC_IRQHandler - PUBWEAK SRC_IRQHandler - PUBWEAK Reserved115_IRQHandler - PUBWEAK GPT1_IRQHandler - PUBWEAK GPT2_IRQHandler - PUBWEAK PWM1_0_IRQHandler - PUBWEAK PWM1_1_IRQHandler - PUBWEAK PWM1_2_IRQHandler - PUBWEAK PWM1_3_IRQHandler - PUBWEAK PWM1_FAULT_IRQHandler - PUBWEAK Reserved123_IRQHandler - PUBWEAK FLEXSPI_IRQHandler - PUBWEAK FLEXSPI_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXSPI_IRQHandler - LDR R0, =FLEXSPI_DriverIRQHandler - BX R0 - - PUBWEAK SEMC_IRQHandler - PUBWEAK USDHC1_IRQHandler - PUBWEAK USDHC1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USDHC1_IRQHandler - LDR R0, =USDHC1_DriverIRQHandler - BX R0 - - PUBWEAK USDHC2_IRQHandler - PUBWEAK USDHC2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USDHC2_IRQHandler - LDR R0, =USDHC2_DriverIRQHandler - BX R0 - - PUBWEAK USB_OTG2_IRQHandler - PUBWEAK USB_OTG1_IRQHandler - PUBWEAK ENET_IRQHandler - PUBWEAK ENET_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ENET_IRQHandler - LDR R0, =ENET_DriverIRQHandler - BX R0 - - PUBWEAK ENET_1588_Timer_IRQHandler - PUBWEAK ENET_1588_Timer_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ENET_1588_Timer_IRQHandler - LDR R0, =ENET_1588_Timer_DriverIRQHandler - BX R0 - - PUBWEAK XBAR1_IRQ_0_1_IRQHandler - PUBWEAK XBAR1_IRQ_2_3_IRQHandler - PUBWEAK ADC_ETC_IRQ0_IRQHandler - PUBWEAK ADC_ETC_IRQ1_IRQHandler - PUBWEAK ADC_ETC_IRQ2_IRQHandler - PUBWEAK ADC_ETC_ERROR_IRQ_IRQHandler - PUBWEAK PIT_IRQHandler - PUBWEAK ACMP1_IRQHandler - PUBWEAK ACMP2_IRQHandler - PUBWEAK ACMP3_IRQHandler - PUBWEAK ACMP4_IRQHandler - PUBWEAK Reserved143_IRQHandler - PUBWEAK Reserved144_IRQHandler - PUBWEAK ENC1_IRQHandler - PUBWEAK ENC2_IRQHandler - PUBWEAK ENC3_IRQHandler - PUBWEAK ENC4_IRQHandler - PUBWEAK TMR1_IRQHandler - PUBWEAK TMR2_IRQHandler - PUBWEAK TMR3_IRQHandler - PUBWEAK TMR4_IRQHandler - PUBWEAK PWM2_0_IRQHandler - PUBWEAK PWM2_1_IRQHandler - PUBWEAK PWM2_2_IRQHandler - PUBWEAK PWM2_3_IRQHandler - PUBWEAK PWM2_FAULT_IRQHandler - PUBWEAK PWM3_0_IRQHandler - PUBWEAK PWM3_1_IRQHandler - PUBWEAK PWM3_2_IRQHandler - PUBWEAK PWM3_3_IRQHandler - PUBWEAK PWM3_FAULT_IRQHandler - PUBWEAK PWM4_0_IRQHandler - PUBWEAK PWM4_1_IRQHandler - PUBWEAK PWM4_2_IRQHandler - PUBWEAK PWM4_3_IRQHandler - PUBWEAK PWM4_FAULT_IRQHandler - PUBWEAK Reserved168_IRQHandler - PUBWEAK Reserved169_IRQHandler - PUBWEAK Reserved170_IRQHandler - PUBWEAK Reserved171_IRQHandler - PUBWEAK Reserved172_IRQHandler - PUBWEAK Reserved173_IRQHandler - PUBWEAK SJC_ARM_DEBUG_IRQHandler - PUBWEAK NMI_WAKEUP_IRQHandler - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(1) -DMA0_DMA16_DriverIRQHandler -DMA1_DMA17_DriverIRQHandler -DMA2_DMA18_DriverIRQHandler -DMA3_DMA19_DriverIRQHandler -DMA4_DMA20_DriverIRQHandler -DMA5_DMA21_DriverIRQHandler -DMA6_DMA22_DriverIRQHandler -DMA7_DMA23_DriverIRQHandler -DMA8_DMA24_DriverIRQHandler -DMA9_DMA25_DriverIRQHandler -DMA10_DMA26_DriverIRQHandler -DMA11_DMA27_DriverIRQHandler -DMA12_DMA28_DriverIRQHandler -DMA13_DMA29_DriverIRQHandler -DMA14_DMA30_DriverIRQHandler -DMA15_DMA31_DriverIRQHandler -DMA_ERROR_DriverIRQHandler -CTI0_ERROR_IRQHandler -CTI1_ERROR_IRQHandler -CORE_IRQHandler -LPUART1_DriverIRQHandler -LPUART2_DriverIRQHandler -LPUART3_DriverIRQHandler -LPUART4_DriverIRQHandler -LPUART5_DriverIRQHandler -LPUART6_DriverIRQHandler -LPUART7_DriverIRQHandler -LPUART8_DriverIRQHandler -LPI2C1_DriverIRQHandler -LPI2C2_DriverIRQHandler -LPI2C3_DriverIRQHandler -LPI2C4_DriverIRQHandler -LPSPI1_DriverIRQHandler -LPSPI2_DriverIRQHandler -LPSPI3_DriverIRQHandler -LPSPI4_DriverIRQHandler -CAN1_DriverIRQHandler -CAN2_DriverIRQHandler -FLEXRAM_IRQHandler -KPP_IRQHandler -TSC_DIG_IRQHandler -GPR_IRQ_IRQHandler -LCDIF_IRQHandler -CSI_IRQHandler -PXP_IRQHandler -WDOG2_IRQHandler -SNVS_HP_WRAPPER_IRQHandler -SNVS_HP_WRAPPER_TZ_IRQHandler -SNVS_LP_WRAPPER_IRQHandler -CSU_IRQHandler -DCP_IRQHandler -DCP_VMI_IRQHandler -Reserved68_IRQHandler -TRNG_IRQHandler -SJC_IRQHandler -BEE_IRQHandler -SAI1_DriverIRQHandler -SAI2_DriverIRQHandler -SAI3_RX_DriverIRQHandler -SAI3_TX_DriverIRQHandler -SPDIF_DriverIRQHandler -ANATOP_EVENT0_IRQHandler -ANATOP_EVENT1_IRQHandler -ANATOP_TAMP_LOW_HIGH_IRQHandler -ANATOP_TEMP_PANIC_IRQHandler -USB_PHY1_IRQHandler -USB_PHY2_IRQHandler -ADC1_IRQHandler -ADC2_IRQHandler -DCDC_IRQHandler -Reserved86_IRQHandler -Reserved87_IRQHandler -GPIO1_INT0_IRQHandler -GPIO1_INT1_IRQHandler -GPIO1_INT2_IRQHandler -GPIO1_INT3_IRQHandler -GPIO1_INT4_IRQHandler -GPIO1_INT5_IRQHandler -GPIO1_INT6_IRQHandler -GPIO1_INT7_IRQHandler -GPIO1_Combined_0_15_IRQHandler -GPIO1_Combined_16_31_IRQHandler -GPIO2_Combined_0_15_IRQHandler -GPIO2_Combined_16_31_IRQHandler -GPIO3_Combined_0_15_IRQHandler -GPIO3_Combined_16_31_IRQHandler -GPIO4_Combined_0_15_IRQHandler -GPIO4_Combined_16_31_IRQHandler -GPIO5_Combined_0_15_IRQHandler -GPIO5_Combined_16_31_IRQHandler -FLEXIO1_DriverIRQHandler -FLEXIO2_DriverIRQHandler -WDOG1_IRQHandler -RTWDOG_IRQHandler -EWM_IRQHandler -CCM_1_IRQHandler -CCM_2_IRQHandler -GPC_IRQHandler -SRC_IRQHandler -Reserved115_IRQHandler -GPT1_IRQHandler -GPT2_IRQHandler -PWM1_0_IRQHandler -PWM1_1_IRQHandler -PWM1_2_IRQHandler -PWM1_3_IRQHandler -PWM1_FAULT_IRQHandler -Reserved123_IRQHandler -FLEXSPI_DriverIRQHandler -SEMC_IRQHandler -USDHC1_DriverIRQHandler -USDHC2_DriverIRQHandler -USB_OTG2_IRQHandler -USB_OTG1_IRQHandler -ENET_DriverIRQHandler -ENET_1588_Timer_DriverIRQHandler -XBAR1_IRQ_0_1_IRQHandler -XBAR1_IRQ_2_3_IRQHandler -ADC_ETC_IRQ0_IRQHandler -ADC_ETC_IRQ1_IRQHandler -ADC_ETC_IRQ2_IRQHandler -ADC_ETC_ERROR_IRQ_IRQHandler -PIT_IRQHandler -ACMP1_IRQHandler -ACMP2_IRQHandler -ACMP3_IRQHandler -ACMP4_IRQHandler -Reserved143_IRQHandler -Reserved144_IRQHandler -ENC1_IRQHandler -ENC2_IRQHandler -ENC3_IRQHandler -ENC4_IRQHandler -TMR1_IRQHandler -TMR2_IRQHandler -TMR3_IRQHandler -TMR4_IRQHandler -PWM2_0_IRQHandler -PWM2_1_IRQHandler -PWM2_2_IRQHandler -PWM2_3_IRQHandler -PWM2_FAULT_IRQHandler -PWM3_0_IRQHandler -PWM3_1_IRQHandler -PWM3_2_IRQHandler -PWM3_3_IRQHandler -PWM3_FAULT_IRQHandler -PWM4_0_IRQHandler -PWM4_1_IRQHandler -PWM4_2_IRQHandler -PWM4_3_IRQHandler -PWM4_FAULT_IRQHandler -Reserved168_IRQHandler -Reserved169_IRQHandler -Reserved170_IRQHandler -Reserved171_IRQHandler -Reserved172_IRQHandler -Reserved173_IRQHandler -SJC_ARM_DEBUG_IRQHandler -NMI_WAKEUP_IRQHandler -DefaultISR - B DefaultISR - - END diff --git a/bsp/imxrt1052-evk/Libraries/system_MIMXRT1052.c b/bsp/imxrt1052-evk/Libraries/system_MIMXRT1052.c deleted file mode 100644 index c9e37381b8..0000000000 --- a/bsp/imxrt1052-evk/Libraries/system_MIMXRT1052.c +++ /dev/null @@ -1,255 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVJ5B -** MIMXRT1052CVL5B -** MIMXRT1052DVJ6B -** MIMXRT1052DVL6B -** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: IMXRT1050RM Rev.1, 03/2018 -** Version: rev. 0.1, 2017-01-10 -** Build: b180509 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** The Clear BSD License -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without -** modification, are permitted (subject to the limitations in the -** disclaimer below) provided that the following conditions are met: -** -** * Redistributions of source code must retain the above copyright -** notice, this list of conditions and the following disclaimer. -** -** * Redistributions in binary form must reproduce the above copyright -** notice, this list of conditions and the following disclaimer in the -** documentation and/or other materials provided with the distribution. -** -** * Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from -** this software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 0.1 (2017-01-10) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file MIMXRT1052 - * @version 0.1 - * @date 2017-01-10 - * @brief Device specific configuration file for MIMXRT1052 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit (void) { -#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ -#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ - -#if defined(__MCUXPRESSO) - extern uint32_t g_pfnVectors[]; // Vector table defined in startup code - SCB->VTOR = (uint32_t)g_pfnVectors; -#endif - -/* Disable Watchdog Power Down Counter */ -WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK; -WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK; - -/* Watchdog disable */ - -#if (DISABLE_WDOG) - if (WDOG1->WCR & WDOG_WCR_WDE_MASK) - { - WDOG1->WCR &= ~WDOG_WCR_WDE_MASK; - } - if (WDOG2->WCR & WDOG_WCR_WDE_MASK) - { - WDOG2->WCR &= ~WDOG_WCR_WDE_MASK; - } - RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */ - RTWDOG->TOVAL = 0xFFFF; - RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK; -#endif /* (DISABLE_WDOG) */ - - /* Disable Systick which might be enabled by bootrom */ - if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) - { - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - } - -/* Enable instruction and data caches */ -#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT - if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) { - SCB_EnableICache(); - } -#endif -#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT - if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) { - SCB_EnableDCache(); - } -#endif - - SystemInitHook(); -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - - uint32_t freq; - uint32_t PLL1MainClock; - uint32_t PLL2MainClock; - - /* Periph_clk2_clk ---> Periph_clk */ - if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) - { - switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) - { - /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ - case CCM_CBCMR_PERIPH_CLK2_SEL(0U): - if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) - { - freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ? - CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; - } - else - { - freq = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); - } - break; - - /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ - case CCM_CBCMR_PERIPH_CLK2_SEL(1U): - freq = CPU_XTAL_CLK_HZ; - break; - - case CCM_CBCMR_PERIPH_CLK2_SEL(2U): - freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? - CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; - - case CCM_CBCMR_PERIPH_CLK2_SEL(3U): - default: - freq = 0U; - break; - } - - freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); - } - /* Pre_Periph_clk ---> Periph_clk */ - else - { - /* check if pll is bypassed */ - if(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) - { - PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ? - CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; - } - else - { - PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> - CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); - } - - /* check if pll is bypassed */ - if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) - { - PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? - CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; - } - else - { - PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U)); - } - PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); - - - switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) - { - /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */ - case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): - freq = PLL2MainClock; - break; - - /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */ - case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): - freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U; - break; - - /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */ - case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): - freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U; - break; - - /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */ - case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): - freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); - break; - - default: - freq = 0U; - break; - } - } - - SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U)); - -} - -/* ---------------------------------------------------------------------------- - -- SystemInitHook() - ---------------------------------------------------------------------------- */ - -__attribute__ ((weak)) void SystemInitHook (void) { - /* Void implementation of the weak function. */ -} diff --git a/bsp/imxrt1052-evk/Libraries/system_MIMXRT1052.h b/bsp/imxrt1052-evk/Libraries/system_MIMXRT1052.h deleted file mode 100644 index 8d9f2073d8..0000000000 --- a/bsp/imxrt1052-evk/Libraries/system_MIMXRT1052.h +++ /dev/null @@ -1,147 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1052CVJ5B -** MIMXRT1052CVL5B -** MIMXRT1052DVJ6B -** MIMXRT1052DVL6B -** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: IMXRT1050RM Rev.1, 03/2018 -** Version: rev. 0.1, 2017-01-10 -** Build: b180509 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** The Clear BSD License -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without -** modification, are permitted (subject to the limitations in the -** disclaimer below) provided that the following conditions are met: -** -** * Redistributions of source code must retain the above copyright -** notice, this list of conditions and the following disclaimer. -** -** * Redistributions in binary form must reproduce the above copyright -** notice, this list of conditions and the following disclaimer in the -** documentation and/or other materials provided with the distribution. -** -** * Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from -** this software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 0.1 (2017-01-10) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file MIMXRT1052 - * @version 0.1 - * @date 2017-01-10 - * @brief Device specific configuration file for MIMXRT1052 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_MIMXRT1052_H_ -#define _SYSTEM_MIMXRT1052_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -#ifndef DISABLE_WDOG - #define DISABLE_WDOG 1 -#endif - -/* Define clock source values */ - -#define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */ - -#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */ - /* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */ - -#define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_MIMXRT1052_H_ */ diff --git a/bsp/imxrt1052-evk/README.md b/bsp/imxrt1052-evk/README.md deleted file mode 100644 index 8f90f6f119..0000000000 --- a/bsp/imxrt1052-evk/README.md +++ /dev/null @@ -1,105 +0,0 @@ -# i.MX RT1050 - -## 1. 简介 - -i.MX RT 1050系列芯片，是由 NXP 半导体公司推出的跨界处理器芯片。它基于应用处理器的芯片架构，采用了微控制器的内核Cortex-M7，从而具有应用处理器的高性能及丰富的功能，又具备传统微控制器的易用、实时及低功耗的特性。 - -BSP默认支持的i.MX RT1052处理器具备以下简要的特性： - -| 介绍 | 描述 | -| ---- | ---- | -| 主CPU平台 | ARM Cortex-M7 | -| 最高频率 | 600MHz | -| 内部存储器 | 512KB SRAM | -| 外部存储器接口 | NAND、eMMC、QuadSPI NOR Flash 和 Parallel NOR Flash | - -## 2. 编译说明 - -i.MX RT1050板级包支持MDK5﹑IAR开发环境和GCC编译器，以下是具体版本信息： - -| IDE/编译器 | 已测试版本 | -| ---------- | --------- | -| MDK5 | MDK525 | -| IAR | IAR 8.11.3.13984 | -| GCC | GCC 5.4.1 20160919 (release) | - -## 3.BSP使用 - -### 3.1 配置工程 - -i.MX RT1052 BSP支持多块开发板，包括官方开发板MIMXRT1050-EVK，野火的i.MX RT1052开发板等。如果不是基于官方开发板，那么需要重新配置并生成工程： - -- 在bsp下打开env工具 -- 输入`menuconfig`命令，`RT1052 Board select (***)-->`选择正确的开发板。 -- 输入`scons --target=mdk5 -s`或`scons --target=iar`来生成需要的工程 - -### 3.2 下载和仿真 - -#### 3.2.1 MIMXRT1050-EVK - -EVK开发板有板载OpenSDA仿真器，仿真器还连接到i.MX RT1052的UART1。使用USB线连接电脑和仿真器的USB口(J28)，就可以进行下载和仿真。在终端工具里打开仿真器的虚拟串口。 - -#### 3.2.2 野火开发板 -连接外置仿真器（野火DAP仿真器或者Jlink）后，就可以进行下载和仿真。使用USB线连接开发板底板的USB转串口，在终端工具里打开相应的串口。 - -#### 3.2.3 ShareBoard开发板 - -连接外置仿真器Jlink后，就可以进行下载和仿真。使用USB线连接开发板底板的USB转串口，在终端工具里打开相应的串口。 - -#### 3.2.4 正点原子开发板 - -连接外置仿真器（正点原子DAP仿真器或者Jlink）后，就可以进行下载和仿真。使用USB线连接开发板底板的USB_232，在终端工具里打开相应的串口。 - -#### 3.2.5 SeeedStudio开发板 - -连接外置仿真器Jlink后，就可以进行下载和仿真。使用TTL转串口工具连接开发板上J3的17/18引脚，在终端工具里打开相应的串口。(17接RX，18接TX) - -### 3.3 运行结果 - -如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： - -``` - - \ | / -- RT - Thread Operating System - / | \ 3.0.4 build May 2 2018 - 2006 - 2018 Copyright by rt-thread team -lwIP-2.0.2 initialized! -using armcc, version: 5060750 -build time: May 2 2018 21:52:40 -msh />[PHY] wait autonegotiation complete... -SD card capacity 123904 KB -probe mmcsd block device! -found part[0], begin: 32256, size: 120.992MB -File System initialized! -[PHY] wait autonegotiation complete... -``` - -## 4. 驱动支持情况及计划 - -| 驱动 | 支持情况 | 备注 | -| ------ | ---- | ------ | -| UART | 支持 | UART 1~8 | -| GPIO | 支持 | | -| IIC | 支持 | IIC 1~4 | -| SPI | 支持 | SPI 1~4 | -| ETH | 支持 | 暂时仅支持官方的ETH | -| LCD | 支持 | | -| RTC | 支持 | | -| SDIO | 支持 | 暂时仅仅支持一个SDIO，还不支持中断方式 | -| SDRAM | 支持 | 32M SDRAM，后面2M作为Non Cache区域 | - -## 5. 联系人信息 - -维护人： - -- [tanek](https://github.com/TanekLiang) -- [liu2guang](https://github.com/liu2guang) - -## 6. 参考 - -- [MIMXRT1050-EVK: i.MX RT1050评估套件概述](https://www.nxp.com/cn/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK) -- [MIMXRT1050 EVK Board Hardware User’s Guide ](https://www.nxp.com/docs/en/user-guide/MIMXRT1050EVKHUG.pdf) -- [i.MX RT Series Crossover Processor Quick Start Guide](https://www.nxp.com/docs/en/user-guide/IMXRT1050EVKQSG.pdf) -- [i.MX RT Series Crossover Processor Fact Sheet](https://www.nxp.com/docs/en/fact-sheet/IMXRTSERIESFS.pdf) -- [Evaluation Kit Based on i.MX RT1050 Crossover Processors](https://www.nxp.com/docs/en/fact-sheet/IMXRT1050EVKFS.pdf) diff --git a/bsp/imxrt1052-evk/SConscript b/bsp/imxrt1052-evk/SConscript deleted file mode 100644 index fe0ae941ae..0000000000 --- a/bsp/imxrt1052-evk/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') - -cwd = str(Dir('#')) -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/imxrt1052-evk/SConstruct b/bsp/imxrt1052-evk/SConstruct deleted file mode 100644 index be5ba963ce..0000000000 --- a/bsp/imxrt1052-evk/SConstruct +++ /dev/null @@ -1,76 +0,0 @@ -import os -import sys -import rtconfig - - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -from building import * - -TARGET = 'rtthread-imxrt.' + rtconfig.TARGET_EXT - -if rtconfig.PLATFORM == 'armcc': - env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, - # overwrite cflags, because cflags has '--C99' - CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') -else: - env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, - CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') - -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM == 'iar': - env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -# make a building -DoBuilding(TARGET, objs) - -def Update_MDKFlashProgrammingAlgorithm(flash_dict): - import xml.etree.ElementTree as etree - from utils import xml_indent - - project_tree = etree.parse('project.uvoptx') - root = project_tree.getroot() - out = file('project.uvoptx', 'wb') - - for elem in project_tree.iterfind('.//Target/TargetOption/TargetDriverDllRegistry/SetRegEntry'): - Key = elem.find('Key') - if Key.text in flash_dict.keys(): - elem.find('Name').text = flash_dict[Key.text] - - xml_indent(root) - out.write(etree.tostring(root, encoding='utf-8')) - out.close() - -if GetOption('target') and GetDepend('BOARD_RT1050_FIRE'): - Update_MDKFlashProgrammingAlgorithm({ - "JL2CM3": '-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI-JP0 -JP0 -RST1 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000', - "CMSIS_AGDI": '-X"Any" -UAny -O974 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000', - }) -if GetOption('target') and GetDepend('BOARD_RT1050_ATK'): - Update_MDKFlashProgrammingAlgorithm({ - "JL2CM3": '-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI-JP0 -JP0 -RST1 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC8000 -FN1 -FF0MIMXRT105x_QuadSPI_4KB_SEC -FS060000000 -FL0800000', - "CMSIS_AGDI": '-X"Any" -UAny -O974 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC8000 -FN1 -FF0MIMXRT105x_QuadSPI_4KB_SEC -FS060000000 -FL0800000', - }) diff --git a/bsp/imxrt1052-evk/applications/SConscript b/bsp/imxrt1052-evk/applications/SConscript deleted file mode 100644 index 7725e3b910..0000000000 --- a/bsp/imxrt1052-evk/applications/SConscript +++ /dev/null @@ -1,17 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'applications') -src = Glob('*.c') -CPPPATH = [cwd, str(Dir('#'))] - -# add for startup script -if rtconfig.CROSS_TOOL == 'gcc': - CPPDEFINES = ['__START=entry'] -else: - CPPDEFINES = [] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) - -Return('group') diff --git a/bsp/imxrt1052-evk/applications/device_test.c b/bsp/imxrt1052-evk/applications/device_test.c deleted file mode 100644 index 337eb0dbd0..0000000000 --- a/bsp/imxrt1052-evk/applications/device_test.c +++ /dev/null @@ -1,517 +0,0 @@ -/* - * File : device_test.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE. - * - * Change Logs: - * Date Author Notes - * 2011-01-01 aozima the first version. - * 2012-02-11 aozima add multiple sector speed test. - * 2012-05-27 aozima use rt_deice API. - */ - -#include - -/* calculate speed */ -static void calculate_speed_print(rt_uint32_t speed) -{ - rt_uint32_t k,m; - - k = speed/1024UL; - if( k ) - { - m = k/1024UL; - if( m ) - { - rt_kprintf("%d.%dMbyte/s",m,k%1024UL*100/1024UL); - } - else - { - rt_kprintf("%d.%dKbyte/s",k,speed%1024UL*100/1024UL); - } - } - else - { - rt_kprintf("%dbyte/s",speed); - } -} - -static rt_err_t _block_device_test(rt_device_t device) -{ - rt_err_t result; - struct rt_device_blk_geometry geometry; - rt_uint8_t * read_buffer = RT_NULL; - rt_uint8_t * write_buffer = RT_NULL; - - rt_kprintf("\r\n"); - - if( (device->flag & RT_DEVICE_FLAG_RDWR) == RT_DEVICE_FLAG_RDWR ) - { - // device can read and write. - // step 1: open device - result = rt_device_open(device,RT_DEVICE_FLAG_RDWR); - if( result != RT_EOK ) - { - return result; - } - - // step 2: get device info - rt_memset(&geometry, 0, sizeof(geometry)); - result = rt_device_control(device, - RT_DEVICE_CTRL_BLK_GETGEOME, - &geometry); - if( result != RT_EOK ) - { - rt_kprintf("device : %s cmd RT_DEVICE_CTRL_BLK_GETGEOME failed.\r\n"); - return result; - } - rt_kprintf("device info:\r\n"); - rt_kprintf("sector size : %d byte\r\n", geometry.bytes_per_sector); - rt_kprintf("sector count : %d \r\n", geometry.sector_count); - rt_kprintf("block size : %d byte\r\n", geometry.block_size); - - rt_kprintf("\r\n"); - read_buffer = rt_malloc(geometry.bytes_per_sector); - if( read_buffer == RT_NULL ) - { - rt_kprintf("no memory for read_buffer!\r\n"); - goto __return; - } - write_buffer = rt_malloc(geometry.bytes_per_sector); - if( write_buffer == RT_NULL ) - { - rt_kprintf("no memory for write_buffer!\r\n"); - goto __return; - } - - /* step 3: R/W test */ - { - rt_uint32_t i,err_count, sector_no; - rt_uint8_t * data_point; - - i = rt_device_read(device, 0, read_buffer, 1); - if(i != 1) - { - rt_kprintf("read device :%s ", device->parent.name); - rt_kprintf("the first sector failed.\r\n"); - goto __return; - } - - data_point = write_buffer; - for(i=0; iparent.name); - rt_kprintf("the first sector failed.\r\n"); - rt_kprintf("maybe readonly!\r\n"); - goto __return; - } - - /* write the second sector */ - sector_no = 1; - data_point = write_buffer; - *data_point++ = (rt_uint8_t)sector_no; - i = rt_device_write(device,sector_no,write_buffer,1); - if( i != 1 ) - { - rt_kprintf("write device :%s ",device->parent.name); - rt_kprintf("the second sector failed.\r\n"); - goto __return; - } - - /* write the end sector */ - sector_no = geometry.sector_count-1; - data_point = write_buffer; - *data_point++ = (rt_uint8_t)sector_no; - i = rt_device_write(device,sector_no,write_buffer,1); - if( i != 1 ) - { - rt_kprintf("write device :%s ",device->parent.name); - rt_kprintf("the end sector failed.\r\n"); - goto __return; - } - - /* verify first sector */ - sector_no = 0; - i = rt_device_read(device,sector_no,read_buffer,1); - if( i != 1 ) - { - rt_kprintf("read device :%s ",device->parent.name); - rt_kprintf("the first sector failed.\r\n"); - goto __return; - } - err_count = 0; - data_point = read_buffer; - if( (*data_point++) != (rt_uint8_t)sector_no) - { - err_count++; - } - for(i=1; i 0 ) - { - rt_kprintf("verify device :%s ",device->parent.name); - rt_kprintf("the first sector failed.\r\n"); - goto __return; - } - - /* verify sector sector */ - sector_no = 1; - i = rt_device_read(device,sector_no,read_buffer,1); - if( i != 1 ) - { - rt_kprintf("read device :%s ",device->parent.name); - rt_kprintf("the second sector failed.\r\n"); - goto __return; - } - err_count = 0; - data_point = read_buffer; - if( (*data_point++) != (rt_uint8_t)sector_no) - { - err_count++; - } - for(i=1; i 0 ) - { - rt_kprintf("verify device :%s ",device->parent.name); - rt_kprintf("the second sector failed.\r\n"); - goto __return; - } - - /* verify the end sector */ - sector_no = geometry.sector_count-1; - i = rt_device_read(device,sector_no,read_buffer,1); - if( i != 1 ) - { - rt_kprintf("read device :%s ",device->parent.name); - rt_kprintf("the end sector failed.\r\n"); - goto __return; - } - err_count = 0; - data_point = read_buffer; - if( (*data_point++) != (rt_uint8_t)sector_no) - { - err_count++; - } - for(i=1; i 0 ) - { - rt_kprintf("verify device :%s ",device->parent.name); - rt_kprintf("the end sector failed.\r\n"); - goto __return; - } - rt_kprintf("device R/W test pass!\r\n"); - - } /* step 3: I/O R/W test */ - - rt_kprintf("\r\nRT_TICK_PER_SECOND:%d\r\n", RT_TICK_PER_SECOND); - - // step 4: continuous single sector speed test - { - rt_uint32_t tick_start,tick_end; - rt_uint32_t i; - - rt_kprintf("\r\ncontinuous single sector speed test:\r\n"); - - if( geometry.sector_count < 10 ) - { - rt_kprintf("device sector_count < 10, speed test abort!\r\n"); - } - else - { - unsigned int sector; - - // sign sector write - rt_kprintf("write: "); - sector = 0; - tick_start = rt_tick_get(); - for(i=0; i<200; i++) - { - sector += rt_device_write(device, i, read_buffer, 1); - if((i != 0) && ((i%4) == 0) ) - { - if(sector < 4) - { - rt_kprintf("#"); - } - else - { - rt_kprintf("<"); - } - sector = 0; - } - } - tick_end = rt_tick_get(); - rt_kprintf("\r\nwrite 200 sector from %d to %d, ",tick_start,tick_end); - calculate_speed_print( (geometry.bytes_per_sector*200UL*RT_TICK_PER_SECOND)/(tick_end-tick_start) ); - rt_kprintf("\r\n"); - - // sign sector read - rt_kprintf("read : "); - sector = 0; - tick_start = rt_tick_get(); - for(i=0; i<200; i++) - { - sector += rt_device_read(device, i, read_buffer, 1); - if((i != 0) && ((i%4) == 0) ) - { - if(sector < 4) - { - rt_kprintf("#"); - } - else - { - rt_kprintf(">"); - } - sector = 0; - } - } - tick_end = rt_tick_get(); - rt_kprintf("\r\nread 200 sector from %d to %d, ",tick_start,tick_end); - calculate_speed_print( (geometry.bytes_per_sector*200UL*RT_TICK_PER_SECOND)/(tick_end-tick_start) ); - rt_kprintf("\r\n"); - } - }// step 4: speed test - - // step 5: random single sector speed test - { - rt_uint32_t tick_start,tick_end; - rt_uint32_t i; - - rt_kprintf("\r\nrandom single sector speed test:\r\n"); - - if( geometry.sector_count < 10 ) - { - rt_kprintf("device sector_count < 10, speed test abort!\r\n"); - } - else - { - unsigned int sector; - - // sign sector write - rt_kprintf("write: "); - sector = 0; - tick_start = rt_tick_get(); - for(i=0; i<200; i++) - { - sector += rt_device_write(device, (geometry.sector_count / 10) * (i%10) + (i%10), read_buffer, 1); - if((i != 0) && ((i%4) == 0) ) - { - if(sector < 4) - { - rt_kprintf("#"); - } - else - { - rt_kprintf("<"); - } - sector = 0; - } - } - tick_end = rt_tick_get(); - rt_kprintf("\r\nwrite 200 sector from %d to %d, ",tick_start,tick_end); - calculate_speed_print( (geometry.bytes_per_sector*200UL*RT_TICK_PER_SECOND)/(tick_end-tick_start) ); - rt_kprintf("\r\n"); - - // sign sector read - rt_kprintf("read : "); - sector = 0; - tick_start = rt_tick_get(); - for(i=0; i<200; i++) - { - sector += rt_device_read(device, (geometry.sector_count / 10) * (i%10) + (i%10), read_buffer, 1); - if((i != 0) && ((i%4) == 0) ) - { - if(sector < 4) - { - rt_kprintf("#"); - } - else - { - rt_kprintf(">"); - } - sector = 0; - } - } - tick_end = rt_tick_get(); - rt_kprintf("\r\nread 200 sector from %d to %d, ",tick_start,tick_end); - calculate_speed_print( (geometry.bytes_per_sector*200UL*RT_TICK_PER_SECOND)/(tick_end-tick_start) ); - rt_kprintf("\r\n"); - } - }// step 4: speed test - - /* step 6: multiple sector speed test */ - { - rt_uint8_t * multiple_buffer; - rt_uint8_t * ptr; - rt_uint32_t tick_start,tick_end; - rt_uint32_t sector,i; - - rt_kprintf("\r\nmultiple sector speed test\r\n"); - - for(sector=2; sector<256; sector=sector*2) - { - multiple_buffer = rt_malloc(geometry.bytes_per_sector * sector); - - if(multiple_buffer == RT_NULL) - { - rt_kprintf("no memory for %d sector! multiple sector speed test abort!\r\n", sector); - break; - } - - rt_memset(multiple_buffer, sector, geometry.bytes_per_sector * sector); - rt_kprintf("write: "); - tick_start = rt_tick_get(); - for(i=0; i<10; i++) - { - rt_size_t n; - n = rt_device_write(device, 50, multiple_buffer, sector); - if(n == sector) - { - rt_kprintf("<"); - } - else - { - rt_kprintf("#"); - } - } - tick_end = rt_tick_get(); - rt_kprintf("\r\n"); - rt_kprintf("multiple write %d sector speed : ", sector); - calculate_speed_print( (geometry.bytes_per_sector * sector * 10 * RT_TICK_PER_SECOND)/(tick_end-tick_start) ); - rt_kprintf("\r\n"); - - rt_memset(multiple_buffer, ~sector, geometry.bytes_per_sector * sector); - rt_kprintf("read : "); - tick_start = rt_tick_get(); - for(i=0; i<10; i++) - { - rt_size_t n; - n = rt_device_read(device, 50, multiple_buffer, sector); - if(n == sector) - { - rt_kprintf(">"); - } - else - { - rt_kprintf("#"); - } - } - tick_end = rt_tick_get(); - rt_kprintf("\r\n"); - rt_kprintf("multiple read %d sector speed : ", sector); - calculate_speed_print( (geometry.bytes_per_sector * sector * 10 * RT_TICK_PER_SECOND)/(tick_end-tick_start) ); - - ptr = multiple_buffer; - for(i=0; iflag & RT_DEVICE_FLAG_ACTIVATED)) - { - rt_err_t result; - result = rt_device_init(device); - if (result != RT_EOK) - { - rt_kprintf("To initialize device:%s failed. The error code is %d\r\n", - device->parent.name, result); - return result; - } - else - { - device->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - } - - // step 3: device test - switch( device->type ) - { - case RT_Device_Class_Block : - rt_kprintf("block device!\r\n"); - return _block_device_test(device); - default: - rt_kprintf("unkown device type : %02X",device->type); - return RT_ERROR; - } -} - -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT(device_test, e.g: device_test("sd0")); -#endif - diff --git a/bsp/imxrt1052-evk/applications/lcd_init.c b/bsp/imxrt1052-evk/applications/lcd_init.c deleted file mode 100644 index be209338b3..0000000000 --- a/bsp/imxrt1052-evk/applications/lcd_init.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * File : lcd_init.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2018-06-12 Tanek first version - */ - -#include - -#if defined(PKG_USING_GUIENGINE) - -#include -int lcd_init(void) -{ - struct rt_device *device; - device = rt_device_find("lcd"); - if (device) - { - rtgui_graphic_set_device(device); - } - - return 0; -} -INIT_APP_EXPORT(lcd_init); -#endif diff --git a/bsp/imxrt1052-evk/applications/main.c b/bsp/imxrt1052-evk/applications/main.c deleted file mode 100644 index 8274fb4c7d..0000000000 --- a/bsp/imxrt1052-evk/applications/main.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2017-10-10 Tanek first version - */ - -#include -#include -#include - -#ifdef RT_USING_DFS -#include -#endif - -#ifdef RT_USING_DEVICE -#include -#endif - -#include - -void dump_clock(void) -{ - rt_kprintf("OSC clock : %d\n", CLOCK_GetFreq(kCLOCK_OscClk)); - rt_kprintf("RTC clock : %d\n", CLOCK_GetFreq(kCLOCK_RtcClk)); - rt_kprintf("CPU clock: %d\n", CLOCK_GetFreq(kCLOCK_CpuClk)); - rt_kprintf("AHB clock : %d\n", CLOCK_GetFreq(kCLOCK_AhbClk)); - rt_kprintf("SEMC clock : %d\n", CLOCK_GetFreq(kCLOCK_SemcClk)); - rt_kprintf("IPG clock : %d\n", CLOCK_GetFreq(kCLOCK_IpgClk)); - rt_kprintf("ARMPLLCLK(PLL1) : %d\n", CLOCK_GetFreq(kCLOCK_ArmPllClk)); - rt_kprintf("SYSPLLCLK(PLL2/528_PLL) : %d\n", CLOCK_GetFreq(kCLOCK_SysPllClk)); - rt_kprintf("SYSPLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk)); - rt_kprintf("SYSPLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk)); - rt_kprintf("SYSPLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk)); - rt_kprintf("SYSPLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk)); - rt_kprintf("USB1PLLCLK(PLL3) : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllClk)); - rt_kprintf("USB1PLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk)); - rt_kprintf("USB1PLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk)); - rt_kprintf("USB1PLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk)); - rt_kprintf("USB1PLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk)); - rt_kprintf("Audio PLLCLK(PLL4) : %d\n", CLOCK_GetFreq(kCLOCK_AudioPllClk)); - rt_kprintf("Video PLLCLK(PLL5) : %d\n", CLOCK_GetFreq(kCLOCK_VideoPllClk)); - rt_kprintf("Enet PLLCLK ref_enetpll0 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll0Clk)); - rt_kprintf("Enet PLLCLK ref_enetpll1 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll1Clk)); - rt_kprintf("USB2PLLCLK(PLL7) : %d\n", CLOCK_GetFreq(kCLOCK_Usb2PllClk)); -} - -void dump_cc_info(void) -{ -#if defined(__CC_ARM) - rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION); -#elif defined(__ICCARM__) - rt_kprintf("using iccarm, version: %d\n", __VER__); -#elif defined(__GNUC__) - rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__); -#endif -} - -void dump_link_info(void) -{ -#if defined(__CC_ARM) - -#elif defined(__ICCARM__) - -#elif defined(__GNUC__) - #define DUMP_SYMBOL(__SYM) \ - extern int __SYM; \ - rt_kprintf("%s: %p\n", #__SYM, &__SYM) - - DUMP_SYMBOL(__fsymtab_start); - DUMP_SYMBOL(__fsymtab_end); - DUMP_SYMBOL(__vsymtab_start); - DUMP_SYMBOL(__vsymtab_end); - DUMP_SYMBOL(__rt_init_start); - DUMP_SYMBOL(__rt_init_end); - - DUMP_SYMBOL(__exidx_start); - DUMP_SYMBOL(__exidx_end); - - DUMP_SYMBOL(__etext); - - DUMP_SYMBOL(__data_start__); - DUMP_SYMBOL(__data_end__); - - DUMP_SYMBOL(__noncachedata_start__); - DUMP_SYMBOL(__noncachedata_init_end__); - - DUMP_SYMBOL(__noncachedata_end__); - - DUMP_SYMBOL(__bss_start__); - DUMP_SYMBOL(__bss_end__); - - DUMP_SYMBOL(stack_start); - DUMP_SYMBOL(stack_end); - - DUMP_SYMBOL(heap_start); -#endif -} - -int main(void) -{ - rt_uint32_t result; - //dump_clock(); - dump_cc_info(); - dump_link_info(); - - rt_kprintf("build time: %s %s\n", __DATE__, __TIME__); - -#if defined(RT_USING_DFS) && defined(RT_USING_SDIO) - result = mmcsd_wait_cd_changed(RT_TICK_PER_SECOND); - if (result == MMCSD_HOST_PLUGED) - { - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - rt_kprintf("File System initialized!\n"); - else - rt_kprintf("File System init failed!\n"); - } - else - { - rt_kprintf("sdcard init fail or timeout: %d!\n", result); - } -#endif - - while (1) - { - rt_thread_delay(RT_TICK_PER_SECOND); - } -} - - - -/*@}*/ diff --git a/bsp/imxrt1052-evk/applications/mem_dump.c b/bsp/imxrt1052-evk/applications/mem_dump.c deleted file mode 100644 index ac209d62ad..0000000000 --- a/bsp/imxrt1052-evk/applications/mem_dump.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2017-12-05 Tanek first version - */ - -#include - -static void mem_dump(uint32_t buffer, uint32_t length) -{ - uint32_t *buf = (uint32_t *)buffer; - int i; - - for (i = 0; i < length / 4; i++) - { - rt_kprintf("0x%08X,", buf[i]); - - if (i % 8 == 7) - { - rt_kprintf("\n"); - } - else - { - rt_kprintf(" "); - } - } -} - -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT(mem_dump, dump memory); -#endif diff --git a/bsp/imxrt1052-evk/applications/mem_test.c b/bsp/imxrt1052-evk/applications/mem_test.c deleted file mode 100644 index 67726c84d6..0000000000 --- a/bsp/imxrt1052-evk/applications/mem_test.c +++ /dev/null @@ -1,103 +0,0 @@ -#include - -#include -#include - -void mem_test(uint32_t address, uint32_t size ) -{ - uint32_t i; - - rt_kprintf("memtest,address: 0x%08X size: 0x%08X\r\n", address, size); - - /**< 8bit test */ - { - uint8_t * p_uint8_t = (uint8_t *)address; - for(i=0; i -FINSH_FUNCTION_EXPORT(mem_test, mem_test(0xA0000000, 0x00100000) ); -#endif diff --git a/bsp/imxrt1052-evk/drivers/SConscript b/bsp/imxrt1052-evk/drivers/SConscript deleted file mode 100644 index 3c526c7453..0000000000 --- a/bsp/imxrt1052-evk/drivers/SConscript +++ /dev/null @@ -1,76 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'drivers') - -# add the general drivers. -src = Split(""" -board.c -drv_uart.c -drv_cache.c -""") - -CPPPATH = [cwd] -CPPDEFINES = [] - -# add sdram driver code -if GetDepend('RT_USING_SDRAM'): - src = src + ['drv_sdram.c'] - -# add pin driver code -if GetDepend('RT_USING_PIN'): - src += ['drv_pin.c'] - -# add rtc driver code -if GetDepend('RT_USING_RTC_HP'): - src = src + ['drv_rtc.c'] - -# add spibus driver code -if GetDepend('RT_USING_SPI'): - src += ['drv_spi_bus.c'] - -# add spi flash driver code -if GetDepend('RT_USING_SPI_FLASH'): - src += ['drv_spi_flash.c'] - -# add i2cbus driver code -if GetDepend('RT_USING_I2C'): - src += ['drv_i2c.c'] - -# add lcd driver code -if GetDepend('RT_USING_LCD'): - src += ['drv_lcd.c'] - if GetDepend('BOARD_RT1050_EVK') and GetDepend('PKG_USING_GUIENGINE'): - src += ['drv_ft5406.c'] - -# add sdio driver code -if GetDepend('RT_USING_SDIO'): - src += ['drv_sdio.c'] - -# add usb device driver code -if GetDepend('RT_USING_USB_DEVICE'): - src += ['drv_usbd.c'] - src += Glob('usb/device/*.c') -# add usb phy driver code -if GetDepend('RT_USING_USB_DEVICE'): - src += Glob('usb/phy/*.c') - CPPDEFINES += ['ENDIANNESS'] - -if GetDepend('BOARD_RT1050_EVK') or GetDepend('BOARD_RT1050_SeeedStudio'): - if GetDepend('RT_USING_LWIP'): - src += ['drv_eth.c', 'fsl_phy.c'] - CPPDEFINES += ['FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE'] - -if GetDepend('BOARD_RT1050_FIRE') and GetDepend('RT_USING_LWIP'): - src += ['drv_eth.c', 'fsl_phy.c'] - -if GetDepend('BOARD_RT1050_ATK') and GetDepend('RT_USING_LWIP'): - src += ['drv_eth.c', 'fsl_phy.c', 'drv_pcf8574.c'] - -if GetDepend('RT_USING_AUDIO'): - src += ['drv_codec.c', 'fsl_wm8960.c'] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) - -Return('group') diff --git a/bsp/imxrt1052-evk/drivers/board.c b/bsp/imxrt1052-evk/drivers/board.c deleted file mode 100644 index a604df6d4c..0000000000 --- a/bsp/imxrt1052-evk/drivers/board.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard first implementation - */ -#include -#include -#include - -#include "board.h" -#include "drv_uart.h" - -#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) -static struct rt_memheap system_heap; -#endif - -/* ARM PLL configuration for RUN mode */ -const clock_arm_pll_config_t armPllConfig = { .loopDivider = 100U }; - -/* SYS PLL configuration for RUN mode */ -const clock_sys_pll_config_t sysPllConfig = { .loopDivider = 1U }; - -/* USB1 PLL configuration for RUN mode */ -const clock_usb_pll_config_t usb1PllConfig = { .loopDivider = 0U }; - -static void BOARD_BootClockGate(void) -{ -// /* Disable all unused peripheral clock */ -// CCM->CCGR0 = 0x00C0000FU; -// CCM->CCGR1 = 0x30000000U; -// CCM->CCGR2 = 0x003F0030U; -// CCM->CCGR3 = 0xF0000330U; -// CCM->CCGR4 = 0x0000FF3CU; -// CCM->CCGR5 = 0xF000330FU; -// CCM->CCGR6 = 0x00FC0300U; -} - -static void BOARD_BootClockRUN(void) -{ - /* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */ - CLOCK_SetXtalFreq(24000000U); - CLOCK_SetRtcXtalFreq(32768U); - - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - - /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz */ - DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); - - CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */ -#ifndef SKIP_SYSCLK_INIT - CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */ -#endif -#ifndef SKIP_USB_PLL_INIT - CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */ -#endif - CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */ - - CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */ - - /* Disable unused clock */ - BOARD_BootClockGate(); - - /* Power down all unused PLL */ - CLOCK_DeinitAudioPll(); - CLOCK_DeinitVideoPll(); - CLOCK_DeinitEnetPll(); - CLOCK_DeinitUsb2Pll(); - - /* iomuxc clock (iomuxc_clk_enable): 0x03u */ - CLOCK_EnableClock(kCLOCK_Iomuxc); - - /* Update core clock */ - SystemCoreClockUpdate(); -} - - -/* MPU configuration. */ -static void BOARD_ConfigMPU(void) -{ - /* Disable I cache and D cache */ - SCB_DisableICache(); - SCB_DisableDCache(); - - /* Disable MPU */ - ARM_MPU_Disable(); - - /* Region 0 setting */ - MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); - - /* Region 1 setting */ - MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); - - /* Region 2 setting */ - // spi flash: normal type, cacheable, no bufferable, no shareable - MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB); - - /* Region 3 setting */ - MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); - - /* Region 4 setting */ - MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); - - /* Region 5 setting */ - MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); - - /* Region 6 setting */ - MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); - -#if defined(SDRAM_MPU_INIT) - /* Region 7 setting */ - MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); - - /* Region 8 setting */ - MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); -#endif - - /* Enable MPU */ - ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); - - /* Enable I cache and D cache */ - SCB_EnableDCache(); - SCB_EnableICache(); -} - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -void SystemInitHook(void) -{ - BOARD_ConfigMPU(); - -#if defined(RT_USING_SDRAM) - extern int imxrt_sdram_init(void); - imxrt_sdram_init(); -#endif -} - -/** - * This function will initial rt1050 board. - */ -void rt_hw_board_init() -{ - BOARD_BootClockRUN(); - - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif - -#ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - -#ifdef RT_USING_HEAP - -#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) - rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END); - rt_system_heap_init((void *)SDRAM_BEGIN, (void *)SDRAM_END); - - rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); - rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE); -#else - rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); -#endif - -#endif -} - -/*@}*/ diff --git a/bsp/imxrt1052-evk/drivers/board.h b/bsp/imxrt1052-evk/drivers/board.h deleted file mode 100644 index 80a61f1a3a..0000000000 --- a/bsp/imxrt1052-evk/drivers/board.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - */ - -// <<< Use Configuration Wizard in Context Menu >>> -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include -#include -#include - -#ifdef __CC_ARM -extern int Image$$RTT_HEAP$$ZI$$Base; -extern int Image$$RTT_HEAP$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base) -#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit) - -#elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) -extern void __RTT_HEAP_END; -#define HEAP_END (&__RTT_HEAP_END) - -#else -extern int heap_start; -extern int heap_end; -#define HEAP_BEGIN (&heap_start) -#define HEAP_END (&heap_end) -#endif - -#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN) - -#define SDRAM_MPU_INIT -#define SDRAM_BEGIN (0x80000000u) -#define SDRAM_END (0x81E00000u) - -void rt_hw_board_init(void); - -#endif - -//*** <<< end of configuration section >>> *** diff --git a/bsp/imxrt1052-evk/drivers/drv_cache.c b/bsp/imxrt1052-evk/drivers/drv_cache.c deleted file mode 100644 index 5cc68c50dc..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_cache.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * File : drv_cache.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2018-04-02 tanek first implementation - */ - -#include -#include -#include - -void rt_hw_cpu_icache_enable(void) -{ - SCB_EnableICache(); -} - -void rt_hw_cpu_icache_disable(void) -{ - SCB_DisableICache(); -} - -rt_base_t rt_hw_cpu_icache_status(void) -{ - return 0; -} - -void rt_hw_cpu_icache_ops(int ops, void* addr, int size) -{ - if (ops & RT_HW_CACHE_INVALIDATE) - { - ICACHE_InvalidateByRange((uint32_t)addr, size); - } -} - -void rt_hw_cpu_dcache_enable(void) -{ - SCB_EnableDCache(); -} - -void rt_hw_cpu_dcache_disable(void) -{ - SCB_DisableDCache(); -} - -rt_base_t rt_hw_cpu_dcache_status(void) -{ - return 0; -} - -void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) -{ - if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE)) - { - DCACHE_CleanInvalidateByRange((uint32_t)addr, size); - } - else if (ops & RT_HW_CACHE_FLUSH) - { - DCACHE_CleanByRange((uint32_t)addr, size); - } - else if (ops & RT_HW_CACHE_INVALIDATE) - { - DCACHE_InvalidateByRange((uint32_t)addr, size); - } - else - { - RT_ASSERT(0); - } -} diff --git a/bsp/imxrt1052-evk/drivers/drv_codec.c b/bsp/imxrt1052-evk/drivers/drv_codec.c deleted file mode 100644 index fe1924fed4..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_codec.c +++ /dev/null @@ -1,395 +0,0 @@ -#include -#include -#include - -#include "board.h" -#include "drv_codec.h" -#include "fsl_wm8960.h" - -#include -#include -#include -#include - -#define DEMO_CODEC_WM8960 -#define DEMO_SAI SAI1 -#define DEMO_SAI_IRQ SAI1_IRQn -#define SAI_TxIRQHandler SAI1_IRQHandler - -/* Select Audio/Video PLL (786.48 MHz) as sai1 clock source */ -#define DEMO_SAI1_CLOCK_SOURCE_SELECT (2U) -/* Clock pre divider for sai1 clock source */ -#define DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER (1U) -/* Clock divider for sai1 clock source */ -#define DEMO_SAI1_CLOCK_SOURCE_DIVIDER (63U) -/* Get frequency of sai1 clock */ -#define DEMO_SAI_CLK_FREQ (CLOCK_GetFreq(kCLOCK_AudioPllClk) / (DEMO_SAI1_CLOCK_SOURCE_DIVIDER + 1U) / (DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER + 1U)) - -/* I2C instance and clock */ -#define DEMO_I2C LPI2C1 - -/* Select USB1 PLL (480 MHz) as master lpi2c clock source */ -#define DEMO_LPI2C_CLOCK_SOURCE_SELECT (0U) -/* Clock divider for master lpi2c clock source */ -#define DEMO_LPI2C_CLOCK_SOURCE_DIVIDER (5U) -/* Get frequency of lpi2c clock */ -#define DEMO_I2C_CLK_FREQ ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (DEMO_LPI2C_CLOCK_SOURCE_DIVIDER + 1U)) - -/* DMA */ -#define DMAMUX0 DMAMUX -#define EXAMPLE_DMA DMA0 -#define EXAMPLE_CHANNEL (0U) -#define EXAMPLE_SAI_TX_SOURCE kDmaRequestMuxSai1Tx - -struct imxcodec -{ - I2S_Type *sai; - sai_edma_handle_t txHandle; - wm8960_handle_t codecHandle; - edma_handle_t dmaHandle; - lpi2c_master_handle_t i2cHandle; - sai_transfer_format_t format; -}; - -static void _InitPins(void) -{ - CLOCK_EnableClock(kCLOCK_Iomuxc); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1); - - IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0xD8B0u); - IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0u); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 1U); - - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 0x10B0u); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 0x10B0u); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 0x10B0u); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 0x10B0u); -} - -static void BOARD_EnableSaiMclkOutput(bool enable) -{ - if (enable) - { - IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK; - } - else - { - IOMUXC_GPR->GPR1 &= (~IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK); - } -} - -static void saidma_callback(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData) -{ - int ind = 0; - rt_uint8_t *saddr; - - ind = handle->queueDriver; - saddr = (rt_uint8_t*)handle->saiQueue[ind].data; - rt_audio_tx_complete(userData, saddr); -} - -/********************************************************************************************************* -** Audio device -*********************************************************************************************************/ - -static rt_err_t icodec_getcaps(struct rt_audio_device *audio,struct rt_audio_caps *caps) -{ - rt_err_t result = RT_EOK; - struct imxcodec *icodec = (struct imxcodec *)audio->parent.user_data; - - switch (caps->main_type) - { - case AUDIO_TYPE_QUERY: /* qurey the types of hw_codec device */ - { - switch (caps->sub_type) - { - case AUDIO_TYPE_QUERY: - caps->udata.mask = AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER; - break; - default: - result = -RT_ERROR; - break; - } - - break; - } - case AUDIO_TYPE_OUTPUT: /* Provide capabilities of OUTPUT unit */ - switch (caps->sub_type) - { - case AUDIO_DSP_PARAM: - if (audio->replay == NULL) - { - result = -RT_ERROR; - break; - } - caps->udata.config.channels = 1; - caps->udata.config.samplefmt = 1; - caps->udata.config.samplerate = 1; - caps->udata.config.samplefmts = 1; - break; - default: - result = -RT_ERROR; - break; - } - break; - case AUDIO_TYPE_MIXER: /* report the Mixer Units */ - switch (caps->sub_type) - { - case AUDIO_MIXER_QUERY: - caps->udata.mask = AUDIO_MIXER_VOLUME | AUDIO_MIXER_DIGITAL | AUDIO_MIXER_LINE; - break; - case AUDIO_MIXER_VOLUME: - caps->udata.value = WM8960_GetVolume(&icodec->codecHandle, kWM8960_ModuleDAC); - break; - case AUDIO_MIXER_DIGITAL: - - break; - case AUDIO_MIXER_LINE: - - break; - default: - result = -RT_ERROR; - break; - } - break; - default: - result = -RT_ERROR; - break; - } - - return result; -} - -static rt_err_t icodec_configure(struct rt_audio_device *audio,struct rt_audio_caps *caps) -{ - rt_err_t result = RT_EOK; - struct imxcodec *icodec = (struct imxcodec *)audio->parent.user_data; - - switch (caps->main_type) - { - case AUDIO_TYPE_MIXER: - { - switch (caps->sub_type) - { - case AUDIO_MIXER_VOLUME: - { - WM8960_SetVolume(&icodec->codecHandle, kWM8960_ModuleDAC, - caps->udata.value); - } - break; - default: - { - result = -RT_ERROR; - } - break; - } - } - break; - case AUDIO_TYPE_OUTPUT: - { - switch (caps->sub_type) - { - case AUDIO_DSP_PARAM: - { - - } break; - case AUDIO_DSP_SAMPLERATE: - { - int rate = caps->udata.value; - - icodec->format.sampleRate_Hz = rate; - SAI_TxSetFormat(icodec->sai, &icodec->format, icodec->format.masterClockHz, icodec->format.masterClockHz); - } - break; - default: - { - result = -RT_ERROR; - } - break; - } - } - break; - default: - result = -RT_ERROR; - break; - } - - return result; -} - -static rt_err_t icodec_init(struct rt_audio_device *audio) -{ - sai_config_t config; - uint32_t mclkSourceClockHz = 0U; - edma_config_t dmaConfig = {0}; - lpi2c_master_config_t i2cConfig = {0}; - uint32_t i2cSourceClock; - clock_audio_pll_config_t audioPllConfig = {32, 1, 77, 100}; - struct imxcodec *icodec = audio->parent.user_data; - sai_transfer_format_t *format; - - icodec->sai = DEMO_SAI; - format = &icodec->format; - - _InitPins(); - CLOCK_InitAudioPll(&audioPllConfig); - - /*Clock setting for LPI2C*/ - CLOCK_SetMux(kCLOCK_Lpi2cMux, DEMO_LPI2C_CLOCK_SOURCE_SELECT); - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, DEMO_LPI2C_CLOCK_SOURCE_DIVIDER); - - /*Clock setting for SAI1*/ - CLOCK_SetMux(kCLOCK_Sai1Mux, DEMO_SAI1_CLOCK_SOURCE_SELECT); - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER); - CLOCK_SetDiv(kCLOCK_Sai1Div, DEMO_SAI1_CLOCK_SOURCE_DIVIDER); - - /*Enable MCLK clock*/ - BOARD_EnableSaiMclkOutput(true); - - /* Create EDMA handle */ - EDMA_GetDefaultConfig(&dmaConfig); - EDMA_Init(EXAMPLE_DMA, &dmaConfig); - EDMA_CreateHandle(&icodec->dmaHandle, EXAMPLE_DMA, EXAMPLE_CHANNEL); - - DMAMUX_Init(DMAMUX0); - DMAMUX_SetSource(DMAMUX0, EXAMPLE_CHANNEL, EXAMPLE_SAI_TX_SOURCE); - DMAMUX_EnableChannel(DMAMUX0, EXAMPLE_CHANNEL); - - /* Init SAI module */ - SAI_TxGetDefaultConfig(&config); - config.protocol = kSAI_BusLeftJustified; - SAI_TxInit(DEMO_SAI, &config); - - /* Configure the audio format */ - format->bitWidth = kSAI_WordWidth16bits; - format->channel = 0U; - format->sampleRate_Hz = kSAI_SampleRate48KHz; - format->masterClockHz = DEMO_SAI_CLK_FREQ; - format->protocol = config.protocol; - format->stereo = kSAI_Stereo; - format->isFrameSyncCompact = 0; - format->watermark = FSL_FEATURE_SAI_FIFO_COUNT / 2U; - - /* Configure Sgtl5000 I2C */ - icodec->codecHandle.base = DEMO_I2C; - icodec->codecHandle.i2cHandle = &icodec->i2cHandle; - i2cSourceClock = DEMO_I2C_CLK_FREQ; - - LPI2C_MasterGetDefaultConfig(&i2cConfig); - LPI2C_MasterInit(DEMO_I2C, &i2cConfig, i2cSourceClock); - LPI2C_MasterTransferCreateHandle(DEMO_I2C, &icodec->i2cHandle, NULL, NULL); - - WM8960_Init(&icodec->codecHandle, NULL); - WM8960_ConfigDataFormat(&icodec->codecHandle, format->masterClockHz, format->sampleRate_Hz, format->bitWidth); - - SAI_TransferTxCreateHandleEDMA(icodec->sai, &icodec->txHandle, saidma_callback, audio, &icodec->dmaHandle); - - mclkSourceClockHz = DEMO_SAI_CLK_FREQ; - SAI_TransferTxSetFormatEDMA(icodec->sai, &icodec->txHandle, format, mclkSourceClockHz, format->masterClockHz); - - return RT_EOK; -} - -static rt_err_t icodec_shutdown(struct rt_audio_device *audio) -{ - return RT_EOK; -} - -rt_err_t icodec_start(struct rt_audio_device *audio,int stream) -{ - return RT_EOK; -} - -rt_err_t icodec_stop(struct rt_audio_device *audio,int stream) -{ - return RT_EOK; -} - -static rt_err_t icodec_suspend(struct rt_audio_device *audio,int stream) -{ - return RT_EOK; -} - -static rt_err_t icodec_resume(struct rt_audio_device *audio,int stream) -{ - return RT_EOK; -} - -static rt_err_t icodec_control (struct rt_audio_device *audio, int cmd, void *args) -{ - rt_err_t result = RT_EOK; - - switch (cmd) - { - case AUDIO_CTL_HWRESET: - - break; - default: - result = -RT_ERROR; - break; - } - - return result; -} - -static rt_size_t icodec_transmit(struct rt_audio_device *audio, const void *writeBuf, void *readBuf, rt_size_t size) -{ - struct imxcodec *icodec = (struct imxcodec *)audio->parent.user_data; - - if(writeBuf != RT_NULL) - { - sai_transfer_t xfer; - - xfer.data = (uint8_t *)writeBuf; - xfer.dataSize = size; - if (size%32 == 0) - icodec->txHandle.count = 16; - else - icodec->txHandle.count = 1; - - rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void*)writeBuf, size); - if (SAI_TransferSendEDMA(icodec->sai, &icodec->txHandle, &xfer) != kStatus_Success) - return 0; - - return size; - } - - return 0; -} - -static struct imxcodec _g_imxcodec; -static struct rt_audio_device _g_audio_device; -const struct rt_audio_ops _g_audio_ops = -{ - .getcaps = icodec_getcaps, - .configure = icodec_configure, - - .init = icodec_init, - .shutdown = icodec_shutdown, - .start = icodec_start, - .stop = icodec_stop, - .suspend = icodec_suspend, - .resume = icodec_resume, - .control = icodec_control, - - .transmit = icodec_transmit, -}; - -int rt_hw_codec_init(void) -{ - int result; - struct rt_audio_device *audio = &_g_audio_device; - - audio->ops = (struct rt_audio_ops*)&_g_audio_ops; - _g_imxcodec.sai = DEMO_SAI; - result = rt_audio_register(audio,"sound0", RT_DEVICE_FLAG_WRONLY, &_g_imxcodec); - - return result; -} -INIT_DEVICE_EXPORT(rt_hw_codec_init); diff --git a/bsp/imxrt1052-evk/drivers/drv_codec.h b/bsp/imxrt1052-evk/drivers/drv_codec.h deleted file mode 100644 index 6ee6c354e9..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_codec.h +++ /dev/null @@ -1,228 +0,0 @@ -#ifndef __DRV_CODEC_H__ -#define __DRV_CODEC_H__ - -#define SUNXI_DAC_DPC 0x00 -#define SUNXI_DAC_FIFOC 0x04 -#define SUNXI_DAC_FIFOS 0x08 -#define SUNXI_DAC_TXDATA 0x0c -#define SUNXI_ADC_FIFOC 0x10 -#define SUNXI_ADC_FIFOS 0x14 -#define SUNXI_ADC_RXDATA 0x18 -#define DAC_MIXER_CTRL 0x20 -#define ADC_MIXER_CTRL 0x24 -#define ADDA_TUNE 0x28 -#define BIAS_DA16_CAL_CTRL0 0x2C -#define BIAS_DA16_CAL_CTRL1 0x34 - -#define SUNXI_DAC_CNT 0x40 -#define SUNXI_ADC_CNT 0x44 -#define SUNXI_DAC_DG 0x48 -#define SUNXI_ADC_DG 0x4c - -#define AC_PR_CFG 0x400 - -/*AC_DAC_DPC:0x00*/ -#define EN_DAC 31 -#define MODQU 25 -#define DWA 24 -#define HPF_EN 18 -#define DVOL 12 -/*#define HUB_EN 0 */ - -/*AC_DAC_FIFOC:0x04*/ -#define DAC_FS 29 -#define FIR_VER 28 -#define SEND_LASAT 26 -#define FIFO_MODE 24 -#define DAC_DRQ_CLR_CNT 21 -#define TX_TRIG_LEVEL 8 -#define ADDA_LOOP_EN 7 -#define DAC_MONO_EN 6 -#define TX_SAMPLE_BITS 5 -#define DAC_DRQ_EN 4 -#define DAC_IRQ_EN 3 -#define FIFO_UNDERRUN_IRQ_EN 2 -#define FIFO_OVERRUN_IRQ_EN 1 -#define FIFO_FLUSH 0 - -/*AC_ADC_FIFOC:0x10*/ -#define ADFS 29 -#define EN_AD 28 -#define RX_FIFO_MODE 24 -#define ADCDFEN 16 -#define RX_FIFO_TRG_LEVEL 8 -#define ADC_MONO_EN 7 -#define RX_SAMPLE_BITS 6 -#define ADC_DRQ_EN 4 -#define ADC_IRQ_EN 3 -#define ADC_OVERRUN_IRQ_EN 1 -#define ADC_FIFO_FLUSH 0 - - -/*DAC_MIXER_CTRL: 0x20*/ -#define DAC_AG_R_EN 31 /* dac right enable bit */ -#define DAC_AG_L_EN 30 /* dac left enable bit */ -#define R_MIXER_EN 29 /* right output mixer */ -#define L_MIXER_EN 28 /* left output mixer */ -#define PH_R_MUTE 27 /* headphone right mute */ -#define PH_L_MUTE 26 /* headphone left mute */ -#define PH_R_PWR_SLT 25 -#define PH_L_PWR_SLT 24 -#define PH_COM_FC 22 -#define PH_COM_PROTEC 21 -#define R_MIXER_MUTE_MIC 20 -#define R_MIXER_MUTE_LINEIN 19 -#define R_MIXER_MUTE_FM 18 -#define R_MIXER_MUTE_R_DAC 17 -#define R_MIXER_MUTE_L_DAC 16 -#define R_MIXER_MUTE 16 -#define HP_POWER_EN 15 -#define L_MIXER_MUTE_MIC 12 -#define L_MIXER_MUTE_LINEIN 11 -#define L_MIXER_MUTE_FM 10 -#define L_MIXER_MUTE_R_DAC 9 -#define L_MIXER_MUTE_L_DAC 8 -#define L_MIXER_MUTE 8 -#define L_HP_TO_R_HP_MUTE 7 -#define R_HP_TO_L_HP_MUTE 6 -#define HP_VOL 0 - -/*ADC_MIXER_CTRL: 0x24*/ -#define ADC_EN 31 /* adc enable bit */ -/* mic in boost stage to L or R output mixer gain control */ -#define MIC_GAIN_CTL 24 -#define LINEIN_VOL 21 /* right output mixer */ -#define ADC_IN_GAIN_CTL 16 /* adc input gain control */ -#define COS_SLOP_TM 14 /* COS slop time control for Anti-pop */ -#define ADC_MIX_MUTE_MIC 13 -#define ADC_MIX_MUTE_FML 12 -#define ADC_MIX_MUTE_FMR 11 -#define ADC_MIX_MUTE_LINEIN 10 -#define ADC_MIX_MUTE_L 9 -#define ADC_MIX_MUTE_R 8 -#define ADC_MIX_MUTE 8 /* ADC mixer mute control */ -#define PA_SPEED_SLT 7 /* PA speed select->0: normal 1: fast */ -#define FM_TO_MIX_GAIN 4 /* FMin to mixer gain control */ -#define MIC_BST_AMP_EN 3 /* MIC boost AMP enable */ -#define MIC_BOST_GAIN 0 /* MIC boast AMP gain control */ - -/*AC_ADC_TXDATA:0x20*/ -#define TX_DATA 0 - -/*AC_DAC_CNT:0x40*/ -#define TX_CNT 0 - -/*AC_ADC_CNT:0x44*/ -#define RX_CNT 0 - -/*AC_DAC_DG:0x48*/ -/* -* DAC Modulator Debug -* 0:DAC Modulator Normal Mode -* 1:DAC Modulator Debug Mode -*/ -#define DAC_MODU_SELECT 11 -/* -* DAC Pattern Select -* 00:Normal(Audio sample from TX fifo) -* 01: -6 dB sin wave -* 10: -60 dB sin wave -* 11: silent wave -*/ -#define DAC_PATTERN_SELECT 9 -/* -* CODEC Clock Source Select -* 0:codec clock from PLL -* 1:codec clock from OSC(for debug) -*/ -#define CODEC_CLK_SELECT 8 -/* -* DAC output channel swap enable -* 0:disable -* 1:enable -*/ -#define DA_SWP 6 - -/*AC_ADC_DG:0x4c*/ -#define AD_SWP 24 - -/*AC_PR_CFG:0x400*/ -#define AC_PR_RST 28 -#define AC_PR_RW 24 -#define AC_PR_ADDR 16 -#define ADDA_PR_WDAT 8 -#define ADDA_PR_RDAT 0 - - - -/* 时钟配置相关寄存器 */ -#define R6_REG_CCU_BASE 0x01c20000 -#define R6_REG_PLL_AUDIO_CTRL (R6_REG_CCU_BASE + 0x008) -#define R6_REG_BUS_CLK_GATING_0 (R6_REG_CCU_BASE + 0x060) -#define R6_REG_BUS_CLK_GATING_1 (R6_REG_CCU_BASE + 0x064) -#define R6_REG_BUS_CLK_GATING_2 (R6_REG_CCU_BASE + 0x068) -#define R6_REG_AUDIO_CODEC_CLK (R6_REG_CCU_BASE + 0x140) -#define R6_REG_BUS_SOFT_RST_0 (R6_REG_CCU_BASE + 0x02C0) -#define R6_REG_BUS_SOFT_RST_1 (R6_REG_CCU_BASE + 0x02C4) -#define R6_REG_BUS_SOFT_RST_2 (R6_REG_CCU_BASE + 0x02D0) - -/* GPIO配置相关寄存器 */ -#define R6_REG_PIO_BASE 0x01c20800 -#define R6_REG_PD_CFG0 (R6_REG_PIO_BASE + (3 * 0x24 + 0X00)) -#define R6_REG_PD_CFG1 (R6_REG_PIO_BASE + (3 * 0x24 + 0X04)) -#define R6_REG_PD_CFG2 (R6_REG_PIO_BASE + (3 * 0x24 + 0X08)) -#define R6_REG_PD_CFG3 (R6_REG_PIO_BASE + (3 * 0x24 + 0X0c)) -#define R6_REG_PD_DATA (R6_REG_PIO_BASE + (3 * 0x24 + 0X10)) -#define R6_REG_PD_DRV0 (R6_REG_PIO_BASE + (3 * 0x24 + 0X14)) -#define R6_REG_PD_DRV1 (R6_REG_PIO_BASE + (3 * 0x24 + 0X18)) -#define R6_REG_PD_PUL0 (R6_REG_PIO_BASE + (3 * 0x24 + 0X1c)) -#define R6_REG_PD_PUL1 (R6_REG_PIO_BASE + (3 * 0x24 + 0X20)) - - -/* AUDIO配置相关寄存器 */ -#define R6_REG_AC_BASE 0x01c23c00 -#define R6_REG_AC_DAC_DPC (R6_REG_AC_BASE + 0x00) -#define R6_REG_AC_DAC_FIFOC (R6_REG_AC_BASE + 0x04) -#define R6_REG_AC_DAC_FIFOS (R6_REG_AC_BASE + 0x08) -#define R6_REG_AC_DAC_TXDADA (R6_REG_AC_BASE + 0x0c) -#define R6_REG_AC_ADC_FIFOC (R6_REG_AC_BASE + 0x10) -#define R6_REG_AC_ADC_FIFOS (R6_REG_AC_BASE + 0x14) -#define R6_REG_AC_ADC_RXDADA (R6_REG_AC_BASE + 0x18) -#define R6_REG_DAC_MIXER_CTRL (R6_REG_AC_BASE + 0x20) -#define R6_REG_ADC_MIXER_CTRL (R6_REG_AC_BASE + 0x24) -#define R6_REG_AC_DAC_CNT (R6_REG_AC_BASE + 0x40) - -/* DMA配置相关寄存器 */ -#define R6_REG_NDMA_0_BASE (0x01c02000 + 0x100 + 0 * 0x20) - -#define R6_REG_DMA_INT_CTRL (0x01c02000 + 0x00) -#define R6_REG_DMA_INT_STA (0x01c02000 + 0x04) -#define R6_REG_DMA_PTY_CFG (0x01c02000 + 0x08) -#define REG_NDMA_CFG (0x0) -#define REG_NDMA_SRC_ADR (0x4) -#define REG_NDMA_DES_ADR (0x8) -#define REG_NDMA_BYTE_CNT (0xc) -// #define REG_NDMA_PAR (0x300 + 0x1c) - - -#define NDMA_CFG_SRC_DRQ_IR_RX (0x00 << 0) -#define NDMA_CFG_SRC_DRQ_NONE (0x01 << 0) -#define NDMA_CFG_SRC_DRQ_SDRAM (0x11 << 0) - -#define NDMA_CFG_DST_LINEAR (0x00 << 21) - -#define NDMA_CFG_DST_DRQ_IR_RX (0x00 << 16) -#define NDMA_CFG_DST_DRQ_NONE (0x01 << 16) -#define NDMA_CFG_DST_DRQ_SRAM (0x10 << 16) -#define NDMA_CFG_DST_DRQ_SDRAM (0x11 << 16) - -#define NDMA_CFG_SRC_DRQ_SRAM (0x10 << 0) -#define NDMA_CFG_SRC_LINEAR (0x00 << 5) -#define NDMA_CFG_SRC_BST4_WIDTH32 ((0x1 << 7) | (0x2 << 8)) -#define NDMA_CFG_DST_DRQ_CODEC (0x0c << 16) -#define NDMA_CFG_DST_IO (0x1 << 21) -#define NDMA_CFG_DST_BST4_WIDTH32 ((0x1 << 23) | (0x2 << 24)) - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -#endif diff --git a/bsp/imxrt1052-evk/drivers/drv_eth.c b/bsp/imxrt1052-evk/drivers/drv_eth.c deleted file mode 100644 index 2ffe06c8d2..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_eth.c +++ /dev/null @@ -1,1430 +0,0 @@ -/* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2017-06-08 tanek first implementation - */ -#include -#include "board.h" -#include - -#ifdef RT_USING_FINSH - #include -#endif - -#include "fsl_enet.h" -#include "fsl_gpio.h" -#include "fsl_iomuxc.h" -#include "fsl_phy.h" -#include "fsl_cache.h" - -#ifdef RT_USING_LWIP - -#include -#include "lwipopts.h" - -#ifdef BOARD_RT1050_ATK - #include "drv_pcf8574.h" -#endif - -#define ENET_RXBD_NUM (4) -#define ENET_TXBD_NUM (4) -#define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) -#define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) - -#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) - #define PHY_ADDRESS 0x00u -#endif - -#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio) - #define PHY_ADDRESS 0x02u -#endif -/* debug option */ -//#define ETH_RX_DUMP -//#define ETH_TX_DUMP - -#define DBG_ENABLE -#define DBG_SECTION_NAME "ETH" -#define DBG_COLOR -#define DBG_LEVEL DBG_INFO -#include - -#define MAX_ADDR_LEN 6 - -struct rt_imxrt_eth -{ - /* inherit from ethernet device */ - struct eth_device parent; - - enet_handle_t enet_handle; - ENET_Type *enet_base; - enet_data_error_stats_t error_statistic; - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ - - rt_bool_t tx_is_waiting; - struct rt_semaphore tx_wait; - - enet_mii_speed_t speed; - enet_mii_duplex_t duplex; -}; - -ALIGN(ENET_BUFF_ALIGNMENT) enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM] SECTION("NonCacheable"); -ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_txDataBuff[ENET_TXBD_NUM][RT_ALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; - -ALIGN(ENET_BUFF_ALIGNMENT) enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM] SECTION("NonCacheable"); -ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_rxDataBuff[ENET_RXBD_NUM][RT_ALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; - -static struct rt_imxrt_eth imxrt_eth_device; - -void _enet_rx_callback(struct rt_imxrt_eth *eth) -{ - rt_err_t result; - - ENET_DisableInterrupts(eth->enet_base, kENET_RxFrameInterrupt); - - result = eth_device_ready(&(eth->parent)); - if (result != RT_EOK) - rt_kprintf("RX err =%d\n", result); -} - -void _enet_tx_callback(struct rt_imxrt_eth *eth) -{ - if (eth->tx_is_waiting == RT_TRUE) - { - eth->tx_is_waiting = RT_FALSE; - rt_sem_release(ð->tx_wait); - } -} - -void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData) -{ - switch (event) - { - case kENET_RxEvent: - - _enet_rx_callback((struct rt_imxrt_eth *)userData); - break; - - case kENET_TxEvent: - _enet_tx_callback((struct rt_imxrt_eth *)userData); - break; - - case kENET_ErrEvent: - //rt_kprintf("kENET_ErrEvent\n"); - break; - - case kENET_WakeUpEvent: - //rt_kprintf("kENET_WakeUpEvent\n"); - break; - - case kENET_TimeStampEvent: - //rt_kprintf("kENET_TimeStampEvent\n"); - break; - - case kENET_TimeStampAvailEvent: - //rt_kprintf("kENET_TimeStampAvailEvent \n"); - break; - - default: - //rt_kprintf("unknow error\n"); - break; - } -} -#if defined(BOARD_RT1050_SeeedStudio) || defined(BOARD_RT1050_EVK) -static void evk_enet_io_init(void) -{ - CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ - 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ - 0xB0A9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ - 0xB0A9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ - 0x31u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/6 - Speed Field: low(50MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Disabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ - 0xB829u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: low(50MHz) - Open Drain Enable Field: Open Drain Enabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ -} -#endif - -#ifdef BOARD_RT1050_ATK -static void atk_enet_io_init(void) -{ - CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ - 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_14_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ - 0); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_15_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ - 0); /* Software Input On Field: Input Path is determined by functionality */ - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ - 0x110F9); - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ - 0x110F9); - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ - 0x110F9); - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ - 0x110F9); - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ - 0x110F9); - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ - 0x110F9); - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ - 0x110F9); - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_14_ENET_MDC, - 0x110F9); - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_15_ENET_MDIO, - 0x110F9); - - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); - IOMUXC_GPR->GPR1 |= 1 << 23; - -} -#endif - -#ifdef BOARD_RT1050_FIRE -static void fire_enet_io_init(void) -{ - CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ - 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_04_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_15_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ - 0xB0A9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ - 0xB0A9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ - 0xB0E9u); - /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - - Hyst. Enable Field: Hysteresis Disabled */ - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ - 0x31u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/6 - Speed Field: low(50MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Disabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_04_ENET_MDC, - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_15_ENET_MDIO, - 0xB829u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: low(50MHz) - Open Drain Enable Field: Open Drain Enabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ -} -#endif -static void _enet_clk_init(void) -{ - const clock_enet_pll_config_t config = {true, false, 1}; - CLOCK_InitEnetPll(&config); - - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); -} - -static void _delay(void) -{ - volatile int i = 1000000; - - while (i--) - i = i; -} - -static void _enet_phy_reset_by_gpio(void) -{ - gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; - -#ifndef BOARD_RT1050_ATK - GPIO_PinInit(GPIO1, 9, &gpio_config); -#endif - GPIO_PinInit(GPIO1, 10, &gpio_config); - /* pull up the ENET_INT before RESET. */ - GPIO_WritePinOutput(GPIO1, 10, 1); - -#ifdef BOARD_RT1050_ATK - pcf8574_write_bit(7, 1); - _delay(); - pcf8574_write_bit(7, 0); -#else - GPIO_WritePinOutput(GPIO1, 9, 0); - _delay(); - GPIO_WritePinOutput(GPIO1, 9, 1); -#endif -} - -static void _enet_config(void) -{ - enet_config_t config; - uint32_t sysClock; - - /* prepare the buffer configuration. */ - enet_buffer_config_t buffConfig = - { - ENET_RXBD_NUM, - ENET_TXBD_NUM, - SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT), - SDK_SIZEALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT), - &g_rxBuffDescrip[0], - &g_txBuffDescrip[0], - &g_rxDataBuff[0][0], - &g_txDataBuff[0][0], - }; - - /* Get default configuration. */ - /* - * config.miiMode = kENET_RmiiMode; - * config.miiSpeed = kENET_MiiSpeed100M; - * config.miiDuplex = kENET_MiiFullDuplex; - * config.rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; - */ - ENET_GetDefaultConfig(&config); - config.interrupt = kENET_TxFrameInterrupt | kENET_RxFrameInterrupt; - //config.interrupt = 0xFFFFFFFF; - config.miiSpeed = imxrt_eth_device.speed; - config.miiDuplex = imxrt_eth_device.duplex; - - /* Set SMI to get PHY link status. */ - sysClock = CLOCK_GetFreq(kCLOCK_AhbClk); - - LOG_D("deinit"); - ENET_Deinit(imxrt_eth_device.enet_base); - LOG_D("init"); - ENET_Init(imxrt_eth_device.enet_base, &imxrt_eth_device.enet_handle, &config, &buffConfig, &imxrt_eth_device.dev_addr[0], sysClock); - LOG_D("set call back"); - ENET_SetCallback(&imxrt_eth_device.enet_handle, _enet_callback, &imxrt_eth_device); - LOG_D("active read"); - ENET_ActiveRead(imxrt_eth_device.enet_base); -} - -#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) -static void packet_dump(const char *msg, const struct pbuf *p) -{ - const struct pbuf *q; - rt_uint32_t i, j; - rt_uint8_t *ptr; - - rt_kprintf("%s %d byte\n", msg, p->tot_len); - - i = 0; - for (q = p; q != RT_NULL; q = q->next) - { - ptr = q->payload; - - for (j = 0; j < q->len; j++) - { - if ((i % 8) == 0) - { - rt_kprintf(" "); - } - if ((i % 16) == 0) - { - rt_kprintf("\r\n"); - } - rt_kprintf("%02x ", *ptr); - - i++; - ptr++; - } - } - - rt_kprintf("\n\n"); -} -#else -#define packet_dump(...) -#endif /* dump */ - -/* initialize the interface */ -static rt_err_t rt_imxrt_eth_init(rt_device_t dev) -{ - LOG_D("rt_imxrt_eth_init..."); - _enet_config(); - - return RT_EOK; -} - -static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag) -{ - LOG_D("rt_imxrt_eth_open..."); - return RT_EOK; -} - -static rt_err_t rt_imxrt_eth_close(rt_device_t dev) -{ - LOG_D("rt_imxrt_eth_close..."); - return RT_EOK; -} - -static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) -{ - LOG_D("rt_imxrt_eth_read..."); - rt_set_errno(-RT_ENOSYS); - return 0; -} - -static rt_size_t rt_imxrt_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) -{ - LOG_D("rt_imxrt_eth_write..."); - rt_set_errno(-RT_ENOSYS); - return 0; -} - -static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args) -{ - LOG_D("rt_imxrt_eth_control..."); - switch (cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if (args) rt_memcpy(args, imxrt_eth_device.dev_addr, 6); - else return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; -} - -static void _ENET_ActiveSend(ENET_Type *base, uint32_t ringId) -{ - assert(ringId < FSL_FEATURE_ENET_QUEUE); - - switch (ringId) - { - case 0: - base->TDAR = ENET_TDAR_TDAR_MASK; - break; -#if FSL_FEATURE_ENET_QUEUE > 1 - case kENET_Ring1: - base->TDAR1 = ENET_TDAR1_TDAR_MASK; - break; - case kENET_Ring2: - base->TDAR2 = ENET_TDAR2_TDAR_MASK; - break; -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - default: - base->TDAR = ENET_TDAR_TDAR_MASK; - break; - } -} - -static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length) -{ - assert(handle); - assert(data); - - volatile enet_tx_bd_struct_t *curBuffDescrip; - uint32_t len = 0; - uint32_t sizeleft = 0; - uint32_t address; - - /* Check the frame length. */ - if (length > ENET_FRAME_MAX_FRAMELEN) - { - return kStatus_ENET_TxFrameOverLen; - } - - /* Check if the transmit buffer is ready. */ - curBuffDescrip = handle->txBdCurrent[0]; - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) - { - return kStatus_ENET_TxFrameBusy; - } -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - bool isPtpEventMessage = false; - /* Check PTP message with the PTP header. */ - isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - /* One transmit buffer is enough for one frame. */ - if (handle->txBuffSizeAlign[0] >= length) - { - /* Copy data to the buffer for uDMA transfer. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - - pbuf_copy_partial((const struct pbuf *)data, (void *)address, length, 0); - - /* Set data length. */ - curBuffDescrip->length = length; -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* For enable the timestamp. */ - if (isPtpEventMessage) - { - curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - else - { - curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); - - /* Increase the buffer descriptor address. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdCurrent[0] = handle->txBdBase[0]; - } - else - { - handle->txBdCurrent[0]++; - } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, length); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - /* Active the transmit buffer descriptor. */ - _ENET_ActiveSend(base, 0); - - return kStatus_Success; - } - else - { - /* One frame requires more than one transmit buffers. */ - do - { -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* For enable the timestamp. */ - if (isPtpEventMessage) - { - curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - else - { - curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - /* Increase the buffer descriptor address. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdCurrent[0] = handle->txBdBase[0]; - } - else - { - handle->txBdCurrent[0]++; - } - /* update the size left to be transmit. */ - sizeleft = length - len; - if (sizeleft > handle->txBuffSizeAlign[0]) - { - /* Data copy. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]); - /* Data length update. */ - curBuffDescrip->length = handle->txBuffSizeAlign[0]; - len += handle->txBuffSizeAlign[0]; - /* Sets the control flag. */ - curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; - /* Active the transmit buffer descriptor*/ - _ENET_ActiveSend(base, 0); - } - else - { -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - memcpy((void *)address, data + len, sizeleft); - curBuffDescrip->length = sizeleft; - /* Set Last buffer wrap flag. */ - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - /* Active the transmit buffer descriptor. */ - _ENET_ActiveSend(base, 0); - - return kStatus_Success; - } - - /* Get the current buffer descriptor address. */ - curBuffDescrip = handle->txBdCurrent[0]; - - } - while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); - - return kStatus_ENET_TxFrameBusy; - } -} - -/* ethernet device interface */ -/* transmit packet. */ -rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p) -{ - rt_err_t result = RT_EOK; - enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle; - - RT_ASSERT(p != NULL); - RT_ASSERT(enet_handle != RT_NULL); - - LOG_D("rt_imxrt_eth_tx: %d", p->len); - -#ifdef ETH_TX_DUMP - packet_dump("send", p); -#endif - - do - { - result = _ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len); - - if (result == kStatus_ENET_TxFrameBusy) - { - imxrt_eth_device.tx_is_waiting = RT_TRUE; - rt_sem_take(&imxrt_eth_device.tx_wait, RT_WAITING_FOREVER); - } - - } - while (result == kStatus_ENET_TxFrameBusy); - - return RT_EOK; -} - -/* reception packet. */ -struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) -{ - uint32_t length = 0; - status_t status; - - struct pbuf *p = RT_NULL; - enet_handle_t *enet_handle = &imxrt_eth_device.enet_handle; - ENET_Type *enet_base = imxrt_eth_device.enet_base; - enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic; - - /* Get the Frame size */ - status = ENET_GetRxFrameSize(enet_handle, &length); - - /* Call ENET_ReadFrame when there is a received frame. */ - if (length != 0) - { - /* Received valid frame. Deliver the rx buffer with the size equal to length. */ - p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL); - - if (p != NULL) - { - status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length); - if (status == kStatus_Success) - { -#ifdef ETH_RX_DUMP - packet_dump("recv", p); -#endif - return p; - } - else - { - LOG_D(" A frame read failed"); - pbuf_free(p); - } - } - else - { - LOG_D(" pbuf_alloc faild"); - } - } - else if (status == kStatus_ENET_RxFrameError) - { - LOG_W("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError"); - /* Update the received buffer when error happened. */ - /* Get the error information of the received g_frame. */ - ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic); - /* update the receive buffer. */ - ENET_ReadFrame(enet_base, enet_handle, NULL, 0); - } - - ENET_EnableInterrupts(enet_base, kENET_RxFrameInterrupt); - return NULL; -} - -static void phy_monitor_thread_entry(void *parameter) -{ - phy_speed_t speed; - phy_duplex_t duplex; - bool link = false; - - _enet_phy_reset_by_gpio(); - - PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk)); - - while (1) - { - bool new_link = false; - status_t status = PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &new_link); - - if ((status == kStatus_Success) && (link != new_link)) - { - link = new_link; - - if (link) // link up - { - PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, - PHY_ADDRESS, &speed, &duplex); - - if (kPHY_Speed10M == speed) - { - LOG_D("10M"); - } - else - { - LOG_D("100M"); - } - - if (kPHY_HalfDuplex == duplex) - { - LOG_D("half dumplex"); - } - else - { - LOG_D("full dumplex"); - } - - if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) - || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex)) - { - imxrt_eth_device.speed = (enet_mii_speed_t)speed; - imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex; - - LOG_D("link up, and update eth mode."); - rt_imxrt_eth_init((rt_device_t)&imxrt_eth_device); - } - else - { - LOG_D("link up, eth not need re-config."); - } - LOG_D("link up."); - eth_device_linkchange(&imxrt_eth_device.parent, RT_TRUE); - } - else // link down - { - LOG_D("link down."); - eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); - } - } - - rt_thread_delay(RT_TICK_PER_SECOND * 2); - } -} - -static int rt_hw_imxrt_eth_init(void) -{ - rt_err_t state; - -#ifdef BOARD_RT1050_ATK - atk_enet_io_init(); -#endif - -#ifdef BOARD_RT1050_FIRE - fire_enet_io_init(); -#endif - -#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio) - evk_enet_io_init(); -#endif - _enet_clk_init(); - /* OUI 00-80-E1 STMICROELECTRONICS. */ - imxrt_eth_device.dev_addr[0] = 0x00; - imxrt_eth_device.dev_addr[1] = 0x04; - imxrt_eth_device.dev_addr[2] = 0x9F; - /* generate MAC addr from 96bit unique ID (only for test). */ - imxrt_eth_device.dev_addr[3] = 0x08; - imxrt_eth_device.dev_addr[4] = 0x43; - imxrt_eth_device.dev_addr[5] = 0x75; - - imxrt_eth_device.speed = kENET_MiiSpeed100M; - imxrt_eth_device.duplex = kENET_MiiFullDuplex; - - imxrt_eth_device.enet_base = ENET; - - imxrt_eth_device.parent.parent.init = rt_imxrt_eth_init; - imxrt_eth_device.parent.parent.open = rt_imxrt_eth_open; - imxrt_eth_device.parent.parent.close = rt_imxrt_eth_close; - imxrt_eth_device.parent.parent.read = rt_imxrt_eth_read; - imxrt_eth_device.parent.parent.write = rt_imxrt_eth_write; - imxrt_eth_device.parent.parent.control = rt_imxrt_eth_control; - imxrt_eth_device.parent.parent.user_data = RT_NULL; - - imxrt_eth_device.parent.eth_rx = rt_imxrt_eth_rx; - imxrt_eth_device.parent.eth_tx = rt_imxrt_eth_tx; - - LOG_D("sem init: tx_wait\r"); - /* init tx semaphore */ - rt_sem_init(&imxrt_eth_device.tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO); - - /* register eth device */ - LOG_D("eth_device_init start\r"); - state = eth_device_init(&(imxrt_eth_device.parent), "e0"); - if (RT_EOK == state) - { - LOG_D("eth_device_init success\r"); - } - else - { - LOG_D("eth_device_init faild: %d\r", state); - } - - eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); - - /* start phy monitor */ - { - rt_thread_t tid; - tid = rt_thread_create("phy", - phy_monitor_thread_entry, - RT_NULL, - 512, - RT_THREAD_PRIORITY_MAX - 2, - 2); - if (tid != RT_NULL) - rt_thread_startup(tid); - } - - return state; -} -#ifdef BOARD_RT1050_ATK - INIT_ENV_EXPORT(rt_hw_imxrt_eth_init); -#else - INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init); -#endif -#endif - -#ifdef RT_USING_FINSH -#include - -void phy_read(uint32_t phyReg) -{ - uint32_t data; - status_t status; - - status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, &data); - if (kStatus_Success == status) - { - rt_kprintf("PHY_Read: %02X --> %08X", phyReg, data); - } - else - { - rt_kprintf("PHY_Read: %02X --> faild", phyReg); - } -} - -void phy_write(uint32_t phyReg, uint32_t data) -{ - status_t status; - - status = PHY_Write(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, data); - if (kStatus_Success == status) - { - rt_kprintf("PHY_Write: %02X --> %08X\n", phyReg, data); - } - else - { - rt_kprintf("PHY_Write: %02X --> faild\n", phyReg); - } -} - -void phy_dump(void) -{ - uint32_t data; - status_t status; - - int i; - for (i = 0; i < 32; i++) - { - status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, i, &data); - if (kStatus_Success != status) - { - rt_kprintf("phy_dump: %02X --> faild", i); - break; - } - - if (i % 8 == 7) - { - rt_kprintf("%02X --> %08X ", i, data); - } - else - { - rt_kprintf("%02X --> %08X\n", i, data); - } - - } -} - -void enet_reg_dump(void) -{ - ENET_Type *enet_base = imxrt_eth_device.enet_base; - -#define DUMP_REG(__REG) \ - rt_kprintf("%s(%08X): %08X\n", #__REG, (uint32_t)&enet_base->__REG, enet_base->__REG) - - DUMP_REG(EIR); - DUMP_REG(EIMR); - DUMP_REG(RDAR); - DUMP_REG(TDAR); - DUMP_REG(ECR); - DUMP_REG(MMFR); - DUMP_REG(MSCR); - DUMP_REG(MIBC); - DUMP_REG(RCR); - DUMP_REG(TCR); - DUMP_REG(PALR); - DUMP_REG(PAUR); - DUMP_REG(OPD); - DUMP_REG(TXIC); - DUMP_REG(RXIC); - DUMP_REG(IAUR); - DUMP_REG(IALR); - DUMP_REG(GAUR); - DUMP_REG(GALR); - DUMP_REG(TFWR); - DUMP_REG(RDSR); - DUMP_REG(TDSR); - DUMP_REG(MRBR); - DUMP_REG(RSFL); - DUMP_REG(RSEM); - DUMP_REG(RAEM); - DUMP_REG(RAFL); - DUMP_REG(TSEM); - DUMP_REG(TAEM); - DUMP_REG(TAFL); - DUMP_REG(TIPG); - DUMP_REG(FTRL); - DUMP_REG(TACC); - DUMP_REG(RACC); - DUMP_REG(RMON_T_DROP); - DUMP_REG(RMON_T_PACKETS); - DUMP_REG(RMON_T_BC_PKT); - DUMP_REG(RMON_T_MC_PKT); - DUMP_REG(RMON_T_CRC_ALIGN); - DUMP_REG(RMON_T_UNDERSIZE); - DUMP_REG(RMON_T_OVERSIZE); - DUMP_REG(RMON_T_FRAG); - DUMP_REG(RMON_T_JAB); - DUMP_REG(RMON_T_COL); - DUMP_REG(RMON_T_P64); - DUMP_REG(RMON_T_P65TO127); - DUMP_REG(RMON_T_P128TO255); - DUMP_REG(RMON_T_P256TO511); - DUMP_REG(RMON_T_P512TO1023); - DUMP_REG(RMON_T_P1024TO2047); - DUMP_REG(RMON_T_P_GTE2048); - DUMP_REG(RMON_T_OCTETS); - DUMP_REG(IEEE_T_DROP); - DUMP_REG(IEEE_T_FRAME_OK); - DUMP_REG(IEEE_T_1COL); - DUMP_REG(IEEE_T_MCOL); - DUMP_REG(IEEE_T_DEF); - DUMP_REG(IEEE_T_LCOL); - DUMP_REG(IEEE_T_EXCOL); - DUMP_REG(IEEE_T_MACERR); - DUMP_REG(IEEE_T_CSERR); - DUMP_REG(IEEE_T_SQE); - DUMP_REG(IEEE_T_FDXFC); - DUMP_REG(IEEE_T_OCTETS_OK); - DUMP_REG(RMON_R_PACKETS); - DUMP_REG(RMON_R_BC_PKT); - DUMP_REG(RMON_R_MC_PKT); - DUMP_REG(RMON_R_CRC_ALIGN); - DUMP_REG(RMON_R_UNDERSIZE); - DUMP_REG(RMON_R_OVERSIZE); - DUMP_REG(RMON_R_FRAG); - DUMP_REG(RMON_R_JAB); - DUMP_REG(RMON_R_RESVD_0); - DUMP_REG(RMON_R_P64); - DUMP_REG(RMON_R_P65TO127); - DUMP_REG(RMON_R_P128TO255); - DUMP_REG(RMON_R_P256TO511); - DUMP_REG(RMON_R_P512TO1023); - DUMP_REG(RMON_R_P1024TO2047); - DUMP_REG(RMON_R_P_GTE2048); - DUMP_REG(RMON_R_OCTETS); - DUMP_REG(IEEE_R_DROP); - DUMP_REG(IEEE_R_FRAME_OK); - DUMP_REG(IEEE_R_CRC); - DUMP_REG(IEEE_R_ALIGN); - DUMP_REG(IEEE_R_MACERR); - DUMP_REG(IEEE_R_FDXFC); - DUMP_REG(IEEE_R_OCTETS_OK); - DUMP_REG(ATCR); - DUMP_REG(ATVR); - DUMP_REG(ATOFF); - DUMP_REG(ATPER); - DUMP_REG(ATCOR); - DUMP_REG(ATINC); - DUMP_REG(ATSTMP); - DUMP_REG(TGSR); -} - -void enet_nvic_tog(void) -{ - NVIC_SetPendingIRQ(ENET_IRQn); -} - -void enet_rx_stat(void) -{ - enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic; - -#define DUMP_STAT(__VAR) \ - rt_kprintf("%-25s: %08X\n", #__VAR, error_statistic->__VAR); - - DUMP_STAT(statsRxLenGreaterErr); - DUMP_STAT(statsRxAlignErr); - DUMP_STAT(statsRxFcsErr); - DUMP_STAT(statsRxOverRunErr); - DUMP_STAT(statsRxTruncateErr); - -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - DUMP_STAT(statsRxProtocolChecksumErr); - DUMP_STAT(statsRxIpHeadChecksumErr); - DUMP_STAT(statsRxMacErr); - DUMP_STAT(statsRxPhyErr); - DUMP_STAT(statsRxCollisionErr); - DUMP_STAT(statsTxErr); - DUMP_STAT(statsTxFrameErr); - DUMP_STAT(statsTxOverFlowErr); - DUMP_STAT(statsTxLateCollisionErr); - DUMP_STAT(statsTxExcessCollisionErr); - DUMP_STAT(statsTxUnderFlowErr); - DUMP_STAT(statsTxTsErr); -#endif - -} - -void enet_buf_info(void) -{ - int i = 0; - for (i = 0; i < ENET_RXBD_NUM; i++) - { - rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n", - i, - g_rxBuffDescrip[i].length, - g_rxBuffDescrip[i].control, - g_rxBuffDescrip[i].buffer); - } - - for (i = 0; i < ENET_TXBD_NUM; i++) - { - rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n", - i, - g_txBuffDescrip[i].length, - g_txBuffDescrip[i].control, - g_txBuffDescrip[i].buffer); - } -} - -FINSH_FUNCTION_EXPORT(phy_read, read phy register); -FINSH_FUNCTION_EXPORT(phy_write, write phy register); -FINSH_FUNCTION_EXPORT(phy_dump, dump phy registers); -FINSH_FUNCTION_EXPORT(enet_reg_dump, dump enet registers); -FINSH_FUNCTION_EXPORT(enet_nvic_tog, toggle enet nvic pendding bit); -FINSH_FUNCTION_EXPORT(enet_rx_stat, dump enet rx statistic); -FINSH_FUNCTION_EXPORT(enet_buf_info, dump enet tx and tx buffer descripter); - -#endif diff --git a/bsp/imxrt1052-evk/drivers/drv_eth_fire.c b/bsp/imxrt1052-evk/drivers/drv_eth_fire.c deleted file mode 100644 index 7e337b9d66..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_eth_fire.c +++ /dev/null @@ -1,1120 +0,0 @@ -/* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2017-06-08 tanek first implementation - */ -#include -#include "board.h" -#include - -#ifdef RT_USING_FINSH - #include -#endif - -#include "fsl_enet.h" -#include "fsl_gpio.h" -#include "fsl_iomuxc.h" -#include "fsl_phy_fire.h" -#include "fsl_cache.h" - -#ifdef RT_USING_LWIP - -#include -#include "lwipopts.h" - -#define ENET_RXBD_NUM (4) -#define ENET_TXBD_NUM (4) -#define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) -#define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN) - -#define PHY_ADDRESS 0x00u - -/* debug option */ -//#define ETH_RX_DUMP -//#define ETH_TX_DUMP - -#define DBG_ENABLE -#define DBG_SECTION_NAME "ETH" -#define DBG_COLOR -#define DBG_LEVEL DBG_LOG -#include - -#define MAX_ADDR_LEN 6 - -struct rt_imxrt_eth -{ - /* inherit from ethernet device */ - struct eth_device parent; - - enet_handle_t enet_handle; - ENET_Type *enet_base; - enet_data_error_stats_t error_statistic; - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ - - rt_bool_t tx_is_waiting; - struct rt_semaphore tx_wait; - - enet_mii_speed_t speed; - enet_mii_duplex_t duplex; -}; - -ALIGN(ENET_BUFF_ALIGNMENT) enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM] SECTION("NonCacheable"); -ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_txDataBuff[ENET_TXBD_NUM][RT_ALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; - -ALIGN(ENET_BUFF_ALIGNMENT) enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM] SECTION("NonCacheable"); -ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_rxDataBuff[ENET_RXBD_NUM][RT_ALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT)]; - -static struct rt_imxrt_eth imxrt_eth_device; - -void _enet_rx_callback(struct rt_imxrt_eth *eth) -{ - rt_err_t result; - - ENET_DisableInterrupts(eth->enet_base, kENET_RxFrameInterrupt); - - result = eth_device_ready(&(eth->parent)); - if (result != RT_EOK) - rt_kprintf("RX err =%d\n", result); -} - -void _enet_tx_callback(struct rt_imxrt_eth *eth) -{ - if (eth->tx_is_waiting == RT_TRUE) - { - eth->tx_is_waiting = RT_FALSE; - rt_sem_release(ð->tx_wait); - } -} - -void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData) -{ - switch (event) - { - case kENET_RxEvent: - - _enet_rx_callback((struct rt_imxrt_eth *)userData); - break; - - case kENET_TxEvent: - _enet_tx_callback((struct rt_imxrt_eth *)userData); - break; - - case kENET_ErrEvent: - //rt_kprintf("kENET_ErrEvent\n"); - break; - - case kENET_WakeUpEvent: - //rt_kprintf("kENET_WakeUpEvent\n"); - break; - - case kENET_TimeStampEvent: - //rt_kprintf("kENET_TimeStampEvent\n"); - break; - - case kENET_TimeStampAvailEvent: - //rt_kprintf("kENET_TimeStampAvailEvent \n"); - break; - - default: - //rt_kprintf("unknow error\n"); - break; - } -} - -static void _enet_io_init(void) -{ - CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ - 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_04_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_15_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ - 0xB0A9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ - 0xB0A9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ - 0x31u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/6 - Speed Field: low(50MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Disabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_04_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_15_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ - 0xB829u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: low(50MHz) - Open Drain Enable Field: Open Drain Enabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ -} - -static void _enet_clk_init(void) -{ - const clock_enet_pll_config_t config = {true, false, 1}; - CLOCK_InitEnetPll(&config); - - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); -} - -static void _delay(void) -{ - volatile int i = 1000000; - - while (i--) - i = i; -} - -static void _enet_phy_reset_by_gpio(void) -{ - gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; - - GPIO_PinInit(GPIO1, 9, &gpio_config); - GPIO_PinInit(GPIO1, 10, &gpio_config); - /* pull up the ENET_INT before RESET. */ - GPIO_WritePinOutput(GPIO1, 10, 1); - GPIO_WritePinOutput(GPIO1, 9, 0); - _delay(); - GPIO_WritePinOutput(GPIO1, 9, 1); -} - -static void _enet_config(void) -{ - enet_config_t config; - uint32_t sysClock; - - /* prepare the buffer configuration. */ - enet_buffer_config_t buffConfig = - { - ENET_RXBD_NUM, - ENET_TXBD_NUM, - SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT), - SDK_SIZEALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT), - &g_rxBuffDescrip[0], - &g_txBuffDescrip[0], - &g_rxDataBuff[0][0], - &g_txDataBuff[0][0], - }; - - /* Get default configuration. */ - /* - * config.miiMode = kENET_RmiiMode; - * config.miiSpeed = kENET_MiiSpeed100M; - * config.miiDuplex = kENET_MiiFullDuplex; - * config.rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; - */ - ENET_GetDefaultConfig(&config); - config.interrupt = kENET_TxFrameInterrupt | kENET_RxFrameInterrupt; - //config.interrupt = 0xFFFFFFFF; - config.miiSpeed = imxrt_eth_device.speed; - config.miiDuplex = imxrt_eth_device.duplex; - - /* Set SMI to get PHY link status. */ - sysClock = CLOCK_GetFreq(kCLOCK_AhbClk); - - LOG_D("deinit"); - ENET_Deinit(imxrt_eth_device.enet_base); - LOG_D("init"); - ENET_Init(imxrt_eth_device.enet_base, &imxrt_eth_device.enet_handle, &config, &buffConfig, &imxrt_eth_device.dev_addr[0], sysClock); - LOG_D("set call back"); - ENET_SetCallback(&imxrt_eth_device.enet_handle, _enet_callback, &imxrt_eth_device); - LOG_D("active read"); - ENET_ActiveRead(imxrt_eth_device.enet_base); -} - -#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) -static void packet_dump(const char *msg, const struct pbuf *p) -{ - const struct pbuf *q; - rt_uint32_t i, j; - rt_uint8_t *ptr; - - rt_kprintf("%s %d byte\n", msg, p->tot_len); - - i = 0; - for (q = p; q != RT_NULL; q = q->next) - { - ptr = q->payload; - - for (j = 0; j < q->len; j++) - { - if ((i % 8) == 0) - { - rt_kprintf(" "); - } - if ((i % 16) == 0) - { - rt_kprintf("\r\n"); - } - rt_kprintf("%02x ", *ptr); - - i++; - ptr++; - } - } - - rt_kprintf("\n\n"); -} -#else -#define packet_dump(...) -#endif /* dump */ - -/* initialize the interface */ -static rt_err_t rt_imxrt_eth_init(rt_device_t dev) -{ - LOG_D("rt_imxrt_eth_init..."); - _enet_config(); - - return RT_EOK; -} - -static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag) -{ - LOG_D("rt_imxrt_eth_open..."); - return RT_EOK; -} - -static rt_err_t rt_imxrt_eth_close(rt_device_t dev) -{ - LOG_D("rt_imxrt_eth_close..."); - return RT_EOK; -} - -static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) -{ - LOG_D("rt_imxrt_eth_read..."); - rt_set_errno(-RT_ENOSYS); - return 0; -} - -static rt_size_t rt_imxrt_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) -{ - LOG_D("rt_imxrt_eth_write..."); - rt_set_errno(-RT_ENOSYS); - return 0; -} - -static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args) -{ - LOG_D("rt_imxrt_eth_control..."); - switch (cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if (args) rt_memcpy(args, imxrt_eth_device.dev_addr, 6); - else return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; -} - -static void _ENET_ActiveSend(ENET_Type *base, uint32_t ringId) -{ - assert(ringId < FSL_FEATURE_ENET_QUEUE); - - switch (ringId) - { - case 0: - base->TDAR = ENET_TDAR_TDAR_MASK; - break; -#if FSL_FEATURE_ENET_QUEUE > 1 - case kENET_Ring1: - base->TDAR1 = ENET_TDAR1_TDAR_MASK; - break; - case kENET_Ring2: - base->TDAR2 = ENET_TDAR2_TDAR_MASK; - break; -#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ - default: - base->TDAR = ENET_TDAR_TDAR_MASK; - break; - } -} - -static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length) -{ - assert(handle); - assert(data); - - volatile enet_tx_bd_struct_t *curBuffDescrip; - uint32_t len = 0; - uint32_t sizeleft = 0; - uint32_t address; - - /* Check the frame length. */ - if (length > ENET_FRAME_MAX_FRAMELEN) - { - return kStatus_ENET_TxFrameOverLen; - } - - /* Check if the transmit buffer is ready. */ - curBuffDescrip = handle->txBdCurrent[0]; - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) - { - return kStatus_ENET_TxFrameBusy; - } -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - bool isPtpEventMessage = false; - /* Check PTP message with the PTP header. */ - isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - /* One transmit buffer is enough for one frame. */ - if (handle->txBuffSizeAlign[0] >= length) - { - /* Copy data to the buffer for uDMA transfer. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - - pbuf_copy_partial((const struct pbuf *)data, (void *)address, length, 0); - - /* Set data length. */ - curBuffDescrip->length = length; -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* For enable the timestamp. */ - if (isPtpEventMessage) - { - curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - else - { - curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); - - /* Increase the buffer descriptor address. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdCurrent[0] = handle->txBdBase[0]; - } - else - { - handle->txBdCurrent[0]++; - } -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, length); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - /* Active the transmit buffer descriptor. */ - _ENET_ActiveSend(base, 0); - - return kStatus_Success; - } - else - { - /* One frame requires more than one transmit buffers. */ - do - { -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - /* For enable the timestamp. */ - if (isPtpEventMessage) - { - curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } - else - { - curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; - } -#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ - - /* Increase the buffer descriptor address. */ - if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) - { - handle->txBdCurrent[0] = handle->txBdBase[0]; - } - else - { - handle->txBdCurrent[0]++; - } - /* update the size left to be transmit. */ - sizeleft = length - len; - if (sizeleft > handle->txBuffSizeAlign[0]) - { - /* Data copy. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]); - /* Data length update. */ - curBuffDescrip->length = handle->txBuffSizeAlign[0]; - len += handle->txBuffSizeAlign[0]; - /* Sets the control flag. */ - curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; - /* Active the transmit buffer descriptor*/ - _ENET_ActiveSend(base, 0); - } - else - { -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - memcpy((void *)address, data + len, sizeleft); - curBuffDescrip->length = sizeleft; - /* Set Last buffer wrap flag. */ - curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL - /* Add the cache clean maintain. */ -#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET - address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local); -#else - address = (uint32_t)curBuffDescrip->buffer; -#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ - DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); -#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ - /* Active the transmit buffer descriptor. */ - _ENET_ActiveSend(base, 0); - - return kStatus_Success; - } - - /* Get the current buffer descriptor address. */ - curBuffDescrip = handle->txBdCurrent[0]; - - } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); - - return kStatus_ENET_TxFrameBusy; - } -} - -/* ethernet device interface */ -/* transmit packet. */ -rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p) -{ - rt_err_t result = RT_EOK; - enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle; - - RT_ASSERT(p != NULL); - RT_ASSERT(enet_handle != RT_NULL); - - LOG_D("rt_imxrt_eth_tx: %d", p->len); - -#ifdef ETH_TX_DUMP - packet_dump("send", p); -#endif - - do - { - result = _ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len); - - if (result == kStatus_ENET_TxFrameBusy) - { - imxrt_eth_device.tx_is_waiting = RT_TRUE; - rt_sem_take(&imxrt_eth_device.tx_wait, RT_WAITING_FOREVER); - } - - } - while (result == kStatus_ENET_TxFrameBusy); - - return RT_EOK; -} - -/* reception packet. */ -struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) -{ - uint32_t length = 0; - status_t status; - - struct pbuf *p = RT_NULL; - enet_handle_t *enet_handle = &imxrt_eth_device.enet_handle; - ENET_Type *enet_base = imxrt_eth_device.enet_base; - enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic; - - /* Get the Frame size */ - status = ENET_GetRxFrameSize(enet_handle, &length); - - /* Call ENET_ReadFrame when there is a received frame. */ - if (length != 0) - { - /* Received valid frame. Deliver the rx buffer with the size equal to length. */ - p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL); - - if (p != NULL) - { - status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length); - if (status == kStatus_Success) - { -#ifdef ETH_RX_DUMP - packet_dump("recv", p); -#endif - return p; - } - else - { - LOG_D(" A frame read failed"); - pbuf_free(p); - } - } - else - { - LOG_D(" pbuf_alloc faild"); - } - } - else if (status == kStatus_ENET_RxFrameError) - { - LOG_W("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError"); - /* Update the received buffer when error happened. */ - /* Get the error information of the received g_frame. */ - ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic); - /* update the receive buffer. */ - ENET_ReadFrame(enet_base, enet_handle, NULL, 0); - } - - ENET_EnableInterrupts(enet_base, kENET_RxFrameInterrupt); - return NULL; -} - -static void phy_monitor_thread_entry(void *parameter) -{ - phy_speed_t speed; - phy_duplex_t duplex; - bool link = false; - - _enet_phy_reset_by_gpio(); - - PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk)); - - while (1) - { - bool new_link = false; - status_t status = PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &new_link); - - if ((status == kStatus_Success) && (link != new_link)) - { - link = new_link; - - if (link) // link up - { - PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, - PHY_ADDRESS, &speed, &duplex); - - if (kPHY_Speed10M == speed) - { - LOG_D("10M"); - } - else - { - LOG_D("100M"); - } - - if (kPHY_HalfDuplex == duplex) - { - LOG_D("half dumplex"); - } - else - { - LOG_D("full dumplex"); - } - - if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) - || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex)) - { - imxrt_eth_device.speed = (enet_mii_speed_t)speed; - imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex; - - LOG_D("link up, and update eth mode."); - rt_imxrt_eth_init((rt_device_t)&imxrt_eth_device); - } - else - { - LOG_D("link up, eth not need re-config."); - } - LOG_D("link up."); - eth_device_linkchange(&imxrt_eth_device.parent, RT_TRUE); - } - else // link down - { - LOG_D("link down."); - eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); - } - } - - rt_thread_delay(RT_TICK_PER_SECOND * 2); - } -} - -static int rt_hw_imxrt_eth_init(void) -{ - rt_err_t state; - - _enet_io_init(); - _enet_clk_init(); - - /* OUI 00-80-E1 STMICROELECTRONICS. */ - imxrt_eth_device.dev_addr[0] = 0x00; - imxrt_eth_device.dev_addr[1] = 0x04; - imxrt_eth_device.dev_addr[2] = 0x9F; - /* generate MAC addr from 96bit unique ID (only for test). */ - imxrt_eth_device.dev_addr[3] = 0x05; - imxrt_eth_device.dev_addr[4] = 0x44; - imxrt_eth_device.dev_addr[5] = 0xE5; - - imxrt_eth_device.speed = kENET_MiiSpeed100M; - imxrt_eth_device.duplex = kENET_MiiFullDuplex; - - imxrt_eth_device.enet_base = ENET; - - imxrt_eth_device.parent.parent.init = rt_imxrt_eth_init; - imxrt_eth_device.parent.parent.open = rt_imxrt_eth_open; - imxrt_eth_device.parent.parent.close = rt_imxrt_eth_close; - imxrt_eth_device.parent.parent.read = rt_imxrt_eth_read; - imxrt_eth_device.parent.parent.write = rt_imxrt_eth_write; - imxrt_eth_device.parent.parent.control = rt_imxrt_eth_control; - imxrt_eth_device.parent.parent.user_data = RT_NULL; - - imxrt_eth_device.parent.eth_rx = rt_imxrt_eth_rx; - imxrt_eth_device.parent.eth_tx = rt_imxrt_eth_tx; - - LOG_D("sem init: tx_wait\r"); - /* init tx semaphore */ - rt_sem_init(&imxrt_eth_device.tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO); - - /* register eth device */ - LOG_D("eth_device_init start\r"); - state = eth_device_init(&(imxrt_eth_device.parent), "e0"); - if (RT_EOK == state) - { - LOG_D("eth_device_init success\r"); - } - else - { - LOG_D("eth_device_init faild: %d\r", state); - } - - eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE); - - /* start phy monitor */ - { - rt_thread_t tid; - tid = rt_thread_create("phy", - phy_monitor_thread_entry, - RT_NULL, - 512, - RT_THREAD_PRIORITY_MAX - 2, - 2); - if (tid != RT_NULL) - rt_thread_startup(tid); - } - - return state; -} -INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init); -#endif - -#ifdef RT_USING_FINSH -#include - -void phy_read(uint32_t phyReg) -{ - uint32_t data; - status_t status; - - status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, &data); - if (kStatus_Success == status) - { - rt_kprintf("PHY_Read: %02X --> %08X", phyReg, data); - } - else - { - rt_kprintf("PHY_Read: %02X --> faild", phyReg); - } -} - -void phy_write(uint32_t phyReg, uint32_t data) -{ - status_t status; - - status = PHY_Write(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, data); - if (kStatus_Success == status) - { - rt_kprintf("PHY_Write: %02X --> %08X\n", phyReg, data); - } - else - { - rt_kprintf("PHY_Write: %02X --> faild\n", phyReg); - } -} - -void phy_dump(void) -{ - uint32_t data; - status_t status; - - int i; - for (i = 0; i < 32; i++) - { - status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, i, &data); - if (kStatus_Success != status) - { - rt_kprintf("phy_dump: %02X --> faild", i); - break; - } - - if (i % 8 == 7) - { - rt_kprintf("%02X --> %08X ", i, data); - } - else - { - rt_kprintf("%02X --> %08X\n", i, data); - } - - } -} - -void enet_reg_dump(void) -{ - ENET_Type *enet_base = imxrt_eth_device.enet_base; - -#define DUMP_REG(__REG) \ - rt_kprintf("%s(%08X): %08X\n", #__REG, (uint32_t)&enet_base->__REG, enet_base->__REG) - - DUMP_REG(EIR); - DUMP_REG(EIMR); - DUMP_REG(RDAR); - DUMP_REG(TDAR); - DUMP_REG(ECR); - DUMP_REG(MMFR); - DUMP_REG(MSCR); - DUMP_REG(MIBC); - DUMP_REG(RCR); - DUMP_REG(TCR); - DUMP_REG(PALR); - DUMP_REG(PAUR); - DUMP_REG(OPD); - DUMP_REG(TXIC); - DUMP_REG(RXIC); - DUMP_REG(IAUR); - DUMP_REG(IALR); - DUMP_REG(GAUR); - DUMP_REG(GALR); - DUMP_REG(TFWR); - DUMP_REG(RDSR); - DUMP_REG(TDSR); - DUMP_REG(MRBR); - DUMP_REG(RSFL); - DUMP_REG(RSEM); - DUMP_REG(RAEM); - DUMP_REG(RAFL); - DUMP_REG(TSEM); - DUMP_REG(TAEM); - DUMP_REG(TAFL); - DUMP_REG(TIPG); - DUMP_REG(FTRL); - DUMP_REG(TACC); - DUMP_REG(RACC); - DUMP_REG(RMON_T_DROP); - DUMP_REG(RMON_T_PACKETS); - DUMP_REG(RMON_T_BC_PKT); - DUMP_REG(RMON_T_MC_PKT); - DUMP_REG(RMON_T_CRC_ALIGN); - DUMP_REG(RMON_T_UNDERSIZE); - DUMP_REG(RMON_T_OVERSIZE); - DUMP_REG(RMON_T_FRAG); - DUMP_REG(RMON_T_JAB); - DUMP_REG(RMON_T_COL); - DUMP_REG(RMON_T_P64); - DUMP_REG(RMON_T_P65TO127); - DUMP_REG(RMON_T_P128TO255); - DUMP_REG(RMON_T_P256TO511); - DUMP_REG(RMON_T_P512TO1023); - DUMP_REG(RMON_T_P1024TO2047); - DUMP_REG(RMON_T_P_GTE2048); - DUMP_REG(RMON_T_OCTETS); - DUMP_REG(IEEE_T_DROP); - DUMP_REG(IEEE_T_FRAME_OK); - DUMP_REG(IEEE_T_1COL); - DUMP_REG(IEEE_T_MCOL); - DUMP_REG(IEEE_T_DEF); - DUMP_REG(IEEE_T_LCOL); - DUMP_REG(IEEE_T_EXCOL); - DUMP_REG(IEEE_T_MACERR); - DUMP_REG(IEEE_T_CSERR); - DUMP_REG(IEEE_T_SQE); - DUMP_REG(IEEE_T_FDXFC); - DUMP_REG(IEEE_T_OCTETS_OK); - DUMP_REG(RMON_R_PACKETS); - DUMP_REG(RMON_R_BC_PKT); - DUMP_REG(RMON_R_MC_PKT); - DUMP_REG(RMON_R_CRC_ALIGN); - DUMP_REG(RMON_R_UNDERSIZE); - DUMP_REG(RMON_R_OVERSIZE); - DUMP_REG(RMON_R_FRAG); - DUMP_REG(RMON_R_JAB); - DUMP_REG(RMON_R_RESVD_0); - DUMP_REG(RMON_R_P64); - DUMP_REG(RMON_R_P65TO127); - DUMP_REG(RMON_R_P128TO255); - DUMP_REG(RMON_R_P256TO511); - DUMP_REG(RMON_R_P512TO1023); - DUMP_REG(RMON_R_P1024TO2047); - DUMP_REG(RMON_R_P_GTE2048); - DUMP_REG(RMON_R_OCTETS); - DUMP_REG(IEEE_R_DROP); - DUMP_REG(IEEE_R_FRAME_OK); - DUMP_REG(IEEE_R_CRC); - DUMP_REG(IEEE_R_ALIGN); - DUMP_REG(IEEE_R_MACERR); - DUMP_REG(IEEE_R_FDXFC); - DUMP_REG(IEEE_R_OCTETS_OK); - DUMP_REG(ATCR); - DUMP_REG(ATVR); - DUMP_REG(ATOFF); - DUMP_REG(ATPER); - DUMP_REG(ATCOR); - DUMP_REG(ATINC); - DUMP_REG(ATSTMP); - DUMP_REG(TGSR); -} - -void enet_nvic_tog(void) -{ - NVIC_SetPendingIRQ(ENET_IRQn); -} - -void enet_rx_stat(void) -{ - enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic; - -#define DUMP_STAT(__VAR) \ - rt_kprintf("%-25s: %08X\n", #__VAR, error_statistic->__VAR); - - DUMP_STAT(statsRxLenGreaterErr); - DUMP_STAT(statsRxAlignErr); - DUMP_STAT(statsRxFcsErr); - DUMP_STAT(statsRxOverRunErr); - DUMP_STAT(statsRxTruncateErr); - -#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE - DUMP_STAT(statsRxProtocolChecksumErr); - DUMP_STAT(statsRxIpHeadChecksumErr); - DUMP_STAT(statsRxMacErr); - DUMP_STAT(statsRxPhyErr); - DUMP_STAT(statsRxCollisionErr); - DUMP_STAT(statsTxErr); - DUMP_STAT(statsTxFrameErr); - DUMP_STAT(statsTxOverFlowErr); - DUMP_STAT(statsTxLateCollisionErr); - DUMP_STAT(statsTxExcessCollisionErr); - DUMP_STAT(statsTxUnderFlowErr); - DUMP_STAT(statsTxTsErr); -#endif - -} - -void enet_buf_info(void) -{ - int i = 0; - for (i = 0; i < ENET_RXBD_NUM; i++) - { - rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n", - i, - g_rxBuffDescrip[i].length, - g_rxBuffDescrip[i].control, - g_rxBuffDescrip[i].buffer); - } - - for (i = 0; i < ENET_TXBD_NUM; i++) - { - rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n", - i, - g_txBuffDescrip[i].length, - g_txBuffDescrip[i].control, - g_txBuffDescrip[i].buffer); - } -} - -FINSH_FUNCTION_EXPORT(phy_read, read phy register); -FINSH_FUNCTION_EXPORT(phy_write, write phy register); -FINSH_FUNCTION_EXPORT(phy_dump, dump phy registers); -FINSH_FUNCTION_EXPORT(enet_reg_dump, dump enet registers); -FINSH_FUNCTION_EXPORT(enet_nvic_tog, toggle enet nvic pendding bit); -FINSH_FUNCTION_EXPORT(enet_rx_stat, dump enet rx statistic); -FINSH_FUNCTION_EXPORT(enet_buf_info, dump enet tx and tx buffer descripter); - -#endif diff --git a/bsp/imxrt1052-evk/drivers/drv_ft5406.c b/bsp/imxrt1052-evk/drivers/drv_ft5406.c deleted file mode 100644 index df81f2e52a..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_ft5406.c +++ /dev/null @@ -1,354 +0,0 @@ -/* - * File : drv_ft5406.c - * FT5406 touch driver - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2017-08-08 Yang the first version - */ - -#include -#include -#include - -#include -#include - -#include "board.h" - -#include "fsl_gpio.h" -#include "fsl_lpi2c.h" - -#define BSP_TOUCH_SAMPLE_HZ 30 - -#define I2CBUS_NAME "i2c1" - -#if 0 -#define FTDEBUG rt_kprintf -#else -#define FTDEBUG(...) -#endif - -#define TOUCH_SLP_TIME (RT_TICK_PER_SECOND * 5) - -#define FT5206_TS_ADDR 0x38 -#define TP_MAX_TOUCH_POINT 2 - -enum ft5x0x_ts_regs -{ - FT5X0X_REG_THGROUP = 0x80, - FT5X0X_REG_THPEAK = 0x81, - FT5X0X_REG_THCAL = 0x82, - FT5X0X_REG_THWATER = 0x83, - FT5X0X_REG_THTEMP = 0x84, - FT5X0X_REG_THDIFF = 0x85, - FT5X0X_REG_CTRL = 0x86, - FT5X0X_REG_TIMEENTERMONITOR = 0x87, - FT5X0X_REG_PERIODACTIVE = 0x88, - FT5X0X_REG_PERIODMONITOR = 0x89, - FT5X0X_REG_HEIGHT_B = 0x8a, - FT5X0X_REG_MAX_FRAME = 0x8b, - FT5X0X_REG_DIST_MOVE = 0x8c, - FT5X0X_REG_DIST_POINT = 0x8d, - FT5X0X_REG_FEG_FRAME = 0x8e, - FT5X0X_REG_SINGLE_CLICK_OFFSET = 0x8f, - FT5X0X_REG_DOUBLE_CLICK_TIME_MIN = 0x90, - FT5X0X_REG_SINGLE_CLICK_TIME = 0x91, - FT5X0X_REG_LEFT_RIGHT_OFFSET = 0x92, - FT5X0X_REG_UP_DOWN_OFFSET = 0x93, - FT5X0X_REG_DISTANCE_LEFT_RIGHT = 0x94, - FT5X0X_REG_DISTANCE_UP_DOWN = 0x95, - FT5X0X_REG_ZOOM_DIS_SQR = 0x96, - FT5X0X_REG_RADIAN_VALUE = 0x97, - FT5X0X_REG_MAX_X_HIGH = 0x98, - FT5X0X_REG_MAX_X_LOW = 0x99, - FT5X0X_REG_MAX_Y_HIGH = 0x9a, - FT5X0X_REG_MAX_Y_LOW = 0x9b, - FT5X0X_REG_K_X_HIGH = 0x9c, - FT5X0X_REG_K_X_LOW = 0x9d, - FT5X0X_REG_K_Y_HIGH = 0x9e, - FT5X0X_REG_K_Y_LOW = 0x9f, - FT5X0X_REG_AUTO_CLB_MODE = 0xa0, - FT5X0X_REG_LIB_VERSION_H = 0xa1, - FT5X0X_REG_LIB_VERSION_L = 0xa2, - FT5X0X_REG_CIPHER = 0xa3, - FT5X0X_REG_G_MODE = 0xa4, - FT5X0X_REG_PMODE = 0xa5, /* Power Consume Mode */ - FT5X0X_REG_FIRMID = 0xa6, - FT5X0X_REG_STATE = 0xa7, - FT5X0X_REG_VENDID = 0xa8, - FT5X0X_REG_ERR = 0xa9, - FT5X0X_REG_CLB = 0xaa, -}; - -#define CTRL_NOAUTO_MONITOR 0x00 -#define CTRL_AUTO_MONITOR 0x01 - -#define PMODE_ACTIVE 0x00 -#define PMODE_MONITOR 0x01 -#define PMODE_STANDBY 0x02 -#define PMODE_HIBERNATE 0x03 - -#define G_MODE_POLLING 0x00 -#define G_MODE_TRIGGER 0x01 - -typedef enum _touch_event -{ - kTouch_Down = 0, /*!< The state changed to touched. */ - kTouch_Up = 1, /*!< The state changed to not touched. */ - kTouch_Contact = 2, /*!< There is a continuous touch being detected. */ - kTouch_Reserved = 3 /*!< No touch information available. */ -} touch_event_t; - -typedef struct _touch_point -{ - touch_event_t TOUCH_EVENT; /*!< Indicates the state or event of the touch point. */ - uint8_t TOUCH_ID; /*!< Id of the touch point. This numeric value stays constant between down and up event. */ - uint16_t TOUCH_X; /*!< X coordinate of the touch point */ - uint16_t TOUCH_Y; /*!< Y coordinate of the touch point */ -} touch_point_t; - -typedef struct _ft5406_touch_point -{ - uint8_t XH; - uint8_t XL; - uint8_t YH; - uint8_t YL; - uint8_t RESERVED[2]; -} ft5406_touch_point_t; - -typedef struct _ft5406_touch_data -{ - uint8_t DEVIDE_MODE; - uint8_t GEST_ID; - uint8_t TD_STATUS; - ft5406_touch_point_t TOUCH; -} ft5406_touch_data_t; - -#define TOUCH_POINT_GET_EVENT(T) ((touch_event_t)((T).XH >> 6)) -#define TOUCH_POINT_GET_ID(T) ((T).YH >> 4) -#define TOUCH_POINT_GET_X(T) ((((T).XH & 0x0f) << 8) | (T).XL) -#define TOUCH_POINT_GET_Y(T) ((((T).YH & 0x0f) << 8) | (T).YL) - -static struct rt_i2c_bus_device *_i2c_bus; -static struct rt_semaphore _tp_sem; - -static int _ft5406_read(unsigned char cmd, - void *buf, - size_t len) -{ - struct rt_i2c_msg msgs[2]; - - msgs[0].addr = FT5206_TS_ADDR; - msgs[0].flags = RT_I2C_WR; - msgs[0].buf = &cmd; - msgs[0].len = sizeof(cmd); - - msgs[1].addr = FT5206_TS_ADDR; - msgs[1].flags = RT_I2C_RD; - msgs[1].buf = buf; - msgs[1].len = len; - - if (rt_i2c_transfer(_i2c_bus, msgs, 2) == 2) - return len; - else - return -1; -} - -static int ft5406_read_touch(touch_point_t *dp) -{ - ft5406_touch_data_t touch_data; - - _ft5406_read(0, &touch_data, sizeof(ft5406_touch_data_t)); - - FTDEBUG("GEST_ID: %02x, TD_STATUS: %02x\n", touch_data.GEST_ID, touch_data.TD_STATUS); - FTDEBUG("XH: %02x, XL: %02x, XH: %02x, XH: %02x, XH: %02x, RESERVED[0]: %02x, RESERVED[1]: %02x\n", - touch_data.TOUCH.XH, touch_data.TOUCH.XL, - touch_data.TOUCH.YH, touch_data.TOUCH.YL, - touch_data.TOUCH.RESERVED[0], touch_data.TOUCH.RESERVED[1]); - - dp->TOUCH_X = TOUCH_POINT_GET_Y(touch_data.TOUCH); - dp->TOUCH_Y = TOUCH_POINT_GET_X(touch_data.TOUCH); - - FTDEBUG(" ==> status : %d (%d, %d)\n", touch_data.TD_STATUS, dp->TOUCH_X, dp->TOUCH_Y); - - if (touch_data.TD_STATUS != 0) - return 0; - else - return -1; -} - -static void _touch_session() -{ - touch_point_t tpd; -#ifdef RT_USING_RTGUI - struct rtgui_event_mouse emouse; -#endif - - ft5406_read_touch(&tpd); - -#ifdef RT_USING_RTGUI - emouse.parent.sender = RT_NULL; - emouse.wid = RT_NULL; - - emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; - emouse.button = RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_DOWN; - emouse.x = tpd.TOUCH_X; - emouse.y = tpd.TOUCH_Y; - emouse.ts = rt_tick_get(); - emouse.id = emouse.ts; - if (emouse.id == 0) emouse.id = 1; - rtgui_server_post_event(&emouse.parent, sizeof(emouse)); -#endif - - do - { - rt_thread_delay(RT_TICK_PER_SECOND / BSP_TOUCH_SAMPLE_HZ); - if (ft5406_read_touch(&tpd) != 0) - break; - -#ifdef RT_USING_RTGUI - emouse.parent.type = RTGUI_EVENT_MOUSE_MOTION; - emouse.x = tpd.TOUCH_X; - emouse.y = tpd.TOUCH_Y; - emouse.ts = rt_tick_get(); - rtgui_server_post_event(&emouse.parent, sizeof(emouse)); -#endif - } - while (1); - -#ifdef RT_USING_RTGUI - /* Always send touch up event. */ - emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; - emouse.button = RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_UP; - emouse.x = tpd.TOUCH_X; - emouse.y = tpd.TOUCH_Y; - emouse.ts = rt_tick_get(); - rtgui_server_post_event(&emouse.parent, sizeof(emouse)); -#endif - - //} while (rt_sem_take(&_tp_sem, TOUCH_SLP_TIME) == RT_EOK); -} - -void touch_down(void) -{ - rt_sem_release(&_tp_sem); -} - -static void _touch(void *p) -{ - int io_s; - - gpio_pin_config_t pin_config = - { - kGPIO_DigitalInput, 0, - }; - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_GPIO1_IO11, 0U); - - /* Enable touch panel controller */ - GPIO_PinInit(GPIO1, 11, &pin_config); - - while(1) - { - rt_thread_delay(RT_TICK_PER_SECOND / 60); - - io_s = GPIO_ReadPinInput(GPIO1, 11); - if (io_s == 0) - { - _touch_session(); - } - else - continue; - } -} - -static rt_device_t _i2c_find(const char *name) -{ - rt_device_t dev; - - dev = rt_device_find(name); - if (!dev) - { - rt_kprintf("search device failed: %s\n", name); - return RT_NULL; - } - - if (rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) != RT_EOK) - { - rt_kprintf("open device failed: %s\n", name); - return RT_NULL; - } - - rt_kprintf("open i2c bus: %s\n", name); - - return dev; -} - -static void ft5406_hw_reset(void) -{ - gpio_pin_config_t pin_config = - { - kGPIO_DigitalOutput, 0, - }; - - CLOCK_EnableClock(kCLOCK_Gpio1); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0x10B0u); - - /* Enable touch panel controller */ - GPIO_PinInit(GPIO1, 2, &pin_config); - GPIO_WritePinOutput(GPIO1, 2, 1); - rt_thread_delay(RT_TICK_PER_SECOND / 20); - GPIO_WritePinOutput(GPIO1, 2, 0); - rt_thread_delay(RT_TICK_PER_SECOND / 20); - GPIO_WritePinOutput(GPIO1, 2, 1); -} - -int ft5406_hw_init(void) -{ - rt_thread_t tid; - - rt_device_t dev = _i2c_find(I2CBUS_NAME); - if (dev == RT_NULL) - { - FTDEBUG("search i2c device faild: %s\n", I2CBUS_NAME); - return -1; - } - else - { - FTDEBUG("ft5406 set i2c bus to %s\n", I2CBUS_NAME); - _i2c_bus = (struct rt_i2c_bus_device *)dev; - } - - ft5406_hw_reset(); - - rt_sem_init(&_tp_sem, "touch", 0, RT_IPC_FLAG_FIFO); - tid = rt_thread_create("touch", _touch, RT_NULL, 2048, 10, 20); - if (!tid) - { - rt_device_close(dev); - return -1; - } - - rt_thread_startup(tid); - - return 0; -} -INIT_APP_EXPORT(ft5406_hw_init); diff --git a/bsp/imxrt1052-evk/drivers/drv_hwtimer.c b/bsp/imxrt1052-evk/drivers/drv_hwtimer.c deleted file mode 100644 index 41ef5d4b5b..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_hwtimer.c +++ /dev/null @@ -1,189 +0,0 @@ -/* -* File : drv_hwtimer.c -* This file is part of RT-Thread RTOS -* COPYRIGHT (C) 2017, RT-Thread Development Team -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -* -* Change Logs: -* Date Author Notes -* 2018-04-17 WangBing the first version. -*/ - -#include -#include -#include "drv_hwtimer.h" - -#include "fsl_common.h" -#include "fsl_gpt.h" - -#ifdef RT_USING_HWTIMER - -#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL -#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" -#endif - -/* Select IPG Clock as PERCLK_CLK clock source */ -#define EXAMPLE_GPT_CLOCK_SOURCE_SELECT (0U) -/* Clock divider for PERCLK_CLK clock source */ -#define EXAMPLE_GPT_CLOCK_DIVIDER_SELECT (5U) -/* Get source clock for GPT driver (GPT prescaler = 6) */ -#define EXAMPLE_GPT_CLK_FREQ (CLOCK_GetFreq(kCLOCK_IpgClk) / (EXAMPLE_GPT_CLOCK_DIVIDER_SELECT + 1U)) - -static void NVIC_Configuration(void) -{ - EnableIRQ(GPT1_IRQn); -} - -static rt_err_t rt1052_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) -{ - rt_err_t err = RT_EOK; - GPT_Type *hwtimer_dev; - hwtimer_dev = (GPT_Type *)timer->parent.user_data; - - RT_ASSERT(timer != RT_NULL); - - switch (cmd) - { - case HWTIMER_CTRL_FREQ_SET: - { - uint32_t clk; - uint32_t pre; - clk = EXAMPLE_GPT_CLK_FREQ; - pre = clk / *((uint32_t *)args) - 1; - GPT_SetClockDivider(hwtimer_dev, pre); - } - break; - default: - err = -RT_ENOSYS; - break; - } - return err; -} - -static rt_uint32_t rt1052_hwtimer_count_get(rt_hwtimer_t *timer) -{ - rt_uint32_t CurrentTimer_Count; - GPT_Type *hwtimer_dev; - hwtimer_dev = (GPT_Type *)timer->parent.user_data; - - RT_ASSERT(timer != RT_NULL); - - CurrentTimer_Count = GPT_GetCurrentTimerCount(hwtimer_dev); - - return CurrentTimer_Count; -} - -static void rt1052_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) -{ - GPT_Type *hwtimer_dev; - gpt_config_t gptConfig; - hwtimer_dev = (GPT_Type *)timer->parent.user_data; - - RT_ASSERT(timer != RT_NULL); - - GPT_Deinit(hwtimer_dev); - - if (state == 1) - { - /*Clock setting for GPT*/ - CLOCK_SetMux(kCLOCK_PerclkMux, EXAMPLE_GPT_CLOCK_SOURCE_SELECT); - CLOCK_SetDiv(kCLOCK_PerclkDiv, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT); - - /* Initialize GPT module by default config */ - GPT_GetDefaultConfig(&gptConfig); - GPT_Init(hwtimer_dev, &gptConfig); - } -} - -static rt_err_t rt1052_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) -{ - GPT_Type *hwtimer_dev; - hwtimer_dev = (GPT_Type *)timer->parent.user_data; - - RT_ASSERT(timer != RT_NULL); - - hwtimer_dev->CR |= (mode == HWTIMER_MODE_PERIOD) ? GPT_CR_FRR_MASK : 0U; - - GPT_SetOutputCompareValue(hwtimer_dev, kGPT_OutputCompare_Channel1, cnt); - - GPT_EnableInterrupts(hwtimer_dev, kGPT_OutputCompare1InterruptEnable); - - NVIC_Configuration(); - - GPT_StartTimer(hwtimer_dev); - - return RT_EOK; -} - -static void rt1052_hwtimer_stop(rt_hwtimer_t *timer) -{ - GPT_Type *hwtimer_dev; - hwtimer_dev = (GPT_Type *)timer->parent.user_data; - - RT_ASSERT(timer != RT_NULL); - - GPT_StopTimer(hwtimer_dev); -} - -static const struct rt_hwtimer_ops rt1052_hwtimer_ops = -{ - rt1052_hwtimer_init, - rt1052_hwtimer_start, - rt1052_hwtimer_stop, - rt1052_hwtimer_count_get, - rt1052_hwtimer_control, -}; - -static const struct rt_hwtimer_info rt1052_hwtimer_info = -{ - 25000000, /* the maximum count frequency can be set */ - 6103, /* the minimum count frequency can be set */ - 0xFFFFFFFF, - HWTIMER_CNTMODE_UP, -}; - -static rt_hwtimer_t GPT_timer1; - -int rt1052_hw_hwtimer_init(void) -{ - int ret = RT_EOK; - - GPT_timer1.info = &rt1052_hwtimer_info; - GPT_timer1.ops = &rt1052_hwtimer_ops; - - rt_device_hwtimer_register(&GPT_timer1, "_timer", GPT1); - - return ret; -} - -void GPT1_IRQHandler(void) -{ - if (GPT_GetStatusFlags(GPT1, kGPT_OutputCompare1Flag) != 0) - { - GPT_ClearStatusFlags(GPT1, kGPT_OutputCompare1Flag); - rt_device_hwtimer_isr(&GPT_timer1); - } - - /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U || __CORTEX_M == 7U) - __DSB(); -#endif -} - -INIT_DEVICE_EXPORT(rt1052_hw_hwtimer_init); - -#endif /*RT_USING_HWTIMER*/ diff --git a/bsp/imxrt1052-evk/drivers/drv_hwtimer.h b/bsp/imxrt1052-evk/drivers/drv_hwtimer.h deleted file mode 100644 index b37d586c96..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_hwtimer.h +++ /dev/null @@ -1,34 +0,0 @@ -/* -* File : drv_hwtimer.h -* This file is part of RT-Thread RTOS -* COPYRIGHT (C) 2017, RT-Thread Development Team -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -* -* Change Logs: -* Date Author Notes -* 2018-04-17 WangBing the first version. -*/ - -#ifndef __DRV_HWTIMER_H__ -#define __DRV_HWTIMER_H__ - -#include -#include - -int rt1052_hw_hwtimer_init(void); - -#endif - diff --git a/bsp/imxrt1052-evk/drivers/drv_i2c.c b/bsp/imxrt1052-evk/drivers/drv_i2c.c deleted file mode 100644 index edd65cb1ac..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_i2c.c +++ /dev/null @@ -1,475 +0,0 @@ -/* - * File : drv_i2c.c - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2017-08-08 Yang the first version - * 2018-03-24 LaiYiKeTang add hardware iic - */ - -#include -#include -#include "board.h" -#include "fsl_gpio.h" -#include "fsl_lpi2c.h" -#include "drv_i2c.h" - -//#define DRV_I2C_DEBUG - -#ifdef RT_USING_I2C - -#define I2C1BUS_NAME "i2c1" -#define I2C2BUS_NAME "i2c2" -#define I2C3BUS_NAME "i2c3" -#define I2C4BUS_NAME "i2c4" - -#define LPI2C_CLOCK_SOURCE_DIVIDER 4 - -/* Get frequency of lpi2c clock */ -#define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER)) - -#ifdef RT_USING_HW_I2C1 -static struct rt1052_i2c_bus lpi2c1 = -{ - .I2C = LPI2C1, - .device_name = I2C1BUS_NAME, -}; -#endif /* RT_USING_HW_I2C1 */ - -#ifdef RT_USING_HW_I2C2 -static struct rt1052_i2c_bus lpi2c2 = -{ - .I2C = LPI2C2, - .device_name = I2C2BUS_NAME, -}; -#endif /* RT_USING_HW_I2C2 */ - -#ifdef RT_USING_HW_I2C3 -static struct rt1052_i2c_bus lpi2c3 = -{ - .I2C = LPI2C3, - .device_name = I2C3BUS_NAME, -}; -#endif /* RT_USING_HW_I2C3 */ - -#ifdef RT_USING_HW_I2C4 -static struct rt1052_i2c_bus lpi2c4 = -{ - .I2C = LPI2C4, - .device_name = I2C4BUS_NAME, -}; -#endif /* RT_USING_HW_I2C4 */ - -#if (defined(RT_USING_HW_I2C1) || defined(RT_USING_HW_I2C2) || defined(RT_USING_HW_I2C3) || defined(RT_USING_HW_I2C4)) - -static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num); -static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num); -static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus, - rt_uint32_t, - rt_uint32_t); - -static const struct rt_i2c_bus_device_ops imxrt_i2c_ops = -{ - imxrt_i2c_mst_xfer, - imxrt_i2c_slv_xfer, - imxrt_i2c_bus_control, -}; - -void imxrt_lpi2c_gpio_init(struct rt1052_i2c_bus *bus) -{ - if (bus->I2C == LPI2C1) - { - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, - 1U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, - 1U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, - 0xD8B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, - 0xD8B0u); - } - else if (bus->I2C == LPI2C2) - { - IOMUXC_SetPinMux( - IOMUXC_GPIO_B0_04_LPI2C2_SCL, - 1U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_B0_05_LPI2C2_SDA, - 1U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B0_04_LPI2C2_SCL, - 0xD8B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B0_05_LPI2C2_SDA, - 0xD8B0u); - } - else if (bus->I2C == LPI2C3) - { - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, - 1U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, - 1U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, - 0xD8B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, - 0xD8B0u); - } - else if (bus->I2C == LPI2C4) - { - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_12_LPI2C4_SCL, - 1U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_11_LPI2C4_SDA, - 1U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_12_LPI2C4_SCL, - 0xD8B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_11_LPI2C4_SDA, - 0xD8B0u); - } - else - { - RT_ASSERT(RT_NULL); - } -} - -static rt_err_t imxrt_lpi2c_configure(struct rt1052_i2c_bus *bus, lpi2c_master_config_t *cfg) -{ - RT_ASSERT(bus != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - - imxrt_lpi2c_gpio_init(bus); - bus->parent.ops = &imxrt_i2c_ops; - LPI2C_MasterInit(bus->I2C, cfg, LPI2C_CLOCK_FREQUENCY); - return RT_EOK; -} - -status_t LPI2C_MasterCheck(LPI2C_Type *base, uint32_t status) -{ - status_t result = kStatus_Success; - - /* Check for error. These errors cause a stop to automatically be sent. We must */ - /* clear the errors before a new transfer can start. */ - status &= 0x3c00; - if (status) - { - /* Select the correct error code. Ordered by severity, with bus issues first. */ - if (status & kLPI2C_MasterPinLowTimeoutFlag) - { - result = kStatus_LPI2C_PinLowTimeout; - } - else if (status & kLPI2C_MasterArbitrationLostFlag) - { - result = kStatus_LPI2C_ArbitrationLost; - } - else if (status & kLPI2C_MasterNackDetectFlag) - { - result = kStatus_LPI2C_Nak; - } - else if (status & kLPI2C_MasterFifoErrFlag) - { - result = kStatus_LPI2C_FifoError; - } - else - { - assert(false); - } - - /* Clear the flags. */ - LPI2C_MasterClearStatusFlags(base, status); - - /* Reset fifos. These flags clear automatically. */ - base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; - } - - return result; -} - -/*! - * @brief Wait until the tx fifo all empty. - * @param base The LPI2C peripheral base address. - * @retval #kStatus_Success - * @retval #kStatus_LPI2C_PinLowTimeout - * @retval #kStatus_LPI2C_ArbitrationLost - * @retval #kStatus_LPI2C_Nak - * @retval #kStatus_LPI2C_FifoError - */ -static status_t LPI2C_MasterWaitForTxFifoAllEmpty(LPI2C_Type *base) -{ - uint32_t status; - size_t txCount; - do - { - status_t result; - - /* Get the number of words in the tx fifo and compute empty slots. */ - LPI2C_MasterGetFifoCounts(base, NULL, &txCount); - - /* Check for error flags. */ - status = LPI2C_MasterGetStatusFlags(base); - result = LPI2C_MasterCheck(base, status); - if (result) - { - return result; - } - } - while (txCount); - return kStatus_Success; -} - -static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num) -{ - struct rt1052_i2c_bus *rt1052_i2c; - rt_size_t i; - RT_ASSERT(bus != RT_NULL); - rt1052_i2c = (struct rt1052_i2c_bus *) bus; - - rt1052_i2c->msg = msgs; - rt1052_i2c->msg_ptr = 0; - rt1052_i2c->msg_cnt = num; - rt1052_i2c->dptr = 0; - - for (i = 0; i < num; i++) - { - if (rt1052_i2c->msg[i].flags & RT_I2C_RD) - { - if (LPI2C_MasterStart(rt1052_i2c->I2C, rt1052_i2c->msg[i].addr, kLPI2C_Read) != kStatus_Success) - { - i = 0; - break; - } - if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1052_i2c->I2C) != kStatus_Success) - { - i = 0; - break; - } - if (LPI2C_MasterReceive(rt1052_i2c->I2C, rt1052_i2c->msg[i].buf, rt1052_i2c->msg[i].len) != kStatus_Success) - { - i = 0; - break; - } - if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1052_i2c->I2C) != kStatus_Success) - { - i = 0; - break; - } - } - else - { - if (LPI2C_MasterStart(rt1052_i2c->I2C, rt1052_i2c->msg[i].addr, kLPI2C_Write) != kStatus_Success) - { - i = 0; - break; - } - if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1052_i2c->I2C) != kStatus_Success) - { - i = 0; - break; - } - if (LPI2C_MasterSend(rt1052_i2c->I2C, rt1052_i2c->msg[i].buf, rt1052_i2c->msg[i].len) != kStatus_Success) - { - i = 0; - break; - } - if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1052_i2c->I2C) != kStatus_Success) - { - i = 0; - break; - } - } - } - i2c_dbg("send stop condition\n"); - if (LPI2C_MasterStop(rt1052_i2c->I2C) != kStatus_Success) - { - i = 0; - } - - rt1052_i2c->msg = RT_NULL; - rt1052_i2c->msg_ptr = 0; - rt1052_i2c->msg_cnt = 0; - rt1052_i2c->dptr = 0; - return i; -} - -static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num) -{ - return 0; -} -static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus, - rt_uint32_t cmd, - rt_uint32_t arg) -{ - return RT_ERROR; -} - -#endif - -int rt_hw_i2c_init(void) -{ -#if (defined(RT_USING_HW_I2C1) || defined(RT_USING_HW_I2C2) || defined(RT_USING_HW_I2C3) || defined(RT_USING_HW_I2C4)) - - lpi2c_master_config_t masterConfig = {0}; - - /*Clock setting for LPI2C*/ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_SOURCE_DIVIDER - 1); - -#endif - -#if defined(RT_USING_HW_I2C1) - LPI2C_MasterGetDefaultConfig(&masterConfig); -#if defined(HW_I2C1_BADURATE_400kHZ) - masterConfig.baudRate_Hz = 400000U; -#elif defined(HW_I2C1_BADURATE_100kHZ) - masterConfig.baudRate_Hz = 100000U; -#endif - imxrt_lpi2c_configure(&lpi2c1, &masterConfig); - rt_i2c_bus_device_register(&lpi2c1.parent, lpi2c1.device_name); -#endif - -#if defined(RT_USING_HW_I2C2) - LPI2C_MasterGetDefaultConfig(&masterConfig); -#if defined(HW_I2C2_BADURATE_400kHZ) - masterConfig.baudRate_Hz = 400000U; -#elif defined(HW_I2C2_BADURATE_100kHZ) - masterConfig.baudRate_Hz = 100000U; -#endif - imxrt_lpi2c_configure(&lpi2c2, &masterConfig); - rt_i2c_bus_device_register(&lpi2c2.parent, lpi2c2.device_name); -#endif - -#if defined(RT_USING_HW_I2C3) - LPI2C_MasterGetDefaultConfig(&masterConfig); -#if defined(HW_I2C3_BADURATE_400kHZ) - masterConfig.baudRate_Hz = 400000U; -#elif defined(HW_I2C3_BADURATE_100kHZ) - masterConfig.baudRate_Hz = 100000U; -#endif - imxrt_lpi2c_configure(&lpi2c3, &masterConfig); - rt_i2c_bus_device_register(&lpi2c3.parent, lpi2c3.device_name); -#endif - -#if defined(RT_USING_HW_I2C4) - LPI2C_MasterGetDefaultConfig(&masterConfig); -#if defined(HW_I2C4_BADURATE_400kHZ) - masterConfig.baudRate_Hz = 400000U; -#elif defined(HW_I2C4_BADURATE_100kHZ) - masterConfig.baudRate_Hz = 100000U; -#endif - imxrt_lpi2c_configure(&lpi2c4, &masterConfig); - rt_i2c_bus_device_register(&lpi2c4.parent, lpi2c4.device_name); -#endif - - return 0; -} -INIT_DEVICE_EXPORT(rt_hw_i2c_init); - -#if defined(RT_USING_FINSH) && defined(DRV_I2C_DEBUG) -#include - -static rt_device_t _i2c_find(const char *name) -{ - rt_device_t dev; - - dev = rt_device_find(name); - if (!dev) - { - rt_kprintf("search device failed: %s\n", name); - return RT_NULL; - } - - if (rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) != RT_EOK) - { - rt_kprintf("open device failed: %s\n", name); - return RT_NULL; - } - - rt_kprintf("open i2c bus: %s\n", name); - - return dev; -} - -static void _search_i2c_device(rt_device_t dev, uint8_t cmd) -{ - int count = 0; - struct rt_i2c_msg msgs[2]; - uint8_t buf = 0; - - msgs[0].flags = RT_I2C_WR; - msgs[0].buf = &cmd; - msgs[0].len = sizeof(cmd); - - msgs[1].flags = RT_I2C_RD; - msgs[1].buf = &buf; - msgs[1].len = 1; - - for (int i = 0; i <= 0x7f; i++) - { - int len; - - msgs[0].addr = i; - msgs[1].addr = i; - len = rt_i2c_transfer((struct rt_i2c_bus_device *)dev, msgs, 2); - if (len == 2) - { - count++; - rt_kprintf("add:%02X transfer success, id: %02X\n", i, buf); - } - } - - rt_kprintf("i2c device: %d\n", count); -} - -static int i2c_test(const char *name, uint8_t cmd) -{ - rt_device_t dev = _i2c_find(name); - - if (dev == RT_NULL) - { - rt_kprintf("search i2c device faild\n"); - return -1; - } - - _search_i2c_device(dev, cmd); - rt_device_close(dev); - - return 0; -} -FINSH_FUNCTION_EXPORT(i2c_test, e.g: i2c_test("i2c1", 0xA3)); - -#endif - -#endif /* RT_USING_I2C */ diff --git a/bsp/imxrt1052-evk/drivers/drv_i2c.h b/bsp/imxrt1052-evk/drivers/drv_i2c.h deleted file mode 100644 index 4743225c37..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_i2c.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * File : drv_i2c.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2018-03-24 LaiYiKeTang the first version - */ - -#ifndef __DRVI2C_H__ -#define __DRVI2C_H__ - -#include -#include -#include -#include "board.h" -struct rt1052_i2c_bus -{ - struct rt_i2c_bus_device parent; - LPI2C_Type *I2C; - struct rt_i2c_msg *msg; - rt_uint32_t msg_cnt; - volatile rt_uint32_t msg_ptr; - volatile rt_uint32_t dptr; - char *device_name; -}; - -#endif - diff --git a/bsp/imxrt1052-evk/drivers/drv_lcd.c b/bsp/imxrt1052-evk/drivers/drv_lcd.c deleted file mode 100644 index 911b8d0786..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_lcd.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * File : drv_lcd.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2017-10-30 Tanek the first version - * 2018-04-05 Liu2guang export LCD config parameters. - */ - -#include "drv_lcd.h" - -#include "fsl_common.h" -#include "fsl_iomuxc.h" -#include "fsl_elcdif.h" - -#if !defined(LCD_WIDTH) || !defined(LCD_HEIGHT) - #error "Please config lcd pixel parameters." -#endif - -#if !defined(LCD_HFP) || !defined(LCD_HBP) || !defined(LCD_HSW) || \ - !defined(LCD_VFP) || !defined(LCD_VBP) || !defined(LCD_VSW) - #error "Please config lcd timing parameters." -#endif - -#if !defined(LCD_BL_PIN) || !defined(LCD_RST_PIN) - #error "Please config lcd backlight or reset pin." -#endif - -struct rt1050_lcd -{ - struct rt_device device; - struct rt_device_graphic_info info; -}; - -static struct rt1050_lcd lcd; -ALIGN(64) static uint16_t frame_buffer[LCD_HEIGHT][LCD_WIDTH] SECTION("NonCacheable"); - -static rt_err_t rt1050_lcd_init(rt_device_t device) -{ - RT_ASSERT(device != RT_NULL); - - rt_memset(frame_buffer, 0x00, sizeof(frame_buffer)); - - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - - /* - * Initialize the Video PLL. - * Video PLL output clock is OSC24M * (loopDivider + (denominator / numerator)) / postDivider = 93MHz. - */ - clock_video_pll_config_t config = - { - .loopDivider = 31, .postDivider = 8, .numerator = 0, .denominator = 1, - }; - - CLOCK_InitVideoPll(&config); - - /* - * 000 derive clock from PLL2 - * 001 derive clock from PLL3 PFD3 - * 010 derive clock from PLL5 - * 011 derive clock from PLL2 PFD0 - * 100 derive clock from PLL2 PFD1 - * 101 derive clock from PLL3 PFD1 - */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 2); - - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 4); - - CLOCK_SetDiv(kCLOCK_LcdifDiv, 1); - - /* GPIO */ - CLOCK_EnableClock(kCLOCK_Iomuxc); - - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0U); /* LCD_B3 */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0U); /* LCD_B4 */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0U); /* LCD_B5 */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0U); /* LCD_B6 */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0U); /* LCD_B7 */ - - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0U); /* LCD_G2 */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0U); /* LCD_G3 */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0U); /* LCD_G4 */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0U); /* LCD_G5 */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0U); /* LCD_G6 */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0U); /* LCD_G7 */ - - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0U); /* LCD_R3 */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0U); /* LCD_R4 */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0U); /* LCD_R5 */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0U); /* LCD_R6 */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0U); /* LCD_R7 */ - - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0u); /* LCD_CLK */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0u); /* LCD_HSYNC */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0u); /* LCD_VSYNC */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0u); /* LCD_ENABLE */ - - rt_pin_mode(LCD_RST_PIN, PIN_MODE_OUTPUT); /* LCD_RESET */ - rt_pin_write(LCD_RST_PIN, PIN_LOW); - rt_thread_delay(RT_TICK_PER_SECOND / 100); - rt_pin_write(LCD_RST_PIN, PIN_HIGH); - - rt_pin_mode(LCD_BL_PIN, PIN_MODE_OUTPUT); /* LCD_BL */ - rt_pin_write(LCD_BL_PIN, PIN_HIGH); - - /* LCD */ - elcdif_rgb_mode_config_t lcd_config; - - lcd_config.hfp = LCD_HFP; - lcd_config.vfp = LCD_VFP; - lcd_config.hbp = LCD_HBP; - lcd_config.vbp = LCD_VBP; - lcd_config.hsw = LCD_HSW; - lcd_config.vsw = LCD_VSW; - - lcd_config.polarityFlags = kELCDIF_DataEnableActiveHigh | - kELCDIF_VsyncActiveHigh | - kELCDIF_HsyncActiveLow | - kELCDIF_DriveDataOnRisingClkEdge; - - lcd_config.panelWidth = LCD_WIDTH; - lcd_config.panelHeight = LCD_HEIGHT; - lcd_config.pixelFormat = kELCDIF_PixelFormatRGB565; - lcd_config.dataBus = kELCDIF_DataBus16Bit; - lcd_config.bufferAddr = (uint32_t)frame_buffer; - - ELCDIF_RgbModeInit(LCDIF, &lcd_config); - ELCDIF_RgbModeStart(LCDIF); - - /* LCD DEVICE */ - lcd.info.width = LCD_WIDTH; - lcd.info.height = LCD_HEIGHT; - lcd.info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; - lcd.info.bits_per_pixel = 16; - lcd.info.framebuffer = (void *)frame_buffer; - - return RT_EOK; -} - -static rt_err_t rt1050_lcd_control(rt_device_t device, int cmd, void *args) -{ - switch (cmd) - { - case RTGRAPHIC_CTRL_RECT_UPDATE: - break; - - case RTGRAPHIC_CTRL_POWERON: - rt_pin_write(LCD_BL_PIN, PIN_HIGH); - break; - - case RTGRAPHIC_CTRL_POWEROFF: - rt_pin_write(LCD_BL_PIN, PIN_LOW); - break; - - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &lcd.info, sizeof(lcd.info)); - break; - - case RTGRAPHIC_CTRL_SET_MODE: - break; - } - - return RT_EOK; -} - -int rt_hw_lcd_init(void) -{ - rt_err_t ret; - - lcd.device.type = RT_Device_Class_Graphic; - lcd.device.init = rt1050_lcd_init; - lcd.device.open = RT_NULL; - lcd.device.close = RT_NULL; - lcd.device.read = RT_NULL; - lcd.device.write = RT_NULL; - lcd.device.control = rt1050_lcd_control; - - lcd.device.user_data = (void *)&lcd.info; - - ret = rt_device_register(&lcd.device, "lcd", RT_DEVICE_FLAG_RDWR); - - return ret; -} -INIT_DEVICE_EXPORT(rt_hw_lcd_init); diff --git a/bsp/imxrt1052-evk/drivers/drv_lcd.h b/bsp/imxrt1052-evk/drivers/drv_lcd.h deleted file mode 100644 index cdde135c78..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_lcd.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * File : drv_lcd2.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2018-04-05 Liuguang the first version. - */ - -#ifndef __DRV_LCD_H__ -#define __DRV_LCD_H__ - -#include -#include - -int rt_hw_lcd_init(void); - -#endif diff --git a/bsp/imxrt1052-evk/drivers/drv_pcf8574.c b/bsp/imxrt1052-evk/drivers/drv_pcf8574.c deleted file mode 100644 index 165b75a562..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_pcf8574.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * File : drv_pcf8574.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2018-06-12 zylx the first version. - */ -#include "drv_pcf8574.h" - -#define PCF8574_I2CBUS_NAME "i2c1" -static struct rt_i2c_bus_device *pcf8574_i2c_bus; - -int pcf8574_Init(void) -{ - rt_uint8_t value = 0x01; - - pcf8574_i2c_bus = rt_i2c_bus_device_find(PCF8574_I2CBUS_NAME); - - if (pcf8574_i2c_bus == RT_NULL) - { - rt_kprintf("can't find i2c device\r\n"); - return -RT_ERROR; - } - - if (!rt_i2c_master_send(pcf8574_i2c_bus, PCF8574_ADDR, 0, &value, 1)) - { - rt_kprintf("can't find pcf8574\r\n"); - return -RT_ERROR; - } - - return 0; -} -INIT_COMPONENT_EXPORT(pcf8574_Init); - -rt_uint8_t pcf8574_read_byte(void) -{ - rt_uint8_t temp = 0; - rt_i2c_master_recv(pcf8574_i2c_bus, PCF8574_ADDR, 0, &temp, 1); - return temp; -} - -void pcf8574_write_byte(rt_uint8_t data) -{ - rt_i2c_master_send(pcf8574_i2c_bus, PCF8574_ADDR, 0, &data, 1); -} - -void pcf8574_write_bit(rt_uint8_t bit, rt_uint8_t sta) -{ - rt_uint8_t data; - data = pcf8574_read_byte(); - if (sta == 0)data &= ~(1 << bit); - else data |= 1 << bit; - pcf8574_write_byte(data); -} - -rt_uint8_t pcf8574_read_bit(rt_uint8_t bit) -{ - rt_uint8_t data; - data = pcf8574_read_byte(); - if (data & (1 << bit))return 1; - else return 0; -} - diff --git a/bsp/imxrt1052-evk/drivers/drv_pcf8574.h b/bsp/imxrt1052-evk/drivers/drv_pcf8574.h deleted file mode 100644 index 7c8274f2d0..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_pcf8574.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * File : drv_pcf8574.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2018-06-12 zylx the first version. - */ -#ifndef __PCF8574_H -#define __PCF8574_H - -#include -#include "rtdevice.h" - -#define PCF8574_ADDR 0X20 - -rt_uint8_t pcf8574_read_byte(void); -void pcf8574_write_byte(rt_uint8_t data); -void pcf8574_write_bit(rt_uint8_t bit, rt_uint8_t sta); -rt_uint8_t pcf8574_read_bit(rt_uint8_t bit); - -#endif - diff --git a/bsp/imxrt1052-evk/drivers/drv_pin.c b/bsp/imxrt1052-evk/drivers/drv_pin.c deleted file mode 100644 index e834c1265f..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_pin.c +++ /dev/null @@ -1,695 +0,0 @@ -/* - * File : drv_pin.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2018-03-13 Liuguang the first version. - * 2018-03-19 Liuguang add GPIO interrupt mode support. - */ -#include "drv_pin.h" - -#include "fsl_common.h" -#include "fsl_iomuxc.h" -#include "fsl_gpio.h" - -#ifdef RT_USING_PIN - -#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL - #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" -#endif - -struct rt1052_pin -{ - rt_uint16_t pin; - GPIO_Type *gpio; - rt_uint32_t gpio_pin; -}; - -struct rt1052_irq -{ - rt_uint16_t enable; - struct rt_pin_irq_hdr irq_info; -}; - -#define __ARRAY_LEN(array) (sizeof(array)/sizeof(array[0])) -#define __RT1052_PIN_DEFAULT {0, 0, 0} -#define __RT1052_PIN(INDEX, PORT, PIN) {INDEX, PORT, PIN} - -static struct rt_pin_ops rt1052_pin_ops; - -static struct rt1052_pin rt1052_pin_map[] = -{ - __RT1052_PIN_DEFAULT, - - /* GPIO4 */ - __RT1052_PIN( 1, GPIO4, 0), /* GPIO_EMC_00 */ - __RT1052_PIN( 2, GPIO4, 1), /* GPIO_EMC_01 */ - __RT1052_PIN( 3, GPIO4, 2), /* GPIO_EMC_02 */ - __RT1052_PIN( 4, GPIO4, 3), /* GPIO_EMC_03 */ - __RT1052_PIN( 5, GPIO4, 4), /* GPIO_EMC_04 */ - __RT1052_PIN( 6, GPIO4, 5), /* GPIO_EMC_05 */ - __RT1052_PIN( 7, GPIO4, 6), /* GPIO_EMC_06 */ - __RT1052_PIN( 8, GPIO4, 7), /* GPIO_EMC_07 */ - __RT1052_PIN( 9, GPIO4, 8), /* GPIO_EMC_08 */ - __RT1052_PIN(10, GPIO4, 9), /* GPIO_EMC_09 */ - __RT1052_PIN(11, GPIO4, 10), /* GPIO_EMC_10 */ - __RT1052_PIN(12, GPIO4, 11), /* GPIO_EMC_11 */ - __RT1052_PIN(13, GPIO4, 12), /* GPIO_EMC_12 */ - __RT1052_PIN(14, GPIO4, 13), /* GPIO_EMC_13 */ - __RT1052_PIN(15, GPIO4, 14), /* GPIO_EMC_14 */ - __RT1052_PIN(16, GPIO4, 15), /* GPIO_EMC_15 */ - __RT1052_PIN(17, GPIO4, 16), /* GPIO_EMC_16 */ - __RT1052_PIN(18, GPIO4, 17), /* GPIO_EMC_17 */ - __RT1052_PIN(19, GPIO4, 18), /* GPIO_EMC_18 */ - __RT1052_PIN(20, GPIO4, 19), /* GPIO_EMC_19 */ - __RT1052_PIN(21, GPIO4, 20), /* GPIO_EMC_20 */ - __RT1052_PIN(22, GPIO4, 21), /* GPIO_EMC_21 */ - __RT1052_PIN(23, GPIO4, 22), /* GPIO_EMC_22 */ - __RT1052_PIN(24, GPIO4, 23), /* GPIO_EMC_23 */ - __RT1052_PIN(25, GPIO4, 24), /* GPIO_EMC_24 */ - __RT1052_PIN(26, GPIO4, 25), /* GPIO_EMC_25 */ - __RT1052_PIN(27, GPIO4, 26), /* GPIO_EMC_26 */ - __RT1052_PIN(28, GPIO4, 27), /* GPIO_EMC_27 */ - __RT1052_PIN(29, GPIO4, 28), /* GPIO_EMC_28 */ - __RT1052_PIN(30, GPIO4, 29), /* GPIO_EMC_29 */ - __RT1052_PIN(31, GPIO4, 30), /* GPIO_EMC_30 */ - __RT1052_PIN(32, GPIO4, 31), /* GPIO_EMC_31 */ - - __RT1052_PIN(33, GPIO3, 18), /* GPIO_EMC_32 */ - __RT1052_PIN(34, GPIO3, 19), /* GPIO_EMC_33 */ - __RT1052_PIN(35, GPIO3, 20), /* GPIO_EMC_34 */ - __RT1052_PIN(36, GPIO3, 21), /* GPIO_EMC_35 */ - __RT1052_PIN(37, GPIO3, 22), /* GPIO_EMC_36 */ - __RT1052_PIN(38, GPIO3, 23), /* GPIO_EMC_37 */ - __RT1052_PIN(39, GPIO3, 24), /* GPIO_EMC_38 */ - __RT1052_PIN(40, GPIO3, 25), /* GPIO_EMC_39 */ - __RT1052_PIN(41, GPIO3, 26), /* GPIO_EMC_40 */ - __RT1052_PIN(42, GPIO3, 27), /* GPIO_EMC_41 */ - - /* GPIO1 */ - __RT1052_PIN(43, GPIO1, 0), /* GPIO_AD_B0_00 */ - __RT1052_PIN(44, GPIO1, 1), /* GPIO_AD_B0_01 */ - __RT1052_PIN(45, GPIO1, 2), /* GPIO_AD_B0_02 */ - __RT1052_PIN(46, GPIO1, 3), /* GPIO_AD_B0_03 */ - __RT1052_PIN(47, GPIO1, 4), /* GPIO_AD_B0_04 */ - __RT1052_PIN(48, GPIO1, 5), /* GPIO_AD_B0_05 */ - __RT1052_PIN(49, GPIO1, 6), /* GPIO_AD_B0_06 */ - __RT1052_PIN(50, GPIO1, 7), /* GPIO_AD_B0_07 */ - __RT1052_PIN(51, GPIO1, 8), /* GPIO_AD_B0_08 */ - __RT1052_PIN(52, GPIO1, 9), /* GPIO_AD_B0_09 */ - __RT1052_PIN(53, GPIO1, 10), /* GPIO_AD_B0_10 */ - __RT1052_PIN(54, GPIO1, 11), /* GPIO_AD_B0_11 */ - __RT1052_PIN(55, GPIO1, 12), /* GPIO_AD_B0_12 */ - __RT1052_PIN(56, GPIO1, 13), /* GPIO_AD_B0_13 */ - __RT1052_PIN(57, GPIO1, 14), /* GPIO_AD_B0_14 */ - __RT1052_PIN(58, GPIO1, 15), /* GPIO_AD_B0_15 */ - __RT1052_PIN(59, GPIO1, 16), /* GPIO_AD_B1_00 */ - __RT1052_PIN(60, GPIO1, 17), /* GPIO_AD_B1_01 */ - __RT1052_PIN(61, GPIO1, 18), /* GPIO_AD_B1_02 */ - __RT1052_PIN(62, GPIO1, 19), /* GPIO_AD_B1_03 */ - __RT1052_PIN(63, GPIO1, 20), /* GPIO_AD_B1_04 */ - __RT1052_PIN(64, GPIO1, 21), /* GPIO_AD_B1_05 */ - __RT1052_PIN(65, GPIO1, 22), /* GPIO_AD_B1_06 */ - __RT1052_PIN(66, GPIO1, 23), /* GPIO_AD_B1_07 */ - __RT1052_PIN(67, GPIO1, 24), /* GPIO_AD_B1_08 */ - __RT1052_PIN(68, GPIO1, 25), /* GPIO_AD_B1_09 */ - __RT1052_PIN(69, GPIO1, 26), /* GPIO_AD_B1_10 */ - __RT1052_PIN(70, GPIO1, 27), /* GPIO_AD_B1_11 */ - __RT1052_PIN(71, GPIO1, 28), /* GPIO_AD_B1_12 */ - __RT1052_PIN(72, GPIO1, 29), /* GPIO_AD_B1_13 */ - __RT1052_PIN(73, GPIO1, 30), /* GPIO_AD_B1_14 */ - __RT1052_PIN(74, GPIO1, 31), /* GPIO_AD_B1_15 */ - - /* GPIO2 */ - __RT1052_PIN( 75, GPIO2, 0), /* GPIO_B0_00 */ - __RT1052_PIN( 76, GPIO2, 1), /* GPIO_B0_01 */ - __RT1052_PIN( 77, GPIO2, 2), /* GPIO_B0_02 */ - __RT1052_PIN( 78, GPIO2, 3), /* GPIO_B0_03 */ - __RT1052_PIN( 79, GPIO2, 4), /* GPIO_B0_04 */ - __RT1052_PIN( 80, GPIO2, 5), /* GPIO_B0_05 */ - __RT1052_PIN( 81, GPIO2, 6), /* GPIO_B0_06 */ - __RT1052_PIN( 82, GPIO2, 7), /* GPIO_B0_07 */ - __RT1052_PIN( 83, GPIO2, 8), /* GPIO_B0_08 */ - __RT1052_PIN( 84, GPIO2, 9), /* GPIO_B0_09 */ - __RT1052_PIN( 85, GPIO2, 10), /* GPIO_B0_10 */ - __RT1052_PIN( 86, GPIO2, 11), /* GPIO_B0_11 */ - __RT1052_PIN( 87, GPIO2, 12), /* GPIO_B0_12 */ - __RT1052_PIN( 88, GPIO2, 13), /* GPIO_B0_13 */ - __RT1052_PIN( 89, GPIO2, 14), /* GPIO_B0_14 */ - __RT1052_PIN( 90, GPIO2, 15), /* GPIO_B0_15 */ - __RT1052_PIN( 91, GPIO2, 16), /* GPIO_B1_00 */ - __RT1052_PIN( 92, GPIO2, 17), /* GPIO_B1_01 */ - __RT1052_PIN( 93, GPIO2, 18), /* GPIO_B1_02 */ - __RT1052_PIN( 94, GPIO2, 19), /* GPIO_B1_03 */ - __RT1052_PIN( 95, GPIO2, 20), /* GPIO_B1_04 */ - __RT1052_PIN( 96, GPIO2, 21), /* GPIO_B1_05 */ - __RT1052_PIN( 97, GPIO2, 22), /* GPIO_B1_06 */ - __RT1052_PIN( 98, GPIO2, 23), /* GPIO_B1_07 */ - __RT1052_PIN( 99, GPIO2, 24), /* GPIO_B1_08 */ - __RT1052_PIN(100, GPIO2, 25), /* GPIO_B1_09 */ - __RT1052_PIN(101, GPIO2, 26), /* GPIO_B1_10 */ - __RT1052_PIN(102, GPIO2, 27), /* GPIO_B1_11 */ - __RT1052_PIN(103, GPIO2, 28), /* GPIO_B1_12 */ - __RT1052_PIN(104, GPIO2, 29), /* GPIO_B1_13 */ - __RT1052_PIN(105, GPIO2, 30), /* GPIO_B1_14 */ - __RT1052_PIN(106, GPIO2, 31), /* GPIO_B1_15 */ - - /* GPIO3 */ - __RT1052_PIN(107, GPIO3, 0), /* GPIO_SD_B1_00 */ - __RT1052_PIN(108, GPIO3, 1), /* GPIO_SD_B1_01 */ - __RT1052_PIN(109, GPIO3, 2), /* GPIO_SD_B1_02 */ - __RT1052_PIN(110, GPIO3, 3), /* GPIO_SD_B1_03 */ - __RT1052_PIN(111, GPIO3, 4), /* GPIO_SD_B1_04 */ - __RT1052_PIN(112, GPIO3, 5), /* GPIO_SD_B1_05 */ - __RT1052_PIN(113, GPIO3, 6), /* GPIO_SD_B1_06 */ - __RT1052_PIN(114, GPIO3, 7), /* GPIO_SD_B1_07 */ - __RT1052_PIN(115, GPIO3, 8), /* GPIO_SD_B1_08 */ - __RT1052_PIN(116, GPIO3, 9), /* GPIO_SD_B1_09 */ - __RT1052_PIN(117, GPIO3, 10), /* GPIO_SD_B1_10 */ - __RT1052_PIN(118, GPIO3, 11), /* GPIO_SD_B1_11 */ - __RT1052_PIN(119, GPIO3, 12), /* GPIO_SD_B0_00 */ - __RT1052_PIN(120, GPIO3, 13), /* GPIO_SD_B0_01 */ - __RT1052_PIN(121, GPIO3, 14), /* GPIO_SD_B0_02 */ - __RT1052_PIN(122, GPIO3, 15), /* GPIO_SD_B0_03 */ - __RT1052_PIN(123, GPIO3, 16), /* GPIO_SD_B0_04 */ - __RT1052_PIN(124, GPIO3, 17), /* GPIO_SD_B0_05 */ - - /* GPIO5 */ - __RT1052_PIN(125, GPIO5, 0), /* WAKEUP */ - __RT1052_PIN(126, GPIO5, 1), /* PMIC_ON_REQ */ - __RT1052_PIN(127, GPIO5, 2) /* PMIC_STBY_REQ */ -}; - -static struct rt1052_irq rt1052_irq_map[] = -{ - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }, - {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} } -}; - -void gpio_isr(GPIO_Type* base, rt_uint32_t gpio_pin) -{ - if((GPIO_PortGetInterruptFlags(base) & (1 << gpio_pin)) != 0) - { - GPIO_PortClearInterruptFlags(base, gpio_pin); - - if(rt1052_irq_map[gpio_pin].irq_info.hdr != RT_NULL) - { - rt1052_irq_map[gpio_pin].irq_info.hdr(rt1052_irq_map[gpio_pin].irq_info.args); - } - } -} - -void GPIO1_Combined_0_15_IRQHandler(void) -{ - rt_uint8_t gpio_pin; - - rt_interrupt_enter(); - - for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++) - { - gpio_isr(GPIO1, gpio_pin); - } - - rt_interrupt_leave(); -} - -void GPIO1_Combined_16_31_IRQHandler(void) -{ - rt_uint8_t gpio_pin; - - rt_interrupt_enter(); - - for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++) - { - gpio_isr(GPIO1, gpio_pin); - } - - rt_interrupt_leave(); -} - -void GPIO2_Combined_0_15_IRQHandler(void) -{ - rt_uint8_t gpio_pin; - - rt_interrupt_enter(); - - for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++) - { - gpio_isr(GPIO2, gpio_pin); - } - - rt_interrupt_leave(); -} - -void GPIO2_Combined_16_31_IRQHandler(void) -{ - rt_uint8_t gpio_pin; - - rt_interrupt_enter(); - - for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++) - { - gpio_isr(GPIO2, gpio_pin); - } - - rt_interrupt_leave(); -} - -void GPIO3_Combined_0_15_IRQHandler(void) -{ - rt_uint8_t gpio_pin; - - rt_interrupt_enter(); - - for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++) - { - gpio_isr(GPIO3, gpio_pin); - } - - rt_interrupt_leave(); -} - -void GPIO3_Combined_16_31_IRQHandler(void) -{ - rt_uint8_t gpio_pin; - - rt_interrupt_enter(); - - for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++) - { - gpio_isr(GPIO3, gpio_pin); - } - - rt_interrupt_leave(); -} - -void GPIO4_Combined_0_15_IRQHandler(void) -{ - rt_uint8_t gpio_pin; - - rt_interrupt_enter(); - - for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++) - { - gpio_isr(GPIO4, gpio_pin); - } - - rt_interrupt_leave(); -} -void GPIO4_Combined_16_31_IRQHandler(void) -{ - rt_uint8_t gpio_pin; - - rt_interrupt_enter(); - - for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++) - { - gpio_isr(GPIO4, gpio_pin); - } - - rt_interrupt_leave(); -} - -void GPIO5_Combined_0_15_IRQHandler(void) -{ - rt_uint8_t gpio_pin; - - rt_interrupt_enter(); - - for(gpio_pin = 0; gpio_pin <= 2; gpio_pin++) - { - gpio_isr(GPIO5, gpio_pin); - } - - rt_interrupt_leave(); -} - -static IRQn_Type rt1052_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin) -{ - IRQn_Type irq_num = -100; /* Invalid interrupt number */ - - if(gpio == GPIO1) - { - if(gpio_pin <= 15) - { - irq_num = GPIO1_Combined_0_15_IRQn; - } - else - { - irq_num = GPIO1_Combined_16_31_IRQn; - } - } - else if(gpio == GPIO2) - { - if(gpio_pin <= 15) - { - irq_num = GPIO2_Combined_0_15_IRQn; - } - else - { - irq_num = GPIO2_Combined_16_31_IRQn; - } - } - else if(gpio == GPIO3) - { - if(gpio_pin <= 15) - { - irq_num = GPIO3_Combined_0_15_IRQn; - } - else - { - irq_num = GPIO3_Combined_16_31_IRQn; - } - } - else if(gpio == GPIO4) - { - if(gpio_pin <= 15) - { - irq_num = GPIO4_Combined_0_15_IRQn; - } - else - { - irq_num = GPIO4_Combined_16_31_IRQn; - } - } - else if(gpio == GPIO5) - { - if(gpio_pin <= 15) - { - irq_num = GPIO5_Combined_0_15_IRQn; - } - else - { - irq_num = GPIO5_Combined_16_31_IRQn; - } - } - - return irq_num; -} - -static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) -{ - gpio_pin_config_t gpio; - rt_uint32_t config_value = 0; - - if((pin > __ARRAY_LEN(rt1052_pin_map)) || (pin == 0)) - { - return; - } - - if(rt1052_pin_map[pin].gpio != GPIO5) - { - CLOCK_EnableClock(kCLOCK_Iomuxc); - IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 1); - } - else - { - CLOCK_EnableClock(kCLOCK_IomuxcSnvs); - IOMUXC_SetPinMux(0x400A8000U + (pin-125)*4, 0x5U, 0, 0, 0, 1); - } - - gpio.outputLogic = 0; - gpio.interruptMode = kGPIO_NoIntmode; - - switch(mode) - { - case PIN_MODE_OUTPUT: - { - config_value = 0x1030U; - gpio.direction = kGPIO_DigitalOutput; - } - break; - - case PIN_MODE_INPUT: - { - config_value = 0x1030U; - gpio.direction = kGPIO_DigitalInput; - } - break; - - case PIN_MODE_INPUT_PULLDOWN: - { - config_value = 0x1030U; - gpio.direction = kGPIO_DigitalInput; - } - break; - - case PIN_MODE_INPUT_PULLUP: - { - config_value = 0x5030U; - gpio.direction = kGPIO_DigitalInput; - } - break; - - case PIN_MODE_OUTPUT_OD: - { - config_value = 0x1830U; - gpio.direction = kGPIO_DigitalOutput; - } - break; - } - - if(rt1052_pin_map[pin].gpio != GPIO5) - { - IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value); - } - else - { - IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin-125)*4, config_value); - } - - GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio); -} - -static int rt1052_pin_read(rt_device_t dev, rt_base_t pin) -{ - return GPIO_PinReadPadStatus(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); -} - -static void rt1052_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) -{ - GPIO_PinWrite(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, value); -} - -static rt_err_t rt1052_pin_attach_irq(struct rt_device *device, rt_int32_t pin, - rt_uint32_t mode, void (*hdr)(void *args), void *args) -{ - struct rt1052_pin* pin_map = RT_NULL; - struct rt1052_irq* irq_map = RT_NULL; - - pin_map = &rt1052_pin_map[pin]; - irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; - - if(pin_map == RT_NULL || irq_map == RT_NULL) - { - return RT_ENOSYS; - } - - if(irq_map->enable == PIN_IRQ_ENABLE) - { - return RT_EBUSY; - } - - irq_map->irq_info.pin = pin; - irq_map->irq_info.hdr = hdr; - irq_map->irq_info.mode = mode; - irq_map->irq_info.args = args; - - return RT_EOK; -} - -static rt_err_t rt1052_pin_detach_irq(struct rt_device *device, rt_int32_t pin) -{ - struct rt1052_pin* pin_map = RT_NULL; - struct rt1052_irq* irq_map = RT_NULL; - - pin_map = &rt1052_pin_map[pin]; - irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; - - if(pin_map == RT_NULL || irq_map == RT_NULL) - { - return RT_ENOSYS; - } - - if(irq_map->enable == PIN_IRQ_DISABLE) - { - return RT_EOK; - } - - irq_map->irq_info.pin = PIN_IRQ_PIN_NONE; - irq_map->irq_info.hdr = RT_NULL; - irq_map->irq_info.mode = PIN_IRQ_MODE_RISING; - irq_map->irq_info.args = RT_NULL; - - return RT_EOK; -} - -static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) -{ - gpio_pin_config_t gpio; - IRQn_Type irq_num; - rt_uint32_t config_value = 0x1b0a0; - - struct rt1052_pin* pin_map = RT_NULL; - struct rt1052_irq* irq_map = RT_NULL; - - pin_map = &rt1052_pin_map[pin]; - irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; - - if(pin_map == RT_NULL || irq_map == RT_NULL) - { - return RT_ENOSYS; - } - - if(enabled == PIN_IRQ_ENABLE) - { - if(irq_map->enable == PIN_IRQ_ENABLE) - { - return RT_EBUSY; - } - - if(irq_map->irq_info.pin != pin) - { - return RT_EIO; - } - - irq_map->enable = PIN_IRQ_ENABLE; - - if(rt1052_pin_map[pin].gpio != GPIO5) - { - CLOCK_EnableClock(kCLOCK_Iomuxc); - IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 0); - } - else - { - CLOCK_EnableClock(kCLOCK_IomuxcSnvs); - IOMUXC_SetPinMux(0x400A8000U + (pin-125)*4, 0x5U, 0, 0, 0, 0); - } - - gpio.direction = kGPIO_DigitalInput; - gpio.outputLogic = 0; - - switch(irq_map->irq_info.mode) - { - case PIN_IRQ_MODE_RISING: - { - gpio.interruptMode = kGPIO_IntRisingEdge; - } - break; - - case PIN_IRQ_MODE_FALLING: - { - gpio.interruptMode = kGPIO_IntFallingEdge; - } - break; - - case PIN_IRQ_MODE_RISING_FALLING: - { - gpio.interruptMode = kGPIO_IntRisingOrFallingEdge; - } - break; - - case PIN_IRQ_MODE_HIGH_LEVEL: - { - gpio.interruptMode = kGPIO_IntHighLevel; - } - break; - - case PIN_IRQ_MODE_LOW_LEVEL: - { - gpio.interruptMode = kGPIO_IntLowLevel; - } - break; - } - - if(rt1052_pin_map[pin].gpio != GPIO5) - { - IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value); - } - else - { - IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin-125)*4, config_value); - } - - irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); - - NVIC_SetPriority(irq_num, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0)); - EnableIRQ(irq_num); - - GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio); - GPIO_PortEnableInterrupts(rt1052_pin_map[pin].gpio, 1U << rt1052_pin_map[pin].gpio_pin); - } - else if(enabled == PIN_IRQ_DISABLE) - { - if(irq_map->enable == PIN_IRQ_DISABLE) - { - return RT_EOK; - } - - irq_map->enable = PIN_IRQ_DISABLE; - irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); - - NVIC_DisableIRQ(irq_num); - } - else - { - return RT_EINVAL; - } - - return RT_EOK; -} - -int rt_hw_pin_init(void) -{ - int ret = RT_EOK; - - rt1052_pin_ops.pin_mode = rt1052_pin_mode; - rt1052_pin_ops.pin_read = rt1052_pin_read; - rt1052_pin_ops.pin_write = rt1052_pin_write; - rt1052_pin_ops.pin_attach_irq = rt1052_pin_attach_irq; - rt1052_pin_ops.pin_detach_irq = rt1052_pin_detach_irq; - rt1052_pin_ops.pin_irq_enable = rt1052_pin_irq_enable; - - ret = rt_device_pin_register("pin", &rt1052_pin_ops, RT_NULL); - - return ret; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - -#endif /*RT_USING_PIN */ diff --git a/bsp/imxrt1052-evk/drivers/drv_pin.h b/bsp/imxrt1052-evk/drivers/drv_pin.h deleted file mode 100644 index 6c0574ec0f..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_pin.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * File : drv_pin.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2018-03-13 Liuguang the first version. - * 2018-03-19 Liuguang add GPIO interrupt mode support. - */ - -#ifndef __DRV_PIN_H__ -#define __DRV_PIN_H__ - -#include -#include - -int rt_hw_pin_init(void); - -#endif diff --git a/bsp/imxrt1052-evk/drivers/drv_rtc.c b/bsp/imxrt1052-evk/drivers/drv_rtc.c deleted file mode 100644 index 0c1dea21eb..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_rtc.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * File : drv_rtc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2018-03-15 Liuguang the first version. - */ -#include "drv_rtc.h" - -#include "fsl_common.h" -#include "fsl_snvs_hp.h" -#include "fsl_snvs_lp.h" -#include - -#ifdef RT_USING_RTC - -#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL - #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" -#endif - -static time_t get_timestamp(void) -{ - struct tm tm_new = {0}; - snvs_hp_rtc_datetime_t rtcDate; - - SNVS_HP_RTC_GetDatetime(SNVS, &rtcDate); - - tm_new.tm_sec = rtcDate.second; - tm_new.tm_min = rtcDate.minute; - tm_new.tm_hour = rtcDate.hour; - - tm_new.tm_mday = rtcDate.day; - tm_new.tm_mon = rtcDate.month - 1; - tm_new.tm_year = rtcDate.year - 1900; - - return mktime(&tm_new); -} - -static int set_timestamp(time_t timestamp) -{ - struct tm *p_tm; - snvs_hp_rtc_datetime_t rtcDate; - - p_tm = localtime(×tamp); - - rtcDate.second = p_tm->tm_sec ; - rtcDate.minute = p_tm->tm_min ; - rtcDate.hour = p_tm->tm_hour; - - rtcDate.day = p_tm->tm_mday; - rtcDate.month = p_tm->tm_mon + 1; - rtcDate.year = p_tm->tm_year + 1900; - - SNVS_HP_RTC_SetDatetime(SNVS, &rtcDate); - - return RT_EOK; -} - -static rt_err_t rt1052_hp_rtc_init(rt_device_t dev) -{ - snvs_hp_rtc_config_t snvsRtcConfig; - - SNVS_HP_RTC_GetDefaultConfig(&snvsRtcConfig); - SNVS_HP_RTC_Init(SNVS, &snvsRtcConfig); - - SNVS_HP_RTC_StartTimer(SNVS); - - return RT_EOK; -} - -static rt_err_t rt1052_hp_rtc_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -static rt_err_t rt1052_hp_rtc_close(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_size_t rt1052_hp_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - return 0; -} - -static rt_size_t rt1052_hp_rtc_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - return 0; -} - -static rt_err_t rt1052_hp_rtc_control(rt_device_t dev, int cmd, void *args) -{ - RT_ASSERT(dev != RT_NULL); - - switch(cmd) - { - case RT_DEVICE_CTRL_RTC_GET_TIME: - { - *(uint32_t *)args = get_timestamp(); - } - break; - - case RT_DEVICE_CTRL_RTC_SET_TIME: - { - set_timestamp(*(time_t *)args); - } - break; - - default: - return RT_EINVAL; - } - - return RT_EOK; -} - -static struct rt_device device = -{ - .type = RT_Device_Class_RTC, - .init = rt1052_hp_rtc_init, - .open = rt1052_hp_rtc_open, - .close = rt1052_hp_rtc_close, - .read = rt1052_hp_rtc_read, - .write = rt1052_hp_rtc_write, - .control = rt1052_hp_rtc_control, -}; - -int rt_hw_hp_rtc_init(void) -{ - rt_err_t ret = RT_EOK; - - ret = rt_device_register(&device, "rtc", RT_DEVICE_FLAG_RDWR); - if(ret != RT_EOK) - { - return ret; - } - - rt_device_open(&device, RT_DEVICE_OFLAG_RDWR); - - return RT_EOK; -} -INIT_DEVICE_EXPORT(rt_hw_hp_rtc_init); - -#endif /*RT_USING_RTC */ diff --git a/bsp/imxrt1052-evk/drivers/drv_rtc.h b/bsp/imxrt1052-evk/drivers/drv_rtc.h deleted file mode 100644 index e7cf53902c..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_rtc.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * File : drv_rtc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2018-03-15 Liuguang the first version. - */ - -#ifndef __DRV_RTC_H__ -#define __DRV_RTC_H__ - -#include -#include - -int rt_hw_hp_rtc_init(void); - -#endif diff --git a/bsp/imxrt1052-evk/drivers/drv_sdio.c b/bsp/imxrt1052-evk/drivers/drv_sdio.c deleted file mode 100644 index 732077df7c..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_sdio.c +++ /dev/null @@ -1,564 +0,0 @@ -/* - * File : syscall_write.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2017-10-10 Tanek first version - */ - -#include -#include -#include - -#include -#include -#include - -#include - -#define RT_USING_SDIO1 -#define RT_USING_SDIO2 - -//#define DEBUG - -#ifdef DEBUG -static int enable_log = 1; - -#define MMCSD_DGB(fmt, ...) \ - do \ - { \ - if (enable_log) \ - { \ - rt_kprintf(fmt, ##__VA_ARGS__); \ - } \ - } while (0) -#else -#define MMCSD_DGB(fmt, ...) -#endif - -#define CACHE_LINESIZE (32) - -#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */ -#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ -#define IMXRT_MAX_FREQ (25UL * 1000UL * 1000UL) - -#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */ -#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ -#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */ -#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */ -#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */ - -/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ -#define USDHC_READ_WATERMARK_LEVEL (0x80U) -#define USDHC_WRITE_WATERMARK_LEVEL (0x80U) - -/* DMA mode */ -#define USDHC_DMA_MODE kUSDHC_DmaModeAdma2 - -/* Endian mode. */ -#define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle - -ALIGN(USDHC_ADMA2_ADDR_ALIGN) uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS] SECTION("NonCacheable"); - -struct imxrt_mmcsd -{ - struct rt_mmcsd_host *host; - struct rt_mmcsd_req *req; - struct rt_mmcsd_cmd *cmd; - - struct rt_timer timer; - - rt_uint32_t *buf; - - //USDHC_Type *base; - usdhc_host_t usdhc_host; - clock_div_t usdhc_div; - clock_ip_name_t ip_clock; - - uint32_t *usdhc_adma2_table; -}; - -static void _mmcsd_gpio_init(struct imxrt_mmcsd *mmcsd) -{ - gpio_pin_config_t sw_config; - - CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ - -#ifdef RT_USING_SDIO1 - if (mmcsd->usdhc_host.base == USDHC1) - { - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0); - - /* voltage select PIN */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0); - - /* card detect PIN */ - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_12_GPIO2_IO28, 0); - /* power reset pin */ - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0); - - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | - IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | - IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | - IOMUXC_SW_PAD_CTL_PAD_DSE(1)); - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | - IOMUXC_SW_PAD_CTL_PAD_SPEED(1) | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | - IOMUXC_SW_PAD_CTL_PAD_DSE(1)); - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | - IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | - IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | - IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | - IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1)); - - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | - IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | - IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | - IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | - IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1)); - - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | - IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | - IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | - IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | - IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1)); - - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | - IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | - IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | - IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | - IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1)); - - /*voltage select pin*/ - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | - IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | - IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | - IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | - IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(4)); - - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_12_GPIO2_IO28, IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | - IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | - IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | - IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | - IOMUXC_SW_PAD_CTL_PAD_PUS(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1)); - - sw_config.direction = kGPIO_DigitalOutput; - sw_config.outputLogic = 0; - sw_config.interruptMode = kGPIO_NoIntmode; - - GPIO_PinInit(GPIO1, 5U, &sw_config); - GPIO_PinWrite(GPIO1, 5U, true); - } - else -#endif - -#ifdef RT_USING_SDIO2 - if (mmcsd->usdhc_host.base == USDHC2) - { - // todo - } -#endif - -} - -static void SDMMCHOST_ErrorRecovery(USDHC_Type *base) -{ - uint32_t status = 0U; - /* get host present status */ - status = USDHC_GetPresentStatusFlags(base); - /* check command inhibit status flag */ - if ((status & kUSDHC_CommandInhibitFlag) != 0U) - { - /* reset command line */ - USDHC_Reset(base, kUSDHC_ResetCommand, 1000U); - } - /* check data inhibit status flag */ - if ((status & kUSDHC_DataInhibitFlag) != 0U) - { - /* reset data line */ - USDHC_Reset(base, kUSDHC_ResetData, 1000U); - } -} - -static void _mmcsd_host_init(struct imxrt_mmcsd *mmcsd) -{ - usdhc_host_t *usdhc_host = &mmcsd->usdhc_host; - - /* Initializes SDHC. */ - usdhc_host->config.dataTimeout = USDHC_DATA_TIMEOUT; - usdhc_host->config.endianMode = USDHC_ENDIAN_MODE; - usdhc_host->config.readWatermarkLevel = USDHC_READ_WATERMARK_LEVEL; - usdhc_host->config.writeWatermarkLevel = USDHC_WRITE_WATERMARK_LEVEL; - usdhc_host->config.readBurstLen = USDHC_READ_BURST_LEN; - usdhc_host->config.writeBurstLen = USDHC_WRITE_BURST_LEN; - - USDHC_Init(usdhc_host->base, &(usdhc_host->config)); -} - -static void _mmcsd_clk_init(struct imxrt_mmcsd *mmcsd) -{ - CLOCK_EnableClock(mmcsd->ip_clock); - CLOCK_SetDiv(mmcsd->usdhc_div, 5U); -} - -static void _mmcsd_isr_init(struct imxrt_mmcsd *mmcsd) -{ - //NVIC_SetPriority(USDHC1_IRQn, 5U); -} - -static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) -{ - struct imxrt_mmcsd *mmcsd; - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; - status_t error; - usdhc_adma_config_t dmaConfig; - usdhc_transfer_t fsl_content = {0}; - usdhc_command_t fsl_command = {0}; - usdhc_data_t fsl_data = {0}; - rt_uint32_t *buf = NULL; - - RT_ASSERT(host != RT_NULL); - RT_ASSERT(req != RT_NULL); - - mmcsd = (struct imxrt_mmcsd *)host->private_data; - RT_ASSERT(mmcsd != RT_NULL); - - cmd = req->cmd; - RT_ASSERT(cmd != RT_NULL); - - MMCSD_DGB("\tcmd->cmd_code: %02d, cmd->arg: %08x, cmd->flags: %08x --> ", cmd->cmd_code, cmd->arg, cmd->flags); - - data = cmd->data; - - memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t)); - /* config adma */ - dmaConfig.dmaMode = USDHC_DMA_MODE; - dmaConfig.burstLen = kUSDHC_EnBurstLenForINCR; - dmaConfig.admaTable = mmcsd->usdhc_adma2_table; - dmaConfig.admaTableWords = USDHC_ADMA_TABLE_WORDS; - - fsl_command.index = cmd->cmd_code; - fsl_command.argument = cmd->arg; - - if (cmd->cmd_code == STOP_TRANSMISSION) - fsl_command.type = kCARD_CommandTypeAbort; - else - fsl_command.type = kCARD_CommandTypeNormal; - - switch (cmd->flags & RESP_MASK) - { - case RESP_NONE: - fsl_command.responseType = kCARD_ResponseTypeNone; - break; - case RESP_R1: - fsl_command.responseType = kCARD_ResponseTypeR1; - break; - case RESP_R1B: - fsl_command.responseType = kCARD_ResponseTypeR1b; - break; - case RESP_R2: - fsl_command.responseType = kCARD_ResponseTypeR2; - break; - case RESP_R3: - fsl_command.responseType = kCARD_ResponseTypeR3; - break; - case RESP_R4: - fsl_command.responseType = kCARD_ResponseTypeR4; - break; - case RESP_R6: - fsl_command.responseType = kCARD_ResponseTypeR6; - break; - case RESP_R7: - fsl_command.responseType = kCARD_ResponseTypeR7; - break; - case RESP_R5: - fsl_command.responseType = kCARD_ResponseTypeR5; - break; - /* - case RESP_R5B: - fsl_command.responseType = kCARD_ResponseTypeR5b; - break; - */ - default: - RT_ASSERT(NULL); - } - - // command type - /* - switch (cmd->flags & CMD_MASK) - { - case CMD_AC: - break; - case CMD_ADTC: - break; - case CMD_BC: - break; - case CMD_BCR: - break; - } - */ - - fsl_command.flags = 0; - //fsl_command.response - //fsl_command.responseErrorFlags - - fsl_content.command = &fsl_command; - - if (data) - { - if (req->stop != NULL) - fsl_data.enableAutoCommand12 = true; - else - fsl_data.enableAutoCommand12 = false; - - fsl_data.enableAutoCommand23 = false; - - fsl_data.enableIgnoreError = false; - fsl_data.dataType = kUSDHC_TransferDataNormal; //todo : update data type - fsl_data.blockSize = data->blksize; - fsl_data.blockCount = data->blks; - - MMCSD_DGB(" blksize:%d, blks:%d ", fsl_data.blockSize, fsl_data.blockCount); - - if (((rt_uint32_t)data->buf & (CACHE_LINESIZE - 1)) || // align cache(32byte) - ((rt_uint32_t)data->buf > 0x00000000 && (rt_uint32_t)data->buf < 0x00080000) /*|| // ITCM - ((rt_uint32_t)data->buf >= 0x20000000 && (rt_uint32_t)data->buf < 0x20080000)*/) // DTCM - { - - buf = rt_malloc_align(fsl_data.blockSize * fsl_data.blockCount, CACHE_LINESIZE); - RT_ASSERT(buf != RT_NULL); - - MMCSD_DGB(" malloc buf: %p, data->buf:%p, %d ", buf, data->buf, fsl_data.blockSize * fsl_data.blockCount); - } - - - if ((cmd->cmd_code == WRITE_BLOCK) || (cmd->cmd_code == WRITE_MULTIPLE_BLOCK)) - { - if (buf) - { - MMCSD_DGB(" write(data->buf to buf) "); - rt_memcpy(buf, data->buf, fsl_data.blockSize * fsl_data.blockCount); - fsl_data.txData = (uint32_t const *)buf; - } - else - { - fsl_data.txData = (uint32_t const *)data->buf; - } - - fsl_data.rxData = NULL; - } - else - { - if (buf) - { - fsl_data.rxData = (uint32_t *)buf; - } - else - { - fsl_data.rxData = (uint32_t *)data->buf; - } - - fsl_data.txData = NULL; - } - - fsl_content.data = &fsl_data; - } - else - { - fsl_content.data = NULL; - } - - error = USDHC_TransferBlocking(mmcsd->usdhc_host.base, &dmaConfig, &fsl_content); - if (error == kStatus_Fail) - { - SDMMCHOST_ErrorRecovery(mmcsd->usdhc_host.base); - MMCSD_DGB(" ***USDHC_TransferBlocking error: %d*** --> \n", error); - cmd->err = -RT_ERROR; - } - - if (buf) - { - if (fsl_data.rxData) - { - MMCSD_DGB("read copy buf to data->buf "); - rt_memcpy(data->buf, buf, fsl_data.blockSize * fsl_data.blockCount); - } - - rt_free_align(buf); - } - - if ((cmd->flags & RESP_MASK) == RESP_R2) - { - cmd->resp[3] = fsl_command.response[0]; - cmd->resp[2] = fsl_command.response[1]; - cmd->resp[1] = fsl_command.response[2]; - cmd->resp[0] = fsl_command.response[3]; - MMCSD_DGB(" resp 0x%08X 0x%08X 0x%08X 0x%08X\n", - cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); - } - else - { - cmd->resp[0] = fsl_command.response[0]; - MMCSD_DGB(" resp 0x%08X\n", cmd->resp[0]); - } - - mmcsd_req_complete(host); - - return; -} - -static void _mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) -{ - - struct imxrt_mmcsd *mmcsd; - unsigned int usdhc_clk; - unsigned int bus_width; - uint32_t src_clk; - - RT_ASSERT(host != RT_NULL); - RT_ASSERT(host->private_data != RT_NULL); - RT_ASSERT(io_cfg != RT_NULL); - - mmcsd = (struct imxrt_mmcsd *)host->private_data; - usdhc_clk = io_cfg->clock; - bus_width = io_cfg->bus_width; - - if (usdhc_clk > IMXRT_MAX_FREQ) - usdhc_clk = IMXRT_MAX_FREQ; - src_clk = (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(mmcsd->usdhc_div) + 1U)); - - MMCSD_DGB("\tsrc_clk: %d, usdhc_clk: %d, bus_width: %d\n", src_clk, usdhc_clk, bus_width); - - if (usdhc_clk) - { - USDHC_SetSdClock(mmcsd->usdhc_host.base, src_clk, usdhc_clk); - //CLOCK_EnableClock(mmcsd->ip_clock); - - /* Change bus width */ - if (bus_width == MMCSD_BUS_WIDTH_8) - USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth8Bit); - else if (bus_width == MMCSD_BUS_WIDTH_4) - USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth4Bit); - else if (bus_width == MMCSD_BUS_WIDTH_1) - USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth1Bit); - else - RT_ASSERT(RT_NULL); - } - else - { - //CLOCK_DisableClock(mmcsd->ip_clock); - } - -} - -#ifdef DEBUG -static void log_toggle(int en) -{ - enable_log = en; -} -FINSH_FUNCTION_EXPORT(log_toggle, toglle log dumple); -#endif - -//static rt_int32_t _mmc_get_card_status(struct rt_mmcsd_host *host) -//{ -// MMCSD_DGB("%s, start\n", __func__); -// MMCSD_DGB("%s, end\n", __func__); -// -// return 0; -//} -// -//static void _mmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable) -//{ -// -//} - -static const struct rt_mmcsd_host_ops ops = -{ - _mmc_request, - _mmc_set_iocfg, - RT_NULL,//_mmc_get_card_status, - RT_NULL,//_mmc_enable_sdio_irq, -}; - -rt_int32_t _imxrt_mci_init(void) -{ - struct rt_mmcsd_host *host; - struct imxrt_mmcsd *mmcsd; - - host = mmcsd_alloc_host(); - if (!host) - { - return -RT_ERROR; - } - - mmcsd = rt_malloc(sizeof(struct imxrt_mmcsd)); - if (!mmcsd) - { - rt_kprintf("alloc mci failed\n"); - goto err; - } - - rt_memset(mmcsd, 0, sizeof(struct imxrt_mmcsd)); - mmcsd->usdhc_host.base = USDHC1; - mmcsd->usdhc_div = kCLOCK_Usdhc1Div; - mmcsd->usdhc_adma2_table = g_usdhcAdma2Table; - - host->ops = &ops; - host->freq_min = 375000; - host->freq_max = 25000000; - host->valid_ocr = VDD_32_33 | VDD_33_34; - host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ - MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; - host->max_seg_size = 65535; - host->max_dma_segs = 2; - host->max_blk_size = 512; - host->max_blk_count = 4096; - - mmcsd->host = host; - - _mmcsd_clk_init(mmcsd); - _mmcsd_isr_init(mmcsd); - _mmcsd_gpio_init(mmcsd); - _mmcsd_host_init(mmcsd); - - host->private_data = mmcsd; - - mmcsd_change(host); - - return 0; - -err: - mmcsd_free_host(host); - - return -RT_ENOMEM; -} - -int imxrt_mci_init(void) -{ - /* initilize sd card */ - _imxrt_mci_init(); - - return 0; -} -INIT_DEVICE_EXPORT(imxrt_mci_init); diff --git a/bsp/imxrt1052-evk/drivers/drv_sdram.c b/bsp/imxrt1052-evk/drivers/drv_sdram.c deleted file mode 100644 index 2560caab5e..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_sdram.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2017-12-04 Tanek first implementation - */ -#include -#include -#include - -static uint32_t _RDWORD(uint32_t address) -{ - return *((uint32_t *)address); -} - -static void _WDWORD(uint32_t address, uint32_t value) -{ - *((uint32_t *)address) = value; -} - -static void SDRAM_WaitIpCmdDone(void) -{ - unsigned long reg; - do - { - reg = _RDWORD(0x402F003C); - }while((reg & 0x3) == 0); -} - -static void _clock_init(void) -{ - // Enable all clocks - _WDWORD(0x400FC068,0xffffffff); - _WDWORD(0x400FC06C,0xffffffff); - _WDWORD(0x400FC070,0xffffffff); - _WDWORD(0x400FC074,0xffffffff); - _WDWORD(0x400FC078,0xffffffff); - _WDWORD(0x400FC07C,0xffffffff); - _WDWORD(0x400FC080,0xffffffff); - - _WDWORD(0x400D8030,0x00002001); - _WDWORD(0x400D8100,0x001d0000); - _WDWORD(0x400FC014,0x00010D40); -} - -static void _sdr_Init(void) -{ - // Config IOMUX - _WDWORD(0x401F8014, 0x00000000); - _WDWORD(0x401F8018, 0x00000000); - _WDWORD(0x401F801C, 0x00000000); - _WDWORD(0x401F8020, 0x00000000); - _WDWORD(0x401F8024, 0x00000000); - _WDWORD(0x401F8028, 0x00000000); - _WDWORD(0x401F802C, 0x00000000); - _WDWORD(0x401F8030, 0x00000000); - _WDWORD(0x401F8034, 0x00000000); - _WDWORD(0x401F8038, 0x00000000); - _WDWORD(0x401F803C, 0x00000000); - _WDWORD(0x401F8040, 0x00000000); - _WDWORD(0x401F8044, 0x00000000); - _WDWORD(0x401F8048, 0x00000000); - _WDWORD(0x401F804C, 0x00000000); - _WDWORD(0x401F8050, 0x00000000); - _WDWORD(0x401F8054, 0x00000000); - _WDWORD(0x401F8058, 0x00000000); - _WDWORD(0x401F805C, 0x00000000); - _WDWORD(0x401F8060, 0x00000000); - _WDWORD(0x401F8064, 0x00000000); - _WDWORD(0x401F8068, 0x00000000); - _WDWORD(0x401F806C, 0x00000000); - _WDWORD(0x401F8070, 0x00000000); - _WDWORD(0x401F8074, 0x00000000); - _WDWORD(0x401F8078, 0x00000000); - _WDWORD(0x401F807C, 0x00000000); - _WDWORD(0x401F8080, 0x00000000); - _WDWORD(0x401F8084, 0x00000000); - _WDWORD(0x401F8088, 0x00000000); - _WDWORD(0x401F808C, 0x00000000); - _WDWORD(0x401F8090, 0x00000000); - _WDWORD(0x401F8094, 0x00000000); - _WDWORD(0x401F8098, 0x00000000); - _WDWORD(0x401F809C, 0x00000000); - _WDWORD(0x401F80A0, 0x00000000); - _WDWORD(0x401F80A4, 0x00000000); - _WDWORD(0x401F80A8, 0x00000000); - _WDWORD(0x401F80AC, 0x00000000); - _WDWORD(0x401F80B0, 0x00000010); // EMC_39, DQS PIN, enable SION - _WDWORD(0x401F80B4, 0x00000000); - _WDWORD(0x401F80B8, 0x00000000); - - // PAD ctrl - // drive strength = 0x7 to increase drive strength - // otherwise the data7 bit may fail. - _WDWORD(0x401F8204, 0x000110F9); - _WDWORD(0x401F8208, 0x000110F9); - _WDWORD(0x401F820C, 0x000110F9); - _WDWORD(0x401F8210, 0x000110F9); - _WDWORD(0x401F8214, 0x000110F9); - _WDWORD(0x401F8218, 0x000110F9); - _WDWORD(0x401F821C, 0x000110F9); - _WDWORD(0x401F8220, 0x000110F9); - _WDWORD(0x401F8224, 0x000110F9); - _WDWORD(0x401F8228, 0x000110F9); - _WDWORD(0x401F822C, 0x000110F9); - _WDWORD(0x401F8230, 0x000110F9); - _WDWORD(0x401F8234, 0x000110F9); - _WDWORD(0x401F8238, 0x000110F9); - _WDWORD(0x401F823C, 0x000110F9); - _WDWORD(0x401F8240, 0x000110F9); - _WDWORD(0x401F8244, 0x000110F9); - _WDWORD(0x401F8248, 0x000110F9); - _WDWORD(0x401F824C, 0x000110F9); - _WDWORD(0x401F8250, 0x000110F9); - _WDWORD(0x401F8254, 0x000110F9); - _WDWORD(0x401F8258, 0x000110F9); - _WDWORD(0x401F825C, 0x000110F9); - _WDWORD(0x401F8260, 0x000110F9); - _WDWORD(0x401F8264, 0x000110F9); - _WDWORD(0x401F8268, 0x000110F9); - _WDWORD(0x401F826C, 0x000110F9); - _WDWORD(0x401F8270, 0x000110F9); - _WDWORD(0x401F8274, 0x000110F9); - _WDWORD(0x401F8278, 0x000110F9); - _WDWORD(0x401F827C, 0x000110F9); - _WDWORD(0x401F8280, 0x000110F9); - _WDWORD(0x401F8284, 0x000110F9); - _WDWORD(0x401F8288, 0x000110F9); - _WDWORD(0x401F828C, 0x000110F9); - _WDWORD(0x401F8290, 0x000110F9); - _WDWORD(0x401F8294, 0x000110F9); - _WDWORD(0x401F8298, 0x000110F9); - _WDWORD(0x401F829C, 0x000110F9); - _WDWORD(0x401F82A0, 0x000110F9); - _WDWORD(0x401F82A4, 0x000110F9); - _WDWORD(0x401F82A8, 0x000110F9); - - // Config SDR Controller Registers/ - _WDWORD(0x402F0000,0x10000004); // MCR - _WDWORD(0x402F0008,0x00030524); // BMCR0 - _WDWORD(0x402F000C,0x06030524); // BMCR1 - _WDWORD(0x402F0010,0x8000001B); // BR0, 32MB - _WDWORD(0x402F0014,0x8200001B); // BR1, 32MB - _WDWORD(0x402F0018,0x8400001B); // BR2, 32MB - _WDWORD(0x402F001C,0x8600001B); // BR3, 32MB - _WDWORD(0x402F0020,0x90000021); // BR4, - _WDWORD(0x402F0024,0xA0000019); // BR5, - _WDWORD(0x402F0028,0xA8000017); // BR6, - _WDWORD(0x402F002C,0xA900001B); // BR7, - _WDWORD(0x402F0030,0x00000021); // BR8, - _WDWORD(0x402F0004,0x000079A8); //IOCR,SEMC_CCSX0 as NOR CE, SEMC_CSX1 as PSRAM CE, SEMC_CSX2 as NAND CE, SEMC_CSX3 as DBI CE. - - // _WDWORD(0x402F0004,0x00000008); // IOCR, SEMC_CCSX0 as SDRAM_CS1 - _WDWORD(0x402F0040,0x00000F31); // SDRAMCR0 - _WDWORD(0x402F0044,0x00652922); // SDRAMCR1 - _WDWORD(0x402F0048,0x00010920); // SDRAMCR2 - _WDWORD(0x402F004C,0x50210A08); // SDRAMCR3 - - _WDWORD(0x402F0080,0x00000021); // DBICR0 - _WDWORD(0x402F0084,0x00888888); // DBICR1 - _WDWORD(0x402F0094,0x00000002); // IPCR1 - _WDWORD(0x402F0098,0x00000000); // IPCR2 - - _WDWORD(0x402F0090,0x80000000); // IPCR0 - _WDWORD(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA - SDRAM_WaitIpCmdDone(); - _WDWORD(0x402F0090,0x80000000); // IPCR0 - _WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF - SDRAM_WaitIpCmdDone(); - _WDWORD(0x402F0090,0x80000000); // IPCR0 - _WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF - SDRAM_WaitIpCmdDone(); - _WDWORD(0x402F00A0,0x00000033); // IPTXDAT - _WDWORD(0x402F0090,0x80000000); // IPCR0 - _WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS - SDRAM_WaitIpCmdDone(); - _WDWORD(0x402F004C,0x50210A09 ); // enable sdram self refresh again after initialization done. -} - -int imxrt_sdram_init(void) -{ - _clock_init(); - _sdr_Init(); - - return 0; -} - -/*@}*/ diff --git a/bsp/imxrt1052-evk/drivers/drv_spi_bus.c b/bsp/imxrt1052-evk/drivers/drv_spi_bus.c deleted file mode 100644 index 4460fafe41..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_spi_bus.c +++ /dev/null @@ -1,428 +0,0 @@ -/* - * File : drv_spi_bus.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2018-03-27 Liuguang the first version. - */ - -#include "drv_spi_bus.h" - -#include "fsl_common.h" -#include "fsl_iomuxc.h" -#include "fsl_lpspi.h" - -#if defined(RT_USING_SPIBUS1) || defined(RT_USING_SPIBUS2) || \ - defined(RT_USING_SPIBUS3) || defined(RT_USING_SPIBUS4) - -#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL - #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" -#endif - -#if !defined(LPSPI_CLK_SOURCE) -#define LPSPI_CLK_SOURCE (1U) /* PLL3 PFD0 */ -#endif -#if !defined(LPSPI_CLK_SOURCE_DIVIDER) -#define LPSPI_CLK_SOURCE_DIVIDER (8U) /* 8div */ -#endif - -/* LPSPI1 SCK SDO SDI IOMUX Config */ -#if defined(LPSPI1_SCK_GPIO_1) -#define LPSPI1_SCK_GPIO IOMUXC_GPIO_EMC_27_LPSPI1_SCK -#elif defined(LPSPI1_SCK_GPIO_2) -#define LPSPI1_SCK_GPIO IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK -#else -#define LPSPI1_SCK_GPIO IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK -#endif - -#if defined(LPSPI1_SDO_GPIO_1) -#define LPSPI1_SDO_GPIO IOMUXC_GPIO_EMC_28_LPSPI1_SDO -#elif defined(LPSPI1_SDO_GPIO_2) -#define LPSPI1_SDO_GPIO IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO -#else -#define LPSPI1_SDO_GPIO IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO -#endif - -#if defined(LPSPI1_SDI_GPIO_1) -#define LPSPI1_SDI_GPIO IOMUXC_GPIO_EMC_29_LPSPI1_SDI -#elif defined(LPSPI1_SDI_GPIO_2) -#define LPSPI1_SDI_GPIO IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI -#else -#define LPSPI1_SDI_GPIO IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI -#endif - -/* LPSPI2 SCK SDO SDI IOMUX Config */ -#if defined(LPSPI2_SCK_GPIO_1) -#define LPSPI2_SCK_GPIO IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK -#elif defined(LPSPI2_SCK_GPIO_2) -#define LPSPI2_SCK_GPIO IOMUXC_GPIO_EMC_00_LPSPI2_SCK -#else -#define LPSPI2_SCK_GPIO IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK -#endif - -#if defined(LPSPI2_SDO_GPIO_1) -#define LPSPI2_SDO_GPIO IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 -#elif defined(LPSPI2_SDO_GPIO_2) -#define LPSPI2_SDO_GPIO IOMUXC_GPIO_EMC_02_LPSPI2_SDO -#else -#define LPSPI2_SDO_GPIO IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 -#endif - -#if defined(LPSPI2_SDI_GPIO_1) -#define LPSPI2_SDI_GPIO IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI -#elif defined(LPSPI2_SDI_GPIO_2) -#define LPSPI2_SDI_GPIO IOMUXC_GPIO_EMC_03_LPSPI2_SDI -#else -#define LPSPI2_SDI_GPIO IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI -#endif - -/* LPSPI3 SCK SDO SDI IOMUX Config */ -#if defined(LPSPI3_SCK_GPIO_1) -#define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK -#elif defined(LPSPI3_SCK_GPIO_2) -#define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK -#else -#define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK -#endif - -#if defined(LPSPI3_SDO_GPIO_1) -#define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO -#elif defined(LPSPI3_SDO_GPIO_2) -#define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO -#else -#define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO -#endif - -#if defined(LPSPI3_SDI_GPIO_1) -#define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI -#elif defined(LPSPI3_SDI_GPIO_2) -#define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI -#else -#define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI -#endif - -/* LPSPI4 SCK SDO SDI IOMUX Config */ -#if defined(LPSPI4_SCK_GPIO_1) -#define LPSPI4_SCK_GPIO IOMUXC_GPIO_B0_03_LPSPI4_SCK -#elif defined(LPSPI4_SCK_GPIO_2) -#define LPSPI4_SCK_GPIO IOMUXC_GPIO_B1_07_LPSPI4_SCK -#else -#define LPSPI4_SCK_GPIO IOMUXC_GPIO_B0_03_LPSPI4_SCK -#endif - -#if defined(LPSPI4_SDO_GPIO_1) -#define LPSPI4_SDO_GPIO IOMUXC_GPIO_B0_02_LPSPI4_SDO -#elif defined(LPSPI4_SDO_GPIO_2) -#define LPSPI4_SDO_GPIO IOMUXC_GPIO_B1_06_LPSPI4_SDO -#else -#define LPSPI4_SDO_GPIO IOMUXC_GPIO_B0_02_LPSPI4_SDO -#endif - -#if defined(LPSPI4_SDI_GPIO_1) -#define LPSPI4_SDI_GPIO IOMUXC_GPIO_B0_01_LPSPI4_SDI -#elif defined(LPSPI4_SDI_GPIO_2) -#define LPSPI4_SDI_GPIO IOMUXC_GPIO_B1_05_LPSPI4_SDI -#else -#define LPSPI4_SDI_GPIO IOMUXC_GPIO_B0_01_LPSPI4_SDI -#endif - -struct rt1050_spi -{ - LPSPI_Type *base; - struct rt_spi_configuration *cfg; -}; - -struct rt1050_sw_spi_cs -{ - rt_uint32_t pin; -}; - -static uint32_t rt1050_get_lpspi_freq(void) -{ - uint32_t freq = 0; - - /* CLOCK_GetMux(kCLOCK_LpspiMux): - 00b: derive clock from PLL3 PFD1 720M - 01b: derive clock from PLL3 PFD0 720M - 10b: derive clock from PLL2 528M - 11b: derive clock from PLL2 PFD2 396M - */ - switch(CLOCK_GetMux(kCLOCK_LpspiMux)) - { - case 0: - freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk); - break; - - case 1: - freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk); - break; - - case 2: - freq = CLOCK_GetFreq(kCLOCK_SysPllClk); - break; - - case 3: - freq = CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk); - break; - } - - freq /= (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1U); - - return freq; -} - -static rt_err_t rt1050_spi_init(LPSPI_Type *base, struct rt_spi_configuration *cfg) -{ - lpspi_master_config_t masterConfig; - - RT_ASSERT(cfg != RT_NULL); - - if(cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32) - { - return RT_EINVAL; - } - -#if defined(RT_USING_SPIBUS1) - if(base == LPSPI1) - { - IOMUXC_SetPinMux (LPSPI1_SCK_GPIO, 0U); - IOMUXC_SetPinConfig(LPSPI1_SCK_GPIO, 0x10B0u); - IOMUXC_SetPinMux (LPSPI1_SDO_GPIO, 0U); - IOMUXC_SetPinConfig(LPSPI1_SDO_GPIO, 0x10B0u); - IOMUXC_SetPinMux (LPSPI1_SDI_GPIO, 0U); - IOMUXC_SetPinConfig(LPSPI1_SDI_GPIO, 0x10B0u); - } -#endif - -#if defined(RT_USING_SPIBUS2) - if(base == LPSPI2) - { - IOMUXC_SetPinMux (LPSPI2_SCK_GPIO, 0U); - IOMUXC_SetPinConfig(LPSPI2_SCK_GPIO, 0x10B0u); - IOMUXC_SetPinMux (LPSPI2_SDO_GPIO, 0U); - IOMUXC_SetPinConfig(LPSPI2_SDO_GPIO, 0x10B0u); - IOMUXC_SetPinMux (LPSPI2_SDI_GPIO, 0U); - IOMUXC_SetPinConfig(LPSPI2_SDI_GPIO, 0x10B0u); - } -#endif - -#if defined(RT_USING_SPIBUS3) - if(base == LPSPI3) - { - IOMUXC_SetPinMux (LPSPI3_SCK_GPIO, 0U); - IOMUXC_SetPinConfig(LPSPI3_SCK_GPIO, 0x10B0u); - IOMUXC_SetPinMux (LPSPI3_SDO_GPIO, 0U); - IOMUXC_SetPinConfig(LPSPI3_SDO_GPIO, 0x10B0u); - IOMUXC_SetPinMux (LPSPI3_SDI_GPIO, 0U); - IOMUXC_SetPinConfig(LPSPI3_SDI_GPIO, 0x10B0u); - } -#endif - -#if defined(RT_USING_SPIBUS4) - if(base == LPSPI4) - { - IOMUXC_SetPinMux (LPSPI4_SCK_GPIO, 0U); - IOMUXC_SetPinConfig(LPSPI4_SCK_GPIO, 0x10B0u); - IOMUXC_SetPinMux (LPSPI4_SDO_GPIO, 0U); - IOMUXC_SetPinConfig(LPSPI4_SDO_GPIO, 0x10B0u); - IOMUXC_SetPinMux (LPSPI4_SDI_GPIO, 0U); - IOMUXC_SetPinConfig(LPSPI4_SDI_GPIO, 0x10B0u); - } -#endif - - LPSPI_MasterGetDefaultConfig(&masterConfig); - - if(cfg->max_hz > 40*1000*1000) - { - cfg->max_hz = 40*1000*1000; - } - masterConfig.baudRate = cfg->max_hz; - masterConfig.bitsPerFrame = cfg->data_width; - - if(cfg->mode & RT_SPI_MSB) - { - masterConfig.direction = kLPSPI_MsbFirst; - } - else - { - masterConfig.direction = kLPSPI_LsbFirst; - } - - if(cfg->mode & RT_SPI_CPHA) - { - masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge; - } - else - { - masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge; - } - - if(cfg->mode & RT_SPI_CPOL) - { - masterConfig.cpol = kLPSPI_ClockPolarityActiveLow; - } - else - { - masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh; - } - - masterConfig.pinCfg = kLPSPI_SdiInSdoOut; - masterConfig.dataOutConfig = kLpspiDataOutTristate; - masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate; - masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate; - masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate; - - LPSPI_MasterInit(base, &masterConfig, rt1050_get_lpspi_freq()); - base->CFGR1 |= LPSPI_CFGR1_PCSCFG_MASK; - - return RT_EOK; -} - -rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin) -{ - rt_err_t ret = RT_EOK; - - struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); - RT_ASSERT(spi_device != RT_NULL); - - struct rt1050_sw_spi_cs *cs_pin = (struct rt1050_sw_spi_cs *)rt_malloc(sizeof(struct rt1050_sw_spi_cs)); - RT_ASSERT(cs_pin != RT_NULL); - - cs_pin->pin = pin; - rt_pin_mode(pin, PIN_MODE_OUTPUT); - rt_pin_write(pin, PIN_HIGH); - - ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); - - return ret; -} - -static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) -{ - rt_err_t ret = RT_EOK; - struct rt1050_spi *spi = RT_NULL; - - RT_ASSERT(cfg != RT_NULL); - RT_ASSERT(device != RT_NULL); - - spi = (struct rt1050_spi *)(device->bus->parent.user_data); - spi->cfg = cfg; - ret = rt1050_spi_init(spi->base, cfg); - - return ret; -} - -static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) -{ - lpspi_transfer_t transfer; - - RT_ASSERT(device != RT_NULL); - RT_ASSERT(device->bus != RT_NULL); - RT_ASSERT(device->bus->parent.user_data != RT_NULL); - - struct rt1050_spi *spi = (struct rt1050_spi *)(device->bus->parent.user_data); - struct rt1050_sw_spi_cs *cs = device->parent.user_data; - - if(message->cs_take) - { - rt_pin_write(cs->pin, PIN_LOW); - } - - transfer.dataSize = message->length; - transfer.rxData = (uint8_t *)(message->recv_buf); - transfer.txData = (uint8_t *)(message->send_buf); - - LPSPI_MasterTransferBlocking(spi->base, &transfer); - - if(message->cs_release) - { - rt_pin_write(cs->pin, PIN_HIGH); - } - - return message->length; -} - -#if defined(RT_USING_SPIBUS1) -static struct rt1050_spi spi1 = -{ - .base = LPSPI1 -}; -static struct rt_spi_bus spi1_bus = -{ - .parent.user_data = &spi1 -}; -#endif - -#if defined(RT_USING_SPIBUS2) -static struct rt1050_spi spi2 = -{ - .base = LPSPI2 -}; -static struct rt_spi_bus spi2_bus = -{ - .parent.user_data = &spi2 -}; -#endif - -#if defined(RT_USING_SPIBUS3) -static struct rt1050_spi spi3 = -{ - .base = LPSPI3 -}; -static struct rt_spi_bus spi3_bus = -{ - .parent.user_data = &spi3 -}; -#endif - -#if defined(RT_USING_SPIBUS4) -static struct rt1050_spi spi4 = -{ - .base = LPSPI4 -}; -static struct rt_spi_bus spi4_bus = -{ - .parent.user_data = &spi4 -}; -#endif - -static struct rt_spi_ops rt1050_spi_ops = -{ - .configure = spi_configure, - .xfer = spixfer -}; - -int rt_hw_spi_bus_init(void) -{ - CLOCK_SetMux(kCLOCK_LpspiMux, LPSPI_CLK_SOURCE); - CLOCK_SetDiv(kCLOCK_LpspiDiv, LPSPI_CLK_SOURCE_DIVIDER-1); - - CLOCK_EnableClock(kCLOCK_Iomuxc); - -#if defined(RT_USING_SPIBUS1) - rt_spi_bus_register(&spi1_bus, "spi1", &rt1050_spi_ops); -#endif - -#if defined(RT_USING_SPIBUS2) - rt_spi_bus_register(&spi2_bus, "spi2", &rt1050_spi_ops); -#endif - -#if defined(RT_USING_SPIBUS3) - rt_spi_bus_register(&spi3_bus, "spi3", &rt1050_spi_ops); -#endif - -#if defined(RT_USING_SPIBUS4) - rt_spi_bus_register(&spi4_bus, "spi4", &rt1050_spi_ops); -#endif - - return RT_EOK; -} -INIT_BOARD_EXPORT(rt_hw_spi_bus_init); - -#endif diff --git a/bsp/imxrt1052-evk/drivers/drv_spi_bus.h b/bsp/imxrt1052-evk/drivers/drv_spi_bus.h deleted file mode 100644 index b5016a4ebf..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_spi_bus.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * File : drv_spi_bus.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2018-03-27 Liuguang the first version. - */ - -#ifndef __DRV_SPI_BUS_H__ -#define __DRV_SPI_BUS_H__ - -#include -#include - -int rt_hw_spi_bus_init(void); -rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); - -#endif diff --git a/bsp/imxrt1052-evk/drivers/drv_spi_flash.c b/bsp/imxrt1052-evk/drivers/drv_spi_flash.c deleted file mode 100644 index 98927396b8..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_spi_flash.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * File : drv_spi_flash.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2018-04-02 Liuguang the first version. - */ - -#include "drv_spi_flash.h" - -#include "spi_flash.h" -#include "spi_flash_sfud.h" - -#ifndef SPI_FLASH_USING_SPIBUS_NAME -#define SPI_FLASH_USING_SPIBUS_NAME "spi4" -#endif -#ifndef SPI_FLASH_NAME -#define SPI_FLASH_NAME "flash0" -#endif -#ifndef SPI_FLASH_USING_CS_PIN -#define SPI_FLASH_USING_CS_PIN (79) -#endif - -int rt_hw_spi_flash_init(void) -{ - rt_err_t ret; - - extern rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, - const char *device_name, rt_uint32_t pin); - - ret = rt1050_spi_bus_attach_device(SPI_FLASH_USING_SPIBUS_NAME, - SPI_FLASH_USING_SPIBUS_NAME "0", SPI_FLASH_USING_CS_PIN); - if(ret != RT_EOK) - { - return ret; - } - - if(rt_sfud_flash_probe(SPI_FLASH_NAME, SPI_FLASH_USING_SPIBUS_NAME "0") == RT_NULL) - { - return RT_ERROR; - } - - return RT_EOK; -} -INIT_DEVICE_EXPORT(rt_hw_spi_flash_init); diff --git a/bsp/imxrt1052-evk/drivers/drv_spi_flash.h b/bsp/imxrt1052-evk/drivers/drv_spi_flash.h deleted file mode 100644 index ede2c53111..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_spi_flash.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * File : drv_spi_flash.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2018-04-02 Liuguang the first version. - */ - -#ifndef __DRV_SPI_FLASH_H_ -#define __DRV_SPI_FLASH_H_ - -#include -#include - -int rt_hw_spi_flash_init(void); - -#endif /* __DRV_SPI_FLASH_H_ */ diff --git a/bsp/imxrt1052-evk/drivers/drv_uart.c b/bsp/imxrt1052-evk/drivers/drv_uart.c deleted file mode 100644 index ca076ab19a..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_uart.c +++ /dev/null @@ -1,568 +0,0 @@ -/* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2013, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2017-10-10 Tanek the first version - * 2018-03-17 laiyiketang Add other uart. - */ -#include -#include "drv_uart.h" - -#include "fsl_common.h" -#include "fsl_lpuart.h" -#include "fsl_iomuxc.h" - -#ifdef RT_USING_SERIAL - -#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL -#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" -#endif - -#if !defined(RT_USING_UART1) && !defined(RT_USING_UART2) && \ - !defined(RT_USING_UART3) && !defined(RT_USING_UART4) && \ - !defined(RT_USING_UART5) && !defined(RT_USING_UART6) && \ - !defined(RT_USING_UART7) && !defined(RT_USING_UART8) -#error "Please define at least one UARTx" - -#endif - - - -#include - -/* imxrt uart driver */ -struct imxrt_uart -{ - LPUART_Type *uart_base; - IRQn_Type irqn; - - struct rt_serial_device *serial; - char *device_name; -}; - -static void uart_isr(struct rt_serial_device *serial); - -#if defined(RT_USING_UART1) -struct rt_serial_device serial1; - -void LPUART1_IRQHandler(void) -{ - uart_isr(&serial1); -} - -#endif /* RT_USING_UART1 */ - -#if defined(RT_USING_UART2) -struct rt_serial_device serial2; - -void LPUART2_IRQHandler(void) -{ - uart_isr(&serial2); -} - -#endif /* RT_USING_UART2 */ - -#if defined(RT_USING_UART3) -struct rt_serial_device serial3; - -void LPUART3_IRQHandler(void) -{ - uart_isr(&serial3); -} - -#endif /* RT_USING_UART3 */ - -#if defined(RT_USING_UART4) -struct rt_serial_device serial4; - -void LPUART4_IRQHandler(void) -{ - uart_isr(&serial4); -} -#endif /* RT_USING_UART4 */ - -#if defined(RT_USING_UART5) -struct rt_serial_device serial5; - -void LPUART5_IRQHandler(void) -{ - uart_isr(&serial5); -} - -#endif /* RT_USING_UART5 */ - -#if defined(RT_USING_UART6) -struct rt_serial_device serial6; - -void LPUART6_IRQHandler(void) -{ - uart_isr(&serial6); -} - -#endif /* RT_USING_UART6 */ - -#if defined(RT_USING_UART7) -struct rt_serial_device serial7; - -void LPUART7_IRQHandler(void) -{ - uart_isr(&serial7); -} - -#endif /* RT_USING_UART7 */ - -#if defined(RT_USING_UART8) -struct rt_serial_device serial8; - -void LPUART8_IRQHandler(void) -{ - uart_isr(&serial8); -} - -#endif /* RT_USING_UART8 */ - -static const struct imxrt_uart uarts[] = -{ -#ifdef RT_USING_UART1 - { - LPUART1, - LPUART1_IRQn, - &serial1, - "uart1", - }, -#endif -#ifdef RT_USING_UART2 - { - LPUART2, - LPUART2_IRQn, - &serial2, - "uart2", - }, -#endif -#ifdef RT_USING_UART3 - { - LPUART3, - LPUART3_IRQn, - &serial3, - "uart3", - }, -#endif -#ifdef RT_USING_UART4 - { - LPUART4, - LPUART4_IRQn, - &serial4, - "uart4", - }, -#endif -#ifdef RT_USING_UART5 - { - LPUART5, - LPUART5_IRQn, - &serial5, - "uart5", - }, -#endif -#ifdef RT_USING_UART6 - { - LPUART6, - LPUART6_IRQn, - &serial6, - "uart6", - }, -#endif -#ifdef RT_USING_UART7 - { - LPUART7, - LPUART7_IRQn, - &serial7, - "uart7", - }, -#endif -#ifdef RT_USING_UART8 - { - LPUART8, - LPUART8_IRQn, - &serial8, - "uart8", - }, -#endif - -}; - -/* Get debug console frequency. */ -uint32_t GetUartSrcFreq(void) -{ - uint32_t freq; - - /* To make it simple, we assume default PLL and divider settings, and the only variable - from application is use PLL3 source or OSC source */ - if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ - { - freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } - else - { - freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } - - return freq; -} - - -/** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example: -* - Peripheral's clock enable -* - Peripheral's GPIO Configuration -* - NVIC configuration for UART interrupt request enable -* @param huart: UART handle pointer -* @retval None -*/ -void imxrt_uart_gpio_init(struct imxrt_uart *uart) -{ - if (uart->uart_base != RT_NULL) - { -#ifdef RT_USING_UART1 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ - 0x10B0u); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ -#endif -#ifdef RT_USING_UART2 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_02_LPUART2_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_03_LPUART2_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_02_LPUART2_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_03_LPUART2_RX, - 0x10B0u); - -#endif -#ifdef RT_USING_UART3 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_06_LPUART3_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_07_LPUART3_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_06_LPUART3_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_07_LPUART3_RX, - 0x10B0u); -#endif -#ifdef RT_USING_UART4 -#ifdef BOARD_RT1050_ATK - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B1_00_LPUART4_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_SD_B1_01_LPUART4_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_SD_B1_00_LPUART4_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_SD_B1_01_LPUART4_RX, - 0x10B0u); -#else - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_00_LPUART4_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_01_LPUART4_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_00_LPUART4_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_01_LPUART4_RX, - 0x10B0u); -#endif -#endif -#ifdef RT_USING_UART5 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_12_LPUART5_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_13_LPUART5_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_12_LPUART5_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_13_LPUART5_RX, - 0x10B0u); -#endif -#ifdef RT_USING_UART6 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_02_LPUART6_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_03_LPUART6_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_02_LPUART6_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_03_LPUART6_RX, - 0x10B0u); -#endif -#ifdef RT_USING_UART7 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_31_LPUART7_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_32_LPUART7_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_31_LPUART7_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_32_LPUART7_RX, - 0x10B0u); -#endif -#ifdef RT_USING_UART8 - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_10_LPUART8_TX, - 0U); - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B1_11_LPUART8_RX, - 0U); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_10_LPUART8_TX, - 0x10B0u); - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B1_11_LPUART8_RX, - 0x10B0u); -#endif - } - else - { - RT_ASSERT(RT_NULL); - } -} - -static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct imxrt_uart *uart; - lpuart_config_t config; - - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - - uart = (struct imxrt_uart *)serial->parent.user_data; - - imxrt_uart_gpio_init(uart); - - LPUART_GetDefaultConfig(&config); - config.baudRate_Bps = cfg->baud_rate; - - switch (cfg->data_bits) - { - case DATA_BITS_7: - config.dataBitsCount = kLPUART_SevenDataBits; - break; - - default: - config.dataBitsCount = kLPUART_EightDataBits; - break; - } - - switch (cfg->stop_bits) - { - case STOP_BITS_2: - config.stopBitCount = kLPUART_TwoStopBit; - break; - default: - config.stopBitCount = kLPUART_OneStopBit; - break; - } - - switch (cfg->parity) - { - case PARITY_ODD: - config.parityMode = kLPUART_ParityOdd; - break; - case PARITY_EVEN: - config.parityMode = kLPUART_ParityEven; - break; - default: - config.parityMode = kLPUART_ParityDisabled; - break; - } - - config.enableTx = true; - config.enableRx = true; - - LPUART_Init(uart->uart_base, &config, GetUartSrcFreq()); - LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable); - - return RT_EOK; -} - -static rt_err_t imxrt_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct imxrt_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct imxrt_uart *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - DisableIRQ(uart->irqn); - - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - EnableIRQ(uart->irqn); - break; - } - - return RT_EOK; -} - -static int imxrt_putc(struct rt_serial_device *serial, char ch) -{ - struct imxrt_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct imxrt_uart *)serial->parent.user_data; - - LPUART_WriteByte(uart->uart_base, ch); - while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag)); - - return 1; -} - -static int imxrt_getc(struct rt_serial_device *serial) -{ - int ch; - struct imxrt_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct imxrt_uart *)serial->parent.user_data; - - ch = -1; - if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag) - ch = LPUART_ReadByte(uart->uart_base); - return ch; -} - -/** - * Uart common interrupt process. This need add to uart ISR. - * - * @param serial serial device - */ -static void uart_isr(struct rt_serial_device *serial) -{ - struct imxrt_uart *uart; - LPUART_Type *base; - - RT_ASSERT(serial != RT_NULL); - - uart = (struct imxrt_uart *) serial->parent.user_data; - RT_ASSERT(uart != RT_NULL); - - base = uart->uart_base; - RT_ASSERT(base != RT_NULL); - - /* enter interrupt */ - rt_interrupt_enter(); - - /* UART in mode Receiver -------------------------------------------------*/ - if (LPUART_GetStatusFlags(base) & kLPUART_RxDataRegFullFlag) - { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - } - - /* If RX overrun. */ - if (LPUART_STAT_OR_MASK & base->STAT) - { - /* Clear overrun flag, otherwise the RX does not work. */ - base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); - } - - /* leave interrupt */ - rt_interrupt_leave(); -} - -static const struct rt_uart_ops imxrt_uart_ops = -{ - imxrt_configure, - imxrt_control, - imxrt_putc, - imxrt_getc, -}; - -int imxrt_hw_uart_init(void) -{ - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - int i; - - /* Configure UART divider to default */ - CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */ - - for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) - { - uarts[i].serial->ops = &imxrt_uart_ops; - uarts[i].serial->config = config; - - /* register UART device */ - rt_hw_serial_register(uarts[i].serial, - uarts[i].device_name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - (void *)&uarts[i]); - } - - return 0; -} -INIT_BOARD_EXPORT(imxrt_hw_uart_init); - -#endif /*RT_USING_SERIAL */ diff --git a/bsp/imxrt1052-evk/drivers/drv_uart.h b/bsp/imxrt1052-evk/drivers/drv_uart.h deleted file mode 100644 index ca9fb423a1..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_uart.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * File : drv_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2017-10-10 Tanek the first version - */ - -#ifndef __DRV_UART_H__ -#define __DRV_UART_H__ - -#include -#include - - -#endif diff --git a/bsp/imxrt1052-evk/drivers/drv_usbd.c b/bsp/imxrt1052-evk/drivers/drv_usbd.c deleted file mode 100644 index 29e9913141..0000000000 --- a/bsp/imxrt1052-evk/drivers/drv_usbd.c +++ /dev/null @@ -1,561 +0,0 @@ -/* - * File : drv_usbc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2017-12-04 ZYH first implementation - */ -#include -#include -#include -#include -#include -#include -#include -#ifdef RT_USING_EHCI0_AS_DEVICE -#ifdef RT_USING_EHCI1_AS_DEVICE -#error Can not using 2 controller as usb device -#endif -#endif -#define FSL_USB_HS - -/* USB PHY condfiguration */ -#define BOARD_USB_PHY_D_CAL (0x0CU) -#define BOARD_USB_PHY_TXCAL45DP (0x06U) -#define BOARD_USB_PHY_TXCAL45DM (0x06U) -#define BOARD_XTAL0_CLK_HZ 24000000U - -#ifdef RT_USING_EHCI0_AS_DEVICE -static usb_device_handle ehci0_handle; -static struct udcd _fsl_udc_0; -#endif -#ifdef RT_USING_EHCI1_AS_DEVICE -static usb_device_handle ehci1_handle; -static struct udcd _fsl_udc_1; -#endif - - - -static usb_status_t usb_device_callback(usb_device_handle handle, uint32_t callbackEvent, void *eventParam); -static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_device_endpoint_callback_message_struct_t *message, void *callbackParam); -void USB_DeviceIsrEnable(uint8_t controllerId) -{ - uint8_t irqNumber; -#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) - uint8_t usbDeviceEhciIrq[] = USBHS_IRQS; - irqNumber = usbDeviceEhciIrq[controllerId - kUSB_ControllerEhci0]; -#endif -/* Install isr, set priority, and enable IRQ. */ -#if defined(__GIC_PRIO_BITS) - GIC_SetPriority((IRQn_Type)irqNumber, 3); -#else - NVIC_SetPriority((IRQn_Type)irqNumber, 3); -#endif - EnableIRQ((IRQn_Type)irqNumber); -} -void USB_DeviceClockInit(uint8_t controllerId) -{ -#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) - usb_phy_config_struct_t phyConfig = { - BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, - }; -#endif -#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) - if (controllerId == kUSB_ControllerEhci0) - { - CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U); - CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U); - } - else - { - CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U); - CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U); - } - USB_EhciPhyInit(controllerId, BOARD_XTAL0_CLK_HZ, &phyConfig); -#endif -} -#ifdef RT_USING_EHCI0_AS_DEVICE -#ifdef FSL_USB_HS -static struct ep_id _ehci0_ep_pool[] = -{ - {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, - {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0x2, USB_EP_ATTR_INT, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0x4, USB_EP_ATTR_INT, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0x5, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x5, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0x6, USB_EP_ATTR_INT, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x6, USB_EP_ATTR_INT, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x7, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, -}; -#else -static struct ep_id _ehci0_ep_pool[] = -{ - {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, - {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x2, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x4, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x5, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x5, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x6, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x6, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x7, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, -}; -#endif -void USB_OTG1_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - USB_DeviceEhciIsrFunction(ehci0_handle); - /* leave interrupt */ - rt_interrupt_leave(); -} -static rt_err_t _ehci0_ep_set_stall(rt_uint8_t address) -{ - USB_DeviceStallEndpoint(ehci0_handle, address); - return RT_EOK; -} -static rt_err_t _ehci0_ep_clear_stall(rt_uint8_t address) -{ - USB_DeviceUnstallEndpoint(ehci0_handle, address); - return RT_EOK; -} - -static rt_err_t _ehci0_set_address(rt_uint8_t address) -{ - USB_DeviceSetStatus(ehci0_handle, kUSB_DeviceStatusAddress, &address); - return RT_EOK; -} -static rt_err_t _ehci0_set_config(rt_uint8_t address) -{ - return RT_EOK; -} -static rt_err_t _ehci0_ep_enable(uep_t ep) -{ - usb_device_endpoint_init_struct_t ep_init; - usb_device_endpoint_callback_struct_t ep_callback; - rt_uint32_t param = ep->ep_desc->bEndpointAddress; - RT_ASSERT(ep != RT_NULL); - RT_ASSERT(ep->ep_desc != RT_NULL); - ep_init.maxPacketSize = ep->ep_desc->wMaxPacketSize; - ep_init.endpointAddress = ep->ep_desc->bEndpointAddress; - ep_init.transferType = ep->ep_desc->bmAttributes; - ep_init.zlt = 0; - ep_callback.callbackFn = usb_device_endpoint_callback; - ep_callback.callbackParam = (void *)param; - ep_callback.isBusy = 0; - USB_DeviceInitEndpoint(ehci0_handle,&ep_init,&ep_callback); - return RT_EOK; -} -static rt_err_t _ehci0_ep_disable(uep_t ep) -{ - RT_ASSERT(ep != RT_NULL); - RT_ASSERT(ep->ep_desc != RT_NULL); - USB_DeviceDeinitEndpoint(ehci0_handle, ep->ep_desc->bEndpointAddress); - return RT_EOK; -} -static rt_size_t _ehci0_ep_read(rt_uint8_t address, void *buffer) -{ - rt_size_t size = 0; - - RT_ASSERT(buffer != RT_NULL); - - return size; -} -static rt_size_t _ehci0_ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size) -{ - USB_DeviceRecvRequest(ehci0_handle, address, buffer, size); - return size; -} -static rt_size_t _ehci0_ep_write(rt_uint8_t address, void *buffer, rt_size_t size) -{ - USB_DeviceSendRequest(ehci0_handle, address, buffer, size); - return size; -} -static rt_err_t _ehci0_ep0_send_status(void) -{ - _ehci0_ep_write(0x00, NULL, 0); - return RT_EOK; -} -static rt_err_t _ehci0_suspend(void) -{ - return RT_EOK; -} - -static rt_err_t _ehci0_wakeup(void) -{ - return RT_EOK; -} -const static struct udcd_ops _ehci0_udc_ops = -{ - _ehci0_set_address, - _ehci0_set_config, - _ehci0_ep_set_stall, - _ehci0_ep_clear_stall, - _ehci0_ep_enable, - _ehci0_ep_disable, - _ehci0_ep_read_prepare, - _ehci0_ep_read, - _ehci0_ep_write, - _ehci0_ep0_send_status, - _ehci0_suspend, - _ehci0_wakeup, -}; -static rt_err_t drv_ehci0_usbd_init(rt_device_t device) -{ - usb_status_t result; - USB_DeviceClockInit(kUSB_ControllerEhci0); - - result = USB_DeviceInit(kUSB_ControllerEhci0,usb_device_callback,&ehci0_handle); - RT_ASSERT(ehci0_handle); - if(result == kStatus_USB_Success) - { - USB_DeviceIsrEnable(kUSB_ControllerEhci0); - USB_DeviceRun(ehci0_handle); - } - else - { - rt_kprintf("USB_DeviceInit ehci0 error\r\n"); - return RT_ERROR; - } - return RT_EOK; -} -#endif -#ifdef RT_USING_EHCI1_AS_DEVICE -#ifdef FSL_USB_HS -static struct ep_id _ehci1_ep_pool[] = -{ - {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, - {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0x2, USB_EP_ATTR_INT, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0x4, USB_EP_ATTR_INT, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0x5, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x5, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0x6, USB_EP_ATTR_INT, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x6, USB_EP_ATTR_INT, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 512, ID_UNASSIGNED}, - {0x7, USB_EP_ATTR_BULK, USB_DIR_OUT, 512, ID_UNASSIGNED}, - {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, -}; -#else -static struct ep_id _ehci1_ep_pool[] = -{ - {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, - {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x2, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x4, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x5, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x5, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x6, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x6, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x7, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, -}; -#endif -void USB_OTG2_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - USB_DeviceEhciIsrFunction(ehci1_handle); - /* leave interrupt */ - rt_interrupt_leave(); -} -static rt_err_t _ehci1_ep_set_stall(rt_uint8_t address) -{ - USB_DeviceStallEndpoint(ehci1_handle, address); - return RT_EOK; -} -static rt_err_t _ehci1_ep_clear_stall(rt_uint8_t address) -{ - USB_DeviceUnstallEndpoint(ehci1_handle, address); - return RT_EOK; -} - -static rt_err_t _ehci1_set_address(rt_uint8_t address) -{ - USB_DeviceSetStatus(ehci1_handle, kUSB_DeviceStatusAddress, &address); - return RT_EOK; -} -static rt_err_t _ehci1_set_config(rt_uint8_t address) -{ - return RT_EOK; -} -static rt_err_t _ehci1_ep_enable(uep_t ep) -{ - usb_device_endpoint_init_struct_t ep_init; - usb_device_endpoint_callback_struct_t ep_callback; - RT_ASSERT(ep != RT_NULL); - RT_ASSERT(ep->ep_desc != RT_NULL); - ep_init.maxPacketSize = ep->ep_desc->wMaxPacketSize; - ep_init.endpointAddress = ep->ep_desc->bEndpointAddress; - ep_init.transferType = ep->ep_desc->bmAttributes; - ep_init.zlt = 0; - ep_callback.callbackFn = usb_device_endpoint_callback; - ep_callback.callbackParam = (void *)ep_init.endpointAddress; - ep_callback.isBusy = 0; - USB_DeviceInitEndpoint(ehci1_handle,&ep_init,&ep_callback); - return RT_EOK; -} -static rt_err_t _ehci1_ep_disable(uep_t ep) -{ - RT_ASSERT(ep != RT_NULL); - RT_ASSERT(ep->ep_desc != RT_NULL); - USB_DeviceDeinitEndpoint(ehci1_handle, ep->ep_desc->bEndpointAddress); - return RT_EOK; -} -static rt_size_t _ehci1_ep_read(rt_uint8_t address, void *buffer) -{ - rt_size_t size = 0; - - RT_ASSERT(buffer != RT_NULL); - - return size; -} -static rt_size_t _ehci1_ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size) -{ - USB_DeviceRecvRequest(ehci1_handle, address, buffer, size); - return size; -} -static rt_size_t _ehci1_ep_write(rt_uint8_t address, void *buffer, rt_size_t size) -{ - USB_DeviceSendRequest(ehci1_handle, address, buffer, size); - return size; -} -static rt_err_t _ehci1_ep0_send_status(void) -{ - _ehci1_ep_write(0x00, NULL, 0); - return RT_EOK; -} -static rt_err_t _ehci1_suspend(void) -{ - return RT_EOK; -} - -static rt_err_t _ehci1_wakeup(void) -{ - return RT_EOK; -} -const static struct udcd_ops _ehci1_udc_ops = -{ - _ehci1_set_address, - _ehci1_set_config, - _ehci1_ep_set_stall, - _ehci1_ep_clear_stall, - _ehci1_ep_enable, - _ehci1_ep_disable, - _ehci1_ep_read_prepare, - _ehci1_ep_read, - _ehci1_ep_write, - _ehci1_ep0_send_status, - _ehci1_suspend, - _ehci1_wakeup, -}; -static rt_err_t drv_ehci1_usbd_init(rt_device_t device) -{ - usb_status_t result; - USB_DeviceClockInit(kUSB_ControllerEhci1); - - result = USB_DeviceInit(kUSB_ControllerEhci1,usb_device_callback,&ehci1_handle); - RT_ASSERT(ehci1_handle); - if(result == kStatus_USB_Success) - { - USB_DeviceIsrEnable(kUSB_ControllerEhci1); - USB_DeviceRun(ehci1_handle); - } - else - { - rt_kprintf("USB_DeviceInit ehci1 error\r\n"); - return RT_ERROR; - } - return RT_EOK; -} -#endif - - - -#if defined(RT_USING_EHCI0_AS_DEVICE) && defined(RT_USING_EHCI1_AS_DEVICE) -#error Can not using both now -#endif -static int rt_usbd_init(void) -{ - #ifdef RT_USING_EHCI0_AS_DEVICE - rt_memset((void *)&_fsl_udc_0, 0, sizeof(struct udcd)); - _fsl_udc_0.parent.type = RT_Device_Class_USBDevice; - _fsl_udc_0.parent.init = drv_ehci0_usbd_init; - _fsl_udc_0.ops = &_ehci0_udc_ops; - /* Register endpoint infomation */ - _fsl_udc_0.ep_pool = _ehci0_ep_pool; - _fsl_udc_0.ep0.id = &_ehci0_ep_pool[0]; - #ifdef FSL_USB_HS - _fsl_udc_0.device_is_hs = RT_TRUE; - #else - _fsl_udc_0.device_is_hs = RT_FALSE; - #endif - rt_device_register((rt_device_t)&_fsl_udc_0, "usbd", 0); - rt_usb_device_init(); - #endif - #ifdef RT_USING_EHCI1_AS_DEVICE - rt_memset((void *)&_fsl_udc_1, 0, sizeof(struct udcd)); - _fsl_udc_1.parent.type = RT_Device_Class_USBDevice; - _fsl_udc_1.parent.init = drv_ehci1_usbd_init; - _fsl_udc_1.ops = &_ehci1_udc_ops; - /* Register endpoint infomation */ - _fsl_udc_1.ep_pool = _ehci1_ep_pool; - _fsl_udc_1.ep0.id = &_ehci1_ep_pool[0]; - #ifdef FSL_USB_HS - _fsl_udc_1.device_is_hs = RT_TRUE; - #else - _fsl_udc_1.device_is_hs = RT_FALSE; - #endif - rt_device_register((rt_device_t)&_fsl_udc_1, "usbd", 0); - rt_usb_device_init(); - #endif - return 0; -} -INIT_DEVICE_EXPORT(rt_usbd_init); -static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_device_endpoint_callback_message_struct_t *message, void *callbackParam) -{ - rt_uint32_t ep_addr = (rt_uint32_t)callbackParam; - usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; - udcd_t udcd = RT_NULL; - uint8_t state; - if(deviceHandle->controllerId == kUSB_ControllerEhci0) - { - #ifdef RT_USING_EHCI0_AS_DEVICE - udcd = &_fsl_udc_0; - #endif - } - else - { - #ifdef RT_USING_EHCI1_AS_DEVICE - udcd = &_fsl_udc_1; - #endif - } - if(message->isSetup) - { - //rt_kprintf("1udcd:%#08X\n",udcd); - rt_usbd_ep0_setup_handler(udcd, (struct urequest*)message->buffer); - } - else if(ep_addr == 0x00) - { - USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - if(state == kUSB_DeviceStateAddressing) - { - if (kStatus_USB_Success == USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, NULL)) - { - state = kUSB_DeviceStateAddress; - USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - } - } - //rt_kprintf("2udcd:%#08X\n",udcd); - rt_usbd_ep0_out_handler(udcd,message->length); - } - else if(ep_addr == 0x80) - { - USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - if(state == kUSB_DeviceStateAddressing) - { - if (kStatus_USB_Success == USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, NULL)) - { - state = kUSB_DeviceStateAddress; - USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); - } - } - //rt_kprintf("3udcd:%#08X\n",udcd); - rt_usbd_ep0_in_handler(udcd); - } - else if(ep_addr&0x80) - { - rt_usbd_ep_in_handler(udcd, ep_addr, message->length); - } - else - { - rt_usbd_ep_out_handler(udcd, ep_addr, message->length); - } - return kStatus_USB_Success; -} -static usb_status_t usb_device_callback(usb_device_handle handle, uint32_t callbackEvent, void *eventParam) -{ - usb_status_t error = kStatus_USB_Error; - usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; - usb_device_endpoint_init_struct_t ep0_init = - { - 0x40, - 0x00, - USB_EP_ATTR_CONTROL, - 0 - }; - usb_device_endpoint_callback_struct_t ep0_callback = - { - usb_device_endpoint_callback, - 0, - 0 - }; - udcd_t udcd = RT_NULL; - if(deviceHandle->controllerId == kUSB_ControllerEhci0) - { - #ifdef RT_USING_EHCI0_AS_DEVICE - udcd = &_fsl_udc_0; - #endif - } - else - { - #ifdef RT_USING_EHCI1_AS_DEVICE - udcd = &_fsl_udc_1; - #endif - } - switch (callbackEvent) - { - case kUSB_DeviceEventBusReset: - ep0_init.endpointAddress = 0x00; - ep0_callback.callbackParam = (void *)0x00; - USB_DeviceInitEndpoint(deviceHandle,&ep0_init,&ep0_callback); - ep0_init.endpointAddress = 0x80; - ep0_callback.callbackParam = (void *)0x80; - USB_DeviceInitEndpoint(deviceHandle,&ep0_init,&ep0_callback); - rt_usbd_reset_handler(udcd); - break; - case kUSB_DeviceEventAttach: - rt_usbd_connect_handler(udcd); - break; - case kUSB_DeviceEventDetach: - rt_usbd_disconnect_handler(udcd); - break; - } - return error; -} - - - diff --git a/bsp/imxrt1052-evk/drivers/fsl_phy.c b/bsp/imxrt1052-evk/drivers/fsl_phy.c deleted file mode 100644 index b10b1e6cd8..0000000000 --- a/bsp/imxrt1052-evk/drivers/fsl_phy.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_phy.h" -#include -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Defines the timeout macro. */ -#define PHY_TIMEOUT_COUNT 0xFFFFU - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the ENET instance from peripheral base address. - * - * @param base ENET peripheral base address. - * @return ENET instance. - */ -extern uint32_t ENET_GetInstance(ENET_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to enet clocks for each instance. */ -extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) -{ - uint32_t bssReg; - uint32_t counter = PHY_TIMEOUT_COUNT; - uint32_t idReg = 0; - status_t result = kStatus_Success; - uint32_t instance = ENET_GetInstance(base); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Set SMI first. */ - CLOCK_EnableClock(s_enetClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - ENET_SetSMI(base, srcClock_Hz, false); - - /* Initialization after PHY stars to work. */ - while ((idReg != PHY_CONTROL_ID1) && (counter != 0)) - { - PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); - counter --; - } - - if (!counter) - { - return kStatus_Fail; - } - - /* Reset PHY. */ - counter = 6; - result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); - if (result == kStatus_Success) - { -#if defined(BOARD_RT1050_FIRE) - for (uint32_t i = 0x10000; i > 0; i--) - { - result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &bssReg); - if (!(bssReg & PHY_BCTL_POWER_DOWN_MASK)) - { - break; - } - } -#endif -#if defined(BOARD_RT1050_ATK) - rt_thread_delay(RT_TICK_PER_SECOND); -#endif -#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE) - uint32_t data = 0; - result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); - if ( result != kStatus_Success) - { - return result; - } - result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK)); - if (result != kStatus_Success) - { - return result; - } -#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */ - - /* Set the negotiation. */ - result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, - (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | - PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); - if (result == kStatus_Success) - { - result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, - (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); - if (result == kStatus_Success) - { - /* Check auto negotiation complete. */ - while (counter --) - { - result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); - if ( result == kStatus_Success) - { -#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) - if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0)) -#else - uint32_t ctlReg = 0; - PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); - if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK)) -#endif - { - rt_kprintf("auto negotiation complete success\n"); - break; - } - else - { - /* Wait a moment for Phy status stable. */ - __ASM("nop"); - } - } - - rt_kprintf("[PHY] wait autonegotiation complete...\n"); - rt_thread_delay(RT_TICK_PER_SECOND); - - if (!counter) - { - return kStatus_PHY_AutoNegotiateFail; - } - } - } - } - } - - return result; -} - -status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) -{ - uint32_t counter; - - /* Clear the SMI interrupt event. */ - ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); - - /* Starts a SMI write command. */ - ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data); - - /* Wait for SMI complete. */ - for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) - { - if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) - { - break; - } - } - - /* Check for timeout. */ - if (!counter) - { - return kStatus_PHY_SMIVisitTimeout; - } - - /* Clear MII interrupt event. */ - ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); - - return kStatus_Success; -} - -status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) -{ - assert(dataPtr); - - uint32_t counter; - - /* Clear the MII interrupt event. */ - ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); - - /* Starts a SMI read command operation. */ - ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame); - - /* Wait for MII complete. */ - for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) - { - if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) - { - break; - } - } - - /* Check for timeout. */ - if (!counter) - { - return kStatus_PHY_SMIVisitTimeout; - } - - /* Get data from MII register. */ - *dataPtr = ENET_ReadSMIData(base); - - /* Clear MII interrupt event. */ - ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); - - return kStatus_Success; -} - -status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable) -{ - status_t result; - uint32_t data = 0; - - /* Set the loop mode. */ - if (enable) - { - if (mode == kPHY_LocalLoop) - { - if (speed == kPHY_Speed100M) - { - data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; - } - else - { - data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; - } - return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data); - } - else - { - /* First read the current status in control register. */ - result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); - if (result == kStatus_Success) - { - return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); - } - } - } - else - { - /* Disable the loop mode. */ - if (mode == kPHY_LocalLoop) - { - /* First read the current status in control register. */ - result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); - if (result == kStatus_Success) - { - data &= ~PHY_BCTL_LOOP_MASK; - return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK)); - } - } - else - { - /* First read the current status in control one register. */ - result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); - if (result == kStatus_Success) - { - return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); - } - } - } - return result; -} - -status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) -{ - assert(status); - - status_t result = kStatus_Success; - uint32_t data; - - /* Read the basic status register. */ - result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data); - if (result == kStatus_Success) - { - if (!(PHY_BSTATUS_LINKSTATUS_MASK & data)) - { - /* link down. */ - *status = false; - } - else - { - /* link up. */ - *status = true; - } - } - return result; -} - -status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex) -{ - assert(duplex); - - status_t result = kStatus_Success; - uint32_t data, ctlReg; - - /* Read the control two register. */ -#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) - result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &ctlReg); -#endif -#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio) - result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); -#endif - if (result == kStatus_Success) - { - data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; - if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) - { - /* Full duplex. */ - *duplex = kPHY_FullDuplex; - } - else - { - /* Half duplex. */ - *duplex = kPHY_HalfDuplex; - } - - data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; - if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) - { - /* 100M speed. */ - *speed = kPHY_Speed100M; - } - else - { /* 10M speed. */ - *speed = kPHY_Speed10M; - } - } - - return result; -} diff --git a/bsp/imxrt1052-evk/drivers/fsl_phy.h b/bsp/imxrt1052-evk/drivers/fsl_phy.h deleted file mode 100644 index a1b4f5f89b..0000000000 --- a/bsp/imxrt1052-evk/drivers/fsl_phy.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _FSL_PHY_H_ -#define _FSL_PHY_H_ -#include "rtconfig.h" -#include "fsl_enet.h" - -/*! - * @addtogroup phy_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief PHY driver version */ -#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - -/*! @brief Defines the PHY registers. */ -#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ -#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ -#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ -#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ -#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ -#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ -#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ - -#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) -#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/ -#endif -#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio) -#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ -#endif -/*! @brief Defines the mask flag in basic control register. */ -#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ -#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ -#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ -#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ -#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ -#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ -#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */ -#define PHY_BCTL_POWER_DOWN_MASK 0x800U /*!< The PHY Power Down mask. */ - - -/*!@brief Defines the mask flag of operation mode in control two register*/ -#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) -#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ -#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ -#define PHY_CTL1_10HALFDUPLEX_MASK 0x0004U /*!< The PHY 10M half duplex mask. */ -#define PHY_CTL1_100HALFDUPLEX_MASK 0x0008U /*!< The PHY 100M half duplex mask. */ -#define PHY_CTL1_10FULLDUPLEX_MASK 0x0014U /*!< The PHY 10M full duplex mask. */ -#define PHY_CTL1_100FULLDUPLEX_MASK 0x0018U /*!< The PHY 100M full duplex mask. */ -#define PHY_CTL1_SPEEDUPLX_MASK 0x001CU /*!< The PHY speed and duplex mask. */ -#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */ -#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ -#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) -#endif -#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio) -#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ -#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ -#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ -#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ -#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ -#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ -#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ -#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */ -#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ -#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) -#endif -/*! @brief Defines the mask flag in basic status register. */ -#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ -#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ -#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ - -/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ -#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ -#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ -#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ -#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ -#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ - -/*! @brief Defines the PHY status. */ -enum _phy_status -{ - kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ - kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ -}; - -/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ -typedef enum _phy_speed -{ - kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ - kPHY_Speed100M /*!< ENET PHY 100M speed. */ -} phy_speed_t; - -/*! @brief Defines the PHY link duplex. */ -typedef enum _phy_duplex -{ - kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ - kPHY_FullDuplex /*!< ENET PHY full duplex. */ -} phy_duplex_t; - -/*! @brief Defines the PHY loopback mode. */ -typedef enum _phy_loop -{ - kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */ - kPHY_RemoteLoop /*!< ENET PHY remote loopback. */ -} phy_loop_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name PHY Driver - * @{ - */ - -/*! - * @brief Initializes PHY. - * - * This function initialize the SMI interface and initialize PHY. - * The SMI is the MII management interface between PHY and MAC, which should be - * firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. - * @retval kStatus_Success PHY initialize success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - * @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail - */ -status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); - -/*! - * @brief PHY Write function. This function write data over the SMI to - * the specified PHY register. This function is called by all PHY interfaces. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. - * @param data The data written to the PHY register. - * @retval kStatus_Success PHY write success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); - -/*! - * @brief PHY Read function. This interface read data over the SMI from the - * specified PHY register. This function is called by all PHY interfaces. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. - * @param dataPtr The address to store the data read from the PHY register. - * @retval kStatus_Success PHY read success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); - -/*! - * @brief Enables/disables PHY loopback. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param mode The loopback mode to be enabled, please see "phy_loop_t". - * the two loopback mode should not be both set. when one loopback mode is set - * the other one should be disabled. - * @param speed PHY speed for loopback mode. - * @param enable True to enable, false to disable. - * @retval kStatus_Success PHY loopback success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable); - -/*! - * @brief Gets the PHY link status. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param status The link up or down status of the PHY. - * - true the link is up. - * - false the link is down. - * @retval kStatus_Success PHY get link status success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status); - -/*! - * @brief Gets the PHY link speed and duplex. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param speed The address of PHY link speed. - * @param duplex The link duplex of PHY. - * @retval kStatus_Success PHY get link speed and duplex success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PHY_H_ */ diff --git a/bsp/imxrt1052-evk/drivers/fsl_wm8960.c b/bsp/imxrt1052-evk/drivers/fsl_wm8960.c deleted file mode 100644 index 11c21742ec..0000000000 --- a/bsp/imxrt1052-evk/drivers/fsl_wm8960.c +++ /dev/null @@ -1,621 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "fsl_wm8960.h" -#include "fsl_common.h" - -/******************************************************************************* - * Definitations - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* - * wm8960 register cache - * We can't read the WM8960 register space when we are - * using 2 wire for device control, so we cache them instead. - */ -static const uint16_t wm8960_reg[WM8960_CACHEREGNUM] = { - 0x0097, 0x0097, 0x0000, 0x0000, 0x0000, 0x0008, 0x0000, 0x000a, 0x01c0, 0x0000, 0x00ff, 0x00ff, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x007b, 0x0100, 0x0032, 0x0000, 0x00c3, 0x00c3, 0x01c0, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0100, 0x0100, 0x0050, 0x0050, 0x0050, 0x0050, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0040, 0x0000, 0x0000, 0x0050, 0x0050, 0x0000, 0x0002, 0x0037, 0x004d, 0x0080, 0x0008, 0x0031, 0x0026, 0x00e9, -}; - -static uint16_t reg_cache[WM8960_CACHEREGNUM]; -/******************************************************************************* - * Code - ******************************************************************************/ - -void WM8960_Init(wm8960_handle_t *handle, wm8960_config_t *config) -{ - uint32_t i = 4000000; - - memcpy(reg_cache, wm8960_reg, sizeof(wm8960_reg)); - - /* Set WM8960 I2C address */ - handle->xfer.slaveAddress = WM8960_I2C_ADDR; - - /* NULL pointer means default setting. */ - if (config == NULL) - { - /* - * Reset all registers - */ - WM8960_WriteReg(handle, WM8960_RESET, 0x00); - - WM8960_WriteReg(handle, WM8960_IFACE2, 0x40); - /* - * VMID=50K, Enable VREF, AINL, AINR, ADCL and ADCR - * I2S_IN (bit 0), I2S_OUT (bit 1), DAP (bit 4), DAC (bit 5), ADC (bit 6) are powered on - */ - WM8960_WriteReg(handle, WM8960_POWER1, 0xCA); - - /* - * Enable DACL, DACR, LOUT1, ROUT1, PLL down - */ - WM8960_WriteReg(handle, WM8960_POWER2, 0x1E0); - - /* - * Enable left and right channel input PGA, left and right output mixer - */ - WM8960_WriteReg(handle, WM8960_POWER3, 0xC); - - /* Configure SYS_FS clock to 44.1kHz, MCLK_FREQ to 256*Fs, SYSCLK derived from MCLK input */ - WM8960_WriteReg(handle, WM8960_CLOCK1, 0x00); - - /* - * Audio data length = 32bit, Left justified data format - */ - WM8960_WriteReg(handle, WM8960_IFACE1, 0x0D); - - /* - * LMICBOOST = 0dB, Connect left and right PGA to left and right Input Boost Mixer - */ - WM8960_WriteReg(handle, WM8960_LINPATH, 0x18); - WM8960_WriteReg(handle, WM8960_RINPATH, 0x18); - - /* - * Left and right input boost, LIN3BOOST and RIN3BOOST = 0dB - */ - WM8960_WriteReg(handle, WM8960_INBMIX1, 0x70); - WM8960_WriteReg(handle, WM8960_INBMIX2, 0x70); - - /* - * Left DAC and LINPUT3 to left output mixer, LINPUT3 left output mixer volume = 0dB - */ - WM8960_WriteReg(handle, WM8960_LOUTMIX, 0x100); - - /* - * Right DAC and RINPUT3 to right output mixer, RINPUT3 right output mixer volume = 0dB - */ - WM8960_WriteReg(handle, WM8960_ROUTMIX, 0x100); - - WM8960_WriteReg(handle, WM8960_BYPASS1, 0x0); - - WM8960_WriteReg(handle, WM8960_BYPASS2, 0x0); - - WM8960_WriteReg(handle, WM8960_MONOMIX1, 0x00); - WM8960_WriteReg(handle, WM8960_MONOMIX2, 0x00); - } - else - { - WM8960_SetDataRoute(handle, config->route); - WM8960_SetProtocol(handle, config->bus); - WM8960_SetMasterSlave(handle, config->master_slave); - } - WM8960_WriteReg(handle, WM8960_ADDCTL1, 0x0C4); - WM8960_WriteReg(handle, WM8960_ADDCTL4, 0x40); - - /* - * ADC volume, 0dB - */ - WM8960_WriteReg(handle, WM8960_LADC, 0x1F3); - WM8960_WriteReg(handle, WM8960_RADC, 0x1F3); - - /* - * Digital DAC volume, 0dB - */ - WM8960_WriteReg(handle, WM8960_LDAC, 0x1E0); - WM8960_WriteReg(handle, WM8960_RDAC, 0x1E0); - - /* - * Headphone volume, LOUT1 and ROUT1, 0dB - */ - WM8960_WriteReg(handle, WM8960_LOUT1, 0x16F); - WM8960_WriteReg(handle, WM8960_ROUT1, 0x16F); - - /* Delay for some while */ - while (i) - { - __ASM("nop"); - i--; - } - - /* Unmute DAC. */ - WM8960_WriteReg(handle, WM8960_DACCTL1, 0x0000); -} - -void WM8960_Deinit(wm8960_handle_t *handle) -{ - WM8960_SetModule(handle, kWM8960_ModuleADC, false); - WM8960_SetModule(handle, kWM8960_ModuleDAC, false); - WM8960_SetModule(handle, kWM8960_ModuleVREF, false); - WM8960_SetModule(handle, kWM8960_ModuleLineIn, false); - WM8960_SetModule(handle, kWM8960_ModuleLineOut, false); - WM8960_SetModule(handle, kWM8960_ModuleSpeaker, false); -} - -void WM8960_SetMasterSlave(wm8960_handle_t *handle, bool master) -{ - if (master == 1) - { - WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS(WM8960_IFACE1_MASTER)); - } - else - { - WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS(WM8960_IFACE1_SLAVE)); - } -} - -status_t WM8960_SetModule(wm8960_handle_t *handle, wm8960_module_t module, bool isEnabled) -{ - status_t ret = kStatus_Success; - switch (module) - { - case kWM8960_ModuleADC: - WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_ADCL_MASK, - ((uint16_t)isEnabled << WM8960_POWER1_ADCL_SHIFT)); - WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_ADCR_MASK, - ((uint16_t)isEnabled << WM8960_POWER1_ADCR_SHIFT)); - break; - case kWM8960_ModuleDAC: - WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_DACL_MASK, - ((uint16_t)isEnabled << WM8960_POWER2_DACL_SHIFT)); - WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_DACR_MASK, - ((uint16_t)isEnabled << WM8960_POWER2_DACR_SHIFT)); - break; - case kWM8960_ModuleVREF: - WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_VREF_MASK, - ((uint16_t)isEnabled << WM8960_POWER1_VREF_SHIFT)); - break; - case kWM8960_ModuleLineIn: - WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_AINL_MASK, - ((uint16_t)isEnabled << WM8960_POWER1_AINL_SHIFT)); - WM8960_ModifyReg(handle, WM8960_POWER1, WM8960_POWER1_AINR_MASK, - ((uint16_t)isEnabled << WM8960_POWER1_AINR_SHIFT)); - break; - case kWM8960_ModuleLineOut: - WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_LOUT1_MASK, - ((uint16_t)isEnabled << WM8960_POWER2_LOUT1_SHIFT)); - WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_ROUT1_MASK, - ((uint16_t)isEnabled << WM8960_POWER2_ROUT1_SHIFT)); - break; - case kWM8960_ModuleSpeaker: - WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_SPKL_MASK, - ((uint16_t)isEnabled << WM8960_POWER2_SPKL_SHIFT)); - WM8960_ModifyReg(handle, WM8960_POWER2, WM8960_POWER2_SPKR_MASK, - ((uint16_t)isEnabled << WM8960_POWER2_SPKR_SHIFT)); - WM8960_WriteReg(handle, WM8960_CLASSD1, 0xF7); - break; - default: - ret = kStatus_InvalidArgument; - break; - } - return ret; -} - -status_t WM8960_SetDataRoute(wm8960_handle_t *handle, wm8960_route_t route) -{ - status_t ret = kStatus_Success; - switch (route) - { - case kWM8960_RouteBypass: - /* Bypass means from line-in to HP*/ - /* - * Left LINPUT3 to left output mixer, LINPUT3 left output mixer volume = 0dB - */ - WM8960_WriteReg(handle, WM8960_LOUTMIX, 0x80); - - /* - * Right RINPUT3 to right output mixer, RINPUT3 right output mixer volume = 0dB - */ - WM8960_WriteReg(handle, WM8960_ROUTMIX, 0x80); - break; - case kWM8960_RoutePlayback: - /* Data route I2S_IN-> DAC-> HP */ - /* - * Left DAC to left output mixer, LINPUT3 left output mixer volume = 0dB - */ - WM8960_WriteReg(handle, WM8960_LOUTMIX, 0x100); - - /* - * Right DAC to right output mixer, RINPUT3 right output mixer volume = 0dB - */ - WM8960_WriteReg(handle, WM8960_ROUTMIX, 0x100); - break; - case kWM8960_RoutePlaybackandRecord: - /* I2S IN->DAC->HP LINE_IN->ADC->I2S_OUT */ - /* - * Left and right input boost, LIN3BOOST and RIN3BOOST = 0dB - */ - WM8960_WriteReg(handle, WM8960_INBMIX1, 0x50); - WM8960_WriteReg(handle, WM8960_INBMIX2, 0x50); - /* - * Left DAC to left output mixer, LINPUT3 left output mixer volume = 0dB - */ - WM8960_WriteReg(handle, WM8960_LOUTMIX, 0x100); - - /* - * Right DAC to right output mixer, RINPUT3 right output mixer volume = 0dB - */ - WM8960_WriteReg(handle, WM8960_ROUTMIX, 0x100); - break; - case kWM8960_RoutePlaybackwithDAP: - /* I2S_IN->DAP->DAC->HP */ - break; - case kWM8960_RoutePlaybackwithDAPandRecord: - /* I2S_IN->DAP->DAC->HP, LINE_IN->ADC->I2S_OUT */ - break; - case kWM8960_RouteRecord: - /* LINE_IN->ADC->I2S_OUT */ - /* - * Left and right input boost, LIN3BOOST and RIN3BOOST = 0dB - */ - WM8960_WriteReg(handle, WM8960_INBMIX1, 0x50); - WM8960_WriteReg(handle, WM8960_INBMIX2, 0x50); - break; - default: - ret = kStatus_InvalidArgument; - break; - } - return ret; -} - -status_t WM8960_SetProtocol(wm8960_handle_t *handle, wm8960_protocol_t protocol) -{ - status_t ret = kStatus_Success; - switch (protocol) - { - case kWM8960_BusI2S: - WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, - WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_I2S)); - break; - case kWM8960_BusLeftJustified: - WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, - WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_LJ)); - break; - case kWM8960_BusRightJustified: - WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, - WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_RJ)); - break; - case kWM8960_BusPCMA: - WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, - WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_DSP)); - WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_LRP_MASK, WM8960_IFACE1_LRP(WM8960_IFACE1_DSP_MODEA)); - break; - case kWM8960_BusPCMB: - WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, - WM8960_IFACE1_FORMAT(WM8960_IFACE1_FORMAT_DSP)); - WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_LRP_MASK, WM8960_IFACE1_LRP(WM8960_IFACE1_DSP_MODEB)); - break; - default: - ret = kStatus_InvalidArgument; - break; - } - WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL(WM8960_IFACE1_WL_32BITS)); - return ret; -} - -status_t WM8960_SetVolume(wm8960_handle_t *handle, wm8960_module_t module, uint32_t volume) -{ - uint16_t vol = 0; - status_t ret = kStatus_Success; - switch (module) - { - case kWM8960_ModuleADC: - vol = 0x100 | volume; - ret = WM8960_WriteReg(handle, WM8960_LADC, vol); - ret = WM8960_WriteReg(handle, WM8960_RADC, vol); - break; - case kWM8960_ModuleDAC: - vol = 0x100 | volume; - ret = WM8960_WriteReg(handle, WM8960_LDAC, vol); - ret = WM8960_WriteReg(handle, WM8960_RDAC, vol); - break; - case kWM8960_ModuleHP: - vol = 0x100 | volume; - ret = WM8960_WriteReg(handle, WM8960_LOUT1, vol); - ret = WM8960_WriteReg(handle, WM8960_ROUT1, vol); - break; - case kWM8960_ModuleLineIn: - vol = 0x100 | volume; - ret = WM8960_WriteReg(handle, WM8960_LINVOL, vol); - ret = WM8960_WriteReg(handle, WM8960_RINVOL, vol); - break; - case kWM8960_ModuleSpeaker: - vol = 0x100 | volume; - ret = WM8960_WriteReg(handle, WM8960_LOUT2, vol); - ret = WM8960_WriteReg(handle, WM8960_ROUT2, vol); - break; - default: - ret = kStatus_InvalidArgument; - break; - } - return ret; -} - -uint32_t WM8960_GetVolume(wm8960_handle_t *handle, wm8960_module_t module) -{ - uint16_t vol = 0; - switch (module) - { - case kWM8960_ModuleADC: - WM8960_ReadReg(WM8960_LADC, &vol); - vol &= 0xFF; - break; - case kWM8960_ModuleDAC: - WM8960_ReadReg(WM8960_LDAC, &vol); - vol &= 0xFF; - break; - case kWM8960_ModuleHP: - WM8960_ReadReg(WM8960_LOUT1, &vol); - vol &= 0x7F; - break; - case kWM8960_ModuleLineOut: - WM8960_ReadReg(WM8960_LINVOL, &vol); - vol &= 0x3F; - break; - default: - vol = 0; - break; - } - return vol; -} - -status_t WM8960_SetMute(wm8960_handle_t *handle, wm8960_module_t module, bool isEnabled) -{ - status_t ret = kStatus_Success; - switch (module) - { - case kWM8960_ModuleADC: - /* - * Digital Mute - */ - if (isEnabled) - { - ret = WM8960_WriteReg(handle, WM8960_LADC, 0x100); - ret = WM8960_WriteReg(handle, WM8960_RADC, 0x100); - } - else - { - ret = WM8960_WriteReg(handle, WM8960_LADC, 0x1C3); - ret = WM8960_WriteReg(handle, WM8960_RADC, 0x1C3); - } - break; - case kWM8960_ModuleDAC: - /* - * Digital mute - */ - if (isEnabled) - { - ret = WM8960_WriteReg(handle, WM8960_LDAC, 0x100); - ret = WM8960_WriteReg(handle, WM8960_RDAC, 0x100); - } - else - { - ret = WM8960_WriteReg(handle, WM8960_LDAC, 0x1FF); - ret = WM8960_WriteReg(handle, WM8960_RDAC, 0x1FF); - } - break; - case kWM8960_ModuleHP: - /* - * Analog mute - */ - if (isEnabled) - { - ret = WM8960_WriteReg(handle, WM8960_LOUT1, 0x100); - ret = WM8960_WriteReg(handle, WM8960_ROUT1, 0x100); - } - else - { - ret = WM8960_WriteReg(handle, WM8960_LOUT1, 0x179); - ret = WM8960_WriteReg(handle, WM8960_ROUT1, 0x179); - } - break; - case kWM8960_ModuleLineOut: - break; - default: - ret = kStatus_InvalidArgument; - break; - } - return ret; -} - -status_t WM8960_ConfigDataFormat(wm8960_handle_t *handle, uint32_t mclk, uint32_t sample_rate, uint8_t bits) -{ - status_t retval = kStatus_Success; - - switch (sample_rate) - { - case 8000: - retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x1B0); - break; - case 11025: - retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0xD8); - break; - case 12000: - retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x120); - break; - case 16000: - retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0xD8); - break; - case 22050: - retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0xD8); - break; - case 24000: - retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x90); - break; - case 32000: - retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x48); - break; - case 44100: - retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0xD8); - break; - case 48000: - retval = WM8960_WriteReg(handle, WM8960_CLOCK1, 0x00); - break; - default: - retval = kStatus_InvalidArgument; - break; - } - - /* - * Slave mode (MS = 0), LRP = 0, 32bit WL, left justified (FORMAT[1:0]=0b01) - */ - switch (bits) - { - case 16: - retval = WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, - WM8960_IFACE1_WL(WM8960_IFACE1_WL_16BITS)); - break; - case 20: - retval = WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, - WM8960_IFACE1_WL(WM8960_IFACE1_WL_20BITS)); - break; - case 24: - retval = WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, - WM8960_IFACE1_WL(WM8960_IFACE1_WL_24BITS)); - break; - case 32: - retval = WM8960_ModifyReg(handle, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, - WM8960_IFACE1_WL(WM8960_IFACE1_WL_32BITS)); - break; - default: - retval = kStatus_InvalidArgument; - break; - } - - return retval; -} - -status_t WM8960_SetJackDetect(wm8960_handle_t *handle, bool isEnabled) -{ - uint8_t retval = 0; - uint16_t val = 0; - - WM8960_ReadReg(WM8960_ADDCTL2, &val); - - if (isEnabled) - { - val |= 0x40U; - } - else - { - val &= 0xCF; - } - - retval = WM8960_WriteReg(handle, WM8960_ADDCTL2, val); - - return retval; -} - -status_t WM8960_WriteReg(wm8960_handle_t *handle, uint8_t reg, uint16_t val) -{ - uint8_t cmd, buff; - uint8_t retval = 0; - - /* The register address */ - cmd = (reg << 1) | ((val >> 8U) & 0x0001U); - /* Data */ - buff = val & 0xFF; - - /* Copy data to cache */ - reg_cache[reg] = val; - -#if defined(FSL_FEATURE_SOC_LPI2C_COUNT) && (FSL_FEATURE_SOC_LPI2C_COUNT) - uint8_t data[2]; - data[0] = cmd; - data[1] = buff; - retval = LPI2C_MasterStart(handle->base, WM8960_I2C_ADDR, kLPI2C_Write); - retval = LPI2C_MasterSend(handle->base, data, 2); - retval = LPI2C_MasterStop(handle->base); -#else - /* Config the I2C xfer */ - handle->xfer.direction = kI2C_Write; - handle->xfer.subaddress = cmd; - handle->xfer.subaddressSize = 1U; - handle->xfer.data = &buff; - handle->xfer.dataSize = 1U; - - retval = I2C_MasterTransferBlocking(handle->base, &handle->xfer); -#endif - - if (retval != kStatus_Success) - { - return kStatus_Fail; - } - return kStatus_Success; -} - -status_t WM8960_ReadReg(uint8_t reg, uint16_t *val) -{ - if (reg >= WM8960_CACHEREGNUM) - { - return kStatus_InvalidArgument; - } - - *val = reg_cache[reg]; - - return kStatus_Success; -} - -status_t WM8960_ModifyReg(wm8960_handle_t *handle, uint8_t reg, uint16_t mask, uint16_t val) -{ - uint8_t retval = 0; - uint16_t reg_val = 0; - retval = WM8960_ReadReg(reg, ®_val); - if (retval != kStatus_Success) - { - return kStatus_Fail; - } - reg_val &= (uint16_t)~mask; - reg_val |= val; - retval = WM8960_WriteReg(handle, reg, reg_val); - if (retval != kStatus_Success) - { - return kStatus_Fail; - } - return kStatus_Success; -} diff --git a/bsp/imxrt1052-evk/drivers/fsl_wm8960.h b/bsp/imxrt1052-evk/drivers/fsl_wm8960.h deleted file mode 100644 index 848e0332f9..0000000000 --- a/bsp/imxrt1052-evk/drivers/fsl_wm8960.h +++ /dev/null @@ -1,426 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_WM8960_H_ -#define _FSL_WM8960_H_ - -#include "fsl_common.h" -#if defined(FSL_FEATURE_SOC_LPI2C_COUNT) && (FSL_FEATURE_SOC_LPI2C_COUNT) -#include "fsl_lpi2c.h" -#else -#include "fsl_i2c.h" -#endif - -/*! - * @addtogroup wm8960 - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Define the register address of WM8960. */ -#define WM8960_LINVOL 0x0 -#define WM8960_RINVOL 0x1 -#define WM8960_LOUT1 0x2 -#define WM8960_ROUT1 0x3 -#define WM8960_CLOCK1 0x4 -#define WM8960_DACCTL1 0x5 -#define WM8960_DACCTL2 0x6 -#define WM8960_IFACE1 0x7 -#define WM8960_CLOCK2 0x8 -#define WM8960_IFACE2 0x9 -#define WM8960_LDAC 0xa -#define WM8960_RDAC 0xb - -#define WM8960_RESET 0xf -#define WM8960_3D 0x10 -#define WM8960_ALC1 0x11 -#define WM8960_ALC2 0x12 -#define WM8960_ALC3 0x13 -#define WM8960_NOISEG 0x14 -#define WM8960_LADC 0x15 -#define WM8960_RADC 0x16 -#define WM8960_ADDCTL1 0x17 -#define WM8960_ADDCTL2 0x18 -#define WM8960_POWER1 0x19 -#define WM8960_POWER2 0x1a -#define WM8960_ADDCTL3 0x1b -#define WM8960_APOP1 0x1c -#define WM8960_APOP2 0x1d - -#define WM8960_LINPATH 0x20 -#define WM8960_RINPATH 0x21 -#define WM8960_LOUTMIX 0x22 - -#define WM8960_ROUTMIX 0x25 -#define WM8960_MONOMIX1 0x26 -#define WM8960_MONOMIX2 0x27 -#define WM8960_LOUT2 0x28 -#define WM8960_ROUT2 0x29 -#define WM8960_MONO 0x2a -#define WM8960_INBMIX1 0x2b -#define WM8960_INBMIX2 0x2c -#define WM8960_BYPASS1 0x2d -#define WM8960_BYPASS2 0x2e -#define WM8960_POWER3 0x2f -#define WM8960_ADDCTL4 0x30 -#define WM8960_CLASSD1 0x31 - -#define WM8960_CLASSD3 0x33 -#define WM8960_PLL1 0x34 -#define WM8960_PLL2 0x35 -#define WM8960_PLL3 0x36 -#define WM8960_PLL4 0x37 - -/*! @brief Cache register number */ -#define WM8960_CACHEREGNUM 56 - -/*! @brief WM8960_IFACE1 FORMAT bits */ -#define WM8960_IFACE1_FORMAT_MASK 0x03 -#define WM8960_IFACE1_FORMAT_SHIFT 0x00 -#define WM8960_IFACE1_FORMAT_RJ 0x00 -#define WM8960_IFACE1_FORMAT_LJ 0x01 -#define WM8960_IFACE1_FORMAT_I2S 0x02 -#define WM8960_IFACE1_FORMAT_DSP 0x03 -#define WM8960_IFACE1_FORMAT(x) ((x << WM8960_IFACE1_FORMAT_SHIFT) & WM8960_IFACE1_FORMAT_MASK) - -/*! @brief WM8960_IFACE1 WL bits */ -#define WM8960_IFACE1_WL_MASK 0x0C -#define WM8960_IFACE1_WL_SHIFT 0x02 -#define WM8960_IFACE1_WL_16BITS 0x00 -#define WM8960_IFACE1_WL_20BITS 0x01 -#define WM8960_IFACE1_WL_24BITS 0x02 -#define WM8960_IFACE1_WL_32BITS 0x03 -#define WM8960_IFACE1_WL(x) ((x << WM8960_IFACE1_WL_SHIFT) & WM8960_IFACE1_WL_MASK) - -/*! @brief WM8960_IFACE1 LRP bit */ -#define WM8960_IFACE1_LRP_MASK 0x10 -#define WM8960_IFACE1_LRP_SHIFT 0x04 -#define WM8960_IFACE1_LRCLK_NORMAL_POL 0x00 -#define WM8960_IFACE1_LRCLK_INVERT_POL 0x01 -#define WM8960_IFACE1_DSP_MODEA 0x00 -#define WM8960_IFACE1_DSP_MODEB 0x01 -#define WM8960_IFACE1_LRP(x) ((x << WM8960_IFACE1_LRP_SHIFT) & WM8960_IFACE1_LRP_MASK) - -/*! @brief WM8960_IFACE1 DLRSWAP bit */ -#define WM8960_IFACE1_DLRSWAP_MASK 0x20 -#define WM8960_IFACE1_DLRSWAP_SHIFT 0x05 -#define WM8960_IFACE1_DACCH_NORMAL 0x00 -#define WM8960_IFACE1_DACCH_SWAP 0x01 -#define WM8960_IFACE1_DLRSWAP(x) ((x << WM8960_IFACE1_DLRSWAP_SHIFT) & WM8960_IFACE1_DLRSWAP_MASK) - -/*! @brief WM8960_IFACE1 MS bit */ -#define WM8960_IFACE1_MS_MASK 0x40 -#define WM8960_IFACE1_MS_SHIFT 0x06 -#define WM8960_IFACE1_SLAVE 0x00 -#define WM8960_IFACE1_MASTER 0x01 -#define WM8960_IFACE1_MS(x) ((x << WM8960_IFACE1_MS_SHIFT) & WM8960_IFACE1_MS_MASK) - -/*! @brief WM8960_IFACE1 BCLKINV bit */ -#define WM8960_IFACE1_BCLKINV_MASK 0x80 -#define WM8960_IFACE1_BCLKINV_SHIFT 0x07 -#define WM8960_IFACE1_BCLK_NONINVERT 0x00 -#define WM8960_IFACE1_BCLK_INVERT 0x01 -#define WM8960_IFACE1_BCLKINV(x) ((x << WM8960_IFACE1_BCLKINV_SHIFT) & WM8960_IFACE1_BCLKINV_MASK) - -/*! @brief WM8960_IFACE1 ALRSWAP bit */ -#define WM8960_IFACE1_ALRSWAP_MASK 0x100 -#define WM8960_IFACE1_ALRSWAP_SHIFT 0x08 -#define WM8960_IFACE1_ADCCH_NORMAL 0x00 -#define WM8960_IFACE1_ADCCH_SWAP 0x01 -#define WM8960_IFACE1_ALRSWAP(x) ((x << WM8960_IFACE1_ALRSWAP_SHIFT) & WM8960_IFACE1_ALRSWAP_MASK) - -/*! @brief WM8960_POWER1 */ -#define WM8960_POWER1_VREF_MASK 0x40 -#define WM8960_POWER1_VREF_SHIFT 0x06 - -#define WM8960_POWER1_AINL_MASK 0x20 -#define WM8960_POWER1_AINL_SHIFT 0x05 - -#define WM8960_POWER1_AINR_MASK 0x10 -#define WM8960_POWER1_AINR_SHIFT 0x04 - -#define WM8960_POWER1_ADCL_MASK 0x08 -#define WM8960_POWER1_ADCL_SHIFT 0x03 - -#define WM8960_POWER1_ADCR_MASK 0x04 -#define WM8960_POWER1_ADCR_SHIFT 0x02 - -/*! @brief WM8960_POWER2 */ -#define WM8960_POWER2_DACL_MASK 0x100 -#define WM8960_POWER2_DACL_SHIFT 0x08 - -#define WM8960_POWER2_DACR_MASK 0x80 -#define WM8960_POWER2_DACR_SHIFT 0x07 - -#define WM8960_POWER2_LOUT1_MASK 0x40 -#define WM8960_POWER2_LOUT1_SHIFT 0x06 - -#define WM8960_POWER2_ROUT1_MASK 0x20 -#define WM8960_POWER2_ROUT1_SHIFT 0x05 - -#define WM8960_POWER2_SPKL_MASK 0x10 -#define WM8960_POWER2_SPKL_SHIFT 0x04 - -#define WM8960_POWER2_SPKR_MASK 0x08 -#define WM8960_POWER2_SPKR_SHIFT 0x03 - -/*! @brief WM8960 I2C address. */ -#define WM8960_I2C_ADDR 0x1A - -/*! @brief Modules in WM8960 board. */ -typedef enum _WM8960_module -{ - kWM8960_ModuleADC = 0x0, /*!< ADC module in WM8960 */ - kWM8960_ModuleDAC = 0x1, /*!< DAC module in WM8960 */ - kWM8960_ModuleVREF = 0x2, /*!< VREF module */ - kWM8960_ModuleHP = 0x03, /*!< Headphone module */ - kWM8960_ModuleLineIn = 0x6, /*!< Line-in module */ - kWM8960_ModuleLineOut = 0x7, /*!< Line out module */ - kWM8960_ModuleSpeaker = 0x8 /*!< Speaker module */ -} wm8960_module_t; - -/*! -* @brief WM8960 data route. -* Only provide some typical data route, not all route listed. -* Note: Users cannot combine any routes, once a new route is set, the previous one would be replaced. -*/ -typedef enum _wm8960_route -{ - kWM8960_RouteBypass = 0x0, /*!< LINEIN->Headphone. */ - kWM8960_RoutePlayback = 0x1, /*!< I2SIN->DAC->Headphone. */ - kWM8960_RoutePlaybackandRecord = 0x2, /*!< I2SIN->DAC->Headphone, LINEIN->ADC->I2SOUT. */ - kWM8960_RoutePlaybackwithDAP = 0x3, /*!< I2SIN->DAP->DAC->Headphone. */ - kWM8960_RoutePlaybackwithDAPandRecord = 0x4, /*!< I2SIN->DAP->DAC->HP, LINEIN->ADC->I2SOUT. */ - kWM8960_RouteRecord = 0x5 /*!< LINEIN->ADC->I2SOUT. */ -} wm8960_route_t; - -/*! -* @brief The audio data transfer protocol choice. -* WM8960 only supports I2S format and PCM format. -*/ -typedef enum _wm8960_protocol -{ - kWM8960_BusI2S = 0x0, /*!< I2S type */ - kWM8960_BusLeftJustified = 0x1, /*!< Left justified mode */ - kWM8960_BusRightJustified = 0x2, /*!< Right justified mode */ - kWM8960_BusPCMA = 0x3, /*!< PCM A mode */ - kWM8960_BusPCMB = 0x4 /*!< PCM B mode */ -} wm8960_protocol_t; - -/*! @brief WM8960 configure definition. */ -typedef struct wm8960_handle -{ -#if defined(FSL_FEATURE_SOC_LPI2C_COUNT) && (FSL_FEATURE_SOC_LPI2C_COUNT) - LPI2C_Type *base; - lpi2c_master_transfer_t xfer; - lpi2c_master_handle_t *i2cHandle; -#else - /* I2C relevant definition. */ - I2C_Type *base; /*!< I2C instance. */ - i2c_master_transfer_t xfer; /*!< I2C device setting */ - i2c_master_handle_t *i2cHandle; /*!< I2C internal state space. */ -#endif -} wm8960_handle_t; - -/*! @brief Initialize structure of WM8960 */ -typedef struct wm8960_config -{ - wm8960_route_t route; /*!< Audio data route.*/ - wm8960_protocol_t bus; /*!< Audio transfer protocol */ - bool master_slave; /*!< Master or slave. */ -} wm8960_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief WM8960 initialize function. - * - * The second parameter is NULL to WM8960 in this version. If users want - * to change the settings, they have to use wm8960_write_reg() or wm8960_modify_reg() - * to set the register value of WM8960. - * Note: If the codec_config is NULL, it would initialize WM8960 using default settings. - * The default setting: - * codec_config->route = kWM8960_RoutePlaybackandRecord - * codec_config->bus = kWM8960_BusI2S - * codec_config->master = slave - * - * @param handle WM8960 handle structure. - * @param codec_config WM8960 configuration structure. - */ -void WM8960_Init(wm8960_handle_t *handle, wm8960_config_t *config); - -/*! - * @brief Deinit the WM8960 codec. - * - * This function close all modules in WM8960 to save power. - * - * @param handle WM8960 handle structure pointer. - */ -void WM8960_Deinit(wm8960_handle_t *handle); - -/*! - * @brief Set audio data route in WM8960. - * - * This function would set the data route according to route. The route cannot be combined, - * as all route would enable different modules. - * Note: If a new route is set, the previous route would not work. - * - * @param handle WM8960 handle structure. - * @param route Audio data route in WM8960. - */ -status_t WM8960_SetDataRoute(wm8960_handle_t *handle, wm8960_route_t route); - -/*! - * @brief Set the audio transfer protocol. - * - * WM8960 only supports I2S, left justified, right justified, PCM A, PCM B format. - * - * @param handle WM8960 handle structure. - * @param bus Audio data transfer protocol. - */ -status_t WM8960_SetProtocol(wm8960_handle_t *handle, wm8960_protocol_t protocol); - -/*! - * @brief Set WM8960 as master or slave. - * - * @param handle WM8960 handle structure. - * @param master 1 represent master, 0 represent slave. - */ -void WM8960_SetMasterSlave(wm8960_handle_t *handle, bool master); - -/*! - * @brief Set the volume of different modules in WM8960. - * - * This function would set the volume of WM8960 modules. Uses need to appoint the module. - * The function assume that left channel and right channel has the same volume. - * - * @param handle WM8960 handle structure. - * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. - * @param volume Volume value need to be set. - */ -status_t WM8960_SetVolume(wm8960_handle_t *handle, wm8960_module_t module, uint32_t volume); - -/*! - * @brief Get the volume of different modules in WM8960. - * - * This function gets the volume of WM8960 modules. Uses need to appoint the module. - * The function assume that left channel and right channel has the same volume. - * - * @param handle WM8960 handle structure. - * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. - * @return Volume value of the module. - */ -uint32_t WM8960_GetVolume(wm8960_handle_t *handle, wm8960_module_t module); - -/*! - * @brief Mute modules in WM8960. - * - * @param handle WM8960 handle structure. - * @param module Modules need to be mute. - * @param isEnabled Mute or unmute, 1 represent mute. - */ -status_t WM8960_SetMute(wm8960_handle_t *handle, wm8960_module_t module, bool isEnabled); - -/*! - * @brief Enable/disable expected devices. - * - * @param handle WM8960 handle structure. - * @param module Module expected to enable. - * @param isEnabled Enable or disable moudles. - */ -status_t WM8960_SetModule(wm8960_handle_t *handle, wm8960_module_t module, bool isEnabled); - -/*! - * @brief Configure the data format of audio data. - * - * This function would configure the registers about the sample rate, bit depths. - * - * @param handle WM8960 handle structure pointer. - * @param mclk Master clock frequency of I2S. - * @param sample_rate Sample rate of audio file running in WM8960. WM8960 now - * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. - * @param bits Bit depth of audio file (WM8960 only supports 16bit, 20bit, 24bit - * and 32 bit in HW). - */ -status_t WM8960_ConfigDataFormat(wm8960_handle_t *handle, uint32_t mclk, uint32_t sample_rate, uint8_t bits); - -/*! - * @brief Enable/disable jack detect feature. - * - * @param handle WM8960 handle structure. - * @param isEnabled Enable or disable moudles. - */ -status_t WM8960_SetJackDetect(wm8960_handle_t *handle, bool isEnabled); - -/*! - * @brief Write register to WM8960 using I2C. - * - * @param handle WM8960 handle structure. - * @param reg The register address in WM8960. - * @param val Value needs to write into the register. - */ -status_t WM8960_WriteReg(wm8960_handle_t *handle, uint8_t reg, uint16_t val); - -/*! - * @brief Read register from WM8960 using I2C. - * @param handle WM8960 handle structure. - * @param reg The register address in WM8960. - * @param val Value written to. - */ -status_t WM8960_ReadReg(uint8_t reg, uint16_t *val); - -/*! - * @brief Modify some bits in the register using I2C. - * @param handle WM8960 handle structure. - * @param reg The register address in WM8960. - * @param mask The mask code for the bits want to write. The bit you want to write should be 0. - * @param val Value needs to write into the register. - */ -status_t WM8960_ModifyReg(wm8960_handle_t *handle, uint8_t reg, uint16_t mask, uint16_t val); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_WM8960_H_ */ - -/******************************************************************************* - * API - ******************************************************************************/ diff --git a/bsp/imxrt1052-evk/drivers/usb/device/usb_device.h b/bsp/imxrt1052-evk/drivers/usb/device/usb_device.h deleted file mode 100644 index 99e8a879f8..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/device/usb_device.h +++ /dev/null @@ -1,644 +0,0 @@ -/* - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FSL_USB_DEVICE_H__ -#define __FSL_USB_DEVICE_H__ - -/*! - * @addtogroup usb_device_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Defines Get/Set status Types */ -typedef enum _usb_device_status -{ - kUSB_DeviceStatusTestMode = 1U, /*!< Test mode */ - kUSB_DeviceStatusSpeed, /*!< Current speed */ - kUSB_DeviceStatusOtg, /*!< OTG status */ - kUSB_DeviceStatusDevice, /*!< Device status */ - kUSB_DeviceStatusEndpoint, /*!< Endpoint state usb_device_endpoint_status_t */ - kUSB_DeviceStatusDeviceState, /*!< Device state */ - kUSB_DeviceStatusAddress, /*!< Device address */ - kUSB_DeviceStatusSynchFrame, /*!< Current frame */ - kUSB_DeviceStatusBus, /*!< Bus status */ - kUSB_DeviceStatusBusSuspend, /*!< Bus suspend */ - kUSB_DeviceStatusBusSleep, /*!< Bus suspend */ - kUSB_DeviceStatusBusResume, /*!< Bus resume */ - kUSB_DeviceStatusRemoteWakeup, /*!< Remote wakeup state */ - kUSB_DeviceStatusBusSleepResume, /*!< Bus resume */ -} usb_device_status_t; - -/*! @brief Defines USB 2.0 device state */ -typedef enum _usb_device_state -{ - kUSB_DeviceStateConfigured = 0U, /*!< Device state, Configured*/ - kUSB_DeviceStateAddress, /*!< Device state, Address*/ - kUSB_DeviceStateDefault, /*!< Device state, Default*/ - kUSB_DeviceStateAddressing, /*!< Device state, Address setting*/ - kUSB_DeviceStateTestMode, /*!< Device state, Test mode*/ -} usb_device_state_t; - -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) -typedef enum _usb_dcd_detection_sequence_status -{ - kUSB_DcdDetectionNotEnabled = 0x0U, - kUSB_DcdDataPinDetectionCompleted = 0x01U, - kUSB_DcdChargingPortDetectionCompleted = 0x02U, - kUSB_DcdChargerTypeDetectionCompleted = 0x03U, -} usb_dcd_detection_sequence_status_t; - -typedef enum _usb_dcd_detection_sequence_results -{ - kUSB_DcdDetectionNoResults = 0x0U, - kUSB_DcdDetectionStandardHost = 0x01U, - kUSB_DcdDetectionChargingPort = 0x02U, - kUSB_DcdDetectionDedicatedCharger = 0x03U, -} usb_dcd_detection_sequence_results_t; -#endif - -/*! @brief Defines endpoint state */ -typedef enum _usb_endpoint_status -{ - kUSB_DeviceEndpointStateIdle = 0U, /*!< Endpoint state, idle*/ - kUSB_DeviceEndpointStateStalled, /*!< Endpoint state, stalled*/ -} usb_device_endpoint_status_t; - -/*! @brief Control endpoint index */ -#define USB_CONTROL_ENDPOINT (0U) -/*! @brief Control endpoint maxPacketSize */ -#define USB_CONTROL_MAX_PACKET_SIZE (64U) - -#if (USB_DEVICE_CONFIG_EHCI && (USB_CONTROL_MAX_PACKET_SIZE != (64U))) -#error For high speed, USB_CONTROL_MAX_PACKET_SIZE must be 64!!! -#endif - -/*! @brief The setup packet size of USB control transfer. */ -#define USB_SETUP_PACKET_SIZE (8U) -/*! @brief USB endpoint mask */ -#define USB_ENDPOINT_NUMBER_MASK (0x0FU) - -/*! @brief Default invalid value or the endpoint callback length of cancelled transfer */ -#define USB_UNINITIALIZED_VAL_32 (0xFFFFFFFFU) - -/*! @brief Available common EVENT types in device callback */ -typedef enum _usb_device_event -{ - kUSB_DeviceEventBusReset = 1U, /*!< USB bus reset signal detected */ - kUSB_DeviceEventSuspend, /*!< USB bus suspend signal detected */ - kUSB_DeviceEventResume, /*!< USB bus resume signal detected. The resume signal is driven by itself or a host */ - kUSB_DeviceEventSleeped, /*!< USB bus LPM suspend signal detected */ - kUSB_DeviceEventLPMResume, /*!< USB bus LPM resume signal detected. The resume signal is driven by itself or a host - */ - kUSB_DeviceEventError, /*!< An error is happened in the bus. */ - kUSB_DeviceEventDetach, /*!< USB device is disconnected from a host. */ - kUSB_DeviceEventAttach, /*!< USB device is connected to a host. */ - kUSB_DeviceEventSetConfiguration, /*!< Set configuration. */ - kUSB_DeviceEventSetInterface, /*!< Set interface. */ - - kUSB_DeviceEventGetDeviceDescriptor, /*!< Get device descriptor. */ - kUSB_DeviceEventGetConfigurationDescriptor, /*!< Get configuration descriptor. */ - kUSB_DeviceEventGetStringDescriptor, /*!< Get string descriptor. */ - kUSB_DeviceEventGetHidDescriptor, /*!< Get HID descriptor. */ - kUSB_DeviceEventGetHidReportDescriptor, /*!< Get HID report descriptor. */ - kUSB_DeviceEventGetHidPhysicalDescriptor, /*!< Get HID physical descriptor. */ - kUSB_DeviceEventGetBOSDescriptor, /*!< Get configuration descriptor. */ - kUSB_DeviceEventGetDeviceQualifierDescriptor, /*!< Get device qualifier descriptor. */ - kUSB_DeviceEventVendorRequest, /*!< Vendor request. */ - kUSB_DeviceEventSetRemoteWakeup, /*!< Enable or disable remote wakeup function. */ - kUSB_DeviceEventGetConfiguration, /*!< Get current configuration index */ - kUSB_DeviceEventGetInterface, /*!< Get current interface alternate setting value */ - kUSB_DeviceEventSetBHNPEnable, -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) - kUSB_DeviceEventDcdTimeOut, /*!< Dcd detect result is timeout */ - kUSB_DeviceEventDcdUnknownType, /*!< Dcd detect result is unknown type */ - kUSB_DeviceEventSDPDetected, /*!< The SDP facility is detected */ - kUSB_DeviceEventChargingPortDetected, /*!< The charging port is detected */ - kUSB_DeviceEventChargingHostDetected, /*!< The CDP facility is detected */ - kUSB_DeviceEventDedicatedChargerDetected, /*!< The DCP facility is detected */ -#endif -} usb_device_event_t; - -/*! @brief Endpoint callback message structure */ -typedef struct _usb_device_endpoint_callback_message_struct -{ - uint8_t *buffer; /*!< Transferred buffer */ - uint32_t length; /*!< Transferred data length */ - uint8_t isSetup; /*!< Is in a setup phase */ -} usb_device_endpoint_callback_message_struct_t; - -/*! - * @brief Endpoint callback function typedef. - * - * This callback function is used to notify the upper layer what the transfer result is. - * This callback pointer is passed when a specified endpoint is initialized by calling API #USB_DeviceInitEndpoint. - * - * @param handle The device handle. It equals to the value returned from #USB_DeviceInit. - * @param message The result of a transfer, which includes transfer buffer, transfer length, and whether is in a - * setup phase. - * phase for control pipe. - * @param callbackParam The parameter for this callback. It is same with - * usb_device_endpoint_callback_struct_t::callbackParam. - * - * @return A USB error code or kStatus_USB_Success. - */ -typedef usb_status_t (*usb_device_endpoint_callback_t)(usb_device_handle handle, - usb_device_endpoint_callback_message_struct_t *message, - void *callbackParam); - -/*! - * @brief Device callback function typedef. - * - * This callback function is used to notify the upper layer that the device status has changed. - * This callback pointer is passed by calling API #USB_DeviceInit. - * - * @param handle The device handle. It equals the value returned from #USB_DeviceInit. - * @param callbackEvent The callback event type. See enumeration #usb_device_event_t. - * @param eventParam The event parameter for this callback. The parameter type is determined by the callback event. - * - * @return A USB error code or kStatus_USB_Success. - */ -typedef usb_status_t (*usb_device_callback_t)(usb_device_handle handle, uint32_t callbackEvent, void *eventParam); - -/*! @brief Endpoint callback structure */ -typedef struct _usb_device_endpoint_callback_struct -{ - usb_device_endpoint_callback_t callbackFn; /*!< Endpoint callback function*/ - void *callbackParam; /*!< Parameter for callback function*/ - uint8_t isBusy; -} usb_device_endpoint_callback_struct_t; - -/*! @brief Endpoint initialization structure */ -typedef struct _usb_device_endpoint_init_struct -{ - uint16_t maxPacketSize; /*!< Endpoint maximum packet size */ - uint8_t endpointAddress; /*!< Endpoint address*/ - uint8_t transferType; /*!< Endpoint transfer type*/ - uint8_t zlt; /*!< ZLT flag*/ -} usb_device_endpoint_init_struct_t; - -/*! @brief Endpoint status structure */ -typedef struct _usb_device_endpoint_status_struct -{ - uint8_t endpointAddress; /*!< Endpoint address */ - uint16_t endpointStatus; /*!< Endpoint status : idle or stalled */ -} usb_device_endpoint_status_struct_t; - -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) -/*! @brief USB DCD charge timing specification structure */ -typedef struct _usb_device_dcd_charging_time -{ - uint16_t dcdSeqInitTime; /*!< The dcd sequence init time */ - uint16_t dcdDbncTime; /*!< The debounce time period on DP signal */ - uint16_t dcdDpSrcOnTime; /*!< The time period comparator enabled */ - uint16_t dcdTimeWaitAfterPrD; /*!< The time period between primary and secondary detection */ - uint8_t dcdTimeDMSrcOn; /*!< The amount of time that the modules enable the Vdm_src */ -} usb_device_dcd_charging_time_t; -#endif - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @name USB device APIs - * @{ - */ - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief Initializes the USB device stack. - * - * This function initializes the USB device module specified by the controllerId. - * - * @param[in] controllerId The controller ID of the USB IP. See the enumeration #usb_controller_index_t. - * @param[in] deviceCallback Function pointer of the device callback. - * @param[out] handle It is an out parameter used to return the pointer of the device handle to the caller. - * - * @retval kStatus_USB_Success The device is initialized successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. - * @retval kStatus_USB_Busy Cannot allocate a device handle. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id. - * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invalid. There is an empty - * interface entity. - * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than the IP's endpoint number. - * Or, the device has been initialized. - * Or, the mutex or message queue is created failed. - */ -extern usb_status_t USB_DeviceInit(uint8_t controllerId, - usb_device_callback_t deviceCallback, - usb_device_handle *handle); - -/*! - * @brief Enables the device functionality. - * - * The function enables the device functionality, so that the device can be recognized by the host when the device - * detects that it has been connected to a host. - * - * @param[in] handle The device handle got from #USB_DeviceInit. - * - * @retval kStatus_USB_Success The device is run successfully. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. - * - */ -extern usb_status_t USB_DeviceRun(usb_device_handle handle); - -/*! - * @brief Disables the device functionality. - * - * The function disables the device functionality. After this function called, even if the device is detached to the - * host, - * it can't work. - * - * @param[in] handle The device handle received from #USB_DeviceInit. - * - * @retval kStatus_USB_Success The device is stopped successfully. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. - */ -extern usb_status_t USB_DeviceStop(usb_device_handle handle); - -/*! - * @brief De-initializes the device controller. - * - * The function de-initializes the device controller specified by the handle. - * - * @param[in] handle The device handle got from #USB_DeviceInit. - * - * @retval kStatus_USB_Success The device is stopped successfully. - * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. - */ -extern usb_status_t USB_DeviceDeinit(usb_device_handle handle); - -/*! - * @brief Sends data through a specified endpoint. - * - * The function is used to send data through a specified endpoint. - * - * @param[in] handle The device handle got from #USB_DeviceInit. - * @param[in] endpointAddress Endpoint index. - * @param[in] buffer The memory address to hold the data need to be sent. The function is not reentrant. - * @param[in] length The data length need to be sent. - * - * @retval kStatus_USB_Success The send request is sent successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_Error The device is doing reset. - * - * @note The return value indicates whether the sending request is successful or not. The transfer done is notified by - * the - * corresponding callback function. - * Currently, only one transfer request can be supported for one specific endpoint. - * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application - * should implement a queue on the application level. - * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint - * callback). - */ -extern usb_status_t USB_DeviceSendRequest(usb_device_handle handle, - uint8_t endpointAddress, - uint8_t *buffer, - uint32_t length); - -/*! - * @brief Receives data through a specified endpoint. - * - * The function is used to receive data through a specified endpoint. The function is not reentrant. - * - * @param[in] handle The device handle got from #USB_DeviceInit. - * @param[in] endpointAddress Endpoint index. - * @param[in] buffer The memory address to save the received data. - * @param[in] length The data length want to be received. - * - * @retval kStatus_USB_Success The receive request is sent successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_Error The device is doing reset. - * - * @note The return value indicates whether the receiving request is successful or not. The transfer done is notified by - * the - * corresponding callback function. - * Currently, only one transfer request can be supported for one specific endpoint. - * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application - * should implement a queue on the application level. - * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint - * callback). - */ -extern usb_status_t USB_DeviceRecvRequest(usb_device_handle handle, - uint8_t endpointAddress, - uint8_t *buffer, - uint32_t length); - -/*! - * @brief Cancels the pending transfer in a specified endpoint. - * - * The function is used to cancel the pending transfer in a specified endpoint. - * - * @param[in] handle The device handle got from #USB_DeviceInit. - * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. - * - * @retval kStatus_USB_Success The transfer is cancelled. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer or the controller handle is invalid. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - */ -extern usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress); - -/*! - * @brief Initializes a specified endpoint. - * - * The function is used to initialize a specified endpoint. The corresponding endpoint callback is also initialized. - * - * @param[in] handle The device handle received from #USB_DeviceInit. - * @param[in] epInit Endpoint initialization structure. See the structure usb_device_endpoint_init_struct_t. - * @param[in] epCallback Endpoint callback structure. See the structure - * usb_device_endpoint_callback_struct_t. - * - * @retval kStatus_USB_Success The endpoint is initialized successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is - * more than USB_DEVICE_CONFIG_ENDPOINTS. - * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - */ -extern usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle, - usb_device_endpoint_init_struct_t *epInit, - usb_device_endpoint_callback_struct_t *epCallback); - -/*! - * @brief Deinitializes a specified endpoint. - * - * The function is used to deinitializes a specified endpoint. - * - * @param[in] handle The device handle got from #USB_DeviceInit. - * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. - * - * @retval kStatus_USB_Success The endpoint is de-initialized successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. - * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - */ -extern usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress); - -/*! - * @brief Stalls a specified endpoint. - * - * The function is used to stall a specified endpoint. - * - * @param[in] handle The device handle received from #USB_DeviceInit. - * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. - * - * @retval kStatus_USB_Success The endpoint is stalled successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - */ -extern usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress); - -/*! - * @brief Unstalls a specified endpoint. - * - * The function is used to unstall a specified endpoint. - * - * @param[in] handle The device handle received from #USB_DeviceInit. - * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. - * - * @retval kStatus_USB_Success The endpoint is unstalled successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - */ -extern usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress); - -/*! - * @brief Gets the status of the selected item. - * - * The function is used to get the status of the selected item. - * - * @param[in] handle The device handle got from #USB_DeviceInit. - * @param[in] type The selected item. See the structure #usb_device_status_t. - * @param[out] param The parameter type is determined by the selected item. - * - * @retval kStatus_USB_Success Get status successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_InvalidParameter The parameter is NULL pointer. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_Error Unsupported type. - */ -extern usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param); - -/*! - * @brief Sets the status of the selected item. - * - * The function is used to set the status of the selected item. - * - * @param[in] handle The device handle got from #USB_DeviceInit. - * @param[in] type The selected item. See the structure #usb_device_status_t. - * @param[in] param The parameter type is determined by the selected item. - * - * @retval kStatus_USB_Success Set status successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_Error Unsupported type or the parameter is NULL pointer. - */ -extern usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param); - -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) -/*! - * @brief Initializes the device dcd module. - * - * The function initializes the device dcd module. - * - * @param[in] handle The device handle got from #USB_DeviceInit. - * @param[in] time_param The time parameter used to config the dcd timing registers. - * - * @retval kStatus_USB_Success The device is run successfully. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. - * - */ -extern usb_status_t USB_DeviceDcdInitModule(usb_device_handle handle, void *time_param); - -/*! - * @brief De-initializes the device dcd module. - * - * The function de-initializes the device dcd module specified by the handle. - * - * @param[in] handle The device handle got from #USB_DeviceInit. - * - * @retval kStatus_USB_Success The device is stopped successfully. - * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. - */ -extern usb_status_t USB_DeviceDcdDeinitModule(usb_device_handle handle); -#endif -/*! - * @brief Device task function. - * - * The function is used to handle the controller message. - * This function should not be called in the application directly. - * - * @param[in] deviceHandle The device handle got from #USB_DeviceInit. - */ -extern void USB_DeviceTaskFunction(void *deviceHandle); - -#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) -/*! - * @brief Device KHCI task function. - * - * The function is used to handle the KHCI controller message. - * In the bare metal environment, this function should be called periodically in the main function. - * In the RTOS environment, this function should be used as a function entry to create a task. - * - * @param[in] deviceHandle The device handle got from #USB_DeviceInit. - */ -#define USB_DeviceKhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) -#endif - -#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) -/*! - * @brief Device EHCI task function. - * - * The function is used to handle the EHCI controller message. - * In the bare metal environment, this function should be called periodically in the main function. - * In the RTOS environment, this function should be used as a function entry to create a task. - * - * @param[in] deviceHandle The device handle got from #USB_DeviceInit. - */ -#define USB_DeviceEhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) -/*! - * @brief Device EHCI DCD ISR function. - * - * The function is the EHCI DCD interrupt service routine. - * - * @param[in] deviceHandle The device handle got from #USB_DeviceInit. - */ -extern void USB_DeviceDcdHSIsrFunction(void *deviceHandle); -#endif -#endif - -#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ - ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) -/*! - * @brief Device LPC ip3511 controller task function. - * - * The function is used to handle the LPC ip3511 controller message. - * In the bare metal environment, this function should be called periodically in the main function. - * In the RTOS environment, this function should be used as a function entry to create a task. - * - * @param[in] deviceHandle The device handle got from #USB_DeviceInit. - */ -#define USB_DeviceLpcIp3511TaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) -#endif - -#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) -/*! - * @brief Device KHCI ISR function. - * - * The function is the KHCI interrupt service routine. - * - * @param[in] deviceHandle The device handle got from #USB_DeviceInit. - */ -extern void USB_DeviceKhciIsrFunction(void *deviceHandle); -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) -/*! - * @brief Device KHCI DCD ISR function. - * - * The function is the KHCI DCD interrupt service routine. - * - * @param[in] deviceHandle The device handle got from #USB_DeviceInit. - */ -extern void USB_DeviceDcdIsrFunction(void *deviceHandle); -#endif -#endif - -#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) -/*! - * @brief Device EHCI ISR function. - * - * The function is the EHCI interrupt service routine. - * - * @param[in] deviceHandle The device handle got from #USB_DeviceInit. - */ -extern void USB_DeviceEhciIsrFunction(void *deviceHandle); -#endif - -#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ - ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) -/*! - * @brief Device LPC USB ISR function. - * - * The function is the LPC USB interrupt service routine. - * - * @param[in] deviceHandle The device handle got from #USB_DeviceInit. - */ -extern void USB_DeviceLpcIp3511IsrFunction(void *deviceHandle); -#endif - -/*! - * @brief Gets the device stack version function. - * - * The function is used to get the device stack version. - * - * @param[out] version The version structure pointer to keep the device stack version. - * - */ -extern void USB_DeviceGetVersion(uint32_t *version); - -#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) -/*! - * @brief Update the hardware tick. - * - * The function is used to update the hardware tick. - * - * @param[in] handle The device handle got from #USB_DeviceInit. - * @param[in] tick Current hardware tick(uint is ms). - * - */ -extern usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick); -#endif - -/*! @}*/ - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/*! @}*/ - -#endif /* __USB_DEVICE_H__ */ diff --git a/bsp/imxrt1052-evk/drivers/usb/device/usb_device_dci.c b/bsp/imxrt1052-evk/drivers/usb/device/usb_device_dci.c deleted file mode 100644 index dd28bdcbe3..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/device/usb_device_dci.c +++ /dev/null @@ -1,1459 +0,0 @@ -/* - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 - 2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -#include "usb_device.h" -#include "usb_device_dci.h" - -#include "fsl_device_registers.h" - -#if ((defined(USB_DEVICE_CONFIG_NUM)) && (USB_DEVICE_CONFIG_NUM > 0U)) - -#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) -#include "usb_device_khci.h" -#endif - -#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) -#include "usb_device_ehci.h" -#endif - -#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ - ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) -#include "usb_device_lpcip3511.h" -#endif - -#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) -#include "fsl_cache.h" -#endif -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -static usb_status_t USB_DeviceAllocateHandle(uint8_t controllerId, usb_device_struct_t **handle); -static usb_status_t USB_DeviceFreeHandle(usb_device_struct_t *handle); -static usb_status_t USB_DeviceGetControllerInterface( - uint8_t controllerId, const usb_device_controller_interface_struct_t **controllerInterface); -static usb_status_t USB_DeviceTransfer(usb_device_handle handle, - uint8_t endpointAddress, - uint8_t *buffer, - uint32_t length); -static usb_status_t USB_DeviceControl(usb_device_handle handle, usb_device_control_type_t type, void *param); -static usb_status_t USB_DeviceResetNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message); -#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) -static usb_status_t USB_DeviceSuspendNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message); -static usb_status_t USB_DeviceResumeNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message); -#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) -static usb_status_t USB_DeviceSleepNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message); - -#endif -#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ -#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U)) -static usb_status_t USB_DeviceDetachNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message); -static usb_status_t USB_DeviceAttachNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message); -#endif -static usb_status_t USB_DeviceNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -USB_GLOBAL static usb_device_struct_t s_UsbDevice[USB_DEVICE_CONFIG_NUM]; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * @brief Allocate a device handle. - * - * This function allocates a device handle. - * - * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t. - * @param handle It is out parameter, is used to return pointer of the device handle to the caller. - * - * @retval kStatus_USB_Success Get a device handle successfully. - * @retval kStatus_USB_Busy Cannot allocate a device handle. - * @retval kStatus_USB_Error The device has been initialized. - */ -static usb_status_t USB_DeviceAllocateHandle(uint8_t controllerId, usb_device_struct_t **handle) -{ - uint32_t count; - USB_OSA_SR_ALLOC(); - - USB_OSA_ENTER_CRITICAL(); - /* Check the controller is initialized or not. */ - for (count = 0U; count < USB_DEVICE_CONFIG_NUM; count++) - { - if ((NULL != s_UsbDevice[count].controllerHandle) && (controllerId == s_UsbDevice[count].controllerId)) - { - USB_OSA_EXIT_CRITICAL(); - return kStatus_USB_Error; - } - } - /* Get a free device handle. */ - for (count = 0U; count < USB_DEVICE_CONFIG_NUM; count++) - { - if (NULL == s_UsbDevice[count].controllerHandle) - { - s_UsbDevice[count].controllerId = controllerId; - *handle = &s_UsbDevice[count]; - USB_OSA_EXIT_CRITICAL(); - return kStatus_USB_Success; - } - } - USB_OSA_EXIT_CRITICAL(); - return kStatus_USB_Busy; -} - -/*! - * @brief Free a device handle. - * - * This function frees a device handle. - * - * @param handle The device handle. - * - * @retval kStatus_USB_Success Free device handle successfully. - */ -static usb_status_t USB_DeviceFreeHandle(usb_device_struct_t *handle) -{ - USB_OSA_SR_ALLOC(); - - USB_OSA_ENTER_CRITICAL(); - handle->controllerHandle = NULL; - handle->controllerId = 0U; - USB_OSA_EXIT_CRITICAL(); - return kStatus_USB_Success; -} - -#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) -/* KHCI device driver interface */ -static const usb_device_controller_interface_struct_t s_UsbDeviceKhciInterface = { - USB_DeviceKhciInit, USB_DeviceKhciDeinit, USB_DeviceKhciSend, - USB_DeviceKhciRecv, USB_DeviceKhciCancel, USB_DeviceKhciControl}; -#endif - -#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) -/* EHCI device driver interface */ -static const usb_device_controller_interface_struct_t s_UsbDeviceEhciInterface = { - USB_DeviceEhciInit, USB_DeviceEhciDeinit, USB_DeviceEhciSend, - USB_DeviceEhciRecv, USB_DeviceEhciCancel, USB_DeviceEhciControl}; -#endif - -#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ - ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) -/* EHCI device driver interface */ -static const usb_device_controller_interface_struct_t s_UsbDeviceLpc3511IpInterface = { - USB_DeviceLpc3511IpInit, USB_DeviceLpc3511IpDeinit, USB_DeviceLpc3511IpSend, - USB_DeviceLpc3511IpRecv, USB_DeviceLpc3511IpCancel, USB_DeviceLpc3511IpControl}; -#endif - -/*! - * @brief Get the controller interface handle. - * - * This function is used to get the controller interface handle. - * - * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t. - * @param controllerInterface It is out parameter, is used to return pointer of the device controller handle to the - * caller. - * - * @retval kStatus_USB_Success Get a device handle successfully. - * @retval kStatus_USB_ControllerNotFound The controller id is invalided. - */ -static usb_status_t USB_DeviceGetControllerInterface( - uint8_t controllerId, const usb_device_controller_interface_struct_t **controllerInterface) -{ - usb_status_t error = kStatus_USB_ControllerNotFound; - switch (controllerId) - { -#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) - /* Get the KHCI controller driver interface */ - case kUSB_ControllerKhci0: - case kUSB_ControllerKhci1: - *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceKhciInterface; - error = kStatus_USB_Success; - break; -#endif -#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) - /* Get the EHCI controller driver interface */ - case kUSB_ControllerEhci0: - case kUSB_ControllerEhci1: - error = kStatus_USB_Success; - *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceEhciInterface; - break; -#endif -#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ - ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) - /* Get the EHCI controller driver interface */ - case kUSB_ControllerLpcIp3511Fs0: - case kUSB_ControllerLpcIp3511Fs1: - case kUSB_ControllerLpcIp3511Hs0: - case kUSB_ControllerLpcIp3511Hs1: - error = kStatus_USB_Success; - *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceLpc3511IpInterface; - break; -#endif - default: - break; - } - return error; -} - -/*! - * @brief Start a new transfer. - * - * This function is used to start a new transfer. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param endpointAddress Endpoint address. Bit7 is direction, 0U - USB_OUT, 1U - USB_IN. - * @param buffer The memory address to be transferred, or the memory address to hold the data need to be - * sent. - * @param length The length of the data. - * - * @retval kStatus_USB_Success Get a device handle successfully. - * @retval kStatus_USB_InvalidHandle The device handle is invalided. - * @retval kStatus_USB_ControllerNotFound The controller interface is not found. - * @retval kStatus_USB_Error The device is doing reset. - */ -static usb_status_t USB_DeviceTransfer(usb_device_handle handle, - uint8_t endpointAddress, - uint8_t *buffer, - uint32_t length) -{ - usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; - usb_status_t error = kStatus_USB_Error; - uint8_t endpoint = endpointAddress & USB_ENDPOINT_NUMBER_MASK; - uint8_t direction = (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> - USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; - USB_OSA_SR_ALLOC(); - - if (NULL == deviceHandle) - { - return kStatus_USB_InvalidHandle; - } - - if (NULL != deviceHandle->controllerInterface) - { - if (deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy) - { - return kStatus_USB_Busy; - } - USB_OSA_ENTER_CRITICAL(); - deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 1U; - USB_OSA_EXIT_CRITICAL(); - if (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) - { -#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - if (length) - { - DCACHE_CleanByRange((uint32_t)buffer, length); - } -#endif - /* Call the controller send interface. */ - error = deviceHandle->controllerInterface->deviceSend(deviceHandle->controllerHandle, endpointAddress, - buffer, length); - } - else - { -#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - if (length) - { - DCACHE_CleanInvalidateByRange((uint32_t)buffer, length); - } -#endif - /* Call the controller receive interface. */ - error = deviceHandle->controllerInterface->deviceRecv(deviceHandle->controllerHandle, endpointAddress, - buffer, length); - } - if (kStatus_USB_Success != error) - { - USB_OSA_ENTER_CRITICAL(); - deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; - USB_OSA_EXIT_CRITICAL(); - } - } - else - { - error = kStatus_USB_ControllerNotFound; - } - return error; -} - -/*! - * @brief Control the status of the selected item. - * - * This function is used to control the status of the selected item.. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param type The control type, please refer to the enumeration usb_device_control_type_t. - * @param param The param type is determined by the selected item. - * - * @retval kStatus_USB_Success Get a device handle successfully. - * @retval kStatus_USB_InvalidHandle The device handle is invalided. - * @retval kStatus_USB_ControllerNotFound The controller interface is not found. - * @retval kStatus_USB_Error Unsupport type. - * Or, the param is NULL pointer. - */ -static usb_status_t USB_DeviceControl(usb_device_handle handle, usb_device_control_type_t type, void *param) -{ - usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; - usb_status_t error = kStatus_USB_Error; - - if (NULL == deviceHandle) - { - return kStatus_USB_InvalidHandle; - } - - if (NULL != deviceHandle->controllerInterface) - { - /* Call the controller control interface. */ - error = deviceHandle->controllerInterface->deviceControl(deviceHandle->controllerHandle, type, param); - } - else - { - error = kStatus_USB_ControllerNotFound; - } - return error; -} - -/*! - * @brief Handle the reset notification. - * - * This function is used to handle the reset notification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @retval kStatus_USB_Success Get a device handle successfully. - */ -static usb_status_t USB_DeviceResetNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message) -{ -#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) - USB_OSA_SR_ALLOC(); -#endif - - handle->isResetting = 1U; - -#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) - /* Clear remote wakeup feature */ - handle->remotewakeup = 0U; -#endif - -#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) - USB_OSA_ENTER_CRITICAL(); - handle->epCallbackDirectly = 1; - USB_OSA_EXIT_CRITICAL(); -#endif - /* Set the controller to default status. */ - USB_DeviceControl(handle, kUSB_DeviceControlSetDefaultStatus, NULL); -#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) - USB_OSA_ENTER_CRITICAL(); - handle->epCallbackDirectly = 0; - USB_OSA_EXIT_CRITICAL(); -#endif - - handle->state = kUSB_DeviceStateDefault; - handle->deviceAddress = 0U; - - for (uint32_t count = 0U; count < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); count++) - { - handle->epCallback[count].callbackFn = (usb_device_endpoint_callback_t)NULL; - handle->epCallback[count].callbackParam = NULL; - handle->epCallback[count].isBusy = 0U; - } - - /* Call device callback to notify the application that the USB bus reset signal detected. */ - handle->deviceCallback(handle, kUSB_DeviceEventBusReset, NULL); - - handle->isResetting = 0U; - return kStatus_USB_Success; -} - -#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) -/*! - * @brief Handle the suspend notification. - * - * This function is used to handle the suspend notification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceSuspendNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message) -{ - /* Call device callback to notify the application that the USB bus suspend signal detected. */ - return handle->deviceCallback(handle, kUSB_DeviceEventSuspend, NULL); -} - -/*! - * @brief Handle the resume notification. - * - * This function is used to handle the resume notification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceResumeNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message) -{ - /* Call device callback to notify the application that the USB bus resume signal detected. */ - return handle->deviceCallback(handle, kUSB_DeviceEventResume, NULL); -} -#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) -/*! - * @brief Handle the suspend notification. - * - * This function is used to handle the suspend notification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceSleepNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message) -{ - /* Call device callback to notify the application that the USB bus suspend signal detected. */ - return handle->deviceCallback(handle, kUSB_DeviceEventSleeped, NULL); -} -#endif -/*! - * @brief Handle the remotewakeup notification. - * - * This function is used to handle the remotewakeup notification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param flag The buffer pointer to store remotewakeup flag. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceGetRemoteWakeUp(usb_device_struct_t *handle, uint8_t **flag) -{ - /* Call device callback to notify the application that the USB bus suspend signal detected. */ - return USB_DeviceControl(handle, kUSB_DeviceControlGetRemoteWakeUp, flag); -} - -#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ - -#if (defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U)) -usb_status_t USB_DeviceErrorNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message) -{ - /* Call device callback to notify the application that the USB bus error signal detected. */ - return handle->deviceCallback(handle, kUSB_DeviceEventError, NULL); -} -#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */ - -#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U)) -/*! - * @brief Handle the detach notification. - * - * This function is used to handle the detach notification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceDetachNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message) -{ - /* Call device callback to notify the application that the device is disconnected from a host. */ - return handle->deviceCallback(handle, kUSB_DeviceEventDetach, NULL); -} - -/*! - * @brief Handle the attach notification. - * - * This function is used to handle the attach notification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceAttachNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message) -{ - /* Call device callback to notify the application that the device is connected to a host. */ - return handle->deviceCallback(handle, kUSB_DeviceEventAttach, NULL); -} -#endif - -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ - ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) -/*! - * @brief Handle the dcd module timeout notification. - * - * This function is used to handle the dcd module timeout notification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceDcdTimeOutNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message) -{ - /* Call device callback to notify the application that the device charger detect timeout happened. */ - return handle->deviceCallback(handle, kUSB_DeviceEventDcdTimeOut, NULL); -} - -/*! - * @brief Handle the dcd module unknown port type notification. - * - * This function is used to handle the dcd module unknown port type notification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceDcdUnknownPortTypeNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message) -{ - /* Call device callback to notify the application that the device charger detect unknown port type happened. */ - return handle->deviceCallback(handle, kUSB_DeviceEventDcdUnknownType, NULL); -} - -/*! - * @brief Handle the SDP facility is detected notification. - * - * This function is used to handle the SDP facility is detectednotification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceDcdSDPDetectNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message) -{ - /* Call device callback to notify the application that the SDP facility is detected. */ - return handle->deviceCallback(handle, kUSB_DeviceEventSDPDetected, NULL); -} - -/*! - * @brief Handle the charging port is detected notification. - * - * This function is used to handle the charging port is detectednotification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceDcdChargingPortDetectNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message) -{ - /* Call device callback to notify the application that the charing port is detected. */ - return handle->deviceCallback(handle, kUSB_DeviceEventChargingPortDetected, NULL); -} - -/*! - * @brief Handle the CDP facility is detected notification. - * - * This function is used to handle the CDP facility is detectednotification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceDcdChargingHostDetectNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message) -{ - /* Call device callback to notify the application that the CDP facility is detected. */ - return handle->deviceCallback(handle, kUSB_DeviceEventChargingHostDetected, NULL); -} - -/*! - * @brief Handle the DCP facility is detected notification. - * - * This function is used to handle the DCP facility is detectednotification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @return A USB error code or kStatus_USB_Success. - */ - -static usb_status_t USB_DeviceDcdDedicatedChargerDetectNotification(usb_device_struct_t *handle, - usb_device_callback_message_struct_t *message) -{ - /* Call device callback to notify the application that the DCP facility is detected. */ - return handle->deviceCallback(handle, kUSB_DeviceEventDedicatedChargerDetected, NULL); -} -#endif - -/*! - * @brief Handle the attach notification. - * - * This function is used to handle the attach notification. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message) -{ - uint8_t endpoint = message->code & USB_ENDPOINT_NUMBER_MASK; - uint8_t direction = (message->code & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> - USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; - usb_status_t error = kStatus_USB_Error; - - switch (message->code) - { - case kUSB_DeviceNotifyBusReset: - error = USB_DeviceResetNotification(handle, message); - break; -#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) - case kUSB_DeviceNotifySuspend: - error = USB_DeviceSuspendNotification(handle, message); - break; - case kUSB_DeviceNotifyResume: - error = USB_DeviceResumeNotification(handle, message); - break; -#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) - case kUSB_DeviceNotifyLPMSleep: - error = USB_DeviceSleepNotification(handle, message); - break; -#endif -#endif - -#if (defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U)) - case kUSB_DeviceNotifyError: - error = USB_DeviceErrorNotification(handle, message); - break; -#endif - -#if USB_DEVICE_CONFIG_DETACH_ENABLE - case kUSB_DeviceNotifyDetach: - error = USB_DeviceDetachNotification(handle, message); - break; - case kUSB_DeviceNotifyAttach: - error = USB_DeviceAttachNotification(handle, message); - break; -#endif -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ - ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) - case kUSB_DeviceNotifyDcdTimeOut: - error = USB_DeviceDcdTimeOutNotification(handle, message); - break; - case kUSB_DeviceNotifyDcdUnknownPortType: - error = USB_DeviceDcdUnknownPortTypeNotification(handle, message); - break; - case kUSB_DeviceNotifySDPDetected: - error = USB_DeviceDcdSDPDetectNotification(handle, message); - break; - case kUSB_DeviceNotifyChargingPortDetected: - error = USB_DeviceDcdChargingPortDetectNotification(handle, message); - break; - case kUSB_DeviceNotifyChargingHostDetected: - error = USB_DeviceDcdChargingHostDetectNotification(handle, message); - break; - case kUSB_DeviceNotifyDedicatedChargerDetected: - error = USB_DeviceDcdDedicatedChargerDetectNotification(handle, message); - break; -#endif - - default: - if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS) - { - if (handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn) - { - usb_device_endpoint_callback_message_struct_t endpointCallbackMessage; - endpointCallbackMessage.buffer = message->buffer; - endpointCallbackMessage.length = message->length; - endpointCallbackMessage.isSetup = message->isSetup; - if (message->isSetup) - { - handle->epCallback[0].isBusy = 0U; - handle->epCallback[1].isBusy = 0U; - } - else - { - handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; - } - /* Call endpoint callback */ - error = handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn( - handle, &endpointCallbackMessage, - handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam); - } - } - break; - } - return error; -} - -/*! - * @brief Notify the device that the controller status changed. - * - * This function is used to notify the device that the controller status changed. - * - * @param handle The device handle. It equals the value returned from USB_DeviceInit. - * @param message The device callback message handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg) -{ - usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; - usb_device_callback_message_struct_t *message = (usb_device_callback_message_struct_t *)msg; - - if ((NULL == msg) || (NULL == handle)) - { - return kStatus_USB_InvalidHandle; - } - - /* The device callback is invalid or not. */ - if (!deviceHandle->deviceCallback) - { - return kStatus_USB_Error; - } - -#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) - if (deviceHandle->epCallbackDirectly) - { - if ((message->code & USB_ENDPOINT_NUMBER_MASK) && (!(message->code & 0x70U))) - { - return USB_DeviceNotification(deviceHandle, message); - } - } - - /* Add the message to message queue when the device task is enabled. */ - if (kStatus_USB_OSA_Success != USB_OsaMsgqSend(deviceHandle->notificationQueue, (void *)message)) - { - return kStatus_USB_Busy; - } - return kStatus_USB_Success; -#else - /* Handle the notification by calling USB_DeviceNotification. */ - return USB_DeviceNotification(deviceHandle, message); -#endif -} - -/*! - * @brief Initialize the USB device stack. - * - * This function initializes the USB device module specified by the controllerId. - * - * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t. - * @param deviceCallback Function pointer of the device callback. - * @param handle It is out parameter, is used to return pointer of the device handle to the caller. - * - * @retval kStatus_USB_Success The device is initialized successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. - * @retval kStatus_USB_Busy Cannot allocate a device handle. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id. - * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invaild, There is an empty - * interface entity. - * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than IP's endpoint number. - * Or, the device has been initialized. - * Or, the message queue is created failed. - */ -usb_status_t USB_DeviceInit(uint8_t controllerId, usb_device_callback_t deviceCallback, usb_device_handle *handle) -{ - usb_device_struct_t *deviceHandle = NULL; - usb_status_t error; - uint32_t count; - - if (NULL == handle) - { - return kStatus_USB_InvalidHandle; - } - - /* Allocate a device handle by using the controller id. */ - error = USB_DeviceAllocateHandle(controllerId, &deviceHandle); - - if (kStatus_USB_Success != error) - { - return error; - } - - /* Save the device callback */ - deviceHandle->deviceCallback = deviceCallback; - /* Save the controller id */ - deviceHandle->controllerId = controllerId; - /* Clear the device address */ - deviceHandle->deviceAddress = 0U; - /* Clear the device reset state */ - deviceHandle->isResetting = 0U; - - /* Initialize the enpoints */ - for (count = 0U; count < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); count++) - { - deviceHandle->epCallback[count].callbackFn = (usb_device_endpoint_callback_t)NULL; - deviceHandle->epCallback[count].callbackParam = NULL; - deviceHandle->epCallback[count].isBusy = 0U; - } - - /* Get the controller interface according to the controller id */ - error = USB_DeviceGetControllerInterface(controllerId, &deviceHandle->controllerInterface); - if (kStatus_USB_Success != error) - { - USB_DeviceFreeHandle(deviceHandle); - return error; - } - if (NULL == deviceHandle->controllerInterface) - { - USB_DeviceFreeHandle(deviceHandle); - return kStatus_USB_ControllerNotFound; - } - if (((usb_device_controller_init_t)NULL == deviceHandle->controllerInterface->deviceInit) || - ((usb_device_controller_deinit_t)NULL == deviceHandle->controllerInterface->deviceDeinit) || - ((usb_device_controller_send_t)NULL == deviceHandle->controllerInterface->deviceSend) || - ((usb_device_controller_recv_t)NULL == deviceHandle->controllerInterface->deviceRecv) || - ((usb_device_controller_cancel_t)NULL == deviceHandle->controllerInterface->deviceCancel) || - ((usb_device_controller_control_t)NULL == deviceHandle->controllerInterface->deviceControl)) - { - USB_DeviceFreeHandle(deviceHandle); - return kStatus_USB_InvalidControllerInterface; - } - -#if USB_DEVICE_CONFIG_USE_TASK - /* Create a message queue when the device handle is enabled. */ - if (kStatus_USB_OSA_Success != - USB_OsaMsgqCreate(&deviceHandle->notificationQueue, USB_DEVICE_CONFIG_MAX_MESSAGES, - (1U + (sizeof(usb_device_callback_message_struct_t) - 1U) / sizeof(uint32_t)))) - { - USB_DeviceDeinit(deviceHandle); - return kStatus_USB_Error; - } -#endif - - *handle = deviceHandle; - - /* Initialize the controller */ - error = deviceHandle->controllerInterface->deviceInit(controllerId, deviceHandle, &deviceHandle->controllerHandle); - if (kStatus_USB_Success != error) - { - USB_DeviceDeinit(deviceHandle); - *handle = NULL; - return error; - } - /* Set the device to deafult state */ - deviceHandle->state = kUSB_DeviceStateDefault; - - return error; -} - -/*! - * @brief Enable the device functionality. - * - * The function enables the device functionality, so that the device can be recognized by the host when the device - * detects that it has been connected to a host. - * - * @param handle The device handle got from USB_DeviceInit. - * - * @retval kStatus_USB_Success The device is run successfully. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. - * - */ -usb_status_t USB_DeviceRun(usb_device_handle handle) -{ - return USB_DeviceControl(handle, kUSB_DeviceControlRun, NULL); -} -/*! - * @brief Disable the device functionality. - * - * The function disables the device functionality, after this function called, even the device is detached to the host, - * and the device can't work. - * - * @param handle The device handle got from USB_DeviceInit. - * - * @retval kStatus_USB_Success The device is stopped successfully. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. - */ -usb_status_t USB_DeviceStop(usb_device_handle handle) -{ - return USB_DeviceControl(handle, kUSB_DeviceControlStop, NULL); -} -/*! - * @brief De-initialize the device controller. - * - * The function de-initializes the device controller specified by the handle. - * - * @param handle The device handle got from USB_DeviceInit. - * - * @retval kStatus_USB_Success The device is stopped successfully. - * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. - */ -usb_status_t USB_DeviceDeinit(usb_device_handle handle) -{ - usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; - - if (NULL == deviceHandle) - { - return kStatus_USB_InvalidHandle; - } - /* De-initialize the controller */ - if (NULL != deviceHandle->controllerInterface) - { - deviceHandle->controllerInterface->deviceDeinit(deviceHandle->controllerHandle); - deviceHandle->controllerInterface = (usb_device_controller_interface_struct_t *)NULL; - } - -#if USB_DEVICE_CONFIG_USE_TASK - /* Destroy the message queue. */ - if (NULL != deviceHandle->notificationQueue) - { - USB_OsaMsgqDestroy(deviceHandle->notificationQueue); - deviceHandle->notificationQueue = NULL; - } -#endif - - /* Free the device handle. */ - USB_DeviceFreeHandle(deviceHandle); - return kStatus_USB_Success; -} - -/*! - * @brief Send data through a specified endpoint. - * - * The function is used to send data through a specified endpoint. - * - * @param handle The device handle got from USB_DeviceInit. - * @param endpointAddress Endpoint index. - * @param buffer The memory address to hold the data need to be sent. - * @param length The data length need to be sent. - * - * @retval kStatus_USB_Success The send request is sent successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_Busy Cannot allocate dtds for current tansfer in EHCI driver. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_Error The device is doing reset. - * - * @note The return value just means if the sending request is successful or not; the transfer done is notified by the - * corresponding callback function. - * Currently, only one transfer request can be supported for one specific endpoint. - * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application - * should implement a queue in the application level. - * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint - * callback). - */ -usb_status_t USB_DeviceSendRequest(usb_device_handle handle, uint8_t endpointAddress, uint8_t *buffer, uint32_t length) -{ - return USB_DeviceTransfer(handle, (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | - (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), - buffer, length); -} - -/*! - * @brief Receive data through a specified endpoint. - * - * The function is used to receive data through a specified endpoint. - * - * @param handle The device handle got from USB_DeviceInit. - * @param endpointAddress Endpoint index. - * @param buffer The memory address to save the received data. - * @param length The data length want to be received. - * - * @retval kStatus_USB_Success The receive request is sent successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_Busy Cannot allocate dtds for current tansfer in EHCI driver. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_Error The device is doing reset. - * - * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the - * corresponding callback function. - * Currently, only one transfer request can be supported for one specific endpoint. - * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application - * should implement a queue in the application level. - * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint - * callback). - */ -usb_status_t USB_DeviceRecvRequest(usb_device_handle handle, uint8_t endpointAddress, uint8_t *buffer, uint32_t length) -{ - return USB_DeviceTransfer(handle, (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | - (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), - buffer, length); -} - -/*! - * @brief Cancel the pending transfer in a specified endpoint. - * - * The function is used to cancel the pending transfer in a specified endpoint. - * - * @param handle The device handle got from USB_DeviceInit. - * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. - * - * @retval kStatus_USB_Success The transfer is cancelled. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - */ -usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress) -{ - usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; - usb_status_t error = kStatus_USB_Error; - - if (NULL == deviceHandle) - { - return kStatus_USB_InvalidHandle; - } - - if (NULL != deviceHandle->controllerInterface) - { - error = deviceHandle->controllerInterface->deviceCancel(deviceHandle->controllerHandle, endpointAddress); - } - else - { - error = kStatus_USB_ControllerNotFound; - } - return error; -} - -/*! - * @brief Initialize a specified endpoint. - * - * The function is used to initialize a specified endpoint and the corresponding endpoint callback is also initialized. - * - * @param handle The device handle got from USB_DeviceInit. - * @param epInit Endpoint initizlization structure. Please refer to the structure usb_device_endpoint_init_struct_t. - * @param epCallback Endpoint callback structure. Please refer to the structure - * usb_device_endpoint_callback_struct_t. - * - * @retval kStatus_USB_Success The endpoint is initialized successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is - * more than USB_DEVICE_CONFIG_ENDPOINTS. - * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - */ -usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle, - usb_device_endpoint_init_struct_t *epInit, - usb_device_endpoint_callback_struct_t *epCallback) -{ - usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; - uint8_t endpoint; - uint8_t direction; - - if (!deviceHandle) - { - return kStatus_USB_InvalidHandle; - } - - if ((!epInit) || (!epCallback)) - { - return kStatus_USB_InvalidParameter; - } - - endpoint = epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK; - direction = (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> - USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; - - if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS) - { - deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn = epCallback->callbackFn; - deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam = - epCallback->callbackParam; - deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; - } - else - { - return kStatus_USB_InvalidParameter; - } - return USB_DeviceControl(handle, kUSB_DeviceControlEndpointInit, epInit); -} - -/*! - * @brief De-initizlize a specified endpoint. - * - * The function is used to de-initizlize a specified endpoint. - * - * @param handle The device handle got from USB_DeviceInit. - * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. - * - * @retval kStatus_USB_Success The endpoint is de-initialized successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. - * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - */ -usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress) -{ - usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; - uint8_t endpoint = endpointAddress & USB_ENDPOINT_NUMBER_MASK; - uint8_t direction = (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> - USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; - usb_status_t error = kStatus_USB_Error; -#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) - USB_OSA_SR_ALLOC(); -#endif - - if (!deviceHandle) - { - return kStatus_USB_InvalidHandle; - } -#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) - USB_OSA_ENTER_CRITICAL(); - deviceHandle->epCallbackDirectly = 1; - USB_OSA_EXIT_CRITICAL(); -#endif - error = USB_DeviceControl(handle, kUSB_DeviceControlEndpointDeinit, &endpointAddress); -#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) - USB_OSA_ENTER_CRITICAL(); - deviceHandle->epCallbackDirectly = 0; - USB_OSA_EXIT_CRITICAL(); -#endif - - if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS) - { - deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn = - (usb_device_endpoint_callback_t)NULL; - deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam = NULL; - deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; - } - else - { - return kStatus_USB_InvalidParameter; - } - return error; -} - -/*! - * @brief Stall a specified endpoint. - * - * The function is used to stall a specified endpoint. - * - * @param handle The device handle got from USB_DeviceInit. - * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. - * - * @retval kStatus_USB_Success The endpoint is stalled successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - */ -usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress) -{ - if ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) < USB_DEVICE_CONFIG_ENDPOINTS) - { - return USB_DeviceControl(handle, kUSB_DeviceControlEndpointStall, &endpointAddress); - } - else - { - return kStatus_USB_InvalidParameter; - } -} - -/*! - * @brief Un-stall a specified endpoint. - * - * The function is used to un-stall a specified endpoint. - * - * @param handle The device handle got from USB_DeviceInit. - * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. - * - * @retval kStatus_USB_Success The endpoint is un-stalled successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - */ -usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress) -{ - if ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) < USB_DEVICE_CONFIG_ENDPOINTS) - { - return USB_DeviceControl(handle, kUSB_DeviceControlEndpointUnstall, &endpointAddress); - } - else - { - return kStatus_USB_InvalidParameter; - } -} - -/*! - * @brief Get the status of the selected item. - * - * The function is used to get the status of the selected item. - * - * @param handle The device handle got from USB_DeviceInit. - * @param type The selected item. Please refer to the structure usb_device_status_t. - * @param param The param type is determined by the selected item. - * - * @retval kStatus_USB_Success Get status successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_InvalidParameter The param is NULL pointer. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_Error Unsupported type. - */ -usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param) -{ - uint8_t *temp8; - usb_status_t error = kStatus_USB_Error; - - if (NULL == param) - { - return kStatus_USB_InvalidParameter; - } - switch (type) - { - case kUSB_DeviceStatusSpeed: - error = USB_DeviceControl(handle, kUSB_DeviceControlGetSpeed, param); - break; - case kUSB_DeviceStatusOtg: - error = USB_DeviceControl(handle, kUSB_DeviceControlGetOtgStatus, param); - break; - case kUSB_DeviceStatusDeviceState: - temp8 = (uint8_t *)param; - error = kStatus_USB_Success; - *temp8 = ((usb_device_struct_t *)handle)->state; - break; - case kUSB_DeviceStatusAddress: - temp8 = (uint8_t *)param; - error = kStatus_USB_Success; - *temp8 = ((usb_device_struct_t *)handle)->deviceAddress; - break; - case kUSB_DeviceStatusDevice: - error = USB_DeviceControl(handle, kUSB_DeviceControlGetDeviceStatus, param); - break; - case kUSB_DeviceStatusEndpoint: - error = USB_DeviceControl(handle, kUSB_DeviceControlGetEndpointStatus, param); - break; - case kUSB_DeviceStatusSynchFrame: - error = USB_DeviceControl(handle, kUSB_DeviceControlGetSynchFrame, param); - break; -#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) - case kUSB_DeviceStatusRemoteWakeup: - temp8 = (uint8_t *)param; - error = kStatus_USB_Success; - *temp8 = ((usb_device_struct_t *)handle)->remotewakeup; - break; -#endif - default: - break; - } - return error; -} - -/*! - * @brief Set the status of the selected item. - * - * The function is used to set the status of the selected item. - * - * @param handle The device handle got from USB_DeviceInit. - * @param type The selected item. Please refer to the structure usb_device_status_t. - * @param param The param type is determined by the selected item. - * - * @retval kStatus_USB_Success Set status successfully. - * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_Error Unsupported type, or the param is NULL pointer. - */ -usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param) -{ - usb_status_t error = kStatus_USB_Error; - switch (type) - { -#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) || \ - (defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) && \ - (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U)) - case kUSB_DeviceStatusTestMode: - error = USB_DeviceControl(handle, kUSB_DeviceControlSetTestMode, param); - break; -#endif - case kUSB_DeviceStatusOtg: - error = USB_DeviceControl(handle, kUSB_DeviceControlSetOtgStatus, param); - break; - case kUSB_DeviceStatusDeviceState: - if (NULL != param) - { - error = kStatus_USB_Success; - ((usb_device_struct_t *)handle)->state = (uint8_t)(*(uint8_t *)param); - } - break; - case kUSB_DeviceStatusAddress: - if (kUSB_DeviceStateAddressing != ((usb_device_struct_t *)handle)->state) - { - if (NULL != param) - { - error = kStatus_USB_Success; - ((usb_device_struct_t *)handle)->deviceAddress = (uint8_t)(*(uint8_t *)param); - ((usb_device_struct_t *)handle)->state = kUSB_DeviceStateAddressing; - } - } - else - { - error = USB_DeviceControl(handle, kUSB_DeviceControlSetDeviceAddress, - &((usb_device_struct_t *)handle)->deviceAddress); - } - break; - case kUSB_DeviceStatusBusResume: - error = USB_DeviceControl(handle, kUSB_DeviceControlResume, param); - break; - case kUSB_DeviceStatusBusSleepResume: - error = USB_DeviceControl(handle, kUSB_DeviceControlSleepResume, param); - break; -#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) - case kUSB_DeviceStatusRemoteWakeup: - if (NULL != param) - { - error = kStatus_USB_Success; - ((usb_device_struct_t *)handle)->remotewakeup = (uint8_t)(*(uint8_t *)param); - } - break; -#endif - case kUSB_DeviceStatusBusSuspend: - error = USB_DeviceControl(handle, kUSB_DeviceControlSuspend, param); - break; - case kUSB_DeviceStatusBusSleep: - error = USB_DeviceControl(handle, kUSB_DeviceControlSleep, param); - break; - default: - break; - } - return error; -} - -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ - ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \ - (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) -/*! - * @brief Initializes the device dcd module. - * - * The function initializes the device dcd module. - * - * @param handle The device handle got from USB_DeviceInit. - * - * @retval kStatus_USB_Success The device is run successfully. - * @retval kStatus_USB_ControllerNotFound Cannot find the controller. - * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. - * - */ -usb_status_t USB_DeviceDcdInitModule(usb_device_handle handle, void *time_param) -{ - return USB_DeviceControl(handle, kUSB_DeviceControlDcdInitModule, time_param); -} - -/*! - * @brief De-initializes the device dcd module. - * - * The function de-intializes the device dcd module. - * - * @param handle The device handle got from USB_DeviceInit. - * - * @retval kStatus_USB_Success The device is run successfully. - * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. - * - */ -usb_status_t USB_DeviceDcdDeinitModule(usb_device_handle handle) -{ - return USB_DeviceControl(handle, kUSB_DeviceControlDcdDeinitModule, NULL); -} -#endif - -#if USB_DEVICE_CONFIG_USE_TASK -/*! - * @brief Device task function. - * - * The function is used to handle controller message. - * This function should not be called in applicartion directly. - * - * @param handle The device handle got from USB_DeviceInit. - */ -void USB_DeviceTaskFunction(void *deviceHandle) -{ - usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle; - static usb_device_callback_message_struct_t message; - - if (deviceHandle) - { - /* Get the message from the queue */ - if (kStatus_USB_OSA_Success == USB_OsaMsgqRecv(handle->notificationQueue, (uint32_t *)&message, 0U)) - { - /* Handle the message */ - USB_DeviceNotification(handle, &message); - } - } -} -#endif - -/*! - * @brief Get dvice stack version function. - * - * The function is used to get dvice stack version. - * - * @param[out] version The version structure pointer to keep the device stack version. - * - */ -void USB_DeviceGetVersion(uint32_t *version) -{ - if (version) - { - *version = - (uint32_t)USB_MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX); - } -} - -#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) -/*! - * @brief Update the hardware tick. - * - * The function is used to update the hardware tick. - * - * @param[in] handle The device handle got from #USB_DeviceInit. - * @param[in] tick Current hardware tick. - * - */ -usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick) -{ - usb_device_struct_t *deviceHandle; - usb_status_t status = kStatus_USB_Success; - - if (handle == NULL) - { - return kStatus_USB_InvalidHandle; - } - deviceHandle = (usb_device_struct_t *)handle; - - deviceHandle->hwTick = tick; - - return status; -} -#endif -#endif /* USB_DEVICE_CONFIG_NUM */ diff --git a/bsp/imxrt1052-evk/drivers/usb/device/usb_device_dci.h b/bsp/imxrt1052-evk/drivers/usb/device/usb_device_dci.h deleted file mode 100644 index fd4fdceb04..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/device/usb_device_dci.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __USB_DEVICE_DCI_H__ -#define __USB_DEVICE_DCI_H__ - -/*! - * @addtogroup usb_device_controller_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Macro to define controller handle */ -#define usb_device_controller_handle usb_device_handle - -/*! @brief Available notify types for device notification */ -typedef enum _usb_device_notification -{ - kUSB_DeviceNotifyBusReset = 0x10U, /*!< Reset signal detected */ - kUSB_DeviceNotifySuspend, /*!< Suspend signal detected */ - kUSB_DeviceNotifyResume, /*!< Resume signal detected */ - kUSB_DeviceNotifyLPMSleep, /*!< LPM signal detected */ - kUSB_DeviceNotifyLPMResume, /*!< Resume signal detected */ - kUSB_DeviceNotifyError, /*!< Errors happened in bus */ - kUSB_DeviceNotifyDetach, /*!< Device disconnected from a host */ - kUSB_DeviceNotifyAttach, /*!< Device connected to a host */ -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) - kUSB_DeviceNotifyDcdTimeOut, /*!< Device charger detection timeout */ - kUSB_DeviceNotifyDcdUnknownPortType, /*!< Device charger detection unknown port type */ - kUSB_DeviceNotifySDPDetected, /*!< The SDP facility is detected */ - kUSB_DeviceNotifyChargingPortDetected, /*!< The charging port is detected */ - kUSB_DeviceNotifyChargingHostDetected, /*!< The CDP facility is detected */ - kUSB_DeviceNotifyDedicatedChargerDetected, /*!< The DCP facility is detected */ -#endif -} usb_device_notification_t; - -/*! @brief Device notification message structure */ -typedef struct _usb_device_callback_message_struct -{ - uint8_t *buffer; /*!< Transferred buffer */ - uint32_t length; /*!< Transferred data length */ - uint8_t code; /*!< Notification code */ - uint8_t isSetup; /*!< Is in a setup phase */ -} usb_device_callback_message_struct_t; - -/*! @brief Control type for controller */ -typedef enum _usb_device_control_type -{ - kUSB_DeviceControlRun = 0U, /*!< Enable the device functionality */ - kUSB_DeviceControlStop, /*!< Disable the device functionality */ - kUSB_DeviceControlEndpointInit, /*!< Initialize a specified endpoint */ - kUSB_DeviceControlEndpointDeinit, /*!< De-initialize a specified endpoint */ - kUSB_DeviceControlEndpointStall, /*!< Stall a specified endpoint */ - kUSB_DeviceControlEndpointUnstall, /*!< Unstall a specified endpoint */ - kUSB_DeviceControlGetDeviceStatus, /*!< Get device status */ - kUSB_DeviceControlGetEndpointStatus, /*!< Get endpoint status */ - kUSB_DeviceControlSetDeviceAddress, /*!< Set device address */ - kUSB_DeviceControlGetSynchFrame, /*!< Get current frame */ - kUSB_DeviceControlResume, /*!< Drive controller to generate a resume signal in USB bus */ - kUSB_DeviceControlSleepResume, /*!< Drive controller to generate a LPM resume signal in USB bus */ - kUSB_DeviceControlSuspend, /*!< Drive controller to enetr into suspend mode */ - kUSB_DeviceControlSleep, /*!< Drive controller to enetr into sleep mode */ - kUSB_DeviceControlSetDefaultStatus, /*!< Set controller to default status */ - kUSB_DeviceControlGetSpeed, /*!< Get current speed */ - kUSB_DeviceControlGetOtgStatus, /*!< Get OTG status */ - kUSB_DeviceControlSetOtgStatus, /*!< Set OTG status */ - kUSB_DeviceControlSetTestMode, /*!< Drive xCHI into test mode */ - kUSB_DeviceControlGetRemoteWakeUp, /*!< Get flag of LPM Remote Wake-up Enabled by USB host. */ -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) - kUSB_DeviceControlDcdInitModule, - kUSB_DeviceControlDcdDeinitModule, -#endif -} usb_device_control_type_t; - -/*! @brief USB device controller initialization function typedef */ -typedef usb_status_t (*usb_device_controller_init_t)(uint8_t controllerId, - usb_device_handle handle, - usb_device_controller_handle *controllerHandle); - -/*! @brief USB device controller de-initialization function typedef */ -typedef usb_status_t (*usb_device_controller_deinit_t)(usb_device_controller_handle controllerHandle); - -/*! @brief USB device controller send data function typedef */ -typedef usb_status_t (*usb_device_controller_send_t)(usb_device_controller_handle controllerHandle, - uint8_t endpointAddress, - uint8_t *buffer, - uint32_t length); - -/*! @brief USB device controller receive data function typedef */ -typedef usb_status_t (*usb_device_controller_recv_t)(usb_device_controller_handle controllerHandle, - uint8_t endpointAddress, - uint8_t *buffer, - uint32_t length); - -/*! @brief USB device controller cancel transfer function in a specified endpoint typedef */ -typedef usb_status_t (*usb_device_controller_cancel_t)(usb_device_controller_handle controllerHandle, - uint8_t endpointAddress); - -/*! @brief USB device controller control function typedef */ -typedef usb_status_t (*usb_device_controller_control_t)(usb_device_controller_handle controllerHandle, - usb_device_control_type_t command, - void *param); - -/*! @brief USB device controller interface structure */ -typedef struct _usb_device_controller_interface_struct -{ - usb_device_controller_init_t deviceInit; /*!< Controller initialization */ - usb_device_controller_deinit_t deviceDeinit; /*!< Controller de-initialization */ - usb_device_controller_send_t deviceSend; /*!< Controller send data */ - usb_device_controller_recv_t deviceRecv; /*!< Controller receive data */ - usb_device_controller_cancel_t deviceCancel; /*!< Controller cancel transfer */ - usb_device_controller_control_t deviceControl; /*!< Controller control */ -} usb_device_controller_interface_struct_t; - -/*! @brief USB device status structure */ -typedef struct _usb_device_struct -{ -#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) - volatile uint64_t hwTick; /*!< Current hw tick(ms)*/ -#endif - usb_device_controller_handle controllerHandle; /*!< Controller handle */ - const usb_device_controller_interface_struct_t *controllerInterface; /*!< Controller interface handle */ -#if USB_DEVICE_CONFIG_USE_TASK - usb_osa_msgq_handle notificationQueue; /*!< Message queue */ -#endif - usb_device_callback_t deviceCallback; /*!< Device callback function pointer */ - usb_device_endpoint_callback_struct_t - epCallback[USB_DEVICE_CONFIG_ENDPOINTS << 1U]; /*!< Endpoint callback function structure */ - uint8_t deviceAddress; /*!< Current device address */ - uint8_t controllerId; /*!< Controller ID */ - uint8_t state; /*!< Current device state */ -#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) - uint8_t remotewakeup; /*!< Remote wakeup is enabled or not */ -#endif - uint8_t isResetting; /*!< Is doing device reset or not */ -#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) - uint8_t epCallbackDirectly; /*!< Whether call ep callback directly when the task is enabled */ -#endif -} usb_device_struct_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! @}*/ - -#endif /* __USB_DEVICE_DCI_H__ */ diff --git a/bsp/imxrt1052-evk/drivers/usb/device/usb_device_ehci.c b/bsp/imxrt1052-evk/drivers/usb/device/usb_device_ehci.c deleted file mode 100644 index 7bb202143d..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/device/usb_device_ehci.c +++ /dev/null @@ -1,1807 +0,0 @@ -/* - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 - 2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include "fsl_device_registers.h" -#include -#include "usb_device.h" -#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) - -#include "usb_device_dci.h" - -#include "usb_device_ehci.h" -#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) -#include "usb_phy.h" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM > 0U) - -#error The SOC does not suppoort dedicated RAM case. - -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -static void USB_DeviceEhciSetDefaultState(usb_device_ehci_state_struct_t *ehciState); -static usb_status_t USB_DeviceEhciEndpointInit(usb_device_ehci_state_struct_t *ehciState, - usb_device_endpoint_init_struct_t *epInit); -static usb_status_t USB_DeviceEhciEndpointDeinit(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); -static usb_status_t USB_DeviceEhciEndpointStall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); -static usb_status_t USB_DeviceEhciEndpointUnstall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); -static void USB_DeviceEhciFillSetupBuffer(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); -static void USB_DeviceEhciCancelControlPipe(usb_device_ehci_state_struct_t *ehciState, - uint8_t endpoint, - uint8_t direction); -static void USB_DeviceEhciInterruptTokenDone(usb_device_ehci_state_struct_t *ehciState); -static void USB_DeviceEhciInterruptPortChange(usb_device_ehci_state_struct_t *ehciState); -static void USB_DeviceEhciInterruptReset(usb_device_ehci_state_struct_t *ehciState); -static void USB_DeviceEhciInterruptSof(usb_device_ehci_state_struct_t *ehciState); -#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) -static void USB_DeviceEhciInterruptSuspend(usb_device_ehci_state_struct_t *ehciState); -#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ -static usb_status_t USB_DeviceEhciTransfer(usb_device_ehci_state_struct_t *ehciState, - uint8_t endpointAddress, - uint8_t *buffer, - uint32_t length); - -extern usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Apply for QH buffer, 2048-byte alignment */ -USB_RAM_ADDRESS_ALIGNMENT(2048) -USB_CONTROLLER_DATA static uint8_t qh_buffer[(USB_DEVICE_CONFIG_EHCI - 1) * 2048 + - USB_DEVICE_CONFIG_ENDPOINTS * 2 * sizeof(usb_device_ehci_qh_struct_t)]; - -/* Apply for DTD buffer, 32-byte alignment */ -USB_RAM_ADDRESS_ALIGNMENT(32) -USB_CONTROLLER_DATA static usb_device_ehci_dtd_struct_t - s_UsbDeviceEhciDtd[USB_DEVICE_CONFIG_EHCI][USB_DEVICE_CONFIG_EHCI_MAX_DTD]; - -/* Apply for ehci device state structure */ -static usb_device_ehci_state_struct_t g_UsbDeviceEhciSate[USB_DEVICE_CONFIG_EHCI]; - -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ - (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) -/* Apply for device dcd state structure */ -static usb_device_dcd_state_struct_t s_UsbDeviceDcdHSState[USB_DEVICE_CONFIG_EHCI]; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * @brief EHCI NC get USB NC bass address. - * - * This function is used to get USB NC bass address. - * - * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. - * - * @retval USB NC bass address. - */ -#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) -void *USB_EhciNCGetBase(uint8_t controllerId) -{ - void *usbNCBase = NULL; -#if ((defined FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) - uint32_t instance; - uint32_t newinstance = 0; - uint32_t usbnc_base_temp[] = USBNC_BASE_ADDRS; - uint32_t usbnc_base[] = USBNC_BASE_ADDRS; - - if (controllerId < kUSB_ControllerEhci0) - { - return NULL; - } - - controllerId = controllerId - kUSB_ControllerEhci0; - - for (instance = 0; instance < (sizeof(usbnc_base_temp) / sizeof(usbnc_base_temp[0])); instance++) - { - if (usbnc_base_temp[instance]) - { - usbnc_base[newinstance++] = usbnc_base_temp[instance]; - } - } - if (controllerId > newinstance) - { - return NULL; - } - - usbNCBase = (void *)usbnc_base[controllerId]; -#endif - return usbNCBase; -} -#endif -#endif - -/*! - * @brief Set device controller state to default state. - * - * The function is used to set device controller state to default state. - * The function will be called when USB_DeviceEhciInit called or the control type kUSB_DeviceControlGetEndpointStatus - * received in USB_DeviceEhciControl. - * - * @param ehciState Pointer of the device EHCI state structure. - * - */ -static void USB_DeviceEhciSetDefaultState(usb_device_ehci_state_struct_t *ehciState) -{ - usb_device_ehci_dtd_struct_t *p; - - /* Initialize the dtd free queue */ - ehciState->dtdFree = ehciState->dtd; - p = ehciState->dtdFree; - for (uint32_t i = 1U; i < USB_DEVICE_CONFIG_EHCI_MAX_DTD; i++) - { - p->nextDtdPointer = (uint32_t)&ehciState->dtd[i]; - p = (usb_device_ehci_dtd_struct_t *)p->nextDtdPointer; - } - p->nextDtdPointer = 0U; - ehciState->dtdCount = USB_DEVICE_CONFIG_EHCI_MAX_DTD; - - /* Not use interrupt threshold. */ - ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_ITC_MASK; - ehciState->registerBase->USBCMD |= USBHS_USBCMD_ITC(0U); - - /* Disable setup lockout, please refer to "Control Endpoint Operation" section in RM. */ - ehciState->registerBase->USBMODE |= USBHS_USBMODE_SLOM_MASK; - -/* Set the endian by using CPU's endian */ -#if (ENDIANNESS == USB_BIG_ENDIAN) - ehciState->registerBase->USBMODE |= USBHS_USBMODE_ES_MASK; -#else - ehciState->registerBase->USBMODE &= ~USBHS_USBMODE_ES_MASK; -#endif - /* Initialize the QHs of endpoint. */ - for (uint32_t i = 0U; i < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); i++) - { - ehciState->qh[i].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; - ehciState->qh[i].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.maxPacketSize = - USB_CONTROL_MAX_PACKET_SIZE; - ehciState->dtdHard[i] = NULL; - ehciState->dtdTail[i] = NULL; - ehciState->qh[i].endpointStatusUnion.endpointStatusBitmap.isOpened = 0U; - } - - /* Add QH buffer address to USBHS_EPLISTADDR_REG */ - ehciState->registerBase->EPLISTADDR = (uint32_t)ehciState->qh; - - /* Clear device address */ - ehciState->registerBase->DEVICEADDR = 0U; - -#if defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U) - ehciState->registerBase->OTGSC = ehciState->registerBase->OTGSC & 0x0000FFFF; - ehciState->registerBase->OTGSC |= USBHS_OTGSC_BSVIE_MASK; -#endif /* USB_DEVICE_CONFIG_DETACH_ENABLE */ - - /* Enable reset, sof, token, stall interrupt */ - ehciState->registerBase->USBINTR = - (USBHS_USBINTR_UE_MASK | USBHS_USBINTR_UEE_MASK | USBHS_USBINTR_PCE_MASK | USBHS_USBINTR_URE_MASK -#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) - | USBHS_USBINTR_SLE_MASK -#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ - ); - - /* Clear reset flag */ - ehciState->isResetting = 0U; -} - -/*! - * @brief Initialize a specified endpoint. - * - * The function is used to initialize a specified endpoint. - * - * @param ehciState Pointer of the device EHCI state structure. - * @param epInit The endpoint initialization structure pointer. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceEhciEndpointInit(usb_device_ehci_state_struct_t *ehciState, - usb_device_endpoint_init_struct_t *epInit) -{ - uint32_t primeBit = 1U << ((epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK) + - ((epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); - uint16_t maxPacketSize = epInit->maxPacketSize & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK; - uint8_t endpoint = (epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK); - uint8_t direction = (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> - USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; - uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; - uint8_t transferType = epInit->transferType & USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK; - - /* Cancel pending transfer of the endpoint */ - USB_DeviceEhciCancel(ehciState, epInit->endpointAddress); - - if ((ehciState->registerBase->EPPRIME & primeBit) || (ehciState->registerBase->EPSR & primeBit)) - { - return kStatus_USB_Busy; - } - - /* Make the endpoint max packet size align with USB Specification 2.0. */ - if (USB_ENDPOINT_ISOCHRONOUS == transferType) - { - if (maxPacketSize > USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE) - { - maxPacketSize = USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE; - } - ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.mult = - 1U + ((maxPacketSize & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK) >> - USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT); - } - else - { - ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.mult = 0U; - } - - /* Save the max packet size of the endpoint */ - ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.maxPacketSize = - maxPacketSize; - /* Set ZLT bit. */ - ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.zlt = !epInit->zlt; - - /* Enable the endpoint. */ - if (USB_ENDPOINT_CONTROL == transferType) - { - ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios = 1U; - ehciState->registerBase->EPCR0 |= - (direction ? - (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXR_MASK | ((uint32_t)transferType << USBHS_EPCR_TXT_SHIFT)) : - (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXR_MASK | ((uint32_t)transferType << USBHS_EPCR_RXT_SHIFT))); - } - else - { - ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios = 0U; - ehciState->registerBase->EPCR[endpoint - 1U] |= - (direction ? - (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXR_MASK | ((uint32_t)transferType << USBHS_EPCR_TXT_SHIFT)) : - (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXR_MASK | ((uint32_t)transferType << USBHS_EPCR_RXT_SHIFT))); - } - - ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened = 1U; - return kStatus_USB_Success; -} - -/*! - * @brief De-initialize a specified endpoint. - * - * The function is used to de-initialize a specified endpoint. - * Current transfer of the endpoint will be cancelled and the specified endpoint will be disabled. - * - * @param ehciState Pointer of the device EHCI state structure. - * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceEhciEndpointDeinit(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) -{ - uint32_t primeBit = - 1U << ((ep & USB_ENDPOINT_NUMBER_MASK) + ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); - uint8_t endpoint = (ep & USB_ENDPOINT_NUMBER_MASK); - uint8_t direction = - (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; - uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; - - ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened = 0U; - - /* Cancel the transfer of the endpoint */ - USB_DeviceEhciCancel(ehciState, ep); - - if ((ehciState->registerBase->EPPRIME & primeBit) || (ehciState->registerBase->EPSR & primeBit)) - { - return kStatus_USB_Busy; - } - - /* Clear endpoint state */ - ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristics = 0U; - /* Disable the endpoint */ - if (!endpoint) - { - ehciState->registerBase->EPCR0 &= - ~(direction ? (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXT_MASK) : (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXT_MASK)); - } - else - { - ehciState->registerBase->EPCR[endpoint - 1U] &= - ~(direction ? (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXT_MASK) : (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXT_MASK)); - } - - return kStatus_USB_Success; -} - -/*! - * @brief Stall a specified endpoint. - * - * The function is used to stall a specified endpoint. - * Current transfer of the endpoint will be cancelled and the specified endpoint will be stalled. - * - * @param ehciState Pointer of the device EHCI state structure. - * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceEhciEndpointStall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) -{ - uint8_t endpoint = ep & USB_ENDPOINT_NUMBER_MASK; - uint8_t direction = - (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; - uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; - - /* Cancel the transfer of the endpoint */ - USB_DeviceEhciCancel(ehciState, ep); - - /* Set endpoint stall flag. */ - if (ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios) - { - if (!endpoint) - { - ehciState->registerBase->EPCR0 |= (USBHS_EPCR_TXS_MASK | USBHS_EPCR_RXS_MASK); - } - else - { - ehciState->registerBase->EPCR[endpoint - 1U] |= (USBHS_EPCR_TXS_MASK | USBHS_EPCR_RXS_MASK); - } - } - else - { - if (!endpoint) - { - ehciState->registerBase->EPCR0 |= (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); - } - else - { - ehciState->registerBase->EPCR[endpoint - 1U] |= (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); - } - } - - return kStatus_USB_Success; -} - -/*! - * @brief Un-stall a specified endpoint. - * - * The function is used to un-stall a specified endpoint. - * Current transfer of the endpoint will be cancelled and the specified endpoint will be un-stalled. - * - * @param ehciState Pointer of the device EHCI state structure. - * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceEhciEndpointUnstall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) -{ - uint8_t endpoint = ep & USB_ENDPOINT_NUMBER_MASK; - uint8_t direction = - (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; - - /* Clear the endpoint stall state */ - if (!endpoint) - { - ehciState->registerBase->EPCR0 &= ~(direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); - } - else - { - ehciState->registerBase->EPCR[endpoint - 1U] &= ~(direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); - ehciState->registerBase->EPCR[endpoint - 1U] |= (direction ? USBHS_EPCR_TXR_MASK : USBHS_EPCR_RXR_MASK); - } - - return kStatus_USB_Success; -} - -/*! - * @brief Get setup packet data. - * - * The function is used to get setup packet data and copy to a backup buffer. - * - * @param ehciState Pointer of the device EHCI state structure. - * @param ep The endpoint number. - * - */ -static void USB_DeviceEhciFillSetupBuffer(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) -{ - uint8_t waitingSafelyAccess = 1U; - uint8_t index = (ep * 2U) | USB_OUT; - - /* Write 1U to clear corresponding bit in EPSETUPSR. */ - ehciState->registerBase->EPSETUPSR = 1U << ep; - - while (waitingSafelyAccess) - { - /* Set the setup tripwire bit. */ - ehciState->registerBase->USBCMD |= USBHS_USBCMD_SUTW_MASK; - - /* Copy setup packet data to backup buffer */ - ehciState->qh[index].setupBufferBack[0] = ehciState->qh[index].setupBuffer[0]; - ehciState->qh[index].setupBufferBack[1] = ehciState->qh[index].setupBuffer[1]; - - /* Read the USBCMD[SUTW] bit. If set, jump out from the while loop; if cleared continue */ - if (ehciState->registerBase->USBCMD & USBHS_USBCMD_SUTW_MASK) - { - waitingSafelyAccess = 0U; - } - } - /* Clear the setup tripwire bit */ - ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_SUTW_MASK; - - /* Poll until the EPSETUPSR bit clearred */ - while (ehciState->registerBase->EPSETUPSR & (1U << ep)) - { - } -} - -/*! - * @brief Cancel the transfer of the control pipe. - * - * The function is used to cancel the transfer of the control pipe. - * - * @param ehciState Pointer of the device EHCI state structure. - * @param endpoint The endpoint number. - * @param direction The direction of the endpoint. - * - */ -static void USB_DeviceEhciCancelControlPipe(usb_device_ehci_state_struct_t *ehciState, - uint8_t endpoint, - uint8_t direction) -{ - usb_device_ehci_dtd_struct_t *currentDtd; - uint32_t index = ((uint32_t)endpoint << 1U) + (uint32_t)direction; - usb_device_callback_message_struct_t message; - - message.buffer = NULL; - message.length = 0U; - /* Get the dtd of the control pipe */ - currentDtd = - (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); - while (currentDtd) - { - /* Pass the transfer buffer address */ - if (NULL == message.buffer) - { - uint32_t bufferAddress = currentDtd->bufferPointerPage[0]; - message.buffer = (uint8_t *)((bufferAddress & USB_DEVICE_ECHI_DTD_PAGE_MASK) | - (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); - } - /* If the dtd is active, set the message length to USB_UNINITIALIZED_VAL_32. Or set the length by using finished - * length. */ - if (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) - { - message.length = USB_UNINITIALIZED_VAL_32; - } - else - { - message.length += (currentDtd->reservedUnion.originalBufferInfo.originalBufferLength - - currentDtd->dtdTokenUnion.dtdTokenBitmap.totalBytes); - } - - /* Move the dtd head pointer to next. */ - /* If the pointer of the head equals to the tail, set the dtd queue to null. */ - if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) - { - ehciState->dtdHard[index] = NULL; - ehciState->dtdTail[index] = NULL; - ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; - ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; - } - else - { - ehciState->dtdHard[index] = (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; - } - - /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ - if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || - (0 == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) - { - message.code = endpoint | (uint8_t)((uint32_t)direction << 0x07U); - message.isSetup = 0U; - USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); - message.buffer = NULL; - message.length = 0U; - } - - /* Clear the token field of the dtd. */ - currentDtd->dtdTokenUnion.dtdToken = 0U; - /* Add the dtd to the free dtd queue. */ - currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; - ehciState->dtdFree = currentDtd; - ehciState->dtdCount++; - - /* Get the next in-used dtd. */ - currentDtd = - (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); - } -} - -/*! - * @brief Handle the endpoint token done interrupt. - * - * The function is used to handle the endpoint token done interrupt. - * - * @param ehciState Pointer of the device EHCI state structure. - * - */ -static void USB_DeviceEhciInterruptTokenDone(usb_device_ehci_state_struct_t *ehciState) -{ - uint32_t status; - uint32_t primeBit; - usb_device_ehci_dtd_struct_t *currentDtd; - usb_device_callback_message_struct_t message; - uint8_t endpoint; - uint8_t direction; - uint8_t count; - uint8_t index; - - /* Get the EPSETUPSR to check the setup packect received in which one endpoint. */ - status = ehciState->registerBase->EPSETUPSR; - - if (status) - { - for (endpoint = 0U; endpoint < USB_DEVICE_CONFIG_ENDPOINTS; endpoint++) - { - /* Check the endpoint receive the setup packet. */ - if (status & (1U << endpoint)) - { - /* Get last setup packet */ - usb_setup_struct_t *deviceSetup = - (usb_setup_struct_t *)&ehciState->qh[(uint8_t)((uint32_t)endpoint << 1U) + USB_OUT].setupBufferBack; - - /* Check the direction of the data phase. */ - direction = (deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_IN) >> USB_REQUEST_TYPE_DIR_SHIFT; - /* Cancel the data phase transfer */ - USB_DeviceEhciCancelControlPipe(ehciState, endpoint, direction); - /* Cancel the status phase transfer */ - USB_DeviceEhciCancelControlPipe(ehciState, endpoint, 1U ^ direction); - message.code = (endpoint) | (USB_OUT << 0x07U); - message.buffer = (uint8_t *)deviceSetup; - message.length = USB_SETUP_PACKET_SIZE; - message.isSetup = 1U; - /* Fill the setup packet to the backup buffer */ - USB_DeviceEhciFillSetupBuffer(ehciState, endpoint); - /* Notify the up layer the EHCI status changed. */ - USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); - } - } - } - /* Read the USBHS_EPCOMPLETE_REG to get the endpoint transfer done status */ - status = ehciState->registerBase->EPCOMPLETE; - /* Clear the endpoint transfer done status */ - ehciState->registerBase->EPCOMPLETE = status; - - if (status) - { - for (count = 0U; count < 32U; count++) - { - /* Check the transfer is done or not in the specified endpoint. */ - if (status & ((uint32_t)(1U << count))) - { - if (count > 15U) - { - endpoint = count - 16U; - direction = USB_IN; - } - else - { - endpoint = count; - direction = USB_OUT; - } - if (endpoint >= USB_DEVICE_CONFIG_ENDPOINTS) - { - continue; - } - index = (endpoint << 1U) + direction; - message.buffer = NULL; - message.length = 0U; - - /* Get the in-used dtd of the specified endpoint. */ - currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & - USB_DEVICE_ECHI_DTD_POINTER_MASK); - while (currentDtd) - { - uint8_t isTokenDone = 0; - /* Get the in-used dtd of the specified endpoint. */ - currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & - USB_DEVICE_ECHI_DTD_POINTER_MASK); - - while (currentDtd) - { - /* Don't handle the active dtd. */ - if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) || - (currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc)) - { - if ((!(currentDtd->dtdTokenUnion.dtdTokenBitmap.status & - USB_DEVICE_ECHI_DTD_STATUS_ACTIVE)) && - (currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc)) - { - isTokenDone = 1U; - } - break; - } - currentDtd = (usb_device_ehci_dtd_struct_t *)(currentDtd->nextDtdPointer & - USB_DEVICE_ECHI_DTD_POINTER_MASK); - } - - if ((0 == isTokenDone) && (currentDtd)) - { - break; - } - - /* Get the in-used dtd of the specified endpoint. */ - currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & - USB_DEVICE_ECHI_DTD_POINTER_MASK); - while (currentDtd) - { - /* Don't handle the active dtd. */ - if (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) - { - break; - } - - /* Save the transfer buffer address */ - if (NULL == message.buffer) - { - message.buffer = - (uint8_t *)((currentDtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_MASK) | - (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); - } - /* Save the transferred data length */ - message.length += (currentDtd->reservedUnion.originalBufferInfo.originalBufferLength - - currentDtd->dtdTokenUnion.dtdTokenBitmap.totalBytes); - - /* Move the dtd queue head pointer to next */ - if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) - { - ehciState->dtdHard[index] = NULL; - ehciState->dtdTail[index] = NULL; - ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; - ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; - } - else - { - ehciState->dtdHard[index] = - (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; - } - - /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ - if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || - (0 == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) - { - message.code = endpoint | (uint8_t)((uint32_t)direction << 0x07U); - message.isSetup = 0U; - USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); - message.buffer = NULL; - message.length = 0U; - } - /* Clear the token field of the dtd */ - currentDtd->dtdTokenUnion.dtdToken = 0U; - currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; - ehciState->dtdFree = currentDtd; - ehciState->dtdCount++; - /* Get the next in-used dtd */ - currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & - USB_DEVICE_ECHI_DTD_POINTER_MASK); - - if ((NULL != currentDtd) && - (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE)) - { - primeBit = 1U << (endpoint + 16U * direction); - - /* Try to prime the next dtd. */ - ehciState->registerBase->EPPRIME = primeBit; - - /* Whether the endpoint transmit/receive buffer is ready or not. If not, wait for prime bit - * cleared and prime the next dtd. */ - if (!(ehciState->registerBase->EPSR & primeBit)) - { - /* Wait for the endpoint prime bit cleared by HW */ - while (ehciState->registerBase->EPPRIME & primeBit) - { - } - - /* If the endpoint transmit/receive buffer is not ready */ - if (!(ehciState->registerBase->EPSR & primeBit)) - { - /* Prime next dtd and prime the transfer */ - ehciState->qh[index].nextDtdPointer = (uint32_t)currentDtd; - ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; - ehciState->registerBase->EPPRIME = primeBit; - } - } - } - } - } - } - } - } -} - -/*! - * @brief Handle the port status change interrupt. - * - * The function is used to handle the port status change interrupt. - * - * @param ehciState Pointer of the device EHCI state structure. - * - */ -static void USB_DeviceEhciInterruptPortChange(usb_device_ehci_state_struct_t *ehciState) -{ - usb_device_callback_message_struct_t message; - - message.buffer = (uint8_t *)NULL; - message.length = 0U; - message.isSetup = 0U; - - /* Whether the port is doing reset. */ - if (!(ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_PR_MASK)) - { - /* If not, update the USB speed. */ - if (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_HSP_MASK) - { - ehciState->speed = USB_SPEED_HIGH; - } - else - { - ehciState->speed = USB_SPEED_FULL; - } - - /* If the device reset flag is non-zero, notify the up layer the device reset finished. */ - if (ehciState->isResetting) - { - message.code = kUSB_DeviceNotifyBusReset; - USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); - ehciState->isResetting = 0U; - } - } - -#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) - if ((ehciState->isSuspending) && (!(ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_SUSP_MASK))) - { - /* Set the resume flag */ - ehciState->isSuspending = 0U; - - message.code = kUSB_DeviceNotifyResume; - USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); - } -#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ -} - -/*! - * @brief Handle the reset interrupt. - * - * The function is used to handle the reset interrupt. - * - * @param ehciState Pointer of the device EHCI state structure. - * - */ -static void USB_DeviceEhciInterruptReset(usb_device_ehci_state_struct_t *ehciState) -{ - uint32_t status = 0U; - - /* Clear the setup flag */ - status = ehciState->registerBase->EPSETUPSR; - ehciState->registerBase->EPSETUPSR = status; - /* Clear the endpoint complete flag */ - status = ehciState->registerBase->EPCOMPLETE; - ehciState->registerBase->EPCOMPLETE = status; - - do - { - /* Flush the pending transfers */ - ehciState->registerBase->EPFLUSH = USBHS_EPFLUSH_FERB_MASK | USBHS_EPFLUSH_FETB_MASK; - } while (ehciState->registerBase->EPPRIME & (USBHS_EPPRIME_PERB_MASK | USBHS_EPPRIME_PETB_MASK)); - - /* Whether is the port reset. If yes, set the isResetting flag. Or, notify the up layer. */ - if (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_PR_MASK) - { - ehciState->isResetting = 1U; - } - else - { - usb_device_callback_message_struct_t message; - message.buffer = (uint8_t *)NULL; - message.code = kUSB_DeviceNotifyBusReset; - message.length = 0U; - message.isSetup = 0U; - - USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); - } -} - -/*! - * @brief Handle the sof interrupt. - * - * The function is used to handle the sof interrupt. - * - * @param ehciState Pointer of the device EHCI state structure. - * - */ -static void USB_DeviceEhciInterruptSof(usb_device_ehci_state_struct_t *ehciState) -{ -} - -#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) -/*! - * @brief Handle the suspend interrupt. - * - * The function is used to handle the suspend interrupt. - * - * @param ehciState Pointer of the device EHCI state structure. - * - */ -static void USB_DeviceEhciInterruptSuspend(usb_device_ehci_state_struct_t *ehciState) -{ - /* If the port is in suspend state, notify the up layer */ - if (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_SUSP_MASK) - { -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) -#else - if (ehciState->registerPhyBase->USB1_VBUS_DET_STAT & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) -#endif - { - usb_device_callback_message_struct_t message; - message.buffer = (uint8_t *)NULL; - message.length = 0U; - message.isSetup = 0U; - message.code = kUSB_DeviceNotifySuspend; - USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); - } - } -} -#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ - -/*! - * @brief Get dtds and link to QH. - * - * The function is used to get dtds and link to QH. - * - * @param ehciState Pointer of the device EHCI state structure. - * @param endpointAddress The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. - * @param buffer The memory address needed to be transferred. - * @param length Data length. - * - * @return A USB error code or kStatus_USB_Success. - */ -static usb_status_t USB_DeviceEhciTransfer(usb_device_ehci_state_struct_t *ehciState, - uint8_t endpointAddress, - uint8_t *buffer, - uint32_t length) -{ - usb_device_ehci_dtd_struct_t *dtd; - usb_device_ehci_dtd_struct_t *dtdHard; - uint32_t index = ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) << 1U) | - ((endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> - USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); - uint32_t primeBit = 1U << ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) + - ((endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); - uint8_t epStatus = primeBit; - uint32_t sendLength; - uint32_t currentIndex = 0U; - uint32_t dtdRequestCount = (length + USB_DEVICE_ECHI_DTD_TOTAL_BYTES - 1U) / USB_DEVICE_ECHI_DTD_TOTAL_BYTES; - uint8_t qhIdle = 0U; - uint8_t waitingSafelyAccess = 1U; - USB_OSA_SR_ALLOC(); - - if (!ehciState) - { - return kStatus_USB_InvalidHandle; - } - - if (0U == ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened) - { - return kStatus_USB_Error; - } - /* Return error when ehci is doing reset */ - if (ehciState->isResetting) - { - return kStatus_USB_Error; - } - - if (!dtdRequestCount) - { - dtdRequestCount = 1U; - } - - USB_OSA_ENTER_CRITICAL(); - /* The free dtd count need to not less than the transfer requests. */ - if (dtdRequestCount > (uint32_t)ehciState->dtdCount) - { - USB_OSA_EXIT_CRITICAL(); - return kStatus_USB_Busy; - } - - do - { - /* The transfer length need to not more than USB_DEVICE_ECHI_DTD_TOTAL_BYTES for each dtd. */ - if (length > USB_DEVICE_ECHI_DTD_TOTAL_BYTES) - { - sendLength = USB_DEVICE_ECHI_DTD_TOTAL_BYTES; - } - else - { - sendLength = length; - } - length -= sendLength; - - /* Get a free dtd */ - dtd = ehciState->dtdFree; - - ehciState->dtdFree = (usb_device_ehci_dtd_struct_t *)dtd->nextDtdPointer; - ehciState->dtdCount--; - - /* Save the dtd head when current active buffer offset is zero. */ - if (!currentIndex) - { - dtdHard = dtd; - } - - /* Set the dtd field */ - dtd->nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; - dtd->dtdTokenUnion.dtdToken = 0U; - dtd->bufferPointerPage[0] = (uint32_t)(buffer + currentIndex); - dtd->bufferPointerPage[1] = - (dtd->bufferPointerPage[0] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK) & USB_DEVICE_ECHI_DTD_PAGE_MASK; - dtd->bufferPointerPage[2] = dtd->bufferPointerPage[1] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; - dtd->bufferPointerPage[3] = dtd->bufferPointerPage[2] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; - dtd->bufferPointerPage[4] = dtd->bufferPointerPage[3] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; - - dtd->dtdTokenUnion.dtdTokenBitmap.totalBytes = sendLength; - - /* Save the data length needed to be transferred. */ - dtd->reservedUnion.originalBufferInfo.originalBufferLength = sendLength; - /* Save the original buffer address */ - dtd->reservedUnion.originalBufferInfo.originalBufferOffest = - dtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_OFFSET_MASK; - dtd->reservedUnion.originalBufferInfo.dtdInvalid = 0U; - - /* Set the IOC field in last dtd. */ - if (!length) - { - dtd->dtdTokenUnion.dtdTokenBitmap.ioc = 1U; - } - - /* Set dtd active */ - dtd->dtdTokenUnion.dtdTokenBitmap.status = USB_DEVICE_ECHI_DTD_STATUS_ACTIVE; - - /* Move the buffer offset index */ - currentIndex += sendLength; - - /* Add dtd to the in-used dtd queue */ - if (ehciState->dtdTail[index]) - { - ehciState->dtdTail[index]->nextDtdPointer = (uint32_t)dtd; - ehciState->dtdTail[index] = dtd; - } - else - { - ehciState->dtdHard[index] = dtd; - ehciState->dtdTail[index] = dtd; - qhIdle = 1U; - } - } while (length); - - /* If the QH is not empty */ - if (!qhIdle) - { - /* If the prime bit is set, nothing need to do. */ - if (ehciState->registerBase->EPPRIME & primeBit) - { - USB_OSA_EXIT_CRITICAL(); - return kStatus_USB_Success; - } - - /* To safely a dtd */ - while (waitingSafelyAccess) - { - /* set the ATDTW flag to USBHS_USBCMD_REG. */ - ehciState->registerBase->USBCMD |= USBHS_USBCMD_ATDTW_MASK; - /* Read EPSR */ - epStatus = ehciState->registerBase->EPSR; - /* Wait the ATDTW bit set */ - if (ehciState->registerBase->USBCMD & USBHS_USBCMD_ATDTW_MASK) - { - waitingSafelyAccess = 0U; - } - } - /* Clear the ATDTW bit */ - ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_ATDTW_MASK; - } - - /* If QH is empty or the endpoint is not primed, need to link current dtd head to the QH. */ - /* When the endpoint is not primed if qhIdle is zero, it means the QH is empty. */ - if ((qhIdle) || (!(epStatus & primeBit))) - { - ehciState->qh[index].nextDtdPointer = (uint32_t)dtdHard; - ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; - ehciState->registerBase->EPPRIME = primeBit; - while (!(ehciState->registerBase->EPSR & primeBit)) - { - if (ehciState->registerBase->EPCOMPLETE & primeBit) - { - break; - } - else - { - ehciState->registerBase->EPPRIME = primeBit; - } - } - } - - USB_OSA_EXIT_CRITICAL(); - return kStatus_USB_Success; -} - -/*! - * @brief Initialize the USB device EHCI instance. - * - * This function initializes the USB device EHCI module specified by the controllerId. - * - * @param controllerId The controller id of the USB IP. Please refer to enumeration type usb_controller_index_t. - * @param handle Pointer of the device handle, used to identify the device object is belonged to. - * @param ehciHandle It is out parameter, is used to return pointer of the device EHCI handle to the caller. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceEhciInit(uint8_t controllerId, - usb_device_handle handle, - usb_device_controller_handle *ehciHandle) -{ - usb_device_ehci_state_struct_t *ehciState; - uint32_t ehci_base[] = USBHS_BASE_ADDRS; - -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ - (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) - usb_device_dcd_state_struct_t *dcdHSState; - uint32_t dcd_base[] = USBHSDCD_BASE_ADDRS; - usb_device_callback_message_struct_t message; -#endif - - if ((controllerId < kUSB_ControllerEhci0) || - ((uint32_t)(controllerId - kUSB_ControllerEhci0) >= USB_DEVICE_CONFIG_EHCI) || - ((uint32_t)(controllerId - kUSB_ControllerEhci0) >= (sizeof(ehci_base) / sizeof(uint32_t)))) - { - return kStatus_USB_ControllerNotFound; - } - - ehciState = &g_UsbDeviceEhciSate[controllerId - kUSB_ControllerEhci0]; - - ehciState->dtd = s_UsbDeviceEhciDtd[controllerId - kUSB_ControllerEhci0]; - ehciState->qh = (usb_device_ehci_qh_struct_t *)&qh_buffer[(controllerId - kUSB_ControllerEhci0) * 2048]; - - ehciState->controllerId = controllerId; - - ehciState->registerBase = (USBHS_Type *)ehci_base[controllerId - kUSB_ControllerEhci0]; -#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) - ehciState->registerPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); - -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) - ehciState->registerNcBase = (USBNC_Type *)USB_EhciNCGetBase(controllerId); -#endif - -#endif - - /* Get the HW's endpoint count */ - ehciState->endpointCount = - (uint8_t)((ehciState->registerBase->DCCPARAMS & USBHS_DCCPARAMS_DEN_MASK) >> USBHS_DCCPARAMS_DEN_SHIFT); - - if (ehciState->endpointCount < USB_DEVICE_CONFIG_ENDPOINTS) - { - return kStatus_USB_Error; - } - ehciState->deviceHandle = (usb_device_struct_t *)handle; - - /* Clear the controller mode field and set to device mode. */ - ehciState->registerBase->USBMODE &= ~USBHS_USBMODE_CM_MASK; - ehciState->registerBase->USBMODE |= USBHS_USBMODE_CM(0x02U); - - /* Set the EHCI to default status. */ - USB_DeviceEhciSetDefaultState(ehciState); - *ehciHandle = (usb_device_controller_handle)ehciState; -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ - (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) - dcdHSState = &s_UsbDeviceDcdHSState[controllerId - kUSB_ControllerEhci0]; - - dcdHSState->controllerId = controllerId; - - dcdHSState->dcdRegisterBase = (USBHSDCD_Type *)dcd_base[controllerId - kUSB_ControllerEhci0]; - - dcdHSState->deviceHandle = (usb_device_struct_t *)handle; - - message.buffer = (uint8_t *)NULL; - message.length = 0U; - message.isSetup = 0U; - if (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSV_MASK) - { - /* Device is connected to a host. */ - message.code = kUSB_DeviceNotifyAttach; - USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); - } -#endif - - return kStatus_USB_Success; -} - -/*! - * @brief De-initialize the USB device EHCI instance. - * - * This function de-initializes the USB device EHCI module. - * - * @param ehciHandle Pointer of the device EHCI handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceEhciDeinit(usb_device_controller_handle ehciHandle) -{ - usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; - - if (!ehciHandle) - { - return kStatus_USB_InvalidHandle; - } - - /* Disable all interrupt. */ - ehciState->registerBase->USBINTR = 0U; - /* Stop the device functionality. */ - ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; - /* Reset the controller. */ - ehciState->registerBase->USBCMD |= USBHS_USBCMD_RST_MASK; - - return kStatus_USB_Success; -} - -/*! - * @brief Send data through a specified endpoint. - * - * This function sends data through a specified endpoint. - * - * @param ehciHandle Pointer of the device EHCI handle. - * @param endpointAddress Endpoint index. - * @param buffer The memory address to hold the data need to be sent. - * @param length The data length need to be sent. - * - * @return A USB error code or kStatus_USB_Success. - * - * @note The return value just means if the sending request is successful or not; the transfer done is notified by the - * corresponding callback function. - * Currently, only one transfer request can be supported for one specific endpoint. - * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application - * should implement a queue in the application level. - * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint - * callback). - */ -usb_status_t USB_DeviceEhciSend(usb_device_controller_handle ehciHandle, - uint8_t endpointAddress, - uint8_t *buffer, - uint32_t length) -{ - /* Add dtd to the QH */ - return USB_DeviceEhciTransfer( - (usb_device_ehci_state_struct_t *)ehciHandle, - (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), - buffer, length); -} - -/*! - * @brief Receive data through a specified endpoint. - * - * This function Receives data through a specified endpoint. - * - * @param ehciHandle Pointer of the device EHCI handle. - * @param endpointAddress Endpoint index. - * @param buffer The memory address to save the received data. - * @param length The data length want to be received. - * - * @return A USB error code or kStatus_USB_Success. - * - * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the - * corresponding callback function. - * Currently, only one transfer request can be supported for one specific endpoint. - * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application - * should implement a queue in the application level. - * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint - * callback). - */ -usb_status_t USB_DeviceEhciRecv(usb_device_controller_handle ehciHandle, - uint8_t endpointAddress, - uint8_t *buffer, - uint32_t length) -{ - /* Add dtd to the QH */ - return USB_DeviceEhciTransfer( - (usb_device_ehci_state_struct_t *)ehciHandle, - (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), - buffer, length); -} - -/*! - * @brief Cancel the pending transfer in a specified endpoint. - * - * The function is used to cancel the pending transfer in a specified endpoint. - * - * @param ehciHandle Pointer of the device EHCI handle. - * @param ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, 0U - OUT. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceEhciCancel(usb_device_controller_handle ehciHandle, uint8_t ep) -{ - usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; - usb_device_callback_message_struct_t message; - usb_device_ehci_dtd_struct_t *currentDtd; - uint32_t primeBit = - 1U << ((ep & USB_ENDPOINT_NUMBER_MASK) + ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); - uint8_t index = - ((ep & USB_ENDPOINT_NUMBER_MASK) << 1U) | ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x07U); - - USB_OSA_SR_ALLOC(); - - if (!ehciHandle) - { - return kStatus_USB_InvalidHandle; - } - - USB_OSA_ENTER_CRITICAL(); - - message.buffer = NULL; - message.length = USB_UNINITIALIZED_VAL_32; - - /* Get the first dtd */ - currentDtd = - (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); - - while (currentDtd) - { - currentDtd->reservedUnion.originalBufferInfo.dtdInvalid = 1U; - currentDtd = (usb_device_ehci_dtd_struct_t *)(currentDtd->nextDtdPointer & USB_DEVICE_ECHI_DTD_POINTER_MASK); - } - - /* Get the first dtd */ - currentDtd = - (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); - while (currentDtd) - { - if (!currentDtd->reservedUnion.originalBufferInfo.dtdInvalid) - { - break; - } - else - { - if (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) - { - /* Flush the endpoint to stop a transfer. */ - do - { - /* Set the corresponding bit(s) in the EPFLUSH register */ - ehciState->registerBase->EPFLUSH |= primeBit; - - /* Wait until all bits in the EPFLUSH register are cleared. */ - while (ehciState->registerBase->EPFLUSH & primeBit) - { - } - /* - * Read the EPSR register to ensure that for all endpoints - * commanded to be flushed, that the corresponding bits - * are now cleared. - */ - } while (ehciState->registerBase->EPSR & primeBit); - } - - /* Save the original buffer address. */ - if (NULL == message.buffer) - { - message.buffer = (uint8_t *)((currentDtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_MASK) | - (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); - } - - /* Remove the dtd from the dtd in-used queue. */ - if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) - { - ehciState->dtdHard[index] = NULL; - ehciState->dtdTail[index] = NULL; - } - else - { - ehciState->dtdHard[index] = (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; - } - - /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ - if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || - (0 == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) - { - message.code = ep; - message.isSetup = 0U; - USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); - message.buffer = NULL; - } - /* Clear the token field. */ - currentDtd->dtdTokenUnion.dtdToken = 0U; - /* Save the dtd to the free queue. */ - currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; - ehciState->dtdFree = currentDtd; - ehciState->dtdCount++; - } - /* Get the next dtd. */ - currentDtd = - (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); - } - if (!currentDtd) - { - /* Set the QH to empty. */ - ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; - ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; - } - USB_OSA_EXIT_CRITICAL(); - return kStatus_USB_Success; -} - -/*! - * @brief Control the status of the selected item. - * - * The function is used to control the status of the selected item. - * - * @param ehciHandle Pointer of the device EHCI handle. - * @param type The selected item. Please refer to enumeration type usb_device_control_type_t. - * @param param The param type is determined by the selected item. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceEhciControl(usb_device_controller_handle ehciHandle, usb_device_control_type_t type, void *param) -{ - usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; - usb_status_t error = kStatus_USB_Error; - uint16_t *temp16; - uint8_t *temp8; -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ - (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) - usb_device_dcd_state_struct_t *dcdHSState; - dcdHSState = - &s_UsbDeviceDcdHSState[ehciState->controllerId - kUSB_ControllerEhci0]; /*The hard code should be replaced*/ - usb_device_dcd_charging_time_t *deviceDcdTimingConfig = (usb_device_dcd_charging_time_t *)param; -#endif -#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) - usb_device_struct_t *deviceHandle; - uint64_t startTick; -#endif - - if (!ehciHandle) - { - return kStatus_USB_InvalidHandle; - } - -#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) - deviceHandle = (usb_device_struct_t *)ehciState->deviceHandle; -#endif - - switch (type) - { - case kUSB_DeviceControlRun: - ehciState->registerBase->USBCMD |= USBHS_USBCMD_RS_MASK; - error = kStatus_USB_Success; - break; - case kUSB_DeviceControlStop: - ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; - error = kStatus_USB_Success; - break; - case kUSB_DeviceControlEndpointInit: - if (param) - { - error = USB_DeviceEhciEndpointInit(ehciState, (usb_device_endpoint_init_struct_t *)param); - } - break; - case kUSB_DeviceControlEndpointDeinit: - if (param) - { - temp8 = (uint8_t *)param; - error = USB_DeviceEhciEndpointDeinit(ehciState, *temp8); - } - break; - case kUSB_DeviceControlEndpointStall: - if (param) - { - temp8 = (uint8_t *)param; - error = USB_DeviceEhciEndpointStall(ehciState, *temp8); - } - break; - case kUSB_DeviceControlEndpointUnstall: - if (param) - { - temp8 = (uint8_t *)param; - error = USB_DeviceEhciEndpointUnstall(ehciState, *temp8); - } - break; - case kUSB_DeviceControlGetDeviceStatus: - if (param) - { - temp16 = (uint16_t *)param; - *temp16 = (USB_DEVICE_CONFIG_SELF_POWER << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT)) -#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) - | (deviceHandle->remotewakeup << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT)) -#endif - ; - error = kStatus_USB_Success; - } - break; - case kUSB_DeviceControlGetEndpointStatus: - if (param) - { - usb_device_endpoint_status_struct_t *endpointStatus = (usb_device_endpoint_status_struct_t *)param; - uint8_t ep = (endpointStatus->endpointAddress) & USB_ENDPOINT_NUMBER_MASK; - uint8_t direction = - ((endpointStatus->endpointAddress) & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> - USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; - - if (ep < USB_DEVICE_CONFIG_ENDPOINTS) - { - if (ep) - { - endpointStatus->endpointStatus = (ehciState->registerBase->EPCR[ep - 1U] & - (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK)) ? - kUSB_DeviceEndpointStateStalled : - kUSB_DeviceEndpointStateIdle; - } - else - { - endpointStatus->endpointStatus = - (ehciState->registerBase->EPCR0 & (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK)) ? - kUSB_DeviceEndpointStateStalled : - kUSB_DeviceEndpointStateIdle; - } - error = kStatus_USB_Success; - } - } - break; - case kUSB_DeviceControlSetDeviceAddress: - if (param) - { - temp8 = (uint8_t *)param; - ehciState->registerBase->DEVICEADDR = (((uint32_t)(*temp8)) << USBHS_DEVICEADDR_USBADR_SHIFT); - error = kStatus_USB_Success; - } - break; - case kUSB_DeviceControlGetSynchFrame: - break; -#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) -#if defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U) - case kUSB_DeviceControlResume: -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) - ehciState->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; -#else - ehciState->registerBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; -#endif - ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; - ehciState->registerBase->PORTSC1 |= USBHS_PORTSC1_FPR_MASK; - startTick = deviceHandle->hwTick; - while ((deviceHandle->hwTick - startTick) < 10) - { - __ASM("nop"); - } - ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_FPR_MASK; - error = kStatus_USB_Success; - break; -#endif /* USB_DEVICE_CONFIG_REMOTE_WAKEUP */ - case kUSB_DeviceControlSuspend: - ehciState->registerBase->OTGSC |= 0x007F0000U; - ehciState->registerPhyBase->PWD = 0xFFFFFFFF; - /* ehciState->registerBase->OTGCTL |= ((1U<<10) | (1U<<17) | (1U<<16)); */ - while (ehciState->registerPhyBase->CTRL & (USBPHY_CTRL_UTMI_SUSPENDM_MASK)) - { - __ASM("nop"); - } - /* ehciState->registerPhyBase->CTRL |= ((1U << 21) | (1U << 22) | (1U << 23)); */ - ehciState->registerBase->USBSTS |= USBHS_USBSTS_SRI_MASK; - ehciState->registerBase->PORTSC1 |= USBHS_PORTSC1_PHCD_MASK; -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) - ehciState->registerPhyBase->CTRL |= USBPHY_CTRL_ENVBUSCHG_WKUP_MASK | USBPHY_CTRL_ENIDCHG_WKUP_MASK | - USBPHY_CTRL_ENDPDMCHG_WKUP_MASK | USBPHY_CTRL_ENIRQRESUMEDETECT_MASK; - ehciState->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK | - USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK | - USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK; - ehciState->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WIE_MASK; -#else - ehciState->registerBase->USBGENCTRL = USBHS_USBGENCTRL_WU_IE_MASK; -#endif - ehciState->registerPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; - ehciState->isSuspending = 1U; - error = kStatus_USB_Success; - break; -#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ - case kUSB_DeviceControlSetDefaultStatus: - for (uint8_t count = 0U; count < USB_DEVICE_CONFIG_ENDPOINTS; count++) - { - USB_DeviceEhciEndpointDeinit(ehciState, (count | (USB_IN << 0x07U))); - USB_DeviceEhciEndpointDeinit(ehciState, (count | (USB_OUT << 0x07U))); - } - USB_DeviceEhciSetDefaultState(ehciState); - error = kStatus_USB_Success; - break; - case kUSB_DeviceControlGetSpeed: - if (param) - { - temp8 = (uint8_t *)param; - *temp8 = ehciState->speed; - error = kStatus_USB_Success; - } - break; - case kUSB_DeviceControlGetOtgStatus: - break; - case kUSB_DeviceControlSetOtgStatus: - break; -#if (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U)) - case kUSB_DeviceControlSetTestMode: - if (param) - { - temp8 = (uint8_t *)param; - ehciState->registerBase->PORTSC1 |= ((uint32_t)(*temp8) << 16U); - error = kStatus_USB_Success; - } - break; -#endif -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ - (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) - case kUSB_DeviceControlDcdInitModule: - dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; - dcdHSState->dcdRegisterBase->TIMER0 = USBDCD_TIMER0_TSEQ_INIT(deviceDcdTimingConfig->dcdSeqInitTime); - dcdHSState->dcdRegisterBase->TIMER1 = USBDCD_TIMER1_TDCD_DBNC(deviceDcdTimingConfig->dcdDbncTime); - dcdHSState->dcdRegisterBase->TIMER1 |= USBDCD_TIMER1_TVDPSRC_ON(deviceDcdTimingConfig->dcdDpSrcOnTime); - dcdHSState->dcdRegisterBase->TIMER2_BC12 = - USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(deviceDcdTimingConfig->dcdTimeWaitAfterPrD); - dcdHSState->dcdRegisterBase->TIMER2_BC12 |= - USBDCD_TIMER2_BC12_TVDMSRC_ON(deviceDcdTimingConfig->dcdTimeDMSrcOn); - dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_IE_MASK; - dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_BC12_MASK; - dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_START_MASK; - break; - case kUSB_DeviceControlDcdDeinitModule: - dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; - break; -#endif - - default: - break; - } - - return error; -} - -/*! - * @brief Handle the EHCI device interrupt. - * - * The function is used to handle the EHCI device interrupt. - * - * @param deviceHandle The device handle got from USB_DeviceInit. - * - */ -void USB_DeviceEhciIsrFunction(void *deviceHandle) -{ - usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle; - usb_device_ehci_state_struct_t *ehciState; - uint32_t status; - - if (NULL == deviceHandle) - { - return; - } - - ehciState = (usb_device_ehci_state_struct_t *)(handle->controllerHandle); - -#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) - -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) - - if (ehciState->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIE_MASK) - { - if (ehciState->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIR_MASK) - { - ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; - ehciState->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; - } - } - else - { - } - -#else - if (ehciState->registerBase->USBGENCTRL & USBHS_USBGENCTRL_WU_IE_MASK) - { - if (ehciState->registerBase->USBGENCTRL & (1U << 8)) - { - ehciState->registerBase->USBGENCTRL &= ~(1U << 8); - ehciState->registerBase->USBGENCTRL |= USBHS_USBGENCTRL_WU_INT_CLR_MASK; - ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; - ehciState->registerBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; - } - } - else - { - } -#endif - -#endif - -#if defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U) - if (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSVIS_MASK) - { - usb_device_callback_message_struct_t message; - - ehciState->registerBase->OTGSC |= USBHS_OTGSC_BSVIS_MASK; - - message.buffer = (uint8_t *)NULL; - message.length = 0U; - message.isSetup = 0U; - if (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSV_MASK) - { - /* Device is connected to a host. */ - message.code = kUSB_DeviceNotifyAttach; - USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); - } - else - { - /* Device is disconnected from a host. */ - message.code = kUSB_DeviceNotifyDetach; - USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); - } - } -#endif /* USB_DEVICE_CONFIG_DETACH_ENABLE */ - - status = ehciState->registerBase->USBSTS; - status &= ehciState->registerBase->USBINTR; - - ehciState->registerBase->USBSTS = status; - -#if defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U) - if (status & USBHS_USBSTS_UEI_MASK) - { - /* Error interrupt */ - USB_DeviceEhciInterruptError(ehciState); - } -#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */ - - if (status & USBHS_USBSTS_URI_MASK) - { - /* Reset interrupt */ - USB_DeviceEhciInterruptReset(ehciState); - } - - if (status & USBHS_USBSTS_UI_MASK) - { - /* Token done interrupt */ - USB_DeviceEhciInterruptTokenDone(ehciState); - } - - if (status & USBHS_USBSTS_PCI_MASK) - { - /* Port status change interrupt */ - USB_DeviceEhciInterruptPortChange(ehciState); - } - -#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) - if (status & USBHS_USBSTS_SLI_MASK) - { - /* Suspend interrupt */ - USB_DeviceEhciInterruptSuspend(ehciState); - } -#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ - - if (status & USBHS_USBSTS_SRI_MASK) - { - /* Sof interrupt */ - USB_DeviceEhciInterruptSof(ehciState); - } -} - -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ - (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) -void USB_DeviceDcdHSIsrFunction(void *deviceHandle) -{ - usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle; - usb_device_ehci_state_struct_t *ehciState; - usb_device_dcd_state_struct_t *dcdHSState; - uint32_t status; - uint32_t chargerType; - usb_device_callback_message_struct_t message; - - if (NULL == deviceHandle) - { - return; - } - - ehciState = (usb_device_ehci_state_struct_t *)(handle->controllerHandle); - - dcdHSState = &s_UsbDeviceDcdHSState[ehciState->controllerId - kUSB_ControllerEhci0]; - - status = dcdHSState->dcdRegisterBase->STATUS; - - dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_IACK_MASK; - - message.buffer = (uint8_t *)NULL; - message.length = 0U; - message.isSetup = 0U; - - if (status & USBDCD_STATUS_ERR_MASK) - { - if (status & USBDCD_STATUS_TO_MASK) - { - dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; - message.code = kUSB_DeviceNotifyDcdTimeOut; - USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); - } - else - { - dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; - message.code = kUSB_DeviceNotifyDcdUnknownPortType; - USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); - } - } - else - { - switch (status & USBDCD_STATUS_SEQ_STAT_MASK) - { - case USBDCD_STATUS_SEQ_STAT(kUSB_DcdChargingPortDetectionCompleted): - chargerType = status & USBDCD_STATUS_SEQ_RES_MASK; - if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionStandardHost)) - { - dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; - message.code = kUSB_DeviceNotifySDPDetected; - USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); - } - else if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionChargingPort)) - { - message.code = kUSB_DeviceNotifyChargingPortDetected; - USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); - } - break; - case USBDCD_STATUS_SEQ_STAT(kUSB_DcdChargerTypeDetectionCompleted): - chargerType = status & USBDCD_STATUS_SEQ_RES_MASK; - if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionChargingPort)) - { - dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; - message.code = kUSB_DeviceNotifyChargingHostDetected; - USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); - } - else if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionDedicatedCharger)) - { - dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; - message.code = kUSB_DeviceNotifyDedicatedChargerDetected; - USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); - } - break; - - default: - break; - } - } -} -#endif - -#endif /* USB_DEVICE_CONFIG_EHCI */ diff --git a/bsp/imxrt1052-evk/drivers/usb/device/usb_device_ehci.h b/bsp/imxrt1052-evk/drivers/usb/device/usb_device_ehci.h deleted file mode 100644 index 869e063263..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/device/usb_device_ehci.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __USB_DEVICE_EHCI_H__ -#define __USB_DEVICE_EHCI_H__ - -#include - -/*! - * @addtogroup usb_device_controller_ehci_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief The maximum value of ISO type maximum packet size for HS in USB specification 2.0 */ -#define USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE (1024U) - -/*! @brief The maximum value of interrupt type maximum packet size for HS in USB specification 2.0 */ -#define USB_DEVICE_MAX_HS_INTERUPT_MAX_PACKET_SIZE (1024U) - -/*! @brief The maximum value of bulk type maximum packet size for HS in USB specification 2.0 */ -#define USB_DEVICE_MAX_HS_BULK_MAX_PACKET_SIZE (512U) - -/*! @brief The maximum value of control type maximum packet size for HS in USB specification 2.0 */ -#define USB_DEVICE_MAX_HS_CONTROL_MAX_PACKET_SIZE (64U) - -/*! @brief EHCI state structure */ -typedef struct _usb_device_ehci_state_struct -{ - usb_device_struct_t *deviceHandle; /*!< Device handle used to identify the device object is belonged to */ - USBHS_Type *registerBase; /*!< The base address of the register */ -#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) - USBPHY_Type *registerPhyBase; /*!< The base address of the PHY register */ -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) - USBNC_Type *registerNcBase; /*!< The base address of the USBNC register */ -#endif -#endif - usb_device_ehci_qh_struct_t *qh; /*!< The QH structure base address */ - usb_device_ehci_dtd_struct_t *dtd; /*!< The DTD structure base address */ - usb_device_ehci_dtd_struct_t *dtdFree; /*!< The idle DTD list head */ - usb_device_ehci_dtd_struct_t - *dtdHard[USB_DEVICE_CONFIG_ENDPOINTS * 2]; /*!< The transferring DTD list head for each endpoint */ - usb_device_ehci_dtd_struct_t - *dtdTail[USB_DEVICE_CONFIG_ENDPOINTS * 2]; /*!< The transferring DTD list tail for each endpoint */ - int8_t dtdCount; /*!< The idle DTD node count */ - uint8_t endpointCount; /*!< The endpoint number of EHCI */ - uint8_t isResetting; /*!< Whether a PORT reset is occurring or not */ - uint8_t controllerId; /*!< Controller ID */ - uint8_t speed; /*!< Current speed of EHCI */ - uint8_t isSuspending; /*!< Is suspending of the PORT */ -} usb_device_ehci_state_struct_t; - -#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ - (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) -typedef struct _usb_device_dcd_state_struct -{ - usb_device_struct_t *deviceHandle; /*!< Device handle used to identify the device object belongs to */ - USBHSDCD_Type *dcdRegisterBase; /*!< The base address of the dcd module */ - uint8_t controllerId; /*!< Controller ID */ -} usb_device_dcd_state_struct_t; -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name USB device EHCI functions - * @{ - */ - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief Initializes the USB device EHCI instance. - * - * This function initializes the USB device EHCI module specified by the controllerId. - * - * @param[in] controllerId The controller ID of the USB IP. See the enumeration type usb_controller_index_t. - * @param[in] handle Pointer of the device handle used to identify the device object is belonged to. - * @param[out] ehciHandle An out parameter used to return the pointer of the device EHCI handle to the caller. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceEhciInit(uint8_t controllerId, - usb_device_handle handle, - usb_device_controller_handle *ehciHandle); - -/*! - * @brief Deinitializes the USB device EHCI instance. - * - * This function deinitializes the USB device EHCI module. - * - * @param[in] ehciHandle Pointer of the device EHCI handle. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceEhciDeinit(usb_device_controller_handle ehciHandle); - -/*! - * @brief Sends data through a specified endpoint. - * - * This function sends data through a specified endpoint. - * - * @param[in] ehciHandle Pointer of the device EHCI handle. - * @param[in] endpointAddress Endpoint index. - * @param[in] buffer The memory address to hold the data need to be sent. - * @param[in] length The data length to be sent. - * - * @return A USB error code or kStatus_USB_Success. - * - * @note The return value means whether the sending request is successful or not. The transfer completion is indicated - * by the - * corresponding callback function. - * Currently, only one transfer request can be supported for a specific endpoint. - * If there is a specific requirement to support multiple transfer requests for a specific endpoint, the application - * should implement a queue in the application level. - * The subsequent transfer can begin only when the previous transfer is done (a notification is received through the - * endpoint - * callback). - */ -usb_status_t USB_DeviceEhciSend(usb_device_controller_handle ehciHandle, - uint8_t endpointAddress, - uint8_t *buffer, - uint32_t length); - -/*! - * @brief Receive data through a specified endpoint. - * - * This function Receives data through a specified endpoint. - * - * @param[in] ehciHandle Pointer of the device EHCI handle. - * @param[in] endpointAddress Endpoint index. - * @param[in] buffer The memory address to save the received data. - * @param[in] length The data length want to be received. - * - * @return A USB error code or kStatus_USB_Success. - * - * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the - * corresponding callback function. - * Currently, only one transfer request can be supported for one specific endpoint. - * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application - * should implement a queue in the application level. - * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint - * callback). - */ -usb_status_t USB_DeviceEhciRecv(usb_device_controller_handle ehciHandle, - uint8_t endpointAddress, - uint8_t *buffer, - uint32_t length); - -/*! - * @brief Cancels the pending transfer in a specified endpoint. - * - * The function is used to cancel the pending transfer in a specified endpoint. - * - * @param[in] ehciHandle Pointer of the device EHCI handle. - * @param[in] ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, 0U - OUT. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceEhciCancel(usb_device_controller_handle ehciHandle, uint8_t ep); - -/*! - * @brief Controls the status of the selected item. - * - * The function is used to control the status of the selected item. - * - * @param[in] ehciHandle Pointer of the device EHCI handle. - * @param[in] type The selected item. See enumeration type usb_device_control_type_t. - * @param[in,out] param The parameter type is determined by the selected item. - * - * @return A USB error code or kStatus_USB_Success. - */ -usb_status_t USB_DeviceEhciControl(usb_device_controller_handle ehciHandle, - usb_device_control_type_t type, - void *param); - -/*! @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* __USB_DEVICE_EHCI_H__ */ diff --git a/bsp/imxrt1052-evk/drivers/usb/host/usb_host.h b/bsp/imxrt1052-evk/drivers/usb/host/usb_host.h deleted file mode 100644 index 53be402cd3..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/host/usb_host.h +++ /dev/null @@ -1,726 +0,0 @@ -/* - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _USB_HOST_H_ -#define _USB_HOST_H_ - -#include -#include -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -struct _usb_host_transfer; /* for cross reference */ - -/*! - * @addtogroup usb_host_drv - * @{ - */ - -/*! @brief USB host class handle type define */ -typedef void *usb_host_class_handle; - -/*! @brief USB host controller handle type define */ -typedef void *usb_host_controller_handle; - -/*! @brief USB host configuration handle type define */ -typedef void *usb_host_configuration_handle; - -/*! @brief USB host interface handle type define */ -typedef void *usb_host_interface_handle; - -/*! @brief USB host pipe handle type define */ -typedef void *usb_host_pipe_handle; - -/*! @brief Event codes for device attach/detach */ -typedef enum _usb_host_event -{ - kUSB_HostEventAttach = 1U, /*!< Device is attached */ - kUSB_HostEventDetach, /*!< Device is detached */ - kUSB_HostEventEnumerationDone, /*!< Device's enumeration is done and the device is supported */ - kUSB_HostEventNotSupported, /*!< Device's enumeration is done and the device is not supported */ -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - kUSB_HostEventNotSuspended, /*!< Suspend failed */ - kUSB_HostEventSuspended, /*!< Suspend successful */ - kUSB_HostEventNotResumed, /*!< Resume failed */ - kUSB_HostEventDetectResume, /*!< Detect resume signal */ - kUSB_HostEventResumed, /*!< Resume successful */ - kUSB_HostEventL1Sleeped, /*!< L1 Sleep successful,state transition was successful (ACK) */ - kUSB_HostEventL1SleepNYET, /*!< Device was unable to enter the L1 state at this time (NYET) */ - kUSB_HostEventL1SleepNotSupport, /*!< Device does not support the L1 state (STALL) */ - kUSB_HostEventL1SleepError, /*!< Device failed to respond or an error occurred */ - kUSB_HostEventL1NotResumed, /*!< Resume failed */ - kUSB_HostEventL1DetectResume, /*!< Detect resume signal */ - kUSB_HostEventL1Resumed, /*!< Resume successful */ -#endif -} usb_host_event_t; - -/*! @brief USB host device information code */ -typedef enum _usb_host_dev_info -{ - kUSB_HostGetDeviceAddress = 1U, /*!< Device's address */ - kUSB_HostGetDeviceHubNumber, /*!< Device's first hub address */ - kUSB_HostGetDevicePortNumber, /*!< Device's first hub port number */ - kUSB_HostGetDeviceSpeed, /*!< Device's speed */ - kUSB_HostGetDeviceHSHubNumber, /*!< Device's first high-speed hub address */ - kUSB_HostGetDeviceHSHubPort, /*!< Device's first high-speed hub number */ - kUSB_HostGetDeviceLevel, /*!< Device's hub level */ - kUSB_HostGetHostHandle, /*!< Device's host handle */ - kUSB_HostGetDeviceControlPipe, /*!< Device's control pipe handle */ - kUSB_HostGetDevicePID, /*!< Device's PID */ - kUSB_HostGetDeviceVID, /*!< Device's VID */ - kUSB_HostGetHubThinkTime, /*!< Device's hub total think time */ - kUSB_HostGetDeviceConfigIndex, /*!< Device's running zero-based config index */ - kUSB_HostGetConfigurationDes, /*!< Device's configuration descriptor pointer */ - kUSB_HostGetConfigurationLength, /*!< Device's configuration descriptor pointer */ -} usb_host_dev_info_t; - -/*! - * @brief Host callback function typedef. - * - * This callback function is used to notify application device attach/detach event. - * This callback pointer is passed when initializing the host. - * - * @param deviceHandle The device handle, which indicates the attached device. - * @param configurationHandle The configuration handle contains the attached device's configuration information. - * @param event_code The callback event code; See the enumeration host_event_t. - * - * @return A USB error code or kStatus_USB_Success. - * @retval kStatus_USB_Success Application handles the attached device successfully. - * @retval kStatus_USB_NotSupported Application don't support the attached device. - * @retval kStatus_USB_Error Application handles the attached device falsely. - */ -typedef usb_status_t (*host_callback_t)(usb_device_handle deviceHandle, - usb_host_configuration_handle configurationHandle, - uint32_t eventCode); - -/*! - * @brief Transfer callback function typedef. - * - * This callback function is used to notify the upper layer the result of the transfer. - * This callback pointer is passed when calling the send/receive APIs. - * - * @param param The parameter pointer, which is passed when calling the send/receive APIs. - * @param data The data buffer pointer. - * @param data_len The result data length. - * @param status A USB error code or kStatus_USB_Success. - */ -typedef void (*transfer_callback_t)(void *param, uint8_t *data, uint32_t dataLen, usb_status_t status); - -/*! - * @brief Host stack inner transfer callback function typedef. - * - * This callback function is used to notify the upper layer the result of a transfer. - * This callback pointer is passed when initializing the structure usb_host_transfer_t. - * - * @param param The parameter pointer, which is passed when calling the send/receive APIs. - * @param transfer The transfer information; See the structure usb_host_transfer_t. - * @param status A USB error code or kStatus_USB_Success. - */ -typedef void (*host_inner_transfer_callback_t)(void *param, struct _usb_host_transfer *transfer, usb_status_t status); - -/*! @brief USB host endpoint information structure */ -typedef struct _usb_host_ep -{ - usb_descriptor_endpoint_t *epDesc; /*!< Endpoint descriptor pointer*/ - uint8_t *epExtension; /*!< Endpoint extended descriptor pointer*/ - uint16_t epExtensionLength; /*!< Extended descriptor length*/ -} usb_host_ep_t; - -/*! @brief USB host interface information structure */ -typedef struct _usb_host_interface -{ - usb_host_ep_t epList[USB_HOST_CONFIG_INTERFACE_MAX_EP]; /*!< Endpoint array*/ - usb_descriptor_interface_t *interfaceDesc; /*!< Interface descriptor pointer*/ - uint8_t *interfaceExtension; /*!< Interface extended descriptor pointer*/ - uint16_t interfaceExtensionLength; /*!< Extended descriptor length*/ - uint8_t interfaceIndex; /*!< The interface index*/ - uint8_t alternateSettingNumber; /*!< The interface alternate setting value*/ - uint8_t epCount; /*!< Interface's endpoint number*/ -} usb_host_interface_t; - -/*! @brief USB host configuration information structure */ -typedef struct _usb_host_configuration -{ - usb_host_interface_t interfaceList[USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE]; /*!< Interface array*/ - usb_descriptor_configuration_t *configurationDesc; /*!< Configuration descriptor pointer*/ - uint8_t *configurationExtension; /*!< Configuration extended descriptor pointer*/ - uint16_t configurationExtensionLength; /*!< Extended descriptor length*/ - uint8_t interfaceCount; /*!< The configuration's interface number*/ -} usb_host_configuration_t; - -/*! @brief USB host pipe common structure */ -typedef struct _usb_host_pipe -{ - struct _usb_host_pipe *next; /*!< Link the idle pipes*/ - usb_device_handle deviceHandle; /*!< This pipe's device's handle*/ - uint16_t currentCount; /*!< For KHCI transfer*/ - uint16_t nakCount; /*!< Maximum NAK count*/ - uint16_t maxPacketSize; /*!< Maximum packet size*/ - uint16_t interval; /*!< FS/LS: frame unit; HS: micro-frame unit*/ - uint8_t open; /*!< 0 - closed, 1 - open*/ - uint8_t nextdata01; /*!< Data toggle*/ - uint8_t endpointAddress; /*!< Endpoint address*/ - uint8_t direction; /*!< Pipe direction*/ - uint8_t pipeType; /*!< Pipe type, for example USB_ENDPOINT_BULK*/ - uint8_t numberPerUframe; /*!< Transaction number per micro-frame*/ -} usb_host_pipe_t; - -/*! @brief USB host transfer structure */ -typedef struct _usb_host_transfer -{ - struct _usb_host_transfer *next; /*!< The next transfer structure*/ - uint8_t *transferBuffer; /*!< Transfer data buffer*/ - uint32_t transferLength; /*!< Transfer data length*/ - uint32_t transferSofar; /*!< Length transferred so far*/ - host_inner_transfer_callback_t callbackFn; /*!< Transfer callback function*/ - void *callbackParam; /*!< Transfer callback parameter*/ - usb_host_pipe_t *transferPipe; /*!< Transfer pipe pointer*/ - usb_setup_struct_t *setupPacket; /*!< Set up packet buffer*/ - uint8_t direction; /*!< Transfer direction; it's values are USB_OUT or USB_IN*/ - uint8_t setupStatus; /*!< Set up the transfer status*/ - union - { - uint32_t unitHead; /*!< xTD head for this transfer*/ - int32_t transferResult; /*!< KHCI transfer result */ - } union1; - - union - { - uint32_t unitTail; /*! 0U)) -/*! - * @brief Send a bus or device suspend request. - * - * This function is used to send a bus or device suspend request. - * - * @param[in] hostHandle The host handle. - * @param[in] deviceHandle The device handle. - * - * @retval kStatus_USB_Success Request successfully. - * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_Error There is no idle transfer. - * Or, the deviceHandle is invalid. - * Or, the request is invalid. - */ -extern usb_status_t USB_HostSuspendDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle); - -/*! - * @brief Send a bus or device resume request. - * - * This function is used to send a bus or device resume request. - * - * @param[in] hostHandle The host handle. - * @param[in] deviceHandle The device handle. - * - * @retval kStatus_USB_Success Request successfully. - * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_Error There is no idle transfer. - * Or, the deviceHandle is invalid. - * Or, the request is invalid. - */ -extern usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle); -#if ((defined(USB_HOST_CONFIG_LPM_L1)) && (USB_HOST_CONFIG_LPM_L1 > 0U)) -/*! - * @brief Send a bus or device suspend request. - * - * This function is used to send a bus or device suspend request. - * - * @param[in] hostHandle The host handle. - * @param[in] deviceHandle The device handle. - *@param[in] sleeptype Bus suspend or single device suspend. - * - * @retval kStatus_USB_Success Request successfully. - * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_Error There is no idle transfer. - * Or, the deviceHandle is invalid. - * Or, the request is invalid. - */ -extern usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle, - usb_device_handle deviceHandle, - uint8_t sleeptype); - -/*! - * @brief Send a bus or device resume request. - * - * This function is used to send a bus or device resume request. - * - * @param[in] hostHandle The host handle. - * @param[in] deviceHandle The device handle. - * *@param[in] sleeptype Bus suspend or single device suspend. - * - * @retval kStatus_USB_Success Request successfully. - * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. - * @retval kStatus_USB_Error There is no idle transfer. - * Or, the deviceHandle is invalid. - * Or, the request is invalid. - */ -extern usb_status_t USB_HostL1ResumeDeviceResquest(usb_host_handle hostHandle, - usb_device_handle deviceHandle, - uint8_t sleepType); -/*! - * @brief Update the lpm param. - * - * The function is used to configuure the lpm token. - * - * @param[in] hostHandle The host handle. - * @param[in] lpmParam HIRD vaule and whether enable remotewakeup. - * - */ -extern usb_status_t USB_HostL1SleepDeviceResquestConfig(usb_host_handle hostHandle, uint8_t *lpmParam); -#endif -/*! - * @brief Update the hardware tick. - * - * The function is used to update the hardware tick. - * - * @param[in] hostHandle The host handle. - * @param[in] tick Current hardware tick(uint is ms). - * - */ -extern usb_status_t USB_HostUpdateHwTick(usb_host_handle hostHandle, uint64_t tick); - -#endif - -/*! @}*/ - -#ifdef __cplusplus -} -#endif - -/*! @}*/ - -#endif /* _USB_HOST_H_ */ diff --git a/bsp/imxrt1052-evk/drivers/usb/host/usb_host_devices.c b/bsp/imxrt1052-evk/drivers/usb/host/usb_host_devices.c deleted file mode 100644 index 42b16e071e..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/host/usb_host_devices.c +++ /dev/null @@ -1,1414 +0,0 @@ -/* - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include "usb_host.h" -#include "usb_host_hci.h" -#include "usb_host_devices.h" - -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) -#include "usb_host_hub.h" -#endif /* USB_HOST_CONFIG_HUB */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief enumeration transfer callback function. - * - * @param param callback parameter. - * @param transfer the transfer. - * @param status transfer result status. - */ -static void USB_HostEnumerationTransferCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status); - -/*! - * @brief process the new step state. - * - * @param deviceInstance device instance pointer. - * - * @return kStatus_USB_Success or error codes - */ -static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInstance); - -/*! - * @brief process the previous step transfer result. - * - * @param deviceInstance device instance pointer. - * - * @return kStatus_USB_Success or error codes - */ -static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceInstance); - -/*! - * @brief notify the application event, the callback is registered when initializing host. - * - * @param deviceInstance device instance pointer. - * @param eventCode event code. - * - * @return kStatus_USB_Success or error codes - */ -static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInstance, uint32_t eventCode); - -/*! - * @brief allocate one address. - * - * @param hostInstance host instance pointer. - * - * @return address, 0 is invalid. - */ -static uint8_t USB_HostAllocateDeviceAddress(usb_host_instance_t *hostInstance); - -/*! - * @brief release one address. - * - * @param hostInstance host instance pointer. - * @param address releasing address. - */ -static void USB_HostReleaseDeviceAddress(usb_host_instance_t *hostInstance, uint8_t address); - -/*! - * @brief release device resource. - * - * @param hostInstance host instance pointer. - * @param deviceInstance device instance pointer. - */ -static void USB_HostReleaseDeviceResource(usb_host_instance_t *hostInstance, - usb_host_device_instance_t *deviceInstance); - -/*! - * @brief parse device configuration descriptor. - * - * @param deviceHandle device handle. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle deviceHandle); - -/*! - * @brief remove device instance from host device list. - * - * @param hostHandle host instance handle. - * @param deviceHandle device handle. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostRemoveDeviceInstance(usb_host_handle hostHandle, usb_device_handle deviceHandle); - -/*! - * @brief control the bus. - * - * This function control the host bus. - * - * @param[in] hostHandle the host handle. - * @param[in] controlType the control code, please reference to bus_event_t. - * - * @retval kStatus_USB_Success control successfully. - * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. - */ -static usb_status_t USB_HostControlBus(usb_host_handle hostHandle, uint8_t controlType); - -extern usb_status_t USB_HostStandardSetGetDescriptor(usb_host_device_instance_t *deviceInstance, - usb_host_transfer_t *transfer, - void *param); -extern usb_status_t USB_HostStandardSetAddress(usb_host_device_instance_t *deviceInstance, - usb_host_transfer_t *transfer, - void *param); -extern usb_status_t USB_HostCh9RequestCommon(usb_host_device_instance_t *deviceInstance, - usb_host_transfer_t *transfer, - uint8_t *buffer, - uint32_t bufferLen); - -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - -extern usb_status_t USB_HostHubDeviceEvent(usb_host_handle hostHandle, - usb_device_handle deviceHandle, - usb_host_configuration_handle configurationHandle, - uint32_t eventCode); - -extern uint32_t USB_HostHubGetHsHubNumber(usb_host_handle hostHandle, uint8_t parentHubNo); - -extern uint32_t USB_HostHubGetHsHubPort(usb_host_handle hostHandle, uint8_t parentHubNo, uint8_t parentPortNo); - -extern usb_status_t USB_HostHubRemovePort(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber); - -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -extern usb_host_instance_t g_UsbHostInstance[USB_HOST_CONFIG_MAX_HOST]; - -/*! @brief enumeration step process array */ -static const usb_host_enum_process_entry_t s_EnumEntries[] = \ -{ - /* kStatus_dev_initial */ - { - 0, 0, NULL, - }, - /* kStatus_DEV_GetDes8 */ - { - kStatus_DEV_SetAddress, kStatus_DEV_GetDes8, USB_HostProcessCallback, - }, - /* kStatus_DEV_SetAddress */ - { - kStatus_DEV_GetDes, kStatus_DEV_SetAddress, USB_HostProcessCallback, - }, - /* kStatus_DEV_GetDes */ - { - kStatus_DEV_GetCfg9, kStatus_DEV_GetDes, NULL, - }, - /* kStatus_DEV_GetCfg9 */ - { - kStatus_DEV_GetCfg, kStatus_DEV_GetCfg9, USB_HostProcessCallback, - }, - /* kStatus_DEV_GetCfg */ - { - kStatus_DEV_SetCfg, kStatus_DEV_GetCfg9, USB_HostProcessCallback, - }, - /* kStatus_DEV_SetCfg */ - { - kStatus_DEV_EnumDone, kStatus_DEV_SetCfg, NULL, - }, -}; - -/******************************************************************************* - * Code - ******************************************************************************/ - -static void USB_HostEnumerationTransferCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status) -{ - uint8_t nextStep = 0; - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)param; - - USB_HostFreeTransfer(deviceInstance->hostHandle, transfer); /* free transfer */ - - if (status == kStatus_USB_Success) - { - nextStep = 1; - } - else if (status == kStatus_USB_TransferStall) - { -#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) - usb_echo("no response from device\r\n"); -#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ - if (deviceInstance->stallRetries > 0) /* retry same transfer when stall */ - { - deviceInstance->stallRetries--; - } - else /* process next state when all retries stall */ - { - nextStep = 1; - } - } - else if (status == kStatus_USB_TransferCancel) - { - return; - } - else - { - if (deviceInstance->enumRetries > 0) /* next whole retry */ - { - deviceInstance->enumRetries--; - deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; - deviceInstance->configurationValue = 0; - deviceInstance->state = kStatus_DEV_GetDes8; - } - else - { -#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) - usb_echo("Device No Response\r\n"); -#endif - return; - } - } - - if (nextStep == 1) - { - deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; - if (s_EnumEntries[deviceInstance->state - 1].process == NULL) - { - deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].successState; /* next state */ - } - else - { - status = s_EnumEntries[deviceInstance->state - 1].process( - deviceInstance); /* process the previous state result */ - if (status == kStatus_USB_Success) /* process success */ - { - deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].successState; - } - else if (status == kStatus_USB_Retry) /* need retry */ - { - deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].retryState; - } - else if (status == kStatus_USB_NotSupported) /* device don't suport by the application */ - { - return; /* unrecoverable fail */ - } - else /* process error, next retry */ - { - if (deviceInstance->enumRetries > 0) /* next whole retry */ - { - deviceInstance->enumRetries--; - deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; - deviceInstance->configurationValue = 0; - deviceInstance->state = kStatus_DEV_GetDes8; - } - else - { -#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) - usb_echo("Device No Response\r\n"); -#endif - return; /* unrecoverable fail */ - } - } - } - } - - if (USB_HostProcessState(deviceInstance) != kStatus_USB_Success) /* process the new state */ - { -#ifdef HOST_ECHO - usb_echo("enumation setup error\r\n"); -#endif - return; - } -} - -static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInstance) -{ - usb_status_t status = kStatus_USB_Success; - usb_host_process_descriptor_param_t getDescriptorParam; - usb_host_transfer_t *transfer; - - /* malloc transfer */ - if (deviceInstance->state != kStatus_DEV_EnumDone) - { - if (USB_HostMallocTransfer(deviceInstance->hostHandle, &transfer) != kStatus_USB_Success) - { -#ifdef HOST_ECHO - usb_echo("error to get transfer\r\n"); -#endif - return kStatus_USB_Error; - } - transfer->callbackFn = USB_HostEnumerationTransferCallback; - transfer->callbackParam = deviceInstance; - - /* reset transfer fields */ - transfer->setupPacket->bmRequestType = 0x00; - transfer->setupPacket->wIndex = 0; - transfer->setupPacket->wLength = 0; - transfer->setupPacket->wValue = 0; - } - - switch (deviceInstance->state) - { - case kStatus_DEV_GetDes8: - case kStatus_DEV_GetDes: /* get descriptor state */ - getDescriptorParam.descriptorLength = sizeof(usb_descriptor_device_t); - if (deviceInstance->state == kStatus_DEV_GetDes8) - { - getDescriptorParam.descriptorLength = 8; - } - getDescriptorParam.descriptorBuffer = (uint8_t *)deviceInstance->deviceDescriptor; - getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_DEVICE; - getDescriptorParam.descriptorIndex = 0; - getDescriptorParam.languageId = 0; - - transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; - transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; - status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); - break; - case kStatus_DEV_SetAddress: /* set address state */ - transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_SET_ADDRESS; - status = USB_HostStandardSetAddress(deviceInstance, transfer, &deviceInstance->allocatedAddress); - break; - - case kStatus_DEV_GetCfg9: /* get 9 bytes configuration state */ - getDescriptorParam.descriptorBuffer = deviceInstance->enumBuffer; - getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE; - getDescriptorParam.descriptorIndex = deviceInstance->configurationValue; - getDescriptorParam.descriptorLength = 9; - getDescriptorParam.languageId = 0; - - transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; - transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; - status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); - break; - - case kStatus_DEV_GetCfg: /* get configuration state */ - getDescriptorParam.descriptorBuffer = deviceInstance->configurationDesc; - getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE; - getDescriptorParam.descriptorIndex = deviceInstance->configurationValue; - getDescriptorParam.descriptorLength = deviceInstance->configurationLen; - getDescriptorParam.languageId = 0; - - transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; - transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; - status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); - break; - - case kStatus_DEV_SetCfg: /* set configuration state */ - transfer->setupPacket->wValue = - USB_SHORT_TO_LITTLE_ENDIAN(deviceInstance->configuration.configurationDesc->bConfigurationValue); - transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_SET_CONFIGURATION; - status = USB_HostCh9RequestCommon(deviceInstance, transfer, NULL, 0); - break; - - case kStatus_DEV_EnumDone: /* enumeration done state */ - status = USB_HostNotifyDevice(deviceInstance, - kUSB_HostEventEnumerationDone); /* notify device enumeration done */ - if (status == kStatus_USB_Success) - { - deviceInstance->state = kStatus_DEV_AppUsed; - } - break; - - default: - break; - } - - return status; -} - -static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceInstance) -{ - usb_host_pipe_t *pipe = (usb_host_pipe_t *)deviceInstance->controlPipe; - usb_status_t status = kStatus_USB_Success; - usb_descriptor_configuration_t *configureDesc; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; - - switch (deviceInstance->state) - { - case kStatus_DEV_GetDes8: /* process get 8 bytes descriptor result */ - pipe->maxPacketSize = deviceInstance->deviceDescriptor->bMaxPacketSize0; - hostInstance->controllerTable->controllerIoctl( - hostInstance->controllerHandle, kUSB_HostUpdateControlPacketSize, deviceInstance->controlPipe); - break; - - case kStatus_DEV_SetAddress: /* process set address result */ - deviceInstance->setAddress = deviceInstance->allocatedAddress; - hostInstance->controllerTable->controllerIoctl( - hostInstance->controllerHandle, kUSB_HostUpdateControlEndpointAddress, deviceInstance->controlPipe); - break; - - case kStatus_DEV_GetDes: /* process set address result */ - /* NULL */ - break; - - case kStatus_DEV_GetCfg9: /* process get 9 bytes configuration result */ - configureDesc = (usb_descriptor_configuration_t *)&deviceInstance->enumBuffer[0]; - - deviceInstance->configurationLen = USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(configureDesc->wTotalLength); - if (deviceInstance->configurationDesc != NULL) - { -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - SDK_Free(deviceInstance->configurationDesc); -#else - USB_OsaMemoryFree(deviceInstance->configurationDesc); -#endif - deviceInstance->configurationDesc = NULL; - } - /* for KHCI, the start address and the length should be 4 byte align */ - if ((deviceInstance->configurationLen & 0x03) != 0) - { -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - deviceInstance->configurationDesc = - (uint8_t *)SDK_Malloc((deviceInstance->configurationLen & 0xFFFFFFFCu) + 4, USB_CACHE_LINESIZE); -#else - deviceInstance->configurationDesc = - (uint8_t *)USB_OsaMemoryAllocate((deviceInstance->configurationLen & 0xFFFFFFFCu) + 4); -#endif - } - else - { -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - deviceInstance->configurationDesc = - (uint8_t *)SDK_Malloc(deviceInstance->configurationLen, USB_CACHE_LINESIZE); -#else - deviceInstance->configurationDesc = (uint8_t *)USB_OsaMemoryAllocate(deviceInstance->configurationLen); -#endif - } - if (deviceInstance->configurationDesc == NULL) - { - return kStatus_USB_Error; - } - break; - - case kStatus_DEV_GetCfg: /* process get cofiguration result */ - if (((usb_descriptor_configuration_t *)deviceInstance->configurationDesc)->bMaxPower > - USB_HOST_CONFIG_MAX_POWER) - { - return kStatus_USB_Error; - } - deviceInstance->configurationValue++; - if (USB_HostParseDeviceConfigurationDescriptor(deviceInstance) != - kStatus_USB_Success) /* parse configuration descriptor */ - { - return kStatus_USB_Error; - } - - status = USB_HostNotifyDevice(deviceInstance, kUSB_HostEventAttach); - - if (status != kStatus_USB_Success) - { - /* next configuration */ - if (deviceInstance->configurationValue < deviceInstance->deviceDescriptor->bNumConfigurations) - { - return kStatus_USB_Retry; - } - else - { - USB_HostNotifyDevice(deviceInstance, - kUSB_HostEventNotSupported); /* notify application device is not supported */ - return kStatus_USB_NotSupported; - } - } - break; - - case kStatus_DEV_SetCfg: - /* NULL */ - break; - - default: - break; - } - - return status; -} - -static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInstance, uint32_t eventCode) -{ - usb_host_instance_t *hostInstance; - usb_status_t status1 = kStatus_USB_Error; -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - usb_status_t status2 = kStatus_USB_Error; - uint8_t haveHub; - uint8_t haveNoHub; - uint8_t interfaceIndex; -#endif /* USB_HOST_CONFIG_HUB */ - - if (deviceInstance == NULL) - { - return kStatus_USB_InvalidHandle; - } - hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; - -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - haveHub = 0; - haveNoHub = 0; - for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) - { - if (((usb_descriptor_interface_t *)deviceInstance->configuration.interfaceList[interfaceIndex].interfaceDesc) - ->bInterfaceClass == USB_HOST_HUB_CLASS_CODE) - { - haveHub = 1; - } - else - { - haveNoHub = 1; - } - } - - if ((haveNoHub == 1) && (hostInstance->deviceCallback != NULL)) - { - status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration, - eventCode); /* notify application event */ - } - if (haveHub) - { - status2 = USB_HostHubDeviceEvent(hostInstance, deviceInstance, &deviceInstance->configuration, - eventCode); /* notify hub event */ - } - - if ((status1 == kStatus_USB_Success) || (status2 == kStatus_USB_Success)) /* the device is supported */ - { - return kStatus_USB_Success; - } - else if (eventCode == kUSB_HostEventAttach) /* attach event */ - { - status1 = kStatus_USB_NotSupported; - } - else - { - status1 = kStatus_USB_Error; - } -#else - if (hostInstance->deviceCallback != NULL) - { - status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration, - eventCode); /* call host callback function */ - } -#endif - return status1; -} - -static uint8_t USB_HostAllocateDeviceAddress(usb_host_instance_t *hostInstance) -{ - uint8_t address = 0; - uint8_t addressIndex; - uint8_t addressBitIndex; - for (addressIndex = 0; addressIndex < 8; ++addressIndex) /* find the idle address postion byte */ - { - if (hostInstance->addressBitMap[addressIndex] != 0xFF) - { - break; - } - } - if (addressIndex < 8) - { - for (addressBitIndex = 0; addressBitIndex < 8; ++addressBitIndex) /* find the idle address position bit */ - { - if (!(hostInstance->addressBitMap[addressIndex] & (0x01u << addressBitIndex))) - { - hostInstance->addressBitMap[addressIndex] |= (0x01u << addressBitIndex); /* set the allocated bit */ - address = addressIndex * 8 + addressBitIndex + 1; /* the address minimum is 1 */ - break; - } - } - } - return address; -} - -static void USB_HostReleaseDeviceAddress(usb_host_instance_t *hostInstance, uint8_t address) -{ - USB_HostLock(); - hostInstance->addressBitMap[(uint32_t)(address - 1) >> 3] &= - (~(0x01u << (((uint32_t)address - 1) & 0x07U))); /* reset the allocated bit */ - USB_HostUnlock(); -} - -static usb_status_t USB_HostRemoveDeviceInstance(usb_host_handle hostHandle, usb_device_handle deviceHandle) -{ - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - usb_host_device_instance_t *currentInstance; - usb_host_device_instance_t *prevInstance; - if ((hostHandle == NULL) || (deviceHandle == NULL)) - { - return kStatus_USB_InvalidHandle; - } - - /* search and remove device instance */ - prevInstance = (usb_host_device_instance_t *)hostInstance->deviceList; - if (prevInstance == deviceHandle) - { - hostInstance->deviceList = prevInstance->next; - return kStatus_USB_Success; - } - else - { - currentInstance = prevInstance->next; - } - - while (currentInstance != NULL) - { - if (currentInstance == deviceHandle) - { - prevInstance->next = currentInstance->next; - return kStatus_USB_Success; - } - prevInstance = currentInstance; - currentInstance = currentInstance->next; - } - - return kStatus_USB_Success; -} - -static void USB_HostReleaseDeviceResource(usb_host_instance_t *hostInstance, usb_host_device_instance_t *deviceInstance) -{ -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - uint8_t level = 0; -#endif - -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - if (deviceInstance == hostInstance->suspendedDevice) - { - hostInstance->suspendedDevice = NULL; - } -#endif - /* release device's address */ - if (deviceInstance->setAddress != 0) - { - USB_HostReleaseDeviceAddress(hostInstance, deviceInstance->setAddress); - } - else - { - if (deviceInstance->allocatedAddress != 0) - { - USB_HostReleaseDeviceAddress(hostInstance, deviceInstance->allocatedAddress); - } - } - - /* close control pipe */ - if (deviceInstance->controlPipe != NULL) - { - USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL); - if (USB_HostClosePipe(hostInstance, deviceInstance->controlPipe) != kStatus_USB_Success) - { -#ifdef HOST_ECHO - usb_echo("error when close pipe\r\n"); -#endif - } - deviceInstance->controlPipe = NULL; - } - - /* free configuration buffer */ - if (deviceInstance->configurationDesc != NULL) - { -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - SDK_Free(deviceInstance->configurationDesc); -#else - USB_OsaMemoryFree(deviceInstance->configurationDesc); -#endif - } - -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - level = deviceInstance->level; -#endif -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - SDK_Free(deviceInstance->deviceDescriptor); -#else - USB_OsaMemoryFree(deviceInstance->deviceDescriptor); -#endif - /* free device instance buffer */ - USB_OsaMemoryFree(deviceInstance); - -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - /* enable controller attach if root hub */ - if (level == 1) - { - USB_HostControlBus(hostInstance, kUSB_HostBusEnableAttach); - } -#else - /* enable controller attach */ - USB_HostControlBus(hostInstance, kUSB_HostBusEnableAttach); -#endif -} - -static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle deviceHandle) -{ - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - uint32_t endPos; - usb_descriptor_union_t *unionDes; - usb_host_interface_t *interfaceParse = NULL; - usb_host_ep_t *epParse; - uint8_t *buffer; - - if (deviceHandle == NULL) - { - return kStatus_USB_InvalidParameter; - } - - buffer = (uint8_t *)&deviceInstance->configuration; - /* clear the previous parse result, note: end_pos means buffer index here*/ - for (endPos = 0; endPos < sizeof(usb_host_configuration_t); endPos++) - { - buffer[endPos] = 0; - } - for (endPos = 0; endPos < USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE; ++endPos) - { - deviceInstance->interfaceStatus[endPos] = 0; - } - - /* parse configuration descriptor */ - unionDes = (usb_descriptor_union_t *)deviceInstance->configurationDesc; - endPos = (uint32_t)(deviceInstance->configurationDesc + deviceInstance->configurationLen); - - if ((unionDes->common.bLength == USB_DESCRIPTOR_LENGTH_CONFIGURE) && - (unionDes->common.bDescriptorType == USB_DESCRIPTOR_TYPE_CONFIGURE)) - { - /* configuration descriptor */ - deviceInstance->configuration.configurationDesc = (usb_descriptor_configuration_t *)unionDes; - deviceInstance->configuration.configurationExtensionLength = 0; - deviceInstance->configuration.configurationExtension = NULL; - deviceInstance->configuration.interfaceCount = 0; - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - while ((uint32_t)unionDes < endPos) - { - if (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) - { - if (deviceInstance->configuration.configurationExtension == NULL) - { - deviceInstance->configuration.configurationExtension = (uint8_t *)unionDes; - } - if ((unionDes->common.bDescriptorType == 0x00) || - (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - deviceInstance->configuration.configurationExtensionLength += unionDes->common.bLength; - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - } - else - { - break; - } - } - - /* interface descriptor */ - deviceInstance->configuration.interfaceCount = 0; - while ((uint32_t)unionDes < endPos) - { - if (unionDes->common.bDescriptorType == USB_DESCRIPTOR_TYPE_INTERFACE) - { - if (unionDes->interface.bAlternateSetting == 0x00) - { - if (deviceInstance->configuration.interfaceCount >= USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE) - { -#ifdef HOST_ECHO - usb_echo( - "Unsupported Device attached\r\n too many interfaces in one configuration, please increase " - "the USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE value\n"); -#endif - return kStatus_USB_Error; - } - interfaceParse = - &deviceInstance->configuration.interfaceList[deviceInstance->configuration.interfaceCount]; - deviceInstance->configuration.interfaceCount++; - interfaceParse->alternateSettingNumber = 0; - interfaceParse->epCount = 0; - interfaceParse->interfaceDesc = &unionDes->interface; - interfaceParse->interfaceExtensionLength = 0; - interfaceParse->interfaceExtension = NULL; - interfaceParse->interfaceIndex = unionDes->interface.bInterfaceNumber; - if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - while ((uint32_t)unionDes < endPos) - { - if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) && - (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) - { - if (interfaceParse->interfaceExtension == NULL) - { - interfaceParse->interfaceExtension = (uint8_t *)unionDes; - } - if ((unionDes->common.bDescriptorType == 0x00) || - (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - interfaceParse->interfaceExtensionLength += unionDes->common.bLength; - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - } - else - { - break; - } - } - - /* endpoint descriptor */ - if (interfaceParse->interfaceDesc->bNumEndpoints != 0) - { - if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) || - (interfaceParse->interfaceDesc->bNumEndpoints > USB_HOST_CONFIG_INTERFACE_MAX_EP)) - { -#ifdef HOST_ECHO - usb_echo("interface descriptor error\n"); -#endif - return kStatus_USB_Error; - } - for (; interfaceParse->epCount < interfaceParse->interfaceDesc->bNumEndpoints; - (interfaceParse->epCount)++) - { - if (((uint32_t)unionDes >= endPos) || - (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) - { -#ifdef HOST_ECHO - usb_echo("endpoint descriptor error\n"); -#endif - return kStatus_USB_Error; - } - epParse = (usb_host_ep_t *)&interfaceParse->epList[interfaceParse->epCount]; - epParse->epDesc = (usb_descriptor_endpoint_t *)unionDes; - epParse->epExtensionLength = 0; - epParse->epExtension = NULL; - if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - while ((uint32_t)unionDes < endPos) - { - if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) && - (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE)) - { - if (epParse->epExtension == NULL) - { - epParse->epExtension = (uint8_t *)unionDes; - } - if ((unionDes->common.bDescriptorType == 0x00) || - (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - epParse->epExtensionLength += unionDes->common.bLength; - unionDes = - (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - } - else - { - break; - } - } - } - } - } - else - { - if (interfaceParse == NULL) - { - return kStatus_USB_Error; /* in normal situation this cannot reach */ - } - interfaceParse->alternateSettingNumber++; - if (interfaceParse->interfaceExtension == NULL) - { - interfaceParse->interfaceExtension = (uint8_t *)unionDes; - } - if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - interfaceParse->interfaceExtensionLength += unionDes->common.bLength; - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - while ((uint32_t)unionDes < endPos) - { - if (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) - { - if ((unionDes->common.bDescriptorType == 0x00) || - (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ - { - return kStatus_USB_Error; - } - interfaceParse->interfaceExtensionLength += unionDes->common.bLength; - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - } - else - { - break; - } - } - } - } - else - { - return kStatus_USB_Error; - } - } - } - - for (endPos = 0; endPos < deviceInstance->configuration.interfaceCount; ++endPos) - { - deviceInstance->interfaceStatus[endPos] = kStatus_interface_Attached; - } - - return kStatus_USB_Success; -} - -usb_status_t USB_HostAttachDevice(usb_host_handle hostHandle, - uint8_t speed, - uint8_t hubNumber, - uint8_t portNumber, - uint8_t level, - usb_device_handle *deviceHandle) -{ - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - usb_host_device_instance_t *newInstance; -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - usb_host_device_instance_t *currentInstance; -#endif - uint8_t address; - usb_host_pipe_init_t pipeInit; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - -/* check whether is the device attached? */ -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - currentInstance = (usb_host_device_instance_t *)hostInstance->deviceList; - while (currentInstance != NULL) - { - if ((currentInstance->hubNumber == hubNumber) && (currentInstance->portNumber == portNumber)) - { - *deviceHandle = NULL; -#ifdef HOST_ECHO - usb_echo("device has attached\r\n"); -#endif - return kStatus_USB_Busy; - } - else - { - currentInstance = currentInstance->next; - } - } -#else - if (hostInstance->deviceList != NULL) - { - *deviceHandle = NULL; - usb_echo("device has attached\r\n"); - return kStatus_USB_Busy; - } -#endif - - /* Allocate new device instance */ - newInstance = (usb_host_device_instance_t *)USB_OsaMemoryAllocate(sizeof(usb_host_device_instance_t)); - if (newInstance == NULL) - { -#ifdef HOST_ECHO - usb_echo("allocate dev instance fail\r\n"); -#endif - return kStatus_USB_AllocFail; - } - - /* new instance fields init */ - newInstance->hostHandle = hostHandle; - newInstance->speed = speed; - newInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; - newInstance->enumRetries = USB_HOST_CONFIG_ENUMERATION_MAX_RETRIES; - newInstance->setAddress = 0; - newInstance->deviceAttachState = kStatus_device_Attached; -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - newInstance->deviceDescriptor = - (usb_descriptor_device_t *)SDK_Malloc(sizeof(usb_descriptor_device_t) + 9, USB_CACHE_LINESIZE); -#else - newInstance->deviceDescriptor = - (usb_descriptor_device_t *)USB_OsaMemoryAllocate(sizeof(usb_descriptor_device_t) + 9); -#endif - if (newInstance->deviceDescriptor == NULL) - { -#ifdef HOST_ECHO - usb_echo("allocate newInstance->deviceDescriptor fail\r\n"); -#endif -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - SDK_Free(newInstance->deviceDescriptor); -#else - USB_OsaMemoryFree(newInstance->deviceDescriptor); -#endif - USB_OsaMemoryFree(newInstance); - return kStatus_USB_AllocFail; - } - newInstance->enumBuffer = (uint8_t *)((uint8_t *)newInstance->deviceDescriptor + sizeof(usb_descriptor_device_t)); -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - newInstance->hubNumber = hubNumber; - newInstance->portNumber = portNumber; - newInstance->level = level; - - if ((speed != USB_SPEED_HIGH) && (level > 1)) - { - newInstance->hsHubNumber = USB_HostHubGetHsHubNumber(hostHandle, hubNumber); - newInstance->hsHubPort = USB_HostHubGetHsHubPort(hostHandle, hubNumber, portNumber); - } - else - { - newInstance->hsHubNumber = hubNumber; - newInstance->hsHubPort = portNumber; - } -#endif /* USB_HOST_CONFIG_HUB */ - - USB_HostLock(); - /* allocate address && insert to the dev list */ - address = USB_HostAllocateDeviceAddress(hostInstance); - if (address == 0) - { -#ifdef HOST_ECHO - usb_echo("allocate address fail\r\n"); -#endif - USB_HostUnlock(); -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - SDK_Free(newInstance->deviceDescriptor); -#else - USB_OsaMemoryFree(newInstance->deviceDescriptor); -#endif - USB_OsaMemoryFree(newInstance); - return kStatus_USB_Error; - } - newInstance->allocatedAddress = address; - - newInstance->next = (usb_host_device_instance_t *)hostInstance->deviceList; - hostInstance->deviceList = newInstance; - newInstance->state = kStatus_DEV_Initial; - USB_HostUnlock(); - - /* open control pipe */ - pipeInit.devInstance = newInstance; - pipeInit.pipeType = USB_ENDPOINT_CONTROL; - pipeInit.direction = 0; - pipeInit.endpointAddress = 0; - pipeInit.interval = 0; - pipeInit.maxPacketSize = 8; - pipeInit.numberPerUframe = 0; - pipeInit.nakCount = USB_HOST_CONFIG_MAX_NAK; - if (USB_HostOpenPipe(hostHandle, &newInstance->controlPipe, &pipeInit) != kStatus_USB_Success) - { - /* don't need release resource, resource is released when detach */ - *deviceHandle = newInstance; -#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) - SDK_Free(newInstance->deviceDescriptor); -#else - USB_OsaMemoryFree(newInstance->deviceDescriptor); -#endif - USB_OsaMemoryFree(newInstance); - return kStatus_USB_Error; - } - - /* start enumeration */ - newInstance->state = kStatus_DEV_GetDes8; - USB_HostProcessState(newInstance); /* process enumeration state machine */ - - *deviceHandle = newInstance; - return kStatus_USB_Success; -} - -usb_status_t USB_HostDetachDevice(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber) -{ - usb_host_device_instance_t *deviceInstance; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - - USB_HostLock(); -/* search for device instance handle */ -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; - while (deviceInstance != NULL) - { - if ((deviceInstance->hubNumber == hubNumber) && (deviceInstance->portNumber == portNumber)) - { - break; - } - deviceInstance = deviceInstance->next; - } -#else - deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; -#endif - USB_HostUnlock(); - if (deviceInstance != NULL) - { - return USB_HostDetachDeviceInternal(hostHandle, deviceInstance); /* device instance detach */ - } - return kStatus_USB_Success; -} - -usb_status_t USB_HostDetachDeviceInternal(usb_host_handle hostHandle, usb_device_handle deviceHandle) -{ - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - if ((hostHandle == NULL) || (deviceHandle == NULL)) - { - return kStatus_USB_InvalidHandle; - } - - deviceInstance->deviceAttachState = kStatus_device_Detached; /* mark the device is detached from host */ - - if (deviceInstance->state >= kStatus_DEV_Initial) /* device instance is valid */ - { - /* detach internally */ - if (deviceInstance->state < kStatus_DEV_AppUsed) /* enumeration is not done */ - { - if (deviceInstance->controlPipe != NULL) - { - USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL); - } - - /* remove device instance from host */ - USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); - USB_HostReleaseDeviceResource(hostInstance, deviceInstance); - } - else /* enumeration has be done and notifed application */ - { - USB_HostNotifyDevice(deviceInstance, kUSB_HostEventDetach); /* notify application device detach */ - } - } - - return kStatus_USB_Success; -} - -uint8_t USB_HostGetDeviceAttachState(usb_device_handle deviceHandle) -{ - return deviceHandle ? ((usb_host_device_instance_t *)deviceHandle)->deviceAttachState : 0x0; -} - -usb_status_t USB_HostValidateDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle) -{ - usb_host_device_instance_t *searchDev; - - if (deviceHandle == NULL) - { - return kStatus_USB_InvalidParameter; - } - /* search for the device */ - searchDev = (usb_host_device_instance_t *)((usb_host_instance_t *)hostHandle)->deviceList; - while ((searchDev != NULL) && ((usb_device_handle)searchDev != deviceHandle)) - { - searchDev = searchDev->next; - } - - if (searchDev) - { - return kStatus_USB_Success; - } - return kStatus_USB_Error; -} - -static usb_status_t USB_HostControlBus(usb_host_handle hostHandle, uint8_t controlType) -{ - usb_status_t status = kStatus_USB_Success; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - - status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, - &controlType); - - return status; -} - -usb_status_t USB_HostOpenDeviceInterface(usb_device_handle deviceHandle, usb_host_interface_handle interfaceHandle) -{ - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - usb_host_instance_t *hostInstance = NULL; - uint8_t interfaceIndex; - uint8_t index = 0; - - if ((deviceHandle == NULL) || (interfaceHandle == NULL)) - { - return kStatus_USB_InvalidHandle; - } - - hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; - USB_HostLock(); - /* check host_instance valid? */ - for (; index < USB_HOST_CONFIG_MAX_HOST; ++index) - { - if ((g_UsbHostInstance[index].occupied == 1) && - ((usb_host_instance_t *)(&g_UsbHostInstance[index]) == (hostInstance))) - { - break; - } - } - if (index >= USB_HOST_CONFIG_MAX_HOST) - { - USB_HostUnlock(); - return kStatus_USB_Error; - } - - /* check deviceHandle valid? */ - if (USB_HostValidateDevice(hostInstance, deviceHandle) != kStatus_USB_Success) - { - USB_HostUnlock(); - return kStatus_USB_Error; - } - - /* search interface and set the interface as opened */ - for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) - { - if (&deviceInstance->configuration.interfaceList[interfaceIndex] == interfaceHandle) - { - deviceInstance->interfaceStatus[interfaceIndex] = kStatus_interface_Opened; - break; - } - } - USB_HostUnlock(); - - return kStatus_USB_Success; -} - -usb_status_t USB_HostCloseDeviceInterface(usb_device_handle deviceHandle, usb_host_interface_handle interfaceHandle) -{ - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - usb_host_instance_t *hostInstance = NULL; - uint8_t interfaceIndex; - uint8_t removeLabel = 1; - uint8_t index = 0; - - if (deviceHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - - hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; - USB_HostLock(); - /* check host_instance valid? */ - for (; index < USB_HOST_CONFIG_MAX_HOST; ++index) - { - if ((g_UsbHostInstance[index].occupied == 1) && - ((usb_host_instance_t *)(&g_UsbHostInstance[index]) == (hostInstance))) - { - break; - } - } - if (index >= USB_HOST_CONFIG_MAX_HOST) - { - USB_HostUnlock(); - return kStatus_USB_Error; - } - - /* check deviceHandle valid? */ - if (USB_HostValidateDevice(hostInstance, deviceHandle) != kStatus_USB_Success) - { - USB_HostUnlock(); - return kStatus_USB_Error; - } - - if (interfaceHandle != NULL) - { - /* search interface and set the interface as detached */ - for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) - { - if (&deviceInstance->configuration.interfaceList[interfaceIndex] == interfaceHandle) - { - deviceInstance->interfaceStatus[interfaceIndex] = kStatus_interface_Detached; - break; - } - } - } - - if (deviceInstance->deviceAttachState == kStatus_device_Detached) /* device is removed from host */ - { - removeLabel = 1; - /* check all the interfaces of the device are not opened */ - for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) - { - if (deviceInstance->interfaceStatus[interfaceIndex] == kStatus_interface_Opened) - { - removeLabel = 0; - break; - } - } - if (removeLabel == 1) - { - /* remove device instance from host */ - USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); - } - USB_HostUnlock(); - - if (removeLabel == 1) - { - USB_HostReleaseDeviceResource((usb_host_instance_t *)deviceInstance->hostHandle, - deviceInstance); /* release device resource */ - } - } - else - { - USB_HostUnlock(); - } - - return kStatus_USB_Success; -} - -usb_status_t USB_HostRemoveDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle) -{ - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - uint8_t interfaceIndex = 0; -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - uint8_t level = 0; - uint8_t devHubNo; - uint8_t devPortNo; -#endif - - if ((hostHandle == NULL) || (deviceHandle == NULL)) - { - return kStatus_USB_InvalidHandle; - } - if (deviceInstance->hostHandle != hostHandle) - { - return kStatus_USB_InvalidParameter; - } - - if (USB_HostValidateDevice(hostInstance, deviceInstance) == kStatus_USB_Success) /* device is valid */ - { -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - devHubNo = deviceInstance->hubNumber; - devPortNo = deviceInstance->portNumber; - level = deviceInstance->level; -#endif - - deviceInstance->deviceAttachState = kStatus_device_Detached; - if (deviceInstance->state >= kStatus_DEV_Initial) /* device is valid */ - { - if (deviceInstance->state < kStatus_DEV_AppUsed) /* enumeraion is not done or application don't use */ - { - /* detach internally */ - USB_HostDetachDeviceInternal(hostHandle, deviceHandle); - } - else /* application use the device */ - { - for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; - ++interfaceIndex) - { - if (deviceInstance->interfaceStatus[interfaceIndex] == kStatus_interface_Opened) - { -#ifdef HOST_ECHO - usb_echo("error: there is class instance that is not deinited\r\n"); -#endif - break; - } - } - /* remove device instance from host */ - USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); - USB_HostReleaseDeviceResource(hostInstance, deviceInstance); /* release resource */ - } - } - -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - if (level == 1) - { - USB_HostControlBus(hostHandle, kUSB_HostBusReset); /* reset controller port */ - USB_HostControlBus(hostHandle, kUSB_HostBusRestart); /* restart controller port */ - } - else - { - USB_HostHubRemovePort(hostHandle, devHubNo, devPortNo); /* reset hub port */ - } -#else - USB_HostControlBus(hostHandle, kUSB_HostBusReset); /* reset controller port */ - USB_HostControlBus(hostHandle, kUSB_HostBusRestart); /* restart controller port */ -#endif /* USB_HOST_CONFIG_HUB */ - } - - return kStatus_USB_Success; -} diff --git a/bsp/imxrt1052-evk/drivers/usb/host/usb_host_devices.h b/bsp/imxrt1052-evk/drivers/usb/host/usb_host_devices.h deleted file mode 100644 index 422e876a12..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/host/usb_host_devices.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _USB_HOST_DEV_MNG_H_ -#define _USB_HOST_DEV_MNG_H_ - -#include "usb_host.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! - * @addtogroup usb_host_drv - * @{ - */ -/*! @brief States of device instances enumeration */ -typedef enum _usb_host_device_enumeration_status -{ - kStatus_DEV_Notinit = 0, /*!< Device is invalid */ - kStatus_DEV_Initial, /*!< Device has been processed by host driver */ - kStatus_DEV_GetDes8, /*!< Enumeration process: get 8 bytes' device descriptor */ - kStatus_DEV_SetAddress, /*!< Enumeration process: set device address */ - kStatus_DEV_GetDes, /*!< Enumeration process: get device descriptor */ - kStatus_DEV_GetCfg9, /*!< Enumeration process: get 9 bytes' configuration descriptor */ - kStatus_DEV_GetCfg, /*!< Enumeration process: get configuration descriptor */ - kStatus_DEV_SetCfg, /*!< Enumeration process: set configuration */ - kStatus_DEV_EnumDone, /*!< Enumeration is done */ - kStatus_DEV_AppUsed, /*!< This device has been used by application */ -} usb_host_device_enumeration_status_t; - -/*! @brief States of device's interface */ -typedef enum _usb_host_interface_state -{ - kStatus_interface_Attached = 1, /*!< Interface's default status */ - kStatus_interface_Opened, /*!< Interface is used by application */ - kStatus_interface_Detached, /*!< Interface is not used by application */ -} usb_host_interface_state_t; - -/*! @brief States of device */ -typedef enum _usb_host_device_state -{ - kStatus_device_Detached = 0, /*!< Device is used by application */ - kStatus_device_Attached, /*!< Device's default status */ -} usb_host_device_state_t; - -/*! @brief Device instance */ -typedef struct _usb_host_device_instance -{ - struct _usb_host_device_instance *next; /*!< Next device, or NULL */ - usb_host_handle hostHandle; /*!< Host handle */ - usb_host_configuration_t configuration; /*!< Parsed configuration information for the device */ - usb_descriptor_device_t *deviceDescriptor; /*!< Standard device descriptor */ - usb_host_pipe_handle controlPipe; /*!< Device's control pipe */ - uint8_t *configurationDesc; /*!< Configuration descriptor pointer */ - uint16_t configurationLen; /*!< Configuration descriptor length */ - uint16_t configurationValue; /*!< Configuration index */ - uint8_t interfaceStatus[USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE]; /*!< Interfaces' status, please reference to - #usb_host_interface_state_t */ - uint8_t *enumBuffer; /*!< Buffer for enumeration */ - uint8_t state; /*!< Device state for enumeration */ - uint8_t enumRetries; /*!< Re-enumeration when error in control transfer */ - uint8_t stallRetries; /*!< Re-transfer when stall */ - uint8_t speed; /*!< Device speed */ - uint8_t allocatedAddress; /*!< Temporary address for the device. When set address request succeeds, setAddress is - a value, 1 - 127 */ - uint8_t setAddress; /*!< The address has been set to the device successfully, 1 - 127 */ - uint8_t deviceAttachState; /*!< See the usb_host_device_state_t */ -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - /* hub related */ - uint8_t hubNumber; /*!< Device's first connected hub address (root hub = 0) */ - uint8_t portNumber; /*!< Device's first connected hub's port no (1 - 8) */ - uint8_t hsHubNumber; /*!< Device's first connected high-speed hub's address (1 - 8) */ - uint8_t hsHubPort; /*!< Device's first connected high-speed hub's port no (1 - 8) */ - uint8_t level; /*!< Device's level (root device = 0) */ -#endif -} usb_host_device_instance_t; - -typedef struct _usb_host_enum_process_entry -{ - uint8_t successState; /*!< When the last step is successful, the next state value */ - uint8_t retryState; /*!< When the last step need retry, the next state value */ - usb_status_t (*process)(usb_host_device_instance_t *deviceInstance); /*!< When the last step transfer is done, the - function is used to process the transfer - data */ -} usb_host_enum_process_entry_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! - * @brief Calls this function when device attach. - * - * @param hostHandle Host instance handle. - * @param speed Device speed. - * @param hubNumber Device hub no. root device's hub no. is 0. - * @param portNumber Device port no. root device's port no. is 0. - * @param level Device level. root device's level is 1. - * @param deviceHandle Return device handle. - * - * @return kStatus_USB_Success or error codes. - */ -extern usb_status_t USB_HostAttachDevice(usb_host_handle hostHandle, - uint8_t speed, - uint8_t hubNumber, - uint8_t portNumber, - uint8_t level, - usb_device_handle *deviceHandle); - -/*! - * @brief Call this function when device detaches. - * - * @param hostHandle Host instance handle. - * @param hubNumber Device hub no. root device's hub no. is 0. - * @param portNumber Device port no. root device's port no. is 0. - * - * @return kStatus_USB_Success or error codes. - */ -extern usb_status_t USB_HostDetachDevice(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber); - -/*! - * @brief Call this function when device detaches. - * - * @param hostHandle Host instance handle. - * @param deviceHandle Device handle. - * - * @return kStatus_USB_Success or error codes. - */ -extern usb_status_t USB_HostDetachDeviceInternal(usb_host_handle hostHandle, usb_device_handle deviceHandle); - -/*! - * @brief Gets the device attach/detach state. - * - * @param deviceHandle Device handle. - * - * @return 0x01 - attached; 0x00 - detached. - */ -extern uint8_t USB_HostGetDeviceAttachState(usb_device_handle deviceHandle); - -/*! - * @brief Determine whether the device is attached. - * - * @param hostHandle Host instance pointer. - * @param deviceHandle Device handle. - * - * @return kStatus_USB_Success or error codes. - */ -extern usb_status_t USB_HostValidateDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle); - -/*! @}*/ -#endif /* _USB_HOST_DEV_MNG_H_ */ diff --git a/bsp/imxrt1052-evk/drivers/usb/host/usb_host_ehci.c b/bsp/imxrt1052-evk/drivers/usb/host/usb_host_ehci.c deleted file mode 100644 index 8a31514b3a..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/host/usb_host_ehci.c +++ /dev/null @@ -1,4747 +0,0 @@ -/* - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI > 0U)) -#include "usb_host.h" -#include "usb_host_hci.h" -#include "usb_host_devices.h" -#include "fsl_device_registers.h" -#include "usb_host_ehci.h" -#include "usb_phy.h" -#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) -#include "usb_host.h" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM > 0U) - -#error The SOC does not suppoort dedicated RAM case. - -#endif - -#define USB_HOST_EHCI_BANDWIDTH_DELAY (3500U) -#define USB_HOST_EHCI_BANDWIDTH_HUB_LS_SETUP (333U) -#define USB_HOST_EHCI_BANDWIDTH_FRAME_TOTOAL_TIME (900U) - -#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) -#define USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH (18U) -#define USB_HOST_EHCI_PORTSC_PTC_J_STATE (0x01U) -#define USB_HOST_EHCI_PORTSC_PTC_K_STATE (0x02U) -#define USB_HOST_EHCI_PORTSC_PTC_SE0_NAK (0x03U) -#define USB_HOST_EHCI_PORTSC_PTC_PACKET (0x04U) -#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_HS (0x05U) -#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_FS (0x06U) -#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_LS (0x07U) -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief compute data bandwidth time. - * - * @param speed data speed. - * @param pipeType data type. - * @param direction data direction. - * @param dataLength data length. - * - *@return time value. - */ -static uint32_t USB_HostBandwidthComputeTime(uint8_t speed, uint8_t pipeType, uint8_t direction, uint32_t dataLength); - -/*! - * @brief compute current allocated bandwidth when ehci work as full-speed or low-speed host. - * - * @param ehciInstance ehci instance pointer. - * @param frameIndex frame index. - * @param frameBandwidths return frame bandwidth data. - */ -static void USB_HostBandwidthFslsHostComputeCurrent(usb_host_ehci_instance_t *ehciInstance, - uint16_t frameIndex, - uint16_t *frameBandwidth); - -/*! - * @brief compute current hub's allocated FS/LS bandwidth when ehci work as hi-speed host. - * - * @param ehciInstance ehci instance pointer. - * @param hubNumber hub address. - * @param frameIndex frame index. - * @param frameBandwidths return frame bandwidth data. - */ -static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t *ehciInstance, - uint32_t hubNumber, - uint16_t frameIndex, - uint8_t frameBandwidths[8]); - -/*! - * @brief compute current allocated HS bandwidth when ehci work as hi-speed host. - * - * @param ehciInstance ehci instance pointer. - * @param frameIndex frame index. - * @param frameBandwidths return frame bandwidth data. - */ -static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t *ehciInstance, - uint16_t frameIndex, - uint8_t frameBandwidths[8]); - -/*! - * @brief allocate HS bandwidth when host work as high-speed host. - * - * @param ehciInstance ehci instance pointer. - * @param uframeInterval micro-frame interval. - * @param timeData time for allocating. - * @param uframe_index_out return start uframe index. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostBandwidthHsHostAllocateHsCommon(usb_host_ehci_instance_t *ehciInstance, - uint16_t uframeInterval, - uint16_t timeData, - uint16_t *uframeIndexOut); - -/*! - * @brief allocate HS interrupt bandwidth when host work as high-speed host. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostBandwidthHsHostAllocateInterrupt(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer); - -/*! - * @brief allocate bandwidth when host work as full-speed or low-speed host. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostBandwidthFslsHostAllocate(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer); - -/*! - * @brief get the 2 power value of uint8_t. - * - * @param value input uint8_t value. - */ -static uint8_t USB_HostEhciGet2PowerValue(uint8_t value); - -/*! - * @brief memory zero. - * - * @param buffer buffer pointer. - * @param length buffer length. - */ -static void USB_HostEhciZeroMem(uint32_t *buffer, uint32_t length); - -/*! - * @brief host ehci delay. - * - * @param ehciIpBase ehci ip base address. - * @param ms millisecond. - */ -static void USB_HostEhciDelay(USBHS_Type *ehciIpBase, uint32_t ms); - -/*! - * @brief host ehci start async schedule. - * - * @param ehciInstance ehci instance pointer. - */ -static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance); - -/*! - * @brief host ehci stop async schedule. - * - * @param ehciInstance ehci instance pointer. - */ -static void USB_HostEhciStopAsync(usb_host_ehci_instance_t *ehciInstance); - -/*! - * @brief host ehci start periodic schedule. - * - * @param ehciInstance ehci instance pointer. - */ -static void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance); - -/*! - * @brief host ehci stop periodic schedule. - * - * @param ehciInstance ehci instance pointer. - */ -static void USB_HostEhciStopPeriodic(usb_host_ehci_instance_t *ehciInstance); - -/*! - * @brief initialize the qtd for one transfer. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * @param transfer transfer information. - * - *@return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer, - usb_host_transfer_t *transfer); - -/*! - * @brief release the qtd list. - * - * @param ehciInstance ehci instance pointer. - * @param ehciQtdStart qtd list start pointer. - * @param ehciQtdEnd qtd list end pointer. - * - *@return the transfer's length. - */ -static uint32_t USB_HostEhciQtdListRelease(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_qtd_t *ehciQtdStart, - usb_host_ehci_qtd_t *ehciQtdEnd); - -/*! - * @brief de-initialize qh's linking qtd list. - * 1. remove qtd from qh; 2. remove transfer from qh; 3. release qtd; 4. transfer callback. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe. - * - *@return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciQhQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer); - -/*! - * @brief de-initialize transfer's linking qtd list. - * 1. stop this qh schedule; 2. remove qtd from qh; 3. remove transfer from qh; 4. release qtd; 5. transfer callback; 6. - *start this qh schedule. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * @param transfer transfer information. - * - *@return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciTransferQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer, - usb_host_transfer_t *transfer); - -/*! - * @brief initialize QH when opening one control, bulk or interrupt pipe. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciQhInit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); - -/*! - * @brief de-initialize QH when closing one control, bulk or interrupt pipe. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciQhDeinit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); - -/*! - * @brief add qh to one frame entry. - * - * @param ehciInstance ehci instance pointer. - * @param entryPointerValue entry pointer value. - * @param framePos frame index. - * @param uframeInterval micro-frame interval. - */ -static void USB_HostEhciAddQhToFrame(usb_host_ehci_instance_t *ehciInstance, - uint32_t entryPointerValue, - uint16_t framePos, - uint16_t uframeInterval); - -/*! - * @brief remove entry from frame list. - * - * @param ehciInstance ehci instance pointer. - * @param entryPointerValue entry pointer value. - * @param framePos frame index. - */ -static void USB_HostEhciRemoveFromFrame(usb_host_ehci_instance_t *ehciInstance, - uint32_t entryPointerValue, - uint16_t framePos); - -#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) -/*! - * @brief add sitd array to the frame list. - * - * @param ehciInstance ehci instance pointer. - * @param entryPointerValue entry pointer value. - * @param startEntryPointer sitd entry pointer. - */ -static void USB_HostEhciLinkSitd(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer, - void *startEntryPointer); - -/*! - * @brief initialize sitd array for one transfer. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * @param transfer transfer information. - */ -static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer, - usb_host_transfer_t *transfer); - -/*! - * @brief release sitd list. - * - * @param ehciInstance ehci instance pointer. - * @param startSitdPointer start sitd pointer. - * @param endSitdPointer end sitd pointer. - * - * @return transfer's result length. - */ -static uint32_t USB_HostEhciSitdArrayRelease(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_sitd_t *startSitdPointer, - usb_host_ehci_sitd_t *endSitdPointer); - -/*! - * @brief de-initialize sitd list. - * 1. remove transfer; 2. remove sitd from frame list and release sitd; 3. transfer callback - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciSitdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer); -#endif /* USB_HOST_CONFIG_EHCI_MAX_SITD */ - -#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) -/*! - * @brief compute the frame index when inserting itd. - * - * @param ehciInstance ehci instance pointer. - * @param lastLinkUframe last inserted micro-frame. - * @param startUframe start micro-frame. - * @param uframeInterval micro-frame interval. - * - * @return frame index - */ -static uint32_t USB_HostEhciGetItdLinkFrame(usb_host_ehci_instance_t *ehciInstance, - uint32_t lastLinkUframe, - uint16_t startUframe, - uint16_t uframeInterval); - -/*! - * @brief initialize itd list for one transfer. - * 1. initialize itd list; 2. insert itd to frame list. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * @param transfer transfer information. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer, - usb_host_transfer_t *transfer); - -/*! - * @brief release itd list. - * - * @param ehciInstance ehci instance pointer. - * @param startItdPointer start itd pointer. - * @param endItdPointer end itd pointer. - * - * @return transfer's result length. - */ -static uint32_t USB_HostEhciItdArrayRelease(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_itd_t *startItdPointer, - usb_host_ehci_itd_t *endItdPointer); - -/*! - * @brief de-initialize itd list. - * 1. remove transfer; 2. remove itd from frame list and release itd; 3. transfer callback - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciItdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer); -#endif /* USB_HOST_CONFIG_EHCI_MAX_ITD */ - -/*! - * @brief open control or bulk pipe. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciOpenControlBulk(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer); - -/*! - * @brief close control or bulk pipe. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciCloseControlBulk(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer); - -/*! - * @brief open interrupt pipe. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciOpenInterrupt(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer); - -/*! - * @brief close interrupt pipe. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciCloseInterrupt(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer); - -#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ - ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) -/*! - * @brief open iso pipe. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciOpenIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); - -/*! - * @brief close iso pipe. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciCloseIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); - -/*! - * @brief allocate HS iso bandwidth when host work as high-speed host. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer); - -#endif - -/*! - * @brief reset ehci ip. - * - * @param ehciInstance ehci instance pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciResetIP(usb_host_ehci_instance_t *ehciInstance); - -/*! - * @brief start ehci ip. - * - * @param ehciInstance ehci instance pointer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciStartIP(usb_host_ehci_instance_t *ehciInstance); - -/*! - * @brief cancel pipe's transfers. - * - * @param ehciInstance ehci instance pointer. - * @param ehciPipePointer ehci pipe pointer. - * @param transfer the canceling transfer. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer, - usb_host_transfer_t *transfer); - -/*! - * @brief control ehci bus. - * - * @param ehciInstance ehci instance pointer. - * @param bus_control control code. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl); - -/*! - * @brief ehci transaction done process function. - * - * @param ehciInstance ehci instance pointer. - */ -void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance); - -/*! - * @brief ehci port change interrupt process function. - * - * @param ehciInstance ehci instance pointer. - */ -static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance); - -/*! - * @brief ehci timer0 interrupt process function. - * cancel control/bulk transfer that time out. - * - * @param ehciInstance ehci instance pointer. - */ -static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance); - -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) -/*! - * @brief ehci timer1 interrupt process function. - * cancel control/bulk transfer that time out. - * - * @param ehciInstance ehci instance pointer. - */ -static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance); -#endif - -#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) -/*! - * @brief suspend bus. - * - * @param ehciInstance ehci instance pointer. - */ -static void USB_HostEhciSuspendBus(usb_host_ehci_instance_t *ehciInstance); - -/*! - * @brief resume bus. - * - * @param ehciInstance ehci instance pointer. - */ -static void USB_HostEhciResumeBus(usb_host_ehci_instance_t *ehciInstance); - -extern usb_status_t USB_HostStandardSetGetDescriptor(usb_host_device_instance_t *deviceInstance, - usb_host_transfer_t *transfer, - void *param); -#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* EHCI controller driver instances. */ -#if (USB_HOST_CONFIG_EHCI == 1U) -USB_RAM_ADDRESS_ALIGNMENT(4096) -USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList1[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4]; - -#define USB_HOST_EHCI_FRAME_LIST_ARRAY \ - { \ - &s_UsbHostEhciFrameList1[0] \ - } - -USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData1; -#define USB_HOST_EHCI_DATA_ARRAY \ - { \ - &s_UsbHostEhciData1 \ - } -#elif(USB_HOST_CONFIG_EHCI == 2U) -USB_RAM_ADDRESS_ALIGNMENT(4096) -USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList1[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4]; -USB_RAM_ADDRESS_ALIGNMENT(4096) -USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList2[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4]; -#define USB_HOST_EHCI_FRAME_LIST_ARRAY \ - { \ - &s_UsbHostEhciFrameList1[0], &s_UsbHostEhciFrameList2[0] \ - } - -USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData1; -USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData2; -#define USB_HOST_EHCI_DATA_ARRAY \ - { \ - &s_UsbHostEhciData1, &s_UsbHostEhciData2 \ - } -#else -#error "Please increase the instance count." -#endif - -static uint8_t s_SlotMaxBandwidth[8] = {125, 125, 125, 125, 125, 125, 50, 0}; - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! -* @brief EHCI NC get USB NC bass address. -* -* This function is used to get USB NC bass address. -* -* @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. -* -* @retval USB NC bass address. -*/ -#if (defined(USB_HOST_CONFIG_LOW_POWER_MODE) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) -void *USB_EhciNCGetBase(uint8_t controllerId) -{ - void *usbNCBase = NULL; -#if ((defined FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) - uint32_t instance; - uint32_t newinstance = 0; - uint32_t usbnc_base_temp[] = USBNC_BASE_ADDRS; - uint32_t usbnc_base[] = USBNC_BASE_ADDRS; - - if (controllerId < kUSB_ControllerEhci0) - { - return NULL; - } - - controllerId = controllerId - kUSB_ControllerEhci0; - - for (instance = 0; instance < (sizeof(usbnc_base_temp) / sizeof(usbnc_base_temp[0])); instance++) - { - if (usbnc_base_temp[instance]) - { - usbnc_base[newinstance++] = usbnc_base_temp[instance]; - } - } - if (controllerId > newinstance) - { - return NULL; - } - - usbNCBase = (void *)usbnc_base[controllerId]; -#endif - return usbNCBase; -} -#endif -#endif - -#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) - -usb_status_t USB_HostEhciTestSetMode(usb_host_ehci_instance_t *ehciInstance, uint32_t testMode) -{ - uint32_t ehciPortSC; - - ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; - ehciPortSC &= ~((uint32_t)USBHS_PORTSC1_PTC_MASK); /* clear test mode bits */ - ehciPortSC |= (testMode << USBHS_PORTSC1_PTC_SHIFT); /* set test mode bits */ - ehciInstance->ehciIpBase->PORTSC1 = ehciPortSC; - return kStatus_USB_Success; -} - -static void USB_HostEhciTestSuspendResume(usb_host_ehci_instance_t *ehciInstance) -{ - uint8_t timeCount; - timeCount = 15; /* 15s */ - while (timeCount--) - { - USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); - } - USB_HostEhciSuspendBus(ehciInstance); - timeCount = 15; /* 15s */ - while (timeCount--) - { - USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); - } - - USB_HostEhciResumeBus(ehciInstance); -} - -static void USB_HostEhciTestCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status) -{ - USB_HostFreeTransfer(param, transfer); -} - -static void USB_HostEhciTestSingleStepGetDeviceDesc(usb_host_ehci_instance_t *ehciInstance, - usb_device_handle deviceHandle) -{ - usb_host_process_descriptor_param_t getDescriptorParam; - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - usb_host_transfer_t *transfer; - uint8_t timeCount; - - /* disable periodic shedule */ - USB_HostEhciStopPeriodic(ehciInstance); - - timeCount = 15; /* 15s */ - while (timeCount--) - { - USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); - } - - /* malloc one transfer */ - if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) - { -#ifdef HOST_ECHO - usb_echo("allocate transfer error\r\n"); -#endif - return; - } - - getDescriptorParam.descriptorLength = sizeof(usb_descriptor_device_t); - getDescriptorParam.descriptorLength = 18; - getDescriptorParam.descriptorBuffer = (uint8_t *)&deviceInstance->deviceDescriptor; - getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_DEVICE; - getDescriptorParam.descriptorIndex = 0; - getDescriptorParam.languageId = 0; - transfer->callbackFn = USB_HostEhciTestCallback; - transfer->callbackParam = ehciInstance->hostHandle; - transfer->setupPacket->bmRequestType = USB_REQUEST_TYPE_DIR_IN; - transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; - transfer->setupPacket->wIndex = 0; - transfer->setupPacket->wLength = 0; - transfer->setupPacket->wValue = 0; - USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); -} - -static usb_status_t USB_HostEhciSingleStepQtdListInit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer, - usb_host_transfer_t *transfer, - uint8_t setupPhase) -{ - volatile usb_host_ehci_qh_t *vltQhPointer; - usb_host_ehci_qtd_t *qtdPointer = NULL; - volatile uint32_t *entryPointer; - uint32_t qtdNumber; - uint32_t dataLength; - uint32_t dataAddress; - uint8_t index; - - /* compute the qtd number */ - qtdNumber = 1; - - vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; - /* get qtd list */ - USB_HostEhciLock(); - if (qtdNumber <= ehciInstance->ehciQtdNumber) - { - ehciInstance->ehciQtdNumber -= qtdNumber; - qtdPointer = NULL; - do - { - if (qtdPointer != NULL) - { - qtdPointer->nextQtdPointer = (uint32_t)ehciInstance->ehciQtdHead; - } - qtdPointer = ehciInstance->ehciQtdHead; - ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer; - qtdPointer->nextQtdPointer = 0; - } while (--qtdNumber); - } - else - { - USB_HostEhciUnlock(); - return kStatus_USB_Error; - } - USB_HostEhciUnlock(); - - /* int qTD */ - if (setupPhase == 1) /* setup transaction qtd init */ - { - qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; - /* dt: need set; ioc: 0; C_Page: 0; PID Code: SETUP; Status: Active */ - qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; - qtdPointer->transferResults[0] = - ((0x00000000 << EHCI_HOST_QTD_DT_SHIFT) | (8 << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | - (EHCI_HOST_PID_SETUP << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); - dataAddress = (uint32_t)(transfer->setupPacket); - qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ - /* set buffer pointer no matter data length */ - for (index = 0; index < 4; ++index) - { - qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000); - } - } - else if (setupPhase == 2) /* data transaction qtd */ - { - dataLength = transfer->transferLength; - if (dataLength != 0) - { - qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; - /* dt: need set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */ - qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; - - qtdPointer->transferResults[0] = - ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | - (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); - - dataAddress = (uint32_t)(transfer->transferBuffer); - qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ - /* set buffer pointer no matter data length */ - for (index = 0; index < 4; ++index) - { - qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000); - } - } - } - else if (setupPhase == 3) - { - /* status transaction qtd */ - qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; - /* dt: dont care; ioc: 1; C_Page: 0; PID Code: IN/OUT; Status: Active */ - qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; - - qtdPointer->transferResults[0] = - ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | - (EHCI_HOST_QTD_IOC_MASK) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); - - qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; - } - qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; - qtdPointer->transferResults[0] |= EHCI_HOST_QTD_IOC_MASK; /* set IOC */ - - /* save qtd to transfer */ - transfer->union1.unitHead = (uint32_t)qtdPointer; - transfer->union2.unitTail = (uint32_t)qtdPointer; - /* link transfer to qh */ - transfer->next = NULL; - if (vltQhPointer->ehciTransferHead == NULL) - { - transfer->next = NULL; - vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = transfer; - } - else - { - transfer->next = NULL; - vltQhPointer->ehciTransferTail->next = transfer; - vltQhPointer->ehciTransferTail = transfer; - } - - USB_HostEhciLock(); - /* link qtd to qh (link to end) */ - entryPointer = &(vltQhPointer->nextQtdPointer); - dataAddress = *entryPointer; /* dataAddress variable means entry value here */ - while ((dataAddress) && (!(dataAddress & EHCI_HOST_T_INVALID_VALUE))) - { - entryPointer = (volatile uint32_t *)dataAddress; - dataAddress = *entryPointer; - } - *entryPointer = (uint32_t)qtdPointer; - USB_HostEhciUnlock(); - USB_HostEhciStartAsync(ehciInstance); - - return kStatus_USB_Success; -} - -static void USB_HostEhciTestSingleStepGetDeviceDescData(usb_host_ehci_instance_t *ehciInstance, - usb_device_handle deviceHandle) -{ - static uint8_t buffer[USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH]; - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - usb_host_transfer_t *transfer; - uint8_t timeCount; - - USB_HostEhciStopPeriodic(ehciInstance); - - if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) - { - return; - } - transfer->callbackFn = USB_HostEhciTestCallback; - transfer->callbackParam = ehciInstance->hostHandle; - transfer->setupPacket->bmRequestType = USB_REQUEST_TYPE_DIR_IN; - transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; - transfer->setupPacket->wLength = USB_SHORT_TO_LITTLE_ENDIAN(USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH); - transfer->setupPacket->wValue = USB_SHORT_TO_LITTLE_ENDIAN((uint16_t)((uint16_t)USB_DESCRIPTOR_TYPE_DEVICE << 8)); - transfer->setupPacket->wIndex = 0; - USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 1); - - timeCount = 15; /* 15s */ - while (timeCount--) - { - USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); - } - - if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) - { - return; - } - transfer->callbackFn = USB_HostEhciTestCallback; - transfer->callbackParam = ehciInstance->hostHandle; - transfer->transferBuffer = buffer; - transfer->transferLength = USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH; - USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 2); - - if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) - { - return; - } - transfer->callbackFn = USB_HostEhciTestCallback; - transfer->callbackParam = ehciInstance->hostHandle; - transfer->transferBuffer = NULL; - transfer->transferLength = 0; - USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 3); - - timeCount = 15; /* 15s */ - while (timeCount--) - { - USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); - } - - usb_echo("test_single_step_get_dev_desc_data finished\r\n"); - - return; -} - -void USB_HostEhciTestModeInit(usb_device_handle deviceHandle) -{ - uint32_t productId; - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - usb_host_ehci_instance_t *ehciInstance = - (usb_host_ehci_instance_t *)(((usb_host_instance_t *)(deviceInstance->hostHandle))->controllerHandle); - - USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDevicePID, &productId); - - usb_echo("usb host ehci test mode init product id:0x%x\r\n", productId); - - switch (productId) - { - case 0x0101U: - USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_SE0_NAK); - break; - case 0x0102U: - USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_J_STATE); - break; - case 0x0103U: - USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_K_STATE); - break; - case 0x0104U: - USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_PACKET); - break; - case 0x0105U: - usb_echo("set test mode FORCE_ENALBE_HS\r\n"); - USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_HS); - break; - case 0x0106U: - USB_HostEhciTestSuspendResume(ehciInstance); - break; - case 0x0107U: - usb_echo("start test SINGLE_STEP_GET_DEV_DESC\r\n"); - USB_HostEhciTestSingleStepGetDeviceDesc(ehciInstance, deviceHandle); - break; - case 0x0108U: - usb_echo("start test SINGLE_STEP_GET_DEV_DESC_DATA\r\n"); - USB_HostEhciTestSingleStepGetDeviceDescData(ehciInstance, deviceHandle); - break; - default: - break; - } - - return; -} - -static void USB_HostEhciSuspendBus(usb_host_ehci_instance_t *ehciInstance) -{ - uint32_t ehciPortSC; - - USB_HostEhciLock(); - ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; - if (ehciPortSC & USBHS_PORTSC1_PE_MASK) - { - ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; - ehciPortSC &= (uint32_t)(~EHCI_PORTSC1_W1_BITS); - ehciInstance->ehciIpBase->PORTSC1 = (ehciPortSC | USBHS_PORTSC1_SUSP_MASK); - } - USB_HostEhciUnlock(); -} - -static void USB_HostEhciResumeBus(usb_host_ehci_instance_t *ehciInstance) -{ - uint32_t ehciPortSC; - - USB_HostEhciLock(); - /* Resume port */ - ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; - if (ehciPortSC & USBHS_PORTSC1_PE_MASK) - { - ehciPortSC &= (uint32_t)(~EHCI_PORTSC1_W1_BITS); - ehciInstance->ehciIpBase->PORTSC1 = (ehciPortSC | USBHS_PORTSC1_FPR_MASK); - } - USB_HostEhciUnlock(); -} -#endif - -static uint32_t USB_HostBandwidthComputeTime(uint8_t speed, uint8_t pipeType, uint8_t direction, uint32_t dataLength) -{ - uint32_t result = (3167 + ((1000 * dataLength) * 7U * 8U / 6U)) / 1000; - - if (pipeType == USB_ENDPOINT_ISOCHRONOUS) /* iso */ - { - if (speed == USB_SPEED_HIGH) - { - result = 38 * 8 * 2083 + 2083 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; - } - else if (speed == USB_SPEED_FULL) - { - if (direction == USB_IN) - { - result = 7268000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; - } - else - { - result = 6265000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; - } - } - else - { - } - } - else /* interrupt */ - { - if (speed == USB_SPEED_HIGH) - { - result = 55 * 8 * 2083 + 2083 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; - } - else if (speed == USB_SPEED_FULL) - { - result = 9107000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; - } - else if (speed == USB_SPEED_LOW) - { - if (direction == USB_IN) - { - result = 64060000 + 2000 * USB_HOST_EHCI_BANDWIDTH_HUB_LS_SETUP + 676670 * result + - USB_HOST_EHCI_BANDWIDTH_DELAY; - } - else - { - result = 6265000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; - } - } - else - { - } - } - - result /= 1000000; - if (result == 0) - { - result = 1; - } - - return result; -} - -static void USB_HostBandwidthFslsHostComputeCurrent(usb_host_ehci_instance_t *ehciInstance, - uint16_t frameIndex, - uint16_t *frameBandwidth) -{ - usb_host_ehci_pipe_t *ehciPipePointer; - - /* clear the bandwidth */ - *frameBandwidth = 0; - - ehciPipePointer = ehciInstance->ehciRunningPipeList; - while (ehciPipePointer != NULL) - { - /* only compute iso and interrupt pipe */ - if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) || - (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)) - { - /* does pipe allocate bandwidth in frameIndex frame? note: interval is power of 2. */ - if ((frameIndex >= ehciPipePointer->startFrame) && - (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) & - (uint32_t)(ehciPipePointer->pipeCommon.interval - 1)))) - { - *frameBandwidth += ehciPipePointer->dataTime; - } - } - ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; - } -} - -static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t *ehciInstance, - uint32_t hubNumber, - uint16_t frameIndex, - uint8_t frameBandwidths[8]) -{ - usb_host_ehci_pipe_t *ehciPipePointer; - uint8_t index; - uint32_t deviceInfo; - - for (index = 0; index < 8; ++index) - { - frameBandwidths[index] = 0; - } - - ehciPipePointer = ehciInstance->ehciRunningPipeList; - while (ehciPipePointer != NULL) - { - /* only compute iso and interrupt pipe */ - if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) || - (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)) - { - /* compute FS/LS bandwidth that blong to same high-speed hub, because FS/LS bandwidth is allocated from - * first parent high-speed hub */ - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, - kUSB_HostGetDeviceHSHubNumber, &deviceInfo); - if (deviceInfo != hubNumber) - { - ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; - continue; - } - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, - &deviceInfo); - if (deviceInfo == USB_SPEED_HIGH) - { - ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; - continue; - } - - /* does pipe allocate bandwidth in frameIndex frame? note: interval is power of 2. */ - if ((frameIndex >= ehciPipePointer->startFrame) && - (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) & - (uint32_t)(ehciPipePointer->pipeCommon.interval - 1)))) - { - if (ehciPipePointer->pipeCommon.pipeType == - USB_ENDPOINT_ISOCHRONOUS) /* iso bandwidth is allocated once */ - { - frameBandwidths[ehciPipePointer->startUframe + 1] += ehciPipePointer->dataTime; - } - else /* iso bandwidth is allocated three times */ - { - frameBandwidths[ehciPipePointer->startUframe + 1] += ehciPipePointer->dataTime; - frameBandwidths[ehciPipePointer->startUframe + 2] += ehciPipePointer->dataTime; - frameBandwidths[ehciPipePointer->startUframe + 3] += ehciPipePointer->dataTime; - } - } - } - ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; - } - - for (index = 0; index < 7; ++index) /* */ - { - if (frameBandwidths[index] > s_SlotMaxBandwidth[index]) - { - frameBandwidths[index + 1] += (frameBandwidths[index] - s_SlotMaxBandwidth[index]); - frameBandwidths[index] = s_SlotMaxBandwidth[index]; - } - } -} - -static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t *ehciInstance, - uint16_t frameIndex, - uint8_t frameBandwidths[8]) -{ - usb_host_ehci_pipe_t *ehciPipePointer; - uint8_t index; - uint32_t deviceInfo; - uint16_t frameInterval; - - for (index = 0; index < 8; ++index) - { - frameBandwidths[index] = 0; - } - - ehciPipePointer = ehciInstance->ehciRunningPipeList; - while (ehciPipePointer != NULL) - { - /* only compute iso and interrupt pipe */ - if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) || - (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)) - { - frameInterval = ehciPipePointer->pipeCommon.interval; - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, - &deviceInfo); - if (deviceInfo == USB_SPEED_HIGH) /* high-speed data bandwidth */ - { - /* frameInterval means micro-frame here */ - if (frameIndex >= ehciPipePointer->startFrame) - { - if ((frameInterval > 8) && - (frameIndex * 8 - ehciPipePointer->startFrame * 8 >= ehciPipePointer->startUframe)) - { - if (!((uint32_t)(frameIndex * 8 - ehciPipePointer->startFrame * 8 - - ehciPipePointer->startUframe) & - (uint32_t)(frameInterval - 1))) - { - frameBandwidths[ehciPipePointer->startUframe] += ehciPipePointer->dataTime; - } - } - else - { - for (index = ehciPipePointer->startUframe; index < 8; index += frameInterval) - { - frameBandwidths[index] += ehciPipePointer->dataTime; - } - } - } - } - else /* full-speed split bandwidth */ - { - if ((frameIndex >= ehciPipePointer->startFrame) && - (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) & (uint32_t)(frameInterval - 1)))) - { - for (index = 0; index < 8; ++index) - { - if ((uint32_t)(ehciPipePointer->uframeSmask) & - (uint32_t)(0x01 << index)) /* start-split micro-frames */ - { - frameBandwidths[index] += ehciPipePointer->startSplitTime; - } - if ((uint32_t)(ehciPipePointer->uframeCmask) & - (uint32_t)(0x01 << index)) /* complete-split micro-frames */ - { - frameBandwidths[index] += ehciPipePointer->completeSplitTime; - } - } - } - } - } - ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; - } - - for (index = 0; index < 7; ++index) /* */ - { - if (frameBandwidths[index] > s_SlotMaxBandwidth[index]) - { - frameBandwidths[index + 1] += (frameBandwidths[index] - s_SlotMaxBandwidth[index]); - frameBandwidths[index] = s_SlotMaxBandwidth[index]; - } - } -} - -/*! - * @brief allocate HS bandwidth when host work as high-speed host. - * - * @param ehciInstance ehci instance pointer. - * @param uframeInterval micro-frame interval. - * @param timeData time for allocating. - * @param uframeIndexOut return start uframe index. - * - * @return kStatus_USB_Success or error codes. - */ -static usb_status_t USB_HostBandwidthHsHostAllocateHsCommon(usb_host_ehci_instance_t *ehciInstance, - uint16_t uframeInterval, - uint16_t timeData, - uint16_t *uframeIndexOut) -{ - uint16_t uframeIntervalIndex; - uint16_t uframeIndex; - uint16_t frameIndex; - uint8_t frameTimes[8]; - - frameIndex = 0; - USB_HostBandwidthHsHostComputeCurrentHsAll( - ehciInstance, frameIndex, frameTimes); /* compute the allocated bandwidths in the frameIndex frame */ - for (uframeIntervalIndex = 0; (uframeIntervalIndex < uframeInterval); ++uframeIntervalIndex) /* start micro-frame */ - { - /* for all the micro-frame in interval uframeInterval */ - for (uframeIndex = uframeIntervalIndex; uframeIndex < (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 8); - uframeIndex += uframeInterval) - { - if (frameIndex != (uframeIndex >> 3)) - { - frameIndex = (uframeIndex >> 3); - USB_HostBandwidthHsHostComputeCurrentHsAll( - ehciInstance, frameIndex, - frameTimes); /* compute the allocated bandwidths in the new frameIndex frame */ - } - if (frameTimes[uframeIndex & 0x0007] + timeData > - s_SlotMaxBandwidth[(uframeIndex & 0x0007)]) /* micro-frame has enough idle bandwidth? */ - { - break; /* fail */ - } - } - if (uframeIndex >= (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 8)) /* success? */ - { - break; - } - } - - if (uframeIntervalIndex < uframeInterval) - { - *uframeIndexOut = (uframeIntervalIndex); - return kStatus_USB_Success; - } - else - { - return kStatus_USB_Error; - } -} - -#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ - ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) - -static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer) -{ - usb_status_t status; - uint32_t deviceInfo; - uint32_t hubNumber; - uint16_t uframeIntervalIndex = 0; - uint16_t frameIntervalIndex = 0; - uint16_t frameIndex; - uint16_t timeCompleteSplit; - uint16_t timeStartSplit; - uint32_t timeData; - uint8_t SsCsNumber = 0; - uint16_t frameInterval; - uint8_t frameTimes[8]; - uint8_t allocateOk = 1; - uint8_t index; - - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, - &deviceInfo); - - timeData = USB_HostBandwidthComputeTime( - deviceInfo, USB_ENDPOINT_ISOCHRONOUS, ehciPipePointer->pipeCommon.direction, - ehciPipePointer->pipeCommon.maxPacketSize * ehciPipePointer->pipeCommon.numberPerUframe); - /* pipe is high-speed */ - if (deviceInfo == USB_SPEED_HIGH) - { - uframeIntervalIndex = 0; - status = USB_HostBandwidthHsHostAllocateHsCommon(ehciInstance, ehciPipePointer->uframeInterval, timeData, - &uframeIntervalIndex); - if (status == kStatus_USB_Success) - { - ehciPipePointer->startFrame = (uframeIntervalIndex / 8); - ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007); - ehciPipePointer->dataTime = timeData; - - return kStatus_USB_Success; - } - } - else /* pipe is full-speed or low-speed */ - { - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime, - &deviceInfo); /* deviceInfo variable means hub think time */ - timeData += (deviceInfo * 7 / (6 * 12)); - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber, - &hubNumber); - frameInterval = ehciPipePointer->pipeCommon.interval; - - /* compute start-split and complete-split bandwidth */ - if (ehciPipePointer->pipeCommon.direction == USB_OUT) - { - timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_OUT, - ehciPipePointer->pipeCommon.maxPacketSize); - timeCompleteSplit = 0; - } - else - { - timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_IN, 1); - timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_IN, - ehciPipePointer->pipeCommon.maxPacketSize); - } - /* note: bandwidth must put in one frame */ - for (uframeIntervalIndex = 0; uframeIntervalIndex <= 5; ++uframeIntervalIndex) /* uframe interval */ - { - for (frameIntervalIndex = 0; frameIntervalIndex < frameInterval; ++frameIntervalIndex) /* frame interval */ - { - allocateOk = 1; - for (frameIndex = frameIntervalIndex; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; - frameIndex += frameInterval) /* check all the frames */ - { - /* compute start-split and complete-split number */ - SsCsNumber = (ehciPipePointer->pipeCommon.maxPacketSize + 187) / - 188; /* ss number for iso out; cs number for iso in */ - if (ehciPipePointer->pipeCommon.direction == USB_OUT) /* ISO OUT */ - { - if (uframeIntervalIndex + SsCsNumber > 8) - { - allocateOk = 0; - } - } - else - { - if (uframeIntervalIndex + 2 + SsCsNumber > - 8) /* ISO IN: there are two micro-frame interval between start-split and complete-split */ - { - allocateOk = 0; - } - } - if (allocateOk) - { - /* allocate start-split and complete-split bandwidth */ - USB_HostBandwidthHsHostComputeCurrentHsAll(ehciInstance, frameIndex, frameTimes); - if (ehciPipePointer->pipeCommon.direction == USB_OUT) /* ISO OUT */ - { - index = uframeIntervalIndex; - for (; index < (uframeIntervalIndex + SsCsNumber); ++index) - { - if (frameTimes[index] + timeStartSplit > s_SlotMaxBandwidth[index]) - { - allocateOk = 0; - break; - } - } - } - else /* ISO IN */ - { - index = uframeIntervalIndex; - if (frameTimes[index] + timeStartSplit > s_SlotMaxBandwidth[index]) - { - allocateOk = 0; - } - if (allocateOk) - { - index = - uframeIntervalIndex + - 2; /* there are two micro-frames interval between start-split and complete-split */ - for (; index < (uframeIntervalIndex + 2 + SsCsNumber); ++index) - { - if (frameTimes[index] + timeCompleteSplit > s_SlotMaxBandwidth[index]) - { - allocateOk = 0; - break; - } - } - } - } - } - - /* allocate data bandwidth */ - if (allocateOk) - { - USB_HostBandwidthHsHostComputeCurrentFsls(ehciInstance, hubNumber, frameIndex, frameTimes); - index = uframeIntervalIndex + 1; /* timeData bandwidth start position */ - /* iso must occupy all the uframe bandwidth */ - { - deviceInfo = timeData; /* note: deviceInfo variable means bandwidth here */ - while ((index < 8) && (deviceInfo > s_SlotMaxBandwidth[index])) - { - if (frameTimes[index] > 0) - { - allocateOk = 0; - break; - } - else - { - deviceInfo -= s_SlotMaxBandwidth[index]; - } - ++index; - } - } - } - if (allocateOk) - { - /* data bandwidth can be put in the frame? */ - index = uframeIntervalIndex + 1; /* timeData bandwidth start position */ - frameTimes[index] += timeData; - for (; index < 7; ++index) - { - if (frameTimes[index] > s_SlotMaxBandwidth[index]) - { - frameTimes[index + 1] += (frameTimes[index] - s_SlotMaxBandwidth[index]); - frameTimes[index] = s_SlotMaxBandwidth[index]; - } - else - { - break; - } - } - if (frameTimes[index] > s_SlotMaxBandwidth[index]) - { - allocateOk = 0; - } - } - - if (allocateOk) - { - break; - } - } - if (allocateOk) - { - break; - } - } - if (allocateOk) - { - break; - } - } - - if (allocateOk) - { - ehciPipePointer->startFrame = frameIntervalIndex; - ehciPipePointer->startUframe = uframeIntervalIndex; - ehciPipePointer->dataTime = timeData; - ehciPipePointer->startSplitTime = timeStartSplit; - ehciPipePointer->completeSplitTime = timeCompleteSplit; - if (ehciPipePointer->pipeCommon.direction == USB_OUT) - { - index = uframeIntervalIndex; - for (; index < (uframeIntervalIndex + SsCsNumber); ++index) - { - ehciPipePointer->uframeSmask = (uint32_t)ehciPipePointer->uframeSmask | (uint32_t)(0x01 << index); - } - } - else - { - index = uframeIntervalIndex; - ehciPipePointer->uframeSmask = (uint32_t)ehciPipePointer->uframeSmask | (uint32_t)(0x01 << index); - index = uframeIntervalIndex + 2; - for (; index < (uframeIntervalIndex + 2 + SsCsNumber); ++index) - { - ehciPipePointer->uframeCmask = (uint32_t)ehciPipePointer->uframeCmask | (uint32_t)(0x01 << index); - } - } - - return kStatus_USB_Success; - } - } - - return kStatus_USB_Error; -} - -#endif - -static usb_status_t USB_HostBandwidthHsHostAllocateInterrupt(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer) -{ - usb_status_t status; - uint32_t deviceInfo; - uint32_t hubNumber; - uint16_t uframeIntervalIndex = 0; - uint16_t frameIntervalIndex = 0; - uint16_t frameIndex; - uint16_t timeCompleteSplit; - uint16_t timeStartSplit; - uint32_t timeData; - uint8_t SsCsNumber; - uint16_t frameInterval; - uint8_t frameTimes[8]; - uint8_t allocateOk = 1; - uint8_t index; - - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, - &deviceInfo); - - timeData = USB_HostBandwidthComputeTime( - deviceInfo, USB_ENDPOINT_INTERRUPT, ehciPipePointer->pipeCommon.direction, - ehciPipePointer->pipeCommon.maxPacketSize * ehciPipePointer->pipeCommon.numberPerUframe); - /* pipe is high-speed */ - if (deviceInfo == USB_SPEED_HIGH) - { - uframeIntervalIndex = 0; - status = USB_HostBandwidthHsHostAllocateHsCommon(ehciInstance, ehciPipePointer->uframeInterval, timeData, - &uframeIntervalIndex); - if (status == kStatus_USB_Success) - { - ehciPipePointer->startFrame = (uframeIntervalIndex / 8); - ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007); - /* for HS interrupt start transaction position */ - if (ehciPipePointer->uframeInterval >= 8) - { - ehciPipePointer->uframeSmask = (0x01 << ehciPipePointer->startUframe); - } - else - { - ehciPipePointer->uframeSmask = 0x00u; - for (index = ehciPipePointer->startUframe; index < 8; index += ehciPipePointer->uframeInterval) - { - ehciPipePointer->uframeSmask |= (0x01U << index); - } - } - ehciPipePointer->dataTime = timeData; - - return kStatus_USB_Success; - } - } - else /* pipe is full-speed or low-speed */ - { - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime, - &deviceInfo); - timeData += (deviceInfo * 7 / (6 * 12)); - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber, - &hubNumber); - frameInterval = ehciPipePointer->pipeCommon.interval; - SsCsNumber = 3; /* complete split number */ - - /* compute start-split and complete-split bandwidth */ - if (ehciPipePointer->pipeCommon.direction == USB_OUT) - { - timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, - ehciPipePointer->pipeCommon.maxPacketSize) + - USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, 1); - timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, 0); - } - else - { - timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, 1); - timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, - ehciPipePointer->pipeCommon.maxPacketSize) + - USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, 0); - } - /* note: bandwidth must put in one frame */ - for (uframeIntervalIndex = 0; uframeIntervalIndex <= 4; ++uframeIntervalIndex) /* uframe interval */ - { - for (frameIntervalIndex = 0; frameIntervalIndex < frameInterval; ++frameIntervalIndex) /* frame interval */ - { - allocateOk = 1; - for (frameIndex = frameIntervalIndex; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; - frameIndex += frameInterval) /* check all the frames */ - { - /* allocate data bandwidth */ - USB_HostBandwidthHsHostComputeCurrentFsls(ehciInstance, hubNumber, frameIndex, frameTimes); - index = uframeIntervalIndex + 1; - for (; index <= (uframeIntervalIndex + 3); ++index) /* data bandwidth number is 3. - uframeIntervalIndex don't exceed 4, so - index cannot exceed 7 */ - { - if (frameTimes[index] + timeData > s_SlotMaxBandwidth[index]) - { - allocateOk = 0; - break; - } - } - - if (allocateOk) - { - USB_HostBandwidthHsHostComputeCurrentHsAll(ehciInstance, frameIndex, frameTimes); - /* allocate start_split bandwidth */ - if (frameTimes[uframeIntervalIndex] + timeStartSplit > s_SlotMaxBandwidth[uframeIntervalIndex]) - { - allocateOk = 0; - } - if (allocateOk) - { - /* allocate complete_split bandwidth */ - index = uframeIntervalIndex + 2; - /* complete-split number is normal 3. When uframeIntervalIndex is 4, complete-split number - * is 2. */ - for (; (index <= (uframeIntervalIndex + 1 + SsCsNumber)) && (index < 8); ++index) - { - if (frameTimes[index] + timeCompleteSplit > s_SlotMaxBandwidth[index]) - { - allocateOk = 0; - break; - } - } - } - } - - if (!allocateOk) - { - break; /* allocate fail */ - } - } - if (allocateOk) - { - break; - } - } - if (allocateOk) - { - break; - } - } - - if (allocateOk) - { - ehciPipePointer->startFrame = frameIntervalIndex; - ehciPipePointer->startUframe = uframeIntervalIndex; - ehciPipePointer->uframeSmask = (0x01 << ehciPipePointer->startUframe); - ehciPipePointer->uframeCmask = 0; - index = uframeIntervalIndex + 2; - for (; (index <= (uframeIntervalIndex + 1 + SsCsNumber)) && (index < 8); ++index) - { - ehciPipePointer->uframeCmask = (uint32_t)ehciPipePointer->uframeCmask | (uint32_t)(0x01 << index); - } - ehciPipePointer->dataTime = timeData; - ehciPipePointer->startSplitTime = timeStartSplit; - ehciPipePointer->completeSplitTime = timeCompleteSplit; - - return kStatus_USB_Success; - } - } - - return kStatus_USB_BandwidthFail; -} - -static usb_status_t USB_HostBandwidthFslsHostAllocate(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer) -{ - uint32_t FslsTime = 0; - uint32_t speed = 0; - uint16_t uframeIntervalIndex; - uint16_t frameIndex; - uint16_t frameInterval; - uint16_t frameTime; - - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime, - &FslsTime); - FslsTime += (FslsTime * 7 / (6 * 12)); - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed); - FslsTime = FslsTime + USB_HostBandwidthComputeTime(speed, ehciPipePointer->pipeCommon.pipeType, - ehciPipePointer->pipeCommon.direction, - ehciPipePointer->pipeCommon.maxPacketSize); - - frameInterval = ehciPipePointer->pipeCommon.interval; - for (uframeIntervalIndex = 0; uframeIntervalIndex < ehciPipePointer->uframeInterval; - ++uframeIntervalIndex) /* uframeIntervalIndex can exceed 8 */ - { - for (frameIndex = (uframeIntervalIndex >> 3); frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; - frameIndex += frameInterval) - { - USB_HostBandwidthFslsHostComputeCurrent(ehciInstance, frameIndex, &frameTime); - if (frameTime + FslsTime > USB_HOST_EHCI_BANDWIDTH_FRAME_TOTOAL_TIME) - { - break; - } - } - if (frameIndex >= USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) - { - break; - } - } - if (uframeIntervalIndex < ehciPipePointer->uframeInterval) - { - ehciPipePointer->startFrame = (uframeIntervalIndex >> 3); - ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007); - ehciPipePointer->uframeSmask = 0; /* useless */ - ehciPipePointer->uframeCmask = 0; - ehciPipePointer->dataTime = FslsTime; - - return kStatus_USB_Success; - } - - return kStatus_USB_BandwidthFail; -} - -static uint8_t USB_HostEhciGet2PowerValue(uint8_t value) -{ - if ((value == 0) || (value == 1)) - { - return value; - } - if (value & 0xf0) - { - if (value & 0x80) - { - return 128; - } - else if (value & 0x40) - { - return 64; - } - else if (value & 0x20) - { - return 32; - } - else - { - return 16; - } - } - else - { - if (value & 0x08) - { - return 8; - } - else if (value & 0x04) - { - return 4; - } - else if (value & 0x02) - { - return 2; - } - else - { - return 1; - } - } -} - -static void USB_HostEhciZeroMem(uint32_t *buffer, uint32_t length) -{ - /* note: the zero unit is uint32_t */ - while (length--) - { - *buffer = 0; - buffer++; - } -} - -static void USB_HostEhciDelay(USBHS_Type *ehciIpBase, uint32_t ms) -{ - /* note: the max delay time cannot exceed half of max value (0x4000) */ - int32_t sofStart; - int32_t SofEnd; - uint32_t distance; - - sofStart = (int32_t)(ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); - - do - { - SofEnd = (int32_t)(ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); - distance = (uint32_t)(SofEnd - sofStart + EHCI_MAX_UFRAME_VALUE + 1); - } while ((distance & EHCI_MAX_UFRAME_VALUE) < (ms * 8)); /* compute the distance between sofStart and SofEnd */ -} - -static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance) -{ - uint32_t stateSync; - - if (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK)) - { - /* the status must be same when change USBCMD->ASE */ - do - { - stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) | - (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_ASE_MASK)); - } while ((stateSync == USBHS_USBSTS_AS_MASK) || (stateSync == USBHS_USBCMD_ASE_MASK)); - - ehciInstance->ehciIpBase->ASYNCLISTADDR = (uint32_t)(ehciInstance->shedFirstQh); - ehciInstance->ehciIpBase->USBCMD |= USBHS_USBCMD_ASE_MASK; - while (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK)) - { - } - } -} - -static void USB_HostEhciStopAsync(usb_host_ehci_instance_t *ehciInstance) -{ - uint32_t stateSync; - - /* the status must be same when change USBCMD->ASE */ - do - { - stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) | - (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_ASE_MASK)); - } while ((stateSync == USBHS_USBSTS_AS_MASK) || (stateSync == USBHS_USBCMD_ASE_MASK)); - - ehciInstance->ehciIpBase->USBCMD &= (uint32_t)(~(uint32_t)USBHS_USBCMD_ASE_MASK); /* disable async schedule */ - while (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) - { - } -} - -static void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance) -{ - uint32_t stateSync; - - if (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK)) - { - /* the status must be same when change USBCMD->PSE */ - do - { - stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK) | - (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK)); - } while ((stateSync == USBHS_USBSTS_PS_MASK) || (stateSync == USBHS_USBCMD_PSE_MASK)); - ehciInstance->ehciIpBase->PERIODICLISTBASE = (uint32_t)(ehciInstance->ehciFrameList); - if (!(ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK)) - { - ehciInstance->ehciIpBase->USBCMD |= USBHS_USBCMD_PSE_MASK; /* start periodic schedule */ - } - while (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK)) - { - } - } - return; -} - -static void USB_HostEhciStopPeriodic(usb_host_ehci_instance_t *ehciInstance) -{ - uint32_t stateSync; - - /* the status must be same when change USBCMD->PSE */ - do - { - stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK) | - (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK)); - } while ((stateSync == USBHS_USBSTS_PS_MASK) || (stateSync == USBHS_USBCMD_PSE_MASK)); - - ehciInstance->ehciIpBase->USBCMD &= (~USBHS_USBCMD_PSE_MASK); /* stop periodic schedule */ - while (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK) - { - } -} - -static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer, - usb_host_transfer_t *transfer) -{ - volatile usb_host_ehci_qh_t *vltQhPointer; - usb_host_ehci_qtd_t *qtdPointer = NULL; - usb_host_ehci_qtd_t *BaseQtdPointer = NULL; - volatile uint32_t *entryPointer; - uint32_t qtdNumber; - uint32_t dataLength; - uint32_t dataAddress; - uint32_t endAddress; - uint8_t index; - - /* compute the qtd number */ - if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) - { - /* assume setup data don't exceed one qtd data size, one qtd can transfer least 16k data */ - if (transfer->transferLength == 0) - { - qtdNumber = 2; - } - else - { - qtdNumber = 3; - } - } - else - { - qtdNumber = - (((transfer->transferLength) & 0xFFFFC000U) >> 14) + (((transfer->transferLength) & 0x00003FFF) ? 1 : 0); - } - - vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; - /* get qtd list */ - USB_HostEhciLock(); - if (qtdNumber <= ehciInstance->ehciQtdNumber) - { - ehciInstance->ehciQtdNumber -= qtdNumber; - BaseQtdPointer = ehciInstance->ehciQtdHead; - qtdPointer = NULL; - do - { - if (qtdPointer != NULL) - { - qtdPointer->nextQtdPointer = (uint32_t)ehciInstance->ehciQtdHead; - } - qtdPointer = ehciInstance->ehciQtdHead; - ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer; - qtdPointer->nextQtdPointer = 0; - } while (--qtdNumber); - if (ehciInstance->ehciQtdNumber == 0) - { - ehciInstance->ehciQtdTail = NULL; - } - } - else - { - USB_HostEhciUnlock(); - return kStatus_USB_Error; - } - USB_HostEhciUnlock(); - - /* int qTD list */ - if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) - { - /* setup transaction qtd */ - qtdPointer = BaseQtdPointer; - qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; - /* dt: need set; ioc: 0; C_Page: 0; PID Code: SETUP; Status: Active */ - qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; - qtdPointer->transferResults[0] = - ((0x00000000 << EHCI_HOST_QTD_DT_SHIFT) | (8 << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | - (EHCI_HOST_PID_SETUP << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); - dataAddress = ((uint32_t)transfer->setupPacket); - qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ - /* set buffer pointer no matter data length */ - for (index = 0; index < 4; ++index) - { - qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U); - } - - /* data transaction qtd */ - dataLength = transfer->transferLength; - if (dataLength != 0) - { - qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer); - - qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; - /* dt: need set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */ - qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; - if (transfer->direction == USB_OUT) - { - qtdPointer->transferResults[0] = - ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | - (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); - } - else - { - qtdPointer->transferResults[0] = - ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | - (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); - } - - dataAddress = (uint32_t)transfer->transferBuffer; - qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ - /* set buffer pointer no matter data length */ - for (index = 0; index < 4; ++index) - { - qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U); - } - } - - /* status transaction qtd */ - qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer); - qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; - /* dt: dont care; ioc: 1; C_Page: 0; PID Code: IN/OUT; Status: Active */ - qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; - if ((dataLength == 0) || (transfer->direction == USB_OUT)) - { - qtdPointer->transferResults[0] = - ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | - (EHCI_HOST_QTD_IOC_MASK) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); - } - else - { - qtdPointer->transferResults[0] = - ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | - (EHCI_HOST_QTD_IOC_MASK) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); - } - qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; - } - else - { - dataLength = transfer->transferLength; - dataAddress = (uint32_t)transfer->transferBuffer; - qtdPointer = BaseQtdPointer; - while (1) - { - endAddress = dataAddress + (16 * 1024); - if (endAddress > (uint32_t)(transfer->transferBuffer + transfer->transferLength)) - { - endAddress = (uint32_t)(transfer->transferBuffer + transfer->transferLength); - } - - qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; - /* dt: set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */ - qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; - if (transfer->direction == USB_OUT) - { - qtdPointer->transferResults[0] = - (((endAddress - dataAddress) << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | - ((uint32_t)ehciPipePointer->pipeCommon.nextdata01 << EHCI_HOST_QTD_DT_SHIFT) | - (EHCI_HOST_QTD_CERR_MAX_VALUE << EHCI_HOST_QTD_CERR_SHIFT) | - (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); - } - else - { - qtdPointer->transferResults[0] = - (((endAddress - dataAddress) << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | - ((uint32_t)ehciPipePointer->pipeCommon.nextdata01 << EHCI_HOST_QTD_DT_SHIFT) | - (EHCI_HOST_QTD_CERR_MAX_VALUE << EHCI_HOST_QTD_CERR_SHIFT) | - (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); - } - qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ - /* set buffer pointer no matter data length */ - for (index = 0; index < 4; ++index) - { - qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U); - } - dataAddress = endAddress; /* for next qtd */ - - if (qtdPointer->nextQtdPointer == 0) - { - break; - } - qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer); - } - - qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; - qtdPointer->transferResults[0] |= EHCI_HOST_QTD_IOC_MASK; /* last one set IOC */ - } - - /* save qtd to transfer */ - transfer->union1.unitHead = (uint32_t)BaseQtdPointer; - transfer->union2.unitTail = (uint32_t)qtdPointer; - /* link transfer to qh */ - transfer->next = NULL; - if (vltQhPointer->ehciTransferHead == NULL) - { - transfer->next = NULL; - vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = transfer; - } - else - { - transfer->next = NULL; - vltQhPointer->ehciTransferTail->next = transfer; - vltQhPointer->ehciTransferTail = transfer; - } - - USB_HostEhciLock(); - /* link qtd to qh (link to end) */ - entryPointer = &(vltQhPointer->nextQtdPointer); - dataAddress = *entryPointer; /* dataAddress variable means entry value here */ - while ((dataAddress) && (!(dataAddress & EHCI_HOST_T_INVALID_VALUE))) - { - entryPointer = (volatile uint32_t *)dataAddress; - dataAddress = *entryPointer; - } - *entryPointer = (uint32_t)BaseQtdPointer; - USB_HostEhciUnlock(); - USB_HostEhciStartAsync(ehciInstance); - - return kStatus_USB_Success; -} - -static uint32_t USB_HostEhciQtdListRelease(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_qtd_t *ehciQtdStart, - usb_host_ehci_qtd_t *ehciQtdEnd) -{ - uint32_t length = 0; - usb_host_ehci_qtd_t *qtdPointer; - - ehciQtdEnd->nextQtdPointer = 0; - - /* compute remaining length */ - qtdPointer = ehciQtdStart; - while (qtdPointer != ehciQtdEnd) - { - length += - ((qtdPointer->transferResults[0] & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> EHCI_HOST_QTD_TOTAL_BYTES_SHIFT); - qtdPointer = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer; - } - qtdPointer = ehciQtdEnd; - length += ((qtdPointer->transferResults[0] & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> EHCI_HOST_QTD_TOTAL_BYTES_SHIFT); - - /* put releasing qtd to idle qtd list */ - USB_HostEhciLock(); - if (ehciInstance->ehciQtdNumber == 0) - { - ehciInstance->ehciQtdHead = ehciQtdStart; - ehciInstance->ehciQtdTail = ehciQtdEnd; - } - else - { - ehciInstance->ehciQtdTail->nextQtdPointer = (uint32_t)ehciQtdStart; - ehciInstance->ehciQtdTail = ehciQtdEnd; - } - - while (ehciQtdStart != ehciQtdEnd) - { - ehciInstance->ehciQtdNumber++; - ehciQtdStart = (usb_host_ehci_qtd_t *)ehciQtdStart->nextQtdPointer; - } - ehciInstance->ehciQtdNumber++; - USB_HostEhciUnlock(); - - return length; -} - -static usb_status_t USB_HostEhciQhQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer) -{ - volatile usb_host_ehci_qh_t *vltQhPointer; - usb_host_transfer_t *transfer; - usb_host_transfer_t *nextTransfer; - uint8_t needStop = 0; - - vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; - - USB_HostEhciLock(); /* this API is called from APP, the host task may occupy to access the same resource */ - /* remove qtd from qh */ - if ((!((uint32_t)vltQhPointer->nextQtdPointer & EHCI_HOST_T_INVALID_VALUE)) || - (!((uint32_t)vltQhPointer->currentQtdPointer & EHCI_HOST_T_INVALID_VALUE))) - { - /* need stop async schedule */ - if ((!(vltQhPointer->horizontalLinkPointer & EHCI_HOST_T_INVALID_VALUE)) && - (ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT)) - { - needStop = 1; - } - if (needStop) - { - USB_HostEhciStopAsync(ehciInstance); - } - vltQhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid current qtd */ - vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ - vltQhPointer->transferOverlayResults[0] &= (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ - if (needStop) - { - USB_HostEhciStartAsync(ehciInstance); - } - } - - /* remove transfer from the QH transfer list */ - transfer = vltQhPointer->ehciTransferHead; - vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = NULL; - USB_HostEhciUnlock(); - - /* release qtd and transfer callback*/ - while (transfer != NULL) - { - nextTransfer = transfer->next; /* the transfer is released when call back */ - transfer->transferSofar = - USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), - (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); - transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? - 0 : - (transfer->transferLength - transfer->transferSofar); - transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); - transfer = nextTransfer; - } - - return kStatus_USB_Success; -} - -static usb_status_t USB_HostEhciTransferQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer, - usb_host_transfer_t *transfer) -{ - volatile usb_host_ehci_qh_t *vltQhPointer; - usb_host_transfer_t *preSearchTransfer; - uint32_t qhNextQtdValue; - uint32_t qtdPointerEntry; - uint32_t *searchQtdEntryPointer; - - vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; - - USB_HostEhciLock(); /* this API is called from APP, the host task may occupy to access the same resource */ - /* remove qtd from qh */ - qhNextQtdValue = (uint32_t)vltQhPointer->currentQtdPointer; - qtdPointerEntry = *((uint32_t *)qhNextQtdValue + 2); /* note: qtdPointerEntry means qtd status */ - if ((qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE) || (!(qtdPointerEntry & EHCI_HOST_QTD_STATUS_ACTIVE_MASK))) - { - qhNextQtdValue = (uint32_t)vltQhPointer->nextQtdPointer; - } - if (!(qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE)) /* there is pending qtd in the qh */ - { - /* this qh don't schedule temporarily */ - if (ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT) - { - USB_HostEhciStopAsync(ehciInstance); - } - vltQhPointer->currentQtdPointer |= EHCI_HOST_T_INVALID_VALUE; /* invalid current qtd */ - vltQhPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ - if (ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT) - { - USB_HostEhciStartAsync(ehciInstance); - } - - /* remove qtd from qh one by one */ - qtdPointerEntry = transfer->union1.unitHead; - while (1) - { - /* search qh's qtd list for qtdPointerEntry */ - searchQtdEntryPointer = &qhNextQtdValue; - while (!((*searchQtdEntryPointer) & EHCI_HOST_T_INVALID_VALUE)) - { - if ((*searchQtdEntryPointer) == qtdPointerEntry) - { - *searchQtdEntryPointer = *((uint32_t *)qtdPointerEntry); /* remove the qtd from qh */ - break; - } - else - { - searchQtdEntryPointer = (uint32_t *)(*searchQtdEntryPointer); - } - } - if (qtdPointerEntry == transfer->union2.unitTail) - { - break; - } - qtdPointerEntry = *((uint32_t *)qtdPointerEntry); - } - } - - /* remove transfer from the QH transfer list */ - preSearchTransfer = vltQhPointer->ehciTransferHead; - if (preSearchTransfer == transfer) - { - vltQhPointer->ehciTransferHead = preSearchTransfer->next; - } - else - { - while (preSearchTransfer != NULL) - { - if (preSearchTransfer->next == transfer) - { - preSearchTransfer->next = transfer->next; - break; - } - else - { - preSearchTransfer = preSearchTransfer->next; - } - } - } - USB_HostEhciUnlock(); - - /* release qtd and callback */ - transfer->transferSofar = - USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), - (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); - transfer->transferSofar = - (transfer->transferLength < transfer->transferSofar) ? 0 : (transfer->transferLength - transfer->transferSofar); - transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); - - /* start this qh schedule */ - vltQhPointer->transferOverlayResults[0] &= (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ - if ((qhNextQtdValue != 0) && (!(qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE))) - { - vltQhPointer->nextQtdPointer = qhNextQtdValue; - } - - return kStatus_USB_Success; -} - -static usb_status_t USB_HostEhciQhInit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) -{ - usb_host_ehci_qh_t *qhPointer = NULL; - uint32_t address, speed, portNumber, hubNumber; - uint32_t controlBits1 = 0; - uint32_t controlBits2 = 0; - /* get qh */ - USB_HostEhciLock(); - if (ehciInstance->ehciQhList != NULL) - { - qhPointer = (usb_host_ehci_qh_t *)ehciInstance->ehciQhList; - ehciInstance->ehciQhList = - (usb_host_ehci_qh_t *)(ehciInstance->ehciQhList->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK); - } - USB_HostEhciUnlock(); - if (qhPointer == NULL) - { -#ifdef HOST_EHCO - usb_echo("get qh error\r\n"); -#endif - return kStatus_USB_Error; - } - ehciPipePointer->ehciQh = (void *)qhPointer; - - /* initialize qh */ - USB_HostEhciZeroMem((uint32_t *)qhPointer, sizeof(usb_host_ehci_qh_t) / 4); - qhPointer->horizontalLinkPointer = EHCI_HOST_T_INVALID_VALUE; - qhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; - qhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; - qhPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; - qhPointer->ehciPipePointer = ehciPipePointer; - qhPointer->timeOutLabel = 0; - qhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed); - /* initialize staticEndpointStates[0] */ - if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT) - { - /* Software should set the RL field to zero if the queue head is an interrupt endpoint. */ - controlBits1 |= ((0U << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK); - } - else - { - if (ehciPipePointer->pipeCommon.nakCount >= 16) - { - controlBits1 |= ((15U << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK); - } - else - { - controlBits1 |= - (((uint32_t)ehciPipePointer->pipeCommon.nakCount << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK); - } - } - if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) - { - if (speed != USB_SPEED_HIGH) - { - controlBits1 |= (1 << EHCI_HOST_QH_C_SHIFT); - } - controlBits1 |= (1 << EHCI_HOST_QH_DTC_SHIFT); - } - controlBits1 |= ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT); - controlBits1 |= (speed << EHCI_HOST_QH_EPS_SHIFT); - controlBits1 |= ((uint32_t)ehciPipePointer->pipeCommon.endpointAddress << EHCI_HOST_QH_ENDPT_SHIFT); - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, - &address); - controlBits1 |= (address << EHCI_HOST_QH_DEVICE_ADDRESS_SHIFT); - qhPointer->staticEndpointStates[0] = controlBits1; - if (speed == USB_SPEED_HIGH) - { - controlBits2 |= ((uint32_t)ehciPipePointer->pipeCommon.numberPerUframe << EHCI_HOST_QH_MULT_SHIFT); - } - else - { - controlBits2 |= (0x00000001U << EHCI_HOST_QH_MULT_SHIFT); - } - /*initialize staticEndpointStates[1] */ - if (speed != USB_SPEED_HIGH) - { - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber, - &hubNumber); - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubPort, - &portNumber); - } - else - { - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHubNumber, - &hubNumber); - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDevicePortNumber, - &portNumber); - } - controlBits2 |= (portNumber << EHCI_HOST_QH_PORT_NUMBER_SHIFT); - controlBits2 |= (hubNumber << EHCI_HOST_QH_HUB_ADDR_SHIFT); - controlBits2 |= ((uint32_t)ehciPipePointer->uframeCmask << EHCI_HOST_QH_UFRAME_CMASK_SHIFT); - controlBits2 |= ((uint32_t)ehciPipePointer->uframeSmask << EHCI_HOST_QH_UFRAME_SMASK_SHIFT); - qhPointer->staticEndpointStates[1] = controlBits2; - - return kStatus_USB_Success; -} - -static usb_status_t USB_HostEhciQhDeinit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) -{ - usb_host_ehci_qh_t *qhPointer; - - qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; - /* de-initialize qtd from qh */ - USB_HostEhciQhQtdListDeinit(ehciInstance, ehciPipePointer); - - /* release QH */ - USB_HostEhciLock(); - qhPointer->horizontalLinkPointer = (uint32_t)ehciInstance->ehciQhList; - ehciInstance->ehciQhList = qhPointer; - USB_HostEhciUnlock(); - - return kStatus_USB_Success; -} - -static void USB_HostEhciAddQhToFrame(usb_host_ehci_instance_t *ehciInstance, - uint32_t entryPointerValue, - uint16_t framePos, - uint16_t uframeInterval) -{ - volatile uint32_t *frameEntryPointer; - uint32_t frameEntryValue; - - /* search for the inserting point by interval */ - frameEntryPointer = (volatile uint32_t *)(&((uint32_t *)ehciInstance->ehciFrameList)[framePos]); - while (frameEntryPointer) - { - frameEntryValue = *frameEntryPointer; - if (frameEntryValue & EHCI_HOST_T_INVALID_VALUE) - { - /* insert into the end */ - *((uint32_t *)entryPointerValue) = EHCI_HOST_T_INVALID_VALUE; - *frameEntryPointer = (entryPointerValue | EHCI_HOST_POINTER_TYPE_QH); - break; - } - - if ((frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK) == entryPointerValue) - { - return; /* has inserted */ - } - if (((frameEntryValue & EHCI_HOST_POINTER_TYPE_MASK) == EHCI_HOST_POINTER_TYPE_QH) && - (((usb_host_ehci_qh_t *)(frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK)) - ->ehciPipePointer->uframeInterval <= uframeInterval)) - { - /* insert into this point */ - *((uint32_t *)entryPointerValue) = frameEntryValue; - *frameEntryPointer = (entryPointerValue | EHCI_HOST_POINTER_TYPE_QH); - return; - } - else - { - frameEntryPointer = (volatile uint32_t *)(frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK); - } - } -} - -static void USB_HostEhciRemoveFromFrame(usb_host_ehci_instance_t *ehciInstance, - uint32_t entryPointerValue, - uint16_t framePos) -{ - volatile uint32_t *frameEntryPointer; - uint32_t frameEntryValue; - - /* search for the qh/itd/sitd entry */ - frameEntryPointer = (volatile uint32_t *)(&((uint32_t *)ehciInstance->ehciFrameList)[framePos]); - - while (frameEntryPointer) - { - frameEntryValue = *frameEntryPointer; - if (frameEntryValue & EHCI_HOST_T_INVALID_VALUE) - { - return; - } - - if ((frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK) == entryPointerValue) - { - /* remove the entry */ - *frameEntryPointer = *((uint32_t *)entryPointerValue); - break; - } - else - { - frameEntryPointer = (volatile uint32_t *)(frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK); - } - } -} - -#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) -static void USB_HostEhciLinkSitd(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer, - void *startEntryPointer) -{ - usb_host_ehci_iso_t *isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; - usb_host_ehci_sitd_t *sitdPointer; - uint32_t distance; - uint32_t frameInterval; - int32_t shouldLinkFrame; - int32_t currentFrame; - - frameInterval = (ehciPipePointer->uframeInterval >> 3); - - if (isoPointer->lastLinkFrame == 0xFFFF) /* first link */ - { - currentFrame = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3); - currentFrame = ((uint32_t)(currentFrame + USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER) & - (EHCI_MAX_UFRAME_VALUE >> 3)); /* add USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER */ - /* frame should align with interval */ - currentFrame -= ehciPipePointer->startFrame; - currentFrame = - ((uint32_t)(currentFrame + frameInterval - 1) & (~(frameInterval - 1))); /* frameInterval is power of 2 */ - currentFrame += ehciPipePointer->startFrame; - } - else - { - shouldLinkFrame = isoPointer->lastLinkFrame + frameInterval; /* continuous next should link frame */ - if (shouldLinkFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3)) - { - shouldLinkFrame = shouldLinkFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1); - } - currentFrame = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3); - distance = ((shouldLinkFrame - currentFrame + (EHCI_MAX_UFRAME_VALUE >> 3) + 1) & - (EHCI_MAX_UFRAME_VALUE >> 3)); /* get the distance from shouldLinkFrame to currentFrame */ - /* shouldLinkFrame has add frameInterval, think about the align with interval, so here add (frameInterval * - * 2) */ - if ((distance <= (USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER + frameInterval * 2)) && (distance > 0)) - { - currentFrame = shouldLinkFrame; - } - else /* re-link */ - { - currentFrame = - ((uint32_t)(currentFrame + USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER) & (EHCI_MAX_UFRAME_VALUE >> 3)); - if (currentFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3)) - { - currentFrame = currentFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1); - } - /* frame should align with interval */ - currentFrame -= ehciPipePointer->startFrame; - currentFrame = ((uint32_t)(currentFrame + frameInterval - 1) & (~(frameInterval - 1))); - currentFrame += ehciPipePointer->startFrame; - } - } - if (currentFrame >= (int32_t)USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) /* frame turn around */ - { - shouldLinkFrame = - (currentFrame - USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE); /* shouldLinkFrame means inserted frame position */ - } - else - { - shouldLinkFrame = currentFrame; /* shouldLinkFrame means inserted frame position */ - } - - sitdPointer = (usb_host_ehci_sitd_t *)startEntryPointer; - while (sitdPointer) - { - sitdPointer->frameEntryIndex = shouldLinkFrame; - /* add to frame list head */ - sitdPointer->nextLinkPointer = ((uint32_t *)ehciInstance->ehciFrameList)[shouldLinkFrame]; - ((uint32_t *)ehciInstance->ehciFrameList)[shouldLinkFrame] = - ((uint32_t)sitdPointer | EHCI_HOST_POINTER_TYPE_SITD); - if (sitdPointer->nextSitdIndex == 0xFF) /* 0xFF is invalid value */ - { - break; - } - sitdPointer = &(ehciInstance->ehciSitdIndexBase[sitdPointer->nextSitdIndex]); /* next sitd */ - - shouldLinkFrame += frameInterval; - currentFrame += frameInterval; - if (shouldLinkFrame >= (int32_t)USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) - { - shouldLinkFrame = (shouldLinkFrame - USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE); - } - } - - if (currentFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3)) - { - currentFrame = currentFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1); - } - isoPointer->lastLinkFrame = currentFrame; /* save the last link frame value */ -} - -static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer, - usb_host_transfer_t *transfer) -{ - usb_host_ehci_iso_t *isoPointer; - uint32_t sitdNumber = 0; - usb_host_ehci_sitd_t *sitdPointer; - uint32_t dataLength = 0; - uint32_t sitdLength = 0; - uint32_t dataBufferValue; - uint32_t hubNumber; - uint32_t portNumber; - uint32_t address; - uint32_t tmp; - uint8_t index; - - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, - &address); - - sitdNumber = ((transfer->transferLength - 1 + (ehciPipePointer->pipeCommon.maxPacketSize)) / - (ehciPipePointer->pipeCommon.maxPacketSize)); - /* get sitd array */ - tmp = ehciPipePointer - ehciInstance->ehciPipeIndexBase; /* pipe index */ - /* USB_HostEhciLock(); */ - if (ehciInstance->ehciSitdNumber >= sitdNumber) - { - sitdPointer = ehciInstance->ehciSitdList; - transfer->union1.unitHead = (uint32_t)sitdPointer; - for (index = 1; index < sitdNumber; ++index) - { - sitdPointer->nextSitdIndex = - (((usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer) - ehciInstance->ehciSitdIndexBase); - sitdPointer = (usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer; - } - sitdPointer->nextSitdIndex = 0xFF; - ehciInstance->ehciSitdList = (usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer; - ehciInstance->ehciSitdNumber -= sitdNumber; - } - else - { - /* USB_HostEhciUnlock(); */ - return kStatus_USB_Error; - } - /* USB_HostEhciUnlock(); */ - transfer->union2.unitTail = (uint32_t)sitdPointer; - /* initialize sitd array */ - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHubNumber, - &hubNumber); - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDevicePortNumber, - &portNumber); - sitdPointer = (usb_host_ehci_sitd_t *)transfer->union1.unitHead; - dataLength = transfer->transferLength; - while (sitdNumber--) - { - USB_HostEhciZeroMem((uint32_t *)sitdPointer, 7); - sitdLength = dataLength; - if (sitdLength > ehciPipePointer->pipeCommon.maxPacketSize) - { - sitdLength = ehciPipePointer->pipeCommon.maxPacketSize; - } - dataBufferValue = (uint32_t)(transfer->transferBuffer + (transfer->transferLength - dataLength)); - dataLength -= sitdLength; /* update left data length */ - sitdPointer->transferResults[1] = dataBufferValue; - sitdPointer->transferResults[2] = ((dataBufferValue + 4 * 1024) & 0xFFFFF000U); - sitdPointer->endpointStates[0] = - (((uint32_t)ehciPipePointer->pipeCommon.direction << EHCI_HOST_SITD_DIRECTION_SHIFT) | - (portNumber << EHCI_HOST_SITD_PORT_NUMBER_SHIFT) | (hubNumber << EHCI_HOST_SITD_HUB_ADDR_SHIFT) | - ((uint32_t)ehciPipePointer->pipeCommon.endpointAddress << EHCI_HOST_SITD_ENDPT_SHIFT) | - (address << EHCI_HOST_SITD_DEVICE_ADDRESS_SHIFT)); - sitdPointer->transferResults[0] = - ((sitdLength << EHCI_HOST_SITD_TOTAL_BYTES_SHIFT) | (EHCI_HOST_SITD_STATUS_ACTIVE_MASK)); - - if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) - { - sitdPointer->endpointStates[1] = (((uint32_t)ehciPipePointer->uframeCmask << EHCI_HOST_SITD_CMASK_SHIFT) | - ((uint32_t)ehciPipePointer->uframeSmask << EHCI_HOST_SITD_SMASK_SHIFT)); - - tmp = (sitdLength + 187) / 188; - if (tmp > 1) - { - sitdPointer->transferResults[2] |= (0x01 << EHCI_HOST_SITD_TP_SHIFT); /* for iso split */ - } - else - { - sitdPointer->transferResults[2] |= (0x00 << EHCI_HOST_SITD_TP_SHIFT); /* for iso split */ - } - sitdPointer->transferResults[2] |= (tmp << EHCI_HOST_SITD_TCOUNT_SHIFT); /* for iso split */ - } - - sitdPointer->backPointer = EHCI_HOST_T_INVALID_VALUE; - - sitdPointer = (ehciInstance->ehciSitdIndexBase + sitdPointer->nextSitdIndex); - } - sitdPointer = (usb_host_ehci_sitd_t *)transfer->union2.unitTail; - sitdPointer->transferResults[0] |= (1U << EHCI_HOST_SITD_IOC_SHIFT); /* last set IOC */ - - /* link transfer to usb_host_ehci_iso_t transfer list */ - isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; - USB_HostEhciLock(); - if (isoPointer->ehciTransferHead == NULL) - { - transfer->next = NULL; - isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = transfer; - } - else - { - transfer->next = NULL; - isoPointer->ehciTransferTail->next = transfer; - isoPointer->ehciTransferTail = transfer; - } - USB_HostEhciUnlock(); - - /* link itd to frame list (note: initialize frameEntryIndex)*/ - USB_HostEhciLinkSitd(ehciInstance, ehciPipePointer, (void *)transfer->union1.unitHead); - - return kStatus_USB_Success; -} - -static uint32_t USB_HostEhciSitdArrayRelease(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_sitd_t *startSitdPointer, - usb_host_ehci_sitd_t *endSitdPointer) -{ - usb_host_ehci_sitd_t *sitdPointer = startSitdPointer; - uint32_t leftLength = 0; - /* remove itd from frame list */ - while (1) - { - /* record the transfer's result length */ - leftLength += - ((sitdPointer->transferResults[0] & EHCI_HOST_SITD_TOTAL_BYTES_MASK) >> EHCI_HOST_SITD_TOTAL_BYTES_SHIFT); - USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)sitdPointer, - sitdPointer->frameEntryIndex); /* remove from the inserted frame list */ - - /* release itd */ - /* USB_HostEhciLock(); */ - sitdPointer->nextLinkPointer = (uint32_t)ehciInstance->ehciSitdList; - ehciInstance->ehciSitdList = sitdPointer; - ehciInstance->ehciSitdNumber++; - /* USB_HostEhciUnlock(); */ - - if (sitdPointer == endSitdPointer) - { - break; - } - - sitdPointer = &(ehciInstance->ehciSitdIndexBase[sitdPointer->nextSitdIndex]); - } - - return leftLength; -} - -static usb_status_t USB_HostEhciSitdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer) -{ - usb_host_ehci_iso_t *isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; - usb_host_transfer_t *transfer; - usb_host_transfer_t *nextTransfer; - - /* firstly remove the transfer (because host task may occupy to access the resource) */ - USB_HostEhciLock(); - transfer = isoPointer->ehciTransferHead; - isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = NULL; - USB_HostEhciUnlock(); - - while (transfer != NULL) - { - nextTransfer = transfer->next; - /* remove sitd from frame list and release itd */ - transfer->transferSofar = - transfer->transferLength - USB_HostEhciSitdArrayRelease(ehciInstance, - (usb_host_ehci_sitd_t *)transfer->union1.unitHead, - (usb_host_ehci_sitd_t *)transfer->union2.unitTail); - /* transfer callback */ - transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); - /* next transfer */ - transfer = nextTransfer; - } - - return kStatus_USB_Success; -} -#endif /* USB_HOST_CONFIG_EHCI_MAX_SITD */ - -#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) -static uint32_t USB_HostEhciGetItdLinkFrame(usb_host_ehci_instance_t *ehciInstance, - uint32_t lastLinkUframe, - uint16_t startUframe, - uint16_t uframeInterval) -{ - int32_t shouldLinkUframe; - int32_t currentUframe; - int32_t distance; - - if (lastLinkUframe != 0xFFFF) - { - shouldLinkUframe = lastLinkUframe + uframeInterval; - if (shouldLinkUframe > (int32_t)EHCI_MAX_UFRAME_VALUE) - { - shouldLinkUframe = shouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1); - } - currentUframe = (ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); - distance = ((shouldLinkUframe - currentUframe + EHCI_MAX_UFRAME_VALUE + 1) & - EHCI_MAX_UFRAME_VALUE); /* get the distance */ - /* shouldLinkUframe has add uframeInterval, think about the align with interval, so here add (uframeInterval - * * 2) */ - if ((distance <= (int32_t)(USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER + (uframeInterval * 2))) && (distance > 2)) - { - currentUframe = shouldLinkUframe; - } - else /* re-link */ - { - currentUframe = - ((uint32_t)(currentUframe + USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER) & EHCI_MAX_UFRAME_VALUE); - if (currentUframe > (int32_t)EHCI_MAX_UFRAME_VALUE) - { - currentUframe = currentUframe - (EHCI_MAX_UFRAME_VALUE + 1); - } - /* uframe should align with interval */ - currentUframe -= startUframe; - currentUframe = ((uint32_t)(currentUframe + uframeInterval - 1) & - (~((uint32_t)uframeInterval - 1))); /* uframeInterval is power of 2 */ - currentUframe += startUframe; - } - } - else - { - currentUframe = (ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); - currentUframe = ((uint32_t)(currentUframe + USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER) & EHCI_MAX_UFRAME_VALUE); - /* uframe should align with interval */ - currentUframe -= startUframe; - currentUframe = ((uint32_t)(currentUframe + uframeInterval - 1) & - (~((uint32_t)uframeInterval - 1))); /* uframeInterval is power of 2 */ - currentUframe += startUframe; - } - - return currentUframe; -} - -static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer, - usb_host_transfer_t *transfer) -{ - usb_host_ehci_iso_t *isoPointer; - usb_host_ehci_itd_t *itdPointer = NULL; - usb_host_ehci_itd_t *tmpItdPointer; - uint32_t dataLength; /* the remaining data for sending */ - uint32_t transactionLength; /* the initializing transaction descriptor data length */ - uint32_t itdBufferValue; - uint32_t itdBufferBaseValue; /* for calculating PG value */ - uint32_t address; - uint32_t lastShouldLinkUframe; - uint32_t linkUframe; - uint32_t minDataPerItd = ehciPipePointer->pipeCommon.numberPerUframe * ehciPipePointer->pipeCommon.maxPacketSize; - uint8_t maxItdNumber; - uint8_t index = 0; - - isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, - &address); - - /* max needed itd number, the actual needed number may be less because micro-frame interval may be less than 8 */ - maxItdNumber = ((transfer->transferLength - 1 + minDataPerItd) / minDataPerItd); - if (ehciPipePointer->uframeInterval < 8) - { - maxItdNumber = ((maxItdNumber * ehciPipePointer->uframeInterval + 7) / 8) + 1; - } - if (maxItdNumber > ehciInstance->ehciItdNumber) - { - return kStatus_USB_Error; - } - - /* link transfer to usb_host_ehci_iso_t transfer list */ - transfer->next = NULL; - /* USB_HostEhciLock(); */ - if (isoPointer->ehciTransferHead == NULL) - { - isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = transfer; - } - else - { - isoPointer->ehciTransferTail->next = transfer; - isoPointer->ehciTransferTail = transfer; - } - /* USB_HostEhciUnlock(); */ - - dataLength = transfer->transferLength; - transfer->union1.unitHead = (uint32_t)NULL; - /* get the link micro-frame */ - lastShouldLinkUframe = USB_HostEhciGetItdLinkFrame( - ehciInstance, isoPointer->lastLinkFrame, - (uint16_t)((ehciPipePointer->startFrame << 3) + ehciPipePointer->startUframe), ehciPipePointer->uframeInterval); - if (lastShouldLinkUframe > EHCI_MAX_UFRAME_VALUE) - { - linkUframe = lastShouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1); - } - else - { - linkUframe = lastShouldLinkUframe; - } - while (dataLength) - { - /* get one idle itd */ - tmpItdPointer = ehciInstance->ehciItdList; - ehciInstance->ehciItdList = (usb_host_ehci_itd_t *)tmpItdPointer->nextLinkPointer; - ehciInstance->ehciItdNumber -= 1; - if (tmpItdPointer == NULL) - { - return kStatus_USB_Error; /* this should not reach */ - } - tmpItdPointer->nextItdPointer = NULL; - - /* use the itd */ - if (transfer->union1.unitHead == (uint32_t)NULL) /* first itd */ - { - transfer->union1.unitHead = (uint32_t)tmpItdPointer; - } - else /* link itd list */ - { - itdPointer->nextItdPointer = tmpItdPointer; - } - itdPointer = tmpItdPointer; - - /* itd has been set to all zero when releasing */ - itdBufferBaseValue = itdBufferValue = - (uint32_t)(transfer->transferBuffer + (transfer->transferLength - dataLength)); - for (index = 0; index < 7; ++index) - { - itdPointer->bufferPointers[index] = ((itdBufferBaseValue + (index * 4 * 1024)) & 0xFFFFF000U); - } - /* initialize iTD common fields */ - itdPointer->bufferPointers[0] |= - (((uint32_t)ehciPipePointer->pipeCommon.endpointAddress << EHCI_HOST_ITD_ENDPT_SHIFT) | - (address << EHCI_HOST_ITD_DEVICE_ADDRESS_SHIFT)); - itdPointer->bufferPointers[1] |= - (((uint32_t)ehciPipePointer->pipeCommon.direction << EHCI_HOST_ITD_DIRECTION_SHIFT) | - ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_ITD_MAX_PACKET_SIZE_SHIFT)); - itdPointer->bufferPointers[2] |= (ehciPipePointer->pipeCommon.numberPerUframe); - /* initialize transaction descriptors */ - for (index = (linkUframe & 0x0007); index < 8; index += ehciPipePointer->uframeInterval) - { - transactionLength = ((dataLength > minDataPerItd) ? minDataPerItd : dataLength); - /* initialize the uframeIndex's transaction descriptor in itd */ - itdPointer->transactions[index] = - ((EHCI_HOST_ITD_STATUS_ACTIVE_MASK) | (transactionLength << EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT) | - ((((itdBufferValue & 0xFFFFF000U) - (itdBufferBaseValue & 0xFFFFF000U)) >> - EHCI_HOST_ITD_BUFFER_POINTER_SHIFT) - << EHCI_HOST_ITD_PG_SHIFT) | - (itdBufferValue & EHCI_HOST_ITD_TRANSACTION_OFFSET_MASK)); - dataLength -= transactionLength; - itdBufferValue += transactionLength; - if (dataLength <= 0) - { - break; - } - } - } - - transfer->union2.unitTail = (uint32_t)itdPointer; - itdPointer->transactions[index] |= (1 << EHCI_HOST_ITD_IOC_SHIFT); /* last set IOC */ - - /* link itd to frame list (note: initialize frameEntryIndex)*/ - while (itdPointer) - { - itdPointer->frameEntryIndex = linkUframe; - /* add to frame head */ - itdPointer->nextLinkPointer = ((uint32_t *)ehciInstance->ehciFrameList)[linkUframe >> 3]; - *(uint32_t *)((uint32_t *)ehciInstance->ehciFrameList)[linkUframe >> 3] = - ((uint32_t)itdPointer | EHCI_HOST_POINTER_TYPE_ITD); - itdPointer = itdPointer->nextItdPointer; - if (itdPointer == NULL) - { - break; - } - - linkUframe += ehciPipePointer->uframeInterval; - lastShouldLinkUframe += ehciPipePointer->uframeInterval; - if (linkUframe >= (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE << 3)) - { - linkUframe = (linkUframe - (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE << 3)); - } - } - - if (lastShouldLinkUframe > EHCI_MAX_UFRAME_VALUE) - { - lastShouldLinkUframe = lastShouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1); - } - isoPointer->lastLinkFrame = lastShouldLinkUframe; - - return kStatus_USB_Success; -} - -static uint32_t USB_HostEhciItdArrayRelease(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_itd_t *startItdPointer, - usb_host_ehci_itd_t *endItdPointer) -{ - usb_host_ehci_itd_t *itdPointer = startItdPointer; - uint8_t index; - uint32_t doneLength = 0; - - /* remove itd from frame list */ - while (1) - { - /* record the transfer's result length */ - for (index = 0; index < 8; ++index) - { - doneLength += ((itdPointer->transactions[index] & EHCI_HOST_ITD_TRANSACTION_LEN_MASK) >> - EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT); - } - - USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)itdPointer, - itdPointer->frameEntryIndex); /* remove from the inserted frame list */ - - /* release itd */ - /* USB_HostEhciLock(); */ - USB_HostEhciZeroMem((uint32_t *)itdPointer, sizeof(usb_host_ehci_itd_t) >> 2); - itdPointer->nextLinkPointer = (uint32_t)ehciInstance->ehciItdList; - ehciInstance->ehciItdList = itdPointer; - ehciInstance->ehciItdNumber++; - /* USB_HostEhciUnlock(); */ - - if (itdPointer == endItdPointer) - { - break; - } - itdPointer = itdPointer->nextItdPointer; - } - - return doneLength; -} - -static usb_status_t USB_HostEhciItdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer) -{ - usb_host_ehci_iso_t *isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; - usb_host_transfer_t *transfer; - usb_host_transfer_t *nextTransfer; - uint32_t doneLength = 0; - - /* firstly remove the transfer (because host task may occupy to access the resource) */ - USB_HostEhciLock(); - transfer = isoPointer->ehciTransferHead; - isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = NULL; - USB_HostEhciUnlock(); - - while (transfer != NULL) - { - nextTransfer = transfer->next; - doneLength = 0; - /* remove itd from frame list and release itd */ - doneLength = USB_HostEhciItdArrayRelease(ehciInstance, (usb_host_ehci_itd_t *)transfer->union1.unitHead, - (usb_host_ehci_itd_t *)transfer->union2.unitTail); - - /* transfer callback */ - if (ehciPipePointer->pipeCommon.direction == USB_OUT) - { - doneLength = transfer->transferLength; - } - transfer->transferSofar = doneLength; - transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); - - /* next transfer */ - transfer = nextTransfer; - } - - return kStatus_USB_Success; -} -#endif /* USB_HOST_CONFIG_EHCI_MAX_ITD */ - -static usb_status_t USB_HostEhciOpenControlBulk(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer) -{ - usb_host_ehci_qh_t *qhPointer; - - if (USB_HostEhciQhInit(ehciInstance, ehciPipePointer) != kStatus_USB_Success) /* initialize control/bulk qh */ - { - return kStatus_USB_Error; - } - - qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; - - /* add qh to async */ - qhPointer->horizontalLinkPointer = ehciInstance->shedFirstQh->horizontalLinkPointer; - ehciInstance->shedFirstQh->horizontalLinkPointer = ((uint32_t)qhPointer | EHCI_HOST_POINTER_TYPE_QH); - - return kStatus_USB_Success; -} - -static usb_status_t USB_HostEhciCloseControlBulk(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer) -{ - volatile usb_host_ehci_qh_t *vltPrevQhPointer; - uint32_t horizontalLinkValue; - - /* remove qh from async schedule */ - if ((ehciInstance->shedFirstQh->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK) == - (uint32_t)ehciPipePointer->ehciQh) /* the removing qh is the first qh in the async list */ - { - USB_HostEhciStopAsync(ehciInstance); - ehciInstance->shedFirstQh->horizontalLinkPointer = - ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer; - USB_HostEhciStartAsync(ehciInstance); - } - else - { - /* search for the removing qh from the async list */ - vltPrevQhPointer = ehciInstance->shedFirstQh; - while (vltPrevQhPointer != NULL) - { - horizontalLinkValue = vltPrevQhPointer->horizontalLinkPointer; - if ((horizontalLinkValue & EHCI_HOST_T_INVALID_VALUE) || - ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciPipePointer->ehciQh) || - ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciInstance->shedFirstQh)) - { - break; - } - - vltPrevQhPointer = (volatile usb_host_ehci_qh_t *)(horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK); - } - - /* remove the qh from async list */ - if ((vltPrevQhPointer != NULL) && (!(horizontalLinkValue & EHCI_HOST_T_INVALID_VALUE)) && - ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciPipePointer->ehciQh)) - { - USB_HostEhciStopAsync(ehciInstance); - vltPrevQhPointer->horizontalLinkPointer = - ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer; - USB_HostEhciStartAsync(ehciInstance); - } - } - ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer = - EHCI_HOST_T_INVALID_VALUE; /* invalid next qh link */ - return USB_HostEhciQhDeinit(ehciInstance, ehciPipePointer); /* de-initialize qh and release qh */ -} - -static usb_status_t USB_HostEhciOpenInterrupt(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer) -{ - usb_status_t status = kStatus_USB_Success; - uint32_t frameIndex; - - /* allocate bandwidth */ - if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) - { - status = USB_HostBandwidthHsHostAllocateInterrupt(ehciInstance, ehciPipePointer); /* host works as high-speed */ - } - else - { - status = USB_HostBandwidthFslsHostAllocate(ehciInstance, - ehciPipePointer); /* host works as full-speed or low-speed */ - } - - if (status != kStatus_USB_Success) - { - return status; - } - if (USB_HostEhciQhInit(ehciInstance, ehciPipePointer) != kStatus_USB_Success) - { - return kStatus_USB_Error; - } - - /* insert QH to frame list */ - for (frameIndex = ehciPipePointer->startFrame; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; - frameIndex += (ehciPipePointer->uframeInterval / 8)) - { - USB_HostEhciAddQhToFrame(ehciInstance, (uint32_t)ehciPipePointer->ehciQh, frameIndex, - ehciPipePointer->uframeInterval); - } - - return kStatus_USB_Success; -} - -static usb_status_t USB_HostEhciCloseInterrupt(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer) -{ - uint32_t frameIndex; - - /* remove from frame list */ - for (frameIndex = ehciPipePointer->startFrame; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; - frameIndex += (ehciPipePointer->uframeInterval / 8)) - { - USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)ehciPipePointer->ehciQh, frameIndex); - } - ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer |= - EHCI_HOST_T_INVALID_VALUE; /* invalid next qh link */ - - return USB_HostEhciQhDeinit(ehciInstance, ehciPipePointer); /* de-initilaze qh and release qh */ -} - -#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ - ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) - -static usb_status_t USB_HostEhciOpenIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) -{ - usb_host_ehci_iso_t *isoPointer; - usb_status_t status = kStatus_USB_Success; - - if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) - { - status = USB_HostBandwidthHsHostAllocateIso( - ehciInstance, ehciPipePointer); /* allocate iso bandwidth when host works as high-speed */ - } - else - { - status = USB_HostBandwidthFslsHostAllocate( - ehciInstance, ehciPipePointer); /* allocate iso bandwidth when host works as full-speed or low-speed */ - } - - if (status != kStatus_USB_Success) - { - return status; - } - - /* get usb_host_ehci_iso_t */ - if (ehciInstance->ehciIsoList == NULL) - { - return kStatus_USB_Error; - } - USB_HostEhciLock(); - isoPointer = ehciInstance->ehciIsoList; - ehciInstance->ehciIsoList = ehciInstance->ehciIsoList->next; - USB_HostEhciUnlock(); - isoPointer->lastLinkFrame = 0xFFFF; - ehciPipePointer->ehciQh = isoPointer; - - return status; -} - -static usb_status_t USB_HostEhciCloseIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) -{ - usb_host_ehci_iso_t *isoPointer; - uint32_t speed; - - isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; - - if (isoPointer->ehciTransferHead != NULL) - { - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, - &speed); - if (speed == USB_SPEED_HIGH) - { -#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) - USB_HostEhciItdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize itd list and free them */ -#endif - } - else - { -#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) - USB_HostEhciSitdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize sitd list and free them */ -#endif - } - } - - /* release usb_host_ehci_iso_t */ - USB_HostEhciLock(); - isoPointer->next = ehciInstance->ehciIsoList; - ehciInstance->ehciIsoList = isoPointer; - USB_HostEhciUnlock(); - return kStatus_USB_Success; -} - -#endif - -static usb_status_t USB_HostEhciResetIP(usb_host_ehci_instance_t *ehciInstance) -{ - /* reset controller */ - ehciInstance->ehciIpBase->USBCMD = USBHS_USBCMD_RST_MASK; - while (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_RST_MASK) - { - } -/* set host mode */ -#if (ENDIANNESS == USB_LITTLE_ENDIAN) - ehciInstance->ehciIpBase->USBMODE |= 0x03; -#else - ehciInstance->ehciIpBase->USBMODE |= (0x03 | (0x01 << USBHS_USBMODE_ES_SHIFT)); -#endif - /* check frame list size */ - if (!(ehciInstance->ehciIpBase->HCCPARAMS & USBHS_HCCPARAMS_PFL_MASK)) - { -#if ((USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE < 8) || (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE > 1024)) - return kStatus_USB_Error; -#endif -#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE & (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE - 1)) - return kStatus_USB_Error; /* frame size must be 1024/512/256/128/64/32/16/8 */ -#endif - } - return kStatus_USB_Success; -} - -static usb_status_t USB_HostEhciStartIP(usb_host_ehci_instance_t *ehciInstance) -{ - uint32_t tmp = 0; - - if (ehciInstance->ehciIpBase->HCSPARAMS & USBHS_HCSPARAMS_PPC_MASK) /* Ports have power port switches */ - { - /* only has one port */ - tmp = ehciInstance->ehciIpBase->PORTSC1; - tmp &= (~EHCI_PORTSC1_W1_BITS); - ehciInstance->ehciIpBase->PORTSC1 = (tmp | USBHS_PORTSC1_PP_MASK); /* turn on port power */ - } - - /* set frame list size */ - if (ehciInstance->ehciIpBase->HCCPARAMS & USBHS_HCCPARAMS_PFL_MASK) - { -#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE <= 64) - ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_FS2_MASK); -#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 64) - ehciInstance->ehciIpBase->USBCMD |= (0x00 << USBHS_USBCMD_FS_SHIFT); -#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 32) - ehciInstance->ehciIpBase->USBCMD |= (0x01 << USBHS_USBCMD_FS_SHIFT); -#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 16) - ehciInstance->ehciIpBase->USBCMD |= (0x02 << USBHS_USBCMD_FS_SHIFT); -#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 8) - ehciInstance->ehciIpBase->USBCMD |= (0x03 << USBHS_USBCMD_FS_SHIFT); -#endif -#else -#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 1024) - ehciInstance->ehciIpBase->USBCMD |= (0x00 << USBHS_USBCMD_FS_SHIFT); -#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 512) - ehciInstance->ehciIpBase->USBCMD |= (0x01 << USBHS_USBCMD_FS_SHIFT); -#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 256) - ehciInstance->ehciIpBase->USBCMD |= (0x02 << USBHS_USBCMD_FS_SHIFT); -#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 128) - ehciInstance->ehciIpBase->USBCMD |= (0x03 << USBHS_USBCMD_FS_SHIFT); -#endif -#endif - } - - /* start the controller */ - ehciInstance->ehciIpBase->USBCMD = USBHS_USBCMD_RS_MASK; - - /* set timer0 */ - ehciInstance->ehciIpBase->GPTIMER0LD = (300 * 1000 - 1); /* 100ms */ - - /* enable interrupt (USB interrupt enable + USB error interrupt enable + port change detect enable + system error - * enable + interrupt on async advance enable) + general purpos Timer 0 Interrupt enable */ - ehciInstance->ehciIpBase->USBINTR |= (0x1000037); - - return kStatus_USB_Success; -} - -static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstance, - usb_host_ehci_pipe_t *ehciPipePointer, - usb_host_transfer_t *transfer) -{ - usb_host_ehci_qh_t *qhPointer; -#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ - ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) - usb_host_ehci_iso_t *isoPointer; - uint32_t speed; -#endif - uint8_t cancelPipe = 0; - - switch (ehciPipePointer->pipeCommon.pipeType) - { - case USB_ENDPOINT_BULK: - case USB_ENDPOINT_CONTROL: - case USB_ENDPOINT_INTERRUPT: - qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; - if (qhPointer->ehciTransferHead == NULL) /* there is no transfer to cancel */ - { - return kStatus_USB_Success; - } - if (transfer != NULL) - { - if ((qhPointer->ehciTransferHead == transfer) && - (qhPointer->ehciTransferHead == qhPointer->ehciTransferTail)) /* only has this one transfer */ - { - cancelPipe = 1; - } - else - { - cancelPipe = 0; - } - } - else - { - cancelPipe = 1; - } - if (cancelPipe == 1) /* cancel all pipe */ - { - USB_HostEhciQhQtdListDeinit(ehciInstance, ehciPipePointer); /* release all the qtd */ - } - else /* cancel one transfer */ - { - USB_HostEhciTransferQtdListDeinit(ehciInstance, ehciPipePointer, transfer); - } - break; - -#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ - ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) - case USB_ENDPOINT_ISOCHRONOUS: - isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; - if (isoPointer->ehciTransferHead == NULL) /* there is no transfer to cancel */ - { - return kStatus_USB_Success; - } - /* cancel all pipe, don't implement canceling transfer for iso */ - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, - &speed); - if (speed == USB_SPEED_HIGH) - { -#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) - USB_HostEhciItdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize itd */ -#endif - } - else - { -#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) - USB_HostEhciSitdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize sitd */ -#endif - } - break; -#endif - - default: - break; - } - - return kStatus_USB_Success; -} - -static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl) -{ - usb_status_t status = kStatus_USB_Success; - uint32_t portScRegister; - - switch (busControl) - { - case kUSB_HostBusReset: - /* reset port */ - portScRegister = ehciInstance->ehciIpBase->PORTSC1; - portScRegister &= (~EHCI_PORTSC1_W1_BITS); - ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_PR_MASK); - while (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PR_MASK) - { - } - break; - - case kUSB_HostBusRestart: - ehciInstance->deviceAttached = kEHCIDeviceDetached; - ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_PCE_MASK); /* enable ehci port change interrupt */ - break; - - case kUSB_HostBusEnableAttach: /* enable device attach */ - if (ehciInstance->deviceAttached == kEHCIDeviceDetached) - { - ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_PCE_MASK); /* enable ehci port change interrupt */ - } - break; - - case kUSB_HostBusDisableAttach: /* disable device attach */ - ehciInstance->ehciIpBase->USBINTR &= (~USBHS_USBINTR_PCE_MASK); /* disable ehci port change interrupt */ - break; -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - case kUSB_HostBusSuspend: - if (ehciInstance->ehciIpBase->PORTSC1 && USBHS_PORTSC1_CCS_MASK) - { - /* set timer1 */ - ehciInstance->ehciIpBase->GPTIMER1LD = (1 * 1000); /* 1ms */ - ehciInstance->ehciIpBase->GPTIMER1CTL |= - (USBHS_GPTIMER0CTL_RUN_MASK | USBHS_GPTIMER0CTL_MODE_MASK | USBHS_GPTIMER0CTL_RST_MASK); - - USB_HostEhciStopAsync(ehciInstance); - USB_HostEhciStopPeriodic(ehciInstance); - while (ehciInstance->ehciIpBase->USBSTS & (USBHS_USBSTS_PS_MASK | USBHS_USBSTS_AS_MASK)) - { - __ASM("nop"); - } - ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_WKCN_MASK; - ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_WKDS_MASK; - ehciInstance->ehciIpBase->PORTSC1 |= (USBHS_PORTSC1_SUSP_MASK); /* Suspend the device */ - - ehciInstance->matchTick = 0U; - ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_TIE1_MASK); - ehciInstance->busSuspendStatus = kBus_EhciStartSuspend; - } - else - { - status = kStatus_USB_Error; - } - break; - case kUSB_HostBusResume: - ehciInstance->ehciIpBase->PORTSC1 &= ~(USBHS_PORTSC1_SUSP_MASK); /* Clear Suspend bit */ - ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; - if (ehciInstance->deviceAttached != kEHCIDeviceDetached) - { - ehciInstance->busSuspendStatus = kBus_EhciStartResume; -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) - ehciInstance->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; -#else - ehciInstance->ehciIpBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; -#endif - ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_RS_MASK); - ehciInstance->ehciIpBase->PORTSC1 |= (USBHS_PORTSC1_FPR_MASK); /* Resume the device */ - } - else - { - status = kStatus_USB_Error; - } - break; -#endif - default: - status = kStatus_USB_Error; - break; - } - return status; -} - -void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance) -{ - /* process async QH */ - usb_host_ehci_pipe_t *ehciPipePointer; - usb_host_ehci_pipe_t *ehciClearPipePointer = NULL; - volatile usb_host_ehci_qh_t *vltQhPointer; - volatile usb_host_ehci_qtd_t *vltQtdPointer; - usb_host_transfer_t *transfer; - usb_host_transfer_t *nextTransfer; - uint32_t qtdStatus = 0; -#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) - volatile usb_host_ehci_itd_t *vltItdPointer; - uint8_t index = 0; -#endif -#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) - volatile usb_host_ehci_sitd_t *vltSitdPointer; -#endif -#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ - ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) - usb_host_ehci_iso_t *isoPointer; - uint32_t dataLength; - uint32_t speed; -#endif - - ehciPipePointer = ehciInstance->ehciRunningPipeList; /* check all the running pipes */ - while (ehciPipePointer != NULL) - { - switch (ehciPipePointer->pipeCommon.pipeType) - { - case USB_ENDPOINT_BULK: - case USB_ENDPOINT_INTERRUPT: - case USB_ENDPOINT_CONTROL: - vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; /* pipe's qh */ - transfer = vltQhPointer->ehciTransferHead; /* qh's transfer */ - while (transfer != NULL) - { - nextTransfer = transfer->next; - /* normal case */ - vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail; - if ((vltQtdPointer->transferResults[0] & (EHCI_HOST_QTD_IOC_MASK)) && - (!(vltQtdPointer->transferResults[0] & - EHCI_HOST_QTD_STATUS_ACTIVE_MASK))) /* transfer is done */ - { - qtdStatus = (vltQtdPointer->transferResults[0] & EHCI_HOST_QTD_STATUS_ERROR_MASK); - transfer->transferSofar = - USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), - (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); - transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? - 0 : - (transfer->transferLength - transfer->transferSofar); - - vltQhPointer->ehciTransferHead = transfer->next; - vltQhPointer->timeOutLabel = 0; - vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; - if (qtdStatus) /* has errors */ - { - if (!(vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK)) - { - vltQhPointer->transferOverlayResults[0] &= - (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ - } - if (qtdStatus & EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK) - { - transfer->callbackFn(transfer->callbackParam, transfer, - kStatus_USB_TransferFailed); /* transfer fail */ - } - else - { - transfer->callbackFn(transfer->callbackParam, transfer, - kStatus_USB_TransferStall); /* transfer stall */ - } - } - else - { - if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) && - (transfer->setupPacket->bRequest == USB_REQUEST_STANDARD_CLEAR_FEATURE) && - (transfer->setupPacket->bmRequestType == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT) && - ((USB_SHORT_FROM_LITTLE_ENDIAN(transfer->setupPacket->wValue) & 0x00FFu) == - USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT)) - { - ehciClearPipePointer = ehciInstance->ehciRunningPipeList; - while (ehciClearPipePointer != NULL) - { - /* only compute bulk and interrupt pipe */ - if (((ehciClearPipePointer->pipeCommon.endpointAddress | - (ehciClearPipePointer->pipeCommon.direction - << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)) == - (uint8_t)(USB_SHORT_FROM_LITTLE_ENDIAN(transfer->setupPacket->wIndex))) && - (ehciClearPipePointer->pipeCommon.deviceHandle == - ehciPipePointer->pipeCommon.deviceHandle)) - { - break; - } - ehciClearPipePointer = - (usb_host_ehci_pipe_t *)ehciClearPipePointer->pipeCommon.next; - } - - if ((ehciClearPipePointer != NULL) && - ((ehciClearPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT) || - (ehciClearPipePointer->pipeCommon.pipeType == USB_ENDPOINT_BULK))) - { - ((volatile usb_host_ehci_qh_t *)(ehciClearPipePointer->ehciQh)) - ->transferOverlayResults[0] &= (~EHCI_HOST_QTD_DT_MASK); - } - } - transfer->callbackFn(transfer->callbackParam, transfer, - kStatus_USB_Success); /* transfer success */ - } - } - else if ((!(vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK)) && - (vltQhPointer->transferOverlayResults[0] & - EHCI_HOST_QH_STATUS_ERROR_MASK)) /* there is error and transfer is done */ - { - qtdStatus = (vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QH_STATUS_ERROR_MASK); - vltQtdPointer = (volatile usb_host_ehci_qtd_t *)(vltQhPointer->currentQtdPointer); - - if (((uint32_t)vltQtdPointer & EHCI_HOST_T_INVALID_VALUE) || - (vltQtdPointer == NULL)) /* the error status is unreasonable */ - { - vltQhPointer->transferOverlayResults[0] &= - (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ - } - else - { - /* remove qtd from qh */ - while ((vltQtdPointer != NULL) && (!(vltQtdPointer->transferResults[0] & - EHCI_HOST_QTD_IOC_MASK))) /* find the IOC qtd */ - { - vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQtdPointer->nextQtdPointer; - } - - vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; - vltQhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; - vltQhPointer->transferOverlayResults[0] &= - (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ - if (vltQtdPointer != NULL) - { - vltQhPointer->nextQtdPointer = vltQtdPointer->nextQtdPointer; - } - - transfer->transferSofar = USB_HostEhciQtdListRelease( - ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), - (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); - transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? - 0 : - (transfer->transferLength - transfer->transferSofar); - vltQhPointer->ehciTransferHead = transfer->next; - vltQhPointer->timeOutLabel = 0; - vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; - if (qtdStatus & EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK) - { - transfer->callbackFn(transfer->callbackParam, transfer, - kStatus_USB_TransferFailed); /* transfer fail */ - } - else - { - transfer->callbackFn(transfer->callbackParam, transfer, - kStatus_USB_TransferStall); /* transfer stall */ - } - } - } - else - { - break; - } - transfer = nextTransfer; - } - break; -#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ - ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) - case USB_ENDPOINT_ISOCHRONOUS: - qtdStatus = 0; /* qtdStatus means break here, because there is only one break in while for misra */ - isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; /* pipe's usb_host_ehci_iso_t */ - transfer = isoPointer->ehciTransferHead; /* usb_host_ehci_iso_t's transfer */ - while (transfer != NULL) - { - nextTransfer = transfer->next; - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, - kUSB_HostGetDeviceSpeed, &speed); - if (speed == USB_SPEED_HIGH) - { -#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) - vltItdPointer = - (volatile usb_host_ehci_itd_t *)(transfer->union2.unitTail); /* transfer's last itd */ - for (index = 0; index < 8; ++index) - { - if (vltItdPointer->transactions[index] & EHCI_HOST_ITD_STATUS_ACTIVE_MASK) - { - break; - } - } - if (index == 8) /* transfer is done */ - { - /* remove itd from frame list and release itd */ - dataLength = USB_HostEhciItdArrayRelease(ehciInstance, - (usb_host_ehci_itd_t *)transfer->union1.unitHead, - (usb_host_ehci_itd_t *)transfer->union2.unitTail); - transfer->transferSofar = dataLength; - isoPointer->ehciTransferHead = transfer->next; - transfer->callbackFn(transfer->callbackParam, transfer, - kStatus_USB_Success); /* transfer callback success */ - /* TODO: iso callback error */ - } - else - { - qtdStatus = 1; /* break */ - } -#endif - } - else - { -#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) - vltSitdPointer = - (volatile usb_host_ehci_sitd_t *)(transfer->union2.unitTail); /* transfer's last sitd */ - if (!(vltSitdPointer->transferResults[0] & - EHCI_HOST_SITD_STATUS_ACTIVE_MASK)) /* transfer is done */ - { - /* remove sitd from frame list and release itd */ - dataLength = USB_HostEhciSitdArrayRelease( - ehciInstance, (usb_host_ehci_sitd_t *)transfer->union1.unitHead, - (usb_host_ehci_sitd_t *)transfer->union2.unitTail); - transfer->transferSofar = dataLength; - isoPointer->ehciTransferHead = transfer->next; - transfer->callbackFn(transfer->callbackParam, transfer, - kStatus_USB_Success); /* transfer callback success */ - /* TODO: iso callback error */ - } - else - { - qtdStatus = 1; /* break */ - } -#endif - } - if (qtdStatus == 1) - { - break; - } - transfer = nextTransfer; - } - break; -#endif - - default: - break; - } - ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; - } -} - -static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance) -{ - /* note: only has one port */ - uint32_t portScRegister = ehciInstance->ehciIpBase->PORTSC1; - int32_t sofStart = 0; - int32_t sofCount = 0; - uint32_t index; - - if (portScRegister & USBHS_PORTSC1_CSC_MASK) /* connection status change */ - { - sofStart = (int32_t)(ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); - - /* process CSC bit */ - while (1) - { - portScRegister = ehciInstance->ehciIpBase->PORTSC1; - if (portScRegister & USBHS_PORTSC1_CSC_MASK) - { - /* clear csc bit */ - portScRegister = ehciInstance->ehciIpBase->PORTSC1; - portScRegister &= (~EHCI_PORTSC1_W1_BITS); - ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_CSC_MASK); - } - sofCount = (int32_t)(ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); - if (((sofCount - sofStart + EHCI_MAX_UFRAME_VALUE + 1) & EHCI_MAX_UFRAME_VALUE) > - (1 * 8)) /* delay 1ms to clear CSC */ - { - break; - } - } - } - - /* process CCS bit */ - portScRegister = ehciInstance->ehciIpBase->PORTSC1; - if (portScRegister & USBHS_PORTSC1_CCS_MASK) /* process attach */ - { - if ((ehciInstance->deviceAttached == kEHCIDevicePhyAttached) || - (ehciInstance->deviceAttached == kEHCIDeviceAttached)) - { - return; - } -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - ehciInstance->busSuspendStatus = kBus_EhciIdle; - ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); -#endif - for (index = 0; index < USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY; ++index) - { - USB_HostEhciDelay(ehciInstance->ehciIpBase, 1); - if (!(ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK)) - { - break; - } - } - if (index < USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY) /* CCS is cleared */ - { - ehciInstance->deviceAttached = kEHCIDeviceDetached; - return; - } - /* reset port */ - portScRegister = ehciInstance->ehciIpBase->PORTSC1; - portScRegister &= (~EHCI_PORTSC1_W1_BITS); - ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_PR_MASK); - while (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PR_MASK) - { - } - ehciInstance->firstDeviceSpeed = - ((ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PSPD_MASK) >> USBHS_PORTSC1_PSPD_SHIFT); - /* enable ehci phy disconnection */ - if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) - { - USB_EhcihostPhyDisconnectDetectCmd(ehciInstance->controllerId, 1); - } - - /* wait for reset */ - USB_HostEhciDelay(ehciInstance->ehciIpBase, USB_HOST_EHCI_PORT_RESET_DELAY); - /* process attach */ - USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_DEVICE_ATTACH); - /* gpt timer start */ - ehciInstance->ehciIpBase->GPTIMER0CTL |= - (USBHS_GPTIMER0CTL_RUN_MASK | USBHS_GPTIMER0CTL_MODE_MASK | USBHS_GPTIMER0CTL_RST_MASK); - ehciInstance->deviceAttached = kEHCIDevicePhyAttached; - } - else - { - if ((ehciInstance->deviceAttached == kEHCIDevicePhyAttached) || - (ehciInstance->deviceAttached == kEHCIDeviceAttached)) - { -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - ehciInstance->busSuspendStatus = kBus_EhciIdle; - ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); -#endif - /* disable ehci phy disconnection */ - USB_EhcihostPhyDisconnectDetectCmd(ehciInstance->controllerId, 0); - /* disable async and periodic */ - USB_HostEhciStopAsync(ehciInstance); - USB_HostEhciStopPeriodic(ehciInstance); - USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_DEVICE_DETACH); - } - } -} - -static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance) -{ - volatile usb_host_ehci_qh_t *vltQhPointer; - volatile usb_host_ehci_qtd_t *vltQtdPointer; - usb_host_transfer_t *transfer; - uint32_t backValue; - volatile uint32_t *totalBytesAddress = NULL; - usb_host_ehci_pipe_t *ehciPipePointer = ehciInstance->ehciRunningPipeList; - uint8_t timeoutLabel; - - while (ehciPipePointer != NULL) - { - switch (ehciPipePointer->pipeCommon.pipeType) - { - case USB_ENDPOINT_BULK: - case USB_ENDPOINT_CONTROL: - vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; /* pipe's qh */ - transfer = vltQhPointer->ehciTransferHead; /* qh's transfer */ - if ((transfer != NULL)) /* there is transfering data */ - { - timeoutLabel = 0; - if (ehciInstance->deviceAttached != kEHCIDeviceAttached) - { - vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail; - - vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ - vltQhPointer->transferOverlayResults[0] &= - (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ - timeoutLabel = 1; - } - else - { - if (vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK) - { - vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQhPointer->currentQtdPointer; - totalBytesAddress = &(vltQhPointer->transferOverlayResults[0]); - } - else - { - vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail; - totalBytesAddress = ((uint32_t *)vltQtdPointer + 2); - } - - backValue = - (((*totalBytesAddress) & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> - EHCI_HOST_QTD_TOTAL_BYTES_SHIFT); /* backValue is used for total bytes to transfer */ - if (vltQhPointer->timeOutLabel != backValue) /* use total bytes to reflect the time out */ - { - vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; - vltQhPointer->timeOutLabel = backValue; - } - else - { - /* time out when the total bytes don't change for the duration - * USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE - */ - (vltQhPointer->timeOutValue)--; - if (vltQhPointer->timeOutValue == 0) - { - /* stop the qh schedule */ - USB_HostEhciStopAsync(ehciInstance); - if (backValue != (((*totalBytesAddress) & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> - EHCI_HOST_QTD_TOTAL_BYTES_SHIFT)) - { - USB_HostEhciStartAsync(ehciInstance); - } - else - { - vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ - vltQhPointer->transferOverlayResults[0] &= - (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ - USB_HostEhciStartAsync(ehciInstance); - timeoutLabel = 1; - } - } - } - } - - if (timeoutLabel == 1) - { - /* remove qtd from qh */ - while ((vltQtdPointer != NULL) && - (!(vltQtdPointer->transferResults[0] & EHCI_HOST_QTD_IOC_MASK)) && - (vltQtdPointer != (usb_host_ehci_qtd_t *)vltQhPointer->ehciTransferTail)) - { - vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQtdPointer->nextQtdPointer; - } - if ((vltQtdPointer != NULL) && (!(vltQtdPointer->nextQtdPointer & EHCI_HOST_T_INVALID_VALUE))) - { - vltQhPointer->nextQtdPointer = - vltQtdPointer->nextQtdPointer; /* start qh if there are other qtd that don't belong to - the transfer */ - } - transfer->transferSofar = - USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), - (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); - transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? - 0 : - (transfer->transferLength - transfer->transferSofar); - - vltQhPointer->ehciTransferHead = transfer->next; - vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; - transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferFailed); - } - } - break; - default: - break; - } - ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; - } -} - -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) -static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance) -{ - if (ehciInstance->deviceAttached != kEHCIDeviceDetached) - { - if (kBus_EhciStartSuspend == ehciInstance->busSuspendStatus) - { - usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; - - if (0 == ehciInstance->matchTick) - { - ehciInstance->matchTick = hostPointer->hwTick; - } - else - { - if ((hostPointer->hwTick - ehciInstance->matchTick) >= 5) - { - ehciInstance->ehciIpBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; - ehciInstance->ehciIpBase->USBSTS |= USBHS_USBSTS_SRI_MASK; -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) -#if 0 - ehciInstance->registerPhyBase->CTRL |= USBPHY_CTRL_ENVBUSCHG_WKUP_MASK - | USBPHY_CTRL_ENIDCHG_WKUP_MASK - | USBPHY_CTRL_ENDPDMCHG_WKUP_MASK - | USBPHY_CTRL_ENIRQRESUMEDETECT_MASK - ; -#endif -#endif - ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_PHCD_MASK; - - ehciInstance->registerPhyBase->PWD = 0xFFFFFFFFU; - - while (ehciInstance->registerPhyBase->CTRL & (USBPHY_CTRL_UTMI_SUSPENDM_MASK)) - { - __ASM("nop"); - } - -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) - ehciInstance->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK | - USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK | - USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK; - ehciInstance->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WIE_MASK; -#else - ehciInstance->ehciIpBase->USBGENCTRL = USBHS_USBGENCTRL_WU_IE_MASK; -#endif - ehciInstance->registerPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; - hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, - kUSB_HostEventSuspended); /* call host callback function */ - ehciInstance->busSuspendStatus = kBus_EhciSuspended; - } - } - } - else if (kBus_EhciStartResume == ehciInstance->busSuspendStatus) - { - usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; - if (!(ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_FPR_MASK)) - { - ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_WKDS_MASK; - if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) - { - USB_HostEhciStartAsync(ehciInstance); - USB_HostEhciStartPeriodic(ehciInstance); - } - hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, - kUSB_HostEventResumed); /* call host callback function */ - hostPointer->suspendedDevice = NULL; - ehciInstance->busSuspendStatus = kBus_EhciIdle; - ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); - } - } - else - { - } - } - else - { - ehciInstance->busSuspendStatus = kBus_EhciIdle; - ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); - } -} -#endif - -usb_status_t USB_HostEhciCreate(uint8_t controllerId, - usb_host_handle upperLayerHandle, - usb_host_controller_handle *controllerHandle) -{ - uint32_t index = 0; - usb_osa_status_t osaStatus; - usb_host_ehci_instance_t *ehciInstance; - uint32_t usbhsBaseAddrs[] = USBHS_BASE_ADDRS; - usb_host_ehci_data_t *usbHostEhciData[] = USB_HOST_EHCI_DATA_ARRAY; - uint8_t *usbHostEhciFrameList[] = USB_HOST_EHCI_FRAME_LIST_ARRAY; - uint32_t *framePointer; - - if ((uint32_t)(controllerId - kUSB_ControllerEhci0) >= (sizeof(usbhsBaseAddrs) / sizeof(usbhsBaseAddrs[0]))) - { - return kStatus_USB_ControllerNotFound; - } - - *controllerHandle = NULL; - ehciInstance = (usb_host_ehci_instance_t *)USB_OsaMemoryAllocate( - sizeof(usb_host_ehci_instance_t)); /* malloc host ehci instance */ - if (ehciInstance == NULL) - { - return kStatus_USB_AllocFail; - } - ehciInstance->controllerId = controllerId; - ehciInstance->hostHandle = upperLayerHandle; - ehciInstance->deviceAttached = kEHCIDeviceDetached; - ehciInstance->ehciIpBase = (USBHS_Type *) - usbhsBaseAddrs[controllerId - kUSB_ControllerEhci0]; /* operate ehci ip through the base address */ -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - ehciInstance->busSuspendStatus = kBus_EhciIdle; - -#if (defined(USB_HOST_CONFIG_LOW_POWER_MODE) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - ehciInstance->registerPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); - -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) - ehciInstance->registerNcBase = (USBNC_Type *)USB_EhciNCGetBase(controllerId); -#endif - -#endif - -#endif - - if (USB_HostEhciResetIP(ehciInstance) != kStatus_USB_Success) /* reset ehci ip */ - { - USB_OsaMemoryFree(ehciInstance); - return kStatus_USB_Error; - } - - /* initialize ehci frame list */ - ehciInstance->ehciFrameList = usbHostEhciFrameList[ehciInstance->controllerId - kUSB_ControllerEhci0]; - - /* initialize ehci units */ - ehciInstance->ehciUnitBase = (uint32_t *)(usbHostEhciData[ehciInstance->controllerId - kUSB_ControllerEhci0]); - /* initialize qh/qtd/itd/sitd/iso list */ - ehciInstance->ehciQhList = (usb_host_ehci_qh_t *)((uint32_t)(ehciInstance->ehciUnitBase)); - ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)((uint32_t)ehciInstance->ehciQhList + - (sizeof(usb_host_ehci_qh_t) * USB_HOST_CONFIG_EHCI_MAX_QH)); - ehciInstance->ehciItdList = (usb_host_ehci_itd_t *)((uint32_t)ehciInstance->ehciQtdHead + - (sizeof(usb_host_ehci_qtd_t) * USB_HOST_CONFIG_EHCI_MAX_QTD)); - ehciInstance->ehciSitdList = ehciInstance->ehciSitdIndexBase = - (usb_host_ehci_sitd_t *)((uint32_t)ehciInstance->ehciItdList + - (sizeof(usb_host_ehci_itd_t) * USB_HOST_CONFIG_EHCI_MAX_ITD)); - ehciInstance->ehciIsoList = (usb_host_ehci_iso_t *)((uint32_t)ehciInstance->ehciSitdList + - (sizeof(usb_host_ehci_sitd_t) * USB_HOST_CONFIG_EHCI_MAX_SITD)); - ehciInstance->ehciPipeIndexBase = - (usb_host_ehci_pipe_t *)((uint32_t)ehciInstance->ehciIsoList + - (sizeof(usb_host_ehci_iso_t) * USB_HOST_EHCI_ISO_NUMBER)); - for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_QH; ++index) - { - ehciInstance->ehciQhList[index - 1].horizontalLinkPointer = (uint32_t)(&ehciInstance->ehciQhList[index]); - } - ehciInstance->ehciQhList[USB_HOST_CONFIG_EHCI_MAX_QH - 1].horizontalLinkPointer = (uint32_t)NULL; - for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_QTD; ++index) - { - ehciInstance->ehciQtdHead[index - 1].nextQtdPointer = (uint32_t)(&ehciInstance->ehciQtdHead[index]); - } - ehciInstance->ehciQtdNumber = USB_HOST_CONFIG_EHCI_MAX_QTD; - ehciInstance->ehciQtdHead[USB_HOST_CONFIG_EHCI_MAX_QTD - 1].nextQtdPointer = (uint32_t)NULL; - ehciInstance->ehciQtdTail = &ehciInstance->ehciQtdHead[USB_HOST_CONFIG_EHCI_MAX_QTD - 1]; - -#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) - for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_ITD; ++index) - { - ehciInstance->ehciItdList[index - 1].nextLinkPointer = (uint32_t)(&ehciInstance->ehciItdList[index]); - } - ehciInstance->ehciItdNumber = USB_HOST_CONFIG_EHCI_MAX_ITD; - ehciInstance->ehciItdList[USB_HOST_CONFIG_EHCI_MAX_ITD - 1].nextLinkPointer = (uint32_t)NULL; -#endif /* USB_HOST_CONFIG_EHCI_MAX_ITD */ - -#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) - for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_SITD; ++index) - { - ehciInstance->ehciSitdList[index - 1].nextLinkPointer = (uint32_t)(&ehciInstance->ehciSitdList[index]); - } - ehciInstance->ehciSitdNumber = USB_HOST_CONFIG_EHCI_MAX_SITD; - ehciInstance->ehciSitdList[USB_HOST_CONFIG_EHCI_MAX_SITD - 1].nextLinkPointer = (uint32_t)NULL; -#endif /* USB_HOST_CONFIG_EHCI_MAX_SITD */ - -#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) - for (index = 1; index < USB_HOST_EHCI_ISO_NUMBER; ++index) - { - ehciInstance->ehciIsoList[index - 1].next = &ehciInstance->ehciIsoList[index]; - } - ehciInstance->ehciIsoList[USB_HOST_EHCI_ISO_NUMBER - 1].next = NULL; -#endif - - /* initialize pipes */ - ehciInstance->ehciPipeList = ehciInstance->ehciPipeIndexBase; - for (index = 1; index < USB_HOST_CONFIG_MAX_PIPES; ++index) - { - ehciInstance->ehciPipeList[index - 1].pipeCommon.next = (usb_host_pipe_t *)&ehciInstance->ehciPipeList[index]; - } - /* initialize mutext */ - osaStatus = USB_OsaMutexCreate(&ehciInstance->ehciMutex); - if (osaStatus != kStatus_USB_OSA_Success) - { -#ifdef HOST_ECHO - usb_echo("ehci mutex init fail\r\n"); -#endif - USB_OsaMemoryFree(ehciInstance); - return kStatus_USB_Error; - } - /* initialize task event */ - osaStatus = USB_OsaEventCreate(&ehciInstance->taskEventHandle, 1); - if (osaStatus != kStatus_USB_OSA_Success) - { -#ifdef HOST_ECHO - usb_echo("ehci event init fail\r\n"); -#endif - USB_OsaMutexDestroy(ehciInstance->ehciMutex); - USB_OsaMemoryFree(ehciInstance); - return kStatus_USB_Error; - } - - /* initialize first qh */ - ehciInstance->shedFirstQh = ehciInstance->ehciQhList; - ehciInstance->ehciQhList = - (usb_host_ehci_qh_t *)(ehciInstance->ehciQhList->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK); - ehciInstance->shedFirstQh->staticEndpointStates[0] |= (1 << EHCI_HOST_QH_H_SHIFT); /* first qh */ - ehciInstance->shedFirstQh->horizontalLinkPointer = EHCI_HOST_T_INVALID_VALUE; - ehciInstance->shedFirstQh->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; - ehciInstance->shedFirstQh->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; - ehciInstance->shedFirstQh->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; - ehciInstance->shedFirstQh->horizontalLinkPointer = - (uint32_t)((uint32_t)(ehciInstance->shedFirstQh) | EHCI_HOST_POINTER_TYPE_QH); - - /* initialize periodic list */ - framePointer = (uint32_t *)ehciInstance->ehciFrameList; - for (index = 0; index < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; ++index) - { - framePointer[index] = EHCI_HOST_T_INVALID_VALUE; - } - - USB_HostEhciStartIP(ehciInstance); /* start ehci ip */ - - *controllerHandle = ehciInstance; - - return kStatus_USB_Success; -} - -usb_status_t USB_HostEhciDestory(usb_host_controller_handle controllerHandle) -{ - usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; - - /* disable all interrupts */ - ehciInstance->ehciIpBase->USBINTR = 0; - /* stop the controller */ - ehciInstance->ehciIpBase->USBCMD = 0; - /* free memory */ - USB_OsaMutexDestroy(ehciInstance->ehciMutex); - USB_OsaEventDestroy(ehciInstance->taskEventHandle); - USB_OsaMemoryFree(ehciInstance); - - return kStatus_USB_Success; -} - -usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle, - usb_host_pipe_handle *pipeHandle, - usb_host_pipe_init_t *pipeInit) -{ - usb_host_ehci_pipe_t *ehciPipePointer = NULL; - usb_status_t status; - uint32_t speed; - usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; - - /* get one pipe */ - USB_HostEhciLock(); - if (ehciInstance->ehciPipeList != NULL) - { - ehciPipePointer = ehciInstance->ehciPipeList; - ehciInstance->ehciPipeList = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; - } - USB_HostEhciUnlock(); - if (ehciPipePointer == NULL) - { -#ifdef HOST_ECHO - usb_echo("ehci open pipe failed\r\n"); -#endif - return kStatus_USB_Busy; - } - - /* initialize pipe informations */ - USB_HostEhciZeroMem((uint32_t *)ehciPipePointer, sizeof(usb_host_ehci_pipe_t) / 4); - ehciPipePointer->pipeCommon.deviceHandle = pipeInit->devInstance; - ehciPipePointer->pipeCommon.endpointAddress = pipeInit->endpointAddress; - ehciPipePointer->pipeCommon.direction = pipeInit->direction; - ehciPipePointer->pipeCommon.interval = pipeInit->interval; - ehciPipePointer->pipeCommon.maxPacketSize = pipeInit->maxPacketSize; - ehciPipePointer->pipeCommon.pipeType = pipeInit->pipeType; - ehciPipePointer->pipeCommon.numberPerUframe = pipeInit->numberPerUframe; - if (ehciPipePointer->pipeCommon.numberPerUframe == 0) - { - ehciPipePointer->pipeCommon.numberPerUframe = 1; - } - ehciPipePointer->pipeCommon.nakCount = pipeInit->nakCount; - ehciPipePointer->pipeCommon.nextdata01 = 0; - ehciPipePointer->ehciQh = NULL; - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed); - if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) - { - ehciPipePointer->pipeCommon.interval = - (1 << (ehciPipePointer->pipeCommon.interval - 1)); /* iso interval is the power of 2 */ - } - else if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT) - { - if (speed == USB_SPEED_HIGH) - { - ehciPipePointer->pipeCommon.interval = - (1 << (ehciPipePointer->pipeCommon.interval - 1)); /* HS interrupt interval is the power of 2 */ - } - else - { - ehciPipePointer->pipeCommon.interval = USB_HostEhciGet2PowerValue( - ehciPipePointer->pipeCommon - .interval); /* FS/LS interrupt interval should be the power of 2, it is used for ehci bandwidth */ - } - } - else - { - } - - /* save the micro-frame interval, it is convenient for the interval process */ - if (speed == USB_SPEED_HIGH) - { - ehciPipePointer->uframeInterval = ehciPipePointer->pipeCommon.interval; - } - else - { - ehciPipePointer->uframeInterval = 8 * ehciPipePointer->pipeCommon.interval; - } - - /* open pipe */ - switch (ehciPipePointer->pipeCommon.pipeType) - { - case USB_ENDPOINT_CONTROL: - case USB_ENDPOINT_BULK: - status = USB_HostEhciOpenControlBulk(ehciInstance, ehciPipePointer); - break; - -#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ - ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) - case USB_ENDPOINT_ISOCHRONOUS: - status = USB_HostEhciOpenIso(ehciInstance, ehciPipePointer); - break; -#endif - - case USB_ENDPOINT_INTERRUPT: - status = USB_HostEhciOpenInterrupt(ehciInstance, ehciPipePointer); - break; - - default: - status = kStatus_USB_Error; - break; - } - - if (status != kStatus_USB_Success) - { - /* release pipe */ - USB_HostEhciLock(); - ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciPipeList; - ehciInstance->ehciPipeList = ehciPipePointer; - USB_HostEhciUnlock(); - return status; - } - - /* add pipe to run pipe list */ - USB_HostEhciLock(); - ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciRunningPipeList; - ehciInstance->ehciRunningPipeList = ehciPipePointer; - USB_HostEhciUnlock(); - - *pipeHandle = ehciPipePointer; - return status; -} - -usb_status_t USB_HostEhciClosePipe(usb_host_controller_handle controllerHandle, usb_host_pipe_handle pipeHandle) -{ - usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; - usb_host_ehci_pipe_t *ehciPipePointer = (usb_host_ehci_pipe_t *)pipeHandle; - usb_host_pipe_t *prevPointer = NULL; - - switch (ehciPipePointer->pipeCommon.pipeType) - { - case USB_ENDPOINT_BULK: - case USB_ENDPOINT_CONTROL: - USB_HostEhciCloseControlBulk(ehciInstance, ehciPipePointer); - break; - - case USB_ENDPOINT_INTERRUPT: - USB_HostEhciCloseInterrupt(ehciInstance, ehciPipePointer); - break; - -#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ - ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) - case USB_ENDPOINT_ISOCHRONOUS: - USB_HostEhciCloseIso(ehciInstance, ehciPipePointer); - break; -#endif - - default: - break; - } - - /* delete pipe from run pipe list */ - USB_HostEhciLock(); - prevPointer = (usb_host_pipe_t *)ehciInstance->ehciRunningPipeList; - if (prevPointer == (usb_host_pipe_t *)ehciPipePointer) - { - ehciInstance->ehciRunningPipeList = (usb_host_ehci_pipe_t *)(prevPointer->next); - } - else - { - while (prevPointer != NULL) - { - if (prevPointer->next == (usb_host_pipe_t *)ehciPipePointer) - { - prevPointer->next = ehciPipePointer->pipeCommon.next; - break; - } - else - { - prevPointer = prevPointer->next; - } - } - } - USB_HostEhciUnlock(); - - /* release pipe */ - USB_HostEhciLock(); - ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciPipeList; - ehciInstance->ehciPipeList = ehciPipePointer; - USB_HostEhciUnlock(); - - return kStatus_USB_Success; -} - -usb_status_t USB_HostEhciWritePipe(usb_host_controller_handle controllerHandle, - usb_host_pipe_handle pipeHandle, - usb_host_transfer_t *transfer) -{ - usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; - usb_host_ehci_pipe_t *ehciPipePointer = (usb_host_ehci_pipe_t *)pipeHandle; - usb_status_t status = kStatus_USB_Success; -#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ - ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) - uint32_t speed; -#endif - - switch (ehciPipePointer->pipeCommon.pipeType) - { - case USB_ENDPOINT_BULK: - case USB_ENDPOINT_CONTROL: - case USB_ENDPOINT_INTERRUPT: - status = USB_HostEhciQhQtdListInit(ehciInstance, ehciPipePointer, - transfer); /* initialize qtd for control/bulk transfer */ - break; - -#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ - ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) - case USB_ENDPOINT_ISOCHRONOUS: - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, - &speed); - if (speed == USB_SPEED_HIGH) - { -#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) - status = USB_HostEhciItdArrayInit(ehciInstance, ehciPipePointer, - transfer); /* initialize itd for iso transfer */ -#endif - } - else - { -#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) - status = USB_HostEhciSitdArrayInit(ehciInstance, ehciPipePointer, - transfer); /* initialize sitd for iso transfer */ -#endif - } - break; -#endif - - default: - break; - } - return status; -} - -usb_status_t USB_HostEhciReadpipe(usb_host_controller_handle controllerHandle, - usb_host_pipe_handle pipeHandle, - usb_host_transfer_t *transfer) -{ - return USB_HostEhciWritePipe(controllerHandle, pipeHandle, transfer); /* same as write */ -} - -usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandle, uint32_t ioctlEvent, void *ioctlParam) -{ - usb_status_t status = kStatus_USB_Success; - usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; - usb_host_cancel_param_t *param; - usb_host_ehci_pipe_t *ehciPipePointer; - volatile usb_host_ehci_qh_t *vltQhPointer; - uint32_t deviceAddress; - - if (controllerHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - - switch (ioctlEvent) - { - case kUSB_HostCancelTransfer: /* cancel pipe or one transfer */ - param = (usb_host_cancel_param_t *)ioctlParam; - status = USB_HostEhciCancelPipe(ehciInstance, (usb_host_ehci_pipe_t *)param->pipeHandle, param->transfer); - break; - - case kUSB_HostBusControl: /* bus control */ - status = USB_HostEhciControlBus(ehciInstance, *((uint8_t *)ioctlParam)); - break; - - case kUSB_HostGetFrameNumber: /* get frame number */ - *((uint32_t *)ioctlParam) = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3); - break; - - case kUSB_HostUpdateControlEndpointAddress: - ehciPipePointer = (usb_host_ehci_pipe_t *)ioctlParam; - vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; - /* update address */ - USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, - &deviceAddress); - vltQhPointer->staticEndpointStates[0] |= deviceAddress; - break; - - case kUSB_HostUpdateControlPacketSize: - ehciPipePointer = (usb_host_ehci_pipe_t *)ioctlParam; - vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; - USB_HostEhciLock(); - if (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) - { - USB_HostEhciStopAsync(ehciInstance); - /* update max packet size */ - vltQhPointer->staticEndpointStates[0] = - (((vltQhPointer->staticEndpointStates[0]) & (~EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK)) | - ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT)); - USB_HostEhciStartAsync(ehciInstance); - } - else - { - /* update max packet size */ - vltQhPointer->staticEndpointStates[0] = - (((vltQhPointer->staticEndpointStates[0]) & (~EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK)) | - ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT)); - } - USB_HostEhciUnlock(); - break; - - default: - break; - } - return status; -} - -void USB_HostEhciTaskFunction(void *hostHandle) -{ - usb_host_ehci_instance_t *ehciInstance; - uint32_t bitSet; - usb_device_handle deviceHandle; - - if (hostHandle == NULL) - { - return; - } - ehciInstance = (usb_host_ehci_instance_t *)((usb_host_instance_t *)hostHandle)->controllerHandle; - - if (USB_OsaEventWait(ehciInstance->taskEventHandle, 0xFF, 0, 0, &bitSet) == - kStatus_USB_OSA_Success) /* wait all event */ - { - if (bitSet & EHCI_TASK_EVENT_PORT_CHANGE) /* port change */ - { - USB_HostEhciPortChange(ehciInstance); - } - - if (bitSet & EHCI_TASK_EVENT_TIMER0) /* timer0 */ - { - USB_HostEhciTimer0(ehciInstance); - } - -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - if (bitSet & EHCI_TASK_EVENT_TIMER1) /* timer1 */ - { - USB_HostEhciTimer1(ehciInstance); - } -#endif - - if (ehciInstance->deviceAttached == kEHCIDeviceAttached) - { - if (bitSet & EHCI_TASK_EVENT_TRANSACTION_DONE) /* transaction done */ - { - USB_HostEhciTransactionDone(ehciInstance); - } - - if (bitSet & EHCI_TASK_EVENT_DEVICE_DETACH) /* device detach */ - { - ehciInstance->ehciIpBase->USBINTR &= - (~USBHS_USBINTR_PCE_MASK); /* disable attach, enable when the detach process is done */ - ehciInstance->deviceAttached = kEHCIDeviceDetached; - USB_HostDetachDevice(ehciInstance->hostHandle, 0, 0); - } - } - else if (ehciInstance->deviceAttached != kEHCIDeviceAttached) - { - if (bitSet & EHCI_TASK_EVENT_DEVICE_ATTACH) /* device is attached */ - { - USB_HostEhciStartAsync(ehciInstance); - USB_HostEhciStartPeriodic(ehciInstance); - - if (USB_HostAttachDevice(ehciInstance->hostHandle, ehciInstance->firstDeviceSpeed, 0, 0, 1, - &deviceHandle) == kStatus_USB_Success) - { - ehciInstance->deviceAttached = kEHCIDeviceAttached; - } - } - } - else - { - } - } -} - -void USB_HostEhciIsrFunction(void *hostHandle) -{ - usb_host_ehci_instance_t *ehciInstance; - static uint32_t interruptStatus = 0; - - if (hostHandle == NULL) - { - return; - } - - ehciInstance = (usb_host_ehci_instance_t *)((usb_host_instance_t *)hostHandle)->controllerHandle; - -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) - if (ehciInstance->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIE_MASK) - { - usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; - ehciInstance->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; - hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, - kUSB_HostEventDetectResume); /* call host callback function */ - - while (!(ehciInstance->registerNcBase->USB_OTGn_PHY_CTRL_0 & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)) - { - } - - if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) - { - USB_HostEhciStartAsync(ehciInstance); - USB_HostEhciStartPeriodic(ehciInstance); - } - ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_RS_MASK); - if ((kBus_EhciSuspended == ehciInstance->busSuspendStatus)) - { - /* ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_FPR_MASK; */ - ehciInstance->busSuspendStatus = kBus_EhciStartResume; - } - else - { - } - } - else - { - } -#else - if (ehciInstance->ehciIpBase->USBGENCTRL & USBHS_USBGENCTRL_WU_IE_MASK) - { - usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; - - hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, - kUSB_HostEventDetectResume); /* call host callback function */ - - while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) - { - } - ehciInstance->ehciIpBase->USBGENCTRL |= USBHS_USBGENCTRL_WU_INT_CLR_MASK; - ehciInstance->ehciIpBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; - if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) - { - USB_HostEhciStartAsync(ehciInstance); - USB_HostEhciStartPeriodic(ehciInstance); - } - ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_RS_MASK); - if ((kBus_EhciSuspended == ehciInstance->busSuspendStatus)) - { - ehciInstance->busSuspendStatus = kBus_EhciStartResume; - /*ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_FPR_MASK; */ - } - else - { - } - } - else - { - } -#endif /* FSL_FEATURE_SOC_USBNC_COUNT */ - -#endif /* USB_HOST_CONFIG_LOW_POWER_MODE */ - - interruptStatus = ehciInstance->ehciIpBase->USBSTS; - interruptStatus &= ehciInstance->ehciIpBase->USBINTR; - while (interruptStatus) /* there are usb interrupts */ - { - ehciInstance->ehciIpBase->USBSTS = interruptStatus; /* clear interrupt */ - - if (interruptStatus & USBHS_USBSTS_SRI_MASK) /* SOF interrupt */ - { - } - - if (interruptStatus & USBHS_USBSTS_SEI_MASK) /* system error interrupt */ - { - } - - if ((interruptStatus & USBHS_USBSTS_UI_MASK) || - (interruptStatus & USBHS_USBSTS_UEI_MASK)) /* USB interrupt or USB error interrupt */ - { - USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TRANSACTION_DONE); - } - - if (interruptStatus & USBHS_USBSTS_PCI_MASK) /* port change detect interrupt */ - { -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; - if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_FPR_MASK) - { - if (kBus_EhciStartSuspend == ehciInstance->busSuspendStatus) - { - if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) - { - USB_HostEhciStartAsync(ehciInstance); - USB_HostEhciStartPeriodic(ehciInstance); - } - hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, - kUSB_HostEventNotSuspended); /* call host callback function */ - hostPointer->suspendedDevice = NULL; - ehciInstance->busSuspendStatus = kBus_EhciIdle; - ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); - } - else - { - } - } -#endif - USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_PORT_CHANGE); - } - - if (interruptStatus & USBHS_USBSTS_TI0_MASK) /* timer 0 interrupt */ - { - USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TIMER0); - } - -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - if (interruptStatus & USBHS_USBSTS_TI1_MASK) /* timer 1 interrupt */ - { - USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TIMER1); - } -#endif - - interruptStatus = ehciInstance->ehciIpBase->USBSTS; - interruptStatus &= ehciInstance->ehciIpBase->USBINTR; - } -} - -#endif /* USB_HOST_CONFIG_EHCI */ diff --git a/bsp/imxrt1052-evk/drivers/usb/host/usb_host_ehci.h b/bsp/imxrt1052-evk/drivers/usb/host/usb_host_ehci.h deleted file mode 100644 index 162d6576cd..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/host/usb_host_ehci.h +++ /dev/null @@ -1,499 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _USB_HOST_CONTROLLER_EHCI_H_ -#define _USB_HOST_CONTROLLER_EHCI_H_ - -/******************************************************************************* - * KHCI private public structures, enumerations, macros, functions - ******************************************************************************/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* EHCI host macros */ -#define EHCI_HOST_T_INVALID_VALUE (1U) -#define EHCI_HOST_POINTER_TYPE_ITD (0x00U) -#define EHCI_HOST_POINTER_TYPE_QH (0x00000002U) -#define EHCI_HOST_POINTER_TYPE_SITD (0x00000004U) -#define EHCI_HOST_POINTER_TYPE_FSTN (0x00000006U) -#define EHCI_HOST_POINTER_TYPE_MASK (0x00000006U) -#define EHCI_HOST_POINTER_ADDRESS_MASK (0xFFFFFFE0U) -#define EHCI_HOST_PID_OUT (0U) -#define EHCI_HOST_PID_IN (1U) -#define EHCI_HOST_PID_SETUP (2U) - -#define EHCI_HOST_QH_RL_SHIFT (28U) -#define EHCI_HOST_QH_RL_MASK (0xF0000000U) -#define EHCI_HOST_QH_C_SHIFT (27U) -#define EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT (16U) -#define EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK (0x07FF0000U) -#define EHCI_HOST_QH_H_SHIFT (15U) -#define EHCI_HOST_QH_DTC_SHIFT (14U) -#define EHCI_HOST_QH_EPS_SHIFT (12U) -#define EHCI_HOST_QH_ENDPT_SHIFT (8U) -#define EHCI_HOST_QH_I_SHIFT (7U) -#define EHCI_HOST_QH_DEVICE_ADDRESS_SHIFT (0U) -#define EHCI_HOST_QH_MULT_SHIFT (30U) -#define EHCI_HOST_QH_PORT_NUMBER_SHIFT (23U) -#define EHCI_HOST_QH_HUB_ADDR_SHIFT (16U) -#define EHCI_HOST_QH_UFRAME_CMASK_SHIFT (8U) -#define EHCI_HOST_QH_UFRAME_SMASK_SHIFT (0U) -#define EHCI_HOST_QH_STATUS_ERROR_MASK (0x0000007EU) -#define EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK (0x0000003EU) - -#define EHCI_HOST_QTD_DT_SHIFT (31U) -#define EHCI_HOST_QTD_DT_MASK (0x80000000U) -#define EHCI_HOST_QTD_TOTAL_BYTES_SHIFT (16U) -#define EHCI_HOST_QTD_TOTAL_BYTES_MASK (0x7FFF0000U) -#define EHCI_HOST_QTD_IOC_MASK (0x00008000U) -#define EHCI_HOST_QTD_C_PAGE_SHIFT (12U) -#define EHCI_HOST_QTD_CERR_SHIFT (10U) -#define EHCI_HOST_QTD_CERR_MAX_VALUE (0x00000003U) -#define EHCI_HOST_QTD_PID_CODE_SHIFT (8U) -#define EHCI_HOST_QTD_STATUS_SHIFT (0U) -#define EHCI_HOST_QTD_CURRENT_OFFSET_MASK (0x00000FFFU) -#define EHCI_HOST_QTD_BUFFER_POINTER_SHIFT (12U) -#define EHCI_HOST_QTD_STATUS_ACTIVE_MASK (0x00000080U) -#define EHCI_HOST_QTD_STATUS_MASK (0x000000ffU) -#define EHCI_HOST_QTD_STATUS_ERROR_MASK (0x0000007EU) -#define EHCI_HOST_QTD_STATUS_STALL_ERROR_MASK (0x00000040U) - -#define EHCI_HOST_ITD_STATUS_ACTIVE_MASK (0x80000000U) -#define EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT (16U) -#define EHCI_HOST_ITD_TRANSACTION_LEN_MASK (0x0FFF0000U) -#define EHCI_HOST_ITD_IOC_SHIFT (15U) -#define EHCI_HOST_ITD_PG_SHIFT (12U) -#define EHCI_HOST_ITD_TRANSACTION_OFFSET_SHIFT (0U) -#define EHCI_HOST_ITD_TRANSACTION_OFFSET_MASK (0x00000FFFU) -#define EHCI_HOST_ITD_BUFFER_POINTER_SHIFT (12U) -#define EHCI_HOST_ITD_ENDPT_SHIFT (8U) -#define EHCI_HOST_ITD_DEVICE_ADDRESS_SHIFT (0U) -#define EHCI_HOST_ITD_MAX_PACKET_SIZE_SHIFT (0U) -#define EHCI_HOST_ITD_MULT_SHIFT (0U) -#define EHCI_HOST_ITD_DIRECTION_SHIFT (11U) - -#define EHCI_HOST_SITD_STATUS_ACTIVE_MASK (0x00000080U) -#define EHCI_HOST_SITD_DIRECTION_SHIFT (31U) -#define EHCI_HOST_SITD_PORT_NUMBER_SHIFT (24U) -#define EHCI_HOST_SITD_HUB_ADDR_SHIFT (16U) -#define EHCI_HOST_SITD_ENDPT_SHIFT (8U) -#define EHCI_HOST_SITD_DEVICE_ADDRESS_SHIFT (0U) -#define EHCI_HOST_SITD_CMASK_SHIFT (8U) -#define EHCI_HOST_SITD_SMASK_SHIFT (0U) -#define EHCI_HOST_SITD_TOTAL_BYTES_SHIFT (16U) -#define EHCI_HOST_SITD_TOTAL_BYTES_MASK (0x03FF0000U) -#define EHCI_HOST_SITD_TP_SHIFT (3U) -#define EHCI_HOST_SITD_TCOUNT_SHIFT (0U) -#define EHCI_HOST_SITD_IOC_SHIFT (31U) - -/* register related MACROs */ -#define EHCI_PORTSC1_W1_BITS (0x0000002AU) -#define EHCI_MAX_UFRAME_VALUE (0x00003FFFU) - -/* task event */ -#define EHCI_TASK_EVENT_DEVICE_ATTACH (0x01U) -#define EHCI_TASK_EVENT_TRANSACTION_DONE (0x02U) -#define EHCI_TASK_EVENT_DEVICE_DETACH (0x04U) -#define EHCI_TASK_EVENT_PORT_CHANGE (0x08U) -#define EHCI_TASK_EVENT_TIMER0 (0x10U) -#define EHCI_TASK_EVENT_TIMER1 (0x20U) - -#define USB_HostEhciLock() USB_OsaMutexLock(ehciInstance->ehciMutex) -#define USB_HostEhciUnlock() USB_OsaMutexUnlock(ehciInstance->ehciMutex) - -/******************************************************************************* - * KHCI driver public structures, enumerations, macros, functions - ******************************************************************************/ - -/*! - * @addtogroup usb_host_controller_ehci - * @{ - */ - -/*! @brief The maximum supported ISO pipe number */ -#define USB_HOST_EHCI_ISO_NUMBER USB_HOST_CONFIG_EHCI_MAX_ITD -/*! @brief Check the port connect state delay if the state is unstable */ -#define USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY (101U) -/*! @brief Delay for port reset */ -#define USB_HOST_EHCI_PORT_RESET_DELAY (11U) -/*! @brief The SITD inserts a frame interval for putting more SITD continuously. - * There is an interval when an application sends two FS/LS ISO transfers. - * When the interval is less than the macro, the two transfers are continuous in the frame list. Otherwise, the two - * transfers - * are not continuous. - * For example: - * - Use case 1: when inserting the SITD first, the inserted frame = the current frame value + this MACRO value. - * - Use case 2: when inserting SITD is not first, choose between the last inserted frame value and the - * current frame value according to the following criteria: - * If the interval is less than the MACRO value, the new SITD is continuous with the last SITD. - * If not, the new SITD inserting frame = the current frame value + this MACRO value. - */ -#define USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER (2U) -/*! @brief The ITD inserts a micro-frame interval for putting more ITD continuously. - * There is an interval when an application sends two HS ISO transfers. - * When the interval is less than the macro, the two transfers are continuous in the frame list. Otherwise, the two - * transfers - * are not continuous. - * For example: - * - Use case 1: when inserting ITD first, the inserted micro-frame = the current micro-frame value + this MACRO value. - * - Use case 2: when inserting ITD is not first, choose between the last inserted micro-frame value and the - * current micro-frame value according to the following criteria: - * If the interval is less than this MACRO value, the new ITD is continuous with the last ITD. - * If not, the new ITD inserting micro-frame = the current micro-frame value + this MACRO value. - */ -#define USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER (16U) -/*! @brief Control or bulk transaction timeout value (unit: 100 ms) */ -#define USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE (20U) - -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) -typedef enum _bus_ehci_suspend_request_state -{ - kBus_EhciIdle = 0U, - kBus_EhciStartSuspend, - kBus_EhciSuspended, - kBus_EhciStartResume, -} bus_ehci_suspend_request_state_t; -#endif - -/*! @brief EHCI state for device attachment/detachment. */ -typedef enum _host_ehci_device_state_ -{ - kEHCIDevicePhyAttached = 1, /*!< Device is physically attached */ - kEHCIDeviceAttached, /*!< Device is attached and initialized */ - kEHCIDeviceDetached, /*!< Device is detached and de-initialized */ -} host_ehci_device_state_t; - -/*! @brief EHCI pipe structure */ -typedef struct _usb_host_ehci_pipe -{ - usb_host_pipe_t pipeCommon; /*!< Common pipe information */ - void *ehciQh; /*!< Control/bulk/interrupt: QH; ISO: usb_host_ehci_iso_t*/ - - /* bandwidth */ - uint16_t uframeInterval; /*!< Micro-frame interval value */ - uint16_t startFrame; /*!< - Bandwidth start frame: its value is from 0 to frame_list. - */ - uint16_t dataTime; /*!< - Bandwidth time value: - - When the host works as HS: it's the data bandwidth value. - - When the host works as FS/LS: - - For FS/LS device, it's the data bandwidth value when transferring the data by FS/LS. - - For HS device, it's the data bandwidth value when transferring the data by HS. - */ - uint16_t startSplitTime; /*!< - Start splitting the bandwidth time value: - - When the host works as HS, it is the start split bandwidth value. - */ - uint16_t completeSplitTime; /*!< - Complete splitting the bandwidth time value: - - When host works as HS, it is the complete split bandwidth value. - */ - uint8_t startUframe; /*!< - Bandwidth start micro-frame: its value is from 0 to 7. - */ - uint8_t uframeSmask; /*!< - Start micro-frame. - - When host works as an HS: - - For FS/LS device, it's the interrupt or ISO transfer start-split mask. - - For HS device, it's the interrupt transfer start micro-frame mask. - - When host works as FS/LS, it's the interrupt and ISO start micro-frame mask - */ - uint8_t uframeCmask; /*!< - Complete micro-frame - - When host works as HS: - - For FS/LS device, it's the interrupt or ISO transfer complete-split mask. - */ -} usb_host_ehci_pipe_t; - -/*! @brief EHCI QH structure. See the USB EHCI specification */ -typedef struct _usb_host_ehci_qh -{ - uint32_t horizontalLinkPointer; /*!< QH specification filed, queue head a horizontal link pointer */ - uint32_t - staticEndpointStates[2]; /*!< QH specification filed, static endpoint state and configuration information */ - uint32_t currentQtdPointer; /*!< QH specification filed, current qTD pointer */ - uint32_t nextQtdPointer; /*!< QH specification filed, next qTD pointer */ - uint32_t alternateNextQtdPointer; /*!< QH specification filed, alternate next qTD pointer */ - uint32_t - transferOverlayResults[6]; /*!< QH specification filed, transfer overlay configuration and transfer results */ - - /* reserved space */ - usb_host_ehci_pipe_t *ehciPipePointer; /*!< EHCI pipe pointer */ - usb_host_transfer_t *ehciTransferHead; /*!< Transfer list head on this QH */ - usb_host_transfer_t *ehciTransferTail; /*!< Transfer list tail on this QH */ - uint16_t timeOutValue; /*!< Its maximum value is USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE. When the value is - zero, the transfer times out. */ - uint16_t timeOutLabel; /*!< It's used to judge the transfer timeout. The EHCI driver maintain the value */ -} usb_host_ehci_qh_t; - -/*! @brief EHCI QTD structure. See the USB EHCI specification. */ -typedef struct _usb_host_ehci_qtd -{ - uint32_t nextQtdPointer; /*!< QTD specification filed, the next QTD pointer */ - uint32_t alternateNextQtdPointer; /*!< QTD specification filed, alternate next QTD pointer */ - uint32_t transferResults[2]; /*!< QTD specification filed, transfer results fields */ - uint32_t bufferPointers[4]; /*!< QTD specification filed, transfer buffer fields */ -} usb_host_ehci_qtd_t; - -/*! @brief EHCI ITD structure. See the USB EHCI specification. */ -typedef struct _usb_host_ehci_itd -{ - uint32_t nextLinkPointer; /*!< ITD specification filed, the next linker pointer */ - uint32_t transactions[8]; /*!< ITD specification filed, transactions information */ - uint32_t bufferPointers[7]; /*!< ITD specification filed, transfer buffer fields */ - - /* add space */ - struct _usb_host_ehci_itd *nextItdPointer; /*!< Next ITD pointer */ - uint32_t frameEntryIndex; /*!< The ITD inserted frame value */ - uint32_t reserved[6]; /*!< Reserved fields for 32 bytes align */ -} usb_host_ehci_itd_t; - -/*! @brief EHCI SITD structure. See the USB EHCI specification. */ -typedef struct _usb_host_ehci_sitd -{ - uint32_t nextLinkPointer; /*!< SITD specification filed, the next linker pointer */ - uint32_t endpointStates[2]; /*!< SITD specification filed, endpoint configuration information */ - uint32_t transferResults[3]; /*!< SITD specification filed, transfer result fields */ - uint32_t backPointer; /*!< SITD specification filed, back pointer */ - - /* reserved space */ - uint16_t frameEntryIndex; /*!< The SITD inserted frame value */ - uint8_t nextSitdIndex; /*!< The next SITD index; Get the next SITD pointer through adding base address with the - index. 0xFF means invalid. */ - uint8_t reserved; /*!< Reserved fields for 32 bytes align */ -} usb_host_ehci_sitd_t; - -/*! @brief EHCI ISO structure; An ISO pipe has an instance of this structure to keep the ISO pipe-specific information. - */ -typedef struct _usb_host_ehci_iso -{ - struct _usb_host_ehci_iso *next; /*!< Next instance pointer */ - usb_host_pipe_t *ehciPipePointer; /*!< This ISO's EHCI pipe pointer */ - usb_host_transfer_t *ehciTransferHead; /*!< Transfer list head on this ISO pipe */ - usb_host_transfer_t *ehciTransferTail; /*!< Transfer list head on this ISO pipe */ - - uint16_t lastLinkFrame; /*!< It means that the inserted frame for ISO ITD/SITD. 0xFFFF is invalid. For ITD, it is a - micro-frame value. For SITD, it is a frame value */ -} usb_host_ehci_iso_t; - -/*! @brief EHCI instance structure */ -typedef struct _usb_host_ehci_instance -{ - usb_host_handle hostHandle; /*!< Related host handle*/ - uint32_t *ehciUnitBase; /*!< Keep the QH/QTD/ITD/SITD buffer pointer for release*/ - uint8_t *ehciFrameList; /*!< The frame list of the current ehci instance*/ - usb_host_ehci_qh_t *ehciQhList; /*!< Idle QH list pointer */ - usb_host_ehci_qtd_t *ehciQtdHead; /*!< Idle QTD list pointer head */ - usb_host_ehci_qtd_t *ehciQtdTail; /*!< Idle QTD list pointer tail (recently used qTD will be used)*/ - usb_host_ehci_itd_t *ehciItdList; /*!< Idle ITD list pointer*/ - usb_host_ehci_sitd_t *ehciSitdIndexBase; /*!< SITD buffer's start pointer*/ - usb_host_ehci_sitd_t *ehciSitdList; /*!< Idle SITD list pointer*/ - usb_host_ehci_iso_t *ehciIsoList; /*!< Idle ISO list pointer*/ - USBHS_Type *ehciIpBase; /*!< EHCI IP base address*/ - usb_host_ehci_qh_t *shedFirstQh; /*!< First async QH*/ - usb_host_ehci_pipe_t *ehciPipeIndexBase; /*!< Pipe buffer's start pointer*/ - usb_host_ehci_pipe_t *ehciPipeList; /*!< Idle pipe list pointer*/ - usb_host_ehci_pipe_t *ehciRunningPipeList; /*!< Running pipe list pointer*/ - usb_osa_mutex_handle ehciMutex; /*!< EHCI mutex*/ - usb_osa_event_handle taskEventHandle; /*!< EHCI task event*/ -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - uint64_t matchTick; - USBPHY_Type *registerPhyBase; /*!< The base address of the PHY register */ -#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) - USBNC_Type *registerNcBase; /*!< The base address of the USBNC register */ -#endif - -#endif - uint8_t controllerId; /*!< EHCI controller ID*/ - uint8_t deviceAttached; /*!< Device attach/detach state, see #host_ehci_device_state_t */ - uint8_t firstDeviceSpeed; /*!< The first device's speed, the controller's work speed*/ - uint8_t ehciItdNumber; /*!< Idle ITD number*/ - uint8_t ehciSitdNumber; /*!< Idle SITD number*/ - uint8_t ehciQtdNumber; /*!< Idle QTD number*/ -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - bus_ehci_suspend_request_state_t busSuspendStatus; /*!< Bus Suspend Status*/ -#endif -} usb_host_ehci_instance_t; - -/*! @brief EHCI data structure */ -typedef struct _usb_host_ehci_data -{ -#if ((defined(USB_HOST_CONFIG_EHCI_MAX_QH)) && (USB_HOST_CONFIG_EHCI_MAX_QH > 0U)) - usb_host_ehci_qh_t ehciQh[USB_HOST_CONFIG_EHCI_MAX_QH]; /*!< Idle QH list array*/ -#endif -#if ((defined(USB_HOST_CONFIG_EHCI_MAX_QTD)) && (USB_HOST_CONFIG_EHCI_MAX_QTD > 0U)) - usb_host_ehci_qtd_t ehciQtd[USB_HOST_CONFIG_EHCI_MAX_QTD]; /*!< Idle QTD list array*/ -#endif -#if ((defined(USB_HOST_CONFIG_EHCI_MAX_ITD)) && (USB_HOST_CONFIG_EHCI_MAX_ITD > 0U)) - usb_host_ehci_itd_t ehciItd[USB_HOST_CONFIG_EHCI_MAX_ITD]; /*!< Idle ITD list array*/ -#endif -#if ((defined(USB_HOST_CONFIG_EHCI_MAX_SITD)) && (USB_HOST_CONFIG_EHCI_MAX_SITD > 0U)) - usb_host_ehci_sitd_t ehciSitd[USB_HOST_CONFIG_EHCI_MAX_SITD]; /*!< Idle SITD list array*/ -#endif -#if ((defined(USB_HOST_EHCI_ISO_NUMBER)) && (USB_HOST_EHCI_ISO_NUMBER > 0U)) - usb_host_ehci_iso_t ehciIso[USB_HOST_EHCI_ISO_NUMBER]; /*!< Idle ISO list array*/ -#endif -#if ((defined(USB_HOST_CONFIG_MAX_PIPES)) && (USB_HOST_CONFIG_MAX_PIPES > 0U)) - usb_host_ehci_pipe_t ehciPipe[USB_HOST_CONFIG_MAX_PIPES]; /*!< Idle pipe list array*/ -#endif -} usb_host_ehci_data_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif -/*! - * @name USB host EHCI APIs - * @{ - */ - -/*! - * @brief Creates the USB host EHCI instance. - * - * This function initializes the USB host EHCI controller driver. - * - * @param[in] controllerId The controller ID of the USB IP. Please refer to the enumeration usb_controller_index_t. - * @param[in] upperLayerHandle The host level handle. - * @param[out] controllerHandle return the controller instance handle. - * - * @retval kStatus_USB_Success The host is initialized successfully. - * @retval kStatus_USB_AllocFail Allocating memory failed. - * @retval kStatus_USB_Error Host mutex create fail, KHCI/EHCI mutex or KHCI/EHCI event create fail. - * Or, KHCI/EHCI IP initialize fail. - */ -extern usb_status_t USB_HostEhciCreate(uint8_t controllerId, - usb_host_handle upperLayerHandle, - usb_host_controller_handle *controllerHandle); - -/*! - * @brief Destroys the USB host EHCI instance. - * - * This function de-initializes The USB host EHCI controller driver. - * - * @param[in] controllerHandle The controller handle. - * - * @retval kStatus_USB_Success The host is initialized successfully. - */ -extern usb_status_t USB_HostEhciDestory(usb_host_controller_handle controllerHandle); - -/*! - * @brief Opens the USB host pipe. - * - * This function opens a pipe according to the pipe_init_ptr parameter. - * - * @param[in] controllerHandle The controller handle. - * @param[out] pipeHandle The pipe handle pointer, it is used to return the pipe handle. - * @param[in] pipeInit It is used to initialize the pipe. - * - * @retval kStatus_USB_Success The host is initialized successfully. - * @retval kStatus_USB_Error There is no idle pipe. - * Or, there is no idle QH for EHCI. - * Or, bandwidth allocate fail for EHCI. - */ -extern usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle, - usb_host_pipe_handle *pipeHandle, - usb_host_pipe_init_t *pipeInit); - -/*! - * @brief Closes the USB host pipe. - * - * This function closes a pipe and releases related resources. - * - * @param[in] controllerHandle The controller handle. - * @param[in] pipeHandle The closing pipe handle. - * - * @retval kStatus_USB_Success The host is initialized successfully. - */ -extern usb_status_t USB_HostEhciClosePipe(usb_host_controller_handle controllerHandle, usb_host_pipe_handle pipeHandle); - -/*! - * @brief Sends data to the pipe. - * - * This function requests to send the transfer to the specified pipe. - * - * @param[in] controllerHandle The controller handle. - * @param[in] pipeHandle The sending pipe handle. - * @param[in] transfer The transfer information. - * - * @retval kStatus_USB_Success Sent successfully. - * @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI. - * @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI. - */ -extern usb_status_t USB_HostEhciWritePipe(usb_host_controller_handle controllerHandle, - usb_host_pipe_handle pipeHandle, - usb_host_transfer_t *transfer); - -/*! - * @brief Receives data from the pipe. - * - * This function requests to receive the transfer from the specified pipe. - * - * @param[in] controllerHandle The controller handle. - * @param[in] pipeHandle The receiving pipe handle. - * @param[in] transfer The transfer information. - - * @retval kStatus_USB_Success Send successfully. - * @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI. - * @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI. - */ -extern usb_status_t USB_HostEhciReadpipe(usb_host_controller_handle controllerHandle, - usb_host_pipe_handle pipeHandle, - usb_host_transfer_t *transfer); - -/*! - * @brief Controls the EHCI. - * - * This function controls the EHCI. - * - * @param[in] controllerHandle The controller handle. - * @param[in] ioctlEvent See enumeration host_bus_control_t. - * @param[in] ioctlParam The control parameter. - * - * @retval kStatus_USB_Success Cancel successfully. - * @retval kStatus_USB_InvalidHandle The controllerHandle is a NULL pointer. - */ -extern usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandle, - uint32_t ioctlEvent, - void *ioctlParam); - -/*! @}*/ - -#ifdef __cplusplus -} -#endif - -/*! @}*/ - -#endif /* _USB_HOST_CONTROLLER_EHCI_H_ */ diff --git a/bsp/imxrt1052-evk/drivers/usb/host/usb_host_hci.c b/bsp/imxrt1052-evk/drivers/usb/host/usb_host_hci.c deleted file mode 100644 index 927bf8bd9c..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/host/usb_host_hci.c +++ /dev/null @@ -1,1052 +0,0 @@ -/* - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include "fsl_common.h" -#include "usb_host.h" -#include "usb_host_hci.h" -#include "usb_host_devices.h" -#include "fsl_device_registers.h" -#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) -#include "fsl_cache.h" -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - -extern uint32_t USB_HostHubGetTotalThinkTime(usb_host_handle hostHandle, uint8_t parentHubNo); - -extern usb_status_t USB_HostHubSuspendDevice(usb_host_handle hostHandle); - -extern usb_status_t USB_HostHubResumeDevice(usb_host_handle hostHandle); -#endif - -/*! - * @brief get the idle host instance. - * - * @return host instance pointer. - */ -static usb_host_instance_t *USB_HostGetInstance(void); - -/*! - * @brief release host instance. - * - * @param hostInstance host instance pointer. - */ -static void USB_HostReleaseInstance(usb_host_instance_t *hostInstance); - -/*! - * @brief get the khci/ehci interface. - * - * @param controllerId controller id. - * @param controllerTable return controller interface structure. - */ -static void USB_HostGetControllerInterface(uint8_t controllerId, - const usb_host_controller_interface_t **controllerTable); - -#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) -#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) -extern void USB_HostEhciTestModeInit(usb_device_handle devHandle); -#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ -#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS)) -extern void USB_HostIp3516HsTestModeInit(usb_device_handle devHandle); -#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ -#endif /* USB_HOST_CONFIG_EHCI */ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief USB host instance resource */ -usb_host_instance_t g_UsbHostInstance[USB_HOST_CONFIG_MAX_HOST]; - -#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) -#include "usb_host_ehci.h" -static const usb_host_controller_interface_t s_EhciInterface = \ -{ - USB_HostEhciCreate, USB_HostEhciDestory, USB_HostEhciOpenPipe, USB_HostEhciClosePipe, - USB_HostEhciWritePipe, USB_HostEhciReadpipe, USB_HostEhciIoctl, -}; -#endif /* USB_HOST_CONFIG_EHCI */ - -#if ((defined USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI)) -#include "usb_host_khci.h" -static const usb_host_controller_interface_t s_KhciInterface = \ -{ - USB_HostKhciCreate, USB_HostKhciDestory, USB_HostKhciOpenPipe, USB_HostKhciClosePipe, - USB_HostKhciWritePipe, USB_HostKhciReadpipe, USB_HostKciIoctl, -}; -#endif /* USB_HOST_CONFIG_KHCI */ - -#if ((defined USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI > 0U)) -#include "usb_host_ohci.h" -static const usb_host_controller_interface_t s_OhciInterface = \ -{ - USB_HostOhciCreate, USB_HostOhciDestory, USB_HostOhciOpenPipe, USB_HostOhciClosePipe, - USB_HostOhciWritePipe, USB_HostOhciReadPipe, USB_HostOhciIoctl, -}; -#endif /* USB_HOST_CONFIG_OHCI */ - -#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS > 0U)) -#include "usb_host_ip3516hs.h" -static const usb_host_controller_interface_t s_Ip3516HsInterface = \ -{ - USB_HostIp3516HsCreate, USB_HostIp3516HsDestory, USB_HostIp3516HsOpenPipe, USB_HostIp3516HsClosePipe, - USB_HostIp3516HsWritePipe, USB_HostIp3516HsReadPipe, USB_HostIp3516HsIoctl, -}; -#endif /* USB_HOST_CONFIG_IP3516HS */ - -USB_DMA_NONINIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE) static uint8_t s_Setupbuffer[USB_HOST_CONFIG_MAX_HOST][USB_HOST_CONFIG_MAX_TRANSFERS][USB_DATA_ALIGN_SIZE_MULTIPLE(8)]; -/******************************************************************************* -* Code -******************************************************************************/ - -#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) -/*FUNCTION*---------------------------------------------------------------- -* -* Function Name : usb_test_mode_init -* Returned Value : None -* Comments : -* This function is called by common class to initialize the class driver. It -* is called in response to a select interface call by application -* -*END*--------------------------------------------------------------------*/ -usb_status_t USB_HostTestModeInit(usb_device_handle deviceHandle) -{ -#if (((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) || \ - ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS))) - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; -#endif - uint32_t productId; - uint32_t vendorId; - - usb_echo("usb host test init\r\n"); - USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDevicePID, &productId); - USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDeviceVID, &vendorId); - usb_echo(" vendor id :0x%x product id:0x%x \r\n", vendorId, productId); - - if ((productId != 0x0200U) && (productId != 0x0101) && (productId != 0x0102) && (productId != 0x0103) && - (productId != 0x0104) && (productId != 0x0105) && (productId != 0x0106) && (productId != 0x0107) && - (productId != 0x0108)) - { - usb_echo("Unsupported Device\r\n"); - } - - if (productId == 0x0200U) - { - usb_echo("PET test device attached\r\n"); - } - else - { -#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) - if (hostInstance->controllerTable == &s_EhciInterface) - { - USB_HostEhciTestModeInit(deviceHandle); - } -#elif((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS)) - if (hostInstance->controllerTable == &s_Ip3516HsInterface) - { - USB_HostIp3516HsTestModeInit(deviceHandle); - } -#endif - } - - return kStatus_USB_Success; -} -#endif - -static usb_host_instance_t *USB_HostGetInstance(void) -{ - uint8_t i = 0; - uint32_t index = 0; - USB_OSA_SR_ALLOC(); - USB_OSA_ENTER_CRITICAL(); - for (; i < USB_HOST_CONFIG_MAX_HOST; i++) - { - if (g_UsbHostInstance[i].occupied != 1) - { - uint8_t *buffer = (uint8_t *)&g_UsbHostInstance[i]; - for (uint32_t j = 0U; j < sizeof(usb_host_instance_t); j++) - { - buffer[j] = 0x00U; - } - g_UsbHostInstance[i].occupied = 1; - USB_OSA_EXIT_CRITICAL(); - for (index = 0; index < USB_HOST_CONFIG_MAX_TRANSFERS; ++index) - { - g_UsbHostInstance[i].transferList[index].setupPacket = - (usb_setup_struct_t *)&(s_Setupbuffer[i][index][0]); - } - return &g_UsbHostInstance[i]; - } - } - USB_OSA_EXIT_CRITICAL(); - return NULL; -} - -static void USB_HostReleaseInstance(usb_host_instance_t *hostInstance) -{ - USB_OSA_SR_ALLOC(); - USB_OSA_ENTER_CRITICAL(); - hostInstance->occupied = 0; - USB_OSA_EXIT_CRITICAL(); -} - -static void USB_HostGetControllerInterface(uint8_t controllerId, - const usb_host_controller_interface_t **controllerTable) -{ -#if ((defined USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI)) - if (controllerId == kUSB_ControllerKhci0) - { - *controllerTable = &s_KhciInterface; - } -#endif /* USB_HOST_CONFIG_KHCI */ - -#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) - if ((controllerId == kUSB_ControllerEhci0) || (controllerId == kUSB_ControllerEhci1)) - { - *controllerTable = &s_EhciInterface; - } -#endif /* USB_HOST_CONFIG_EHCI */ - -#if ((defined USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI > 0U)) - if (controllerId == kUSB_ControllerOhci0) - { - *controllerTable = &s_OhciInterface; - } -#endif /* USB_HOST_CONFIG_OHCI */ - -#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS > 0U)) - if (controllerId == kUSB_ControllerIp3516Hs0) - { - *controllerTable = &s_Ip3516HsInterface; - } -#endif /* USB_HOST_CONFIG_IP3516HS */ -} - -usb_status_t USB_HostInit(uint8_t controllerId, usb_host_handle *hostHandle, host_callback_t callbackFn) -{ - usb_status_t status = kStatus_USB_Success; - usb_host_instance_t *hostInstance = NULL; - usb_host_transfer_t *transferPrev = NULL; - uint8_t i = 0; - - hostInstance = USB_HostGetInstance(); /* get one host instance */ - if (hostInstance == NULL) - { - return kStatus_USB_InvalidHandle; - } - - /* get khci/ehci API table */ - USB_HostGetControllerInterface(controllerId, &hostInstance->controllerTable); - if (hostInstance->controllerTable == NULL) - { - USB_HostReleaseInstance(hostInstance); - return kStatus_USB_ControllerNotFound; - } - - /* judge the controller interface one time at here */ - if ((hostInstance->controllerTable->controllerCreate == NULL) || - (hostInstance->controllerTable->controllerDestory == NULL) || - (hostInstance->controllerTable->controllerOpenPipe == NULL) || - (hostInstance->controllerTable->controllerClosePipe == NULL) || - (hostInstance->controllerTable->controllerWritePipe == NULL) || - (hostInstance->controllerTable->controllerReadPipe == NULL) || - (hostInstance->controllerTable->controllerIoctl == NULL)) - { - return kStatus_USB_Error; - } - - /* HOST instance init*/ - hostInstance->controllerId = controllerId; - hostInstance->deviceCallback = callbackFn; - hostInstance->deviceList = NULL; - if (kStatus_USB_OSA_Success != USB_OsaMutexCreate(&hostInstance->hostMutex)) - { - USB_HostReleaseInstance(hostInstance); -#ifdef HOST_ECHO - usb_echo("host init: create host mutex fail\r\n"); -#endif - return kStatus_USB_Error; - } - - /* initialize transfer list */ - - hostInstance->transferHead = &hostInstance->transferList[0]; - transferPrev = hostInstance->transferHead; - for (i = 1; i < USB_HOST_CONFIG_MAX_TRANSFERS; ++i) - { - transferPrev->next = &hostInstance->transferList[i]; - transferPrev = transferPrev->next; - } - - /* controller create */ - status = - hostInstance->controllerTable->controllerCreate(controllerId, hostInstance, &(hostInstance->controllerHandle)); - if ((status != kStatus_USB_Success) || (hostInstance->controllerHandle == NULL)) - { - USB_OsaMutexDestroy(hostInstance->hostMutex); - USB_HostReleaseInstance(hostInstance); -#ifdef HOST_ECHO - usb_echo("host init: controller init fail\r\n"); -#endif - return kStatus_USB_Error; - } - - *hostHandle = hostInstance; - return kStatus_USB_Success; -} - -usb_status_t USB_HostDeinit(usb_host_handle hostHandle) -{ - usb_status_t status = kStatus_USB_Success; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - usb_host_device_instance_t *deviceInstance = NULL; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - - /* device list detach */ - deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; - while (deviceInstance != NULL) - { - deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; - USB_HostDetachDeviceInternal(hostHandle, deviceInstance); - } - - /* controller instance destory */ - status = hostInstance->controllerTable->controllerDestory(hostInstance->controllerHandle); - hostInstance->controllerHandle = NULL; - if (status != kStatus_USB_Success) - { -#ifdef HOST_ECHO - usb_echo("host controller destory fail\r\n"); -#endif - } - - /* resource release */ - if (hostInstance->hostMutex) - { - USB_OsaMutexDestroy(hostInstance->hostMutex); - hostInstance->hostMutex = NULL; - } - USB_HostReleaseInstance(hostInstance); - - return status; -} - -usb_status_t USB_HostOpenPipe(usb_host_handle hostHandle, - usb_host_pipe_handle *pipeHandle, - usb_host_pipe_init_t *pipeInit) -{ - usb_status_t status = kStatus_USB_Success; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - - if ((hostHandle == NULL) || (pipeInit == NULL)) - { - return kStatus_USB_InvalidHandle; - } - - /* call controller open pipe interface */ - status = hostInstance->controllerTable->controllerOpenPipe(hostInstance->controllerHandle, pipeHandle, pipeInit); - - return status; -} - -usb_status_t USB_HostClosePipe(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle) -{ - usb_status_t status = kStatus_USB_Success; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - - if ((hostHandle == NULL) || (pipeHandle == NULL)) - { - return kStatus_USB_InvalidHandle; - } - - /* call controller close pipe interface */ - status = hostInstance->controllerTable->controllerClosePipe(hostInstance->controllerHandle, pipeHandle); - - return status; -} - -usb_status_t USB_HostSend(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle, usb_host_transfer_t *transfer) -{ - usb_status_t status = kStatus_USB_Success; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - - if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL)) - { - return kStatus_USB_InvalidHandle; - } - - /* initialize transfer */ - transfer->transferSofar = 0; - transfer->direction = USB_OUT; - - USB_HostLock(); /* This api can be called by host task and app task */ -/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function - */ -#if 0 - if ((USB_HostValidateDevice(pipe_ptr->deviceHandle) != kStatus_USB_Success) || (!(USB_HostGetDeviceAttachState(pipe_ptr->deviceHandle)))) - { - USB_HostUnlock(); - return status; - } -#endif -/* call controller write pipe interface */ -#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) - if (transfer->transferLength > 0) - { - DCACHE_CleanByRange((uint32_t)transfer->transferBuffer, transfer->transferLength); - } -#endif - status = hostInstance->controllerTable->controllerWritePipe(hostInstance->controllerHandle, pipeHandle, transfer); - - USB_HostUnlock(); - return status; -} - -usb_status_t USB_HostSendSetup(usb_host_handle hostHandle, - usb_host_pipe_handle pipeHandle, - usb_host_transfer_t *transfer) -{ - usb_status_t status = kStatus_USB_Success; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - - if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL)) - { - return kStatus_USB_InvalidHandle; - } - - /* initialize transfer */ - transfer->transferSofar = 0; - transfer->next = NULL; - transfer->setupStatus = 0; - if ((transfer->setupPacket->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_IN) - { - transfer->direction = USB_IN; - } - else - { - transfer->direction = USB_OUT; - } - - USB_HostLock(); /* This API can be called by host task and application task */ -/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function - */ -#if 0 - if ((USB_HostValidateDevice(pipe_ptr->deviceHandle) != kStatus_USB_Success) || (!(USB_HostGetDeviceAttachState(pipe_ptr->deviceHandle)))) - { - USB_HostUnlock(); - return status; - } -#endif -/* call controller write pipe interface */ -#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) - DCACHE_CleanByRange((uint32_t)&transfer->setupPacket->bmRequestType, sizeof(usb_setup_struct_t)); - if (transfer->transferLength > 0) - { - DCACHE_CleanInvalidateByRange((uint32_t)transfer->transferBuffer, transfer->transferLength); - } -#endif - status = hostInstance->controllerTable->controllerWritePipe(hostInstance->controllerHandle, pipeHandle, transfer); - - USB_HostUnlock(); - return status; -} - -usb_status_t USB_HostRecv(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle, usb_host_transfer_t *transfer) -{ - usb_status_t status = kStatus_USB_Success; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - - if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL)) - { - return kStatus_USB_InvalidHandle; - } - - /* initialize transfer */ - transfer->transferSofar = 0; - transfer->direction = USB_IN; - - USB_HostLock(); /* This API can be called by host task and application task */ -/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function - */ -#if 0 - if ((USB_HostValidateDevice(pipe_ptr->deviceHandle) != kStatus_USB_Success) || (!(USB_HostGetDeviceAttachState(pipe_ptr->deviceHandle)))) - { - USB_HostUnlock(); - return status; - } -#endif - -#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) - if (transfer->transferLength > 0) - { - DCACHE_CleanInvalidateByRange((uint32_t)transfer->transferBuffer, transfer->transferLength); - } -#endif - status = hostInstance->controllerTable->controllerReadPipe(hostInstance->controllerHandle, pipeHandle, transfer); - - USB_HostUnlock(); - return status; -} - -usb_status_t USB_HostCancelTransfer(usb_host_handle hostHandle, - usb_host_pipe_handle pipeHandle, - usb_host_transfer_t *transfer) -{ - usb_status_t status = kStatus_USB_Success; - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - usb_host_cancel_param_t cancelParam; - - if ((hostHandle == NULL) || (pipeHandle == NULL)) - { - return kStatus_USB_InvalidHandle; - } - - /* initialize cancel parameter */ - cancelParam.pipeHandle = pipeHandle; - cancelParam.transfer = transfer; - - /* USB_HostLock(); This api can be called by host task and app task */ - status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostCancelTransfer, - &cancelParam); - /* USB_HostUnlock(); */ - - return status; -} - -usb_status_t USB_HostMallocTransfer(usb_host_handle hostHandle, usb_host_transfer_t **transfer) -{ - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - - if ((hostHandle == NULL) || (transfer == NULL)) - { - return kStatus_USB_InvalidHandle; - } - - /* get one from the transfer_head */ - USB_HostLock(); - if (hostInstance->transferHead != NULL) - { - *transfer = hostInstance->transferHead; - hostInstance->transferHead = hostInstance->transferHead->next; - USB_HostUnlock(); - return kStatus_USB_Success; - } - else - { - *transfer = NULL; - USB_HostUnlock(); - return kStatus_USB_Error; - } -} - -usb_status_t USB_HostFreeTransfer(usb_host_handle hostHandle, usb_host_transfer_t *transfer) -{ - usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - if (transfer == NULL) - { - return kStatus_USB_Success; - } - - /* release one to the transfer_head */ - USB_HostLock(); - transfer->next = hostInstance->transferHead; - hostInstance->transferHead = transfer; - USB_HostUnlock(); - return kStatus_USB_Success; -} - -usb_status_t USB_HostHelperGetPeripheralInformation(usb_device_handle deviceHandle, - uint32_t infoCode, - uint32_t *infoValue) -{ - usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; - if ((deviceHandle == NULL) || (infoValue == NULL)) - { - return kStatus_USB_InvalidParameter; - } - - switch (infoCode) - { - case kUSB_HostGetDeviceAddress: /* device address */ - *infoValue = (uint32_t)deviceInstance->setAddress; - break; - - case kUSB_HostGetDeviceControlPipe: /* device control pipe */ - *infoValue = (uint32_t)deviceInstance->controlPipe; - break; - - case kUSB_HostGetHostHandle: /* device host handle */ - *infoValue = (uint32_t)deviceInstance->hostHandle; - break; - -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - case kUSB_HostGetDeviceHubNumber: /* device hub address */ - *infoValue = (uint32_t)deviceInstance->hubNumber; - break; - - case kUSB_HostGetDevicePortNumber: /* device port no */ - *infoValue = (uint32_t)deviceInstance->portNumber; - break; - - case kUSB_HostGetDeviceLevel: /* device level */ - *infoValue = (uint32_t)deviceInstance->level; - break; - - case kUSB_HostGetDeviceHSHubNumber: /* device high-speed hub address */ - *infoValue = (uint32_t)deviceInstance->hsHubNumber; - break; - - case kUSB_HostGetDeviceHSHubPort: /* device high-speed hub port no */ - *infoValue = (uint32_t)deviceInstance->hsHubPort; - break; - - case kUSB_HostGetHubThinkTime: /* device hub think time */ - *infoValue = USB_HostHubGetTotalThinkTime(deviceInstance->hostHandle, deviceInstance->hubNumber); - break; -#else - case kUSB_HostGetDeviceHubNumber: /* device hub address */ - case kUSB_HostGetDevicePortNumber: /* device port no */ - case kUSB_HostGetDeviceHSHubNumber: /* device high-speed hub address */ - case kUSB_HostGetDeviceHSHubPort: /* device high-speed hub port no */ - case kUSB_HostGetHubThinkTime: /* device hub think time */ - *infoValue = 0; - break; - case kUSB_HostGetDeviceLevel: /* device level */ - *infoValue = 1; - break; -#endif /* USB_HOST_CONFIG_HUB */ - - case kUSB_HostGetDeviceSpeed: /* device speed */ - *infoValue = (uint32_t)deviceInstance->speed; - break; - - case kUSB_HostGetDevicePID: /* device pid */ - *infoValue = (uint32_t)USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(deviceInstance->deviceDescriptor->idProduct); - break; - - case kUSB_HostGetDeviceVID: /* device vid */ - *infoValue = (uint32_t)USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(deviceInstance->deviceDescriptor->idVendor); - break; - - case kUSB_HostGetDeviceConfigIndex: /* device config index */ - *infoValue = (uint32_t)deviceInstance->configurationValue - 1U; - break; - - case kUSB_HostGetConfigurationDes: /* configuration descriptor pointer */ - *infoValue = (uint32_t)deviceInstance->configurationDesc; - break; - - case kUSB_HostGetConfigurationLength: /* configuration descriptor length */ - *infoValue = (uint32_t)deviceInstance->configurationLen; - break; - - default: - return kStatus_USB_Error; - } - - return kStatus_USB_Success; -} - -usb_status_t USB_HostHelperParseAlternateSetting(usb_host_interface_handle interfaceHandle, - uint8_t alternateSetting, - usb_host_interface_t *interface) -{ - uint32_t endPosition; - usb_descriptor_union_t *unionDes; - usb_host_ep_t *epParse; - - if (interfaceHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - - if (alternateSetting == 0) - { - return kStatus_USB_InvalidParameter; - } - - /* parse configuration descriptor */ - unionDes = (usb_descriptor_union_t *)((usb_host_interface_t *)interfaceHandle) - ->interfaceDesc; /* interface extend descriptor start */ - endPosition = - (uint32_t)unionDes + - ((usb_host_interface_t *)interfaceHandle)->interfaceExtensionLength; /* interface extend descriptor end */ - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - - /* search for the alternate setting interface descritpor */ - while ((uint32_t)unionDes < endPosition) - { - if (unionDes->interface.bDescriptorType == USB_DESCRIPTOR_TYPE_INTERFACE) - { - if (unionDes->interface.bAlternateSetting == alternateSetting) - { - break; - } - else - { - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - } - } - else - { - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - } - } - if ((uint32_t)unionDes >= endPosition) - { - return kStatus_USB_Error; - } - - /* initialize interface handle structure instance */ - interface->interfaceDesc = &unionDes->interface; - interface->alternateSettingNumber = 0; - interface->epCount = 0; - interface->interfaceExtension = NULL; - interface->interfaceExtensionLength = 0; - interface->interfaceIndex = unionDes->interface.bInterfaceNumber; - - /* search for endpoint descriptor start position */ - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - while ((uint32_t)unionDes < endPosition) - { - if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) && - (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) - { - if (interface->interfaceExtension == NULL) - { - interface->interfaceExtension = (uint8_t *)unionDes; - } - interface->interfaceExtensionLength += unionDes->common.bLength; - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - } - else - { - break; - } - } - - /* parse endpoint descriptor */ - if (interface->interfaceDesc->bNumEndpoints != 0) - { - if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) || - (interface->interfaceDesc->bNumEndpoints > USB_HOST_CONFIG_INTERFACE_MAX_EP)) - { -#ifdef HOST_ECHO - usb_echo("interface descriptor error\n"); -#endif - return kStatus_USB_Error; - } - for (; interface->epCount < interface->interfaceDesc->bNumEndpoints; (interface->epCount)++) - { - if (((uint32_t)unionDes >= endPosition) || - (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) - { -#ifdef HOST_ECHO - usb_echo("endpoint descriptor error\n"); -#endif - return kStatus_USB_Error; - } - epParse = (usb_host_ep_t *)&interface->epList[interface->epCount]; - epParse->epDesc = (usb_descriptor_endpoint_t *)unionDes; - epParse->epExtensionLength = 0; - epParse->epExtension = NULL; - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - while ((uint32_t)unionDes < endPosition) - { - if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) && - (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE)) - { - if (epParse->epExtension == NULL) - { - epParse->epExtension = (uint8_t *)unionDes; - } - epParse->epExtensionLength += unionDes->common.bLength; - unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); - } - else - { - break; - } - } - } - } - - return kStatus_USB_Success; -} - -void USB_HostGetVersion(uint32_t *version) -{ - if (version) - { - *version = - (uint32_t)USB_MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX); - } -} - -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) -/* Send BUS or specific device suepend request */ -usb_status_t USB_HostSuspendDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle) -{ - usb_host_instance_t *hostInstance; - usb_host_device_instance_t *deviceInstance; - usb_status_t status = kStatus_USB_Error; - usb_host_bus_control_t type = kUSB_HostBusSuspend; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - hostInstance = (usb_host_instance_t *)hostHandle; - - hostInstance->suspendedDevice = (void *)deviceHandle; - - if (NULL == deviceHandle) - { -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - status = USB_HostHubSuspendDevice(hostInstance); -#else - status = - hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); -#endif - } - else - { -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - deviceInstance = (usb_host_device_instance_t *)deviceHandle; - if (0 == deviceInstance->hubNumber) - { -#endif - if (hostInstance->deviceList == deviceHandle) - { - status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, - kUSB_HostBusControl, &type); - } -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - } - else - { - if (kStatus_USB_Success == USB_HostValidateDevice(hostInstance, deviceHandle)) - { - status = USB_HostHubSuspendDevice(hostInstance); - } - } -#endif - } - if (kStatus_USB_Error == status) - { - hostInstance->suspendedDevice = NULL; - } - return status; -} - -/* Send BUS or specific device resume request */ -usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle) -{ - usb_host_instance_t *hostInstance; - usb_host_device_instance_t *deviceInstance; - usb_status_t status = kStatus_USB_Error; - usb_host_bus_control_t type = kUSB_HostBusResume; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - hostInstance = (usb_host_instance_t *)hostHandle; - - if (hostInstance->suspendedDevice != deviceHandle) - { - return kStatus_USB_InvalidParameter; - } - hostInstance->suspendedDevice = (void *)deviceHandle; - - if (NULL == deviceHandle) - { - status = - hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); - } - else - { -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - deviceInstance = (usb_host_device_instance_t *)deviceHandle; - if (0 == deviceInstance->hubNumber) - { -#endif - if (hostInstance->deviceList == deviceHandle) - { - status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, - kUSB_HostBusControl, &type); - } -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) - } - else - { - if (kStatus_USB_Success == USB_HostValidateDevice(hostInstance, deviceHandle)) - { - status = USB_HostHubResumeDevice(hostInstance); - } - } -#endif - } - - return status; -} -#if ((defined(USB_HOST_CONFIG_LPM_L1)) && (USB_HOST_CONFIG_LPM_L1 > 0U)) -/* Send BUS or specific device suepend request */ -usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle, - usb_device_handle deviceHandle, - uint8_t sleepType) -{ - usb_host_instance_t *hostInstance; - usb_status_t status = kStatus_USB_Error; - usb_host_bus_control_t type = kUSB_HostBusL1Sleep; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - hostInstance = (usb_host_instance_t *)hostHandle; - - hostInstance->suspendedDevice = (void *)deviceHandle; - - if (1U == sleepType) - { - /*#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))*/ - /*To do, implete hub L1 suspend device*/ - /*#else*/ - status = - hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); - /*#endif*/ - } - else - { -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) -/*To do, if device hub number is 0, need suspend the bus ,else suspend the corresponding device*/ -#endif - if (hostInstance->deviceList == deviceHandle) - { - status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, - &type); - } - } - if (kStatus_USB_Error == status) - { - hostInstance->suspendedDevice = NULL; - } - return status; -} -/* Send BUS or specific device suepend request */ -usb_status_t USB_HostL1SleepDeviceResquestConfig(usb_host_handle hostHandle, uint8_t *lpmParam) -{ - usb_host_instance_t *hostInstance; - usb_status_t status = kStatus_USB_Error; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - hostInstance = (usb_host_instance_t *)hostHandle; - - status = - hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostL1Config, lpmParam); - - return status; -} - -/* Send BUS or specific device resume request */ -usb_status_t USB_HostL1ResumeDeviceResquest(usb_host_handle hostHandle, - usb_device_handle deviceHandle, - uint8_t sleepType) -{ - usb_host_instance_t *hostInstance; - - usb_status_t status = kStatus_USB_Error; - usb_host_bus_control_t type = kUSB_HostBusL1Resume; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - hostInstance = (usb_host_instance_t *)hostHandle; - - if (1U == sleepType) - { - status = - hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); - } - else - { -#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) -/*To do, if device hub number is 0, need suspend the bus ,else suspend the corresponding device*/ - -#endif - if (hostInstance->deviceList == deviceHandle) - { - status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, - &type); - } - } - - return status; -} -#endif -/* Update HW tick(unit is ms) */ -usb_status_t USB_HostUpdateHwTick(usb_host_handle hostHandle, uint64_t tick) -{ - usb_host_instance_t *hostInstance; - usb_status_t status = kStatus_USB_Success; - - if (hostHandle == NULL) - { - return kStatus_USB_InvalidHandle; - } - hostInstance = (usb_host_instance_t *)hostHandle; - - hostInstance->hwTick = tick; - - return status; -} -#endif diff --git a/bsp/imxrt1052-evk/drivers/usb/host/usb_host_hci.h b/bsp/imxrt1052-evk/drivers/usb/host/usb_host_hci.h deleted file mode 100644 index 26b6d4a9c5..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/host/usb_host_hci.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _USB_HOST_HCI_H_ -#define _USB_HOST_HCI_H_ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief USB host lock */ -#define USB_HostLock() USB_OsaMutexLock(hostInstance->hostMutex) -/*! @brief USB host unlock */ -#define USB_HostUnlock() USB_OsaMutexUnlock(hostInstance->hostMutex) - -/*! - * @addtogroup usb_host_controller_driver - * @{ - */ - -/*! @brief USB host controller control code */ -typedef enum _usb_host_controller_control -{ - kUSB_HostCancelTransfer = 1U, /*!< Cancel transfer code */ - kUSB_HostBusControl, /*!< Bus control code */ - kUSB_HostGetFrameNumber, /*!< Get frame number code */ - kUSB_HostUpdateControlEndpointAddress, /*!< Update control endpoint address */ - kUSB_HostUpdateControlPacketSize, /*!< Update control endpoint maximum packet size */ - kUSB_HostPortAttachDisable, /*!< Disable the port attach event */ - kUSB_HostPortAttachEnable, /*!< Enable the port attach event */ - kUSB_HostL1Config, /*!< L1 suspend Bus control code */ -} usb_host_controller_control_t; - -/*! @brief USB host controller bus control code */ -typedef enum _usb_host_bus_control -{ - kUSB_HostBusReset = 1U, /*!< Reset bus */ - kUSB_HostBusRestart, /*!< Restart bus */ - kUSB_HostBusEnableAttach, /*!< Enable attach */ - kUSB_HostBusDisableAttach, /*!< Disable attach */ - kUSB_HostBusSuspend, /*!< Suspend BUS */ - kUSB_HostBusResume, /*!< Resume BUS */ - kUSB_HostBusL1SuspendInit, /*!< L1 Suspend BUS */ - kUSB_HostBusL1Sleep, /*!< L1 Suspend BUS */ - kUSB_HostBusL1Resume, /*!< L1 Resume BUS */ -} usb_host_bus_control_t; - -/*! @brief USB host controller interface structure */ -typedef struct _usb_host_controller_interface -{ - usb_status_t (*controllerCreate)( - uint8_t controllerId, - usb_host_handle upperLayerHandle, - usb_host_controller_handle *controllerHandle); /*!< Create a controller instance function prototype*/ - usb_status_t (*controllerDestory)( - usb_host_controller_handle controllerHandle); /*!< Destroy a controller instance function prototype*/ - usb_status_t (*controllerOpenPipe)(usb_host_controller_handle controllerHandle, - usb_host_pipe_handle *pipeHandle, - usb_host_pipe_init_t *pipeInit); /*!< Open a controller pipe function prototype*/ - usb_status_t (*controllerClosePipe)( - usb_host_controller_handle controllerHandle, - usb_host_pipe_handle pipeHandle); /*!< Close a controller pipe function prototype*/ - usb_status_t (*controllerWritePipe)(usb_host_controller_handle controllerHandle, - usb_host_pipe_handle pipeHandle, - usb_host_transfer_t *transfer); /*!< Write data to a pipe function prototype*/ - usb_status_t (*controllerReadPipe)(usb_host_controller_handle controllerHandle, - usb_host_pipe_handle pipeHandle, - usb_host_transfer_t *transfer); /*!< Read data from a pipe function prototype*/ - usb_status_t (*controllerIoctl)(usb_host_controller_handle controllerHandle, - uint32_t ioctlEvent, - void *ioctlParam); /*!< Control a controller function prototype*/ -} usb_host_controller_interface_t; - -/*! @}*/ - -/*! - * @addtogroup usb_host_drv - * @{ - */ - -/*! @brief USB host instance structure */ -typedef struct _usb_host_instance -{ - void *controllerHandle; /*!< The low level controller handle*/ - host_callback_t deviceCallback; /*!< Device attach/detach callback*/ - usb_osa_mutex_handle hostMutex; /*!< Host layer mutex*/ - usb_host_transfer_t transferList[USB_HOST_CONFIG_MAX_TRANSFERS]; /*!< Transfer resource*/ - usb_host_transfer_t *transferHead; /*!< Idle transfer head*/ - const usb_host_controller_interface_t *controllerTable; /*!< KHCI/EHCI interface*/ - void *deviceList; /*!< Device list*/ -#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) - void *suspendedDevice; /*!< Suspended device handle*/ - volatile uint64_t hwTick; /*!< Current hw tick(ms)*/ - uint8_t sleepType; /*!< L1 LPM device handle*/ -#endif - uint8_t addressBitMap[16]; /*!< Used for address allocation. The first bit is the address 1, second bit is the - address 2*/ - uint8_t occupied; /*!< 0 - the instance is not occupied; 1 - the instance is occupied*/ - uint8_t controllerId; /*!< The controller ID*/ -} usb_host_instance_t; - -/*! @}*/ - -#endif /* _USB_HOST_HCI_H_ */ diff --git a/bsp/imxrt1052-evk/drivers/usb/include/usb.h b/bsp/imxrt1052-evk/drivers/usb/include/usb.h deleted file mode 100644 index 256896b472..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/include/usb.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __USB_H__ -#define __USB_H__ - -#include -#include -#include -#include "usb_misc.h" -#include "usb_spec.h" - -/*! - * @addtogroup usb_drv - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Defines USB stack major version */ -#define USB_STACK_VERSION_MAJOR (1U) -/*! @brief Defines USB stack minor version */ -#define USB_STACK_VERSION_MINOR (6U) -/*! @brief Defines USB stack bugfix version */ -#define USB_STACK_VERSION_BUGFIX (3U) - -/*! @brief USB stack version definition */ -#define USB_MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) - -/*! @brief USB error code */ -typedef enum _usb_status -{ - kStatus_USB_Success = 0x00U, /*!< Success */ - kStatus_USB_Error, /*!< Failed */ - - kStatus_USB_Busy, /*!< Busy */ - kStatus_USB_InvalidHandle, /*!< Invalid handle */ - kStatus_USB_InvalidParameter, /*!< Invalid parameter */ - kStatus_USB_InvalidRequest, /*!< Invalid request */ - kStatus_USB_ControllerNotFound, /*!< Controller cannot be found */ - kStatus_USB_InvalidControllerInterface, /*!< Invalid controller interface */ - - kStatus_USB_NotSupported, /*!< Configuration is not supported */ - kStatus_USB_Retry, /*!< Enumeration get configuration retry */ - kStatus_USB_TransferStall, /*!< Transfer stalled */ - kStatus_USB_TransferFailed, /*!< Transfer failed */ - kStatus_USB_AllocFail, /*!< Allocation failed */ - kStatus_USB_LackSwapBuffer, /*!< Insufficient swap buffer for KHCI */ - kStatus_USB_TransferCancel, /*!< The transfer cancelled */ - kStatus_USB_BandwidthFail, /*!< Allocate bandwidth failed */ - kStatus_USB_MSDStatusFail, /*!< For MSD, the CSW status means fail */ - kStatus_USB_EHCIAttached, - kStatus_USB_EHCIDetached, -} usb_status_t; - -/*! @brief USB host handle type define */ -typedef void *usb_host_handle; - -/*! @brief USB device handle type define. For device stack it is the whole device handle; for host stack it is the - * attached device instance handle*/ -typedef void *usb_device_handle; - -/*! @brief USB OTG handle type define */ -typedef void *usb_otg_handle; - -/*! @brief USB controller ID */ -typedef enum _usb_controller_index -{ - kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */ - kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved - to be used in the future. */ - kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */ - kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U, Currently, there are no platforms which have two EHCI IPs, this is reserved - to be used in the future. */ - - kUSB_ControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */ - kUSB_ControllerLpcIp3511Fs1 = - 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511 IPs, this is reserved - to be used in the future. */ - - kUSB_ControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */ - kUSB_ControllerLpcIp3511Hs1 = - 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511 IPs, this is reserved - to be used in the future. */ - - kUSB_ControllerOhci0 = 8U, /*!< OHCI 0U */ - kUSB_ControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved - to be used in the future. */ - - kUSB_ControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */ - kUSB_ControllerIp3516Hs1 = - 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs, this is reserved - to be used in the future. */ -} usb_controller_index_t; - -/** -* @brief USB stack version fields -*/ -typedef struct _usb_version -{ - uint8_t major; /*!< Major */ - uint8_t minor; /*!< Minor */ - uint8_t bugfix; /*!< Bug fix */ -} usb_version_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -/*! @} */ - -#endif /* __USB_H__ */ diff --git a/bsp/imxrt1052-evk/drivers/usb/include/usb_device_config.h b/bsp/imxrt1052-evk/drivers/usb/include/usb_device_config.h deleted file mode 100644 index 551d92edc7..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/include/usb_device_config.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016 - 2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _USB_DEVICE_CONFIG_H_ -#define _USB_DEVICE_CONFIG_H_ - -/******************************************************************************* -* Definitions -******************************************************************************/ -/*! - * @addtogroup usb_device_configuration - * @{ - */ - -/*! - * @name Hardware instance define - * @{ - */ - -/*! @brief KHCI instance count */ -#define USB_DEVICE_CONFIG_KHCI (0U) - -/*! @brief EHCI instance count */ -#define USB_DEVICE_CONFIG_EHCI (2U) - -/*! @brief LPC USB IP3511 FS instance count */ -#define USB_DEVICE_CONFIG_LPCIP3511FS (0U) - -/*! @brief LPC USB IP3511 HS instance count */ -#define USB_DEVICE_CONFIG_LPCIP3511HS (0U) - -/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/ -#define USB_DEVICE_CONFIG_NUM \ - (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI + USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS) - -/* @} */ - -/*! - * @name class instance define - * @{ - */ - -/*! @brief HID instance count */ -#define USB_DEVICE_CONFIG_HID (0U) - -/*! @brief CDC ACM instance count */ -#define USB_DEVICE_CONFIG_CDC_ACM (1U) - -/*! @brief MSC instance count */ -#define USB_DEVICE_CONFIG_MSC (0U) - -/*! @brief Audio instance count */ -#define USB_DEVICE_CONFIG_AUDIO (0U) - -/*! @brief PHDC instance count */ -#define USB_DEVICE_CONFIG_PHDC (0U) - -/*! @brief Video instance count */ -#define USB_DEVICE_CONFIG_VIDEO (0U) - -/*! @brief CCID instance count */ -#define USB_DEVICE_CONFIG_CCID (0U) - -/*! @brief Printer instance count */ -#define USB_DEVICE_CONFIG_PRINTER (0U) - -/*! @brief DFU instance count */ -#define USB_DEVICE_CONFIG_DFU (0U) - -/* @} */ - -/*! @brief Whether device is self power. 1U supported, 0U not supported */ -#define USB_DEVICE_CONFIG_SELF_POWER (1U) - -/*! @brief How many endpoints are supported in the stack. */ -#define USB_DEVICE_CONFIG_ENDPOINTS (4U) - -/*! @brief Whether the device task is enabled. */ -#define USB_DEVICE_CONFIG_USE_TASK (0U) - -/*! @brief How many the notification message are supported when the device task is enabled. */ -#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U) - -/*! @brief Whether test mode enabled. */ -#define USB_DEVICE_CONFIG_USB20_TEST_MODE (0U) - -/*! @brief Whether device CV test is enabled. */ -#define USB_DEVICE_CONFIG_CV_TEST (0U) - -/*! @brief Whether device compliance test is enabled. If the macro is enabled, - the test mode and CV test macroes will be set.*/ -#define USB_DEVICE_CONFIG_COMPLIANCE_TEST (0U) - -#if ((defined(USB_DEVICE_CONFIG_COMPLIANCE_TEST)) && (USB_DEVICE_CONFIG_COMPLIANCE_TEST > 0U)) - -/*! @brief Undefine the marco USB_DEVICE_CONFIG_USB20_TEST_MODE. */ -#undef USB_DEVICE_CONFIG_USB20_TEST_MODE -/*! @brief Undefine the marco USB_DEVICE_CONFIG_CV_TEST. */ -#undef USB_DEVICE_CONFIG_CV_TEST - -/*! @brief enable the test mode. */ -#define USB_DEVICE_CONFIG_USB20_TEST_MODE (1U) - -/*! @brief enable the CV test */ -#define USB_DEVICE_CONFIG_CV_TEST (1U) - -#endif - -#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) - -/*! @brief The MAX buffer length for the KHCI DMA workaround.*/ -#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U) -#endif - -#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) -/*! @brief How many the DTD are supported. */ -#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U) - -/*! @brief Whether the EHCI ID pin detect feature enabled. */ -#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U) -#endif - -/*! @brief Whether the keep alive feature enabled. */ -#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U) - -/*! @brief Whether the transfer buffer is cache-enabled or not. */ -#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (1U) - -/*! @brief Whether the low power mode is enabled or not. */ -#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U) - -#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) -/*! @brief Whether device remote wakeup supported. 1U supported, 0U not supported */ -#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) - -/*! @brief Whether LPM is supported. 1U supported, 0U not supported */ -#define USB_DEVICE_CONFIG_LPM_L1 (0U) -#else -/*! @brief The device remote wakeup is unsupported. */ -#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) -#endif - -/*! @brief Whether the device detached feature is enabled or not. */ -#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U) - -/*! @brief Whether handle the USB bus error. */ -#define USB_DEVICE_CONFIG_ERROR_HANDLING (0U) - -/* @} */ -/*! @brief rt-thread port alloc */ -#include -#define USB_OSA_SR_ALLOC(...) -/*! @brief rt-thread port enter critical */ -#define USB_OSA_ENTER_CRITICAL rt_enter_critical -/*! @brief rt-thread port exit critical */ -#define USB_OSA_EXIT_CRITICAL rt_exit_critical - -#endif /* _USB_DEVICE_CONFIG_H_ */ diff --git a/bsp/imxrt1052-evk/drivers/usb/include/usb_ehci.h b/bsp/imxrt1052-evk/drivers/usb/include/usb_ehci.h deleted file mode 100644 index edc3496643..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/include/usb_ehci.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __USB_EHCI_H__ -#define __USB_EHCI_H__ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Device QH */ -#define USB_DEVICE_EHCI_QH_POINTER_MASK (0xFFFFFFC0U) -#define USB_DEVICE_EHCI_QH_MULT_MASK (0xC0000000U) -#define USB_DEVICE_EHCI_QH_ZLT_MASK (0x20000000U) -#define USB_DEVICE_EHCI_QH_MAX_PACKET_SIZE_MASK (0x07FF0000U) -#define USB_DEVICE_EHCI_QH_MAX_PACKET_SIZE (0x00000800U) -#define USB_DEVICE_EHCI_QH_IOS_MASK (0x00008000U) - -/* Device DTD */ -#define USB_DEVICE_ECHI_DTD_POINTER_MASK (0xFFFFFFE0U) -#define USB_DEVICE_ECHI_DTD_TERMINATE_MASK (0x00000001U) -#define USB_DEVICE_ECHI_DTD_PAGE_MASK (0xFFFFF000U) -#define USB_DEVICE_ECHI_DTD_PAGE_OFFSET_MASK (0x00000FFFU) -#define USB_DEVICE_ECHI_DTD_PAGE_BLOCK (0x00001000U) -#define USB_DEVICE_ECHI_DTD_TOTAL_BYTES_MASK (0x7FFF0000U) -#define USB_DEVICE_ECHI_DTD_TOTAL_BYTES (0x00004000U) -#define USB_DEVICE_ECHI_DTD_IOC_MASK (0x00008000U) -#define USB_DEVICE_ECHI_DTD_MULTIO_MASK (0x00000C00U) -#define USB_DEVICE_ECHI_DTD_STATUS_MASK (0x000000FFU) -#define USB_DEVICE_EHCI_DTD_STATUS_ERROR_MASK (0x00000068U) -#define USB_DEVICE_ECHI_DTD_STATUS_ACTIVE (0x00000080U) -#define USB_DEVICE_ECHI_DTD_STATUS_HALTED (0x00000040U) -#define USB_DEVICE_ECHI_DTD_STATUS_DATA_BUFFER_ERROR (0x00000020U) -#define USB_DEVICE_ECHI_DTD_STATUS_TRANSACTION_ERROR (0x00000008U) - -typedef struct _usb_device_ehci_qh_struct -{ - union - { - volatile uint32_t capabilttiesCharacteristics; - struct - { - volatile uint32_t reserved1 : 15; - volatile uint32_t ios : 1; - volatile uint32_t maxPacketSize : 11; - volatile uint32_t reserved2 : 2; - volatile uint32_t zlt : 1; - volatile uint32_t mult : 2; - } capabilttiesCharacteristicsBitmap; - } capabilttiesCharacteristicsUnion; - volatile uint32_t currentDtdPointer; - volatile uint32_t nextDtdPointer; - union - { - volatile uint32_t dtdToken; - struct - { - volatile uint32_t status : 8; - volatile uint32_t reserved1 : 2; - volatile uint32_t multiplierOverride : 2; - volatile uint32_t reserved2 : 3; - volatile uint32_t ioc : 1; - volatile uint32_t totalBytes : 15; - volatile uint32_t reserved3 : 1; - } dtdTokenBitmap; - } dtdTokenUnion; - volatile uint32_t bufferPointerPage[5]; - volatile uint32_t reserved1; - uint32_t setupBuffer[2]; - uint32_t setupBufferBack[2]; - union - { - uint32_t endpointStatus; - struct - { - uint32_t isOpened : 1; - uint32_t : 31; - } endpointStatusBitmap; - } endpointStatusUnion; - uint32_t reserved2; -} usb_device_ehci_qh_struct_t; - -typedef struct _usb_device_ehci_dtd_struct -{ - volatile uint32_t nextDtdPointer; - union - { - volatile uint32_t dtdToken; - struct - { - volatile uint32_t status : 8; - volatile uint32_t reserved1 : 2; - volatile uint32_t multiplierOverride : 2; - volatile uint32_t reserved2 : 3; - volatile uint32_t ioc : 1; - volatile uint32_t totalBytes : 15; - volatile uint32_t reserved3 : 1; - } dtdTokenBitmap; - } dtdTokenUnion; - volatile uint32_t bufferPointerPage[5]; - union - { - volatile uint32_t reserved; - struct - { - uint32_t originalBufferOffest : 12; - uint32_t originalBufferLength : 19; - uint32_t dtdInvalid : 1; - } originalBufferInfo; - } reservedUnion; -} usb_device_ehci_dtd_struct_t; - -#endif /* __USB_EHCI_H__ */ diff --git a/bsp/imxrt1052-evk/drivers/usb/include/usb_misc.h b/bsp/imxrt1052-evk/drivers/usb/include/usb_misc.h deleted file mode 100644 index 4e65cfa94b..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/include/usb_misc.h +++ /dev/null @@ -1,452 +0,0 @@ -/* - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __USB_MISC_H__ -#define __USB_MISC_H__ - -#ifndef ENDIANNESS - -#error ENDIANNESS should be defined, and then rebulid the project. - -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Define USB printf */ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -extern int DbgConsole_Printf(const char *fmt_s, ...); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -#if defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE < 1) -#define usb_echo printf -#else -#define usb_echo DbgConsole_Printf -#endif - -#if defined(__ICCARM__) - -#ifndef STRUCT_PACKED -#define STRUCT_PACKED __packed -#endif - -#ifndef STRUCT_UNPACKED -#define STRUCT_UNPACKED -#endif - -#elif defined(__GNUC__) - -#ifndef STRUCT_PACKED -#define STRUCT_PACKED -#endif - -#ifndef STRUCT_UNPACKED -#define STRUCT_UNPACKED __attribute__((__packed__)) -#endif - -#elif defined(__CC_ARM) - -#ifndef STRUCT_PACKED -#define STRUCT_PACKED _Pragma("pack(1U)") -#endif - -#ifndef STRUCT_UNPACKED -#define STRUCT_UNPACKED _Pragma("pack()") -#endif - -#endif - -#define USB_SHORT_GET_LOW(x) (((uint16_t)x) & 0xFFU) -#define USB_SHORT_GET_HIGH(x) ((uint8_t)(((uint16_t)x) >> 8U) & 0xFFU) - -#define USB_LONG_GET_BYTE0(x) ((uint8_t)(((uint32_t)(x))) & 0xFFU) -#define USB_LONG_GET_BYTE1(x) ((uint8_t)(((uint32_t)(x)) >> 8U) & 0xFFU) -#define USB_LONG_GET_BYTE2(x) ((uint8_t)(((uint32_t)(x)) >> 16U) & 0xFFU) -#define USB_LONG_GET_BYTE3(x) ((uint8_t)(((uint32_t)(x)) >> 24U) & 0xFFU) - -#define USB_MEM4_ALIGN_MASK (0x03U) - -/* accessory macro */ -#define USB_MEM4_ALIGN(n) ((n + 3U) & (0xFFFFFFFCu)) -#define USB_MEM32_ALIGN(n) ((n + 31U) & (0xFFFFFFE0u)) -#define USB_MEM64_ALIGN(n) ((n + 63U) & (0xFFFFFFC0u)) - -/* big/little endian */ -#define SWAP2BYTE_CONST(n) ((((n)&0x00FFU) << 8U) | (((n)&0xFF00U) >> 8U)) -#define SWAP4BYTE_CONST(n) \ - ((((n)&0x000000FFU) << 24U) | (((n)&0x0000FF00U) << 8U) | (((n)&0x00FF0000U) >> 8U) | (((n)&0xFF000000U) >> 24U)) - -#define USB_ASSIGN_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \ - { \ - *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \ - *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \ - *((uint8_t *)&(n) + 2) = *((uint8_t *)&(m) + 2); \ - *((uint8_t *)&(n) + 3) = *((uint8_t *)&(m) + 3); \ - } - -#define USB_ASSIGN_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \ - { \ - *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \ - *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \ - } - -#define USB_ASSIGN_MACRO_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \ - { \ - *((uint8_t *)&(n)) = (uint8_t)m; \ - *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \ - *((uint8_t *)&(n) + 2) = (uint8_t)(m >> 16); \ - *((uint8_t *)&(n) + 3) = (uint8_t)(m >> 24); \ - } - -#define USB_ASSIGN_MACRO_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \ - { \ - *((uint8_t *)&(n)) = (uint8_t)m; \ - *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \ - } - -#if (ENDIANNESS == USB_BIG_ENDIAN) - -#define USB_SHORT_TO_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) -#define USB_LONG_TO_LITTLE_ENDIAN(n) SWAP4BYTE_CONST(n) -#define USB_SHORT_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) -#define USB_LONG_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) - -#define USB_SHORT_TO_BIG_ENDIAN(n) (n) -#define USB_LONG_TO_BIG_ENDIAN(n) (n) -#define USB_SHORT_FROM_BIG_ENDIAN(n) (n) -#define USB_LONG_FROM_BIG_ENDIAN(n) (n) - -#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ - { \ - m[3] = ((n >> 24U) & 0xFFU); \ - m[2] = ((n >> 16U) & 0xFFU); \ - m[1] = ((n >> 8U) & 0xFFU); \ - m[0] = (n & 0xFFU); \ - } - -#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \ - ((uint32_t)((((uint8_t)n[3]) << 24U) | (((uint8_t)n[2]) << 16U) | (((uint8_t)n[1]) << 8U) | \ - (((uint8_t)n[0]) << 0U))) - -#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \ - { \ - m[0] = ((n >> 24U) & 0xFFU); \ - m[1] = ((n >> 16U) & 0xFFU); \ - m[2] = ((n >> 8U) & 0xFFU); \ - m[3] = (n & 0xFFU); \ - } - -#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \ - ((uint32_t)((((uint8_t)n[0]) << 24U) | (((uint8_t)n[1]) << 16U) | (((uint8_t)n[2]) << 8U) | \ - (((uint8_t)n[3]) << 0U))) - -#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ - { \ - m[1] = ((n >> 8U) & 0xFFU); \ - m[0] = (n & 0xFFU); \ - } - -#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[1]) << 8U) | (((uint8_t)n[0]) << 0U))) - -#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \ - { \ - m[0] = ((n >> 8U) & 0xFFU); \ - m[1] = (n & 0xFFU); \ - } - -#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[0]) << 8U) | (((uint8_t)n[1]) << 0U))) - -#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \ - { \ - *((uint8_t *)&(m) + 3) = ((n >> 24U) & 0xFFU); \ - *((uint8_t *)&(m) + 2) = ((n >> 16U) & 0xFFU); \ - *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ - *((uint8_t *)&(m) + 0) = (n & 0xFFU); \ - } - -#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \ - ((uint32_t)(((*((uint8_t *)&(n) + 3)) << 24U) | ((*((uint8_t *)&(n) + 2)) << 16U) | \ - ((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))) << 0U))) - -#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \ - { \ - *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ - *((uint8_t *)&(m)) = ((n)&0xFFU); \ - } - -#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) ((uint32_t)(((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n)))))) - -#else - -#define USB_SHORT_TO_LITTLE_ENDIAN(n) (n) -#define USB_LONG_TO_LITTLE_ENDIAN(n) (n) -#define USB_SHORT_FROM_LITTLE_ENDIAN(n) (n) -#define USB_LONG_FROM_LITTLE_ENDIAN(n) (n) - -#define USB_SHORT_TO_BIG_ENDIAN(n) SWAP2BYTE_CONST(n) -#define USB_LONG_TO_BIG_ENDIAN(n) SWAP4BYTE_CONST(n) -#define USB_SHORT_FROM_BIG_ENDIAN(n) SWAP2BYTE_CONST(n) -#define USB_LONG_FROM_BIG_ENDIAN(n) SWAP4BYTE_CONST(n) - -#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ - { \ - m[3] = ((n >> 24U) & 0xFFU); \ - m[2] = ((n >> 16U) & 0xFFU); \ - m[1] = ((n >> 8U) & 0xFFU); \ - m[0] = (n & 0xFFU); \ - } - -#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \ - ((uint32_t)((((uint8_t)n[3]) << 24U) | (((uint8_t)n[2]) << 16U) | (((uint8_t)n[1]) << 8U) | \ - (((uint8_t)n[0]) << 0U))) - -#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \ - { \ - m[0] = ((n >> 24U) & 0xFFU); \ - m[1] = ((n >> 16U) & 0xFFU); \ - m[2] = ((n >> 8U) & 0xFFU); \ - m[3] = (n & 0xFFU); \ - } - -#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \ - ((uint32_t)((((uint8_t)n[0]) << 24U) | (((uint8_t)n[1]) << 16U) | (((uint8_t)n[2]) << 8U) | \ - (((uint8_t)n[3]) << 0U))) - -#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ - { \ - m[1] = ((n >> 8U) & 0xFFU); \ - m[0] = (n & 0xFFU); \ - } - -#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[1]) << 8U) | (((uint8_t)n[0]) << 0U))) - -#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \ - { \ - m[0] = ((n >> 8U) & 0xFFU); \ - m[1] = (n & 0xFFU); \ - } - -#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[0]) << 8U) | (((uint8_t)n[1]) << 0U))) - -#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \ - { \ - *((uint8_t *)&(m) + 3) = ((n >> 24U) & 0xFFU); \ - *((uint8_t *)&(m) + 2) = ((n >> 16U) & 0xFFU); \ - *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ - *((uint8_t *)&(m) + 0) = (n & 0xFFU); \ - } - -#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \ - ((uint32_t)(((*((uint8_t *)&(n) + 3)) << 24U) | ((*((uint8_t *)&(n) + 2)) << 16U) | \ - ((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))) << 0U))) - -#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \ - { \ - *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ - *((uint8_t *)&(m)) = ((n)&0xFFU); \ - } - -#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) ((uint32_t)(((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n)))))) - -#endif - -/* - * The following MACROs (USB_GLOBAL, USB_BDT, USB_RAM_ADDRESS_ALIGNMENT, etc) are only used for USB device stack. - * The USB device global variables are put into the section m_usb_global and m_usb_bdt or the section - * .bss.m_usb_global and .bss.m_usb_bdt by using the MACRO USB_GLOBAL and USB_BDT. In this way, the USB device - * global variables can be linked into USB dedicated RAM by USB_STACK_USE_DEDICATED_RAM. - * The MACRO USB_STACK_USE_DEDICATED_RAM is used to decide the USB stack uses dedicated RAM or not. The value of - * the marco can be set as 0, USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL, or USB_STACK_DEDICATED_RAM_TYPE_BDT. - * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL means USB device global variables, including USB_BDT and - * USB_GLOBAL, are put into the USB dedicated RAM. This feature can only be enabled when the USB dedicated RAM - * is not less than 2K Bytes. - * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT means USB device global variables, only including USB_BDT, are put - * into the USB dedicated RAM, the USB_GLOBAL will be put into .bss section. This feature is used for some SOCs, - * the USB dedicated RAM size is not more than 512 Bytes. - */ -#define USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL 1 -#define USB_STACK_DEDICATED_RAM_TYPE_BDT 2 - -#if defined(__ICCARM__) - -#define USB_WEAK_VAR __attribute__((weak)) -#define USB_WEAK_FUN __attribute__((weak)) -/* disable misra 19.13 */ -_Pragma("diag_suppress=Pm120") -#define USB_ALIGN_PRAGMA(x) _Pragma(#x) - _Pragma("diag_default=Pm120") - -#define USB_RAM_ADDRESS_ALIGNMENT(n) USB_ALIGN_PRAGMA(data_alignment = n) - _Pragma("diag_suppress=Pm120") -#define USB_LINK_SECTION_PART(str) _Pragma(#str) -#define USB_LINK_SECTION_SUB(sec) USB_LINK_SECTION_PART(location = #sec) -#define USB_LINK_USB_GLOBAL _Pragma("location = \"m_usb_global\"") -#define USB_LINK_USB_BDT _Pragma("location = \"m_usb_bdt\"") -#define USB_LINK_USB_GLOBAL_BSS _Pragma("location = \".bss.m_usb_global\"") -#define USB_LINK_USB_BDT_BSS _Pragma("location = \".bss.m_usb_bdt\"") - _Pragma("diag_default=Pm120") -#define USB_LINK_DMA_NONINIT_DATA _Pragma("location = \"m_usb_dma_noninit_data\"") -#define USB_LINK_NONCACHE_NONINIT_DATA _Pragma("location = \"NonCacheable\"") -#elif defined(__CC_ARM) - -#define USB_WEAK_VAR __attribute__((weak)) -#define USB_WEAK_FUN __weak -#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) -#define USB_LINK_SECTION_SUB(sec) __attribute__((section(#sec))) -#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global"))) __attribute__((zero_init)) -#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt"))) __attribute__((zero_init)) -#define USB_LINK_USB_GLOBAL_BSS __attribute__((section(".bss.m_usb_global"))) __attribute__((zero_init)) -#define USB_LINK_USB_BDT_BSS __attribute__((section(".bss.m_usb_bdt"))) __attribute__((zero_init)) -#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data"))) __attribute__((zero_init)) -#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable"))) __attribute__((zero_init)) - -#elif defined(__GNUC__) - -#define USB_WEAK_VAR __attribute__((weak)) -#define USB_WEAK_FUN __attribute__((weak)) -#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) -#define USB_LINK_SECTION_SUB(sec) __attribute__((section(#sec))) -#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global, \"aw\", %nobits @"))) -#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt, \"aw\", %nobits @"))) -#define USB_LINK_USB_GLOBAL_BSS __attribute__((section(".bss.m_usb_global, \"aw\", %nobits @"))) -#define USB_LINK_USB_BDT_BSS __attribute__((section(".bss.m_usb_bdt, \"aw\", %nobits @"))) -#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data, \"aw\", %nobits @"))) -#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable, \"aw\", %nobits @"))) - -#else -#error The tool-chain is not supported. -#endif - -#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ - (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) - -#if ((defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) && (defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) -#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#elif(defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) -#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, 0) -#elif(defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)) -#define USB_CACHE_LINESIZE MAX(0, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#else -#define USB_CACHE_LINESIZE 4 -#endif - -#else -#define USB_CACHE_LINESIZE 4 -#endif - -#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ - ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) -#define USB_DATA_ALIGN 64 -#else -#define USB_DATA_ALIGN 4 -#endif - -#define USB_DATA_ALIGN_SIZE MAX(USB_CACHE_LINESIZE, USB_DATA_ALIGN) - -#define USB_DATA_ALIGN_SIZE_MULTIPLE(n) ((n + USB_DATA_ALIGN_SIZE - 1) & (~(USB_DATA_ALIGN_SIZE - 1))) - -#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL) - -#define USB_GLOBAL USB_LINK_USB_GLOBAL -#define USB_BDT USB_LINK_USB_BDT - -#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ - (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) -#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA -#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data) -#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA -#else -#define USB_DMA_DATA_NONINIT_SUB -#define USB_DMA_DATA_INIT_SUB -#define USB_CONTROLLER_DATA USB_LINK_USB_GLOBAL -#endif - -#elif defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT) - -#define USB_BDT USB_LINK_USB_BDT - -#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ - (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) -#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA -#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA -#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data) -#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA -#else -#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS -#define USB_DMA_DATA_NONINIT_SUB -#define USB_DMA_DATA_INIT_SUB -#define USB_CONTROLLER_DATA -#endif - -#else - -#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ - (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) - -#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA -#define USB_BDT USB_LINK_NONCACHE_NONINIT_DATA -#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA -#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data) -#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA - -#else -#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS -#define USB_BDT USB_LINK_USB_BDT_BSS -#define USB_DMA_DATA_NONINIT_SUB -#define USB_DMA_DATA_INIT_SUB -#define USB_CONTROLLER_DATA -#endif - -#endif - -#define USB_DMA_NONINIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_NONINIT_SUB -#define USB_DMA_INIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_INIT_SUB - -#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ - (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) -#define USB_DMA_DATA_NONCACHEABLE USB_LINK_NONCACHE_NONINIT_DATA - -#else -#define USB_DMA_DATA_NONCACHEABLE -#endif - -#define USB_GLOBAL_DEDICATED_RAM USB_LINK_USB_GLOBAL - -/* #define USB_RAM_ADDRESS_NONCACHEREG_ALIGNMENT(n, var) AT_NONCACHEABLE_SECTION_ALIGN(var, n) */ -/* #define USB_RAM_ADDRESS_NONCACHEREG(var) AT_NONCACHEABLE_SECTION(var) */ - -#endif /* __USB_MISC_H__ */ diff --git a/bsp/imxrt1052-evk/drivers/usb/include/usb_spec.h b/bsp/imxrt1052-evk/drivers/usb/include/usb_spec.h deleted file mode 100644 index d77b7d3598..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/include/usb_spec.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __USB_SPEC_H__ -#define __USB_SPEC_H__ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* USB speed (the value cannot be changed because EHCI QH use the value directly)*/ -#define USB_SPEED_FULL (0x00U) -#define USB_SPEED_LOW (0x01U) -#define USB_SPEED_HIGH (0x02U) - -/* Set up packet structure */ -typedef struct _usb_setup_struct -{ - uint8_t bmRequestType; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -} usb_setup_struct_t; - -/* USB standard descriptor endpoint type */ -#define USB_ENDPOINT_CONTROL (0x00U) -#define USB_ENDPOINT_ISOCHRONOUS (0x01U) -#define USB_ENDPOINT_BULK (0x02U) -#define USB_ENDPOINT_INTERRUPT (0x03U) - -/* USB standard descriptor transfer direction (cannot change the value because iTD use the value directly) */ -#define USB_OUT (0U) -#define USB_IN (1U) - -/* USB standard descriptor length */ -#define USB_DESCRIPTOR_LENGTH_DEVICE (0x12U) -#define USB_DESCRIPTOR_LENGTH_CONFIGURE (0x09U) -#define USB_DESCRIPTOR_LENGTH_INTERFACE (0x09U) -#define USB_DESCRIPTOR_LENGTH_ENDPOINT (0x07U) -#define USB_DESCRIPTOR_LENGTH_DEVICE_QUALITIER (0x0AU) -#define USB_DESCRIPTOR_LENGTH_OTG_DESCRIPTOR (5U) -#define USB_DESCRIPTOR_LENGTH_BOS_DESCRIPTOR (5U) - -/* USB Device Capability Type Codes */ -#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_WIRELESS (0x01U) -#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_USB20_EXTENSION (0x02U) -#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_SUPERSPEED (0x03U) - -/* USB standard descriptor type */ -#define USB_DESCRIPTOR_TYPE_DEVICE (0x01U) -#define USB_DESCRIPTOR_TYPE_CONFIGURE (0x02U) -#define USB_DESCRIPTOR_TYPE_STRING (0x03U) -#define USB_DESCRIPTOR_TYPE_INTERFACE (0x04U) -#define USB_DESCRIPTOR_TYPE_ENDPOINT (0x05U) -#define USB_DESCRIPTOR_TYPE_DEVICE_QUALITIER (0x06U) -#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION (0x07U) -#define USB_DESCRIPTOR_TYPE_INTERFAACE_POWER (0x08U) -#define USB_DESCRIPTOR_TYPE_OTG (0x09U) -#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION (0x0BU) -#define USB_DESCRIPTOR_TYPE_BOS (0x0F) -#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY (0x10) - -#define USB_DESCRIPTOR_TYPE_HID (0x21U) -#define USB_DESCRIPTOR_TYPE_HID_REPORT (0x22U) -#define USB_DESCRIPTOR_TYPE_HID_PHYSICAL (0x23U) - -/* USB standard request type */ -#define USB_REQUEST_TYPE_DIR_MASK (0x80U) -#define USB_REQUEST_TYPE_DIR_SHIFT (7U) -#define USB_REQUEST_TYPE_DIR_OUT (0x00U) -#define USB_REQUEST_TYPE_DIR_IN (0x80U) - -#define USB_REQUEST_TYPE_TYPE_MASK (0x60U) -#define USB_REQUEST_TYPE_TYPE_SHIFT (5U) -#define USB_REQUEST_TYPE_TYPE_STANDARD (0U) -#define USB_REQUEST_TYPE_TYPE_CLASS (0x20U) -#define USB_REQUEST_TYPE_TYPE_VENDOR (0x40U) - -#define USB_REQUEST_TYPE_RECIPIENT_MASK (0x1FU) -#define USB_REQUEST_TYPE_RECIPIENT_SHIFT (0U) -#define USB_REQUEST_TYPE_RECIPIENT_DEVICE (0x00U) -#define USB_REQUEST_TYPE_RECIPIENT_INTERFACE (0x01U) -#define USB_REQUEST_TYPE_RECIPIENT_ENDPOINT (0x02U) -#define USB_REQUEST_TYPE_RECIPIENT_OTHER (0x03U) - -/* USB standard request */ -#define USB_REQUEST_STANDARD_GET_STATUS (0x00U) -#define USB_REQUEST_STANDARD_CLEAR_FEATURE (0x01U) -#define USB_REQUEST_STANDARD_SET_FEATURE (0x03U) -#define USB_REQUEST_STANDARD_SET_ADDRESS (0x05U) -#define USB_REQUEST_STANDARD_GET_DESCRIPTOR (0x06U) -#define USB_REQUEST_STANDARD_SET_DESCRIPTOR (0x07U) -#define USB_REQUEST_STANDARD_GET_CONFIGURATION (0x08U) -#define USB_REQUEST_STANDARD_SET_CONFIGURATION (0x09U) -#define USB_REQUEST_STANDARD_GET_INTERFACE (0x0AU) -#define USB_REQUEST_STANDARD_SET_INTERFACE (0x0BU) -#define USB_REQUEST_STANDARD_SYNCH_FRAME (0x0CU) - -/* USB standard request GET Status */ -#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT (0U) -#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT (1U) - -#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_MASK (0x01U) -#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_SHIFT (0U) - -#define USB_REQUEST_STANDARD_GET_STATUS_OTG_STATUS_SELECTOR (0xF000U) - -/* USB standard request CLEAR/SET feature */ -#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT (0U) -#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP (1U) -#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE (2U) -#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_B_HNP_ENABLE (3U) -#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_HNP_SUPPORT (4U) -#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_ALT_HNP_SUPPORT (5U) - -/* USB standard descriptor configure bmAttributes */ -#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK (0x80U) -#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_SHIFT (7U) - -#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_MASK (0x40U) -#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT (6U) - -#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_MASK (0x20U) -#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT (5U) - -/* USB standard descriptor endpoint bmAttributes */ -#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK (0x80U) -#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT (7U) -#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_OUT (0U) -#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN (0x80U) - -#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK (0x0FU) -#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_SHFIT (0U) - -#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK (0x03U) -#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_NUMBER_SHFIT (0U) - -#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_MASK (0x0CU) -#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SHFIT (2U) -#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_NO_SYNC (0x00U) -#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ASYNC (0x04U) -#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ADAPTIVE (0x08U) -#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SYNC (0x0CU) - -#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_MASK (0x30U) -#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_SHFIT (4U) -#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_DATA_ENDPOINT (0x00U) -#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_FEEDBACK_ENDPOINT (0x10U) -#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_IMPLICIT_FEEDBACK_DATA_ENDPOINT (0x20U) - -#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK (0x07FFu) -#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK (0x1800u) -#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT (11U) - -/* USB standard descriptor otg bmAttributes */ -#define USB_DESCRIPTOR_OTG_ATTRIBUTES_SRP_MASK (0x01u) -#define USB_DESCRIPTOR_OTG_ATTRIBUTES_HNP_MASK (0x02u) -#define USB_DESCRIPTOR_OTG_ATTRIBUTES_ADP_MASK (0x04u) - -/* USB standard descriptor device capability usb20 extension bmAttributes */ -#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_MASK (0x02U) -#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_SHIFT (1U) -#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_MASK (0x04U) -#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_SHIFT (2U) - - -/* Language structure */ -typedef struct _usb_language -{ - uint8_t **string; /* The Strings descriptor array */ - uint32_t *length; /* The strings descriptor length array */ - uint16_t languageId; /* The language id of current language */ -} usb_language_t; - -typedef struct _usb_language_list -{ - uint8_t *languageString; /* The String 0U pointer */ - uint32_t stringLength; /* The String 0U Length */ - usb_language_t *languageList; /* The language list */ - uint8_t count; /* The language count */ -} usb_language_list_t; - -typedef struct _usb_descriptor_common -{ - uint8_t bLength; /* Size of this descriptor in bytes */ - uint8_t bDescriptorType; /* DEVICE Descriptor Type */ - uint8_t bData[1]; /* Data */ -} usb_descriptor_common_t; - -typedef struct _usb_descriptor_device -{ - uint8_t bLength; /* Size of this descriptor in bytes */ - uint8_t bDescriptorType; /* DEVICE Descriptor Type */ - uint8_t bcdUSB[2]; /* UUSB Specification Release Number in Binary-Coded Decimal, e.g. 0x0200U */ - uint8_t bDeviceClass; /* Class code */ - uint8_t bDeviceSubClass; /* Sub-Class code */ - uint8_t bDeviceProtocol; /* Protocol code */ - uint8_t bMaxPacketSize0; /* Maximum packet size for endpoint zero */ - uint8_t idVendor[2]; /* Vendor ID (assigned by the USB-IF) */ - uint8_t idProduct[2]; /* Product ID (assigned by the manufacturer) */ - uint8_t bcdDevice[2]; /* Device release number in binary-coded decimal */ - uint8_t iManufacturer; /* Index of string descriptor describing manufacturer */ - uint8_t iProduct; /* Index of string descriptor describing product */ - uint8_t iSerialNumber; /* Index of string descriptor describing the device serial number */ - uint8_t bNumConfigurations; /* Number of possible configurations */ -} usb_descriptor_device_t; - -typedef struct _usb_descriptor_configuration -{ - uint8_t bLength; /* Descriptor size in bytes = 9U */ - uint8_t bDescriptorType; /* CONFIGURATION type = 2U or 7U */ - uint8_t wTotalLength[2]; /* Length of concatenated descriptors */ - uint8_t bNumInterfaces; /* Number of interfaces, this configuration. */ - uint8_t bConfigurationValue; /* Value to set this configuration. */ - uint8_t iConfiguration; /* Index to configuration string */ - uint8_t bmAttributes; /* Configuration characteristics */ - uint8_t bMaxPower; /* Maximum power from bus, 2 mA units */ -} usb_descriptor_configuration_t; - -typedef struct _usb_descriptor_interface -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bInterfaceNumber; - uint8_t bAlternateSetting; - uint8_t bNumEndpoints; - uint8_t bInterfaceClass; - uint8_t bInterfaceSubClass; - uint8_t bInterfaceProtocol; - uint8_t iInterface; -} usb_descriptor_interface_t; - -typedef struct _usb_descriptor_endpoint -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - uint8_t wMaxPacketSize[2]; - uint8_t bInterval; -} usb_descriptor_endpoint_t; - -typedef struct _usb_descriptor_binary_device_object_store -{ - uint8_t bLength; /* Descriptor size in bytes = 5U */ - uint8_t bDescriptorType; /* BOS Descriptor type = 0FU*/ - uint8_t wTotalLength[2]; /*Length of this descriptor and all of its sub descriptors*/ - uint8_t bNumDeviceCaps; /*The number of separate device capability descriptors in the BOS*/ -} usb_descriptor_bos_t; - -typedef struct _usb_descriptor_usb20_extension -{ - uint8_t bLength; /* Descriptor size in bytes = 7U */ - uint8_t bDescriptorType; /* DEVICE CAPABILITY Descriptor type = 0x10U*/ - uint8_t bDevCapabilityType; /*Length of this descriptor and all of its sub descriptors*/ - uint8_t bmAttributes[4]; /*Bitmap encoding of supported device level features.*/ -} usb_descriptor_usb20_extension_t; - -typedef union _usb_descriptor_union -{ - usb_descriptor_common_t common; /* Common descriptor */ - usb_descriptor_device_t device; /* Device descriptor */ - usb_descriptor_configuration_t configuration; /* Configuration descriptor */ - usb_descriptor_interface_t interface; /* Interface descriptor */ - usb_descriptor_endpoint_t endpoint; /* Endpoint descriptor */ -} usb_descriptor_union_t; - -#endif /* __USB_SPEC_H__ */ diff --git a/bsp/imxrt1052-evk/drivers/usb/phy/usb_phy.c b/bsp/imxrt1052-evk/drivers/usb/phy/usb_phy.c deleted file mode 100644 index 85258c63af..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/phy/usb_phy.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 - 2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include "fsl_device_registers.h" - -#include - -void *USB_EhciPhyGetBase(uint8_t controllerId) -{ - void *usbPhyBase = NULL; -#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) - uint32_t instance; - uint32_t newinstance = 0; - uint32_t usbphy_base_temp[] = USBPHY_BASE_ADDRS; - uint32_t usbphy_base[] = USBPHY_BASE_ADDRS; - - if (controllerId < kUSB_ControllerEhci0) - { - return NULL; - } - - controllerId = controllerId - kUSB_ControllerEhci0; - - for (instance = 0; instance < (sizeof(usbphy_base_temp) / sizeof(usbphy_base_temp[0])); instance++) - { - if (usbphy_base_temp[instance]) - { - usbphy_base[newinstance++] = usbphy_base_temp[instance]; - } - } - if (controllerId > newinstance) - { - return NULL; - } - - usbPhyBase = (void *)usbphy_base[controllerId]; -#endif - return usbPhyBase; -} - -/*! - * @brief ehci phy initialization. - * - * This function initialize ehci phy IP. - * - * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. - * @param[in] freq the external input clock. - * for example: if the external input clock is 16M, the parameter freq should be 16000000. - * - * @retval kStatus_USB_Success cancel successfully. - * @retval kStatus_USB_Error the freq value is incorrect. - */ -uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) -{ -#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) - USBPHY_Type *usbPhyBase; - - usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); - if (NULL == usbPhyBase) - { - return kStatus_USB_Error; - } - -#if ((defined FSL_FEATURE_SOC_ANATOP_COUNT) && (FSL_FEATURE_SOC_ANATOP_COUNT > 0U)) - ANATOP->HW_ANADIG_REG_3P0.RW = - (ANATOP->HW_ANADIG_REG_3P0.RW & - (~(ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x1F) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_ILIMIT_MASK))) | - ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x17) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_LINREG_MASK; - ANATOP->HW_ANADIG_USB2_CHRG_DETECT.SET = - ANATOP_HW_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK | ANATOP_HW_ANADIG_USB2_CHRG_DETECT_EN_B_MASK; -#endif - -#if (defined USB_ANALOG) - USB_ANALOG->INSTANCE[controllerId - kUSB_ControllerEhci0].CHRG_DETECT_SET = USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(1) | USB_ANALOG_CHRG_DETECT_EN_B(1); -#endif - -#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) - - usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ -#endif - usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ - usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ - /* PWD register provides overall control of the PHY power state */ - usbPhyBase->PWD = 0U; - - /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ - usbPhyBase->TX = - ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | - (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | - USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); -#endif - - return kStatus_USB_Success; -} - -/*! - * @brief ehci phy initialization for suspend and resume. - * - * This function initialize ehci phy IP for suspend and resume. - * - * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. - * @param[in] freq the external input clock. - * for example: if the external input clock is 16M, the parameter freq should be 16000000. - * - * @retval kStatus_USB_Success cancel successfully. - * @retval kStatus_USB_Error the freq value is incorrect. - */ -uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) -{ -#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) - USBPHY_Type *usbPhyBase; - - usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); - if (NULL == usbPhyBase) - { - return kStatus_USB_Error; - } - -#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) - usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ -#endif - -#if ((defined USBPHY_CTRL_AUTORESUME_EN_MASK) && (USBPHY_CTRL_AUTORESUME_EN_MASK > 0U)) - usbPhyBase->CTRL |= USBPHY_CTRL_AUTORESUME_EN_MASK; -#else - usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK; -#endif - usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK; - usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ - usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ - /* PWD register provides overall control of the PHY power state */ - usbPhyBase->PWD = 0U; -#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) - /* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD - * pfd clock = 480MHz*18/N, where N=18~35 - * Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode - */ - usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */ - usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(1); /* div by 4 */ - - usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK; - usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK; - while (!(usbPhyBase->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK)) - { - } -#endif - /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ - usbPhyBase->TX = - ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | - (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | - USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); -#endif - - return kStatus_USB_Success; -} - -/*! - * @brief ehci phy de-initialization. - * - * This function de-initialize ehci phy IP. - * - * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. - */ -void USB_EhciPhyDeinit(uint8_t controllerId) -{ -#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) - USBPHY_Type *usbPhyBase; - - usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); - if (NULL == usbPhyBase) - { - return; - } -#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) - usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */ - usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */ -#endif - usbPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */ -#endif -} - -/*! - * @brief ehci phy disconnect detection enable or disable. - * - * This function enable/disable host ehci disconnect detection. - * - * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. - * @param[in] enable - * 1U - enable; - * 0U - disable; - */ -void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable) -{ -#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) - USBPHY_Type *usbPhyBase; - - usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); - if (NULL == usbPhyBase) - { - return; - } - - if (enable) - { - usbPhyBase->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; - } - else - { - usbPhyBase->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK); - } -#endif -} diff --git a/bsp/imxrt1052-evk/drivers/usb/phy/usb_phy.h b/bsp/imxrt1052-evk/drivers/usb/phy/usb_phy.h deleted file mode 100644 index 0409f9c8b9..0000000000 --- a/bsp/imxrt1052-evk/drivers/usb/phy/usb_phy.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016 - 2017 NXP - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __USB_PHY_H__ -#define __USB_PHY_H__ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -typedef struct _usb_phy_config_struct -{ - uint8_t D_CAL; /* Decode to trim the nominal 17.78mA current source */ - uint8_t TXCAL45DP; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DP output pin */ - uint8_t TXCAL45DM; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DM output pin */ -} usb_phy_config_struct_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -/*! - * @brief EHCI PHY get USB phy bass address. - * - * This function is used to get USB phy bass address. - * - * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. - * - * @retval USB phy bass address. - */ -extern void *USB_EhciPhyGetBase(uint8_t controllerId); - -/*! - * @brief EHCI PHY initialization. - * - * This function initializes the EHCI PHY IP. - * - * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. - * @param[in] freq The external input clock. - * - * @retval kStatus_USB_Success Cancel successfully. - * @retval kStatus_USB_Error The freq value is incorrect. - */ -extern uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig); - -/*! - * @brief ehci phy initialization for suspend and resume. - * - * This function initialize ehci phy IP for suspend and resume. - * - * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. - * @param[in] freq the external input clock. - * for example: if the external input clock is 16M, the parameter freq should be 16000000. - * - * @retval kStatus_USB_Success cancel successfully. - * @retval kStatus_USB_Error the freq value is incorrect. - */ -extern uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig); - -/*! - * @brief EHCI PHY deinitialization. - * - * This function deinitializes the EHCI PHY IP. - * - * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. - */ -extern void USB_EhciPhyDeinit(uint8_t controllerId); - -/*! - * @brief EHCI PHY disconnect detection enable or disable. - * - * This function enable/disable the host EHCI disconnect detection. - * - * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. - * @param[in] enable - * 1U - enable; - * 0U - disable; - */ -extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable); - -#if defined(__cplusplus) -} -#endif - -#endif /* __USB_PHY_H__ */ diff --git a/bsp/imxrt1052-evk/project.ewd b/bsp/imxrt1052-evk/project.ewd deleted file mode 100644 index 60c31a48ee..0000000000 --- a/bsp/imxrt1052-evk/project.ewd +++ /dev/null @@ -1,2908 +0,0 @@ - - - 3 - - Debug - - ARM - - 1 - - C-SPY - 2 - - 29 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 1 - 1 - 1 - - - - - - - - CADI_ID - 2 - - 0 - 1 - 1 - - - - - - - - - CMSISDAP_ID - 2 - - 4 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GDBSERVER_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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4099 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M7" - - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 2 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x60000 - - - 1 - 0x0 - 0x8000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x60000 - - - 0 - 0x0 - 0x20000 - - - - - - 1 - 3 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 - SKIP_SYSCLK_INIT, FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1, EVK_MCIMXRM, FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE, CPU_MIMXRT1052DVL6B, RT_USING_ARM_LIBC - - applications;.;drivers;Libraries;Libraries\drivers;Libraries\utilities;Libraries\CMSIS\Include;xip;..\..\include;..\..\libcpu\arm\cortex-m7;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\lwip-2.0.2\src\include\posix - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x10000000 - - .\Libraries\arm\MIMXRT1052xxxxx_flexspi_nor.scf - - - --keep=*(.boot_hdr.ivt)--keep=*(.boot_hdr.boot_data)--keep=*(.boot_hdr.dcd_data)--keep=*(.boot_hdr.conf) --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - - - - - - - Applications - - - device_test.c - 1 - applications\device_test.c - - - - - main.c - 1 - applications\main.c - - - - - mem_dump.c - 1 - applications\mem_dump.c - - - - - mem_test.c - 1 - applications\mem_test.c - - - - - Drivers - - - board.c - 1 - drivers\board.c - - - - - drv_uart.c - 1 - drivers\drv_uart.c - - - - - drv_cache.c - 1 - drivers\drv_cache.c - - - - - drv_sdram.c - 1 - drivers\drv_sdram.c - - - - - drv_pin.c - 1 - drivers\drv_pin.c - - - - - drv_rtc.c - 1 - drivers\drv_rtc.c - - - - - drv_spi_bus.c - 1 - drivers\drv_spi_bus.c - - - - - drv_i2c.c - 1 - drivers\drv_i2c.c - - - - - drv_lcd.c - 1 - drivers\drv_lcd.c - - - - - drv_sdio.c - 1 - drivers\drv_sdio.c - - - - - drv_eth.c - 1 - drivers\drv_eth.c - - - - - fsl_phy.c - 1 - drivers\fsl_phy.c - - - - - Libraries - - - fsl_adc.c - 1 - Libraries\drivers\fsl_adc.c - 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- - - - raw.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\raw.c - - - - - stats.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\stats.c - - - - - sys.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\sys.c - - - - - tcp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp.c - - - - - tcp_in.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c - - - - - tcp_out.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c - - - - - timeouts.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\timeouts.c - - - - - udp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\udp.c - - - - - ethernet.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c - - - - - ethernetif.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c - - - - - lowpan6.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c - - - - - autoip.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c - - - - - dhcp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c - - - - - etharp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c - - - - - icmp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c - - - - - igmp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c - - - - - ip4.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c - - - - - ip4_addr.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c - - - - - ip4_frag.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c - - - - - - - - - - - - - - - - - - - diff --git a/bsp/imxrt1052-evk/rtconfig.h b/bsp/imxrt1052-evk/rtconfig.h deleted file mode 100644 index d4298a93ca..0000000000 --- a/bsp/imxrt1052-evk/rtconfig.h +++ /dev/null @@ -1,251 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 4 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_DEBUG -#define RT_USING_OVERFLOW_CHECK -#define RT_DEBUG_INIT 0 -#define RT_DEBUG_THREAD 0 -#define RT_USING_HOOK -#define IDLE_THREAD_STACK_SIZE 256 - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMHEAP -#define RT_USING_MEMHEAP_AS_HEAP -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart1" -#define ARCH_ARM -#define ARCH_ARM_CORTEX_M -#define ARCH_ARM_CORTEX_M7 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 - -/* C++ features */ - - -/* Command shell */ - -#define RT_USING_FINSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT -#define FINSH_ARG_MAX 10 - -/* Device virtual file system */ - -#define RT_USING_DFS -#define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 -#define DFS_FD_MAX 4 -#define RT_USING_DFS_ELMFAT - -/* elm-chan's FatFs, Generic FAT Filesystem Module */ - -#define RT_DFS_ELM_CODE_PAGE 437 -#define RT_DFS_ELM_WORD_ACCESS -#define RT_DFS_ELM_USE_LFN_3 -#define RT_DFS_ELM_USE_LFN 3 -#define RT_DFS_ELM_MAX_LFN 255 -#define RT_DFS_ELM_DRIVES 2 -#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 -#define RT_DFS_ELM_REENTRANT -#define RT_USING_DFS_DEVFS - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_USING_SERIAL -#define RT_SERIAL_USING_DMA -#define RT_USING_I2C -#define RT_USING_I2C_BITOPS -#define RT_USING_PIN -#define RT_USING_RTC -#define RT_USING_SDIO -#define RT_USING_SPI - -/* Using USB */ - - -/* POSIX layer and C standard library */ - -#define RT_USING_LIBC - -/* Network stack */ - -/* light weight TCP/IP stack */ - -#define RT_USING_LWIP -#define RT_USING_LWIP202 -#define RT_LWIP_ICMP -#define RT_LWIP_DNS -#define RT_LWIP_DHCP -#define IP_SOF_BROADCAST 1 -#define IP_SOF_BROADCAST_RECV 1 - -/* Static IPv4 Address */ - -#define RT_LWIP_IPADDR "192.168.1.30" -#define RT_LWIP_GWADDR "192.168.1.1" -#define RT_LWIP_MSKADDR "255.255.255.0" -#define RT_LWIP_UDP -#define RT_LWIP_TCP -#define RT_MEMP_NUM_NETCONN 8 -#define RT_LWIP_PBUF_NUM 16 -#define RT_LWIP_RAW_PCB_NUM 4 -#define RT_LWIP_UDP_PCB_NUM 4 -#define RT_LWIP_TCP_PCB_NUM 4 -#define RT_LWIP_TCP_SEG_NUM 40 -#define RT_LWIP_TCP_SND_BUF 8196 -#define RT_LWIP_TCP_WND 8196 -#define RT_LWIP_TCPTHREAD_PRIORITY 10 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 -#define RT_LWIP_ETHTHREAD_PRIORITY 12 -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 -#define LWIP_NETIF_STATUS_CALLBACK 1 -#define SO_REUSE 1 -#define LWIP_SO_RCVTIMEO 1 -#define LWIP_SO_SNDTIMEO 1 -#define LWIP_SO_RCVBUF 1 -#define LWIP_NETIF_LOOPBACK 0 - -/* Modbus master and slave stack */ - - -/* VBUS(Virtual Software BUS) */ - - -/* Utilities */ - - -/* ARM CMSIS */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* security packages */ - - -/* language packages */ - - -/* multimedia packages */ - - -/* tools packages */ - - -/* system packages */ - -/* RT-Thread GUI Engine */ - - -/* peripheral libraries and drivers */ - - -/* miscellaneous packages */ - - -/* sample package */ - - -/* example package: hello */ - - -/* Privated Packages of RealThread */ - - -/* Network Utilities */ - -#define SOC_IMXRT1052 -#define BOARD_USING_HYPERFLASH -#define BOARD_RT1050_EVK - -/* RT1050 Bsp Config */ - -/* Select uart drivers */ - -#define RT_USING_UART1 - -/* Select spi bus and dev drivers */ - -#define LPSPI_CLK_SOURCE_FROM_PLL3PFD1 -#define LPSPI_CLK_SOURCE 0 -#define LPSPI_CLK_SOURCE_DIVIDER 8 -#define RT_USING_SPIBUS4 -#define LPSPI4_SCK_GPIO_1 -#define LPSPI4_SDO_GPIO_1 -#define LPSPI4_SDI_GPIO_1 - -/* Select iic bus drivers */ - -#define RT_USING_HW_I2C1 -#define HW_I2C1_BADURATE_100kHZ - -/* Select lcd driver */ - -/* Notice: Evk Board para: 480*272 4 4 8 2 40 10 106 45 */ - -#define RT_USING_LCD -#define LCD_WIDTH 480 -#define LCD_HEIGHT 272 -#define LCD_HFP 4 -#define LCD_VFP 4 -#define LCD_HBP 8 -#define LCD_VBP 2 -#define LCD_HSW 40 -#define LCD_VSW 10 -#define LCD_BL_PIN 106 -#define LCD_RST_PIN 45 -#define RT_USING_SDRAM -#define RT_USING_RTC_HP - -#endif diff --git a/bsp/imxrt1052-evk/rtconfig.py b/bsp/imxrt1052-evk/rtconfig.py deleted file mode 100644 index cb11a8267d..0000000000 --- a/bsp/imxrt1052-evk/rtconfig.py +++ /dev/null @@ -1,144 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m7' -CROSS_TOOL='gcc' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = '/usr/local/Cellar/arm-none-eabi-gcc/7-2017-q4-major/gcc/bin/' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = 'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -#BUILD = 'debug' -BUILD = 'release' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - CXX = PREFIX + 'g++' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - STRIP = PREFIX + 'strip' - - DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -std=c99 -Wall -D__FPU_PRESENT -eentry' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread-imxrt-gcc.map,-cref,-u,Reset_Handler -T ./Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -gdwarf-2' - AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - else: - CFLAGS += ' -O2 -Os' - - POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - - # module setting - CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' - M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' - M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' - M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ - ' -shared -fPIC -nostartfiles -static-libgcc' - M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M7.fp.sp' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread-imxrt-mdk.map --scatter ./Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf' - - CFLAGS += ' --diag_suppress=66,1296,186' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' - - EXEC_PATH += '/arm/bin40/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' --c99' - - POST_ACTION = 'fromelf -z $TARGET' - # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - CXX = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = ' -D__FPU_PRESENT' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M7' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - CXXFLAGS = CFLAGS - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M7' - AFLAGS += ' --fpu None' - - LFLAGS = ' --config ./Libraries/iar/MIMXRT1052xxxxx_flexspi_nor.icf' - LFLAGS += ' --redirect _Printf=_PrintfTiny' - LFLAGS += ' --redirect _Scanf=_ScanfSmall' - LFLAGS += ' --entry __iar_program_start' - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = '' diff --git a/bsp/imxrt1052-evk/template.ewp b/bsp/imxrt1052-evk/template.ewp deleted file mode 100644 index cf4216d8b3..0000000000 --- a/bsp/imxrt1052-evk/template.ewp +++ /dev/null @@ -1,1823 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 21 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 28 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 14 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 21 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 28 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 14 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - - diff --git a/bsp/imxrt1052-evk/template.uvoptx b/bsp/imxrt1052-evk/template.uvoptx deleted file mode 100644 index deca1cf444..0000000000 --- a/bsp/imxrt1052-evk/template.uvoptx +++ /dev/null @@ -1,190 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - RT-Thread IMXRT1052 - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 8 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - .\Libraries\arm\evkmimxrt1050_flexspi_nor.ini - BIN\CMSIS_AGDI.dll - - - - 0 - JL2CM3 - -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC.FLM -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM) - - - 0 - CMSIS_AGDI - -X"" -O974 -S0 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC.FLM -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM) - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM)) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - - diff --git a/bsp/imxrt1052-evk/template.uvprojx b/bsp/imxrt1052-evk/template.uvprojx deleted file mode 100644 index 30ff50525f..0000000000 --- a/bsp/imxrt1052-evk/template.uvprojx +++ /dev/null @@ -1,400 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - RT-Thread IMXRT1052 - 0x4 - ARM-ADS - 5060528::V5.06 update 5 (build 528)::ARMCC - 0 - - - MIMXRT1052:M7 - NXP - NXP.iMXRT_DFP.1.0.2 - http://mcuxpresso.nxp.com/cmsis_pack/repo/ - IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0RT1050 -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\RT1050.FLM)) - 0 - $$Device:MIMXRT1052$Device\Include\MIMXRT1052.h - - - - - - - - - - $$Device:MIMXRT1052$SVD\MIMXRT1052.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-imxrt - 1 - 0 - 0 - 1 - 0 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread-mdk.bin - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP -MPU - DCM.DLL - -pCM7 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM7 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4099 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M7" - - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 2 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x60000 - - - 1 - 0x0 - 0x8000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x60000 - - - 0 - 0x0 - 0x20000 - - - - - - 1 - 3 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x10000000 - - .\Libraries\arm\MIMXRT1052xxxxx_flexspi_nor.scf - - - - - - - - - - - ::CMSIS - - - - - - - - - - - - - - - - - - - diff --git a/bsp/imxrt1052-evk/xip/SConscript b/bsp/imxrt1052-evk/xip/SConscript deleted file mode 100644 index 1b69f9e2e5..0000000000 --- a/bsp/imxrt1052-evk/xip/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -if GetDepend('BOARD_USING_HYPERFLASH'): - cwd = GetCurrentDir() - src = Glob('*.c') - CPPPATH = [cwd] - - if rtconfig.CROSS_TOOL == 'keil': - LINKFLAGS = '--keep=*(.boot_hdr.ivt)' - LINKFLAGS += '--keep=*(.boot_hdr.boot_data)' - LINKFLAGS += '--keep=*(.boot_hdr.dcd_data)' - LINKFLAGS += '--keep=*(.boot_hdr.conf)' - else: - LINKFLAGS = '' - - group = DefineGroup('xip', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS) - Return('group') - -if GetDepend('BOARD_USING_QSPIFLASH'): - group = [] - Return('group') diff --git a/bsp/imxrt1052-evk/xip/fsl_flexspi_nor_boot.c b/bsp/imxrt1052-evk/xip/fsl_flexspi_nor_boot.c deleted file mode 100644 index 5addfdbfaf..0000000000 --- a/bsp/imxrt1052-evk/xip/fsl_flexspi_nor_boot.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flexspi_nor_boot.h" - -#if defined(__CC_ARM) || defined(__GNUC__) - __attribute__((section(".boot_hdr.ivt"))) -#elif defined(__ICCARM__) -#pragma location=".boot_hdr.ivt" -#endif - -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - 0x60002000, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -#if defined(__CC_ARM) || defined(__GNUC__) - __attribute__((section(".boot_hdr.boot_data"))) -#elif defined(__ICCARM__) -#pragma location=".boot_hdr.boot_data" -#endif - -const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - (FLASH_END-FLASH_BASE), /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; - -#if defined(__CC_ARM) || defined(__GNUC__) - __attribute__((section(".boot_hdr.dcd_data"))) -#elif defined(__ICCARM__) -#pragma location=".boot_hdr.dcd_data" -#endif -const uint8_t dcd_sdram[1072] = { -/*0000*/ 0xD2, 0x04, 0x30, 0x41, 0xCC, 0x03, 0xAC, 0x04, 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, -/*0010*/ 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, -/*0020*/ 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, -/*0030*/ 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, -/*0040*/ 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, -/*0050*/ 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, -/*0060*/ 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, -/*0070*/ 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, -/*0080*/ 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, -/*0090*/ 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, -/*00a0*/ 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, -/*00b0*/ 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, -/*00c0*/ 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, -/*00d0*/ 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, -/*00e0*/ 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, -/*00f0*/ 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, -/*0100*/ 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, -/*0110*/ 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, -/*0120*/ 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, -/*0130*/ 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, -/*0140*/ 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, -/*0150*/ 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, -/*0160*/ 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, -/*0170*/ 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, -/*0180*/ 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, -/*0190*/ 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, 0x40, 0x1F, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00, -/*01a0*/ 0x40, 0x1F, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, -/*01b0*/ 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, -/*01c0*/ 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, -/*01d0*/ 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, -/*01e0*/ 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, -/*01f0*/ 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, -/*0200*/ 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, -/*0210*/ 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, -/*0220*/ 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, -/*0230*/ 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, -/*0240*/ 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, -/*0250*/ 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, -/*0260*/ 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, -/*0270*/ 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, -/*0280*/ 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, -/*0290*/ 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, -/*02a0*/ 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, -/*02b0*/ 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, -/*02c0*/ 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, -/*02d0*/ 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, -/*02e0*/ 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0xA4, 0x00, 0x01, 0x10, 0xF9, -/*02f0*/ 0x40, 0x1F, 0x82, 0xA8, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, -/*0300*/ 0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24, 0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24, -/*0310*/ 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, -/*0320*/ 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, -/*0330*/ 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, -/*0340*/ 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, -/*0350*/ 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, -/*0360*/ 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, -/*0370*/ 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, -/*0380*/ 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, -/*0390*/ 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, -/*03a0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, -/*03b0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, -/*03c0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, -/*03d0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, -/*03e0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, -/*03f0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x1C, 0x04, -/*0400*/ 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, -/*0410*/ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, -/*0420*/ 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09, -}; diff --git a/bsp/imxrt1052-evk/xip/fsl_flexspi_nor_boot.h b/bsp/imxrt1052-evk/xip/fsl_flexspi_nor_boot.h deleted file mode 100644 index 073bf5229b..0000000000 --- a/bsp/imxrt1052-evk/xip/fsl_flexspi_nor_boot.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _QUADSPI_BOOT_H_ -#define _QUADSPI_BOOT_H_ - -#include - -/************************************* - * IVT Data - *************************************/ -typedef struct _ivt_ { - /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields - * (see @ref data) - */ - uint32_t hdr; - /** Absolute address of the first instruction to execute from the - * image - */ - uint32_t entry; - /** Reserved in this version of HAB: should be NULL. */ - uint32_t reserved1; - /** Absolute address of the image DCD: may be NULL. */ - uint32_t dcd; - /** Absolute address of the Boot Data: may be NULL, but not interpreted - * any further by HAB - */ - uint32_t boot_data; - /** Absolute address of the IVT.*/ - uint32_t self; - /** Absolute address of the image CSF.*/ - uint32_t csf; - /** Reserved in this version of HAB: should be zero. */ - uint32_t reserved2; -} ivt; - -#define IVT_MAJOR_VERSION 0x4 -#define IVT_MAJOR_VERSION_SHIFT 0x4 -#define IVT_MAJOR_VERSION_MASK 0xF -#define IVT_MINOR_VERSION 0x1 -#define IVT_MINOR_VERSION_SHIFT 0x0 -#define IVT_MINOR_VERSION_MASK 0xF - -#define IVT_VERSION(major, minor) \ - ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ - (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) - -#define IVT_TAG_HEADER (0xD1) /**< Image Vector Table */ -#define IVT_SIZE 0x2000 -#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) - -#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) -#define IVT_RSVD (uint32_t)(0x00000000) - - -/************************************* - * Boot Data - *************************************/ -typedef struct _boot_data_ { - uint32_t start; /* boot start location */ - uint32_t size; /* size */ - uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ - uint32_t placeholder; /* placehoder to make even 0x10 size */ -}BOOT_DATA_T; - - -/************************************* - * DCD Data - *************************************/ -#define DCD_TAG_HEADER (0xD2) -#define DCD_TAG_HEADER_SHIFT (24) -#define DCD_VERSION (0x40) -#define DCD_ARRAY_SIZE 1 - -#define FLASH_BASE 0x60000000 -#define FLASH_END 0x7F7FFFFF -#define SCLK 1 - -#define DCD_ADDRESS dcd_sdram -#define BOOT_DATA_ADDRESS &boot_data -#define CSF_ADDRESS 0 -#define PLUGIN_FLAG (uint32_t)0 - -/* External Variables */ -extern const uint8_t dcd_sdram[1072]; -extern const BOOT_DATA_T boot_data; - -#endif diff --git a/bsp/imxrt1052-evk/xip/fsl_flexspi_nor_flash.c b/bsp/imxrt1052-evk/xip/fsl_flexspi_nor_flash.c deleted file mode 100644 index 67076dd62f..0000000000 --- a/bsp/imxrt1052-evk/xip/fsl_flexspi_nor_flash.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * The Clear BSD License - * Copyright 2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_flexspi_nor_flash.h" - -/******************************************************************************* - * Code - ******************************************************************************/ -#if defined(__CC_ARM) || defined(__GNUC__) - __attribute__((section(".boot_hdr.conf"))) -#elif defined(__ICCARM__) -#pragma location=".boot_hdr.conf" -#endif - -const flexspi_nor_config_t hyperflash_config = -{ - .memConfig = - { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .columnAddressWidth = 3u, - // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock - .controllerMiscOption = (1u << kFlexSpiMiscOffset_DdrModeEnable) | - (1u << kFlexSpiMiscOffset_WordAddressableEnable) | - (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | - (1u << kFlexSpiMiscOffset_DiffClkEnable), - .sflashPadType = kSerialFlash_8Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = 64u * 1024u * 1024u, - .dataValidTime = {16u, 16u}, - .lookupTable = - { - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), - FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), - FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), - }, - }, - .pageSize = 512u, - .sectorSize = 256u * 1024u, - .blockSize = 256u * 1024u, - .isUniformBlockSize = true, -}; diff --git a/bsp/imxrt1052-evk/xip/fsl_flexspi_nor_flash.h b/bsp/imxrt1052-evk/xip/fsl_flexspi_nor_flash.h deleted file mode 100644 index 6d3b5269cd..0000000000 --- a/bsp/imxrt1052-evk/xip/fsl_flexspi_nor_flash.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this - * list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, - * this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FLEXSPI_NOR_FLASH_H__ -#define __FLEXSPI_NOR_FLASH_H__ - -#include -#include -#include "fsl_common.h" - -/* FLEXSPI memory config block related defintions */ -#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian -#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 -#define FLEXSPI_CFG_BLK_SIZE (512) - -/* FLEXSPI Feature related definitions */ -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 - -/* Lookup table related defintions */ -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 -#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 - -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0A -#define LEARN_DDR 0x2A -#define DATSZ_SDR 0x0B -#define DATSZ_DDR 0x2B -#define DUMMY_SDR 0x0C -#define DUMMY_DDR 0x2C -#define DUMMY_RWDS_SDR 0x0D -#define DUMMY_RWDS_DDR 0x2D -#define JMP_ON_CS 0x1F -#define STOP 0 - -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 - -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -//!@brief Definitions for FlexSPI Serial Clock Frequency -typedef enum _FlexSpiSerialClockFreq -{ - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_75MHz = 4, - kFlexSpiSerialClk_80MHz = 5, - kFlexSpiSerialClk_100MHz = 6, - kFlexSpiSerialClk_133MHz = 7, - kFlexSpiSerialClk_166MHz = 8, - kFlexSpiSerialClk_200MHz = 9, -} flexspi_serial_clk_freq_t; - -//!@brief FlexSPI clock configuration type -enum -{ - kFlexSpiClk_SDR, //!< Clock configure for SDR mode - kFlexSpiClk_DDR, //!< Clock configurat for DDR mode -}; - -//!@brief FlexSPI Read Sample Clock Source definition -typedef enum _FlashReadSampleClkSource -{ - kFlexSPIReadSampleClk_LoopbackInternally = 0, - kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, - kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, -} flexspi_read_sample_clk_t; - - -//!@brief Misc feature bit definitions -enum -{ - kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable - kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable - kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable - kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable - kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable - kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable - kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. -}; - -//!@brief Flash Type Definition -enum -{ - kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR - kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND - kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH - kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND - kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs -}; - -//!@brief Flash Pad Definitions -enum -{ - kSerialFlash_1Pad = 1, - kSerialFlash_2Pads = 2, - kSerialFlash_4Pads = 4, - kSerialFlash_8Pads = 8, -}; - -//!@brief FlexSPI LUT Sequence structure -typedef struct _lut_sequence -{ - uint8_t seqNum; //!< Sequence Number, valid number: 1-16 - uint8_t seqId; //!< Sequence Index, valid number: 0-15 - uint16_t reserved; -} flexspi_lut_seq_t; - -//!@brief Flash Configuration Command Type -enum -{ - kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc - kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command - kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode - kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode - kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode - kDeviceConfigCmdType_Reset, //!< Reset device command -}; - -//!@brief FlexSPI Memory Configuration Block -typedef struct _FlexSPIConfig -{ - uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL - uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix - uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use - uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 - uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 - uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 - uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For - //! Serial NAND, need to refer to datasheet - uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable - uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, - //! Generic configuration, etc. - uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for - //! DPI/QPI/OPI switch or reset command - flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt - //! sequence number, [31:16] Reserved - uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration - uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable - uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe - flexspi_lut_seq_t - configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq - uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use - uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands - uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use - uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more - //! details - uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details - uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal - uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot - //! Chapter for more details - uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot - //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH - uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use - uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 - uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 - uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 - uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 - uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value - uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value - uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value - uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value - uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command - uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands - uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns - uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 - uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - - //! busy flag is 0 when flash device is busy - uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences - flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences - uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use -} flexspi_mem_config_t; - -/* */ -#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 -#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 -#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 -#define NOR_CMD_INDEX_DUMMY 6 //!< 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 - -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk - - -/* - * Serial NOR configuration block - */ -typedef struct _flexspi_nor_config -{ - flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI - uint32_t pageSize; //!< Page size of Serial NOR - uint32_t sectorSize; //!< Sector size of Serial NOR - uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command - uint8_t isUniformBlockSize; //!< Sector/Block size is the same - uint8_t reserved0[2]; //!< Reserved for future use - uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 - uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command - uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false - uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution - uint32_t blockSize; //!< Block size - uint32_t reserve2[11]; //!< Reserved for future use -} flexspi_nor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif // __FLEXSPI_NOR_FLASH_H__ -- GitLab