diff --git a/libcpu/arm/s3c24x0/start_rvds.s b/libcpu/arm/s3c24x0/start_rvds.s
new file mode 100644
index 0000000000000000000000000000000000000000..5dc5d8aefef2cc1ef1b6b033f3e780cf79d1757b
--- /dev/null
+++ b/libcpu/arm/s3c24x0/start_rvds.s
@@ -0,0 +1,1165 @@
+;/*****************************************************************************/
+;/* S3C2440.S: Startup file for Samsung S3C440 */
+;/*****************************************************************************/
+;/* <<< Use Configuration Wizard in Context Menu >>> */
+;/*****************************************************************************/
+;/* This file is part of the uVision/ARM development tools. */
+;/* Copyright (c) 2005-2008 Keil Software. All rights reserved. */
+;/* This software may only be used under the terms of a valid, current, */
+;/* end user licence from KEIL for a compatible version of KEIL software */
+;/* development tools. Nothing else gives you the right to use this software. */
+;/*****************************************************************************/
+
+
+;/*
+; * The S3C2440.S code is executed after CPU Reset. This file may be
+; * translated with the following SET symbols. In uVision these SET
+; * symbols are entered under Options - ASM - Define.
+; *
+; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock
+; * (used mostly when clock is already initialized from script .ini
+; * file).
+; *
+; * NO_MC_SETUP: when set the startup code will not initialize Memory
+; * Controller (used mostly when clock is already initialized from script
+; * .ini file).
+; *
+; * NO_GP_SETUP: when set the startup code will not initialize General Ports
+; * (used mostly when clock is already initialized from script .ini
+; * file).
+; *
+; * RAM_INTVEC: when set the startup code copies exception vectors
+; * from execution address to on-chip RAM.
+; */
+
+
+; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
+
+Mode_USR EQU 0x10
+Mode_FIQ EQU 0x11
+Mode_IRQ EQU 0x12
+Mode_SVC EQU 0x13
+Mode_ABT EQU 0x17
+Mode_UND EQU 0x1B
+Mode_SYS EQU 0x1F
+
+I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
+F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
+
+
+;----------------------- Stack and Heap Definitions ----------------------------
+
+;// Stack Configuration (Stack Sizes in Bytes)
+;// Undefined Mode <0x0-0xFFFFFFFF:8>
+;// Supervisor Mode <0x0-0xFFFFFFFF:8>
+;// Abort Mode <0x0-0xFFFFFFFF:8>
+;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
+;// Interrupt Mode <0x0-0xFFFFFFFF:8>
+;// User/System Mode <0x0-0xFFFFFFFF:8>
+;//
+
+UND_Stack_Size EQU 0x00000000
+SVC_Stack_Size EQU 0x00000100
+ABT_Stack_Size EQU 0x00000000
+FIQ_Stack_Size EQU 0x00000000
+IRQ_Stack_Size EQU 0x00000100
+USR_Stack_Size EQU 0x00000100
+
+ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+ FIQ_Stack_Size + IRQ_Stack_Size)
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+
+Stack_Mem SPACE USR_Stack_Size
+__initial_sp SPACE ISR_Stack_Size
+Stack_Top
+
+
+;// Heap Configuration
+;// Heap Size (in Bytes) <0x0-0xFFFFFFFF>
+;//
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+;----------------------- Memory Definitions ------------------------------------
+
+; Internal Memory Base Addresses
+IRAM_BASE EQU 0x40000000
+
+
+;----------------------- Watchdog Timer Definitions ----------------------------
+
+WT_BASE EQU 0x53000000 ; Watchdog Timer Base Address
+WTCON_OFS EQU 0x00 ; Watchdog Timer Control Register Offset
+WTDAT_OFS EQU 0x04 ; Watchdog Timer Data Register Offset
+WTCNT_OFS EQU 0x08 ; Watchdog Timer Count Register Offset
+
+;// Watchdog Timer Setup
+;// Watchdog Timer Control Register (WTCON)
+;// Prescaler Value <0-255>
+;// Watchdog Timer Enable
+;// Clock Division Factor
+;// <0=> 16 <1=> 32 <2=> 64 <3=> 128
+;// Interrupt Generation Enable
+;// Reset Enable
+;//
+;// Watchdog Timer Data Register (WTDAT)
+;// Count Reload Value <0-65535>
+;//
+;// Watchdog Timer Setup
+WT_SETUP EQU 1
+WTCON_Val EQU 0x00000000
+WTDAT_Val EQU 0x00008000
+
+
+;----------------------- Clock and Power Management Definitions ----------------
+
+CLOCK_BASE EQU 0x4C000000 ; Clock Base Address
+LOCKTIME_OFS EQU 0x00 ; PLL Lock Time Count Register Offset
+MPLLCON_OFS EQU 0x04 ; MPLL Configuration Register Offset
+UPLLCON_OFS EQU 0x08 ; UPLL Configuration Register Offset
+CLKCON_OFS EQU 0x0C ; Clock Generator Control Reg Offset
+CLKSLOW_OFS EQU 0x10 ; Clock Slow Control Register Offset
+CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset
+CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset
+
+;// Clock Setup
+;// PLL Lock Time Count Register (LOCKTIME)
+;// U_LTIME: UPLL Lock Time Count Value for UCLK <0x0-0xFFFF>
+;// M_LTIME: MPLL Lock Time Count Value for FCLK, HCLK and PCLK <0x0-0xFFFF>
+;//
+;// MPLL Configuration Register (MPLLCON)
+;// MPLL = (2 * m * Fin) / (p * 2^s)
+;// m: Main Divider m Value <9-256><#-8>
+;// m = MDIV + 8
+;// p: Pre-divider p Value <3-64><#-2>
+;// p = PDIV + 2
+;// s: Post Divider s Value <0-3>
+;// s = SDIV
+;//
+;// UPLL Configuration Register (UPLLCON)
+;// UPLL = ( m * Fin) / (p * 2^s)
+;// m: Main Divider m Value <8-263><#-8>
+;// m = MDIV + 8
+;// p: Pre-divider p Value <2-65><#-2>
+;// p = PDIV + 2
+;// s: Post Divider s Value <0-3>
+;// s = SDIV
+;//
+;// Clock Generation Control Register (CLKCON)
+;// AC97 Enable
+;// Camera Enable
+;// SPI Enable
+;// IIS Enable
+;// IIC Enable
+;// ADC + Touch Screen Enable
+;// RTC Enable
+;// GPIO Enable
+;// UART2 Enable
+;// UART1 Enable
+;// UART0 Enable
+;// SDI Enable
+;// PWMTIMER Enable
+;// USB Device Enable
+;// USB Host Enable
+;// LCDC Enable
+;// NAND FLASH Controller Enable
+;// SLEEP Enable
+;// IDLE BIT Enable
+;//
+;// Clock Slow Control Register (CLKSLOW)
+;// UCLK_ON: UCLK ON
+;// MPLL_OFF: Turn off PLL
+;// SLOW_BIT: Slow Mode Enable
+;// SLOW_VAL: Slow Clock Divider <0-7>
+;//
+;// Clock Divider Control Register (CLKDIVN)
+;// DIVN_UPLL: UCLK Select
+;// <0=> UCLK = UPLL clock
+;// <1=> UCLK = UPLL clock / 2
+;// HDIVN: HCLK Select
+;// <0=> HCLK = FCLK
+;// <1=> HCLK = FCLK / 2
+;// <2=> HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8
+;// <3=> HCLK = FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6
+;// PDIVN: PCLK Select
+;// <0=> PCLK = HCLK
+;// <1=> PCLK = HCLK / 2
+;//
+;// Camera Clock Divider Control Register (CAMDIVN)
+;// DVS_EN: ARM Core Clock Select
+;// <0=> ARM core runs at FCLK
+;// <1=> ARM core runs at HCLK
+;// HCLK4_HALF: HDIVN Division Rate Change Bit
+;// <0=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4
+;// <1=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8
+;// HCLK3_HALF: HDIVN Division Rate Change Bit
+;// <0=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 3
+;// <1=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6
+;// CAMCLK Select
+;// <0=> CAMCLK = UPLL
+;// <1=> CAMCLK = UPLL / CAMCLK_DIV
+;// CAMCLK_DIV: CAMCLK Divider <0-15>
+;// Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1))
+;// Divider is used only if CAMCLK_SEL = 1
+;//
+;// Clock Setup
+CLOCK_SETUP EQU 0
+LOCKTIME_Val EQU 0x0FFF0FFF
+MPLLCON_Val EQU 0x00043011
+UPLLCON_Val EQU 0x00038021
+CLKCON_Val EQU 0x001FFFF0
+CLKSLOW_Val EQU 0x00000004
+CLKDIVN_Val EQU 0x0000000F
+CAMDIVN_Val EQU 0x00000000
+
+
+;----------------------- Memory Controller Definitions -------------------------
+
+MC_BASE EQU 0x48000000 ; Memory Controller Base Address
+BWSCON_OFS EQU 0x00 ; Bus Width and Wait Status Ctrl Offset
+BANKCON0_OFS EQU 0x04 ; Bank 0 Control Register Offset
+BANKCON1_OFS EQU 0x08 ; Bank 1 Control Register Offset
+BANKCON2_OFS EQU 0x0C ; Bank 2 Control Register Offset
+BANKCON3_OFS EQU 0x10 ; Bank 3 Control Register Offset
+BANKCON4_OFS EQU 0x14 ; Bank 4 Control Register Offset
+BANKCON5_OFS EQU 0x18 ; Bank 5 Control Register Offset
+BANKCON6_OFS EQU 0x1C ; Bank 6 Control Register Offset
+BANKCON7_OFS EQU 0x20 ; Bank 7 Control Register Offset
+REFRESH_OFS EQU 0x24 ; SDRAM Refresh Control Register Offset
+BANKSIZE_OFS EQU 0x28 ; Flexible Bank Size Register Offset
+MRSRB6_OFS EQU 0x2C ; Bank 6 Mode Register Offset
+MRSRB7_OFS EQU 0x30 ; Bank 7 Mode Register Offset
+
+;// Memory Controller Setup
+;// Bus Width and Wait Control Register (BWSCON)
+;// ST7: Use UB/LB for Bank 7
+;// WS7: Enable Wait Status for Bank 7
+;// DW7: Data Bus Width for Bank 7
+;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
+;// ST6: Use UB/LB for Bank 6
+;// WS6: Enable Wait Status for Bank 6
+;// DW6: Data Bus Width for Bank 6
+;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
+;// ST5: Use UB/LB for Bank 5
+;// WS5: Enable Wait Status for Bank 5
+;// DW5: Data Bus Width for Bank 5
+;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
+;// ST4: Use UB/LB for Bank 4
+;// WS4: Enable Wait Status for Bank 4
+;// DW4: Data Bus Width for Bank 4
+;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
+;// ST3: Use UB/LB for Bank 3
+;// WS3: Enable Wait Status for Bank 3
+;// DW3: Data Bus Width for Bank 3
+;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
+;// ST2: Use UB/LB for Bank 2
+;// WS2: Enable Wait Status for Bank 2
+;// DW2: Data Bus Width for Bank 2
+;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
+;// ST1: Use UB/LB for Bank 1
+;// WS1: Enable Wait Status for Bank 1
+;// DW1: Data Bus Width for Bank 1
+;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
+;// DW0: Indicate Data Bus Width for Bank 0
+;// <1=> 16-bit <2=> 32-bit
+;//
+;// Bank 0 Control Register (BANKCON0)
+;// Tacs: Address Set-up Time before nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcos: Chip Selection Set-up Time before nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacc: Access Cycle
+;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
+;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
+;// Tcoh: Chip Selection Hold Time after nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcah: Address Hold Time after nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacp: Page Mode Access Cycle at Page Mode
+;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
+;// PMC: Page Mode Configuration
+;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
+;//
+;// Bank 1 Control Register (BANKCON1)
+;// Tacs: Address Set-up Time before nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcos: Chip Selection Set-up Time before nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacc: Access Cycle
+;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
+;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
+;// Tcoh: Chip Selection Hold Time after nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcah: Address Hold Time after nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacp: Page Mode Access Cycle at Page Mode
+;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
+;// PMC: Page Mode Configuration
+;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
+;//
+;// Bank 2 Control Register (BANKCON2)
+;// Tacs: Address Set-up Time before nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcos: Chip Selection Set-up Time before nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacc: Access Cycle
+;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
+;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
+;// Tcoh: Chip Selection Hold Time after nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcah: Address Hold Time after nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacp: Page Mode Access Cycle at Page Mode
+;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
+;// PMC: Page Mode Configuration
+;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
+;//
+;// Bank 3 Control Register (BANKCON3)
+;// Tacs: Address Set-up Time before nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcos: Chip Selection Set-up Time before nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacc: Access Cycle
+;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
+;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
+;// Tcoh: Chip Selection Hold Time after nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcah: Address Hold Time after nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacp: Page Mode Access Cycle at Page Mode
+;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
+;// PMC: Page Mode Configuration
+;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
+;//
+;// Bank 4 Control Register (BANKCON4)
+;// Tacs: Address Set-up Time before nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcos: Chip Selection Set-up Time before nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacc: Access Cycle
+;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
+;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
+;// Tcoh: Chip Selection Hold Time after nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcah: Address Hold Time after nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacp: Page Mode Access Cycle at Page Mode
+;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
+;// PMC: Page Mode Configuration
+;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
+;//
+;// Bank 5 Control Register (BANKCON5)
+;// Tacs: Address Set-up Time before nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcos: Chip Selection Set-up Time before nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacc: Access Cycle
+;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
+;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
+;// Tcoh: Chip Selection Hold Time after nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcah: Address Hold Time after nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacp: Page Mode Access Cycle at Page Mode
+;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
+;// PMC: Page Mode Configuration
+;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
+;//
+;// Bank 6 Control Register (BANKCON6)
+;// Memory Type Selection
+;// <0=> ROM or SRAM <3=> SDRAM
+;// Tacs: Address Set-up Time before nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcos: Chip Selection Set-up Time before nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacc: Access Cycle
+;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
+;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
+;// Tcoh: Chip Selection Hold Time after nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcah: Address Hold Time after nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay
+;// Parameter depends on Memory Type: if type SRAM then parameter is Tacp,
+;// if type is SDRAM then parameter is Trcd
+;// For SDRAM 6 cycles setting is not allowed
+;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
+;// PMC/SCAN: Page Mode Configuration / Column Address Number <0-3>
+;// Parameter depends on Memory Type: if type SRAM then parameter is PMC,
+;// if type is SDRAM then parameter is SCAN
+;//
+;// Bank 7 Control Register (BANKCON7)
+;// Memory Type Selection
+;// <0=> ROM or SRAM <3=> SDRAM
+;// Tacs: Address Set-up Time before nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcos: Chip Selection Set-up Time before nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacc: Access Cycle
+;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
+;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
+;// Tcoh: Chip Selection Hold Time after nOE
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tcah: Address Hold Time after nGCS
+;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
+;// Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay
+;// Parameter depends on Memory Type: if type SRAM then parameter is Tacp,
+;// if type is SDRAM then parameter is Trcd
+;// For SDRAM 6 cycles setting is not allowed
+;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
+;// PMC/SCAN: Page Mode Configuration / Column Address Number <0-3>
+;// Parameter depends on Memory Type: if type SRAM then parameter is PMC,
+;// if type is SDRAM then parameter is SCAN
+;//
+;// SDRAM Refresh Control Register (REFRESH)
+;// REFEN: SDRAM Refresh Enable
+;// TREFMD: SDRAM Refresh Mode
+;// <0=> CBR/Auto Refresh <1=> Self Refresh
+;// Trp: SDRAM RAS Pre-charge Time
+;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> Reserved
+;// Tsrc: SDRAM Semi Row Cycle Time
+;// SDRAM Row cycle time: Trc = Tsrc + Trp
+;// <0=> 4 clocks <1=> 5 clocks <2=> 6 clocks <3=> 7 clocks
+;// Refresh Counter <0-1023>
+;// Refresh Period = (2048 - Refresh Count + 1) / HCLK
+;//
+;// Flexible Bank Size Register (BANKSIZE)
+;// BURST_EN: ARM Core Burst Operation Enable
+;// SCKE_EN: SDRAM Power Down Mode Enable
+;// SCLK_EN: SCLK Enabled During SDRAM Access Cycle
+;// <0=> SCLK is always active <1=> SCLK is active only during the access
+;// BK76MAP: BANK6 and BANK7 Memory Map
+;// <0=> 32MB / 32MB <1=> 64MB / 64MB <2=> 128MB / 128MB
+;// <4=> 2MB / 2MB <5=> 4MB / 4MB <6=> 8MB / 8MB <7=> 16MB / 16MB
+;// Refresh Counter <0-1023>
+;// Refresh Period = (2048 - Refresh Count + 1) / HCLK
+;//
+;// SDRAM Mode Register Set Register 6 (MRSRB6)
+;// WBL: Write Burst Length
+;// <0=> Burst (Fixed)
+;// TM: Test Mode
+;// <0=> Mode register set (Fixed)
+;// CL: CAS Latency
+;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks
+;// BT: Burst Type
+;// <0=> Sequential (Fixed)
+;// BL: Burst Length
+;// <0=> 1 (Fixed)
+;//
+;// SDRAM Mode Register Set Register 7 (MRSRB7)
+;// WBL: Write Burst Length
+;// <0=> Burst (Fixed)
+;// TM: Test Mode
+;// <0=> Mode register set (Fixed)
+;// CL: CAS Latency
+;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks
+;// BT: Burst Type
+;// <0=> Sequential (Fixed)
+;// BL: Burst Length
+;// <0=> 1 (Fixed)
+;//
+;// Memory Controller Setup
+MC_SETUP EQU 0
+BWSCON_Val EQU 0x22000000
+BANKCON0_Val EQU 0x00000700
+BANKCON1_Val EQU 0x00000700
+BANKCON2_Val EQU 0x00000700
+BANKCON3_Val EQU 0x00000700
+BANKCON4_Val EQU 0x00000700
+BANKCON5_Val EQU 0x00000700
+BANKCON6_Val EQU 0x00018005
+BANKCON7_Val EQU 0x00018005
+REFRESH_Val EQU 0x008404F3
+BANKSIZE_Val EQU 0x00000032
+MRSRB6_Val EQU 0x00000020
+MRSRB7_Val EQU 0x00000020
+
+
+;----------------------- I/O Port Definitions ----------------------------------
+
+GPA_BASE EQU 0x56000000 ; GPA Base Address
+GPB_BASE EQU 0x56000010 ; GPB Base Address
+GPC_BASE EQU 0x56000020 ; GPC Base Address
+GPD_BASE EQU 0x56000030 ; GPD Base Address
+GPE_BASE EQU 0x56000040 ; GPE Base Address
+GPF_BASE EQU 0x56000050 ; GPF Base Address
+GPG_BASE EQU 0x56000060 ; GPG Base Address
+GPH_BASE EQU 0x56000070 ; GPH Base Address
+GPJ_BASE EQU 0x560000D0 ; GPJ Base Address
+GPCON_OFS EQU 0x00 ; Control Register Offset
+GPDAT_OFS EQU 0x04 ; Data Register Offset
+GPUP_OFS EQU 0x08 ; Pull-up Disable Register Offset
+
+;// I/O Setup
+GP_SETUP EQU 0
+
+;// Port A Settings
+;// Port A Control Register (GPACON)
+;// GPA22 <0=> Output <1=> nFCE
+;// GPA21 <0=> Output <1=> nRSTOUT
+;// GPA20 <0=> Output <1=> nFRE
+;// GPA19 <0=> Output <1=> nFWE
+;// GPA18 <0=> Output <1=> ALE
+;// GPA17 <0=> Output <1=> CLE
+;// GPA16 <0=> Output <1=> nGCS[5]
+;// GPA15 <0=> Output <1=> nGCS[4]
+;// GPA14 <0=> Output <1=> nGCS[3]
+;// GPA13 <0=> Output <1=> nGCS[2]
+;// GPA12 <0=> Output <1=> nGCS[1]
+;// GPA11 <0=> Output <1=> ADDR26
+;// GPA10 <0=> Output <1=> ADDR25
+;// GPA9 <0=> Output <1=> ADDR24
+;// GPA8 <0=> Output <1=> ADDR23
+;// GPA7 <0=> Output <1=> ADDR22
+;// GPA6 <0=> Output <1=> ADDR21
+;// GPA5 <0=> Output <1=> ADDR20
+;// GPA4 <0=> Output <1=> ADDR19
+;// GPA3 <0=> Output <1=> ADDR18
+;// GPA2 <0=> Output <1=> ADDR17
+;// GPA1 <0=> Output <1=> ADDR16
+;// GPA0 <0=> Output <1=> ADDR0
+;//
+;//
+GPA_SETUP EQU 0
+GPACON_Val EQU 0x000003FF
+
+;// Port B Settings
+;// Port B Control Register (GPBCON)
+;// GPB10 <0=> Input <1=> Output <2=> nXDREQ0 <3=> Reserved
+;// GPB9 <0=> Input <1=> Output <2=> nXDACK0 <3=> Reserved
+;// GPB8 <0=> Input <1=> Output <2=> nXDREQ1 <3=> Reserved
+;// GPB7 <0=> Input <1=> Output <2=> nXDACK1 <3=> Reserved
+;// GPB6 <0=> Input <1=> Output <2=> nXBREQ <3=> Reserved
+;// GPB5 <0=> Input <1=> Output <2=> nXBACK <3=> Reserved
+;// GPB4 <0=> Input <1=> Output <2=> TCLK[0] <3=> Reserved
+;// GPB3 <0=> Input <1=> Output <2=> TOUT3 <3=> Reserved
+;// GPB2 <0=> Input <1=> Output <2=> TOUT2 <3=> Reserved
+;// GPB1 <0=> Input <1=> Output <2=> TOUT1 <3=> Reserved
+;// GPB0 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved
+;//
+;// Port B Pull-up Settings Register (GPBUP)
+;// GPB10 Pull-up Disable
+;// GPB9 Pull-up Disable
+;// GPB8 Pull-up Disable
+;// GPB7 Pull-up Disable
+;// GPB6 Pull-up Disable
+;// GPB5 Pull-up Disable
+;// GPB4 Pull-up Disable
+;// GPB3 Pull-up Disable
+;// GPB2 Pull-up Disable
+;// GPB1 Pull-up Disable
+;// GPB0 Pull-up Disable
+;//
+;//
+GPB_SETUP EQU 0
+GPBCON_Val EQU 0x00000000
+GPBUP_Val EQU 0x00000000
+
+;// Port C Settings
+;// Port C Control Register (GPCCON)
+;// GPC15 <0=> Input <1=> Output <2=> VD[7] <3=> Reserved
+;// GPC14 <0=> Input <1=> Output <2=> VD[6] <3=> Reserved
+;// GPC13 <0=> Input <1=> Output <2=> VD[5] <3=> Reserved
+;// GPC12 <0=> Input <1=> Output <2=> VD[4] <3=> Reserved
+;// GPC11 <0=> Input <1=> Output <2=> VD[3] <3=> Reserved
+;// GPC10 <0=> Input <1=> Output <2=> VD[2] <3=> Reserved
+;// GPC9 <0=> Input <1=> Output <2=> VD[1] <3=> Reserved
+;// GPC8 <0=> Input <1=> Output <2=> VD[0] <3=> Reserved
+;// GPC7 <0=> Input <1=> Output <2=> LCD_LPCREVB <3=> Reserved
+;// GPC6 <0=> Input <1=> Output <2=> LCD_LPCREV <3=> Reserved
+;// GPC5 <0=> Input <1=> Output <2=> LCD_LPCOE <3=> Reserved
+;// GPC4 <0=> Input <1=> Output <2=> VM <3=> I2SSDI
+;// GPC3 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved
+;// GPC2 <0=> Input <1=> Output <2=> VLINE <3=> Reserved
+;// GPC1 <0=> Input <1=> Output <2=> VCLK <3=> Reserved
+;// GPC0 <0=> Input <1=> Output <2=> LEND <3=> Reserved
+;//
+;// Port C Pull-up Settings Register (GPCUP)
+;// GPC15 Pull-up Disable
+;// GPC14 Pull-up Disable
+;// GPC13 Pull-up Disable
+;// GPC12 Pull-up Disable
+;// GPC11 Pull-up Disable
+;// GPC10 Pull-up Disable
+;// GPC9 Pull-up Disable
+;// GPC8 Pull-up Disable
+;// GPC7 Pull-up Disable
+;// GPC6 Pull-up Disable
+;// GPC5 Pull-up Disable
+;// GPC4 Pull-up Disable
+;// GPC3 Pull-up Disable
+;// GPC2 Pull-up Disable
+;// GPC1 Pull-up Disable
+;// GPC0 Pull-up Disable
+;//
+;//
+GPC_SETUP EQU 0
+GPCCON_Val EQU 0x00000000
+GPCUP_Val EQU 0x00000000
+
+;// Port D Settings
+;// Port D Control Register (GPDCON)
+;// GPD15 <0=> Input <1=> Output <2=> VD[23] <3=> nSS0
+;// GPD14 <0=> Input <1=> Output <2=> VD[22] <3=> nSS1
+;// GPD13 <0=> Input <1=> Output <2=> VD[21] <3=> Reserved
+;// GPD12 <0=> Input <1=> Output <2=> VD[20] <3=> Reserved
+;// GPD11 <0=> Input <1=> Output <2=> VD[19] <3=> Reserved
+;// GPD10 <0=> Input <1=> Output <2=> VD[18] <3=> SPICLK1
+;// GPD9 <0=> Input <1=> Output <2=> VD[17] <3=> SPIMOSI1
+;// GPD8 <0=> Input <1=> Output <2=> VD[16] <3=> SPIMISO1
+;// GPD7 <0=> Input <1=> Output <2=> VD[15] <3=> Reserved
+;// GPD6 <0=> Input <1=> Output <2=> VD[14] <3=> Reserved
+;// GPD5 <0=> Input <1=> Output <2=> VD[13] <3=> Reserved
+;// GPD4 <0=> Input <1=> Output <2=> VD[12] <3=> Reserved
+;// GPD3 <0=> Input <1=> Output <2=> VD[11] <3=> Reserved
+;// GPD2 <0=> Input <1=> Output <2=> VD[10] <3=> Reserved
+;// GPD1 <0=> Input <1=> Output <2=> VD[9] <3=> Reserved
+;// GPD0 <0=> Input <1=> Output <2=> VD[8] <3=> Reserved
+;//
+;// Port D Pull-up Settings Register (GPDUP)
+;// GPD15 Pull-up Disable
+;// GPD14 Pull-up Disable
+;// GPD13 Pull-up Disable
+;// GPD12 Pull-up Disable
+;// GPD11 Pull-up Disable
+;// GPD10 Pull-up Disable
+;// GPD9 Pull-up Disable
+;// GPD8 Pull-up Disable
+;// GPD7 Pull-up Disable
+;// GPD6 Pull-up Disable
+;// GPD5 Pull-up Disable
+;// GPD4 Pull-up Disable
+;// GPD3 Pull-up Disable
+;// GPD2 Pull-up Disable
+;// GPD1 Pull-up Disable
+;// GPD0 Pull-up Disable
+;//
+;//
+GPD_SETUP EQU 0
+GPDCON_Val EQU 0x00000000
+GPDUP_Val EQU 0x00000000
+
+;// Port E Settings
+;// Port E Control Register (GPECON)
+;// GPE15 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved
+;// This pad is open-drain, and has no pull-up option.
+;// GPE14 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved
+;// This pad is open-drain, and has no pull-up option.
+;// GPE13 <0=> Input <1=> Output <2=> SPICLK0 <3=> Reserved
+;// GPE12 <0=> Input <1=> Output <2=> SPIMOSI0 <3=> Reserved
+;// GPE11 <0=> Input <1=> Output <2=> SPIMISO0 <3=> Reserved
+;// GPE10 <0=> Input <1=> Output <2=> SDDAT3 <3=> Reserved
+;// GPE9 <0=> Input <1=> Output <2=> SDDAT2 <3=> Reserved
+;// GPE8 <0=> Input <1=> Output <2=> SDDAT1 <3=> Reserved
+;// GPE7 <0=> Input <1=> Output <2=> SDDAT0 <3=> Reserved
+;// GPE6 <0=> Input <1=> Output <2=> SDCMD <3=> Reserved
+;// GPE5 <0=> Input <1=> Output <2=> SDCLK <3=> Reserved
+;// GPE4 <0=> Input <1=> Output <2=> I2SDO <3=> AC_SDATA_OUT
+;// GPE3 <0=> Input <1=> Output <2=> I2SDI <3=> AC_SDATA_IN
+;// GPE2 <0=> Input <1=> Output <2=> CDCLK <3=> AC_nRESET
+;// GPE1 <0=> Input <1=> Output <2=> I2SSCLK <3=> AC_BIT_CLK
+;// GPE0 <0=> Input <1=> Output <2=> I2SLRCK <3=> AC_SYNC
+;//
+;// Port E Pull-up Settings Register (GPEUP)
+;// GPE13 Pull-up Disable
+;// GPE12 Pull-up Disable
+;// GPE11 Pull-up Disable
+;// GPE10 Pull-up Disable
+;// GPE9 Pull-up Disable
+;// GPE8 Pull-up Disable
+;// GPE7 Pull-up Disable
+;// GPE6 Pull-up Disable
+;// GPE5 Pull-up Disable
+;// GPE4 Pull-up Disable
+;// GPE3 Pull-up Disable
+;// GPE2 Pull-up Disable
+;// GPE1 Pull-up Disable
+;// GPE0 Pull-up Disable
+;//
+;//
+GPE_SETUP EQU 0
+GPECON_Val EQU 0x00000000
+GPEUP_Val EQU 0x00000000
+
+;// Port F Settings
+;// Port F Control Register (GPFCON)
+;// GPF7 <0=> Input <1=> Output <2=> EINT[7] <3=> Reserved
+;// GPF6 <0=> Input <1=> Output <2=> EINT[6] <3=> Reserved
+;// GPF5 <0=> Input <1=> Output <2=> EINT[5] <3=> Reserved
+;// GPF4 <0=> Input <1=> Output <2=> EINT[4] <3=> Reserved
+;// GPF3 <0=> Input <1=> Output <2=> EINT[3] <3=> Reserved
+;// GPF2 <0=> Input <1=> Output <2=> EINT[2] <3=> Reserved
+;// GPF1 <0=> Input <1=> Output <2=> EINT[1] <3=> Reserved
+;// GPF0 <0=> Input <1=> Output <2=> EINT[0] <3=> Reserved
+;//
+;// Port F Pull-up Settings Register (GPFUP)
+;// GPF7 Pull-up Disable
+;// GPF6 Pull-up Disable
+;// GPF5 Pull-up Disable
+;// GPF4 Pull-up Disable
+;// GPF3 Pull-up Disable
+;// GPF2 Pull-up Disable
+;// GPF1 Pull-up Disable
+;// GPF0 Pull-up Disable
+;//
+;//
+GPF_SETUP EQU 0
+GPFCON_Val EQU 0x00000000
+GPFUP_Val EQU 0x00000000
+
+;// Port G Settings
+;// Port G Control Register (GPGCON)
+;// GPG15 <0=> Input <1=> Output <2=> EINT[23] <3=> Reserved
+;// GPG14 <0=> Input <1=> Output <2=> EINT[22] <3=> Reserved
+;// GPG13 <0=> Input <1=> Output <2=> EINT[21] <3=> Reserved
+;// GPG12 <0=> Input <1=> Output <2=> EINT[20] <3=> Reserved
+;// GPG11 <0=> Input <1=> Output <2=> EINT[19] <3=> TCLK[1]
+;// GPG10 <0=> Input <1=> Output <2=> EINT[18] <3=> nCTS1
+;// GPG9 <0=> Input <1=> Output <2=> EINT[17] <3=> nRTS1
+;// GPG8 <0=> Input <1=> Output <2=> EINT[16] <3=> Reserved
+;// GPG7 <0=> Input <1=> Output <2=> EINT[15] <3=> SPICLK1
+;// GPG6 <0=> Input <1=> Output <2=> EINT[14] <3=> SPIMOSI1
+;// GPG5 <0=> Input <1=> Output <2=> EINT[13] <3=> SPIMISO1
+;// GPG4 <0=> Input <1=> Output <2=> EINT[12] <3=> LCD_PWRDN
+;// GPG3 <0=> Input <1=> Output <2=> EINT[11] <3=> nSS1
+;// GPG2 <0=> Input <1=> Output <2=> EINT[10] <3=> nSS0
+;// GPG1 <0=> Input <1=> Output <2=> EINT[9] <3=> Reserved
+;// GPG0 <0=> Input <1=> Output <2=> EINT[8] <3=> Reserved
+;//
+;// Port G Pull-up Settings Register (GPGUP)
+;// GPG15 Pull-up Disable
+;// GPG14 Pull-up Disable
+;// GPG13 Pull-up Disable
+;// GPG12 Pull-up Disable
+;// GPG11 Pull-up Disable
+;// GPG10 Pull-up Disable
+;// GPG9 Pull-up Disable
+;// GPG8 Pull-up Disable
+;// GPG7 Pull-up Disable
+;// GPG6 Pull-up Disable
+;// GPG5 Pull-up Disable
+;// GPG4 Pull-up Disable
+;// GPG3 Pull-up Disable
+;// GPG2 Pull-up Disable
+;// GPG1 Pull-up Disable
+;// GPG0 Pull-up Disable
+;//
+;//
+GPG_SETUP EQU 0
+GPGCON_Val EQU 0x00000000
+GPGUP_Val EQU 0x00000000
+
+;// Port H Settings
+;// Port H Control Register (GPHCON)
+;// GPH10 <0=> Input <1=> Output <2=> CLKOUT1 <3=> Reserved
+;// GPH9 <0=> Input <1=> Output <2=> CLKOUT0 <3=> Reserved
+;// GPH8 <0=> Input <1=> Output <2=> UEXTCLK <3=> Reserved
+;// GPH7 <0=> Input <1=> Output <2=> RXD[2] <3=> nCTS1
+;// GPH6 <0=> Input <1=> Output <2=> TXD[2] <3=> nRTS1
+;// GPH5 <0=> Input <1=> Output <2=> RXD[1] <3=> Reserved
+;// GPH4 <0=> Input <1=> Output <2=> TXD[1] <3=> Reserved
+;// GPH3 <0=> Input <1=> Output <2=> RXD[0] <3=> Reserved
+;// GPH2 <0=> Input <1=> Output <2=> TXD[0] <3=> Reserved
+;// GPH1 <0=> Input <1=> Output <2=> nRTS0 <3=> Reserved
+;// GPH0 <0=> Input <1=> Output <2=> nCTS0 <3=> Reserved
+;//
+;// Port H Pull-up Settings Register (GPHUP)
+;// GPH10 Pull-up Disable
+;// GPH9 Pull-up Disable
+;// GPH8 Pull-up Disable
+;// GPH7 Pull-up Disable
+;// GPH6 Pull-up Disable
+;// GPH5 Pull-up Disable
+;// GPH4 Pull-up Disable
+;// GPH3 Pull-up Disable
+;// GPH2 Pull-up Disable
+;// GPH1 Pull-up Disable
+;// GPH0 Pull-up Disable
+;//
+;//
+GPH_SETUP EQU 0
+GPHCON_Val EQU 0x00000000
+GPHUP_Val EQU 0x00000000
+
+;// Port J Settings
+;// Port J Control Register (GPJCON)
+;// GPJ12 <0=> Input <1=> Output <2=> CAMRESET <3=> Reserved
+;// GPJ11 <0=> Input <1=> Output <2=> CAMCLKOUT <3=> Reserved
+;// GPJ10 <0=> Input <1=> Output <2=> CAMHREF <3=> Reserved
+;// GPJ9 <0=> Input <1=> Output <2=> CAMVSYNC <3=> Reserved
+;// GPJ8 <0=> Input <1=> Output <2=> CAMPCLK <3=> Reserved
+;// GPJ7 <0=> Input <1=> Output <2=> CAMDATA[7] <3=> Reserved
+;// GPJ6 <0=> Input <1=> Output <2=> CAMDATA[6] <3=> Reserved
+;// GPJ5 <0=> Input <1=> Output <2=> CAMDATA[5] <3=> Reserved
+;// GPJ4 <0=> Input <1=> Output <2=> CAMDATA[4] <3=> Reserved
+;// GPJ3 <0=> Input <1=> Output <2=> CAMDATA[3] <3=> Reserved
+;// GPJ2 <0=> Input <1=> Output <2=> CAMDATA[2] <3=> Reserved
+;// GPJ1 <0=> Input <1=> Output <2=> CAMDATA[1] <3=> Reserved
+;// GPJ0 <0=> Input <1=> Output <2=> CAMDATA[0] <3=> Reserved
+;//
+;// Port J Pull-up Settings Register (GPJUP)
+;// GPJ12 Pull-up Disable
+;// GPJ11 Pull-up Disable
+;// GPJ10 Pull-up Disable
+;// GPJ9 Pull-up Disable
+;// GPJ8 Pull-up Disable
+;// GPJ7 Pull-up Disable
+;// GPJ6 Pull-up Disable
+;// GPJ5 Pull-up Disable
+;// GPJ4 Pull-up Disable
+;// GPJ3 Pull-up Disable
+;// GPJ2 Pull-up Disable
+;// GPJ1 Pull-up Disable
+;// GPJ0 Pull-up Disable
+;//
+;//
+GPJ_SETUP EQU 0
+GPJCON_Val EQU 0x00000000
+GPJUP_Val EQU 0x00000000
+
+;// I/O Setup
+
+
+;----------------------- CODE --------------------------------------------------
+
+ PRESERVE8
+
+
+; Area Definition and Entry Point
+; Startup Code must be linked first at Address at which it expects to run.
+
+ AREA RESET, CODE, READONLY
+ ARM
+
+; Exception Vectors
+; Mapped to Address 0.
+; Absolute addressing mode must be used.
+; Dummy Handlers are implemented as infinite loops which can be modified.
+
+ EXPORT Entry_Point
+Entry_Point
+Vectors LDR PC, Reset_Addr
+ LDR PC, Undef_Addr
+ LDR PC, SWI_Addr
+ LDR PC, PAbt_Addr
+ LDR PC, DAbt_Addr
+ NOP
+ LDR PC, IRQ_Addr
+ LDR PC, FIQ_Addr
+
+Reset_Addr DCD Reset_Handler
+Undef_Addr DCD Undef_Handler
+SWI_Addr DCD SWI_Handler
+PAbt_Addr DCD PAbt_Handler
+DAbt_Addr DCD DAbt_Handler
+ DCD 0 ; Reserved Address
+IRQ_Addr DCD IRQ_Handler
+FIQ_Addr DCD FIQ_Handler
+
+Undef_Handler B Undef_Handler
+SWI_Handler B SWI_Handler
+PAbt_Handler B PAbt_Handler
+DAbt_Handler B DAbt_Handler
+FIQ_Handler B FIQ_Handler
+
+
+; Reset Handler
+
+ EXPORT Reset_Handler
+Reset_Handler
+
+
+; Watchdog Setup ---------------------------------------------------------------
+
+ IF WT_SETUP != 0
+ LDR R0, =WT_BASE
+ LDR R1, =WTCON_Val
+ LDR R2, =WTDAT_Val
+ STR R2, [R0, #WTCNT_OFS]
+ STR R2, [R0, #WTDAT_OFS]
+ STR R1, [R0, #WTCON_OFS]
+ ENDIF
+
+
+; Clock Setup ------------------------------------------------------------------
+
+ IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0)
+ LDR R0, =CLOCK_BASE
+ LDR R1, =LOCKTIME_Val
+ STR R1, [R0, #LOCKTIME_OFS]
+ MOV R1, #CLKDIVN_Val
+ STR R1, [R0, #CLKDIVN_OFS]
+ LDR R1, =CAMDIVN_Val
+ STR R1, [R0, #CAMDIVN_OFS]
+ LDR R1, =MPLLCON_Val
+ STR R1, [R0, #MPLLCON_OFS]
+ LDR R1, =UPLLCON_Val
+ STR R1, [R0, #UPLLCON_OFS]
+ MOV R1, #CLKSLOW_Val
+ STR R1, [R0, #CLKSLOW_OFS]
+ LDR R1, =CLKCON_Val
+ STR R1, [R0, #CLKCON_OFS]
+ ENDIF
+
+
+; Memory Controller Setup ------------------------------------------------------
+
+ IF (:LNOT:(:DEF:NO_MC_SETUP)):LAND:(CLOCK_SETUP != 0)
+ LDR R0, =MC_BASE
+ LDR R1, =BWSCON_Val
+ STR R1, [R0, #BWSCON_OFS]
+ LDR R1, =BANKCON0_Val
+ STR R1, [R0, #BANKCON0_OFS]
+ LDR R1, =BANKCON1_Val
+ STR R1, [R0, #BANKCON1_OFS]
+ LDR R1, =BANKCON2_Val
+ STR R1, [R0, #BANKCON2_OFS]
+ LDR R1, =BANKCON3_Val
+ STR R1, [R0, #BANKCON3_OFS]
+ LDR R1, =BANKCON4_Val
+ STR R1, [R0, #BANKCON4_OFS]
+ LDR R1, =BANKCON5_Val
+ STR R1, [R0, #BANKCON5_OFS]
+ LDR R1, =BANKCON6_Val
+ STR R1, [R0, #BANKCON6_OFS]
+ LDR R1, =BANKCON7_Val
+ STR R1, [R0, #BANKCON7_OFS]
+ LDR R1, =REFRESH_Val
+ STR R1, [R0, #REFRESH_OFS]
+ MOV R1, #BANKSIZE_Val
+ STR R1, [R0, #BANKSIZE_OFS]
+ MOV R1, #MRSRB6_Val
+ STR R1, [R0, #MRSRB6_OFS]
+ MOV R1, #MRSRB7_Val
+ STR R1, [R0, #MRSRB7_OFS]
+ ENDIF
+
+
+; I/O Pins Setup ---------------------------------------------------------------
+
+ IF (:LNOT:(:DEF:NO_GP_SETUP)):LAND:(GP_SETUP != 0)
+
+ IF GPA_SETUP != 0
+ LDR R0, =GPA_BASE
+ LDR R1, =GPACON_Val
+ STR R1, [R0, #GPCON_OFS]
+ ENDIF
+
+ IF GPB_SETUP != 0
+ LDR R0, =GPB_BASE
+ LDR R1, =GPBCON_Val
+ STR R1, [R0, #GPCON_OFS]
+ LDR R1, =GPBUP_Val
+ STR R1, [R0, #GPUP_OFS]
+ ENDIF
+
+ IF GPC_SETUP != 0
+ LDR R0, =GPC_BASE
+ LDR R1, =GPCCON_Val
+ STR R1, [R0, #GPCON_OFS]
+ LDR R1, =GPCUP_Val
+ STR R1, [R0, #GPUP_OFS]
+ ENDIF
+
+ IF GPD_SETUP != 0
+ LDR R0, =GPD_BASE
+ LDR R1, =GPDCON_Val
+ STR R1, [R0, #GPCON_OFS]
+ LDR R1, =GPDUP_Val
+ STR R1, [R0, #GPUP_OFS]
+ ENDIF
+
+ IF GPE_SETUP != 0
+ LDR R0, =GPE_BASE
+ LDR R1, =GPECON_Val
+ STR R1, [R0, #GPCON_OFS]
+ LDR R1, =GPEUP_Val
+ STR R1, [R0, #GPUP_OFS]
+ ENDIF
+
+ IF GPF_SETUP != 0
+ LDR R0, =GPF_BASE
+ LDR R1, =GPFCON_Val
+ STR R1, [R0, #GPCON_OFS]
+ LDR R1, =GPFUP_Val
+ STR R1, [R0, #GPUP_OFS]
+ ENDIF
+
+ IF GPG_SETUP != 0
+ LDR R0, =GPG_BASE
+ LDR R1, =GPGCON_Val
+ STR R1, [R0, #GPCON_OFS]
+ LDR R1, =GPGUP_Val
+ STR R1, [R0, #GPUP_OFS]
+ ENDIF
+
+ IF GPH_SETUP != 0
+ LDR R0, =GPH_BASE
+ LDR R1, =GPHCON_Val
+ STR R1, [R0, #GPCON_OFS]
+ LDR R1, =GPHUP_Val
+ STR R1, [R0, #GPUP_OFS]
+ ENDIF
+
+ IF GPJ_SETUP != 0
+ LDR R0, =GPJ_BASE
+ LDR R1, =GPJCON_Val
+ STR R1, [R0, #GPCON_OFS]
+ LDR R1, =GPJUP_Val
+ STR R1, [R0, #GPUP_OFS]
+ ENDIF
+
+ ENDIF
+
+
+; Copy Exception Vectors to Internal RAM ---------------------------------------
+
+ IF :DEF:RAM_INTVEC
+ ADR R8, Vectors ; Source
+ LDR R9, =IRAM_BASE ; Destination
+ LDMIA R8!, {R0-R7} ; Load Vectors
+ STMIA R9!, {R0-R7} ; Store Vectors
+ LDMIA R8!, {R0-R7} ; Load Handler Addresses
+ STMIA R9!, {R0-R7} ; Store Handler Addresses
+ ENDIF
+
+
+; Setup Stack for each mode ----------------------------------------------------
+
+ LDR R0, =Stack_Top
+
+; Enter Undefined Instruction Mode and set its Stack Pointer
+ MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #UND_Stack_Size
+
+; Enter Abort Mode and set its Stack Pointer
+ MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #ABT_Stack_Size
+
+; Enter FIQ Mode and set its Stack Pointer
+ MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #FIQ_Stack_Size
+
+; Enter IRQ Mode and set its Stack Pointer
+ MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #IRQ_Stack_Size
+
+; Enter Supervisor Mode and set its Stack Pointer
+ MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #SVC_Stack_Size
+
+; Enter User Mode and set its Stack Pointer
+ MSR CPSR_c, #Mode_USR
+ MOV SP, R0
+ SUB SL, SP, #USR_Stack_Size
+
+; Enter the C code -------------------------------------------------------------
+
+ IMPORT __main
+ LDR R0, =__main
+ BX R0
+
+ IMPORT rt_interrupt_enter
+ IMPORT rt_interrupt_leave
+ IMPORT rt_thread_switch_interrput_flag
+ IMPORT rt_interrupt_from_thread
+ IMPORT rt_interrupt_to_thread
+ IMPORT rt_hw_trap_irq
+
+IRQ_Handler PROC
+ EXPORT IRQ_Handler
+ STMFD sp!, {r0-r12,lr}
+ BL rt_interrupt_enter
+ BL rt_hw_trap_irq
+ BL rt_interrupt_leave
+
+ ; if rt_thread_switch_interrput_flag set, jump to
+ ; rt_hw_context_switch_interrupt_do and don't return
+ LDR r0, =rt_thread_switch_interrput_flag
+ LDR r1, [r0]
+ CMP r1, #1
+ BEQ rt_hw_context_switch_interrupt_do
+
+ LDMFD sp!, {r0-r12,lr}
+ SUBS pc, lr, #4
+ ENDP
+
+; /*
+; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
+; */
+rt_hw_context_switch_interrupt_do PROC
+ EXPORT rt_hw_context_switch_interrupt_do
+ MOV r1, #0 ; clear flag
+ STR r1, [r0]
+
+ LDMFD sp!, {r0-r12,lr}; reload saved registers
+ STMFD sp!, {r0-r3} ; save r0-r3
+ MOV r1, sp
+ ADD sp, sp, #16 ; restore sp
+ SUB r2, lr, #4 ; save old task's pc to r2
+
+ MRS r3, spsr ; get cpsr of interrupt thread
+
+ ; switch to SVC mode and no interrupt
+ MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC
+
+ STMFD sp!, {r2} ; push old task's pc
+ STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
+ MOV r4, r1 ; Special optimised code below
+ MOV r5, r3
+ LDMFD r4!, {r0-r3}
+ STMFD sp!, {r0-r3} ; push old task's r3-r0
+ STMFD sp!, {r5} ; push old task's cpsr
+ MRS r4, spsr
+ STMFD sp!, {r4} ; push old task's spsr
+
+ LDR r4, =rt_interrupt_from_thread
+ LDR r5, [r4]
+ STR sp, [r5] ; store sp in preempted tasks's TCB
+
+ LDR r6, =rt_interrupt_to_thread
+ LDR r6, [r6]
+ LDR sp, [r6] ; get new task's stack pointer
+
+ LDMFD sp!, {r4} ; pop new task's spsr
+ MSR spsr_cxsf, r4
+ LDMFD sp!, {r4} ; pop new task's psr
+ MSR cpsr_cxsf, r4
+
+ LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
+ ENDP
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+; User Initial Stack & Heap
+ AREA |.text|, CODE, READONLY
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + USR_Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDIF
+
+
+ END