From 715cbb7809eab02e125f1e2290c7fb16e5a66668 Mon Sep 17 00:00:00 2001 From: xuzhuoyi Date: Sat, 20 Aug 2016 18:27:07 +0800 Subject: [PATCH] [bsp][stm32f429-disco] Add SDRAM support --- .../Release_Notes.html | 172 ++- .../STM32F4xx_StdPeriph_Driver/inc/misc.h | 26 +- .../inc/stm32f4xx_adc.h | 33 +- .../inc/stm32f4xx_can.h | 26 +- .../inc/stm32f4xx_crc.h | 26 +- .../inc/stm32f4xx_cryp.h | 114 +- .../inc/stm32f4xx_dac.h | 26 +- .../inc/stm32f4xx_dbgmcu.h | 26 +- .../inc/stm32f4xx_dcmi.h | 26 +- .../inc/stm32f4xx_dma.h | 28 +- .../inc/stm32f4xx_dma2d.h | 469 ++++++ .../inc/stm32f4xx_exti.h | 26 +- .../inc/stm32f4xx_flash.h | 318 +++- .../inc/stm32f4xx_fmc.h | 1137 ++++++++++++++ .../inc/stm32f4xx_fsmc.h | 669 -------- .../inc/stm32f4xx_gpio.h | 179 ++- .../inc/stm32f4xx_hash.h | 93 +- .../inc/stm32f4xx_i2c.h | 39 +- .../inc/stm32f4xx_iwdg.h | 26 +- .../inc/stm32f4xx_ltdc.h | 525 +++++++ .../inc/stm32f4xx_pwr.h | 91 +- .../inc/stm32f4xx_rcc.h | 265 +++- .../inc/stm32f4xx_rng.h | 26 +- .../inc/stm32f4xx_rtc.h | 26 +- .../inc/stm32f4xx_sai.h | 611 ++++++++ .../inc/stm32f4xx_sdio.h | 32 +- .../inc/stm32f4xx_spi.h | 48 +- .../inc/stm32f4xx_syscfg.h | 123 +- .../inc/stm32f4xx_tim.h | 26 +- .../inc/stm32f4xx_usart.h | 32 +- .../inc/stm32f4xx_wwdg.h | 26 +- .../STM32F4xx_StdPeriph_Driver/src/misc.c | 26 +- .../src/stm32f4xx_adc.c | 517 ++++--- .../src/stm32f4xx_can.c | 469 +++--- .../src/stm32f4xx_crc.c | 26 +- .../src/stm32f4xx_cryp.c | 594 ++++--- .../src/stm32f4xx_cryp_aes.c | 1133 +++++++++++++- .../src/stm32f4xx_cryp_des.c | 67 +- .../src/stm32f4xx_cryp_tdes.c | 69 +- .../src/stm32f4xx_dac.c | 221 +-- .../src/stm32f4xx_dbgmcu.c | 26 +- .../src/stm32f4xx_dcmi.c | 146 +- .../src/stm32f4xx_dma.c | 474 +++--- .../src/stm32f4xx_dma2d.c | 778 ++++++++++ .../src/stm32f4xx_exti.c | 108 +- .../src/stm32f4xx_flash.c | 836 ++++++++-- .../src/stm32f4xx_fmc.c | 1373 +++++++++++++++++ .../src/stm32f4xx_fsmc.c | 982 ------------ .../src/stm32f4xx_gpio.c | 220 ++- .../src/stm32f4xx_hash.c | 408 ++--- .../src/stm32f4xx_hash_md5.c | 52 +- .../src/stm32f4xx_hash_sha1.c | 52 +- .../src/stm32f4xx_i2c.c | 307 ++-- .../src/stm32f4xx_iwdg.c | 143 +- .../src/stm32f4xx_ltdc.c | 1104 +++++++++++++ .../src/stm32f4xx_pwr.c | 607 +++++--- .../src/stm32f4xx_rcc.c | 673 ++++++-- .../src/stm32f4xx_rng.c | 190 ++- .../src/stm32f4xx_rtc.c | 767 ++++----- .../src/stm32f4xx_sai.c | 1079 +++++++++++++ .../src/stm32f4xx_sdio.c | 281 ++-- .../src/stm32f4xx_spi.c | 620 ++++---- .../src/stm32f4xx_syscfg.c | 107 +- .../src/stm32f4xx_tim.c | 425 ++--- .../src/stm32f4xx_usart.c | 735 ++++----- .../src/stm32f4xx_wwdg.c | 140 +- bsp/stm32f429-disco/applications/sram.c | 60 + bsp/stm32f429-disco/applications/sram.h | 23 + bsp/stm32f429-disco/drivers/SConscript | 2 +- bsp/stm32f429-disco/drivers/board.c | 14 +- bsp/stm32f429-disco/drivers/board.h | 32 +- bsp/stm32f429-disco/drivers/drv_sdram.c | 400 +++++ bsp/stm32f429-disco/drivers/drv_sdram.h | 108 ++ bsp/stm32f429-disco/drivers/gpio.h | 6 + bsp/stm32f429-disco/drivers/stm32f4xx_conf.h | 2 +- 75 files changed, 15597 insertions(+), 6095 deletions(-) create mode 100644 bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h create mode 100644 bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h delete mode 100644 bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h create mode 100644 bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h create mode 100644 bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h create mode 100644 bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c create mode 100644 bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c delete mode 100644 bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c create mode 100644 bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c create mode 100644 bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c create mode 100644 bsp/stm32f429-disco/applications/sram.c create mode 100644 bsp/stm32f429-disco/applications/sram.h create mode 100644 bsp/stm32f429-disco/drivers/drv_sdram.c create mode 100644 bsp/stm32f429-disco/drivers/drv_sdram.h diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/Release_Notes.html b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/Release_Notes.html index b1a3e9789e..636a2731ab 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/Release_Notes.html +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/Release_Notes.html @@ -898,9 +898,9 @@ ul

Release Notes for STM32F4xx Standard - Peripherals Library Drivers (StdPeriph_Driver)

+ Peripherals  Drivers

Copyright - 2011 STMicroelectronics

+ 2013 STMicroelectronics

@@ -916,7 +916,152 @@ ul
  • License

    • STM32F4xx - Standard Peripherals Library Drivers  update History

    V1.0.0 / 30-September-2011

    Main + Standard Peripherals Library Drivers  update History

    V1.3.0 / 08-November-2013

    Main +Changes

    + + + +
    • Add support of STM32F401xExx devices
    • stm32f4xx_gpio.c/h
      • Update + GPIOSpeed_TypeDef structure’s fields name to be in line with GPIO out + speed definition in the product Reference Manual
      • Add + a legacy defines to keep compatibility with previous version
    • stm32f4xx_flash.c/h
      • File’s header comments: update + description of the maximum AHB frequency vs. voltage scaling + configuration
    +

    V1.2.1 / 19-September-2013

    +

    Main +Changes

    + +
    • + +

      stm32f4xx_pwr.c/.h 

      • + +

        Add +new function to configure the Under-Drive STOP Mode : PWR_EnterUnderDriveSTOPMode(uint32_t +PWR_Regulator, uint8_t PWR_STOPEntry) only used in case of STM32F427/437/429/439xx devices.

        +

    V1.2.0 / 11-September-2013

    +

    Main +Changes

    + +
    • + +

      Add +support of STM32F429/439xx and STM32F401xCxx devices

    • Update definition of STM32F427/437xx devices : extension +of the features to include system clock up to 180MHz, dual bank Flash, reduced +STOP Mode current, SAI, PCROP, SDRAM and DMA2D
    • Add drivers for new +peripherals of STM32F4xx STM32F427/437xx and STM32F429/439xx devices: +
      • stm32f4xx_dma2d.h/.c +
      • stm32f4xx_fmc.h/.c +
      • stm32f4xx_ltdc.h/.c +
      • stm32f4xx_sai.h/.c
    • + +

      stm32f4xx_adc.c/.h 

      • Update +the Temperature sensor channel for STM32F427/STM32F437x/STM32F429x/STM32F439x +devices from Channel 16 to Channel 18
      • + + + +

        Add +a note in ADC_VBATCmd() header function to inform that the Voltage measured is +VBAT/2 in case of STM3240xxx/41xxx and VBAT/4 in case of STM32F42xxx/43xxx.

      • In +ADC_GetSoftwareStartConvStatus() function, replace "ADC_CR2_JSWSTART" +by "ADC_CR2_SWSTART"

    • stm32f4xx_flash.c/.h
      • Update +the header file descriptioon, add the table of number of wait states +according to system frequency selected for all STM32F4xx family devices
      • Update FLASH_EraseAllSectors() function to support the erase for all sectors within Bank1 and Bank2 in case of STM32F42/43xxx devices
      • Add new FLASH Latency values: FLASH_Latency_8, FLASH_Latency_9, FLASH_Latency_10, FLASH_Latency_11, FLASH_Latency_12, FLASH_Latency_13, FLASH_Latency_14, FLASH_Latency_15.
      • Add new flag error in FLASH_Status structure: " FLASH_ERROR_RD"
      • Add new functions: 
        • FLASH_EraseAllBank1Sectors(): mass erase in bank 1 (Half mass erase)
        • FLASH_EraseAllBank2Sectors(): mass erase in Bank 2 (Half mass erase)
        • FLASH_OB_BootConfig(): configure Dual bank boot mode
        • FLASH_OB_PCROPSelectionConfig(): select PCROP feature
        • FLASH_OB_WRP1Config(): configure write protection from Sector 12 to sector 23
        • FLASH_OB_PCROPConfig(): configure PC read/write protection from Sector 0 to sector 11
        • FLASH_OB_PCROP1Config(): configure PC read/write protection from Sector12 to sector23
        • FLASH_OB_GetWRP1(): Read the write protected sectors from 12 to 23
        • FLASH_OB_GetPCROP(): Read the PC read/write protected sectors from 0 to 11
        • FLASH_OB_GetPCROP1(): Read the PC read/write protected sectors from 12 to 23
    • stm32f4xx_gpio.c/.h
      • Update GPIO_DeInit() function : Add GPIOJ, GPIOK clock reset/enable
      • Add a new alternate function for I2C2 and I2C3 :
        • #define +GPIO_AF9_I2C2          +((uint8_t)0x09)  /* I2C2 Alternate Function mapping */
        • #define +GPIO_AF9_I2C3          +((uint8_t)0x09)  /* I2C3 Alternate Function mapping */
      • Update all functions header +comments.
    • stm32f4xx_rcc.c/.h
      • Add new definitions for new +peripherals: SAI1, LTDC, FMC
      • Add a new parameter in RCC_PLLI2SConfig() function : PLLI2SQ to specifies the division factor for SAI1 clock
      • Add new functions: 
        • RCC_PLLSAIConfig(), RCC_PLLSAICmd(): PLL SAI Clock configuration
        • Add new function RCC_SAICLKConfig(): SAI clock division factors configuration
        • RCC_LCDCLKConfig(): LCD clock division factors configuration
    • stm32l1xx_syscfg.c/.h
      • Add new SYSCFG port sources configurations : EXTI_PortSourceGPIOJ, EXTI_PortSourceGPIOK +
      • Add new function SYSCFG_MemorySwappingBank(): swap between bank 1 and Bank 2
    • + +

      stm32f4xx_pwr.c/.h + 

      • + + + +

        Add +more details and update comments in functions and groups description

      • + +

        Add the following functions to +configure the Over-drive and Under-drive Modes :

        • PWR_OverDriveCmd()

        • + +

          PWR_OverDriveSWCmd()

        • PWR_UnderDriveCmd()

    V1.1.0 / +11-Janury-2013

    +

    Main +Changes

    +
    • Official release for STM32F427x/437x devices. +
    • stm32f4xx_cryp.c/.h +
      • Update CRYP_Init() function : add the support +for new algorithms (GCM/CCM). +
      • Add new function : CRYP_PhaseConfig() used for new AES-GCM and +AES-CCM algorithms. +
      • CRYP_InitTypeDef structure : update all +structure fields from uint16_t to uint32_t and update all driver functions  +parameters and the correpondant define to be declared with uint32_t type. +
      • Replace the "CRYP_ContextSave->CR_bits9to2" by +"CRYP_ContextSave->CurrentConfig".
    +
    • stm32f4xx_flash.c/.h +
      • Update FLASH sectors numbers "FLASH_Sector_x" with x = +0..23. +
      • Update +FLASH_EraseAllSectors() function to support mass erase +for STM32F427x/437x +devices.
    +
    • stm32f4xx_gpio.c/.h +
      • Add Alternate functions for new peripherals: SPI4, SPI5, SPI6, UART7, +UART8.
      +
      • Update all functions header +comment.
      +
    • stm32f4xx_hash.c/.h +
      • Update HASH_GetDigest() function : add the +HASH_DIGEST structure. +
      • Add new function HASH_AutoStartDigest(). +
      • Update HASH_MsgDigest structure: to support SHA-224 +and SHA-256 modes. +
      •  Update HASH_Context structure. +
      • Update some define using bit definitions already +declared in stm32f4xx.h.
      +
    • stm32f4xx_i2c.c/.h +
      • Add new functions:
      +
        • I2C_AnalogFilterCmd(): enable/disable the +analog I2C filters.
        • I2C_DigitalFilterConfig(): configure the +digital I2C filters.
      +
    • stm32f4xx_pwr.c/.h + +
      • Add new argument +"PWR_Regulator_Voltage_Scale3"  to PWR_MainRegulatorModeConfig() +function to be in line with Reference Manual +description.
    +
    • stm32f4xx_rcc.c/.h +
      • Add new definitions for new +peripherals: SPI4, SPI5, +SPI6, SAI1, UART7, UART8. +
      • Add a new parameter in RCC_PLLI2SConfig() function : PLLI2SQ to specifies the division factor for +SAI1 clock. +
      • Add RCC_TIMCLKPresConfig() function +: TIMER Prescaler +selection. 
      +
    • stm32l1xx_spi.c/.h +
      • Update to support SPI4, SPI5, +SPI6.
      +
      • Update all functions header +comment.
      +
    • stm32l1xx_usart.c/.h +
      • Update to support UART7 and +UART8. +
      • Update all functions header +comment.

    V1.0.2 / 05-March-2012

    +

    Main +Changes

    + +
    • All source files: license disclaimer text update and add link to the License file on ST Internet.
    • stm32f4xx_dcmi.c
      • DCMI_GetFlagStatus() function: fix test condition on RISR register, use if (dcmireg == 0x00) instead of if (dcmireg == 0x01)
    • stm32f4xx_pwr.c
      • PWR_PVDLevelConfig() +function: remove value of the voltage threshold corresponding to each +PVD detection level, user should refer to the electrical +characteristics of the STM32 device datasheet to have the correct +value

    V1.0.1 / 28-December-2011

    Main +Changes

    +
    • All source files: update disclaimer to add reference to the new license agreement
    • stm32f4xx_rtc.c: 
      • In “RTC_FLAGS_MASK” define: add RTC_FLAG_RECALPF and RTC_FLAG_SHPF
      • RTC_DeInit() function: add reset of the following registers: SHIFTR, CALR, ALRMASSR and ALRMBSSR
      • RTC_SetTime() and RTC_SetDate() functions: add test condition on BYPSHAD flag before to test RSF flag (when Bypass mode is enabled, the RSF bit is never set).

    V1.0.0 / 30-September-2011

    Main Changes

    • First official release for STM32F40x/41x devices
    • stm32f4xx_rtc.c: remove useless code from RTC_GetDate() function
    • stm32f4xx_rcc.c, stm32f4xx_spi.c, stm32f4xx_wwdg.c and stm32f4xx_syscfg.c: driver's comments update

    V1.0.0RC2 / 26-September-2011

    Main Changes

    @@ -924,22 +1069,19 @@ Changes

    Changes

    License

    -

    The enclosed firmware and all the related documentation are - not covered by a License Agreement, if you need such License you can - contact your local STMicroelectronics office.

    -

    THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING - CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR - THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE - FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY - CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY - CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH - THEIR PRODUCTS.

    -

     

    + + +

    Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:

           http://www.st.com/software_license_agreement_liberty_v2

    Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License.

    For - complete documentation on STM32(CORTEX M3) 32-Bit + complete documentation on STM32 Microcontrollers visit www.st.com/STM32

    diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h index cedbd01468..5264ea9cf4 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file misc.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the miscellaneous * firmware library functions (add-on to CMSIS functions). ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -169,4 +175,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h index b9d9d09048..12ef44e088 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_adc.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the ADC firmware * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -319,7 +325,14 @@ typedef struct #define ADC_Channel_17 ((uint8_t)0x11) #define ADC_Channel_18 ((uint8_t)0x12) +#if defined (STM32F40_41xxx) #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18) +#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx */ + #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) #define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) @@ -640,4 +653,4 @@ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h index 900d50f03c..f06f7b06cb 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_can.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the CAN firmware * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -635,4 +641,4 @@ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h index 9a8c79af0d..8fb059e9dc 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_crc.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the CRC firmware * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -74,4 +80,4 @@ uint8_t CRC_GetIDRegister(void); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h index 0b2572a91e..8689316438 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_cryp.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the Cryptographic * processor(CRYP) firmware library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -46,14 +52,14 @@ */ typedef struct { - uint16_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a + uint32_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a value of @ref CRYP_Algorithm_Direction */ - uint16_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, - AES-CBC, AES-CTR, AES-Key. This parameter can be - a value of @ref CRYP_Algorithm_Mode */ - uint16_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit-string. + uint32_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, + AES-CBC, AES-CTR, AES-Key, AES-GCM and AES-CCM. + This parameter can be a value of @ref CRYP_Algorithm_Mode */ + uint32_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit string. This parameter can be a value of @ref CRYP_Data_Type */ - uint16_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit + uint32_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length. This parameter can be a value of @ref CRYP_Key_Size_for_AES_only */ }CRYP_InitTypeDef; @@ -88,14 +94,14 @@ typedef struct */ typedef struct { - /*!< Configuration */ - uint32_t CR_bits9to2; - /*!< KEY */ + /*!< Current Configuration */ + uint32_t CR_CurrentConfig; + /*!< IV */ uint32_t CRYP_IV0LR; uint32_t CRYP_IV0RR; uint32_t CRYP_IV1LR; uint32_t CRYP_IV1RR; - /*!< IV */ + /*!< KEY */ uint32_t CRYP_K0LR; uint32_t CRYP_K0RR; uint32_t CRYP_K1LR; @@ -104,6 +110,8 @@ typedef struct uint32_t CRYP_K2RR; uint32_t CRYP_K3LR; uint32_t CRYP_K3RR; + uint32_t CRYP_CSGCMCCMR[8]; + uint32_t CRYP_CSGCMR[8]; }CRYP_Context; @@ -130,31 +138,54 @@ typedef struct */ /*!< TDES Modes */ -#define CRYP_AlgoMode_TDES_ECB ((uint16_t)0x0000) -#define CRYP_AlgoMode_TDES_CBC ((uint16_t)0x0008) +#define CRYP_AlgoMode_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_AlgoMode_TDES_CBC ((uint32_t)0x00000008) /*!< DES Modes */ -#define CRYP_AlgoMode_DES_ECB ((uint16_t)0x0010) -#define CRYP_AlgoMode_DES_CBC ((uint16_t)0x0018) +#define CRYP_AlgoMode_DES_ECB ((uint32_t)0x00000010) +#define CRYP_AlgoMode_DES_CBC ((uint32_t)0x00000018) /*!< AES Modes */ -#define CRYP_AlgoMode_AES_ECB ((uint16_t)0x0020) -#define CRYP_AlgoMode_AES_CBC ((uint16_t)0x0028) -#define CRYP_AlgoMode_AES_CTR ((uint16_t)0x0030) -#define CRYP_AlgoMode_AES_Key ((uint16_t)0x0038) +#define CRYP_AlgoMode_AES_ECB ((uint32_t)0x00000020) +#define CRYP_AlgoMode_AES_CBC ((uint32_t)0x00000028) +#define CRYP_AlgoMode_AES_CTR ((uint32_t)0x00000030) +#define CRYP_AlgoMode_AES_Key ((uint32_t)0x00000038) +#define CRYP_AlgoMode_AES_GCM ((uint32_t)0x00080000) +#define CRYP_AlgoMode_AES_CCM ((uint32_t)0x00080008) #define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \ ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \ - ((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \ + ((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || \ ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_Key)) + ((ALGOMODE) == CRYP_AlgoMode_AES_Key) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_CCM)) /** * @} */ - + +/** @defgroup CRYP_Phase + * @{ + */ + +/*!< The phases are valid only for AES-GCM and AES-CCM modes */ +#define CRYP_Phase_Init ((uint32_t)0x00000000) +#define CRYP_Phase_Header CRYP_CR_GCM_CCMPH_0 +#define CRYP_Phase_Payload CRYP_CR_GCM_CCMPH_1 +#define CRYP_Phase_Final CRYP_CR_GCM_CCMPH + +#define IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init) || \ + ((PHASE) == CRYP_Phase_Header) || \ + ((PHASE) == CRYP_Phase_Payload) || \ + ((PHASE) == CRYP_Phase_Final)) + +/** + * @} + */ + /** @defgroup CRYP_Data_Type * @{ */ @@ -260,23 +291,24 @@ void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); void CRYP_Cmd(FunctionalState NewState); - +void CRYP_PhaseConfig(uint32_t CRYP_Phase); +void CRYP_FIFOFlush(void); /* CRYP Data processing functions *********************************************/ void CRYP_DataIn(uint32_t Data); uint32_t CRYP_DataOut(void); -void CRYP_FIFOFlush(void); /* CRYP Context swapping functions ********************************************/ ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore); -/* CRYP's DMA interface function **********************************************/ +/* CRYP DMA interface function ************************************************/ void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState); ITStatus CRYP_GetITStatus(uint8_t CRYP_IT); +FunctionalState CRYP_GetCmdStatus(void); FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG); /* High Level AES functions **************************************************/ @@ -297,6 +329,20 @@ ErrorStatus CRYP_AES_CTR(uint8_t Mode, uint8_t *Input, uint32_t Ilength, uint8_t *Output); +ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16], + uint8_t *Key, uint16_t Keysize, + uint8_t *Input, uint32_t ILength, + uint8_t *Header, uint32_t HLength, + uint8_t *Output, uint8_t *AuthTAG); + +ErrorStatus CRYP_AES_CCM(uint8_t Mode, + uint8_t* Nonce, uint32_t NonceSize, + uint8_t* Key, uint16_t Keysize, + uint8_t* Input, uint32_t ILength, + uint8_t* Header, uint32_t HLength, uint8_t *HBuffer, + uint8_t* Output, + uint8_t* AuthTAG, uint32_t TAGSize); + /* High Level TDES functions **************************************************/ ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], @@ -335,4 +381,4 @@ ErrorStatus CRYP_DES_CBC(uint8_t Mode, * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h index 8d928184ac..cfa10af1e5 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_dac.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the DAC firmware * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -295,4 +301,4 @@ void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h index da913375ed..47535019a8 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h @@ -2,20 +2,26 @@ ****************************************************************************** * @file stm32f4xx_dbgmcu.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the DBGMCU firmware library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -100,4 +106,4 @@ void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h index c2631d618f..707eec792a 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h @@ -2,20 +2,26 @@ ****************************************************************************** * @file stm32f4xx_dcmi.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the DCMI firmware library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -303,4 +309,4 @@ void DCMI_ClearITPendingBit(uint16_t DCMI_IT); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h index a081e3dffc..a2d211d219 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_dma.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the DMA firmware * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -393,7 +399,7 @@ typedef struct #define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ - (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00)) + (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00)) #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ @@ -600,4 +606,4 @@ void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h new file mode 100644 index 0000000000..4bfa2249a2 --- /dev/null +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h @@ -0,0 +1,469 @@ +/** + ****************************************************************************** + * @file stm32f4xx_dma2d.h + * @author MCD Application Team + * @version V1.3.0 + * @date 08-November-2013 + * @brief This file contains all the functions prototypes for the DMA2D firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

    © COPYRIGHT 2013 STMicroelectronics

    + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_DMA2D_H +#define __STM32F4xx_DMA2D_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA2D + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DMA2D Init structure definition + */ + +typedef struct +{ + uint32_t DMA2D_Mode; /*!< configures the DMA2D transfer mode. + This parameter can be one value of @ref DMA2D_MODE */ + + uint32_t DMA2D_CMode; /*!< configures the color format of the output image. + This parameter can be one value of @ref DMA2D_CMODE */ + + uint32_t DMA2D_OutputBlue; /*!< configures the blue value of the output image. + This parameter must range: + - from 0x00 to 0xFF if ARGB8888 color mode is slected + - from 0x00 to 0xFF if RGB888 color mode is slected + - from 0x00 to 0x1F if RGB565 color mode is slected + - from 0x00 to 0x1F if ARGB1555 color mode is slected + - from 0x00 to 0x0F if ARGB4444 color mode is slected */ + + uint32_t DMA2D_OutputGreen; /*!< configures the green value of the output image. + This parameter must range: + - from 0x00 to 0xFF if ARGB8888 color mode is slected + - from 0x00 to 0xFF if RGB888 color mode is slected + - from 0x00 to 0x2F if RGB565 color mode is slected + - from 0x00 to 0x1F if ARGB1555 color mode is slected + - from 0x00 to 0x0F if ARGB4444 color mode is slected */ + + uint32_t DMA2D_OutputRed; /*!< configures the red value of the output image. + This parameter must range: + - from 0x00 to 0xFF if ARGB8888 color mode is slected + - from 0x00 to 0xFF if RGB888 color mode is slected + - from 0x00 to 0x1F if RGB565 color mode is slected + - from 0x00 to 0x1F if ARGB1555 color mode is slected + - from 0x00 to 0x0F if ARGB4444 color mode is slected */ + + uint32_t DMA2D_OutputAlpha; /*!< configures the alpha channel of the output color. + This parameter must range: + - from 0x00 to 0xFF if ARGB8888 color mode is slected + - from 0x00 to 0x01 if ARGB1555 color mode is slected + - from 0x00 to 0x0F if ARGB4444 color mode is slected */ + + uint32_t DMA2D_OutputMemoryAdd; /*!< Specifies the memory address. This parameter + must be range from 0x00000000 to 0xFFFFFFFF. */ + + uint32_t DMA2D_OutputOffset; /*!< Specifies the Offset value. This parameter must be range from + 0x0000 to 0x3FFF. */ + + uint32_t DMA2D_NumberOfLine; /*!< Configures the number of line of the area to be transfered. + This parameter must range from 0x0000 to 0xFFFF */ + + uint32_t DMA2D_PixelPerLine; /*!< Configures the number pixel per line of the area to be transfered. + This parameter must range from 0x0000 to 0x3FFF */ +} DMA2D_InitTypeDef; + + + +typedef struct +{ + uint32_t DMA2D_FGMA; /*!< configures the DMA2D foreground memory address. + This parameter must be range from 0x00000000 to 0xFFFFFFFF. */ + + uint32_t DMA2D_FGO; /*!< configures the DMA2D foreground offset. + This parameter must be range from 0x0000 to 0x3FFF. */ + + uint32_t DMA2D_FGCM; /*!< configures the DMA2D foreground color mode . + This parameter can be one value of @ref DMA2D_FGCM */ + + uint32_t DMA2D_FG_CLUT_CM; /*!< configures the DMA2D foreground CLUT color mode. + This parameter can be one value of @ref DMA2D_FG_CLUT_CM */ + + uint32_t DMA2D_FG_CLUT_SIZE; /*!< configures the DMA2D foreground CLUT size. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t DMA2D_FGPFC_ALPHA_MODE; /*!< configures the DMA2D foreground alpha mode. + This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */ + + uint32_t DMA2D_FGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D foreground alpha value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_FGC_BLUE; /*!< Specifies the DMA2D foreground blue value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_FGC_GREEN; /*!< Specifies the DMA2D foreground green value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_FGC_RED; /*!< Specifies the DMA2D foreground red value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_FGCMAR; /*!< Configures the DMA2D foreground CLUT memory address. + This parameter must range from 0x00000000 to 0xFFFFFFFF. */ +} DMA2D_FG_InitTypeDef; + + +typedef struct +{ + uint32_t DMA2D_BGMA; /*!< configures the DMA2D background memory address. + This parameter must be range from 0x00000000 to 0xFFFFFFFF. */ + + uint32_t DMA2D_BGO; /*!< configures the DMA2D background offset. + This parameter must be range from 0x0000 to 0x3FFF. */ + + uint32_t DMA2D_BGCM; /*!< configures the DMA2D background color mode . + This parameter can be one value of @ref DMA2D_FGCM */ + + uint32_t DMA2D_BG_CLUT_CM; /*!< configures the DMA2D background CLUT color mode. + This parameter can be one value of @ref DMA2D_FG_CLUT_CM */ + + uint32_t DMA2D_BG_CLUT_SIZE; /*!< configures the DMA2D background CLUT size. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t DMA2D_BGPFC_ALPHA_MODE; /*!< configures the DMA2D background alpha mode. + This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */ + + uint32_t DMA2D_BGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D background alpha value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_BGC_BLUE; /*!< Specifies the DMA2D background blue value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_BGC_GREEN; /*!< Specifies the DMA2D background green value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_BGC_RED; /*!< Specifies the DMA2D background red value + must be range from 0x00 to 0xFF. */ + + uint32_t DMA2D_BGCMAR; /*!< Configures the DMA2D background CLUT memory address. + This parameter must range from 0x00000000 to 0xFFFFFFFF. */ +} DMA2D_BG_InitTypeDef; + + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA2D_Exported_Constants + * @{ + */ + +/** @defgroup DMA2D_MODE + * @{ + */ + + +#define DMA2D_M2M ((uint32_t)0x00000000) +#define DMA2D_M2M_PFC ((uint32_t)0x00010000) +#define DMA2D_M2M_BLEND ((uint32_t)0x00020000) +#define DMA2D_R2M ((uint32_t)0x00030000) + +#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ + ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) + + +/** + * @} + */ + +/** @defgroup DMA2D_CMODE + * @{ + */ +#define DMA2D_ARGB8888 ((uint32_t)0x00000000) +#define DMA2D_RGB888 ((uint32_t)0x00000001) +#define DMA2D_RGB565 ((uint32_t)0x00000002) +#define DMA2D_ARGB1555 ((uint32_t)0x00000003) +#define DMA2D_ARGB4444 ((uint32_t)0x00000004) + +#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \ + ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \ + ((MODE_ARGB) == DMA2D_ARGB4444)) + + +/** + * @} + */ + +/** @defgroup DMA2D_OUTPUT_COLOR + * @{ + */ +#define DMA2D_Output_Color ((uint32_t)0x000000FF) + +#define IS_DMA2D_OGREEN(OGREEN) ((OGREEN) <= DMA2D_Output_Color) +#define IS_DMA2D_ORED(ORED) ((ORED) <= DMA2D_Output_Color) +#define IS_DMA2D_OBLUE(OBLUE) ((OBLUE) <= DMA2D_Output_Color) +#define IS_DMA2D_OALPHA(OALPHA) ((OALPHA) <= DMA2D_Output_Color) + +/** + * @} + */ + +/** @defgroup DMA2D_OUTPUT_OFFSET + * @{ + */ +#define DMA2D_OUTPUT_OFFSET ((uint32_t)0x00003FFF) + +#define IS_DMA2D_OUTPUT_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OUTPUT_OFFSET) + + +/** + * @} + */ + +/** @defgroup DMA2D_SIZE + * @{ + */ + +#define DMA2D_pixel ((uint32_t)0x00003FFF) +#define DMA2D_Line ((uint32_t)0x0000FFFF) + +#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_Line) +#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_pixel) + + +/** + * @} + */ + +/** @defgroup DMA2D_OFFSET + * @{ + */ +#define OFFSET ((uint32_t)0x00003FFF) + +#define IS_DMA2D_FGO(FGO) ((FGO) <= OFFSET) + +#define IS_DMA2D_BGO(BGO) ((BGO) <= OFFSET) + +/** + * @} + */ + + +/** @defgroup DMA2D_FGCM + * @{ + */ + +#define CM_ARGB8888 ((uint32_t)0x00000000) +#define CM_RGB888 ((uint32_t)0x00000001) +#define CM_RGB565 ((uint32_t)0x00000002) +#define CM_ARGB1555 ((uint32_t)0x00000003) +#define CM_ARGB4444 ((uint32_t)0x00000004) +#define CM_L8 ((uint32_t)0x00000005) +#define CM_AL44 ((uint32_t)0x00000006) +#define CM_AL88 ((uint32_t)0x00000007) +#define CM_L4 ((uint32_t)0x00000008) +#define CM_A8 ((uint32_t)0x00000009) +#define CM_A4 ((uint32_t)0x0000000A) + +#define IS_DMA2D_FGCM(FGCM) (((FGCM) == CM_ARGB8888) || ((FGCM) == CM_RGB888) || \ + ((FGCM) == CM_RGB565) || ((FGCM) == CM_ARGB1555) || \ + ((FGCM) == CM_ARGB4444) || ((FGCM) == CM_L8) || \ + ((FGCM) == CM_AL44) || ((FGCM) == CM_AL88) || \ + ((FGCM) == CM_L4) || ((FGCM) == CM_A8) || \ + ((FGCM) == CM_A4)) + +#define IS_DMA2D_BGCM(BGCM) (((BGCM) == CM_ARGB8888) || ((BGCM) == CM_RGB888) || \ + ((BGCM) == CM_RGB565) || ((BGCM) == CM_ARGB1555) || \ + ((BGCM) == CM_ARGB4444) || ((BGCM) == CM_L8) || \ + ((BGCM) == CM_AL44) || ((BGCM) == CM_AL88) || \ + ((BGCM) == CM_L4) || ((BGCM) == CM_A8) || \ + ((BGCM) == CM_A4)) + +/** + * @} + */ + +/** @defgroup DMA2D_FG_CLUT_CM + * @{ + */ + +#define CLUT_CM_ARGB8888 ((uint32_t)0x00000000) +#define CLUT_CM_RGB888 ((uint32_t)0x00000001) + +#define IS_DMA2D_FG_CLUT_CM(FG_CLUT_CM) (((FG_CLUT_CM) == CLUT_CM_ARGB8888) || ((FG_CLUT_CM) == CLUT_CM_RGB888)) + +#define IS_DMA2D_BG_CLUT_CM(BG_CLUT_CM) (((BG_CLUT_CM) == CLUT_CM_ARGB8888) || ((BG_CLUT_CM) == CLUT_CM_RGB888)) + +/** + * @} + */ + +/** @defgroup DMA2D_FG_COLOR_VALUE + * @{ + */ + +#define COLOR_VALUE ((uint32_t)0x000000FF) + +#define IS_DMA2D_FG_CLUT_SIZE(FG_CLUT_SIZE) ((FG_CLUT_SIZE) <= COLOR_VALUE) + +#define IS_DMA2D_FG_ALPHA_VALUE(FG_ALPHA_VALUE) ((FG_ALPHA_VALUE) <= COLOR_VALUE) +#define IS_DMA2D_FGC_BLUE(FGC_BLUE) ((FGC_BLUE) <= COLOR_VALUE) +#define IS_DMA2D_FGC_GREEN(FGC_GREEN) ((FGC_GREEN) <= COLOR_VALUE) +#define IS_DMA2D_FGC_RED(FGC_RED) ((FGC_RED) <= COLOR_VALUE) + +#define IS_DMA2D_BG_CLUT_SIZE(BG_CLUT_SIZE) ((BG_CLUT_SIZE) <= COLOR_VALUE) + +#define IS_DMA2D_BG_ALPHA_VALUE(BG_ALPHA_VALUE) ((BG_ALPHA_VALUE) <= COLOR_VALUE) +#define IS_DMA2D_BGC_BLUE(BGC_BLUE) ((BGC_BLUE) <= COLOR_VALUE) +#define IS_DMA2D_BGC_GREEN(BGC_GREEN) ((BGC_GREEN) <= COLOR_VALUE) +#define IS_DMA2D_BGC_RED(BGC_RED) ((BGC_RED) <= COLOR_VALUE) + +/** + * @} + */ + +/** DMA2D_FGPFC_ALPHA_MODE + * @{ + */ + +#define NO_MODIF_ALPHA_VALUE ((uint32_t)0x00000000) +#define REPLACE_ALPHA_VALUE ((uint32_t)0x00000001) +#define COMBINE_ALPHA_VALUE ((uint32_t)0x00000002) + +#define IS_DMA2D_FG_ALPHA_MODE(FG_ALPHA_MODE) (((FG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \ + ((FG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \ + ((FG_ALPHA_MODE) == COMBINE_ALPHA_VALUE)) + +#define IS_DMA2D_BG_ALPHA_MODE(BG_ALPHA_MODE) (((BG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \ + ((BG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \ + ((BG_ALPHA_MODE) == COMBINE_ALPHA_VALUE)) + +/** + * @} + */ + +/** @defgroup DMA2D_Interrupts + * @{ + */ + +#define DMA2D_IT_CE DMA2D_CR_CEIE +#define DMA2D_IT_CTC DMA2D_CR_CTCIE +#define DMA2D_IT_CAE DMA2D_CR_CAEIE +#define DMA2D_IT_TW DMA2D_CR_TWIE +#define DMA2D_IT_TC DMA2D_CR_TCIE +#define DMA2D_IT_TE DMA2D_CR_TEIE + +#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ + ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ + ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) + +/** + * @} + */ + +/** @defgroup DMA2D_Flag + * @{ + */ + +#define DMA2D_FLAG_CE DMA2D_ISR_CEIF +#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF +#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF +#define DMA2D_FLAG_TW DMA2D_ISR_TWIF +#define DMA2D_FLAG_TC DMA2D_ISR_TCIF +#define DMA2D_FLAG_TE DMA2D_ISR_TEIF + + +#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ + ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ + ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) + + +/** + * @} + */ + +/** @defgroup DMA2D_DeadTime + * @{ + */ + +#define DEADTIME ((uint32_t)0x000000FF) + +#define IS_DMA2D_DEAD_TIME(DEAD_TIME) ((DEAD_TIME) <= DEADTIME) + + +#define LINE_WATERMARK DMA2D_LWR_LW + +#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the DMA2D configuration to the default reset state *****/ +void DMA2D_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct); +void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct); +void DMA2D_StartTransfer(void); +void DMA2D_AbortTransfer(void); +void DMA2D_Suspend(FunctionalState NewState); +void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct); +void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct); +void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct); +void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct); +void DMA2D_FGStart(FunctionalState NewState); +void DMA2D_BGStart(FunctionalState NewState); +void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState); +void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig); + +/* Interrupts and flags management functions **********************************/ +void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState); +FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG); +void DMA2D_ClearFlag(uint32_t DMA2D_FLAG); +ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT); +void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_DMA2D_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h index e25f152ae4..78cd9c8d55 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_exti.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the EXTI firmware * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -174,4 +180,4 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h index 458f1d8b83..6d692a196a 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_flash.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the FLASH * firmware library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -46,6 +52,7 @@ typedef enum { FLASH_BUSY = 1, + FLASH_ERROR_RD, FLASH_ERROR_PGS, FLASH_ERROR_PGP, FLASH_ERROR_PGA, @@ -64,23 +71,40 @@ typedef enum /** @defgroup Flash_Latency * @{ */ -#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ -#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ -#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ -#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ -#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ -#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2) || \ - ((LATENCY) == FLASH_Latency_3) || \ - ((LATENCY) == FLASH_Latency_4) || \ - ((LATENCY) == FLASH_Latency_5) || \ - ((LATENCY) == FLASH_Latency_6) || \ - ((LATENCY) == FLASH_Latency_7)) +#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ +#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ +#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ +#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ +#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ +#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ +#define FLASH_Latency_8 ((uint8_t)0x0008) /*!< FLASH Eight Latency cycles */ +#define FLASH_Latency_9 ((uint8_t)0x0009) /*!< FLASH Nine Latency cycles */ +#define FLASH_Latency_10 ((uint8_t)0x000A) /*!< FLASH Ten Latency cycles */ +#define FLASH_Latency_11 ((uint8_t)0x000B) /*!< FLASH Eleven Latency cycles */ +#define FLASH_Latency_12 ((uint8_t)0x000C) /*!< FLASH Twelve Latency cycles */ +#define FLASH_Latency_13 ((uint8_t)0x000D) /*!< FLASH Thirteen Latency cycles */ +#define FLASH_Latency_14 ((uint8_t)0x000E) /*!< FLASH Fourteen Latency cycles */ +#define FLASH_Latency_15 ((uint8_t)0x000F) /*!< FLASH Fifteen Latency cycles */ + + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2) || \ + ((LATENCY) == FLASH_Latency_3) || \ + ((LATENCY) == FLASH_Latency_4) || \ + ((LATENCY) == FLASH_Latency_5) || \ + ((LATENCY) == FLASH_Latency_6) || \ + ((LATENCY) == FLASH_Latency_7) || \ + ((LATENCY) == FLASH_Latency_8) || \ + ((LATENCY) == FLASH_Latency_9) || \ + ((LATENCY) == FLASH_Latency_10) || \ + ((LATENCY) == FLASH_Latency_11) || \ + ((LATENCY) == FLASH_Latency_12) || \ + ((LATENCY) == FLASH_Latency_13) || \ + ((LATENCY) == FLASH_Latency_14) || \ + ((LATENCY) == FLASH_Latency_15)) /** * @} */ @@ -103,27 +127,59 @@ typedef enum /** @defgroup FLASH_Sectors * @{ - */ -#define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */ -#define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */ -#define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */ -#define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */ -#define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */ -#define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */ -#define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */ -#define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */ -#define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */ -#define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */ -#define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */ -#define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */ -#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\ - ((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\ - ((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\ - ((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\ - ((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\ - ((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11)) -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ + */ +#define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */ +#define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */ +#define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */ +#define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */ +#define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */ +#define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */ +#define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */ +#define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */ +#define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */ +#define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */ +#define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */ +#define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */ +#define FLASH_Sector_12 ((uint16_t)0x0080) /*!< Sector Number 12 */ +#define FLASH_Sector_13 ((uint16_t)0x0088) /*!< Sector Number 13 */ +#define FLASH_Sector_14 ((uint16_t)0x0090) /*!< Sector Number 14 */ +#define FLASH_Sector_15 ((uint16_t)0x0098) /*!< Sector Number 15 */ +#define FLASH_Sector_16 ((uint16_t)0x00A0) /*!< Sector Number 16 */ +#define FLASH_Sector_17 ((uint16_t)0x00A8) /*!< Sector Number 17 */ +#define FLASH_Sector_18 ((uint16_t)0x00B0) /*!< Sector Number 18 */ +#define FLASH_Sector_19 ((uint16_t)0x00B8) /*!< Sector Number 19 */ +#define FLASH_Sector_20 ((uint16_t)0x00C0) /*!< Sector Number 20 */ +#define FLASH_Sector_21 ((uint16_t)0x00C8) /*!< Sector Number 21 */ +#define FLASH_Sector_22 ((uint16_t)0x00D0) /*!< Sector Number 22 */ +#define FLASH_Sector_23 ((uint16_t)0x00D8) /*!< Sector Number 23 */ + +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\ + ((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\ + ((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\ + ((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\ + ((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\ + ((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11) ||\ + ((SECTOR) == FLASH_Sector_12) || ((SECTOR) == FLASH_Sector_13) ||\ + ((SECTOR) == FLASH_Sector_14) || ((SECTOR) == FLASH_Sector_15) ||\ + ((SECTOR) == FLASH_Sector_16) || ((SECTOR) == FLASH_Sector_17) ||\ + ((SECTOR) == FLASH_Sector_18) || ((SECTOR) == FLASH_Sector_19) ||\ + ((SECTOR) == FLASH_Sector_20) || ((SECTOR) == FLASH_Sector_21) ||\ + ((SECTOR) == FLASH_Sector_22) || ((SECTOR) == FLASH_Sector_23)) + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x081FFFFF)) ||\ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#if defined (STM32F40_41xxx) +#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ + (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F401xx) +#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0803FFFF)) ||\ + (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) +#endif /* STM32F401xx */ /** * @} */ @@ -131,18 +187,30 @@ typedef enum /** @defgroup Option_Bytes_Write_Protection * @{ */ -#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ -#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ -#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ -#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ -#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ -#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ -#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ -#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ -#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ -#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ -#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ -#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ +#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ +#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ +#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ +#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ +#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ +#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ +#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ +#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ +#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ +#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ +#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ +#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ +#define OB_WRP_Sector_12 ((uint32_t)0x00000001) /*!< Write protection of Sector12 */ +#define OB_WRP_Sector_13 ((uint32_t)0x00000002) /*!< Write protection of Sector13 */ +#define OB_WRP_Sector_14 ((uint32_t)0x00000004) /*!< Write protection of Sector14 */ +#define OB_WRP_Sector_15 ((uint32_t)0x00000008) /*!< Write protection of Sector15 */ +#define OB_WRP_Sector_16 ((uint32_t)0x00000010) /*!< Write protection of Sector16 */ +#define OB_WRP_Sector_17 ((uint32_t)0x00000020) /*!< Write protection of Sector17 */ +#define OB_WRP_Sector_18 ((uint32_t)0x00000040) /*!< Write protection of Sector18 */ +#define OB_WRP_Sector_19 ((uint32_t)0x00000080) /*!< Write protection of Sector19 */ +#define OB_WRP_Sector_20 ((uint32_t)0x00000100) /*!< Write protection of Sector20 */ +#define OB_WRP_Sector_21 ((uint32_t)0x00000200) /*!< Write protection of Sector21 */ +#define OB_WRP_Sector_22 ((uint32_t)0x00000400) /*!< Write protection of Sector22 */ +#define OB_WRP_Sector_23 ((uint32_t)0x00000800) /*!< Write protection of Sector23 */ #define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ #define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) @@ -150,6 +218,50 @@ typedef enum * @} */ +/** @defgroup Selection_Protection_Mode + * @{ + */ +#define OB_PcROP_Disable ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */ +#define OB_PcROP_Enable ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */ +#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable)) +/** + * @} + */ + +/** @defgroup Option_Bytes_PC_ReadWrite_Protection + * @{ + */ +#define OB_PCROP_Sector_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ +#define OB_PCROP_Sector_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ +#define OB_PCROP_Sector_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ +#define OB_PCROP_Sector_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */ +#define OB_PCROP_Sector_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */ +#define OB_PCROP_Sector_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */ +#define OB_PCROP_Sector_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */ +#define OB_PCROP_Sector_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */ +#define OB_PCROP_Sector_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */ +#define OB_PCROP_Sector_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */ +#define OB_PCROP_Sector_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */ +#define OB_PCROP_Sector_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */ +#define OB_PCROP_Sector_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */ +#define OB_PCROP_Sector_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */ +#define OB_PCROP_Sector_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */ +#define OB_PCROP_Sector_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */ +#define OB_PCROP_Sector_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */ +#define OB_PCROP_Sector_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */ +#define OB_PCROP_Sector_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */ +#define OB_PCROP_Sector_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */ +#define OB_PCROP_Sector_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */ +#define OB_PCROP_Sector_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */ +#define OB_PCROP_Sector_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */ +#define OB_PCROP_Sector_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */ +#define OB_PCROP_Sector_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ + +#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) +/** + * @} + */ + /** @defgroup FLASH_Option_Bytes_Read_Protection * @{ */ @@ -207,6 +319,16 @@ typedef enum /** * @} */ + +/** @defgroup FLASH_Dual_Boot + * @{ + */ +#define OB_Dual_BootEnabled ((uint8_t)0x10) /*!< Dual Bank Boot Enable */ +#define OB_Dual_BootDisabled ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */ +#define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled)) +/** + * @} + */ /** @defgroup FLASH_Interrupts * @{ @@ -221,18 +343,19 @@ typedef enum /** @defgroup FLASH_Flags * @{ */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ -#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ +#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ #define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ -#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ -#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ +#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ +#define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */ +#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ - ((FLAG) == FLASH_FLAG_BSY)) + ((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR)) /** * @} */ @@ -262,15 +385,30 @@ typedef enum */ /** - * @brief ACR register byte 0 (Bits[8:0]) base address + * @brief ACR register byte 0 (Bits[7:0]) base address */ #define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) /** - * @brief OPTCR register byte 3 (Bits[24:16]) base address + * @brief OPTCR register byte 0 (Bits[7:0]) base address */ #define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) +/** + * @brief OPTCR register byte 1 (Bits[15:8]) base address + */ #define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) +/** + * @brief OPTCR register byte 2 (Bits[23:16]) base address + */ #define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) +/** + * @brief OPTCR register byte 3 (Bits[31:24]) base address + */ +#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17) + +/** + * @brief OPTCR1 register byte 0 (Bits[7:0]) base address + */ +#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A) /** * @} @@ -288,32 +426,42 @@ void FLASH_InstructionCacheReset(void); void FLASH_DataCacheReset(void); /* FLASH Memory Programming functions *****************************************/ -void FLASH_Unlock(void); -void FLASH_Lock(void); +void FLASH_Unlock(void); +void FLASH_Lock(void); FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); +FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange); +FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange); FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); /* Option Bytes Programming functions *****************************************/ -void FLASH_OB_Unlock(void); -void FLASH_OB_Lock(void); -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); -void FLASH_OB_RDPConfig(uint8_t OB_RDP); -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -void FLASH_OB_BORConfig(uint8_t OB_BOR); +void FLASH_OB_Unlock(void); +void FLASH_OB_Lock(void); +void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); +void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState); +void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP); +void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState); +void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState); +void FLASH_OB_RDPConfig(uint8_t OB_RDP); +void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); +void FLASH_OB_BORConfig(uint8_t OB_BOR); +void FLASH_OB_BootConfig(uint8_t OB_BOOT); FLASH_Status FLASH_OB_Launch(void); -uint8_t FLASH_OB_GetUser(void); -uint16_t FLASH_OB_GetWRP(void); -FlagStatus FLASH_OB_GetRDP(void); -uint8_t FLASH_OB_GetBOR(void); +uint8_t FLASH_OB_GetUser(void); +uint16_t FLASH_OB_GetWRP(void); +uint16_t FLASH_OB_GetWRP1(void); +uint16_t FLASH_OB_GetPCROP(void); +uint16_t FLASH_OB_GetPCROP1(void); +FlagStatus FLASH_OB_GetRDP(void); +uint8_t FLASH_OB_GetBOR(void); /* Interrupts and flags management functions **********************************/ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); FLASH_Status FLASH_GetStatus(void); FLASH_Status FLASH_WaitForLastOperation(void); @@ -331,4 +479,4 @@ FLASH_Status FLASH_WaitForLastOperation(void); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h new file mode 100644 index 0000000000..3f9534e55d --- /dev/null +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h @@ -0,0 +1,1137 @@ +/** + ****************************************************************************** + * @file stm32f4xx_fmc.h + * @author MCD Application Team + * @version V1.3.0 + * @date 08-November-2013 + * @brief This file contains all the functions prototypes for the FMC firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

    © COPYRIGHT 2011 STMicroelectronics

    + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_FMC_H +#define __STM32F4xx_FMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FMC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ +typedef struct +{ + uint32_t FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 1 and 15. + @note This parameter is not used with synchronous NOR Flash memories.*/ + + uint32_t FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 1 and 255. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 15. + @note This parameter is only used for multiplexed NOR Flash memories. */ + + uint32_t FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 15. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The parameter value depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 15 in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FMC_AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FMC_Access_Mode */ +}FMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FMC NOR/SRAM Init structure definition + */ +typedef struct +{ + uint32_t FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FMC_NORSRAM_Bank */ + + uint32_t FMC_DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + + uint32_t FMC_MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FMC_Memory_Type */ + + uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + + uint32_t FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FMC_Burst_Access_Mode */ + + uint32_t FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + + uint32_t FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FMC_Wrap_Mode */ + + uint32_t FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FMC_Wait_Timing */ + + uint32_t FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ + + uint32_t FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal */ + + uint32_t FMC_ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FMC_Extended_Mode */ + + uint32_t FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FMC_AsynchronousWait */ + + uint32_t FMC_WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FMC_Write_Burst */ + + uint32_t FMC_ContinousClock; /*!< Enables or disables the FMC clock output to external memory devices. + This parameter is only enabled through the FMC_BCR1 register, and don't care + through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Continous_Clock */ + + + FMC_NORSRAMTimingInitTypeDef* FMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/ + + FMC_NORSRAMTimingInitTypeDef* FMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/ +}FMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FMC NAND and PCCARD Banks + */ +typedef struct +{ + uint32_t FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 255.*/ + + uint32_t FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0 and 255 */ + + uint32_t FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command de-assertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0 and 255 */ + + uint32_t FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0 and 255 */ +}FMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FMC NAND Init structure definition + */ +typedef struct +{ + uint32_t FMC_Bank; /*!< Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FMC_NAND_Bank */ + + uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FMC_Wait_feature */ + + uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FMC_NAND_Data_Width */ + + uint32_t FMC_ECC; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FMC_ECC */ + + uint32_t FMC_ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FMC_ECC_Page_Size */ + + uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 255. */ + + uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0 and 255 */ + + FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */ + + FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */ +}FMC_NANDInitTypeDef; + +/** + * @brief FMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. + This parameter can be any value of @ref FMC_Wait_feature */ + + uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 255. */ + + uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0 and 255 */ + + + FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */ + + FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */ + + FMC_NAND_PCCARDTimingInitTypeDef* FMC_IOSpaceTimingStruct; /*!< FMC IO Space Timing */ +}FMC_PCCARDInitTypeDef; + +/** + * @brief Timing parameters for FMC SDRAM Banks + */ + +typedef struct +{ + uint32_t FMC_LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and + an active or Refresh command in number of memory clock cycles. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to + issuing the Activate command in number of memory clock cycles. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock + cycles. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command + and the delay between two consecutive Refresh commands in number of + memory clock cycles. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_RPDelay; /*!< Defines the delay between a Precharge Command and an other command + in number of memory clock cycles. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command + in number of memory clock cycles. + This parameter can be a value between 1 and 16. */ + +}FMC_SDRAMTimingInitTypeDef; + +/** + * @brief Command parameters for FMC SDRAM Banks + */ + + +typedef struct +{ + uint32_t FMC_CommandMode; /*!< Defines the command issued to the SDRAM device. + This parameter can be a value of @ref FMC_Command_Mode. */ + + uint32_t FMC_CommandTarget; /*!< Defines which bank (1 or 2) the command will be issued to. + This parameter can be a value of @ref FMC_Command_Target. */ + + uint32_t FMC_AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued + in auto refresh mode. + This parameter can be a value between 1 and 16. */ + + uint32_t FMC_ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ + +}FMC_SDRAMCommandTypeDef; + +/** + * @brief FMC SDRAM Init structure definition + */ + +typedef struct +{ + uint32_t FMC_Bank; /*!< Specifies the SDRAM memory bank that will be used. + This parameter can be a value of @ref FMC_SDRAM_Bank */ + + uint32_t FMC_ColumnBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref FMC_ColumnBits_Number. */ + + uint32_t FMC_RowBitsNumber; /*!< Defines the number of bits of column address.. + This parameter can be a value of @ref FMC_RowBits_Number. */ + + uint32_t FMC_SDMemoryDataWidth; /*!< Defines the memory device width. + This parameter can be a value of @ref FMC_SDMemory_Data_Width. */ + + uint32_t FMC_InternalBankNumber; /*!< Defines the number of bits of column address. + This parameter can be of @ref FMC_InternalBank_Number. */ + + uint32_t FMC_CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. + This parameter can be a value of @ref FMC_CAS_Latency. */ + + uint32_t FMC_WriteProtection; /*!< Enables the SDRAM bank to be accessed in write mode. + This parameter can be a value of @ref FMC_Write_Protection. */ + + uint32_t FMC_SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM Banks and they allow to disable + the clock before changing frequency. + This parameter can be a value of @ref FMC_SDClock_Period. */ + + uint32_t FMC_ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read commands + during the CAS latency and stores data in the Read FIFO. + This parameter can be a value of @ref FMC_Read_Burst. */ + + uint32_t FMC_ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. + This parameter can be a value of @ref FMC_ReadPipe_Delay. */ + + FMC_SDRAMTimingInitTypeDef* FMC_SDRAMTimingStruct; /*!< Timing Parameters for write and read access*/ + +}FMC_SDRAMInitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FMC_Exported_Constants + * @{ + */ + +/** @defgroup FMC_NORSRAM_Bank + * @{ + */ +#define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) + +#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \ + ((BANK) == FMC_Bank1_NORSRAM2) || \ + ((BANK) == FMC_Bank1_NORSRAM3) || \ + ((BANK) == FMC_Bank1_NORSRAM4)) +/** + * @} + */ + +/** @defgroup FMC_NAND_Bank + * @{ + */ +#define FMC_Bank2_NAND ((uint32_t)0x00000010) +#define FMC_Bank3_NAND ((uint32_t)0x00000100) + +#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ + ((BANK) == FMC_Bank3_NAND)) +/** + * @} + */ + +/** @defgroup FMC_PCCARD_Bank + * @{ + */ +#define FMC_Bank4_PCCARD ((uint32_t)0x00001000) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Bank + * @{ + */ +#define FMC_Bank1_SDRAM ((uint32_t)0x00000000) +#define FMC_Bank2_SDRAM ((uint32_t)0x00000001) + +#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_Bank1_SDRAM) || \ + ((BANK) == FMC_Bank2_SDRAM)) + +/** + * @} + */ + + +/** @defgroup FMC_NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FMC_DataAddressMux_Enable ((uint32_t)0x00000002) + +#define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \ + ((MUX) == FMC_DataAddressMux_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Memory_Type + * @{ + */ + +#define FMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FMC_MemoryType_NOR ((uint32_t)0x00000008) + +#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \ + ((MEMORY) == FMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FMC_MemoryType_NOR)) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Data_Width + * @{ + */ + +#define FMC_NORSRAM_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FMC_NORSRAM_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define FMC_NORSRAM_MemoryDataWidth_32b ((uint32_t)0x00000020) + +#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b) || \ + ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b) || \ + ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_32b)) +/** + * @} + */ + +/** @defgroup FMC_Burst_Access_Mode + * @{ + */ + +#define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100) + +#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \ + ((STATE) == FMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FMC_AsynchronousWait + * @{ + */ +#define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000) + +#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \ + ((STATE) == FMC_AsynchronousWait_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal_Polarity + * @{ + */ +#define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200) + +#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FMC_WaitSignalPolarity_High)) +/** + * @} + */ + +/** @defgroup FMC_Wrap_Mode + * @{ + */ +#define FMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FMC_WrapMode_Enable ((uint32_t)0x00000400) + +#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \ + ((MODE) == FMC_WrapMode_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Wait_Timing + * @{ + */ +#define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) + +#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FMC_WaitSignalActive_DuringWaitState)) +/** + * @} + */ + +/** @defgroup FMC_Write_Operation + * @{ + */ +#define FMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FMC_WriteOperation_Enable ((uint32_t)0x00001000) + +#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \ + ((OPERATION) == FMC_WriteOperation_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal + * @{ + */ +#define FMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FMC_WaitSignal_Enable ((uint32_t)0x00002000) + +#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \ + ((SIGNAL) == FMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Extended_Mode + * @{ + */ +#define FMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \ + ((MODE) == FMC_ExtendedMode_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Write_Burst + * @{ + */ + +#define FMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FMC_WriteBurst_Enable ((uint32_t)0x00080000) + +#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \ + ((BURST) == FMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FMC_Continous_Clock + * @{ + */ + +#define FMC_CClock_SyncOnly ((uint32_t)0x00000000) +#define FMC_CClock_SyncAsync ((uint32_t)0x00100000) + +#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \ + ((CCLOCK) == FMC_CClock_SyncAsync)) +/** + * @} + */ + +/** @defgroup FMC_Address_Setup_Time + * @{ + */ +#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15) +/** + * @} + */ + +/** @defgroup FMC_Address_Hold_Time + * @{ + */ +#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15)) +/** + * @} + */ + +/** @defgroup FMC_Data_Setup_Time + * @{ + */ +#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255)) +/** + * @} + */ + +/** @defgroup FMC_Bus_Turn_around_Duration + * @{ + */ +#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15) +/** + * @} + */ + +/** @defgroup FMC_CLK_Division + * @{ + */ +#define IS_FMC_CLK_DIV(DIV) (((DIV) > 0) && ((DIV) <= 15)) +/** + * @} + */ + +/** @defgroup FMC_Data_Latency + * @{ + */ +#define IS_FMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 15) +/** + * @} + */ + +/** @defgroup FMC_Access_Mode + * @{ + */ +#define FMC_AccessMode_A ((uint32_t)0x00000000) +#define FMC_AccessMode_B ((uint32_t)0x10000000) +#define FMC_AccessMode_C ((uint32_t)0x20000000) +#define FMC_AccessMode_D ((uint32_t)0x30000000) + +#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A) || \ + ((MODE) == FMC_AccessMode_B) || \ + ((MODE) == FMC_AccessMode_C) || \ + ((MODE) == FMC_AccessMode_D)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_NAND_PCCARD_Controller + * @{ + */ + +/** @defgroup FMC_Wait_feature + * @{ + */ +#define FMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FMC_Waitfeature_Enable ((uint32_t)0x00000002) + +#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \ + ((FEATURE) == FMC_Waitfeature_Enable)) +/** + * @} + */ + +/** @defgroup FMC_NAND_Data_Width + * @{ + */ +#define FMC_NAND_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FMC_NAND_MemoryDataWidth_16b ((uint32_t)0x00000010) + +#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \ + ((WIDTH) == FMC_NAND_MemoryDataWidth_16b)) +/** + * @} + */ + +/** @defgroup FMC_ECC + * @{ + */ +#define FMC_ECC_Disable ((uint32_t)0x00000000) +#define FMC_ECC_Enable ((uint32_t)0x00000040) + +#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \ + ((STATE) == FMC_ECC_Enable)) +/** + * @} + */ + +/** @defgroup FMC_ECC_Page_Size + * @{ + */ +#define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) + +#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FMC_ECCPageSize_8192Bytes)) +/** + * @} + */ + +/** @defgroup FMC_TCLR_Setup_Time + * @{ + */ +#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** @defgroup FMC_TAR_Setup_Time + * @{ + */ +#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** @defgroup FMC_Setup_Time + * @{ + */ +#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** @defgroup FMC_Wait_Setup_Time + * @{ + */ +#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** @defgroup FMC_Hold_Setup_Time + * @{ + */ +#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** @defgroup FMC_HiZ_Setup_Time + * @{ + */ +#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup FMC_NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FMC_ColumnBits_Number + * @{ + */ +#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) +#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) +#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) +#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) + +#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_ColumnBits_Number_8b) || \ + ((COLUMN) == FMC_ColumnBits_Number_9b) || \ + ((COLUMN) == FMC_ColumnBits_Number_10b) || \ + ((COLUMN) == FMC_ColumnBits_Number_11b)) + +/** + * @} + */ + +/** @defgroup FMC_RowBits_Number + * @{ + */ +#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) +#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) +#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) + +#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_RowBits_Number_11b) || \ + ((ROW) == FMC_RowBits_Number_12b) || \ + ((ROW) == FMC_RowBits_Number_13b)) + +/** + * @} + */ + +/** @defgroup FMC_SDMemory_Data_Width + * @{ + */ +#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) +#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) +#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) + +#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDMemory_Width_8b) || \ + ((WIDTH) == FMC_SDMemory_Width_16b) || \ + ((WIDTH) == FMC_SDMemory_Width_32b)) + +/** + * @} + */ + +/** @defgroup FMC_InternalBank_Number + * @{ + */ +#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) +#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) + +#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_InternalBank_Number_2) || \ + ((NUMBER) == FMC_InternalBank_Number_4)) + +/** + * @} + */ + + +/** @defgroup FMC_CAS_Latency + * @{ + */ +#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) +#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) +#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) + +#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_CAS_Latency_1) || \ + ((LATENCY) == FMC_CAS_Latency_2) || \ + ((LATENCY) == FMC_CAS_Latency_3)) + +/** + * @} + */ + +/** @defgroup FMC_Write_Protection + * @{ + */ +#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) +#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) + +#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_Write_Protection_Disable) || \ + ((WRITE) == FMC_Write_Protection_Enable)) + +/** + * @} + */ + + +/** @defgroup FMC_SDClock_Period + * @{ + */ +#define FMC_SDClock_Disable ((uint32_t)0x00000000) +#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) +#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) + +#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDClock_Disable) || \ + ((PERIOD) == FMC_SDClock_Period_2) || \ + ((PERIOD) == FMC_SDClock_Period_3)) + +/** + * @} + */ + +/** @defgroup FMC_Read_Burst + * @{ + */ +#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) +#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) + +#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_Read_Burst_Disable) || \ + ((RBURST) == FMC_Read_Burst_Enable)) + +/** + * @} + */ + +/** @defgroup FMC_ReadPipe_Delay + * @{ + */ +#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) +#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) +#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) + +#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_ReadPipe_Delay_0) || \ + ((DELAY) == FMC_ReadPipe_Delay_1) || \ + ((DELAY) == FMC_ReadPipe_Delay_2)) + +/** + * @} + */ + +/** @defgroup FMC_LoadToActive_Delay + * @{ + */ +#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_ExitSelfRefresh_Delay + * @{ + */ +#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SelfRefresh_Time + * @{ + */ +#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_RowCycle_Delay + * @{ + */ +#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_Write_Recovery_Time + * @{ + */ +#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_RP_Delay + * @{ + */ +#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_RCD_Delay + * @{ + */ +#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) + +/** + * @} + */ + +/** @defgroup FMC_Command_Mode + * @{ + */ +#define FMC_Command_Mode_normal ((uint32_t)0x00000000) +#define FMC_Command_Mode_CLK_Enabled ((uint32_t)0x00000001) +#define FMC_Command_Mode_PALL ((uint32_t)0x00000002) +#define FMC_Command_Mode_AutoRefresh ((uint32_t)0x00000003) +#define FMC_Command_Mode_LoadMode ((uint32_t)0x00000004) +#define FMC_Command_Mode_Selfrefresh ((uint32_t)0x00000005) +#define FMC_Command_Mode_PowerDown ((uint32_t)0x00000006) + +#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_Command_Mode_normal) || \ + ((COMMAND) == FMC_Command_Mode_CLK_Enabled) || \ + ((COMMAND) == FMC_Command_Mode_PALL) || \ + ((COMMAND) == FMC_Command_Mode_AutoRefresh) || \ + ((COMMAND) == FMC_Command_Mode_LoadMode) || \ + ((COMMAND) == FMC_Command_Mode_Selfrefresh) || \ + ((COMMAND) == FMC_Command_Mode_PowerDown)) + +/** + * @} + */ + +/** @defgroup FMC_Command_Target + * @{ + */ +#define FMC_Command_Target_bank2 ((uint32_t)0x00000008) +#define FMC_Command_Target_bank1 ((uint32_t)0x00000010) +#define FMC_Command_Target_bank1_2 ((uint32_t)0x00000018) + +#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_Command_Target_bank1) || \ + ((TARGET) == FMC_Command_Target_bank2) || \ + ((TARGET) == FMC_Command_Target_bank1_2)) + +/** + * @} + */ + +/** @defgroup FMC_AutoRefresh_Number + * @{ + */ +#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16)) + +/** + * @} + */ + +/** @defgroup FMC_ModeRegister_Definition + * @{ + */ +#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191) + +/** + * @} + */ + + +/** @defgroup FMC_Mode_Status + * @{ + */ +#define FMC_NormalMode_Status ((uint32_t)0x00000000) +#define FMC_SelfRefreshMode_Status FMC_SDSR_MODES1_0 +#define FMC_PowerDownMode_Status FMC_SDSR_MODES1_1 + +#define IS_FMC_MODE_STATUS(STATUS) (((STATUS) == FMC_NormalMode_Status) || \ + ((STATUS) == FMC_SelfRefreshMode_Status) || \ + ((STATUS) == FMC_PowerDownMode_Status)) + + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_Interrupt_sources + * @{ + */ +#define FMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FMC_IT_Level ((uint32_t)0x00000010) +#define FMC_IT_FallingEdge ((uint32_t)0x00000020) +#define FMC_IT_Refresh ((uint32_t)0x00004000) + +#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge) || \ + ((IT) == FMC_IT_Level) || \ + ((IT) == FMC_IT_FallingEdge) || \ + ((IT) == FMC_IT_Refresh)) + +#define IS_FMC_IT_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ + ((BANK) == FMC_Bank3_NAND) || \ + ((BANK) == FMC_Bank4_PCCARD) || \ + ((BANK) == FMC_Bank1_SDRAM) || \ + ((BANK) == FMC_Bank2_SDRAM)) +/** + * @} + */ + +/** @defgroup FMC_Flags + * @{ + */ +#define FMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FMC_FLAG_Level ((uint32_t)0x00000002) +#define FMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define FMC_FLAG_Refresh FMC_SDSR_RE +#define FMC_FLAG_Busy FMC_SDSR_BUSY + +#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RisingEdge) || \ + ((FLAG) == FMC_FLAG_Level) || \ + ((FLAG) == FMC_FLAG_FallingEdge) || \ + ((FLAG) == FMC_FLAG_FEMPT) || \ + ((FLAG) == FMC_FLAG_Refresh) || \ + ((FLAG) == FMC_SDSR_BUSY)) + +#define IS_FMC_GETFLAG_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ + ((BANK) == FMC_Bank3_NAND) || \ + ((BANK) == FMC_Bank4_PCCARD) || \ + ((BANK) == FMC_Bank1_SDRAM) || \ + ((BANK) == FMC_Bank2_SDRAM) || \ + ((BANK) == (FMC_Bank1_SDRAM | FMC_Bank2_SDRAM))) + +#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) + + +/** + * @} + */ + +/** @defgroup FMC_Refresh_count + * @{ + */ +#define IS_FMC_REFRESH_COUNT(COUNT) ((COUNT) <= 8191) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* NOR/SRAM Controller functions **********************************************/ +void FMC_NORSRAMDeInit(uint32_t FMC_Bank); +void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct); +void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct); +void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState); + +/* NAND Controller functions **************************************************/ +void FMC_NANDDeInit(uint32_t FMC_Bank); +void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct); +void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct); +void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState); +void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState); +uint32_t FMC_GetECC(uint32_t FMC_Bank); + +/* PCCARD Controller functions ************************************************/ +void FMC_PCCARDDeInit(void); +void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct); +void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct); +void FMC_PCCARDCmd(FunctionalState NewState); + +/* SDRAM Controller functions ************************************************/ +void FMC_SDRAMDeInit(uint32_t FMC_Bank); +void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct); +void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct); +void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct); +uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank); +void FMC_SetRefreshCount(uint32_t FMC_Count); +void FMC_SetAutoRefresh_Number(uint32_t FMC_Number); +void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState); +FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG); +void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG); +ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT); +void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_FMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h deleted file mode 100644 index 29baf50bf8..0000000000 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h +++ /dev/null @@ -1,669 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_fsmc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 - * @brief This file contains all the functions prototypes for the FSMC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

    © COPYRIGHT 2011 STMicroelectronics

    - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_FSMC_H -#define __STM32F4xx_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FSMC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief Timing parameters For NOR/SRAM Banks - */ -typedef struct -{ - uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 0xF. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 0 and 0xF. - @note This parameter is not used with synchronous NOR Flash memories.*/ - - uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 0 and 0xFF. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 0xF. - @note This parameter is only used for multiplexed NOR Flash memories. */ - - uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 0xF. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The parameter value depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 0xF in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ -}FSMC_NORSRAMTimingInitTypeDef; - -/** - * @brief FSMC NOR/SRAM Init structure definition - */ -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the databus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_Data_Width */ - - uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ - - uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ - - uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ -}FSMC_NORSRAMInitTypeDef; - -/** - * @brief Timing parameters For FSMC NAND and PCCARD Banks - */ -typedef struct -{ - uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 0xFF.*/ - - uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command deassertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - databus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ -}FSMC_NAND_PCCARDTimingInitTypeDef; - -/** - * @brief FSMC NAND Init structure definition - */ -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_Data_Width */ - - uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ - - uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ -}FSMC_NANDInitTypeDef; - -/** - * @brief FSMC PCCARD Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ -}FSMC_PCCARDInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FSMC_Exported_Constants - * @{ - */ - -/** @defgroup FSMC_NORSRAM_Bank - * @{ - */ -#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) -#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) -#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) -#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup FSMC_NAND_Bank - * @{ - */ -#define FSMC_Bank2_NAND ((uint32_t)0x00000010) -#define FSMC_Bank3_NAND ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup FSMC_PCCARD_Bank - * @{ - */ -#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) -/** - * @} - */ - -#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ - ((BANK) == FSMC_Bank1_NORSRAM2) || \ - ((BANK) == FSMC_Bank1_NORSRAM3) || \ - ((BANK) == FSMC_Bank1_NORSRAM4)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND)) - -#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -/** @defgroup FSMC_NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FSMC_Data_Address_Bus_Multiplexing - * @{ - */ - -#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) -#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ - ((MUX) == FSMC_DataAddressMux_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Memory_Type - * @{ - */ - -#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) -#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ - ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ - ((MEMORY) == FSMC_MemoryType_NOR)) -/** - * @} - */ - -/** @defgroup FSMC_Data_Width - * @{ - */ - -#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) -#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ - ((WIDTH) == FSMC_MemoryDataWidth_16b)) -/** - * @} - */ - -/** @defgroup FSMC_Burst_Access_Mode - * @{ - */ - -#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) -#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ - ((STATE) == FSMC_BurstAccessMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_AsynchronousWait - * @{ - */ -#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) -#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) -#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ - ((STATE) == FSMC_AsynchronousWait_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal_Polarity - * @{ - */ -#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) -#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ - ((POLARITY) == FSMC_WaitSignalPolarity_High)) -/** - * @} - */ - -/** @defgroup FSMC_Wrap_Mode - * @{ - */ -#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) -#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ - ((MODE) == FSMC_WrapMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Timing - * @{ - */ -#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ - ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) -/** - * @} - */ - -/** @defgroup FSMC_Write_Operation - * @{ - */ -#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) -#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ - ((OPERATION) == FSMC_WriteOperation_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal - * @{ - */ -#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) -#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ - ((SIGNAL) == FSMC_WaitSignal_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Extended_Mode - * @{ - */ -#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ - ((MODE) == FSMC_ExtendedMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Write_Burst - * @{ - */ - -#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) -#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ - ((BURST) == FSMC_WriteBurst_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time - * @{ - */ -#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time - * @{ - */ -#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Data_Setup_Time - * @{ - */ -#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration - * @{ - */ -#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_CLK_Division - * @{ - */ -#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Data_Latency - * @{ - */ -#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Access_Mode - * @{ - */ -#define FSMC_AccessMode_A ((uint32_t)0x00000000) -#define FSMC_AccessMode_B ((uint32_t)0x10000000) -#define FSMC_AccessMode_C ((uint32_t)0x20000000) -#define FSMC_AccessMode_D ((uint32_t)0x30000000) -#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ - ((MODE) == FSMC_AccessMode_B) || \ - ((MODE) == FSMC_AccessMode_C) || \ - ((MODE) == FSMC_AccessMode_D)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FSMC_NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup FSMC_Wait_feature - * @{ - */ -#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ - ((FEATURE) == FSMC_Waitfeature_Enable)) -/** - * @} - */ - - -/** @defgroup FSMC_ECC - * @{ - */ -#define FSMC_ECC_Disable ((uint32_t)0x00000000) -#define FSMC_ECC_Enable ((uint32_t)0x00000040) -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ - ((STATE) == FSMC_ECC_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_ECC_Page_Size - * @{ - */ -#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_8192Bytes)) -/** - * @} - */ - -/** @defgroup FSMC_TCLR_Setup_Time - * @{ - */ -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_TAR_Setup_Time - * @{ - */ -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Setup_Time - * @{ - */ -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Setup_Time - * @{ - */ -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Hold_Setup_Time - * @{ - */ -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_HiZ_Setup_Time - * @{ - */ -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Interrupt_sources - * @{ - */ -#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FSMC_IT_Level ((uint32_t)0x00000010) -#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) -#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ - ((IT) == FSMC_IT_Level) || \ - ((IT) == FSMC_IT_FallingEdge)) -/** - * @} - */ - -/** @defgroup FSMC_Flags - * @{ - */ -#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FSMC_FLAG_Level ((uint32_t)0x00000002) -#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ - ((FLAG) == FSMC_FLAG_Level) || \ - ((FLAG) == FSMC_FLAG_FallingEdge) || \ - ((FLAG) == FSMC_FLAG_FEMPT)) - -#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* NOR/SRAM Controller functions **********************************************/ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); - -/* NAND Controller functions **************************************************/ -void FSMC_NANDDeInit(uint32_t FSMC_Bank); -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); -uint32_t FSMC_GetECC(uint32_t FSMC_Bank); - -/* PCCARD Controller functions ************************************************/ -void FSMC_PCCARDDeInit(void); -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_PCCARDCmd(FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_FSMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h index 5cbc201c7b..199a20440f 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_gpio.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the GPIO firmware - * library. + * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -49,8 +55,10 @@ ((PERIPH) == GPIOF) || \ ((PERIPH) == GPIOG) || \ ((PERIPH) == GPIOH) || \ - ((PERIPH) == GPIOI)) - + ((PERIPH) == GPIOI) || \ + ((PERIPH) == GPIOJ) || \ + ((PERIPH) == GPIOK)) + /** * @brief GPIO Configuration Mode enumeration */ @@ -80,13 +88,20 @@ typedef enum */ typedef enum { - GPIO_Speed_2MHz = 0x00, /*!< Low speed */ - GPIO_Speed_25MHz = 0x01, /*!< Medium speed */ - GPIO_Speed_50MHz = 0x02, /*!< Fast speed */ - GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */ + GPIO_Low_Speed = 0x00, /*!< Low speed */ + GPIO_Medium_Speed = 0x01, /*!< Medium speed */ + GPIO_Fast_Speed = 0x02, /*!< Fast speed */ + GPIO_High_Speed = 0x03 /*!< High speed */ }GPIOSpeed_TypeDef; -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \ - ((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz)) + +/* Add legacy definition */ +#define GPIO_Speed_2MHz GPIO_Low_Speed +#define GPIO_Speed_25MHz GPIO_Medium_Speed +#define GPIO_Speed_50MHz GPIO_Fast_Speed +#define GPIO_Speed_100MHz GPIO_High_Speed + +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \ + ((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed)) /** * @brief GPIO Configuration PullUp PullDown enumeration @@ -264,38 +279,48 @@ typedef struct /** * @brief AF 5 selection */ -#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + /** * @brief AF 7 selection */ -#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ #define GPIO_AF_I2S3ext ((uint8_t)0x07) /* I2S3ext Alternate Function mapping */ /** * @brief AF 8 selection */ -#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ +#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ /** * @brief AF 9 selection */ -#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ #define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ #define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ #define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx Devices) */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx Devices) */ + /** * @brief AF 10 selection */ @@ -310,38 +335,96 @@ typedef struct /** * @brief AF 12 selection */ -#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ -#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ +#if defined (STM32F40_41xxx) +#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */ +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ /** * @brief AF 13 selection */ #define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ +/** + * @brief AF 14 selection + */ + +#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ + /** * @brief AF 15 selection */ #define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ - ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \ - ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \ - ((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT)) +#if defined (STM32F40_41xxx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ + ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ + ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ + ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ + ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ + ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ + ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ + ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ + ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ + ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ + ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ + ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ + ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ + ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ + ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ + ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC)) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F401xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ + ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ + ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ + ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ + ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ + ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ + ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ + ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ + ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ + ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \ + ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ + ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4)) +#endif /* STM32F401xx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ + ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ + ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ + ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ + ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ + ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ + ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ + ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ + ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ + ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ + ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ + ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ + ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ + ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ + ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ + ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \ + ((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \ + ((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \ + ((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \ + ((AF) == GPIO_AF_LTDC)) +#endif /* STM32F427_437xx || STM32F429_439xx */ + /** * @} */ @@ -403,4 +486,4 @@ void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h index f303c880a6..f3629f9089 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_hash.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the HASH * firmware library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -46,12 +52,12 @@ */ typedef struct { - uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value - of @ref HASH_Algo_Selection */ + uint32_t HASH_AlgoSelection; /*!< SHA-1, SHA-224, SHA-256 or MD5. This parameter + can be a value of @ref HASH_Algo_Selection */ uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value of @ref HASH_processor_Algorithm_Mode */ uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or - bit-string. This parameter can be a value of + bit string. This parameter can be a value of @ref HASH_Data_Type */ uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */ @@ -62,7 +68,9 @@ typedef struct */ typedef struct { - uint32_t Data[5]; /*!< Message digest result : 5x 32bit words for SHA1 or + uint32_t Data[8]; /*!< Message digest result : 8x 32bit wors for SHA-256, + 7x 32bit wors for SHA-224, + 5x 32bit words for SHA-1 or 4x 32bit words for MD5 */ } HASH_MsgDigest; @@ -74,7 +82,7 @@ typedef struct uint32_t HASH_IMR; uint32_t HASH_STR; uint32_t HASH_CR; - uint32_t HASH_CSR[51]; + uint32_t HASH_CSR[54]; }HASH_Context; /* Exported constants --------------------------------------------------------*/ @@ -86,10 +94,14 @@ typedef struct /** @defgroup HASH_Algo_Selection * @{ */ -#define HASH_AlgoSelection_SHA1 ((uint16_t)0x0000) /*!< HASH function is SHA1 */ -#define HASH_AlgoSelection_MD5 ((uint16_t)0x0080) /*!< HASH function is MD5 */ +#define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */ +#define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ +#define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ +#define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ #define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \ + ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \ + ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \ ((ALGOSELECTION) == HASH_AlgoSelection_MD5)) /** * @} @@ -98,8 +110,8 @@ typedef struct /** @defgroup HASH_processor_Algorithm_Mode * @{ */ -#define HASH_AlgoMode_HASH ((uint16_t)0x0000) /*!< Algorithm is HASH */ -#define HASH_AlgoMode_HMAC ((uint16_t)0x0040) /*!< Algorithm is HMAC */ +#define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */ +#define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */ #define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \ ((ALGOMODE) == HASH_AlgoMode_HMAC)) @@ -110,14 +122,14 @@ typedef struct /** @defgroup HASH_Data_Type * @{ */ -#define HASH_DataType_32b ((uint16_t)0x0000) -#define HASH_DataType_16b ((uint16_t)0x0010) -#define HASH_DataType_8b ((uint16_t)0x0020) -#define HASH_DataType_1b ((uint16_t)0x0030) +#define HASH_DataType_32b ((uint32_t)0x0000) /*!< 32-bit data. No swapping */ +#define HASH_DataType_16b HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ +#define HASH_DataType_8b HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ +#define HASH_DataType_1b HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ #define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \ ((DATATYPE) == HASH_DataType_16b)|| \ - ((DATATYPE) == HASH_DataType_8b)|| \ + ((DATATYPE) == HASH_DataType_8b) || \ ((DATATYPE) == HASH_DataType_1b)) /** * @} @@ -127,10 +139,10 @@ typedef struct * @{ */ #define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ -#define HASH_HMACKeyType_LongKey ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */ +#define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */ #define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \ - ((KEYTYPE) == HASH_HMACKeyType_LongKey)) + ((KEYTYPE) == HASH_HMACKeyType_LongKey)) /** * @} */ @@ -147,10 +159,10 @@ typedef struct /** @defgroup HASH_interrupts_definition * @{ */ -#define HASH_IT_DINI ((uint8_t)0x01) /*!< A new block can be entered into the input buffer (DIN)*/ -#define HASH_IT_DCI ((uint8_t)0x02) /*!< Digest calculation complete */ +#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */ +#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */ -#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) +#define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000)) #define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI)) /** @@ -160,11 +172,11 @@ typedef struct /** @defgroup HASH_flags_definition * @{ */ -#define HASH_FLAG_DINIS ((uint16_t)0x0001) /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/ -#define HASH_FLAG_DCIS ((uint16_t)0x0002) /*!< Digest calculation complete */ -#define HASH_FLAG_DMAS ((uint16_t)0x0004) /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ -#define HASH_FLAG_BUSY ((uint16_t)0x0008) /*!< The hash core is Busy : processing a block of data */ -#define HASH_FLAG_DINNE ((uint16_t)0x1000) /*!< DIN not empty : The input buffer contains at least one word of data */ +#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */ +#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ +#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ +#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */ +#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */ #define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \ ((FLAG) == HASH_FLAG_DCIS) || \ @@ -199,21 +211,22 @@ void HASH_DataIn(uint32_t Data); uint8_t HASH_GetInFIFOWordsNbr(void); void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber); void HASH_StartDigest(void); +void HASH_AutoStartDigest(FunctionalState NewState); void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest); /* HASH Context swapping functions ********************************************/ void HASH_SaveContext(HASH_Context* HASH_ContextSave); void HASH_RestoreContext(HASH_Context* HASH_ContextRestore); -/* HASH's DMA interface function **********************************************/ +/* HASH DMA interface function ************************************************/ void HASH_DMACmd(FunctionalState NewState); /* HASH Interrupts and flags management functions *****************************/ -void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState); -FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG); -void HASH_ClearFlag(uint16_t HASH_FLAG); -ITStatus HASH_GetITStatus(uint8_t HASH_IT); -void HASH_ClearITPendingBit(uint8_t HASH_IT); +void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState); +FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG); +void HASH_ClearFlag(uint32_t HASH_FLAG); +ITStatus HASH_GetITStatus(uint32_t HASH_IT); +void HASH_ClearITPendingBit(uint32_t HASH_IT); /* High Level SHA1 functions **************************************************/ ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); @@ -241,4 +254,4 @@ ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h index ea5e36dbb7..9b12d87678 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_i2c.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the I2C firmware * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -76,6 +82,17 @@ typedef struct #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ ((PERIPH) == I2C2) || \ ((PERIPH) == I2C3)) + +/** @defgroup I2C_Digital_Filter + * @{ + */ + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) +/** + * @} + */ + + /** @defgroup I2C_mode * @{ */ @@ -534,6 +551,8 @@ void I2C_DeInit(I2C_TypeDef* I2Cx); void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter); +void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); @@ -689,4 +708,4 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h index fd5deb5afa..1b5c2a1d4e 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_iwdg.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the IWDG * firmware library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -122,4 +128,4 @@ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h new file mode 100644 index 0000000000..acac0ba767 --- /dev/null +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h @@ -0,0 +1,525 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ltdc.h + * @author MCD Application Team + * @version V1.3.0 + * @date 08-November-2013 + * @brief This file contains all the functions prototypes for the LTDC firmware + * library. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

    © COPYRIGHT 2013 STMicroelectronics

    + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LTDC_H +#define __STM32F4xx_LTDC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup LTDC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief LTDC Init structure definition + */ + +typedef struct +{ + uint32_t LTDC_HSPolarity; /*!< configures the horizontal synchronization polarity. + This parameter can be one value of @ref LTDC_HSPolarity */ + + uint32_t LTDC_VSPolarity; /*!< configures the vertical synchronization polarity. + This parameter can be one value of @ref LTDC_VSPolarity */ + + uint32_t LTDC_DEPolarity; /*!< configures the data enable polarity. This parameter can + be one of value of @ref LTDC_DEPolarity */ + + uint32_t LTDC_PCPolarity; /*!< configures the pixel clock polarity. This parameter can + be one of value of @ref LTDC_PCPolarity */ + + uint32_t LTDC_HorizontalSync; /*!< configures the number of Horizontal synchronization + width. This parameter must range from 0x000 to 0xFFF. */ + + uint32_t LTDC_VerticalSync; /*!< configures the number of Vertical synchronization + heigh. This parameter must range from 0x000 to 0x7FF. */ + + uint32_t LTDC_AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. + This parameter must range from LTDC_HorizontalSync to 0xFFF. */ + + uint32_t LTDC_AccumulatedVBP; /*!< configures the accumulated vertical back porch heigh. + This parameter must range from LTDC_VerticalSync to 0x7FF. */ + + uint32_t LTDC_AccumulatedActiveW; /*!< configures the accumulated active width. This parameter + must range from LTDC_AccumulatedHBP to 0xFFF. */ + + uint32_t LTDC_AccumulatedActiveH; /*!< configures the accumulated active heigh. This parameter + must range from LTDC_AccumulatedVBP to 0x7FF. */ + + uint32_t LTDC_TotalWidth; /*!< configures the total width. This parameter + must range from LTDC_AccumulatedActiveW to 0xFFF. */ + + uint32_t LTDC_TotalHeigh; /*!< configures the total heigh. This parameter + must range from LTDC_AccumulatedActiveH to 0x7FF. */ + + uint32_t LTDC_BackgroundRedValue; /*!< configures the background red value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_BackgroundGreenValue; /*!< configures the background green value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_BackgroundBlueValue; /*!< configures the background blue value. + This parameter must range from 0x00 to 0xFF. */ +} LTDC_InitTypeDef; + +/** + * @brief LTDC Layer structure definition + */ + +typedef struct +{ + uint32_t LTDC_HorizontalStart; /*!< Configures the Window Horizontal Start Position. + This parameter must range from 0x000 to 0xFFF. */ + + uint32_t LTDC_HorizontalStop; /*!< Configures the Window Horizontal Stop Position. + This parameter must range from 0x0000 to 0xFFFF. */ + + uint32_t LTDC_VerticalStart; /*!< Configures the Window vertical Start Position. + This parameter must range from 0x000 to 0xFFF. */ + + uint32_t LTDC_VerticalStop; /*!< Configures the Window vaertical Stop Position. + This parameter must range from 0x0000 to 0xFFFF. */ + + uint32_t LTDC_PixelFormat; /*!< Specifies the pixel format. This parameter can be + one of value of @ref LTDC_Pixelformat */ + + uint32_t LTDC_ConstantAlpha; /*!< Specifies the constant alpha used for blending. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_DefaultColorBlue; /*!< Configures the default blue value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_DefaultColorGreen; /*!< Configures the default green value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_DefaultColorRed; /*!< Configures the default red value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_DefaultColorAlpha; /*!< Configures the default alpha value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_BlendingFactor_1; /*!< Select the blending factor 1. This parameter + can be one of value of @ref LTDC_BlendingFactor1 */ + + uint32_t LTDC_BlendingFactor_2; /*!< Select the blending factor 2. This parameter + can be one of value of @ref LTDC_BlendingFactor2 */ + + uint32_t LTDC_CFBStartAdress; /*!< Configures the color frame buffer address */ + + uint32_t LTDC_CFBLineLength; /*!< Configures the color frame buffer line length. + This parameter must range from 0x0000 to 0x1FFF. */ + + uint32_t LTDC_CFBPitch; /*!< Configures the color frame buffer pitch in bytes. + This parameter must range from 0x0000 to 0x1FFF. */ + + uint32_t LTDC_CFBLineNumber; /*!< Specifies the number of line in frame buffer. + This parameter must range from 0x000 to 0x7FF. */ +} LTDC_Layer_InitTypeDef; + +/** + * @brief LTDC Position structure definition + */ + +typedef struct +{ + uint32_t LTDC_POSX; /*!< Current X Position */ + uint32_t LTDC_POSY; /*!< Current Y Position */ +} LTDC_PosTypeDef; + +typedef struct +{ + uint32_t LTDC_BlueWidth; /*!< Blue width */ + uint32_t LTDC_GreenWidth; /*!< Green width */ + uint32_t LTDC_RedWidth; /*!< Red width */ +} LTDC_RGBTypeDef; + +typedef struct +{ + uint32_t LTDC_ColorKeyBlue; /*!< Configures the color key blue value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_ColorKeyGreen; /*!< Configures the color key green value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_ColorKeyRed; /*!< Configures the color key red value. + This parameter must range from 0x00 to 0xFF. */ +} LTDC_ColorKeying_InitTypeDef; + +typedef struct +{ + uint32_t LTDC_CLUTAdress; /*!< Configures the CLUT address. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_BlueValue; /*!< Configures the blue value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_GreenValue; /*!< Configures the green value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LTDC_RedValue; /*!< Configures the red value. + This parameter must range from 0x00 to 0xFF. */ +} LTDC_CLUT_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup LTDC_Exported_Constants + * @} + */ + +/** @defgroup LTDC_SYNC + * @{ + */ + +#define LTDC_HorizontalSYNC ((uint32_t)0x00000FFF) +#define LTDC_VerticalSYNC ((uint32_t)0x000007FF) + +#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HorizontalSYNC) +#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VerticalSYNC) +#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HorizontalSYNC) +#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VerticalSYNC) +#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HorizontalSYNC) +#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VerticalSYNC) +#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HorizontalSYNC) +#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VerticalSYNC) + +/** + * @} + */ + +/** @defgroup LTDC_HSPolarity + * @{ + */ +#define LTDC_HSPolarity_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */ +#define LTDC_HSPolarity_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ + +#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPolarity_AL) || \ + ((HSPOL) == LTDC_HSPolarity_AH)) + +/** + * @} + */ + +/** @defgroup LTDC_VSPolarity + * @{ + */ +#define LTDC_VSPolarity_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */ +#define LTDC_VSPolarity_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ + +#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPolarity_AL) || \ + ((VSPOL) == LTDC_VSPolarity_AH)) + +/** + * @} + */ + +/** @defgroup LTDC_DEPolarity + * @{ + */ +#define LTDC_DEPolarity_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */ +#define LTDC_DEPolarity_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ + +#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_VSPolarity_AL) || \ + ((DEPOL) == LTDC_DEPolarity_AH)) + +/** + * @} + */ + +/** @defgroup LTDC_PCPolarity + * @{ + */ +#define LTDC_PCPolarity_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */ +#define LTDC_PCPolarity_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ + +#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPolarity_IPC) || \ + ((PCPOL) == LTDC_PCPolarity_IIPC)) + +/** + * @} + */ + +/** @defgroup LTDC_Reload + * @{ + */ +#define LTDC_IMReload LTDC_SRCR_IMR /*!< Immediately Reload. */ +#define LTDC_VBReload LTDC_SRCR_VBR /*!< Vertical Blanking Reload. */ + +#define IS_LTDC_RELOAD(RELOAD) (((RELOAD) == LTDC_IMReload) || \ + ((RELOAD) == LTDC_VBReload)) + +/** + * @} + */ + +/** @defgroup LTDC_Back_Color + * @{ + */ + +#define LTDC_Back_Color ((uint32_t)0x000000FF) + +#define IS_LTDC_BackBlueValue(BBLUE) ((BBLUE) <= LTDC_Back_Color) +#define IS_LTDC_BackGreenValue(BGREEN) ((BGREEN) <= LTDC_Back_Color) +#define IS_LTDC_BackRedValue(BRED) ((BRED) <= LTDC_Back_Color) + +/** + * @} + */ + +/** @defgroup LTDC_Position + * @{ + */ + +#define LTDC_POS_CY LTDC_CPSR_CYPOS +#define LTDC_POS_CX LTDC_CPSR_CXPOS + +#define IS_LTDC_GET_POS(POS) (((POS) <= LTDC_POS_CY)) + + +/** + * @} + */ + +/** @defgroup LTDC_LIPosition + * @{ + */ + +#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF) + +/** + * @} + */ + +/** @defgroup LTDC_CurrentStatus + * @{ + */ + +#define LTDC_CD_VDES LTDC_CDSR_VDES +#define LTDC_CD_HDES LTDC_CDSR_HDES +#define LTDC_CD_VSYNC LTDC_CDSR_VSYNCS +#define LTDC_CD_HSYNC LTDC_CDSR_HSYNCS + + +#define IS_LTDC_GET_CD(CD) (((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \ + ((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC)) + + +/** + * @} + */ + +/** @defgroup LTDC_Interrupts + * @{ + */ + +#define LTDC_IT_LI LTDC_IER_LIE +#define LTDC_IT_FU LTDC_IER_FUIE +#define LTDC_IT_TERR LTDC_IER_TERRIE +#define LTDC_IT_RR LTDC_IER_RRIE + +#define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00)) + +/** + * @} + */ + +/** @defgroup LTDC_Flag + * @{ + */ + +#define LTDC_FLAG_LI LTDC_ISR_LIF +#define LTDC_FLAG_FU LTDC_ISR_FUIF +#define LTDC_FLAG_TERR LTDC_ISR_TERRIF +#define LTDC_FLAG_RR LTDC_ISR_RRIF + + +#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \ + ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR)) + +/** + * @} + */ + +/** @defgroup LTDC_Pixelformat + * @{ + */ +#define LTDC_Pixelformat_ARGB8888 ((uint32_t)0x00000000) +#define LTDC_Pixelformat_RGB888 ((uint32_t)0x00000001) +#define LTDC_Pixelformat_RGB565 ((uint32_t)0x00000002) +#define LTDC_Pixelformat_ARGB1555 ((uint32_t)0x00000003) +#define LTDC_Pixelformat_ARGB4444 ((uint32_t)0x00000004) +#define LTDC_Pixelformat_L8 ((uint32_t)0x00000005) +#define LTDC_Pixelformat_AL44 ((uint32_t)0x00000006) +#define LTDC_Pixelformat_AL88 ((uint32_t)0x00000007) + +#define IS_LTDC_Pixelformat(Pixelformat) (((Pixelformat) == LTDC_Pixelformat_ARGB8888) || ((Pixelformat) == LTDC_Pixelformat_RGB888) || \ + ((Pixelformat) == LTDC_Pixelformat_RGB565) || ((Pixelformat) == LTDC_Pixelformat_ARGB1555) || \ + ((Pixelformat) == LTDC_Pixelformat_ARGB4444) || ((Pixelformat) == LTDC_Pixelformat_L8) || \ + ((Pixelformat) == LTDC_Pixelformat_AL44) || ((Pixelformat) == LTDC_Pixelformat_AL88)) + +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor1 + * @{ + */ + +#define LTDC_BlendingFactor1_CA ((uint32_t)0x00000400) +#define LTDC_BlendingFactor1_PAxCA ((uint32_t)0x00000600) + +#define IS_LTDC_BlendingFactor1(BlendingFactor1) (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA)) + +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor2 + * @{ + */ + +#define LTDC_BlendingFactor2_CA ((uint32_t)0x00000005) +#define LTDC_BlendingFactor2_PAxCA ((uint32_t)0x00000007) + +#define IS_LTDC_BlendingFactor2(BlendingFactor2) (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA)) + + +/** + * @} + */ + + +/** @defgroup LTDC_LAYER_Config + * @{ + */ + +#define LTDC_STOPPosition ((uint32_t)0x0000FFFF) +#define LTDC_STARTPosition ((uint32_t)0x00000FFF) + +#define LTDC_DefaultColorConfig ((uint32_t)0x000000FF) +#define LTDC_ColorFrameBuffer ((uint32_t)0x00001FFF) +#define LTDC_LineNumber ((uint32_t)0x000007FF) + +#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPosition) +#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPosition) +#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPosition) +#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPosition) + +#define IS_LTDC_DEFAULTCOLOR(DEFAULTCOLOR) ((DEFAULTCOLOR) <= LTDC_DefaultColorConfig) + +#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_ColorFrameBuffer) +#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_ColorFrameBuffer) + +#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LineNumber) + + + +/** + * @} + */ + +/** @defgroup LTDC_colorkeying_Config + * @{ + */ + +#define LTDC_colorkeyingConfig ((uint32_t)0x000000FF) + +#define IS_LTDC_CKEYING(CKEYING) ((CKEYING) <= LTDC_colorkeyingConfig) + + +/** + * @} + */ + +/** @defgroup LTDC_CLUT_Config + * @{ + */ + +#define LTDC_CLUTWR ((uint32_t)0x000000FF) + +#define IS_LTDC_CLUTWR(CLUTWR) ((CLUTWR) <= LTDC_CLUTWR) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the LTDC configuration to the default reset state *****/ +void LTDC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct); +void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct); +void LTDC_Cmd(FunctionalState NewState); +void LTDC_DitherCmd(FunctionalState NewState); +LTDC_RGBTypeDef LTDC_GetRGBWidth(void); +void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct); +void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig); +void LTDC_ReloadConfig(uint32_t LTDC_Reload); +void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct); +void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct); +void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState); +LTDC_PosTypeDef LTDC_GetPosStatus(void); +void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct); +FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD); +void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState); +void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct); +void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState); +void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct); +void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct); +void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY); +void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha); +void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address); +void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height); +void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat); + +/* Interrupts and flags management functions **********************************/ +void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState); +FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG); +void LTDC_ClearFlag(uint32_t LTDC_FLAG); +ITStatus LTDC_GetITStatus(uint32_t LTDC_IT); +void LTDC_ClearITPendingBit(uint32_t LTDC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LTDC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h index 8f479841e5..690cd9a63f 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_pwr.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the PWR firmware * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -49,7 +55,6 @@ /** @defgroup PWR_PVD_detection_level * @{ */ - #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 @@ -71,31 +76,52 @@ /** @defgroup PWR_Regulator_state_in_STOP_mode * @{ */ +#define PWR_MainRegulator_ON ((uint32_t)0x00000000) +#define PWR_LowPowerRegulator_ON PWR_CR_LPDS + +/* --- PWR_Legacy ---*/ +#define PWR_Regulator_ON PWR_MainRegulator_ON +#define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \ + ((REGULATOR) == PWR_LowPowerRegulator_ON)) -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower PWR_CR_LPDS -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) /** * @} */ -/** @defgroup PWR_STOP_mode_entry +/** @defgroup PWR_Regulator_state_in_UnderDrive_mode * @{ */ +#define PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS +#define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) +#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \ + ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON)) + +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry + * @{ + */ #define PWR_STOPEntry_WFI ((uint8_t)0x01) #define PWR_STOPEntry_WFE ((uint8_t)0x02) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) +/** + * @} + */ /** @defgroup PWR_Regulator_Voltage_Scale * @{ */ - -#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x00004000) -#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00000000) -#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || ((VOLTAGE) == PWR_Regulator_Voltage_Scale2)) - +#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000) +#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000) +#define PWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000) +#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \ + ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \ + ((VOLTAGE) == PWR_Regulator_Voltage_Scale3)) /** * @} */ @@ -103,26 +129,27 @@ /** @defgroup PWR_Flag * @{ */ - #define PWR_FLAG_WU PWR_CSR_WUF #define PWR_FLAG_SB PWR_CSR_SBF #define PWR_FLAG_PVDO PWR_CSR_PVDO #define PWR_FLAG_BRR PWR_CSR_BRR #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY +#define PWR_FLAG_ODRDY PWR_CSR_ODRDY +#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY +#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY -/** @defgroup PWR_Flag_Legacy - * @{ - */ +/* --- FLAG Legacy ---*/ #define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY -/** - * @} - */ #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \ - ((FLAG) == PWR_FLAG_VOSRDY)) + ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \ + ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY)) + + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_UDRDY)) -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) /** * @} */ @@ -150,12 +177,16 @@ void PWR_WakeUpPinCmd(FunctionalState NewState); /* Main and Backup Regulators configuration functions *************************/ void PWR_BackupRegulatorCmd(FunctionalState NewState); void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage); +void PWR_OverDriveCmd(FunctionalState NewState); +void PWR_OverDriveSWCmd(FunctionalState NewState); +void PWR_UnderDriveCmd(FunctionalState NewState); /* FLASH Power Down configuration functions ***********************************/ void PWR_FlashPowerDownCmd(FunctionalState NewState); /* Low Power modes configuration functions ************************************/ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); void PWR_EnterSTANDBYMode(void); /* Flags management functions *************************************************/ @@ -176,4 +207,4 @@ void PWR_ClearFlag(uint32_t PWR_FLAG); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h index f06b643fc7..7cc3d4d71f 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h @@ -2,20 +2,26 @@ ****************************************************************************** * @file stm32f4xx_rcc.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 - * @brief This file contains all the functions prototypes for the RCC firmware library. + * @version V1.3.0 + * @date 08-November-2013 + * @brief This file contains all the functions prototypes for the RCC firmware library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -42,9 +48,9 @@ typedef struct { uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ }RCC_ClocksTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -78,8 +84,26 @@ typedef struct #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) -/** +#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) +#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) +#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) +#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) + +#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000) +#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000) +#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000) +#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000) +#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\ + ((VALUE) == RCC_PLLSAIDivR_Div4) ||\ + ((VALUE) == RCC_PLLSAIDivR_Div8) ||\ + ((VALUE) == RCC_PLLSAIDivR_Div16)) + +/** * @} */ @@ -140,14 +164,17 @@ typedef struct #define RCC_IT_HSIRDY ((uint8_t)0x04) #define RCC_IT_HSERDY ((uint8_t)0x08) #define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) +#define RCC_IT_PLLSAIRDY ((uint8_t)0x40) #define RCC_IT_CSS ((uint8_t)0x80) -#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) + +#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLLI2SRDY)) -#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) + ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY)) +#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00) + /** * @} */ @@ -245,6 +272,45 @@ typedef struct /** * @} */ + +/** @defgroup RCC_SAI_BlockA_Clock_Source + * @{ + */ +#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000) +#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000) +#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000) + +#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\ + ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\ + ((SOURCE) == RCC_SAIACLKSource_Ext)) +/** + * @} + */ + +/** @defgroup RCC_SAI_BlockB_Clock_Source + * @{ + */ +#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000) +#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000) +#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000) + +#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\ + ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\ + ((SOURCE) == RCC_SAIBCLKSource_Ext)) +/** + * @} + */ + +/** @defgroup RCC_TIM_PRescaler_Selection + * @{ + */ +#define RCC_TIMPrescDesactivated ((uint8_t)0x00) +#define RCC_TIMPrescActivated ((uint8_t)0x01) + +#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated)) +/** + * @} + */ /** @defgroup RCC_AHB1_Peripherals * @{ @@ -257,24 +323,30 @@ typedef struct #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) -#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) +#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) +#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200) +#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) +#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) +#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000) #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) -#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00)) + +#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00)) + /** * @} */ @@ -295,7 +367,14 @@ typedef struct /** @defgroup RCC_AHB3_Peripherals * @{ */ -#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) +#if defined (STM32F40_41xxx) +#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) +#endif /* STM32F427_437xx || STM32F429_439xx */ + #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) /** * @} @@ -327,7 +406,9 @@ typedef struct #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00)) +#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000) +#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000) +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ @@ -345,12 +426,19 @@ typedef struct #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00)) +#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) +#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) +#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000) +#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFB8880CC) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFB8886CC) == 0x00) && ((PERIPH) != 0x00)) + /** * @} */ @@ -406,6 +494,7 @@ typedef struct #define RCC_FLAG_HSERDY ((uint8_t)0x31) #define RCC_FLAG_PLLRDY ((uint8_t)0x39) #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) +#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D) #define RCC_FLAG_LSERDY ((uint8_t)0x41) #define RCC_FLAG_LSIRDY ((uint8_t)0x61) #define RCC_FLAG_BORRST ((uint8_t)0x79) @@ -415,13 +504,15 @@ typedef struct #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) -#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ - ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ - ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ - ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ - ((FLAG) == RCC_FLAG_PLLI2SRDY)) + +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ + ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ + ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)) + #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) /** * @} @@ -438,60 +529,74 @@ typedef struct void RCC_DeInit(void); /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ -void RCC_HSEConfig(uint8_t RCC_HSE); +void RCC_HSEConfig(uint8_t RCC_HSE); ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); +void RCC_PLLCmd(FunctionalState NewState); + +#if defined (STM32F40_41xxx) || defined (STM32F401xx) +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); +#endif /* STM32F40_41xxx || STM32F401xx */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); -void RCC_PLLI2SCmd(FunctionalState NewState); +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR); +#endif /* STM32F41_43xxx */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); +void RCC_PLLI2SCmd(FunctionalState NewState); +void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR); +void RCC_PLLSAICmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); +void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); /* System, AHB and APB busses clocks configuration functions ******************/ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); /* Peripheral clocks configuration functions **********************************/ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); - -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); +void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ); +void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ); +void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); +void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); +void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR); +void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler); + +void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); #ifdef __cplusplus } @@ -507,4 +612,4 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h index 5a080a3b65..a364796bb0 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_rng.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the Random * Number Generator(RNG) firmware library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -111,4 +117,4 @@ void RNG_ClearITPendingBit(uint8_t RNG_IT); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h index d5e5794ccc..78fb560876 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_rtc.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the RTC firmware * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -872,4 +878,4 @@ void RTC_ClearITPendingBit(uint32_t RTC_IT); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h new file mode 100644 index 0000000000..b8f48512cc --- /dev/null +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h @@ -0,0 +1,611 @@ +/** + ****************************************************************************** + * @file stm32f4xx_sai.h + * @author MCD Application Team + * @version V1.3.0 + * @date 08-November-2013 + * @brief This file contains all the functions prototypes for the SAI + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_SAI_H +#define __STM32F4xx_SAI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SAI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief SAI Block Init structure definition + */ + +typedef struct +{ + uint32_t SAI_AudioMode; /*!< Specifies the SAI Block Audio Mode. + This parameter can be a value of @ref SAI_Block_Mode */ + + uint32_t SAI_Protocol; /*!< Specifies the SAI Block Protocol. + This parameter can be a value of @ref SAI_Block_Protocol */ + + uint32_t SAI_DataSize; /*!< Specifies the SAI Block data size. + This parameter can be a value of @ref SAI_Block_Data_Size + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission + @note this value has no meaning when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. + This parameter can be a value of @ref SAI_Block_Clock_Strobing */ + + uint32_t SAI_Synchro; /*!< Specifies SAI Block synchronization + This parameter can be a value of @ref SAI_Block_Synchronization */ + + uint32_t SAI_OUTDRIV; /*!< Specifies when SAI Block outputs are driven. + This parameter can be a value of @ref SAI_Block_Output_Drive + @note this value has to be set before enabling the audio block + but after the audio block configuration. */ + + uint32_t SAI_NoDivider; /*!< Specifies whether Master Clock will be divided or not. + This parameter can be a value of @ref SAI_Block_NoDivider */ + + uint32_t SAI_MasterDivider; /*!< Specifies SAI Block Master Clock Divider. + @note the Master Clock Frequency is calculated accordingly to the + following formula : MCLK_x = SAI_CK_x/(MCKDIV[3:0]*2)*/ + + uint32_t SAI_FIFOThreshold; /*!< Specifies SAI Block FIFO Threshold. + This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ +}SAI_InitTypeDef; + +/** + * @brief SAI Block Frame Init structure definition + */ + +typedef struct +{ + + uint32_t SAI_FrameLength; /*!< Specifies the Frame Length, the number of SCK clocks + for each audio frame. + This parameter must be a number between 8 and 256. + @note If master Clock MCLK_x pin is declared as an output, the frame length + should be Aligned to a number equal to power of 2 in order to keep + in an audio frame, an integer number of MCLK pulses by bit Clock. + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_ActiveFrameLength; /*!< Specifies the Frame synchronization active level length. + This Parameter specifies the length in number of bit clock (SCK + 1) + of the active level of FS signal in audio frame. + This parameter must be a number between 1 and 128. + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_FSDefinition; /*!< Specifies the Frame Synchronization definition. + This parameter can be a value of @ref SAI_Block_FS_Definition + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_FSPolarity; /*!< Specifies the Frame Synchronization Polarity. + This parameter can be a value of @ref SAI_Block_FS_Polarity + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_FSOffset; /*!< Specifies the Frame Synchronization Offset. + This parameter can be a value of @ref SAI_Block_FS_Offset + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + +}SAI_FrameInitTypeDef; + +/** + * @brief SAI Block Slot Init Structure definition + */ + +typedef struct +{ + uint32_t SAI_FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot. + This parameter must be a number between 0 and 24. + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_SlotSize; /*!< Specifies the Slot Size. + This parameter can be a value of @ref SAI_Block_Slot_Size + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_SlotNumber; /*!< Specifies the number of slot in the audio frame. + This parameter must be a number between 1 and 16. + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ + + uint32_t SAI_SlotActive; /*!< Specifies the slots in audio frame that will be activated. + This parameter can be a value of @ ref SAI_Block_Slot_Active + @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ +}SAI_SlotInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SAI_Exported_Constants + * @{ + */ + +#define IS_SAI_PERIPH(PERIPH) ((PERIPH) == SAI1) + +#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \ + ((PERIPH) == SAI1_Block_B)) + + +/** @defgroup SAI_Block_Mode + * @{ + */ +#define SAI_Mode_MasterTx ((uint32_t)0x00000000) +#define SAI_Mode_MasterRx ((uint32_t)0x00000001) +#define SAI_Mode_SlaveTx ((uint32_t)0x00000002) +#define SAI_Mode_SlaveRx ((uint32_t)0x00000003) +#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_Mode_MasterTx) || \ + ((MODE) == SAI_Mode_MasterRx) || \ + ((MODE) == SAI_Mode_SlaveTx) || \ + ((MODE) == SAI_Mode_SlaveRx)) +/** + * @} + */ + +/** @defgroup SAI_Block_Protocol + * @{ + */ + +#define SAI_Free_Protocol ((uint32_t)0x00000000) +#define SAI_SPDIF_Protocol ((uint32_t)SAI_xCR1_PRTCFG_0) +#define SAI_AC97_Protocol ((uint32_t)SAI_xCR1_PRTCFG_1) +#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_Free_Protocol) || \ + ((PROTOCOL) == SAI_SPDIF_Protocol) || \ + ((PROTOCOL) == SAI_AC97_Protocol)) +/** + * @} + */ + +/** @defgroup SAI_Block_Data_Size + * @{ + */ + +#define SAI_DataSize_8b ((uint32_t)0x00000040) +#define SAI_DataSize_10b ((uint32_t)0x00000060) +#define SAI_DataSize_16b ((uint32_t)0x00000080) +#define SAI_DataSize_20b ((uint32_t)0x000000A0) +#define SAI_DataSize_24b ((uint32_t)0x000000C0) +#define SAI_DataSize_32b ((uint32_t)0x000000E0) +#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DataSize_8b) || \ + ((DATASIZE) == SAI_DataSize_10b) || \ + ((DATASIZE) == SAI_DataSize_16b) || \ + ((DATASIZE) == SAI_DataSize_20b) || \ + ((DATASIZE) == SAI_DataSize_24b) || \ + ((DATASIZE) == SAI_DataSize_32b)) +/** + * @} + */ + +/** @defgroup SAI_Block_MSB_LSB_transmission + * @{ + */ + +#define SAI_FirstBit_MSB ((uint32_t)0x00000000) +#define SAI_FirstBit_LSB ((uint32_t)SAI_xCR1_LSBFIRST) +#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FirstBit_MSB) || \ + ((BIT) == SAI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup SAI_Block_Clock_Strobing + * @{ + */ + +#define SAI_ClockStrobing_FallingEdge ((uint32_t)0x00000000) +#define SAI_ClockStrobing_RisingEdge ((uint32_t)SAI_xCR1_CKSTR) +#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_ClockStrobing_FallingEdge) || \ + ((CLOCK) == SAI_ClockStrobing_RisingEdge)) +/** + * @} + */ + +/** @defgroup SAI_Block_Synchronization + * @{ + */ + +#define SAI_Asynchronous ((uint32_t)0x00000000) +#define SAI_Synchronous ((uint32_t)SAI_xCR1_SYNCEN_0) +#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_Synchronous) || \ + ((SYNCHRO) == SAI_Asynchronous)) +/** + * @} + */ + +/** @defgroup SAI_Block_Output_Drive + * @{ + */ + +#define SAI_OutputDrive_Disabled ((uint32_t)0x00000000) +#define SAI_OutputDrive_Enabled ((uint32_t)SAI_xCR1_OUTDRIV) +#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OutputDrive_Disabled) || \ + ((DRIVE) == SAI_OutputDrive_Enabled)) +/** + * @} + */ + + + +/** @defgroup SAI_Block_NoDivider + * @{ + */ + +#define SAI_MasterDivider_Enabled ((uint32_t)0x00000000) +#define SAI_MasterDivider_Disabled ((uint32_t)SAI_xCR1_NODIV) +#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MasterDivider_Enabled) || \ + ((NODIVIDER) == SAI_MasterDivider_Disabled)) +/** + * @} + */ + + +/** @defgroup SAI_Block_Master_Divider + * @{ + */ +#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) + +/** + * @} + */ + +/** @defgroup SAI_Block_Frame_Length + * @{ + */ +#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) + +/** + * @} + */ + +/** @defgroup SAI_Block_Active_FrameLength + * @{ + */ +#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) + +/** + * @} + */ + +/** @defgroup SAI_Block_FS_Definition + * @{ + */ + +#define SAI_FS_StartFrame ((uint32_t)0x00000000) +#define I2S_FS_ChannelIdentification ((uint32_t)SAI_xFRCR_FSDEF) +#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_StartFrame) || \ + ((DEFINITION) == I2S_FS_ChannelIdentification)) +/** + * @} + */ + +/** @defgroup SAI_Block_FS_Polarity + * @{ + */ + +#define SAI_FS_ActiveLow ((uint32_t)0x00000000) +#define SAI_FS_ActiveHigh ((uint32_t)SAI_xFRCR_FSPO) +#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ActiveLow) || \ + ((POLARITY) == SAI_FS_ActiveHigh)) +/** + * @} + */ + +/** @defgroup SAI_Block_FS_Offset + * @{ + */ + +#define SAI_FS_FirstBit ((uint32_t)0x00000000) +#define SAI_FS_BeforeFirstBit ((uint32_t)SAI_xFRCR_FSOFF) +#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FirstBit) || \ + ((OFFSET) == SAI_FS_BeforeFirstBit)) +/** + * @} + */ + +/** @defgroup SAI_Block_Slot_FirstBit_Offset + * @{ + */ +#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) + +/** + * @} + */ + + /** @defgroup SAI_Block_Slot_Size + * @{ + */ +#define SAI_SlotSize_DataSize ((uint32_t)0x00000000) +#define SAI_SlotSize_16b ((uint32_t)SAI_xSLOTR_SLOTSZ_0) +#define SAI_SlotSize_32b ((uint32_t)SAI_xSLOTR_SLOTSZ_1) +#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SlotSize_DataSize) || \ + ((SIZE) == SAI_SlotSize_16b) || \ + ((SIZE) == SAI_SlotSize_32b)) + +/** + * @} + */ + +/** @defgroup SAI_Block_Slot_Number + * @{ + */ +#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) + +/** + * @} + */ + +/** @defgroup SAI_Block_Slot_Active + * @{ + */ +#define SAI_Slot_NotActive ((uint32_t)0x00000000) +#define SAI_SlotActive_0 ((uint32_t)0x00010000) +#define SAI_SlotActive_1 ((uint32_t)0x00020000) +#define SAI_SlotActive_2 ((uint32_t)0x00040000) +#define SAI_SlotActive_3 ((uint32_t)0x00080000) +#define SAI_SlotActive_4 ((uint32_t)0x00100000) +#define SAI_SlotActive_5 ((uint32_t)0x00200000) +#define SAI_SlotActive_6 ((uint32_t)0x00400000) +#define SAI_SlotActive_7 ((uint32_t)0x00800000) +#define SAI_SlotActive_8 ((uint32_t)0x01000000) +#define SAI_SlotActive_9 ((uint32_t)0x02000000) +#define SAI_SlotActive_10 ((uint32_t)0x04000000) +#define SAI_SlotActive_11 ((uint32_t)0x08000000) +#define SAI_SlotActive_12 ((uint32_t)0x10000000) +#define SAI_SlotActive_13 ((uint32_t)0x20000000) +#define SAI_SlotActive_14 ((uint32_t)0x40000000) +#define SAI_SlotActive_15 ((uint32_t)0x80000000) +#define SAI_SlotActive_ALL ((uint32_t)0xFFFF0000) + +#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0) + +/** + * @} + */ + +/** @defgroup SAI_Mono_Streo_Mode + * @{ + */ + +#define SAI_MonoMode ((uint32_t)SAI_xCR1_MONO) +#define SAI_StreoMode ((uint32_t)0x00000000) +#define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MonoMode) ||\ + ((MODE) == SAI_StreoMode)) +/** + * @} + */ + +/** @defgroup SAI_TRIState_Management + * @{ + */ + +#define SAI_Output_NotReleased ((uint32_t)0x00000000) +#define SAI_Output_Released ((uint32_t)SAI_xCR2_TRIS) +#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_Output_NotReleased) ||\ + ((STATE) == SAI_Output_Released)) +/** + * @} + */ + +/** @defgroup SAI_Block_Fifo_Threshold + * @{ + */ + +#define SAI_Threshold_FIFOEmpty ((uint32_t)0x00000000) +#define SAI_FIFOThreshold_1QuarterFull ((uint32_t)0x00000001) +#define SAI_FIFOThreshold_HalfFull ((uint32_t)0x00000002) +#define SAI_FIFOThreshold_3QuartersFull ((uint32_t)0x00000003) +#define SAI_FIFOThreshold_Full ((uint32_t)0x00000004) +#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_Threshold_FIFOEmpty) || \ + ((THRESHOLD) == SAI_FIFOThreshold_1QuarterFull) || \ + ((THRESHOLD) == SAI_FIFOThreshold_HalfFull) || \ + ((THRESHOLD) == SAI_FIFOThreshold_3QuartersFull) || \ + ((THRESHOLD) == SAI_FIFOThreshold_Full)) +/** + * @} + */ + +/** @defgroup SAI_Block_Companding_Mode + * @{ + */ + +#define SAI_NoCompanding ((uint32_t)0x00000000) +#define SAI_ULaw_1CPL_Companding ((uint32_t)0x00008000) +#define SAI_ALaw_1CPL_Companding ((uint32_t)0x0000C000) +#define SAI_ULaw_2CPL_Companding ((uint32_t)0x0000A000) +#define SAI_ALaw_2CPL_Companding ((uint32_t)0x0000E000) +#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NoCompanding) || \ + ((MODE) == SAI_ULaw_1CPL_Companding) || \ + ((MODE) == SAI_ALaw_1CPL_Companding) || \ + ((MODE) == SAI_ULaw_2CPL_Companding) || \ + ((MODE) == SAI_ALaw_2CPL_Companding)) +/** + * @} + */ + +/** @defgroup SAI_Block_Mute_Value + * @{ + */ + +#define SAI_ZeroValue ((uint32_t)0x00000000) +#define SAI_LastSentValue ((uint32_t)SAI_xCR2_MUTEVAL) +#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZeroValue) || \ + ((VALUE) == SAI_LastSentValue)) +/** + * @} + */ + +/** @defgroup SAI_Block_Mute_Frame_Counter + * @{ + */ + +#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63) + +/** + * @} + */ + +/** @defgroup SAI_Block_Interrupts_Definition + * @{ + */ + +#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE) +#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE) +#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE) +#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE) +#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE) +#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE) +#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE) + +#define IS_SAI_BLOCK_CONFIG_IT(IT) (((IT) == SAI_IT_OVRUDR) || \ + ((IT) == SAI_IT_MUTEDET) || \ + ((IT) == SAI_IT_WCKCFG) || \ + ((IT) == SAI_IT_FREQ) || \ + ((IT) == SAI_IT_CNRDY) || \ + ((IT) == SAI_IT_AFSDET) || \ + ((IT) == SAI_IT_LFSDET)) +/** + * @} + */ + +/** @defgroup SAI_Block_Flags_Definition + * @{ + */ + +#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR) +#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET) +#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG) +#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ) +#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY) +#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET) +#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET) + +#define IS_SAI_BLOCK_GET_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \ + ((FLAG) == SAI_FLAG_MUTEDET) || \ + ((FLAG) == SAI_FLAG_WCKCFG) || \ + ((FLAG) == SAI_FLAG_FREQ) || \ + ((FLAG) == SAI_FLAG_CNRDY) || \ + ((FLAG) == SAI_FLAG_AFSDET) || \ + ((FLAG) == SAI_FLAG_LFSDET)) + +#define IS_SAI_BLOCK_CLEAR_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \ + ((FLAG) == SAI_FLAG_MUTEDET) || \ + ((FLAG) == SAI_FLAG_WCKCFG) || \ + ((FLAG) == SAI_FLAG_FREQ) || \ + ((FLAG) == SAI_FLAG_CNRDY) || \ + ((FLAG) == SAI_FLAG_AFSDET) || \ + ((FLAG) == SAI_FLAG_LFSDET)) +/** + * @} + */ + +/** @defgroup SAI_Block_Fifo_Status_Level + * @{ + */ +#define SAI_FIFOStatus_Empty ((uint32_t)0x00000000) +#define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000) +#define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000) +#define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000) +#define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000) +#define SAI_FIFOStatus_Full ((uint32_t)0x00050000) + +#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \ + ((STATUS) == SAI_FIFOStatus_HalfFull) || \ + ((STATUS) == SAI_FIFOStatus_1QuarterFull) || \ + ((STATUS) == SAI_FIFOStatus_3QuartersFull) || \ + ((STATUS) == SAI_FIFOStatus_Full) || \ + ((STATUS) == SAI_FIFOStatus_Empty)) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the SAI configuration to the default reset state *****/ +void SAI_DeInit(SAI_TypeDef* SAIx); + +/* Initialization and Configuration functions *********************************/ +void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct); +void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct); +void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct); +void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct); +void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct); +void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct); + +void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); +void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode); +void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState); +void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode); +void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); +void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue); +void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter); +void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x); + +/* Data transfers functions ***************************************************/ +void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data); +uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x); + +/* DMA transfers management functions *****************************************/ +void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState); +FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); +void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); +ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); +void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); +FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x); +uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_SAI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h index 315703d2d3..47e92fd904 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_sdio.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the SDIO firmware * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -77,7 +83,7 @@ typedef struct uint32_t SDIO_Response; /*!< Specifies the SDIO response type. This parameter can be a value of @ref SDIO_Response_Type */ - uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait for interrupt request is enabled or disabled. This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) @@ -453,8 +459,8 @@ typedef struct * @{ */ -#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000) -#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ ((MODE) == SDIO_ReadWaitMode_DATA2)) /** @@ -527,4 +533,4 @@ void SDIO_ClearITPendingBit(uint32_t SDIO_IT); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h index 3e0d79eb22..e51301f96c 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_spi.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the SPI - * firmware library. + * firmware library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -112,19 +118,25 @@ typedef struct #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ + ((PERIPH) == SPI3) || \ + ((PERIPH) == SPI4) || \ + ((PERIPH) == SPI5) || \ + ((PERIPH) == SPI6)) + +#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3) || \ + ((PERIPH) == SPI4) || \ + ((PERIPH) == SPI5) || \ + ((PERIPH) == SPI6) || \ ((PERIPH) == I2S2ext) || \ ((PERIPH) == I2S3ext)) #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ ((PERIPH) == SPI3)) -#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ +#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3) || \ ((PERIPH) == I2S2ext) || \ ((PERIPH) == I2S3ext)) @@ -534,4 +546,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h index e8505e7a9d..6d223c8b3c 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_syscfg.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the SYSCFG firmware - * library. + * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -58,16 +64,21 @@ #define EXTI_PortSourceGPIOG ((uint8_t)0x06) #define EXTI_PortSourceGPIOH ((uint8_t)0x07) #define EXTI_PortSourceGPIOI ((uint8_t)0x08) - +#define EXTI_PortSourceGPIOJ ((uint8_t)0x09) +#define EXTI_PortSourceGPIOK ((uint8_t)0x0A) + #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOI)) + ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOI) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOK)) + /** * @} */ @@ -92,16 +103,16 @@ #define EXTI_PinSource13 ((uint8_t)0x0D) #define EXTI_PinSource14 ((uint8_t)0x0E) #define EXTI_PinSource15 ((uint8_t)0x0F) -#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ - ((PINSOURCE) == EXTI_PinSource1) || \ - ((PINSOURCE) == EXTI_PinSource2) || \ - ((PINSOURCE) == EXTI_PinSource3) || \ - ((PINSOURCE) == EXTI_PinSource4) || \ - ((PINSOURCE) == EXTI_PinSource5) || \ - ((PINSOURCE) == EXTI_PinSource6) || \ - ((PINSOURCE) == EXTI_PinSource7) || \ - ((PINSOURCE) == EXTI_PinSource8) || \ - ((PINSOURCE) == EXTI_PinSource9) || \ +#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ + ((PINSOURCE) == EXTI_PinSource1) || \ + ((PINSOURCE) == EXTI_PinSource2) || \ + ((PINSOURCE) == EXTI_PinSource3) || \ + ((PINSOURCE) == EXTI_PinSource4) || \ + ((PINSOURCE) == EXTI_PinSource5) || \ + ((PINSOURCE) == EXTI_PinSource6) || \ + ((PINSOURCE) == EXTI_PinSource7) || \ + ((PINSOURCE) == EXTI_PinSource8) || \ + ((PINSOURCE) == EXTI_PinSource9) || \ ((PINSOURCE) == EXTI_PinSource10) || \ ((PINSOURCE) == EXTI_PinSource11) || \ ((PINSOURCE) == EXTI_PinSource12) || \ @@ -118,13 +129,38 @@ */ #define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) #define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) -#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) #define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) - -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_FSMC)) +#define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04) + +#if defined (STM32F40_41xxx) +#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02) +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#if defined (STM32F40_41xxx) +#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ + ((REMAP) == SYSCFG_MemoryRemap_FSMC)) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F401xx) +#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SRAM)) +#endif /* STM32F401xx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ + ((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \ + ((REMAP) == SYSCFG_MemoryRemap_FMC)) +#endif /* STM32F427_437xx || STM32F429_439xx */ + /** * @} */ @@ -133,11 +169,11 @@ /** @defgroup SYSCFG_ETHERNET_Media_Interface * @{ */ -#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) -#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) +#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) +#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) #define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ - ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) + ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) /** * @} */ @@ -150,10 +186,11 @@ /* Exported functions --------------------------------------------------------*/ void SYSCFG_DeInit(void); -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); -void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); -void SYSCFG_CompensationCellCmd(FunctionalState NewState); +void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); +void SYSCFG_MemorySwappingBank(FunctionalState NewState); +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); +void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); +void SYSCFG_CompensationCellCmd(FunctionalState NewState); FlagStatus SYSCFG_GetCompensationCellStatus(void); #ifdef __cplusplus @@ -170,4 +207,4 @@ FlagStatus SYSCFG_GetCompensationCellStatus(void); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h index 228e81ab6f..2ea1fce224 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_tim.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the TIM firmware * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -1141,4 +1147,4 @@ void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h index c4025e315b..2e6b6e97c2 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_usart.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the USART - * firmware library. + * firmware library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -106,7 +112,9 @@ typedef struct ((PERIPH) == USART3) || \ ((PERIPH) == UART4) || \ ((PERIPH) == UART5) || \ - ((PERIPH) == USART6)) + ((PERIPH) == USART6) || \ + ((PERIPH) == UART7) || \ + ((PERIPH) == UART8)) #define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ ((PERIPH) == USART2) || \ @@ -420,4 +428,4 @@ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h index b054e68c6b..261229af4e 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h @@ -2,21 +2,27 @@ ****************************************************************************** * @file stm32f4xx_wwdg.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file contains all the functions prototypes for the WWDG firmware * library. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -102,4 +108,4 @@ void WWDG_ClearFlag(void); * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c index 80f5c1da51..0713d2bbc4 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file misc.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides all the miscellaneous firmware functions (add-on * to CMSIS functions). * @@ -55,14 +55,20 @@ ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -240,4 +246,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c index d0206c3c7d..484592850e 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c @@ -2,95 +2,103 @@ ****************************************************************************** * @file stm32f4xx_adc.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: - * - Initialization and Configuration (in addition to ADC multi mode + * + Initialization and Configuration (in addition to ADC multi mode * selection) - * - Analog Watchdog configuration - * - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT + * + Analog Watchdog configuration + * + Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT * management - * - Regular Channels Configuration - * - Regular Channels DMA Configuration - * - Injected channels Configuration - * - Interrupts and flags management + * + Regular Channels Configuration + * + Regular Channels DMA Configuration + * + Injected channels Configuration + * + Interrupts and flags management * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - - * 1. Enable the ADC interface clock using - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); - * - * 2. ADC pins configuration - * - Enable the clock for the ADC GPIOs using the following function: - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - Configure these ADC pins in analog mode using GPIO_Init(); - * - * 3. Configure the ADC Prescaler, conversion resolution and data - * alignment using the ADC_Init() function. - * 4. Activate the ADC peripheral using ADC_Cmd() function. - * - * Regular channels group configuration - * ==================================== - * - To configure the ADC regular channels group features, use - * ADC_Init() and ADC_RegularChannelConfig() functions. - * - To activate the continuous mode, use the ADC_continuousModeCmd() - * function. - * - To configurate and activate the Discontinuous mode, use the - * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. - * - To read the ADC converted values, use the ADC_GetConversionValue() - * function. - * - * Multi mode ADCs Regular channels configuration - * =============================================== - * - Refer to "Regular channels group configuration" description to - * configure the ADC1, ADC2 and ADC3 regular channels. - * - Select the Multi mode ADC regular channels features (dual or - * triple mode) using ADC_CommonInit() function and configure - * the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() - * functions. - * - Read the ADCs converted values using the - * ADC_GetMultiModeConversionValue() function. - * - * DMA for Regular channels group features configuration - * ====================================================== - * - To enable the DMA mode for regular channels group, use the - * ADC_DMACmd() function. - * - To enable the generation of DMA requests continuously at the end - * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() - * function. + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable the ADC interface clock using + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); + + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs using the following function: + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + (++) Configure these ADC pins in analog mode using GPIO_Init(); + + (#) Configure the ADC Prescaler, conversion resolution and data + alignment using the ADC_Init() function. + (#) Activate the ADC peripheral using ADC_Cmd() function. + + *** Regular channels group configuration *** + ============================================ + [..] + (+) To configure the ADC regular channels group features, use + ADC_Init() and ADC_RegularChannelConfig() functions. + (+) To activate the continuous mode, use the ADC_continuousModeCmd() + function. + (+) To configurate and activate the Discontinuous mode, use the + ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. + (+) To read the ADC converted values, use the ADC_GetConversionValue() + function. + + *** Multi mode ADCs Regular channels configuration *** + ====================================================== + [..] + (+) Refer to "Regular channels group configuration" description to + configure the ADC1, ADC2 and ADC3 regular channels. + (+) Select the Multi mode ADC regular channels features (dual or + triple mode) using ADC_CommonInit() function and configure + the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() + functions. + (+) Read the ADCs converted values using the + ADC_GetMultiModeConversionValue() function. + + *** DMA for Regular channels group features configuration *** + ============================================================= + [..] + (+) To enable the DMA mode for regular channels group, use the + ADC_DMACmd() function. + (+) To enable the generation of DMA requests continuously at the end + of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() + function. + + *** Injected channels group configuration *** + ============================================= + [..] + (+) To configure the ADC Injected channels group features, use + ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() + functions. + (+) To activate the continuous mode, use the ADC_continuousModeCmd() + function. + (+) To activate the Injected Discontinuous mode, use the + ADC_InjectedDiscModeCmd() function. + (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() + function. + (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue() + function. + + @endverbatim + ****************************************************************************** + * @attention * - * Injected channels group configuration - * ===================================== - * - To configure the ADC Injected channels group features, use - * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() - * functions. - * - To activate the continuous mode, use the ADC_continuousModeCmd() - * function. - * - To activate the Injected Discontinuous mode, use the - * ADC_InjectedDiscModeCmd() function. - * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() - * function. - * - To read the ADC converted values, use the ADC_GetInjectedConversionValue() - * function. + *

    © COPYRIGHT 2013 STMicroelectronics

    * - * @endverbatim + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -176,23 +184,22 @@ * @verbatim =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to: - - Initialize and configure the ADC Prescaler - - ADC Conversion Resolution (12bit..6bit) - - Scan Conversion Mode (multichannels or one channel) for regular group - - ADC Continuous Conversion Mode (Continuous or Single conversion) for - regular group - - External trigger Edge and source of regular group, - - Converted data alignment (left or right) - - The number of ADC conversions that will be done using the sequencer for - regular channel group - - Multi ADC mode selection - - Direct memory access mode selection for multi ADC mode - - Delay between 2 sampling phases (used in dual or triple interleaved modes) - - Enable or disable the ADC peripheral - + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC Prescaler + (+) ADC Conversion Resolution (12bit..6bit) + (+) Scan Conversion Mode (multichannel or one channel) for regular group + (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for + regular group + (+) External trigger Edge and source of regular group, + (+) Converted data alignment (left or right) + (+) The number of ADC conversions that will be done using the sequencer for + regular channel group + (+) Multi ADC mode selection + (+) Direct memory access mode selection for multi ADC mode + (+) Delay between 2 sampling phases (used in dual or triple interleaved modes) + (+) Enable or disable the ADC peripheral @endverbatim * @{ */ @@ -414,20 +421,18 @@ void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) * @verbatim =============================================================================== - Analog Watchdog configuration functions + ##### Analog Watchdog configuration functions ##### =============================================================================== - - This section provides functions allowing to configure the Analog Watchdog - (AWD) feature in the ADC. + [..] This section provides functions allowing to configure the Analog Watchdog + (AWD) feature in the ADC. - A typical configuration Analog Watchdog is done following these steps : - 1. the ADC guarded channel(s) is (are) selected using the - ADC_AnalogWatchdogSingleChannelConfig() function. - 2. The Analog watchdog lower and higher threshold are configured using the - ADC_AnalogWatchdogThresholdsConfig() function. - 3. The Analog watchdog is enabled and configured to enable the check, on one - or more channels, using the ADC_AnalogWatchdogCmd() function. - + [..] A typical configuration Analog Watchdog is done following these steps : + (#) the ADC guarded channel(s) is (are) selected using the + ADC_AnalogWatchdogSingleChannelConfig() function. + (#) The Analog watchdog lower and higher threshold are configured using the + ADC_AnalogWatchdogThresholdsConfig() function. + (#) The Analog watchdog is enabled and configured to enable the check, on one + or more channels, using the ADC_AnalogWatchdogCmd() function. @endverbatim * @{ */ @@ -546,30 +551,29 @@ void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channe * @verbatim =============================================================================== - Temperature Sensor, Vrefint and VBAT management functions + ##### Temperature Sensor, Vrefint and VBAT management functions ##### =============================================================================== - - This section provides functions allowing to enable/ disable the internal - connections between the ADC and the Temperature Sensor, the Vrefint and the - Vbat sources. + [..] This section provides functions allowing to enable/ disable the internal + connections between the ADC and the Temperature Sensor, the Vrefint and + the Vbat sources. - A typical configuration to get the Temperature sensor and Vrefint channels - voltages is done following these steps : - 1. Enable the internal connection of Temperature sensor and Vrefint sources - with the ADC channels using ADC_TempSensorVrefintCmd() function. - 2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using - ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions - 3. Get the voltage values, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - - A typical configuration to get the VBAT channel voltage is done following - these steps : - 1. Enable the internal connection of VBAT source with the ADC channel using - ADC_VBATCmd() function. - 2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or - ADC_InjectedChannelConfig() functions - 3. Get the voltage value, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). + [..] A typical configuration to get the Temperature sensor and Vrefint channels + voltages is done following these steps : + (#) Enable the internal connection of Temperature sensor and Vrefint sources + with the ADC channels using ADC_TempSensorVrefintCmd() function. + (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using + ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions + (#) Get the voltage values, using ADC_GetConversionValue() or + ADC_GetInjectedConversionValue(). + + [..] A typical configuration to get the VBAT channel voltage is done following + these steps : + (#) Enable the internal connection of VBAT source with the ADC channel using + ADC_VBATCmd() function. + (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or + ADC_InjectedChannelConfig() functions + (#) Get the voltage value, using ADC_GetConversionValue() or + ADC_GetInjectedConversionValue(). @endverbatim * @{ @@ -600,6 +604,10 @@ void ADC_TempSensorVrefintCmd(FunctionalState NewState) /** * @brief Enables or disables the VBAT (Voltage Battery) channel. + * + * @note the Battery voltage measured is equal to VBAT/2 on STM32F40xx and + * STM32F41xx devices and equal to VBAT/4 on STM32F42xx and STM32F43xx devices + * * @param NewState: new state of the VBAT channel. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -629,40 +637,39 @@ void ADC_VBATCmd(FunctionalState NewState) * @verbatim =============================================================================== - Regular Channels Configuration functions + ##### Regular Channels Configuration functions ##### =============================================================================== - This section provides functions allowing to manage the ADC's regular channels, - it is composed of 2 sub sections : - - 1. Configuration and management functions for regular channels: This subsection - provides functions allowing to configure the ADC regular channels : - - Configure the rank in the regular group sequencer for each channel - - Configure the sampling time for each channel - - select the conversion Trigger for regular channels - - select the desired EOC event behavior configuration - - Activate the continuous Mode (*) - - Activate the Discontinuous Mode - Please Note that the following features for regular channels are configurated - using the ADC_Init() function : - - scan mode activation - - continuous mode activation (**) - - External trigger source - - External trigger edge - - number of conversion in the regular channels group sequencer. + [..] This section provides functions allowing to manage the ADC's regular channels, + it is composed of 2 sub sections : + + (#) Configuration and management functions for regular channels: This subsection + provides functions allowing to configure the ADC regular channels : + (++) Configure the rank in the regular group sequencer for each channel + (++) Configure the sampling time for each channel + (++) select the conversion Trigger for regular channels + (++) select the desired EOC event behavior configuration + (++) Activate the continuous Mode (*) + (++) Activate the Discontinuous Mode + -@@- Please Note that the following features for regular channels + are configurated using the ADC_Init() function : + (+@@) scan mode activation + (+@@) continuous mode activation (**) + (+@@) External trigger source + (+@@) External trigger edge + (+@@) number of conversion in the regular channels group sequencer. - @note (*) and (**) are performing the same configuration + -@@- (*) and (**) are performing the same configuration - 2. Get the conversion data: This subsection provides an important function in - the ADC peripheral since it returns the converted data of the current - regular channel. When the Conversion value is read, the EOC Flag is - automatically cleared. + (#) Get the conversion data: This subsection provides an important function in + the ADC peripheral since it returns the converted data of the current + regular channel. When the Conversion value is read, the EOC Flag is + automatically cleared. - @note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions - results data (in the selected multi mode) can be returned in the same - time using ADC_GetMultiModeConversionValue() function. - - + -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions + results data (in the selected multi mode) can be returned in the same + time using ADC_GetMultiModeConversionValue() function. + @endverbatim * @{ */ @@ -846,7 +853,7 @@ FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) + if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET) { /* SWSTART bit is set */ bitstatus = SET; @@ -1010,29 +1017,26 @@ uint32_t ADC_GetMultiModeConversionValue(void) * @verbatim =============================================================================== - Regular Channels DMA Configuration functions + ##### Regular Channels DMA Configuration functions ##### =============================================================================== - - This section provides functions allowing to configure the DMA for ADC regular - channels. - Since converted regular channel values are stored into a unique data register, - it is useful to use DMA for conversion of more than one regular channel. This - avoids the loss of the data already stored in the ADC Data register. - - When the DMA mode is enabled (using the ADC_DMACmd() function), after each - conversion of a regular channel, a DMA request is generated. - - Depending on the "DMA disable selection for Independent ADC mode" - configuration (using the ADC_DMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - - No new DMA request is issued to the DMA controller (feature DISABLED) - - Requests can continue to be generated (feature ENABLED). - - Depending on the "DMA disable selection for multi ADC mode" configuration - (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - - No new DMA request is issued to the DMA controller (feature DISABLED) - - Requests can continue to be generated (feature ENABLED). + [..] This section provides functions allowing to configure the DMA for ADC + regular channels. + Since converted regular channel values are stored into a unique data + register, it is useful to use DMA for conversion of more than one regular + channel. This avoids the loss of the data already stored in the ADC + Data register. + When the DMA mode is enabled (using the ADC_DMACmd() function), after each + conversion of a regular channel, a DMA request is generated. + [..] Depending on the "DMA disable selection for Independent ADC mode" + configuration (using the ADC_DMARequestAfterLastTransferCmd() function), + at the end of the last DMA transfer, two possibilities are allowed: + (+) No new DMA request is issued to the DMA controller (feature DISABLED) + (+) Requests can continue to be generated (feature ENABLED). + [..] Depending on the "DMA disable selection for multi ADC mode" configuration + (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), + at the end of the last DMA transfer, two possibilities are allowed: + (+) No new DMA request is issued to the DMA controller (feature DISABLED) + (+) Requests can continue to be generated (feature ENABLED). @endverbatim * @{ @@ -1120,26 +1124,26 @@ void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState) * @verbatim =============================================================================== - Injected channels Configuration functions + ##### Injected channels Configuration functions ##### =============================================================================== - This section provide functions allowing to configure the ADC Injected channels, - it is composed of 2 sub sections : + [..] This section provide functions allowing to configure the ADC Injected channels, + it is composed of 2 sub sections : - 1. Configuration functions for Injected channels: This subsection provides - functions allowing to configure the ADC injected channels : - - Configure the rank in the injected group sequencer for each channel - - Configure the sampling time for each channel - - Activate the Auto injected Mode - - Activate the Discontinuous Mode - - scan mode activation - - External/software trigger source - - External trigger edge - - injected channels sequencer. + (#) Configuration functions for Injected channels: This subsection provides + functions allowing to configure the ADC injected channels : + (++) Configure the rank in the injected group sequencer for each channel + (++) Configure the sampling time for each channel + (++) Activate the Auto injected Mode + (++) Activate the Discontinuous Mode + (++) scan mode activation + (++) External/software trigger source + (++) External trigger edge + (++) injected channels sequencer. - 2. Get the Specified Injected channel conversion data: This subsection - provides an important function in the ADC peripheral since it returns the - converted data of the specific injected channel. + (#) Get the Specified Injected channel conversion data: This subsection + provides an important function in the ADC peripheral since it returns the + converted data of the specific injected channel. @endverbatim * @{ @@ -1493,75 +1497,74 @@ uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedC * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== - This section provides functions allowing to configure the ADC Interrupts and - to get the status and clear flags and Interrupts pending bits. + [..] This section provides functions allowing to configure the ADC Interrupts + and to get the status and clear flags and Interrupts pending bits. - Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into - 3 groups: + [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided + into 3 groups: - I. Flags and Interrupts for ADC regular channels - ================================================= - Flags : - ---------- - 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost - - 2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending - on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of: - ==> a regular CHANNEL conversion - ==> sequence of regular GROUP conversions . - - 3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL - conversion starts. - - Interrupts : - ------------ - 1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event. - 2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of - conversion event. + *** Flags and Interrupts for ADC regular channels *** + ===================================================== + [..] + (+) Flags : + (##) ADC_FLAG_OVR : Overrun detection when regular converted data are lost + + (##) ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate + (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) + the end of: + (+++) a regular CHANNEL conversion + (+++) sequence of regular GROUP conversions . + + (##) ADC_FLAG_STRT: Regular channel start ==> to indicate when regular + CHANNEL conversion starts. + [..] + (+) Interrupts : + (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection + event. + (##) ADC_IT_EOC : specifies the interrupt source for Regular channel end + of conversion event. - II. Flags and Interrupts for ADC Injected channels - ================================================= - Flags : - ---------- - 1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at - the end of injected GROUP conversion - - 2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when - injected GROUP conversion starts. - - Interrupts : - ------------ - 1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of - conversion event. - - III. General Flags and Interrupts for the ADC - ================================================= - Flags : - ---------- - 1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage - crosses the programmed thresholds values. + *** Flags and Interrupts for ADC Injected channels *** + ====================================================== + [..] + (+) Flags : + (##) ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate + at the end of injected GROUP conversion - Interrupts : - ------------ - 1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. + (##) ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when + injected GROUP conversion starts. + [..] + (+) Interrupts : + (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel + end of conversion event. + + *** General Flags and Interrupts for the ADC *** + ================================================ + [..] + (+)Flags : + (##) ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage + crosses the programmed thresholds values. + [..] + (+) Interrupts : + (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. - The user should identify which mode will be used in his application to manage - the ADC controller events: Polling mode or Interrupt mode. + [..] The user should identify which mode will be used in his application to + manage the ADC controller events: Polling mode or Interrupt mode. - In the Polling Mode it is advised to use the following functions: - - ADC_GetFlagStatus() : to check if flags events occur. - - ADC_ClearFlag() : to clear the flags events. + [..] In the Polling Mode it is advised to use the following functions: + (+) ADC_GetFlagStatus() : to check if flags events occur. + (+) ADC_ClearFlag() : to clear the flags events. - In the Interrupt Mode it is advised to use the following functions: - - ADC_ITConfig() : to enable or disable the interrupt source. - - ADC_GetITStatus() : to check if Interrupt occurs. - - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). + [..] In the Interrupt Mode it is advised to use the following functions: + (+) ADC_ITConfig() : to enable or disable the interrupt source. + (+) ADC_GetITStatus() : to check if Interrupt occurs. + (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). @endverbatim * @{ */ @@ -1739,4 +1742,4 @@ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c index 8543ab8b59..ef8dbfd596 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c @@ -2,77 +2,82 @@ ****************************************************************************** * @file stm32f4xx_can.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Controller area network (CAN) peripheral: - * - Initialization and Configuration - * - CAN Frames Transmission - * - CAN Frames Reception - * - Operation modes switch - * - Error management - * - Interrupts and flags + * + Initialization and Configuration + * + CAN Frames Transmission + * + CAN Frames Reception + * + Operation modes switch + * + Error management + * + Interrupts and flags * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== +@verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable the CAN controller interface clock using + RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 + and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2 + -@- In case you are using CAN2 only, you have to enable the CAN1 clock. + + (#) CAN pins configuration + (++) Enable the clock for the CAN GPIOs using the following function: + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + (++) Connect the involved CAN pins to AF9 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); + (++) Configure these CAN pins in alternate function mode by calling + the function GPIO_Init(); + + (#) Initialise and configure the CAN using CAN_Init() and + CAN_FilterInit() functions. + + (#) Transmit the desired CAN frame using CAN_Transmit() function. + + (#) Check the transmission of a CAN frame using CAN_TransmitStatus() + function. + + (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit() + function. + + (#) Receive a CAN frame using CAN_Recieve() function. + + (#) Release the receive FIFOs using CAN_FIFORelease() function. + + (#) Return the number of pending received frames using + CAN_MessagePending() function. + + (#) To control CAN events you can use one of the following two methods: + (++) Check on CAN flags using the CAN_GetFlagStatus() function. + (++) Use CAN interrupts through the function CAN_ITConfig() at + initialization phase and CAN_GetITStatus() function into + interrupt routines to check if the event has occurred or not. + After checking on a flag you should clear it using CAN_ClearFlag() + function. And after checking on an interrupt event you should + clear it using CAN_ClearITPendingBit() function. + - * 1. Enable the CAN controller interface clock using - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 - * and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2 - * @note In case you are using CAN2 only, you have to enable the CAN1 clock. - * - * 2. CAN pins configuration - * - Enable the clock for the CAN GPIOs using the following function: - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - Connect the involved CAN pins to AF9 using the following function - * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); - * - Configure these CAN pins in alternate function mode by calling - * the function GPIO_Init(); - * - * 3. Initialise and configure the CAN using CAN_Init() and - * CAN_FilterInit() functions. - * - * 4. Transmit the desired CAN frame using CAN_Transmit() function. - * - * 5. Check the transmission of a CAN frame using CAN_TransmitStatus() - * function. - * - * 6. Cancel the transmission of a CAN frame using CAN_CancelTransmit() - * function. - * - * 7. Receive a CAN frame using CAN_Recieve() function. - * - * 8. Release the receive FIFOs using CAN_FIFORelease() function. - * - * 9. Return the number of pending received frames using - * CAN_MessagePending() function. - * - * 10. To control CAN events you can use one of the following two methods: - * - Check on CAN flags using the CAN_GetFlagStatus() function. - * - Use CAN interrupts through the function CAN_ITConfig() at - * initialization phase and CAN_GetITStatus() function into - * interrupt routines to check if the event has occurred or not. - * After checking on a flag you should clear it using CAN_ClearFlag() - * function. And after checking on an interrupt event you should - * clear it using CAN_ClearITPendingBit() function. - * - * - * @endverbatim - * +@endverbatim + ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -138,17 +143,17 @@ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); * @verbatim =============================================================================== - Initialization and Configuration functions + ##### Initialization and Configuration functions ##### =============================================================================== - This section provides functions allowing to - - Initialize the CAN peripherals : Prescaler, operating mode, the maximum number - of time quanta to perform resynchronization, the number of time quanta in - Bit Segment 1 and 2 and many other modes. - Refer to @ref CAN_InitTypeDef for more details. - - Configures the CAN reception filter. - - Select the start bank filter for slave CAN. - - Enables or disables the Debug Freeze mode for CAN - - Enables or disables the CAN Time Trigger Operation communication mode + [..] This section provides functions allowing to + (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum + number of time quanta to perform resynchronization, the number of time + quanta in Bit Segment 1 and 2 and many other modes. + Refer to @ref CAN_InitTypeDef for more details. + (+) Configures the CAN reception filter. + (+) Select the start bank filter for slave CAN. + (+) Enables or disables the Debug Freeze mode for CAN + (+)Enables or disables the CAN Time Trigger Operation communication mode @endverbatim * @{ @@ -551,12 +556,12 @@ void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) * @verbatim =============================================================================== - CAN Frames Transmission functions + ##### CAN Frames Transmission functions ##### =============================================================================== - This section provides functions allowing to - - Initiate and transmit a CAN frame message (if there is an empty mailbox). - - Check the transmission status of a CAN Frame - - Cancel a transmit request + [..] This section provides functions allowing to + (+) Initiate and transmit a CAN frame message (if there is an empty mailbox). + (+) Check the transmission status of a CAN Frame + (+) Cancel a transmit request @endverbatim * @{ @@ -723,12 +728,12 @@ void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) * @verbatim =============================================================================== - CAN Frames Reception functions + ##### CAN Frames Reception functions ##### =============================================================================== - This section provides functions allowing to - - Receive a correct CAN frame - - Release a specified receive FIFO (2 FIFOs are available) - - Return the number of the pending received CAN frames + [..] This section provides functions allowing to + (+) Receive a correct CAN frame + (+) Release a specified receive FIFO (2 FIFOs are available) + (+) Return the number of the pending received CAN frames @endverbatim * @{ @@ -844,12 +849,12 @@ uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) * @verbatim =============================================================================== - CAN Operation modes functions + ##### CAN Operation modes functions ##### =============================================================================== - This section provides functions allowing to select the CAN Operation modes - - sleep mode - - normal mode - - initialization mode + [..] This section provides functions allowing to select the CAN Operation modes + (+) sleep mode + (+) normal mode + (+) initialization mode @endverbatim * @{ @@ -1004,16 +1009,16 @@ uint8_t CAN_WakeUp(CAN_TypeDef* CANx) * @verbatim =============================================================================== - CAN Bus Error management functions + ##### CAN Bus Error management functions ##### =============================================================================== - This section provides functions allowing to - - Return the CANx's last error code (LEC) - - Return the CANx Receive Error Counter (REC) - - Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). + [..] This section provides functions allowing to + (+) Return the CANx's last error code (LEC) + (+) Return the CANx Receive Error Counter (REC) + (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). - @note If TEC is greater than 255, The CAN is in bus-off state. - @note if REC or TEC are greater than 96, an Error warning flag occurs. - @note if REC or TEC are greater than 127, an Error Passive Flag occurs. + -@- If TEC is greater than 255, The CAN is in bus-off state. + -@- if REC or TEC are greater than 96, an Error warning flag occurs. + -@- if REC or TEC are greater than 127, an Error Passive Flag occurs. @endverbatim * @{ @@ -1099,163 +1104,161 @@ uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== - This section provides functions allowing to configure the CAN Interrupts and - to get the status and clear flags and Interrupts pending bits. + [..] This section provides functions allowing to configure the CAN Interrupts + and to get the status and clear flags and Interrupts pending bits. - The CAN provides 14 Interrupts sources and 15 Flags: - - =============== - Flags : - =============== - The 15 flags can be divided on 4 groups: - - A. Transmit Flags - ----------------------- - CAN_FLAG_RQCP0, - CAN_FLAG_RQCP1, - CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags - Set when when the last request (transmit or abort) has - been performed. - - B. Receive Flags - ----------------------- - - CAN_FLAG_FMP0, - CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags - set to signal that messages are pending in the receive - FIFO. - These Flags are cleared only by hardware. - - CAN_FLAG_FF0, - CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags - set when three messages are stored in the selected - FIFO. - - CAN_FLAG_FOV0 - CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags - set when a new message has been received and passed - the filter while the FIFO was full. - - C. Operating Mode Flags - ----------------------- - CAN_FLAG_WKU : Wake up Flag - set to signal that a SOF bit has been detected while - the CAN hardware was in Sleep mode. + The CAN provides 14 Interrupts sources and 15 Flags: + + + *** Flags *** + ============= + [..] The 15 flags can be divided on 4 groups: + + (+) Transmit Flags + (++) CAN_FLAG_RQCP0, + (++) CAN_FLAG_RQCP1, + (++) CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags + Set when when the last request (transmit or abort) + has been performed. + + (+) Receive Flags + + + (++) CAN_FLAG_FMP0, + (++) CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags + set to signal that messages are pending in the receive + FIFO. + These Flags are cleared only by hardware. + + (++) CAN_FLAG_FF0, + (++) CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags + set when three messages are stored in the selected + FIFO. + + (++) CAN_FLAG_FOV0 + (++) CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags + set when a new message has been received and passed + the filter while the FIFO was full. + + (+) Operating Mode Flags + + (++) CAN_FLAG_WKU : Wake up Flag + set to signal that a SOF bit has been detected while + the CAN hardware was in Sleep mode. - CAN_FLAG_SLAK : Sleep acknowledge Flag - Set to signal that the CAN has entered Sleep Mode. + (++) CAN_FLAG_SLAK : Sleep acknowledge Flag + Set to signal that the CAN has entered Sleep Mode. - D. Error Flags - ----------------------- - CAN_FLAG_EWG : Error Warning Flag - Set when the warning limit has been reached (Receive - Error Counter or Transmit Error Counter greater than 96). - This Flag is cleared only by hardware. + (+) Error Flags + + (++) CAN_FLAG_EWG : Error Warning Flag + Set when the warning limit has been reached (Receive + Error Counter or Transmit Error Counter greater than 96). + This Flag is cleared only by hardware. - CAN_FLAG_EPV : Error Passive Flag - Set when the Error Passive limit has been reached - (Receive Error Counter or Transmit Error Counter - greater than 127). - This Flag is cleared only by hardware. + (++) CAN_FLAG_EPV : Error Passive Flag + Set when the Error Passive limit has been reached + (Receive Error Counter or Transmit Error Counter + greater than 127). + This Flag is cleared only by hardware. - CAN_FLAG_BOF : Bus-Off Flag - set when CAN enters the bus-off state. The bus-off - state is entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. + (++) CAN_FLAG_BOF : Bus-Off Flag + set when CAN enters the bus-off state. The bus-off + state is entered on TEC overflow, greater than 255. + This Flag is cleared only by hardware. - CAN_FLAG_LEC : Last error code Flag - set If a message has been transferred (reception or - transmission) with error, and the error code is hold. - - =============== - Interrupts : - =============== - The 14 interrupts can be divided on 4 groups: + (++) CAN_FLAG_LEC : Last error code Flag + set If a message has been transferred (reception or + transmission) with error, and the error code is hold. + + *** Interrupts *** + ================== + [..] The 14 interrupts can be divided on 4 groups: + + (+) Transmit interrupt - A. Transmit interrupt - ----------------------- - CAN_IT_TME : Transmit mailbox empty Interrupt - if enabled, this interrupt source is pending when - no transmit request are pending for Tx mailboxes. - - B. Receive Interrupts - ----------------------- - CAN_IT_FMP0, - CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts - if enabled, these interrupt sources are pending when - messages are pending in the receive FIFO. - The corresponding interrupt pending bits are cleared - only by hardware. + (++) CAN_IT_TME : Transmit mailbox empty Interrupt + if enabled, this interrupt source is pending when + no transmit request are pending for Tx mailboxes. + + (+) Receive Interrupts + + (++) CAN_IT_FMP0, + (++) CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts + if enabled, these interrupt sources are pending + when messages are pending in the receive FIFO. + The corresponding interrupt pending bits are cleared + only by hardware. - CAN_IT_FF0, - CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts - if enabled, these interrupt sources are pending when - three messages are stored in the selected FIFO. + (++) CAN_IT_FF0, + (++) CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts + if enabled, these interrupt sources are pending + when three messages are stored in the selected FIFO. - CAN_IT_FOV0, - CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts - if enabled, these interrupt sources are pending when - a new message has been received and passed the filter - while the FIFO was full. - - C. Operating Mode Interrupts - ------------------------------- - CAN_IT_WKU : Wake-up Interrupt - if enabled, this interrupt source is pending when - a SOF bit has been detected while the CAN hardware was - in Sleep mode. + (++) CAN_IT_FOV0, + (++) CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts + if enabled, these interrupt sources are pending + when a new message has been received and passed + the filter while the FIFO was full. + + (+) Operating Mode Interrupts + + (++) CAN_IT_WKU : Wake-up Interrupt + if enabled, this interrupt source is pending when + a SOF bit has been detected while the CAN hardware + was in Sleep mode. - CAN_IT_SLK : Sleep acknowledge Interrupt - if enabled, this interrupt source is pending when - the CAN has entered Sleep Mode. - - D. Error Interrupts - ----------------------- - CAN_IT_EWG : Error warning Interrupt - if enabled, this interrupt source is pending when - the warning limit has been reached (Receive Error - Counter or Transmit Error Counter=96). + (++) CAN_IT_SLK : Sleep acknowledge Interrupt + if enabled, this interrupt source is pending when + the CAN has entered Sleep Mode. + + (+) Error Interrupts + + (++) CAN_IT_EWG : Error warning Interrupt + if enabled, this interrupt source is pending when + the warning limit has been reached (Receive Error + Counter or Transmit Error Counter=96). - CAN_IT_EPV : Error passive Interrupt - if enabled, this interrupt source is pending when - the Error Passive limit has been reached (Receive - Error Counter or Transmit Error Counter>127). + (++) CAN_IT_EPV : Error passive Interrupt + if enabled, this interrupt source is pending when + the Error Passive limit has been reached (Receive + Error Counter or Transmit Error Counter>127). - CAN_IT_BOF : Bus-off Interrupt - if enabled, this interrupt source is pending when - CAN enters the bus-off state. The bus-off state is - entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. + (++) CAN_IT_BOF : Bus-off Interrupt + if enabled, this interrupt source is pending when + CAN enters the bus-off state. The bus-off state is + entered on TEC overflow, greater than 255. + This Flag is cleared only by hardware. - CAN_IT_LEC : Last error code Interrupt - if enabled, this interrupt source is pending when - a message has been transferred (reception or - transmission) with error, and the error code is hold. + (++) CAN_IT_LEC : Last error code Interrupt + if enabled, this interrupt source is pending when + a message has been transferred (reception or + transmission) with error, and the error code is hold. - CAN_IT_ERR : Error Interrupt - if enabled, this interrupt source is pending when - an error condition is pending. + (++) CAN_IT_ERR : Error Interrupt + if enabled, this interrupt source is pending when + an error condition is pending. - - Managing the CAN controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the CAN controller events: Polling mode or Interrupt mode. + [..] Managing the CAN controller events : + + The user should identify which mode will be used in his application to + manage the CAN controller events: Polling mode or Interrupt mode. - 1. In the Polling Mode it is advised to use the following functions: - - CAN_GetFlagStatus() : to check if flags events occur. - - CAN_ClearFlag() : to clear the flags events. + (#) In the Polling Mode it is advised to use the following functions: + (++) CAN_GetFlagStatus() : to check if flags events occur. + (++) CAN_ClearFlag() : to clear the flags events. - 2. In the Interrupt Mode it is advised to use the following functions: - - CAN_ITConfig() : to enable or disable the interrupt source. - - CAN_GetITStatus() : to check if Interrupt occurs. - - CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). - @note This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts + (#) In the Interrupt Mode it is advised to use the following functions: + (++) CAN_ITConfig() : to enable or disable the interrupt source. + (++) CAN_GetITStatus() : to check if Interrupt occurs. + (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). + -@@- This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts pending bits since there are cleared only by hardware. @endverbatim @@ -1695,4 +1698,4 @@ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c index c2c6bbb3ce..9ad9d98af3 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c @@ -2,20 +2,26 @@ ****************************************************************************** * @file stm32f4xx_crc.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides all the CRC firmware functions. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -124,4 +130,4 @@ uint8_t CRC_GetIDRegister(void) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c index dcdbef8f5a..dd502484b1 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c @@ -2,156 +2,161 @@ ****************************************************************************** * @file stm32f4xx_cryp.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Cryptographic processor (CRYP) peripheral: - * - Initialization and Configuration functions - * - Data treatment functions - * - Context swapping functions - * - DMA interface function - * - Interrupts and flags management + * + Initialization and Configuration functions + * + Data treatment functions + * + Context swapping functions + * + DMA interface function + * + Interrupts and flags management * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable the CRYP controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - * - * 2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if - * needed CRYP_IVInit(). - * - * 3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function. - * - * 4. Enable the CRYP controller using the CRYP_Cmd() function. - * - * 5. If using DMA for Data input and output transfer, - * Activate the needed DMA Requests using CRYP_DMACmd() function +@verbatim + =================================================================== + ##### How to use this driver ##### + =================================================================== + [..] + (#) Enable the CRYP controller clock using + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - * 6. If DMA is not used for data transfer, use CRYP_DataIn() and - * CRYP_DataOut() functions to enter data to IN FIFO and get result - * from OUT FIFO. - * - * 7. To control CRYP events you can use one of the following - * two methods: - * - Check on CRYP flags using the CRYP_GetFlagStatus() function. - * - Use CRYP interrupts through the function CRYP_ITConfig() at - * initialization phase and CRYP_GetITStatus() function into - * interrupt routines in processing phase. - * - * 8. Save and restore Cryptographic processor context using - * CRYP_SaveContext() and CRYP_RestoreContext() functions. - * - * - * =================================================================== - * Procedure to perform an encryption or a decryption - * =================================================================== - * - * Initialization - * =============== - * 1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and - * CRYP_IVInit functions: - * - Configure the key size (128-, 192- or 256-bit, in the AES only) - * - Enter the symmetric key - * - Configure the data type - * - In case of decryption in AES-ECB or AES-CBC, you must prepare - * the key: configure the key preparation mode. Then Enable the CRYP - * peripheral using CRYP_Cmd() function: the BUSY flag is set. - * Wait until BUSY flag is reset : the key is prepared for decryption - * - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the - * AES in ECB/CBC/CTR) - * - Configure the direction (encryption/decryption). - * - Write the initialization vectors (in CBC or CTR modes only) - * - * 2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function - * - * - * Basic Processing mode (polling mode) - * ==================================== - * 1. Enable the cryptographic processor using CRYP_Cmd() function. - * - * 2. Write the first blocks in the input FIFO (2 to 8 words) using - * CRYP_DataIn() function. - * - * 3. Repeat the following sequence until the complete message has been - * processed: - * - * a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() - * function), then read the OUT-FIFO using CRYP_DataOut() function - * (1 block or until the FIFO is empty) - * - * b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() - * function then write the IN FIFO using CRYP_DataIn() function - * (1 block or until the FIFO is full) - * - * 4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and - * both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is - * reset). You can disable the peripheral using CRYP_Cmd() function. - * - * Interrupts Processing mode - * =========================== - * In this mode, Processing is done when the data are transferred by the - * CPU during interrupts. - * - * 1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using - * CRYP_ITConfig() function. - * - * 2. Enable the cryptographic processor using CRYP_Cmd() function. - * - * 3. In the CRYP_IT_INI interrupt handler : load the input message into the - * IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a - * time, or load data until the IN FIFO is full. When the last word of - * the message has been entered into the IN FIFO, disable the CRYP_IT_INI - * interrupt (using CRYP_ITConfig() function). - * - * 4. In the CRYP_IT_OUTI interrupt handler : read the output message from - * the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or - * 4 words) at a time or read data until the FIFO is empty. - * When the last word has been read, INIM=0, BUSY=0 and both FIFOs are - * empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). - * You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() - * function) and you can disable the peripheral using CRYP_Cmd() function. - * - * DMA Processing mode - * ==================== - * In this mode, Processing is done when the DMA is used to transfer the - * data from/to the memory. - * - * 1. Configure the DMA controller to transfer the input data from the - * memory using DMA_Init() function. - * The transfer length is the length of the message. - * As message padding is not managed by the peripheral, the message - * length must be an entire number of blocks. The data are transferred - * in burst mode. The burst length is 4 words in the AES and 2 or 4 - * words in the DES/TDES. The DMA should be configured to set an - * interrupt on transfer completion of the output data to indicate that - * the processing is finished. - * Refer to DMA peripheral driver for more details. + (#) Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if needed + CRYP_IVInit(). + + (#) Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function. + + (#) Enable the CRYP controller using the CRYP_Cmd() function. + + (#) If using DMA for Data input and output transfer, activate the needed DMA + Requests using CRYP_DMACmd() function + + (#) If DMA is not used for data transfer, use CRYP_DataIn() and CRYP_DataOut() + functions to enter data to IN FIFO and get result from OUT FIFO. + + (#) To control CRYP events you can use one of the following two methods: + (++) Check on CRYP flags using the CRYP_GetFlagStatus() function. + (++) Use CRYP interrupts through the function CRYP_ITConfig() at + initialization phase and CRYP_GetITStatus() function into interrupt + routines in processing phase. + + (#) Save and restore Cryptographic processor context using CRYP_SaveContext() + and CRYP_RestoreContext() functions. + + + *** Procedure to perform an encryption or a decryption *** + ========================================================== + + *** Initialization *** + ====================== + [..] + (#) Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and CRYP_IVInit + functions: + (++) Configure the key size (128-, 192- or 256-bit, in the AES only) + (++) Enter the symmetric key + (++) Configure the data type + (++) In case of decryption in AES-ECB or AES-CBC, you must prepare + the key: configure the key preparation mode. Then Enable the CRYP + peripheral using CRYP_Cmd() function: the BUSY flag is set. + Wait until BUSY flag is reset : the key is prepared for decryption + (++) Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the + AES in ECB/CBC/CTR) + (++) Configure the direction (encryption/decryption). + (++) Write the initialization vectors (in CBC or CTR modes only) + + (#) Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function + + + *** Basic Processing mode (polling mode) *** + ============================================ + [..] + (#) Enable the cryptographic processor using CRYP_Cmd() function. + + (#) Write the first blocks in the input FIFO (2 to 8 words) using + CRYP_DataIn() function. + + (#) Repeat the following sequence until the complete message has been + processed: + + (++) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() + function), then read the OUT-FIFO using CRYP_DataOut() function + (1 block or until the FIFO is empty) + + (++) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() + function then write the IN FIFO using CRYP_DataIn() function + (1 block or until the FIFO is full) + + (#) At the end of the processing, CRYP_FLAG_BUSY flag will be reset and + both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is + reset). You can disable the peripheral using CRYP_Cmd() function. + + *** Interrupts Processing mode *** + ================================== + [..] In this mode, Processing is done when the data are transferred by the + CPU during interrupts. + + (#) Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using CRYP_ITConfig() + function. + + (#) Enable the cryptographic processor using CRYP_Cmd() function. + + (#) In the CRYP_IT_INI interrupt handler : load the input message into the + IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a + time, or load data until the IN FIFO is full. When the last word of + the message has been entered into the IN FIFO, disable the CRYP_IT_INI + interrupt (using CRYP_ITConfig() function). + + (#) In the CRYP_IT_OUTI interrupt handler : read the output message from + the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or + 4 words) at a time or read data until the FIFO is empty. + When the last word has been read, INIM=0, BUSY=0 and both FIFOs are + empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). + You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() + function) and you can disable the peripheral using CRYP_Cmd() function. + + *** DMA Processing mode *** + =========================== + [..] In this mode, Processing is done when the DMA is used to transfer the + data from/to the memory. + + (#) Configure the DMA controller to transfer the input data from the + memory using DMA_Init() function. + The transfer length is the length of the message. + As message padding is not managed by the peripheral, the message + length must be an entire number of blocks. The data are transferred + in burst mode. The burst length is 4 words in the AES and 2 or 4 + words in the DES/TDES. The DMA should be configured to set an + interrupt on transfer completion of the output data to indicate that + the processing is finished. + Refer to DMA peripheral driver for more details. + + (#) Enable the cryptographic processor using CRYP_Cmd() function. + Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT + using CRYP_DMACmd() function. + + (#) All the transfers and processing are managed by the DMA and the + cryptographic processor. The DMA transfer complete interrupt indicates + that the processing is complete. Both FIFOs are normally empty and + CRYP_FLAG_BUSY flag is reset. + + @endverbatim * - * 2. Enable the cryptographic processor using CRYP_Cmd() function. - * Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT - * using CRYP_DMACmd() function. + ****************************************************************************** + * @attention * - * 3. All the transfers and processing are managed by the DMA and the - * cryptographic processor. The DMA transfer complete interrupt indicates - * that the processing is complete. Both FIFOs are normally empty and - * CRYP_FLAG_BUSY flag is reset. + *

    © COPYRIGHT 2013 STMicroelectronics

    * - * @endverbatim + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -187,23 +192,22 @@ * @verbatim =============================================================================== - Initialization and Configuration functions + ##### Initialization and Configuration functions ##### =============================================================================== - This section provides functions allowing to - - Initialize the cryptographic Processor using CRYP_Init() function - - Encrypt or Decrypt - - mode : TDES-ECB, TDES-CBC, - DES-ECB, DES-CBC, - AES-ECB, AES-CBC, AES-CTR, AES-Key - - DataType : 32-bit data, 16-bit data, bit data or bit-string - - Key Size (only in AES modes) - - Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function - - Configure the Initialization Vectors(IV) for CBC and CTR modes using - CRYP_IVInit() function. - - Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. - - Enable or disable the CRYP Processor using CRYP_Cmd() function - - + [..] This section provides functions allowing to + (+) Initialize the cryptographic Processor using CRYP_Init() function + (++) Encrypt or Decrypt + (++) mode : TDES-ECB, TDES-CBC, + DES-ECB, DES-CBC, + AES-ECB, AES-CBC, AES-CTR, AES-Key, AES-GCM, AES-CCM + (++) DataType : 32-bit data, 16-bit data, bit data or bit-string + (++) Key Size (only in AES modes) + (+) Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function + (+) Configure the Initialization Vectors(IV) for CBC and CTR modes using + CRYP_IVInit() function. + (+) Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. + (+) Enable or disable the CRYP Processor using CRYP_Cmd() function + @endverbatim * @{ */ @@ -244,10 +248,10 @@ void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct) CRYP->CR |= CRYP_InitStruct->CRYP_DataType; /* select Key size (used only with AES algorithm) */ - if ((CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_ECB) || - (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CBC) || - (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CTR) || - (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_Key)) + if ((CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_ECB) && + (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_CBC) && + (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_ECB) && + (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_CBC)) { assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize)); CRYP->CR &= ~CRYP_CR_KEYSIZE; @@ -348,6 +352,35 @@ void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) CRYP_IVInitStruct->CRYP_IV1Right = 0; } +/** + * @brief Configures the AES-CCM and AES-GCM phases + * @note This function is used only with AES-CCM or AES-GCM Algorithms + * @param CRYP_Phase: specifies the CRYP AES-CCM and AES-GCM phase to be configured. + * This parameter can be one of the following values: + * @arg CRYP_Phase_Init: Initialization phase + * @arg CRYP_Phase_Header: Header phase + * @arg CRYP_Phase_Payload: Payload phase + * @arg CRYP_Phase_Final: Final phase + * @retval None + */ +void CRYP_PhaseConfig(uint32_t CRYP_Phase) +{ uint32_t tempcr = 0; + + /* Check the parameter */ + assert_param(IS_CRYP_PHASE(CRYP_Phase)); + + /* Get the CR register */ + tempcr = CRYP->CR; + + /* Reset the phase configuration bits: GCMP_CCMPH */ + tempcr &= (uint32_t)(~CRYP_CR_GCM_CCMPH); + /* Set the selected phase */ + tempcr |= (uint32_t)CRYP_Phase; + + /* Set the CR register */ + CRYP->CR = tempcr; +} + /** * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the * FIFOs are reset) @@ -392,12 +425,12 @@ void CRYP_Cmd(FunctionalState NewState) * @verbatim =============================================================================== - CRYP Data processing functions + ##### CRYP Data processing functions ##### =============================================================================== - This section provides functions allowing the encryption and decryption - operations: - - Enter data to be treated in the IN FIFO : using CRYP_DataIn() function. - - Get the data result from the OUT FIFO : using CRYP_DataOut() function. + [..] This section provides functions allowing the encryption and decryption + operations: + (+) Enter data to be treated in the IN FIFO : using CRYP_DataIn() function. + (+) Get the data result from the OUT FIFO : using CRYP_DataOut() function. @endverbatim * @{ @@ -433,20 +466,18 @@ uint32_t CRYP_DataOut(void) * @verbatim =============================================================================== - Context swapping functions + ##### Context swapping functions ##### =============================================================================== + [..] This section provides functions allowing to save and store CRYP Context - This section provides functions allowing to save and store CRYP Context - - It is possible to interrupt an encryption/ decryption/ key generation process - to perform another processing with a higher priority, and to complete the - interrupted process later on, when the higher-priority task is complete. To do - so, the context of the interrupted task must be saved from the CRYP registers - to memory, and then be restored from memory to the CRYP registers. + [..] It is possible to interrupt an encryption/ decryption/ key generation process + to perform another processing with a higher priority, and to complete the + interrupted process later on, when the higher-priority task is complete. To do + so, the context of the interrupted task must be saved from the CRYP registers + to memory, and then be restored from memory to the CRYP registers. - 1. To save the current context, use CRYP_SaveContext() function - 2. To restore the saved context, use CRYP_RestoreContext() function - + (#) To save the current context, use CRYP_SaveContext() function + (#) To restore the saved context, use CRYP_RestoreContext() function @endverbatim * @{ @@ -506,11 +537,12 @@ ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN; CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN; - /* Save the current configuration (bits [9:2] in the CRYP_CR register) */ - CRYP_ContextSave->CR_bits9to2 = CRYP->CR & (CRYP_CR_KEYSIZE | - CRYP_CR_DATATYPE | - CRYP_CR_ALGOMODE | - CRYP_CR_ALGODIR); + /* Save the current configuration (bit 19, bit[17:16] and bits [9:2] in the CRYP_CR register) */ + CRYP_ContextSave->CR_CurrentConfig = CRYP->CR & (CRYP_CR_GCM_CCMPH | + CRYP_CR_KEYSIZE | + CRYP_CR_DATATYPE | + CRYP_CR_ALGOMODE | + CRYP_CR_ALGODIR); /* and, if not in ECB mode, the initialization vectors. */ CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR; @@ -528,6 +560,25 @@ ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; + /* Save the content of context swap registers */ + CRYP_ContextSave->CRYP_CSGCMCCMR[0] = CRYP->CSGCMCCM0R; + CRYP_ContextSave->CRYP_CSGCMCCMR[1] = CRYP->CSGCMCCM1R; + CRYP_ContextSave->CRYP_CSGCMCCMR[2] = CRYP->CSGCMCCM2R; + CRYP_ContextSave->CRYP_CSGCMCCMR[3] = CRYP->CSGCMCCM3R; + CRYP_ContextSave->CRYP_CSGCMCCMR[4] = CRYP->CSGCMCCM4R; + CRYP_ContextSave->CRYP_CSGCMCCMR[5] = CRYP->CSGCMCCM5R; + CRYP_ContextSave->CRYP_CSGCMCCMR[6] = CRYP->CSGCMCCM6R; + CRYP_ContextSave->CRYP_CSGCMCCMR[7] = CRYP->CSGCMCCM7R; + + CRYP_ContextSave->CRYP_CSGCMR[0] = CRYP->CSGCM0R; + CRYP_ContextSave->CRYP_CSGCMR[1] = CRYP->CSGCM1R; + CRYP_ContextSave->CRYP_CSGCMR[2] = CRYP->CSGCM2R; + CRYP_ContextSave->CRYP_CSGCMR[3] = CRYP->CSGCM3R; + CRYP_ContextSave->CRYP_CSGCMR[4] = CRYP->CSGCM4R; + CRYP_ContextSave->CRYP_CSGCMR[5] = CRYP->CSGCM5R; + CRYP_ContextSave->CRYP_CSGCMR[6] = CRYP->CSGCM6R; + CRYP_ContextSave->CRYP_CSGCMR[7] = CRYP->CSGCM7R; + /* When needed, save the DMA status (pointers for IN and OUT messages, number of remaining bytes, etc.) */ @@ -552,7 +603,7 @@ void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) { /* Configure the processor with the saved configuration */ - CRYP->CR = CRYP_ContextRestore->CR_bits9to2; + CRYP->CR = CRYP_ContextRestore->CR_CurrentConfig; /* restore The key value */ CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; @@ -570,6 +621,25 @@ void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR; CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR; + /* Restore the content of context swap registers */ + CRYP->CSGCMCCM0R = CRYP_ContextRestore->CRYP_CSGCMCCMR[0]; + CRYP->CSGCMCCM1R = CRYP_ContextRestore->CRYP_CSGCMCCMR[1]; + CRYP->CSGCMCCM2R = CRYP_ContextRestore->CRYP_CSGCMCCMR[2]; + CRYP->CSGCMCCM3R = CRYP_ContextRestore->CRYP_CSGCMCCMR[3]; + CRYP->CSGCMCCM4R = CRYP_ContextRestore->CRYP_CSGCMCCMR[4]; + CRYP->CSGCMCCM5R = CRYP_ContextRestore->CRYP_CSGCMCCMR[5]; + CRYP->CSGCMCCM6R = CRYP_ContextRestore->CRYP_CSGCMCCMR[6]; + CRYP->CSGCMCCM7R = CRYP_ContextRestore->CRYP_CSGCMCCMR[7]; + + CRYP->CSGCM0R = CRYP_ContextRestore->CRYP_CSGCMR[0]; + CRYP->CSGCM1R = CRYP_ContextRestore->CRYP_CSGCMR[1]; + CRYP->CSGCM2R = CRYP_ContextRestore->CRYP_CSGCMR[2]; + CRYP->CSGCM3R = CRYP_ContextRestore->CRYP_CSGCMR[3]; + CRYP->CSGCM4R = CRYP_ContextRestore->CRYP_CSGCMR[4]; + CRYP->CSGCM5R = CRYP_ContextRestore->CRYP_CSGCMR[5]; + CRYP->CSGCM6R = CRYP_ContextRestore->CRYP_CSGCMR[6]; + CRYP->CSGCM7R = CRYP_ContextRestore->CRYP_CSGCMR[7]; + /* Enable the cryptographic processor */ CRYP->CR |= CRYP_CR_CRYPEN; } @@ -582,18 +652,17 @@ void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) * @verbatim =============================================================================== - CRYP's DMA interface Configuration function + ##### CRYP's DMA interface Configuration function ##### =============================================================================== - - This section provides functions allowing to configure the DMA interface for - CRYP data input and output transfer. + [..] This section provides functions allowing to configure the DMA interface for + CRYP data input and output transfer. - When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be - transferred: - - From memory to the CRYP IN FIFO using the DMA peripheral by enabling - the CRYP_DMAReq_DataIN request. - - From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling - the CRYP_DMAReq_DataOUT request. + [..] When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be + transferred: + (+) From memory to the CRYP IN FIFO using the DMA peripheral by enabling + the CRYP_DMAReq_DataIN request. + (+) From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling + the CRYP_DMAReq_DataOUT request. @endverbatim * @{ @@ -635,90 +704,83 @@ void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState) * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== + + [..] This section provides functions allowing to configure the CRYP Interrupts and + to get the status and Interrupts pending bits. - This section provides functions allowing to configure the CRYP Interrupts and - to get the status and Interrupts pending bits. - - The CRYP provides 2 Interrupts sources and 7 Flags: + [..] The CRYP provides 2 Interrupts sources and 7 Flags: - Flags : - ------- - - 1. CRYP_FLAG_IFEM : Set when Input FIFO is empty. - This Flag is cleared only by hardware. + *** Flags : *** + =============== + [..] + (#) CRYP_FLAG_IFEM : Set when Input FIFO is empty. This Flag is cleared only + by hardware. - 2. CRYP_FLAG_IFNF : Set when Input FIFO is not full. - This Flag is cleared only by hardware. + (#) CRYP_FLAG_IFNF : Set when Input FIFO is not full. This Flag is cleared + only by hardware. - 3. CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending - it gives the raw interrupt state prior to masking - of the input FIFO service interrupt. - This Flag is cleared only by hardware. + (#) CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending it gives + the raw interrupt state prior to masking of the input FIFO service interrupt. + This Flag is cleared only by hardware. - 4. CRYP_FLAG_OFNE : Set when Output FIFO not empty. - This Flag is cleared only by hardware. + (#) CRYP_FLAG_OFNE : Set when Output FIFO not empty. This Flag is cleared + only by hardware. - 5. CRYP_FLAG_OFFU : Set when Output FIFO is full. - This Flag is cleared only by hardware. + (#) CRYP_FLAG_OFFU : Set when Output FIFO is full. This Flag is cleared only + by hardware. - 6. CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending - it gives the raw interrupt state prior to masking - of the output FIFO service interrupt. - This Flag is cleared only by hardware. + (#) CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending it gives + the raw interrupt state prior to masking of the output FIFO service interrupt. + This Flag is cleared only by hardware. - 7. CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a - block of data or a key preparation (for AES - decryption). - This Flag is cleared only by hardware. - To clear it, the CRYP core must be disabled and the - last processing has completed. - - Interrupts : - ------------ + (#) CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a block + of data or a key preparation (for AES decryption). This Flag is cleared + only by hardware. To clear it, the CRYP core must be disabled and the last + processing has completed. - 1. CRYP_IT_INI : The input FIFO service interrupt is asserted when there - are less than 4 words in the input FIFO. - This interrupt is associated to CRYP_FLAG_INRIS flag. + *** Interrupts : *** + ==================== + [..] + (#) CRYP_IT_INI : The input FIFO service interrupt is asserted when there + are less than 4 words in the input FIFO. This interrupt is associated to + CRYP_FLAG_INRIS flag. - @note This interrupt is cleared by performing write operations - to the input FIFO until it holds 4 or more words. The - input FIFO service interrupt INMIS is enabled with the - CRYP enable bit. Consequently, when CRYP is disabled, the - INMIS signal is low even if the input FIFO is empty. + -@- This interrupt is cleared by performing write operations to the input FIFO + until it holds 4 or more words. The input FIFO service interrupt INMIS is + enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the + INMIS signal is low even if the input FIFO is empty. - 2. CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there - is one or more (32-bit word) data items in the output FIFO. - This interrupt is associated to CRYP_FLAG_OUTRIS flag. + (#) CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there + is one or more (32-bit word) data items in the output FIFO. This interrupt + is associated to CRYP_FLAG_OUTRIS flag. - @note This interrupt is cleared by reading data from the output - FIFO until there is no valid (32-bit) word left (that is, - the interrupt follows the state of the OFNE (output FIFO - not empty) flag). + -@- This interrupt is cleared by reading data from the output FIFO until there + is no valid (32-bit) word left (that is, the interrupt follows the state + of the OFNE (output FIFO not empty) flag). + *** Managing the CRYP controller events : *** + ============================================= + [..] The user should identify which mode will be used in his application to manage + the CRYP controller events: Polling mode or Interrupt mode. - Managing the CRYP controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the CRYP controller events: Polling mode or Interrupt mode. + (#) In the Polling Mode it is advised to use the following functions: + (++) CRYP_GetFlagStatus() : to check if flags events occur. - 1. In the Polling Mode it is advised to use the following functions: - - CRYP_GetFlagStatus() : to check if flags events occur. + -@@- The CRYPT flags do not need to be cleared since they are cleared as + soon as the associated event are reset. - @note The CRYPT flags do not need to be cleared since they are cleared as - soon as the associated event are reset. + (#) In the Interrupt Mode it is advised to use the following functions: + (++) CRYP_ITConfig() : to enable or disable the interrupt source. + (++) CRYP_GetITStatus() : to check if Interrupt occurs. - 2. In the Interrupt Mode it is advised to use the following functions: - - CRYP_ITConfig() : to enable or disable the interrupt source. - - CRYP_GetITStatus() : to check if Interrupt occurs. - - @note The CRYPT interrupts have no pending bits, the interrupt is cleared as - soon as the associated event is reset. + -@@- The CRYPT interrupts have no pending bits, the interrupt is cleared as + soon as the associated event is reset. @endverbatim * @{ @@ -783,6 +845,28 @@ ITStatus CRYP_GetITStatus(uint8_t CRYP_IT) return bitstatus; } +/** + * @brief Returns whether CRYP peripheral is enabled or disabled. + * @param none. + * @retval Current state of the CRYP peripheral (ENABLE or DISABLE). + */ +FunctionalState CRYP_GetCmdStatus(void) +{ + FunctionalState state = DISABLE; + + if ((CRYP->CR & CRYP_CR_CRYPEN) != 0) + { + /* CRYPEN bit is set */ + state = ENABLE; + } + else + { + /* CRYPEN bit is reset */ + state = DISABLE; + } + return state; +} + /** * @brief Checks whether the specified CRYP flag is set or not. * @param CRYP_FLAG: specifies the CRYP flag to check. @@ -847,4 +931,4 @@ FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c index 286680979b..a9ee8390aa 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c @@ -2,43 +2,52 @@ ****************************************************************************** * @file stm32f4xx_cryp_aes.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides high level functions to encrypt and decrypt an - * input message using AES in ECB/CBC/CTR modes. + * input message using AES in ECB/CBC/CTR/GCM/CCM modes. * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP * peripheral. + * AES-ECB/CBC/CTR/GCM/CCM modes are available on STM32F437x Devices. + * For STM32F41xx Devices, only AES-ECB/CBC/CTR modes are available. * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The CRYP controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - * - * 2. Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() - * function. +@verbatim + =================================================================== + ##### How to use this driver ##### + =================================================================== + [..] + (#) Enable The CRYP controller clock using + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. + + (#) Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() function. + + (#) Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() function. + + (#) Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() function. + + (#) Encrypt and decrypt using AES in GCM Mode using CRYP_AES_GCM() function. + + (#) Encrypt and decrypt using AES in CCM Mode using CRYP_AES_CCM() function. + +@endverbatim * - * 3. Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() - * function. + ****************************************************************************** + * @attention * - * 4. Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() - * function. + *

    © COPYRIGHT 2013 STMicroelectronics

    * - * @endverbatim + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -72,10 +81,9 @@ * @verbatim =============================================================================== - High Level AES functions + ##### High Level AES functions ##### =============================================================================== - @endverbatim * @{ */ @@ -214,6 +222,13 @@ ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize, /* Enable Crypto processor */ CRYP_Cmd(ENABLE); + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + for(i=0; ((i>32)); + CRYP_DataIn(__REV(headerlength)); + CRYP_DataIn(__REV(inputlength>>32)); + CRYP_DataIn(__REV(inputlength)); + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + tagaddr = (uint32_t)AuthTAG; + /* Read the Auth TAG in the IN FIFO */ + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + } + /*------------------ AES Decryption ------------------*/ + else /* AES decryption */ + { + /* Flush IN/OUT FIFOs */ + CRYP_FIFOFlush(); + + /* Key Initialisation */ + CRYP_KeyInit(&AES_CRYP_KeyInitStructure); + + /* CRYP Initialization Vectors */ + CRYP_IVInit(&AES_CRYP_IVInitStructure); + + /* Crypto Init for Key preparation for decryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_GCM; + AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&AES_CRYP_InitStructure); + + /***************************** Init phase *********************************/ + /* Select init phase */ + CRYP_PhaseConfig(CRYP_Phase_Init); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + /* Wait for CRYPEN bit to be 0 */ + while(CRYP_GetCmdStatus() == ENABLE) + { + } + + /***************************** header phase *******************************/ + if(HLength != 0) + { + /* Select header phase */ + CRYP_PhaseConfig(CRYP_Phase_Header); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + for(loopcounter = 0; (loopcounter < HLength); loopcounter+=16) + { + /* Wait until the IFEM flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) + { + } + + /* Write the Input block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + } + + /* Wait until the complete message has been processed */ + counter = 0; + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + } + + /**************************** payload phase *******************************/ + if(ILength != 0) + { + /* Select payload phase */ + CRYP_PhaseConfig(CRYP_Phase_Payload); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) + { + /* Wait until the IFEM flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) + { + } + /* Write the Input block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + + /* Wait until the complete message has been processed */ + counter = 0; + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + else + { + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + /* Read the Output block from the Output FIFO */ + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + } + } + } + + /***************************** final phase ********************************/ + /* Select final phase */ + CRYP_PhaseConfig(CRYP_Phase_Final); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + /* Write number of bits concatenated with header in the IN FIFO */ + CRYP_DataIn(__REV(headerlength>>32)); + CRYP_DataIn(__REV(headerlength)); + CRYP_DataIn(__REV(inputlength>>32)); + CRYP_DataIn(__REV(inputlength)); + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + tagaddr = (uint32_t)AuthTAG; + /* Read the Auth TAG in the IN FIFO */ + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + *(uint32_t*)(tagaddr) = CRYP_DataOut(); + tagaddr+=4; + } + /* Disable Crypto */ + CRYP_Cmd(DISABLE); + + return status; +} + +/** + * @brief Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes + * are available only on STM32F437x Devices. + * @param Mode: encryption or decryption Mode. + * This parameter can be one of the following values: + * @arg MODE_ENCRYPT: Encryption + * @arg MODE_DECRYPT: Decryption + * @param Nonce: the nounce used for AES algorithm. It shall be unique for each processing. + * @param Key: Key used for AES algorithm. + * @param Keysize: length of the Key, must be a 128, 192 or 256. + * @param Input: pointer to the Input buffer. + * @param Ilength: length of the Input buffer in bytes, must be a multiple of 16. + * @param Header: pointer to the header buffer. + * @param Hlength: length of the header buffer in bytes. + * @param HBuffer: pointer to temporary buffer used to append the header + * HBuffer size must be equal to Hlength + 21 + * @param Output: pointer to the returned buffer. + * @param AuthTAG: pointer to the authentication TAG buffer. + * @param TAGSize: the size of the TAG (called also MAC). + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Operation done + * - ERROR: Operation failed + */ +ErrorStatus CRYP_AES_CCM(uint8_t Mode, + uint8_t* Nonce, uint32_t NonceSize, + uint8_t *Key, uint16_t Keysize, + uint8_t *Input, uint32_t ILength, + uint8_t *Header, uint32_t HLength, uint8_t *HBuffer, + uint8_t *Output, + uint8_t *AuthTAG, uint32_t TAGSize) +{ + CRYP_InitTypeDef AES_CRYP_InitStructure; + CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; + CRYP_IVInitTypeDef AES_CRYP_IVInitStructure; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t keyaddr = (uint32_t)Key; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + uint32_t headeraddr = (uint32_t)Header; + uint32_t tagaddr = (uint32_t)AuthTAG; + uint32_t headersize = HLength; + uint32_t loopcounter = 0; + uint32_t bufferidx = 0; + uint8_t blockb0[16] = {0};/* Block B0 */ + uint8_t ctr[16] = {0}; /* Counter */ + uint32_t temptag[4] = {0}; /* temporary TAG (MAC) */ + uint32_t ctraddr = (uint32_t)ctr; + uint32_t b0addr = (uint32_t)blockb0; + + /************************ Formatting the header block ***********************/ + if(headersize != 0) + { + /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ + if(headersize < 65280) + { + HBuffer[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF); + HBuffer[bufferidx++] = (uint8_t) ((headersize) & 0xFF); + headersize += 2; + } + else + { + /* header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ + HBuffer[bufferidx++] = 0xFF; + HBuffer[bufferidx++] = 0xFE; + HBuffer[bufferidx++] = headersize & 0xff000000; + HBuffer[bufferidx++] = headersize & 0x00ff0000; + HBuffer[bufferidx++] = headersize & 0x0000ff00; + HBuffer[bufferidx++] = headersize & 0x000000ff; + headersize += 6; + } + /* Copy the header buffer in internal buffer "HBuffer" */ + for(loopcounter = 0; loopcounter < headersize; loopcounter++) + { + HBuffer[bufferidx++] = Header[loopcounter]; + } + /* Check if the header size is modulo 16 */ + if ((headersize % 16) != 0) + { + /* Padd the header buffer with 0s till the HBuffer length is modulo 16 */ + for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++) + { + HBuffer[loopcounter] = 0; + } + /* Set the header size to modulo 16 */ + headersize = ((headersize/16) + 1) * 16; + } + /* set the pointer headeraddr to HBuffer */ + headeraddr = (uint32_t)HBuffer; + } + /************************* Formatting the block B0 **************************/ + if(headersize != 0) + { + blockb0[0] = 0x40; + } + /* Flags byte */ + blockb0[0] |= 0u | (((( (uint8_t) TAGSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - NonceSize) - 1) & 0x07); + + for (loopcounter = 0; loopcounter < NonceSize; loopcounter++) + { + blockb0[loopcounter+1] = Nonce[loopcounter]; + } + for ( ; loopcounter < 13; loopcounter++) + { + blockb0[loopcounter+1] = 0; + } + + blockb0[14] = ((ILength >> 8) & 0xFF); + blockb0[15] = (ILength & 0xFF); + + /************************* Formatting the initial counter *******************/ + /* Byte 0: + Bits 7 and 6 are reserved and shall be set to 0 + Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks + are distinct from B0 + Bits 0, 1, and 2 contain the same encoding of q as in B0 + */ + ctr[0] = blockb0[0] & 0x07; + /* byte 1 to NonceSize is the IV (Nonce) */ + for(loopcounter = 1; loopcounter < NonceSize + 1; loopcounter++) + { + ctr[loopcounter] = blockb0[loopcounter]; + } + /* Set the LSB to 1 */ + ctr[15] |= 0x01; + + /* Crypto structures initialisation*/ + CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); + + switch(Keysize) + { + case 128: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + case 192: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; + AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + case 256: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; + AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + default: + break; + } + + /* CRYP Initialization Vectors */ + AES_CRYP_IVInitStructure.CRYP_IV0Left = (__REV(*(uint32_t*)(ctraddr))); + ctraddr+=4; + AES_CRYP_IVInitStructure.CRYP_IV0Right= (__REV(*(uint32_t*)(ctraddr))); + ctraddr+=4; + AES_CRYP_IVInitStructure.CRYP_IV1Left = (__REV(*(uint32_t*)(ctraddr))); + ctraddr+=4; + AES_CRYP_IVInitStructure.CRYP_IV1Right= (__REV(*(uint32_t*)(ctraddr))); + + /*------------------ AES Encryption ------------------*/ + if(Mode == MODE_ENCRYPT) /* AES encryption */ + { + /* Flush IN/OUT FIFOs */ + CRYP_FIFOFlush(); + + /* Key Initialisation */ + CRYP_KeyInit(&AES_CRYP_KeyInitStructure); + + /* CRYP Initialization Vectors */ + CRYP_IVInit(&AES_CRYP_IVInitStructure); + + /* Crypto Init for Key preparation for decryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM; + AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&AES_CRYP_InitStructure); + + /***************************** Init phase *********************************/ + /* Select init phase */ + CRYP_PhaseConfig(CRYP_Phase_Init); + + b0addr = (uint32_t)blockb0; + /* Write the blockb0 block in the IN FIFO */ + CRYP_DataIn((*(uint32_t*)(b0addr))); + b0addr+=4; + CRYP_DataIn((*(uint32_t*)(b0addr))); + b0addr+=4; + CRYP_DataIn((*(uint32_t*)(b0addr))); + b0addr+=4; + CRYP_DataIn((*(uint32_t*)(b0addr))); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + /* Wait for CRYPEN bit to be 0 */ + while(CRYP_GetCmdStatus() == ENABLE) + { + } + /***************************** header phase *******************************/ + if(headersize != 0) + { + /* Select header phase */ + CRYP_PhaseConfig(CRYP_Phase_Header); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) + { + /* Wait until the IFEM flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) + { + } + + /* Write the Input block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + } + + /* Wait until the complete message has been processed */ + counter = 0; + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + } + + /**************************** payload phase *******************************/ + if(ILength != 0) + { + /* Select payload phase */ + CRYP_PhaseConfig(CRYP_Phase_Payload); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) + { + /* Wait until the IFEM flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) + { + } + + /* Write the Input block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + + /* Wait until the complete message has been processed */ + counter = 0; + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + else + { + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + /* Read the Output block from the Output FIFO */ + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + } + } + } + + /***************************** final phase ********************************/ + /* Select final phase */ + CRYP_PhaseConfig(CRYP_Phase_Final); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + ctraddr = (uint32_t)ctr; + /* Write the counter block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(ctraddr)); + ctraddr+=4; + CRYP_DataIn(*(uint32_t*)(ctraddr)); + ctraddr+=4; + CRYP_DataIn(*(uint32_t*)(ctraddr)); + ctraddr+=4; + /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */ + CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff); + + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + /* Read the Auth TAG in the IN FIFO */ + temptag[0] = CRYP_DataOut(); + temptag[1] = CRYP_DataOut(); + temptag[2] = CRYP_DataOut(); + temptag[3] = CRYP_DataOut(); + } + /*------------------ AES Decryption ------------------*/ + else /* AES decryption */ + { + /* Flush IN/OUT FIFOs */ + CRYP_FIFOFlush(); + + /* Key Initialisation */ + CRYP_KeyInit(&AES_CRYP_KeyInitStructure); + + /* CRYP Initialization Vectors */ + CRYP_IVInit(&AES_CRYP_IVInitStructure); + + /* Crypto Init for Key preparation for decryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM; + AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&AES_CRYP_InitStructure); + + /***************************** Init phase *********************************/ + /* Select init phase */ + CRYP_PhaseConfig(CRYP_Phase_Init); + + b0addr = (uint32_t)blockb0; + /* Write the blockb0 block in the IN FIFO */ + CRYP_DataIn((*(uint32_t*)(b0addr))); + b0addr+=4; + CRYP_DataIn((*(uint32_t*)(b0addr))); + b0addr+=4; + CRYP_DataIn((*(uint32_t*)(b0addr))); + b0addr+=4; + CRYP_DataIn((*(uint32_t*)(b0addr))); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + /* Wait for CRYPEN bit to be 0 */ + while(CRYP_GetCmdStatus() == ENABLE) + { + } + + /***************************** header phase *******************************/ + if(headersize != 0) + { + /* Select header phase */ + CRYP_PhaseConfig(CRYP_Phase_Header); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) + { + /* Wait until the IFEM flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) + { + } + + /* Write the Input block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + CRYP_DataIn(*(uint32_t*)(headeraddr)); + headeraddr+=4; + } + + /* Wait until the complete message has been processed */ + counter = 0; + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + } + + /**************************** payload phase *******************************/ + if(ILength != 0) + { + /* Select payload phase */ + CRYP_PhaseConfig(CRYP_Phase_Payload); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) + { + /* Wait until the IFEM flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) + { + } + + /* Write the Input block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + CRYP_DataIn(*(uint32_t*)(inputaddr)); + inputaddr+=4; + + /* Wait until the complete message has been processed */ + counter = 0; + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + else + { + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + /* Read the Output block from the Output FIFO */ + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + *(uint32_t*)(outputaddr) = CRYP_DataOut(); + outputaddr+=4; + } + } + } + + /***************************** final phase ********************************/ + /* Select final phase */ + CRYP_PhaseConfig(CRYP_Phase_Final); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } + + ctraddr = (uint32_t)ctr; + /* Write the counter block in the IN FIFO */ + CRYP_DataIn(*(uint32_t*)(ctraddr)); + ctraddr+=4; + CRYP_DataIn(*(uint32_t*)(ctraddr)); + ctraddr+=4; + CRYP_DataIn(*(uint32_t*)(ctraddr)); + ctraddr+=4; + /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */ + CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff); + + /* Wait until the OFNE flag is reset */ + while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) + { + } + + /* Read the Authentaication TAG (MAC) in the IN FIFO */ + temptag[0] = CRYP_DataOut(); + temptag[1] = CRYP_DataOut(); + temptag[2] = CRYP_DataOut(); + temptag[3] = CRYP_DataOut(); + } + + /* Copy temporary authentication TAG in user TAG buffer */ + for(loopcounter = 0; (loopcounter < TAGSize); loopcounter++) + { + /* Set the authentication TAG buffer */ + *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter); + } + + /* Disable Crypto */ + CRYP_Cmd(DISABLE); + + return status; +} + /** * @} */ @@ -634,5 +1703,5 @@ ErrorStatus CRYP_AES_CTR(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c index 7b4c47b805..84db6d0a18 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c @@ -2,40 +2,45 @@ ****************************************************************************** * @file stm32f4xx_cryp_des.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides high level functions to encrypt and decrypt an * input message using DES in ECB/CBC modes. * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP * peripheral. * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The CRYP controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. +@verbatim + + =================================================================== + ##### How to use this driver ##### + =================================================================== + [..] + (#) Enable The CRYP controller clock using + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. + + (#) Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB() function. + + (#) Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC() function. + +@endverbatim * - * 2. Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB() - * function. + ****************************************************************************** + * @attention * - * 3. Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC() - * function. + *

    © COPYRIGHT 2013 STMicroelectronics

    * - * @endverbatim + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -71,7 +76,7 @@ * @verbatim =============================================================================== - High Level DES functions + ##### High Level DES functions ##### =============================================================================== @endverbatim * @{ @@ -133,6 +138,12 @@ ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, /* Enable Crypto processor */ CRYP_Cmd(ENABLE); + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } for(i=0; ((i
    © COPYRIGHT 2013 STMicroelectronics
    * - * @endverbatim + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -71,10 +76,9 @@ * @verbatim =============================================================================== - High Level TDES functions + ##### High Level TDES functions ##### =============================================================================== - @endverbatim * @{ */ @@ -143,6 +147,12 @@ ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, /* Enable Crypto processor */ CRYP_Cmd(ENABLE); + if(CRYP_GetCmdStatus() == DISABLE) + { + /* The CRYP peripheral clock is not enabled or the device doesn't embedd + the CRYP peripheral (please check the device sales type. */ + return(ERROR); + } for(i=0; ((i
    © COPYRIGHT 2013 STMicroelectronics
    * - * DMA requests - * ============= - * A DMA1 request can be generated when an external trigger (but not - * a software trigger) occurs if DMA1 requests are enabled using - * DAC_DMACmd() - * DMA1 requests are mapped as following: - * 1- DAC channel1 : mapped on DMA1 Stream5 channel7 which must be - * already configured - * 2- DAC channel2 : mapped on DMA1 Stream6 channel7 which must be - * already configured + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - * =================================================================== - * How to use this driver - * =================================================================== - * - DAC APB clock must be enabled to get write access to DAC - * registers using - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE) - * - Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. - * - Configure the DAC channel using DAC_Init() function - * - Enable the DAC channel using DAC_Cmd() function - * - * @endverbatim - * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -159,7 +172,7 @@ * @verbatim =============================================================================== - DAC channels configuration: trigger, output buffer, data format + ##### DAC channels configuration: trigger, output buffer, data format ##### =============================================================================== @endverbatim @@ -471,7 +484,7 @@ uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) * @verbatim =============================================================================== - DMA management functions + ##### DMA management functions ##### =============================================================================== @endverbatim @@ -520,7 +533,7 @@ void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim @@ -698,4 +711,4 @@ void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c index b81dff46c5..18f97b44d6 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c @@ -2,20 +2,26 @@ ****************************************************************************** * @file stm32f4xx_dbgmcu.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides all the DBGMCU firmware functions. ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -171,4 +177,4 @@ void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c index 3ffc36d7cc..f797c2783e 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c @@ -2,79 +2,83 @@ ****************************************************************************** * @file stm32f4xx_dcmi.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the DCMI peripheral: - * - Initialization and Configuration - * - Image capture functions - * - Interrupts and flags management + * + Initialization and Configuration + * + Image capture functions + * + Interrupts and flags management * - * @verbatim - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * The sequence below describes how to use this driver to capture image - * from a camera module connected to the DCMI Interface. - * This sequence does not take into account the configuration of the - * camera module, which should be made before to configure and enable - * the DCMI to capture images. - * - * 1. Enable the clock for the DCMI and associated GPIOs using the following functions: - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - * 2. DCMI pins configuration - * - Connect the involved DCMI pins to AF13 using the following function - * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); - * - Configure these DCMI pins in alternate function mode by calling the function - * GPIO_Init(); - * - * 3. Declare a DCMI_InitTypeDef structure, for example: - * DCMI_InitTypeDef DCMI_InitStructure; - * and fill the DCMI_InitStructure variable with the allowed values - * of the structure member. - * - * 4. Initialize the DCMI interface by calling the function - * DCMI_Init(&DCMI_InitStructure); - * - * 5. Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR - * register to the destination memory buffer. - * - * 6. Enable DCMI interface using the function - * DCMI_Cmd(ENABLE); - * - * 7. Start the image capture using the function - * DCMI_CaptureCmd(ENABLE); - * - * 8. At this stage the DCMI interface waits for the first start of frame, - * then a DMA request is generated continuously/once (depending on the - * mode used, Continuous/Snapshot) to transfer the received data into - * the destination memory. - * - * @note If you need to capture only a rectangular window from the received - * image, you have to use the DCMI_CROPConfig() function to configure - * the coordinates and size of the window to be captured, then enable - * the Crop feature using DCMI_CROPCmd(ENABLE); - * In this case, the Crop configuration should be made before to enable - * and start the DCMI interface. - * - * @endverbatim - * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The sequence below describes how to use this driver to capture image + from a camera module connected to the DCMI Interface. + This sequence does not take into account the configuration of the + camera module, which should be made before to configure and enable + the DCMI to capture images. + + (#) Enable the clock for the DCMI and associated GPIOs using the following + functions: + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) DCMI pins configuration + (++) Connect the involved DCMI pins to AF13 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); + (++) Configure these DCMI pins in alternate function mode by calling + the function GPIO_Init(); + + (#) Declare a DCMI_InitTypeDef structure, for example: + DCMI_InitTypeDef DCMI_InitStructure; + and fill the DCMI_InitStructure variable with the allowed values + of the structure member. + + (#) Initialize the DCMI interface by calling the function + DCMI_Init(&DCMI_InitStructure); + + (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR + register to the destination memory buffer. + + (#) Enable DCMI interface using the function + DCMI_Cmd(ENABLE); + + (#) Start the image capture using the function + DCMI_CaptureCmd(ENABLE); + + (#) At this stage the DCMI interface waits for the first start of frame, + then a DMA request is generated continuously/once (depending on the + mode used, Continuous/Snapshot) to transfer the received data into + the destination memory. + + -@- If you need to capture only a rectangular window from the received + image, you have to use the DCMI_CROPConfig() function to configure + the coordinates and size of the window to be captured, then enable + the Crop feature using DCMI_CROPCmd(ENABLE); + In this case, the Crop configuration should be made before to enable + and start the DCMI interface. + + @endverbatim ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -107,7 +111,7 @@ * @verbatim =============================================================================== - Initialization and Configuration functions + ##### Initialization and Configuration functions ##### =============================================================================== @endverbatim @@ -279,7 +283,7 @@ void DCMI_JPEGCmd(FunctionalState NewState) * @verbatim =============================================================================== - Image capture functions + ##### Image capture functions ##### =============================================================================== @endverbatim @@ -350,7 +354,7 @@ uint32_t DCMI_ReadData(void) * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim @@ -418,7 +422,7 @@ FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG) /* Get the DCMI register index */ dcmireg = (((uint16_t)DCMI_FLAG) >> 12); - if (dcmireg == 0x01) /* The FLAG is in RISR register */ + if (dcmireg == 0x00) /* The FLAG is in RISR register */ { tempreg= DCMI->RISR; } @@ -531,4 +535,4 @@ void DCMI_ClearITPendingBit(uint16_t DCMI_IT) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c index c2868cff25..03b983c482 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c @@ -2,113 +2,121 @@ ****************************************************************************** * @file stm32f4xx_dma.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Direct Memory Access controller (DMA): - * - Initialization and Configuration - * - Data Counter - * - Double Buffer mode configuration and command - * - Interrupts and flags management + * + Initialization and Configuration + * + Data Counter + * + Double Buffer mode configuration and command + * + Interrupts and flags management * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) - * function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) - * function for DMA2. - * - * 2. Enable and configure the peripheral to be connected to the DMA Stream - * (except for internal SRAM / FLASH memories: no initialization is - * necessary). - * - * 3. For a given Stream, program the required configuration through following parameters: - * Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination - * data formats, Circular or Normal mode, Stream Priority level, Source and Destination - * Incrementation mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or - * Destination (if needed) using the DMA_Init() function. - * To avoid filling un-nesecessary fields, you can call DMA_StructInit() function - * to initialize a given structure with default values (reset values), the modify - * only necessary fields (ie. Source and Destination addresses, Transfer size and Data Formats). - * - * 4. Enable the NVIC and the corresponding interrupt(s) using the function - * DMA_ITConfig() if you need to use DMA interrupts. + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) + function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) + function for DMA2. + + (#) Enable and configure the peripheral to be connected to the DMA Stream + (except for internal SRAM / FLASH memories: no initialization is + necessary). + + (#) For a given Stream, program the required configuration through following parameters: + Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination + data formats, Circular or Normal mode, Stream Priority level, Source and Destination + Incrementation mode, FIFO mode and its Threshold (if needed), Burst + mode for Source and/or Destination (if needed) using the DMA_Init() function. + To avoid filling unneccessary fields, you can call DMA_StructInit() function + to initialize a given structure with default values (reset values), the modify + only necessary fields + (ie. Source and Destination addresses, Transfer size and Data Formats). + + (#) Enable the NVIC and the corresponding interrupt(s) using the function + DMA_ITConfig() if you need to use DMA interrupts. + + (#) Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring + the second Memory address and the first Memory to be used through the function + DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function + DMA_DoubleBufferModeCmd(). These operations must be done before step 6. + + (#) Enable the DMA stream using the DMA_Cmd() function. + + (#) Activate the needed Stream Request using PPP_DMACmd() function for + any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) + The function allowing this operation is provided in each PPP peripheral + driver (ie. SPI_DMACmd for SPI peripheral). + Once the Stream is enabled, it is not possible to modify its configuration + unless the stream is stopped and disabled. + After enabling the Stream, it is advised to monitor the EN bit status using + the function DMA_GetCmdStatus(). In case of configuration errors or bus errors + this bit will remain reset and all transfers on this Stream will remain on hold. + + (#) Optionally, you can configure the number of data to be transferred + when the Stream is disabled (ie. after each Transfer Complete event + or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). + And you can get the number of remaining data to be transferred using + the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is + enabled and running). + + (#) To control DMA events you can use one of the following two methods: + (##) Check on DMA Stream flags using the function DMA_GetFlagStatus(). + (##) Use DMA interrupts through the function DMA_ITConfig() at initialization + phase and DMA_GetITStatus() function into interrupt routines in + communication phase. + [..] + After checking on a flag you should clear it using DMA_ClearFlag() + function. And after checking on an interrupt event you should + clear it using DMA_ClearITPendingBit() function. + + (#) Optionally, if Circular mode and Double Buffer mode are enabled, you can modify + the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that + the Memory Address to be modified is not the one currently in use by DMA Stream. + This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). + + (#) Optionally, Pause-Resume operations may be performed: + The DMA_Cmd() function may be used to perform Pause-Resume operation. + When a transfer is ongoing, calling this function to disable the + Stream will cause the transfer to be paused. All configuration registers + and the number of remaining data will be preserved. When calling again + this function to re-enable the Stream, the transfer will be resumed from + the point where it was paused. + + -@- Memory-to-Memory transfer is possible by setting the address of the memory into + the Peripheral registers. In this mode, Circular mode and Double Buffer mode + are not allowed. + + -@- The FIFO is used mainly to reduce bus usage and to allow data + packing/unpacking: it is possible to set different Data Sizes for + the Peripheral and the Memory (ie. you can set Half-Word data size + for the peripheral to access its data register and set Word data size + for the Memory to gain in access time. Each two Half-words will be + packed and written in a single access to a Word in the Memory). + + -@- When FIFO is disabled, it is not allowed to configure different + Data Sizes for Source and Destination. In this case the Peripheral + Data Size will be applied to both Source and Destination. + + @endverbatim + ****************************************************************************** + * @attention * - * 5. Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring - * the second Memory address and the first Memory to be used through the function - * DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function - * DMA_DoubleBufferModeCmd(). These operations must be done before step 6. - * - * 6. Enable the DMA stream using the DMA_Cmd() function. - * - * 7. Activate the needed Stream Request using PPP_DMACmd() function for - * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) - * The function allowing this operation is provided in each PPP peripheral - * driver (ie. SPI_DMACmd for SPI peripheral). - * Once the Stream is enabled, it is not possible to modify its configuration - * unless the stream is stopped and disabled. - * After enabling the Stream, it is advised to monitor the EN bit status using - * the function DMA_GetCmdStatus(). In case of configuration errors or bus errors - * this bit will remain reset and all transfers on this Stream will remain on hold. + *

    © COPYRIGHT 2013 STMicroelectronics

    * - * 8. Optionally, you can configure the number of data to be transferred - * when the Stream is disabled (ie. after each Transfer Complete event - * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). - * And you can get the number of remaining data to be transferred using - * the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is - * enabled and running). - * - * 9. To control DMA events you can use one of the following - * two methods: - * a- Check on DMA Stream flags using the function DMA_GetFlagStatus(). - * b- Use DMA interrupts through the function DMA_ITConfig() at initialization - * phase and DMA_GetITStatus() function into interrupt routines in - * communication phase. - * After checking on a flag you should clear it using DMA_ClearFlag() - * function. And after checking on an interrupt event you should - * clear it using DMA_ClearITPendingBit() function. - * - * 10. Optionally, if Circular mode and Double Buffer mode are enabled, you can modify - * the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that - * the Memory Address to be modified is not the one currently in use by DMA Stream. - * This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). - * - * 11. Optionally, Pause-Resume operations may be performed: - * The DMA_Cmd() function may be used to perform Pause-Resume operation. When a - * transfer is ongoing, calling this function to disable the Stream will cause the - * transfer to be paused. All configuration registers and the number of remaining - * data will be preserved. When calling again this function to re-enable the Stream, - * the transfer will be resumed from the point where it was paused. - * - * @note Memory-to-Memory transfer is possible by setting the address of the memory into - * the Peripheral registers. In this mode, Circular mode and Double Buffer mode - * are not allowed. - * - * @note The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is - * possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set - * Half-Word data size for the peripheral to access its data register and set Word data size - * for the Memory to gain in access time. Each two Half-words will be packed and written in - * a single access to a Word in the Memory). - * - * @note When FIFO is disabled, it is not allowed to configure different Data Sizes for Source - * and Destination. In this case the Peripheral Data Size will be applied to both Source - * and Destination. + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - * @endverbatim - * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -162,18 +170,18 @@ * @verbatim =============================================================================== - Initialization and Configuration functions + ##### Initialization and Configuration functions ##### =============================================================================== - - This subsection provides functions allowing to initialize the DMA Stream source - and destination addresses, incrementation and data sizes, transfer direction, - buffer size, circular/normal mode selection, memory-to-memory mode selection - and Stream priority value. - - The DMA_Init() function follows the DMA configuration procedures as described in - reference manual (RM0090) except the first point: waiting on EN bit to be reset. - This condition should be checked by user application using the function DMA_GetCmdStatus() - before calling the DMA_Init() function. + [..] + This subsection provides functions allowing to initialize the DMA Stream source + and destination addresses, incrementation and data sizes, transfer direction, + buffer size, circular/normal mode selection, memory-to-memory mode selection + and Stream priority value. + [..] + The DMA_Init() function follows the DMA configuration procedures as described in + reference manual (RM0090) except the first point: waiting on EN bit to be reset. + This condition should be checked by user application using the function DMA_GetCmdStatus() + before calling the DMA_Init() function. @endverbatim * @{ @@ -566,37 +574,35 @@ void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Flo * @verbatim =============================================================================== - Data Counter functions + ##### Data Counter functions ##### =============================================================================== - - This subsection provides function allowing to configure and read the buffer size - (number of data to be transferred). - - The DMA data counter can be written only when the DMA Stream is disabled - (ie. after transfer complete event). - - The following function can be used to write the Stream data counter value: - - void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); - -@note It is advised to use this function rather than DMA_Init() in situations where - only the Data buffer needs to be reloaded. - -@note If the Source and Destination Data Sizes are different, then the value written in - data counter, expressing the number of transfers, is relative to the number of - transfers from the Peripheral point of view. - ie. If Memory data size is Word, Peripheral data size is Half-Words, then the value - to be configured in the data counter is the number of Half-Words to be transferred - from/to the peripheral. - - The DMA data counter can be read to indicate the number of remaining transfers for - the relative DMA Stream. This counter is decremented at the end of each data - transfer and when the transfer is complete: - - If Normal mode is selected: the counter is set to 0. - - If Circular mode is selected: the counter is reloaded with the initial value - (configured before enabling the DMA Stream) - - The following function can be used to read the Stream data counter value: - - uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); + [..] + This subsection provides function allowing to configure and read the buffer size + (number of data to be transferred). + [..] + The DMA data counter can be written only when the DMA Stream is disabled + (ie. after transfer complete event). + [..] + The following function can be used to write the Stream data counter value: + (+) void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); + -@- It is advised to use this function rather than DMA_Init() in situations + where only the Data buffer needs to be reloaded. + -@- If the Source and Destination Data Sizes are different, then the value + written in data counter, expressing the number of transfers, is relative + to the number of transfers from the Peripheral point of view. + ie. If Memory data size is Word, Peripheral data size is Half-Words, + then the value to be configured in the data counter is the number + of Half-Words to be transferred from/to the peripheral. + [..] + The DMA data counter can be read to indicate the number of remaining transfers for + the relative DMA Stream. This counter is decremented at the end of each data + transfer and when the transfer is complete: + (+) If Normal mode is selected: the counter is set to 0. + (+) If Circular mode is selected: the counter is reloaded with the initial value + (configured before enabling the DMA Stream) + [..] + The following function can be used to read the Stream data counter value: + (+) uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); @endverbatim * @{ @@ -655,45 +661,51 @@ uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx) * @verbatim =============================================================================== - Double Buffer mode functions + ##### Double Buffer mode functions ##### =============================================================================== - - This subsection provides function allowing to configure and control the double - buffer mode parameters. - - The Double Buffer mode can be used only when Circular mode is enabled. - The Double Buffer mode cannot be used when transferring data from Memory to Memory. - - The Double Buffer mode allows to set two different Memory addresses from/to which - the DMA controller will access alternatively (after completing transfer to/from target - memory 0, it will start transfer to/from target memory 1). - This allows to reduce software overhead for double buffering and reduce the CPU - access time. - - Two functions must be called before calling the DMA_Init() function: - - void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory); - - void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); - - DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address and the first - Memory target from/to which the transfer will start after enabling the DMA Stream. - Then DMA_DoubleBufferModeCmd() must be called to enable the Double Buffer mode (or disable - it when it should not be used). + [..] + This subsection provides function allowing to configure and control the double + buffer mode parameters. + + [..] + The Double Buffer mode can be used only when Circular mode is enabled. + The Double Buffer mode cannot be used when transferring data from Memory to Memory. + + [..] + The Double Buffer mode allows to set two different Memory addresses from/to which + the DMA controller will access alternatively (after completing transfer to/from + target memory 0, it will start transfer to/from target memory 1). + This allows to reduce software overhead for double buffering and reduce the CPU + access time. + + [..] + Two functions must be called before calling the DMA_Init() function: + (+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, + uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory); + (+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); + + [..] + DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address + and the first Memory target from/to which the transfer will start after + enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called + to enable the Double Buffer mode (or disable it when it should not be used). - - Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is - stopped) to modify on of the target Memories addresses or to check wich Memory target is currently - used: - - void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget); - - uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); - - DMA_MemoryTargetConfig() can be called to modify the base address of one of the two target Memories. - The Memory of which the base address will be modified must not be currently be used by the DMA Stream - (ie. if the DMA Stream is currently transferring from Memory 1 then you can only modify base address - of target Memory 0 and vice versa). - To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which - returns the index of the Memory target currently in use by the DMA Stream. + [..] + Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is + stopped) to modify on of the target Memories addresses or to check wich Memory target is currently + used: + (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, + uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget); + (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); + + [..] + DMA_MemoryTargetConfig() can be called to modify the base address of one of + the two target Memories. + The Memory of which the base address will be modified must not be currently + be used by the DMA Stream (ie. if the DMA Stream is currently transferring + from Memory 1 then you can only modify base address of target Memory 0 and vice versa). + To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which + returns the index of the Memory target currently in use by the DMA Stream. @endverbatim * @{ @@ -842,64 +854,70 @@ uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx) * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== - - This subsection provides functions allowing to - - Check the DMA enable status - - Check the FIFO status - - Configure the DMA Interrupts sources and check or clear the flags or pending bits status. - - 1. DMA Enable status: - After configuring the DMA Stream (DMA_Init() function) and enabling the stream, - it is recommended to check (or wait until) the DMA Stream is effectively enabled. - A Stream may remain disabled if a configuration parameter is wrong. - After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA - Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, - the current data will be transferred and the Stream will be effectively disabled only after - this data transfer completion. - To monitor this state it is possible to use the following function: - - FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); + [..] + This subsection provides functions allowing to + (+) Check the DMA enable status + (+) Check the FIFO status + (+) Configure the DMA Interrupts sources and check or clear the flags or + pending bits status. + + [..] + (#) DMA Enable status: + After configuring the DMA Stream (DMA_Init() function) and enabling + the stream, it is recommended to check (or wait until) the DMA Stream + is effectively enabled. A Stream may remain disabled if a configuration + parameter is wrong. After disabling a DMA Stream, it is also recommended + to check (or wait until) the DMA Stream is effectively disabled. + If a Stream is disabled while a data transfer is ongoing, the current + data will be transferred and the Stream will be effectively disabled + only after this data transfer completion. + To monitor this state it is possible to use the following function: + (++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); - 2. FIFO Status: - It is possible to monitor the FIFO status when a transfer is ongoing using the following - function: - - uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); + (#) FIFO Status: + It is possible to monitor the FIFO status when a transfer is ongoing + using the following function: + (++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); - 3. DMA Interrupts and Flags: - The user should identify which mode will be used in his application to manage the - DMA controller events: Polling mode or Interrupt mode. + (#) DMA Interrupts and Flags: + The user should identify which mode will be used in his application + to manage the DMA controller events: Polling mode or Interrupt mode. - Polling Mode - ============= + *** Polling Mode *** + ==================== + [..] Each DMA stream can be managed through 4 event Flags: (x : DMA Stream number ) - 1. DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. - 2. DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. - 3. DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. - 4. DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. - 5. DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . - - In this Mode it is advised to use the following functions: - - FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - - void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - - Interrupt Mode - =============== + (#) DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. + (#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. + (#) DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. + (#) DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. + (#) DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . + [..] + In this Mode it is advised to use the following functions: + (+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); + (+) void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); + + *** Interrupt Mode *** + ====================== + [..] Each DMA Stream can be managed through 4 Interrupts: - Interrupt Source - ---------------- - 1. DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. - 2. DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. - 3. DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. - 4. DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. - 5. DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. - - In this Mode it is advised to use the following functions: - - void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); - - ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - - void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); + *** Interrupt Source *** + ======================== + [..] + (#) DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. + (#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. + (#) DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. + (#) DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. + (#) DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. + [..] + In this Mode it is advised to use the following functions: + (+) void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); + (+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); + (+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); @endverbatim * @{ @@ -1280,4 +1298,4 @@ void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c new file mode 100644 index 0000000000..6370e56332 --- /dev/null +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c @@ -0,0 +1,778 @@ +/** + ****************************************************************************** + * @file stm32f4xx_dma2d.c + * @author MCD Application Team + * @version V1.3.0 + * @date 08-November-2013 + * @brief This file provides firmware functions to manage the following + * functionalities of the DMA2D controller (DMA2D) peripheral: + * + Initialization and configuration + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable DMA2D clock using + RCC_APB2PeriphResetCmd(RCC_APB2Periph_DMA2D, ENABLE) function. + + (#) Configures DMA2D + (++) transfer mode + (++) pixel format, line_number, pixel_per_line + (++) output memory address + (++) alpha value + (++) output offset + (++) Default color (RGB) + + (#) Configures Foreground or/and background + (++) memory address + (++) alpha value + (++) offset and default color + + (#) Call the DMA2D_Start() to enable the DMA2D controller. + + @endverbatim + + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

    © COPYRIGHT 2013 STMicroelectronics

    + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_dma2d.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA2D + * @brief DMA2D driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +#define CR_MASK ((uint32_t)0xFFFCE0FC) /* DMA2D CR Mask */ +#define PFCCR_MASK ((uint32_t)0x00FC00C0) /* DMA2D FGPFCCR Mask */ +#define DEAD_MASK ((uint32_t)0xFFFF00FE) /* DMA2D DEAD Mask */ + +/** @defgroup DMA2D_Private_Functions + * @{ + */ + +/** @defgroup DMA2D_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DMA2D + (+) Start/Abort/Suspend Transfer + (+) Initialize, configure and set Foreground and background + (+) configure and enable DeadTime + (+) configure lineWatermark + + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the DMA2D peripheral registers to their default reset + * values. + * @param None + * @retval None + */ + +void DMA2D_DeInit(void) +{ + /* Enable DMA2D reset state */ + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, ENABLE); + /* Release DMA2D from reset state */ + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, DISABLE); +} + + +/** + * @brief Initializes the DMA2D peripheral according to the specified parameters + * in the DMA2D_InitStruct. + * @note This function can be used only when the DMA2D is disabled. + * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure that contains + * the configuration information for the specified DMA2D peripheral. + * @retval None + */ +void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct) +{ + + uint32_t outgreen = 0; + uint32_t outred = 0; + uint32_t outalpha = 0; + uint32_t pixline = 0; + + /* Check the parameters */ + assert_param(IS_DMA2D_MODE(DMA2D_InitStruct->DMA2D_Mode)); + assert_param(IS_DMA2D_CMODE(DMA2D_InitStruct->DMA2D_CMode)); + assert_param(IS_DMA2D_OGREEN(DMA2D_InitStruct->DMA2D_OutputGreen)); + assert_param(IS_DMA2D_ORED(DMA2D_InitStruct->DMA2D_OutputRed)); + assert_param(IS_DMA2D_OBLUE(DMA2D_InitStruct->DMA2D_OutputBlue)); + assert_param(IS_DMA2D_OALPHA(DMA2D_InitStruct->DMA2D_OutputAlpha)); + assert_param(IS_DMA2D_OUTPUT_OFFSET(DMA2D_InitStruct->DMA2D_OutputOffset)); + assert_param(IS_DMA2D_LINE(DMA2D_InitStruct->DMA2D_NumberOfLine)); + assert_param(IS_DMA2D_PIXEL(DMA2D_InitStruct->DMA2D_PixelPerLine)); + + /* Configures the DMA2D operation mode */ + DMA2D->CR &= (uint32_t)CR_MASK; + DMA2D->CR |= (DMA2D_InitStruct->DMA2D_Mode); + + /* Configures the color mode of the output image */ + DMA2D->OPFCCR &= ~(uint32_t)DMA2D_OPFCCR_CM; + DMA2D->OPFCCR |= (DMA2D_InitStruct->DMA2D_CMode); + + /* Configures the output color */ + + if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB8888) + { + outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8; + outred = DMA2D_InitStruct->DMA2D_OutputRed << 16; + outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 24; + } + else + + if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB888) + { + outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8; + outred = DMA2D_InitStruct->DMA2D_OutputRed << 16; + outalpha = (uint32_t)0x00000000; + } + + else + + if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB565) + { + outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5; + outred = DMA2D_InitStruct->DMA2D_OutputRed << 11; + outalpha = (uint32_t)0x00000000; + } + + else + + if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB1555) + { + outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5; + outred = DMA2D_InitStruct->DMA2D_OutputRed << 10; + outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 15; + } + + else /* DMA2D_CMode = DMA2D_ARGB4444 */ + { + outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 4; + outred = DMA2D_InitStruct->DMA2D_OutputRed << 8; + outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 12; + } + DMA2D->OCOLR |= ((outgreen) | (outred) | (DMA2D_InitStruct->DMA2D_OutputBlue) | (outalpha)); + + /* Configures the output memory address */ + DMA2D->OMAR = (DMA2D_InitStruct->DMA2D_OutputMemoryAdd); + + /* Configure the line Offset */ + DMA2D->OOR &= ~(uint32_t)DMA2D_OOR_LO; + DMA2D->OOR |= (DMA2D_InitStruct->DMA2D_OutputOffset); + + /* Configure the number of line and pixel per line */ + pixline = DMA2D_InitStruct->DMA2D_PixelPerLine << 16; + DMA2D->NLR &= ~(DMA2D_NLR_NL | DMA2D_NLR_PL); + DMA2D->NLR |= ((DMA2D_InitStruct->DMA2D_NumberOfLine) | (pixline)); + +/** + * @brief Fills each DMA2D_InitStruct member with its default value. + * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure which will + * be initialized. + * @retval None + */ +} +void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct) +{ + /* Initialize the transfer mode member */ + DMA2D_InitStruct->DMA2D_Mode = DMA2D_M2M; + + /* Initialize the output color mode members */ + DMA2D_InitStruct->DMA2D_CMode = DMA2D_ARGB8888; + + /* Initialize the alpha and RGB values */ + DMA2D_InitStruct->DMA2D_OutputGreen = 0x00; + DMA2D_InitStruct->DMA2D_OutputBlue = 0x00; + DMA2D_InitStruct->DMA2D_OutputRed = 0x00; + DMA2D_InitStruct->DMA2D_OutputAlpha = 0x00; + + /* Initialize the output memory address */ + DMA2D_InitStruct->DMA2D_OutputMemoryAdd = 0x00; + + /* Initialize the output offset */ + DMA2D_InitStruct->DMA2D_OutputOffset = 0x00; + + /* Initialize the number of line and the number of pixel per line */ + DMA2D_InitStruct->DMA2D_NumberOfLine = 0x00; + DMA2D_InitStruct->DMA2D_PixelPerLine = 0x00; +} + +/** + * @brief Start the DMA2D transfer. + * @param + * @retval None + */ + +void DMA2D_StartTransfer(void) +{ + /* Start DMA2D transfer by setting START bit */ + DMA2D->CR |= (uint32_t)DMA2D_CR_START; +} + +/** + * @brief Aboart the DMA2D transfer. + * @param + * @retval None + */ + +void DMA2D_AbortTransfer(void) +{ + /* Start DMA2D transfer by setting START bit */ + DMA2D->CR |= (uint32_t)DMA2D_CR_ABORT; + +} + +/** + * @brief Stop or continue the DMA2D transfer. + * @param NewState: new state of the DMA2D peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA2D_Suspend(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Suspend DMA2D transfer by setting STOP bit */ + DMA2D->CR |= (uint32_t)DMA2D_CR_SUSP; + } + else + { + /* Continue DMA2D transfer by clearing STOP bit */ + DMA2D->CR &= ~(uint32_t)DMA2D_CR_SUSP; + } +} + +/** + * @brief Configures the Foreground according to the specified parameters + * in the DMA2D_FGStruct. + * @note This function can be used only when the transfer is disabled. + * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure that contains + * the configuration information for the specified Background. + * @retval None + */ +void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct) +{ + + uint32_t fg_clutcolormode = 0; + uint32_t fg_clutsize = 0; + uint32_t fg_alpha_mode = 0; + uint32_t fg_alphavalue = 0; + uint32_t fg_colorgreen = 0; + uint32_t fg_colorred = 0; + + assert_param(IS_DMA2D_FGO(DMA2D_FG_InitStruct->DMA2D_FGO)); + assert_param(IS_DMA2D_FGCM(DMA2D_FG_InitStruct->DMA2D_FGCM)); + assert_param(IS_DMA2D_FG_CLUT_CM(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM)); + assert_param(IS_DMA2D_FG_CLUT_SIZE(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE)); + assert_param(IS_DMA2D_FG_ALPHA_MODE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE)); + assert_param(IS_DMA2D_FG_ALPHA_VALUE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE)); + assert_param(IS_DMA2D_FGC_BLUE(DMA2D_FG_InitStruct->DMA2D_FGC_BLUE)); + assert_param(IS_DMA2D_FGC_GREEN(DMA2D_FG_InitStruct->DMA2D_FGC_GREEN)); + assert_param(IS_DMA2D_FGC_RED(DMA2D_FG_InitStruct->DMA2D_FGC_RED)); + + /* Configures the FG memory address */ + DMA2D->FGMAR = (DMA2D_FG_InitStruct->DMA2D_FGMA); + + /* Configures the FG offset */ + DMA2D->FGOR &= ~(uint32_t)DMA2D_FGOR_LO; + DMA2D->FGOR |= (DMA2D_FG_InitStruct->DMA2D_FGO); + + /* Configures foreground Pixel Format Convertor */ + DMA2D->FGPFCCR &= (uint32_t)PFCCR_MASK; + fg_clutcolormode = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM << 4; + fg_clutsize = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE << 8; + fg_alpha_mode = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE << 16; + fg_alphavalue = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE << 24; + DMA2D->FGPFCCR |= (DMA2D_FG_InitStruct->DMA2D_FGCM | fg_clutcolormode | fg_clutsize | \ + fg_alpha_mode | fg_alphavalue); + + /* Configures foreground color */ + DMA2D->FGCOLR &= ~(DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_RED); + fg_colorgreen = DMA2D_FG_InitStruct->DMA2D_FGC_GREEN << 8; + fg_colorred = DMA2D_FG_InitStruct->DMA2D_FGC_RED << 16; + DMA2D->FGCOLR |= (DMA2D_FG_InitStruct->DMA2D_FGC_BLUE | fg_colorgreen | fg_colorred); + + /* Configures foreground CLUT memory address */ + DMA2D->FGCMAR = DMA2D_FG_InitStruct->DMA2D_FGCMAR; +} + +/** + * @brief Fills each DMA2D_FGStruct member with its default value. + * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct) +{ + /*!< Initialize the DMA2D foreground memory address */ + DMA2D_FG_InitStruct->DMA2D_FGMA = 0x00; + + /*!< Initialize the DMA2D foreground offset */ + DMA2D_FG_InitStruct->DMA2D_FGO = 0x00; + + /*!< Initialize the DMA2D foreground color mode */ + DMA2D_FG_InitStruct->DMA2D_FGCM = CM_ARGB8888; + + /*!< Initialize the DMA2D foreground CLUT color mode */ + DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM = CLUT_CM_ARGB8888; + + /*!< Initialize the DMA2D foreground CLUT size */ + DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE = 0x00; + + /*!< Initialize the DMA2D foreground alpha mode */ + DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; + + /*!< Initialize the DMA2D foreground alpha value */ + DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE = 0x00; + + /*!< Initialize the DMA2D foreground blue value */ + DMA2D_FG_InitStruct->DMA2D_FGC_BLUE = 0x00; + + /*!< Initialize the DMA2D foreground green value */ + DMA2D_FG_InitStruct->DMA2D_FGC_GREEN = 0x00; + + /*!< Initialize the DMA2D foreground red value */ + DMA2D_FG_InitStruct->DMA2D_FGC_RED = 0x00; + + /*!< Initialize the DMA2D foreground CLUT memory address */ + DMA2D_FG_InitStruct->DMA2D_FGCMAR = 0x00; +} + + +/** + * @brief Configures the Background according to the specified parameters + * in the DMA2D_BGStruct. + * @note This function can be used only when the transfer is disabled. + * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure that contains + * the configuration information for the specified Background. + * @retval None + */ +void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct) +{ + + uint32_t bg_clutcolormode = 0; + uint32_t bg_clutsize = 0; + uint32_t bg_alpha_mode = 0; + uint32_t bg_alphavalue = 0; + uint32_t bg_colorgreen = 0; + uint32_t bg_colorred = 0; + + assert_param(IS_DMA2D_BGO(DMA2D_BG_InitStruct->DMA2D_BGO)); + assert_param(IS_DMA2D_BGCM(DMA2D_BG_InitStruct->DMA2D_BGCM)); + assert_param(IS_DMA2D_BG_CLUT_CM(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM)); + assert_param(IS_DMA2D_BG_CLUT_SIZE(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE)); + assert_param(IS_DMA2D_BG_ALPHA_MODE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE)); + assert_param(IS_DMA2D_BG_ALPHA_VALUE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE)); + assert_param(IS_DMA2D_BGC_BLUE(DMA2D_BG_InitStruct->DMA2D_BGC_BLUE)); + assert_param(IS_DMA2D_BGC_GREEN(DMA2D_BG_InitStruct->DMA2D_BGC_GREEN)); + assert_param(IS_DMA2D_BGC_RED(DMA2D_BG_InitStruct->DMA2D_BGC_RED)); + + /* Configures the BG memory address */ + DMA2D->BGMAR = (DMA2D_BG_InitStruct->DMA2D_BGMA); + + /* Configures the BG offset */ + DMA2D->BGOR &= ~(uint32_t)DMA2D_BGOR_LO; + DMA2D->BGOR |= (DMA2D_BG_InitStruct->DMA2D_BGO); + + /* Configures background Pixel Format Convertor */ + DMA2D->BGPFCCR &= (uint32_t)PFCCR_MASK; + bg_clutcolormode = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM << 4; + bg_clutsize = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE << 8; + bg_alpha_mode = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE << 16; + bg_alphavalue = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE << 24; + DMA2D->BGPFCCR |= (DMA2D_BG_InitStruct->DMA2D_BGCM | bg_clutcolormode | bg_clutsize | \ + bg_alpha_mode | bg_alphavalue); + + /* Configures background color */ + DMA2D->BGCOLR &= ~(DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_RED); + bg_colorgreen = DMA2D_BG_InitStruct->DMA2D_BGC_GREEN << 8; + bg_colorred = DMA2D_BG_InitStruct->DMA2D_BGC_RED << 16; + DMA2D->BGCOLR |= (DMA2D_BG_InitStruct->DMA2D_BGC_BLUE | bg_colorgreen | bg_colorred); + + /* Configures background CLUT memory address */ + DMA2D->BGCMAR = DMA2D_BG_InitStruct->DMA2D_BGCMAR; + +} + +/** + * @brief Fills each DMA2D_BGStruct member with its default value. + * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct) +{ + /*!< Initialize the DMA2D background memory address */ + DMA2D_BG_InitStruct->DMA2D_BGMA = 0x00; + + /*!< Initialize the DMA2D background offset */ + DMA2D_BG_InitStruct->DMA2D_BGO = 0x00; + + /*!< Initialize the DMA2D background color mode */ + DMA2D_BG_InitStruct->DMA2D_BGCM = CM_ARGB8888; + + /*!< Initialize the DMA2D background CLUT color mode */ + DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM = CLUT_CM_ARGB8888; + + /*!< Initialize the DMA2D background CLUT size */ + DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE = 0x00; + + /*!< Initialize the DMA2D background alpha mode */ + DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; + + /*!< Initialize the DMA2D background alpha value */ + DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE = 0x00; + + /*!< Initialize the DMA2D background blue value */ + DMA2D_BG_InitStruct->DMA2D_BGC_BLUE = 0x00; + + /*!< Initialize the DMA2D background green value */ + DMA2D_BG_InitStruct->DMA2D_BGC_GREEN = 0x00; + + /*!< Initialize the DMA2D background red value */ + DMA2D_BG_InitStruct->DMA2D_BGC_RED = 0x00; + + /*!< Initialize the DMA2D background CLUT memory address */ + DMA2D_BG_InitStruct->DMA2D_BGCMAR = 0x00; +} + +/** + * @brief Start the automatic loading of the CLUT or abort the transfer. + * @param NewState: new state of the DMA2D peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void DMA2D_FGStart(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Start the automatic loading of the CLUT */ + DMA2D->FGPFCCR |= DMA2D_FGPFCCR_START; + } + else + { + /* abort the transfer */ + DMA2D->FGPFCCR &= (uint32_t)~DMA2D_FGPFCCR_START; + } +} + +/** + * @brief Start the automatic loading of the CLUT or abort the transfer. + * @param NewState: new state of the DMA2D peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void DMA2D_BGStart(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Start the automatic loading of the CLUT */ + DMA2D->BGPFCCR |= DMA2D_BGPFCCR_START; + } + else + { + /* abort the transfer */ + DMA2D->BGPFCCR &= (uint32_t)~DMA2D_BGPFCCR_START; + } +} + +/** + * @brief Configures the DMA2D dead time. + * @param DMA2D_DeadTime: specifies the DMA2D dead time. + * This parameter can be one of the following values: + * @retval None + */ +void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState) +{ + uint32_t DeadTime; + + /* Check the parameters */ + assert_param(IS_DMA2D_DEAD_TIME(DMA2D_DeadTime)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable and Configures the dead time */ + DMA2D->AMTCR &= (uint32_t)DEAD_MASK; + DeadTime = DMA2D_DeadTime << 8; + DMA2D->AMTCR |= (DeadTime | DMA2D_AMTCR_EN); + } + else + { + DMA2D->AMTCR &= ~(uint32_t)DMA2D_AMTCR_EN; + } +} + +/** + * @brief Define the configuration of the line watermark . + * @param DMA2D_LWatermarkConfig: Line Watermark configuration. + * @retval None + */ + +void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LineWatermark(DMA2D_LWatermarkConfig)); + + /* Sets the Line watermark configuration */ + DMA2D->LWR = (uint32_t)DMA2D_LWatermarkConfig; +} + +/** + * @} + */ + +/** @defgroup DMA2D_Group2 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure the DMA2D + Interrupts and to get the status and clear flags and Interrupts + pending bits. + [..] The DMA2D provides 6 Interrupts sources and 6 Flags + + *** Flags *** + ============= + [..] + (+) DMA2D_FLAG_CE : Configuration Error Interrupt flag + (+) DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag + (+) DMA2D_FLAG_TW: Transfer Watermark Interrupt flag + (+) DMA2D_FLAG_TC: Transfer Complete interrupt flag + (+) DMA2D_FLAG_TE: Transfer Error interrupt flag + (+) DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag + + *** Interrupts *** + ================== + [..] + (+) DMA2D_IT_CE: Configuration Error Interrupt is generated when a wrong + configuration is detected + (+) DMA2D_IT_CAE: CLUT Access Error Interrupt + (+) DMA2D_IT_TW: Transfer Watermark Interrupt is generated when + the programmed watermark is reached + (+) DMA2D_IT_TE: Transfer Error interrupt is generated when the CPU trying + to access the CLUT while a CLUT loading or a DMA2D1 transfer + is on going + (+) DMA2D_IT_CTC: CLUT Transfer Complete Interrupt + (+) DMA2D_IT_TC: Transfer Complete interrupt +@endverbatim + * @{ + */ +/** + * @brief Enables or disables the specified DMA2D's interrupts. + * @param DMA2D_IT: specifies the DMA2D interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable. + * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable. + * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable. + * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable. + * @arg DMA2D_IT_TC: Transfer Complete interrupt enable. + * @arg DMA2D_IT_TE: Transfer Error interrupt enable. + * @param NewState: new state of the specified DMA2D interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_IT(DMA2D_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA2D interrupts */ + DMA2D->CR |= DMA2D_IT; + } + else + { + /* Disable the selected DMA2D interrupts */ + DMA2D->CR &= (uint32_t)~DMA2D_IT; + } +} + +/** + * @brief Checks whether the specified DMA2D's flag is set or not. + * @param DMA2D_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag. + * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag. + * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag. + * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag. + * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag. + * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag. + * @retval The new state of DMA2D_FLAG (SET or RESET). + */ + +FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG)); + + /* Check the status of the specified DMA2D flag */ + if (((DMA2D->ISR) & DMA2D_FLAG) != (uint32_t)RESET) + { + /* DMA2D_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA2D_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DMA2D_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMA2D's pending flags. + * @param DMA2D_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag. + * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag. + * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag. + * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag. + * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag. + * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag. + * @retval None + */ +void DMA2D_ClearFlag(uint32_t DMA2D_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG)); + + /* Clear the corresponding DMA2D flag */ + DMA2D->IFCR = (uint32_t)DMA2D_FLAG; +} + +/** + * @brief Checks whether the specified DMA2D's interrupt has occurred or not. + * @param DMA2D_IT: specifies the DMA2D interrupts sources to check. + * This parameter can be one of the following values: + * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable. + * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable. + * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable. + * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable. + * @arg DMA2D_IT_TC: Transfer Complete interrupt enable. + * @arg DMA2D_IT_TE: Transfer Error interrupt enable. + * @retval The new state of the DMA2D_IT (SET or RESET). + */ +ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT) +{ + ITStatus bitstatus = RESET; + uint32_t DMA2D_IT_FLAG = DMA2D_IT >> 8; + + /* Check the parameters */ + assert_param(IS_DMA2D_IT(DMA2D_IT)); + + if ((DMA2D->ISR & DMA2D_IT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + if (((DMA2D->CR & DMA2D_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the DMA2D's interrupt pending bits. + * @param DMA2D_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg DMA2D_IT_CE: Configuration Error Interrupt. + * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt. + * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt. + * @arg DMA2D_IT_TW: Transfer Watermark Interrupt. + * @arg DMA2D_IT_TC: Transfer Complete interrupt. + * @arg DMA2D_IT_TE: Transfer Error interrupt. + * @retval None + */ +void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_IT(DMA2D_IT)); + DMA2D_IT = DMA2D_IT >> 8; + + /* Clear the corresponding DMA2D Interrupt */ + DMA2D->IFCR = (uint32_t)DMA2D_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c index f1cf7c960d..9bbc801065 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c @@ -2,58 +2,65 @@ ****************************************************************************** * @file stm32f4xx_exti.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the EXTI peripheral: - * - Initialization and Configuration - * - Interrupts and flags management + * + Initialization and Configuration + * + Interrupts and flags management * - * @verbatim - * - * =================================================================== - * EXTI features - * =================================================================== - * - * External interrupt/event lines are mapped as following: - * 1- All available GPIO pins are connected to the 16 external - * interrupt/event lines from EXTI0 to EXTI15. - * 2- EXTI line 16 is connected to the PVD Output - * 3- EXTI line 17 is connected to the RTC Alarm event - * 4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event - * 5- EXTI line 19 is connected to the Ethernet Wakeup event - * 6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event - * 7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events - * 8- EXTI line 22 is connected to the RTC Wakeup event - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * In order to use an I/O pin as an external interrupt source, follow - * steps below: - * 1- Configure the I/O in input mode using GPIO_Init() - * 2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() - * 3- Select the mode(interrupt, event) and configure the trigger - * selection (Rising, falling or both) using EXTI_Init() - * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() - * - * @note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx - * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - * - * @endverbatim +@verbatim + + =================================================================== + ##### EXTI features ##### + =================================================================== + + [..] External interrupt/event lines are mapped as following: + (#) All available GPIO pins are connected to the 16 external + interrupt/event lines from EXTI0 to EXTI15. + (#) EXTI line 16 is connected to the PVD Output + (#) EXTI line 17 is connected to the RTC Alarm event + (#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event + (#) EXTI line 19 is connected to the Ethernet Wakeup event + (#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event + (#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events + (#) EXTI line 22 is connected to the RTC Wakeup event + + + ##### How to use this driver ##### + =================================================================== + + [..] In order to use an I/O pin as an external interrupt source, follow steps + below: + (#) Configure the I/O in input mode using GPIO_Init() + (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() + (#) Select the mode(interrupt, event) and configure the trigger + selection (Rising, falling or both) using EXTI_Init() + (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() + + [..] + (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx + registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + +@endverbatim * ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -88,7 +95,7 @@ * @verbatim =============================================================================== - Initialization and Configuration functions + ##### Initialization and Configuration functions ##### =============================================================================== @endverbatim @@ -204,7 +211,7 @@ void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim @@ -256,13 +263,11 @@ void EXTI_ClearFlag(uint32_t EXTI_Line) */ ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) { - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; + FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - enablestatus = EXTI->IMR & EXTI_Line; - if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) { bitstatus = SET; } @@ -271,6 +276,7 @@ ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) bitstatus = RESET; } return bitstatus; + } /** @@ -303,4 +309,4 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c index 280b1d394e..54b2d31749 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c @@ -2,67 +2,69 @@ ****************************************************************************** * @file stm32f4xx_flash.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the FLASH peripheral: - * - FLASH Interface configuration - * - FLASH Memory Programming - * - Option Bytes Programming - * - Interrupts and flags management + * + FLASH Interface configuration + * + FLASH Memory Programming + * + Option Bytes Programming + * + Interrupts and flags management * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * This driver provides functions to configure and program the FLASH - * memory of all STM32F4xx devices. - * These functions are split in 4 groups: - * - * 1. FLASH Interface configuration functions: this group includes the - * management of the following features: - * - Set the latency - * - Enable/Disable the prefetch buffer - * - Enable/Disable the Instruction cache and the Data cache - * - Reset the Instruction cache and the Data cache - * - * 2. FLASH Memory Programming functions: this group includes all needed - * functions to erase and program the main memory: - * - Lock and Unlock the FLASH interface - * - Erase function: Erase sector, erase all sectors - * - Program functions: byte, half word, word and double word - * - * 3. Option Bytes Programming functions: this group includes all needed - * functions to manage the Option Bytes: - * - Set/Reset the write protection - * - Set the Read protection Level - * - Set the BOR level - * - Program the user Option Bytes - * - Launch the Option Bytes loader - * - * 4. Interrupts and flags management functions: this group - * includes all needed functions to: - * - Enable/Disable the FLASH interrupt sources - * - Get flags status - * - Clear flags - * - Get FLASH operation status - * - Wait for last FLASH operation - * - * @endverbatim - * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + This driver provides functions to configure and program the FLASH memory + of all STM32F4xx devices. These functions are split in 4 groups: + + (#) FLASH Interface configuration functions: this group includes the + management of the following features: + (++) Set the latency + (++) Enable/Disable the prefetch buffer + (++) Enable/Disable the Instruction cache and the Data cache + (++) Reset the Instruction cache and the Data cache + + (#) FLASH Memory Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the FLASH interface + (++) Erase function: Erase sector, erase all sectors + (++) Program functions: byte, half word, word and double word + + (#) Option Bytes Programming functions: this group includes all needed + functions to manage the Option Bytes: + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Set the BOR level + (++) Program the user Option Bytes + (++) Launch the Option Bytes loader + + (#) Interrupts and flags management functions: this group + includes all needed functions to: + (++) Enable/Disable the FLASH interrupt sources + (++) Get flags status + (++) Clear flags + (++) Get FLASH operation status + (++) Wait for last FLASH operation + @endverbatim ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -97,36 +99,87 @@ @verbatim =============================================================================== - FLASH Interface configuration functions + ##### FLASH Interface configuration functions ##### =============================================================================== + [..] + This group includes the following functions: + (+) void FLASH_SetLatency(uint32_t FLASH_Latency) + To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. + [..] + For STM32F405xx/07xx and STM32F415xx/17xx devices + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| + +---------------|----------------|----------------|-----------------|-----------------+ - This group includes the following functions: - - void FLASH_SetLatency(uint32_t FLASH_Latency) - To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. + [..] + For STM32F42xxx/43xxx devices +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |---------------------------------------------------------------------| | | voltage range | voltage range | voltage range | voltage range | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | + |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | + |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 | + |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 | + |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120| - |***************|****************|****************|*****************|*****************|*****************************+ + |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| + +-------------------------------------------------------------------------------------+ + + [..] + For STM32F401x devices + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | + +-------------------------------------------------------------------------------------+ + + [..] + +-------------------------------------------------------------------------------------------------------------------+ | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V | |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| @@ -134,23 +187,37 @@ |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| |PSIZE[1:0] | 10 | 01 | 00 | 11 | +-------------------------------------------------------------------------------------------------------------------+ - @note When VOS bit (in PWR_CR register) is reset to '0’, the maximum value of HCLK is 144 MHz. - You can use PWR_MainRegulatorModeConfig() function to set or reset this bit. - - - void FLASH_PrefetchBufferCmd(FunctionalState NewState) - - void FLASH_InstructionCacheCmd(FunctionalState NewState) - - void FLASH_DataCacheCmd(FunctionalState NewState) - - void FLASH_InstructionCacheReset(void) - - void FLASH_DataCacheReset(void) - - The unlock sequence is not needed for these functions. + + -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: + (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz. + (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz. + [..] + On STM32F42xxx/43xxx devices: + (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz. + (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON. + (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON. + [..] + On STM32F401x devices: + (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz. + (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz. + For more details please refer product DataSheet + You can use PWR_MainRegulatorModeConfig() function to control VOS bits. + + (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState) + (+) void FLASH_InstructionCacheCmd(FunctionalState NewState) + (+) void FLASH_DataCacheCmd(FunctionalState NewState) + (+) void FLASH_InstructionCacheReset(void) + (+) void FLASH_DataCacheReset(void) + + [..] + The unlock sequence is not needed for these functions. @endverbatim * @{ */ /** - * @brief Sets the code latency value. + * @brief Sets the code latency value. * @param FLASH_Latency: specifies the FLASH Latency value. * This parameter can be one of the following values: * @arg FLASH_Latency_0: FLASH Zero Latency cycle @@ -160,7 +227,22 @@ * @arg FLASH_Latency_4: FLASH Four Latency cycles * @arg FLASH_Latency_5: FLASH Five Latency cycles * @arg FLASH_Latency_6: FLASH Six Latency cycles - * @arg FLASH_Latency_7: FLASH Seven Latency cycles + * @arg FLASH_Latency_7: FLASH Seven Latency cycles + * @arg FLASH_Latency_8: FLASH Eight Latency cycles + * @arg FLASH_Latency_9: FLASH Nine Latency cycles + * @arg FLASH_Latency_10: FLASH Teen Latency cycles + * @arg FLASH_Latency_11: FLASH Eleven Latency cycles + * @arg FLASH_Latency_12: FLASH Twelve Latency cycles + * @arg FLASH_Latency_13: FLASH Thirteen Latency cycles + * @arg FLASH_Latency_14: FLASH Fourteen Latency cycles + * @arg FLASH_Latency_15: FLASH Fifteen Latency cycles + * + * @note For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx devices this parameter + * can be a value between FLASH_Latency_0 and FLASH_Latency_7. + * + * @note For STM32F42xxx/43xxx devices this parameter can be a value between + * FLASH_Latency_0 and FLASH_Latency_15. + * * @retval None */ void FLASH_SetLatency(uint32_t FLASH_Latency) @@ -267,26 +349,29 @@ void FLASH_DataCacheReset(void) * @verbatim =============================================================================== - FLASH Memory Programming functions + ##### FLASH Memory Programming functions ##### =============================================================================== - - This group includes the following functions: - - void FLASH_Unlock(void) - - void FLASH_Lock(void) - - FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) - - FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) - - FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) - - FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) - - FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) - - FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) - - Any operation of erase or program should follow these steps: - 1. Call the FLASH_Unlock() function to enable the FLASH control register access - - 2. Call the desired function to erase sector(s) or program data - - 3. Call the FLASH_Lock() function to disable the FLASH control register access - (recommended to protect the FLASH memory against possible unwanted operation) + [..] + This group includes the following functions: + (+) void FLASH_Unlock(void) + (+) void FLASH_Lock(void) + (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) + (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) + (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) + (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) + (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) + (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) + The following functions can be used only for STM32F42xxx/43xxx devices. + (+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange) + (+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange) + [..] + Any operation of erase or program should follow these steps: + (#) Call the FLASH_Unlock() function to enable the FLASH control register access + + (#) Call the desired function to erase sector(s) or program data + + (#) Call the FLASH_Lock() function to disable the FLASH control register access + (recommended to protect the FLASH memory against possible unwanted operation) @endverbatim * @{ @@ -320,9 +405,20 @@ void FLASH_Lock(void) /** * @brief Erases a specified FLASH Sector. + * + * @note If an erase and a program operations are requested simustaneously, + * the erase operation is performed before the program one. * * @param FLASH_Sector: The Sector number to be erased. - * This parameter can be a value between FLASH_Sector_0 and FLASH_Sector_11 + * + * @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can + * be a value between FLASH_Sector_0 and FLASH_Sector_11. + * + * For STM32F42xxx/43xxx devices this parameter can be a value between + * FLASH_Sector_0 and FLASH_Sector_23. + * + * For STM32F401xx devices this parameter can be a value between + * FLASH_Sector_0 and FLASH_Sector_5. * * @param VoltageRange: The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: @@ -388,7 +484,10 @@ FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) /** * @brief Erases all FLASH Sectors. - * + * + * @note If an erase and a program operations are requested simustaneously, + * the erase operation is performed before the program one. + * * @param VoltageRange: The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, @@ -412,6 +511,87 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) status = FLASH_WaitForLastOperation(); assert_param(IS_VOLTAGERANGE(VoltageRange)); + if(VoltageRange == VoltageRange_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == VoltageRange_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == VoltageRange_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all sectors */ +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2); + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2); +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#if defined (STM32F40_41xxx) || defined (STM32F401xx) + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_CR_MER); +#endif /* STM32F40_41xxx || STM32F401xx */ + + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH Sectors in Bank 1. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0x0; + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + if(VoltageRange == VoltageRange_1) { tmp_psize = FLASH_PSIZE_BYTE; @@ -433,14 +613,81 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) /* if the previous operation is completed, proceed to erase all sectors */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_MER1; FLASH->CR |= FLASH_CR_STRT; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_CR_MER); + FLASH->CR &= (~FLASH_CR_MER1); + + } + /* Return the Erase Status */ + return status; +} + + +/** + * @brief Erases all FLASH Sectors in Bank 2. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0x0; + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == VoltageRange_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == VoltageRange_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == VoltageRange_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all sectors */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR |= FLASH_CR_MER2; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_CR_MER2); } /* Return the Erase Status */ @@ -450,7 +697,11 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) /** * @brief Programs a double word (64-bit) at a specified address. * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V and an External Vpp is present. + * 2.7V to 3.6V and an External Vpp is present. + * + * @note If an erase and a program operations are requested simustaneously, + * the erase operation is performed before the program one. + * * @param Address: specifies the address to be programmed. * @param Data: specifies the data to be programmed. * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, @@ -487,9 +738,14 @@ FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) /** * @brief Programs a word (32-bit) at a specified address. + * + * @note This function must be used when the device voltage range is from 2.7V to 3.6V. + * + * @note If an erase and a program operations are requested simustaneously, + * the erase operation is performed before the program one. + * * @param Address: specifies the address to be programmed. * This parameter can be any address in Program memory zone or in OTP zone. - * @note This function must be used when the device voltage range is from 2.7V to 3.6V. * @param Data: specifies the data to be programmed. * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. @@ -525,7 +781,11 @@ FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) /** * @brief Programs a half word (16-bit) at a specified address. - * @note This function must be used when the device voltage range is from 2.1V to 3.6V. + * @note This function must be used when the device voltage range is from 2.1V to 3.6V. + * + * @note If an erase and a program operations are requested simustaneously, + * the erase operation is performed before the program one. + * * @param Address: specifies the address to be programmed. * This parameter can be any address in Program memory zone or in OTP zone. * @param Data: specifies the data to be programmed. @@ -563,7 +823,11 @@ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) /** * @brief Programs a byte (8-bit) at a specified address. - * @note This function can be used within all the device supply voltage ranges. + * @note This function can be used within all the device supply voltage ranges. + * + * @note If an erase and a program operations are requested simustaneously, + * the erase operation is performed before the program one. + * * @param Address: specifies the address to be programmed. * This parameter can be any address in Program memory zone or in OTP zone. * @param Data: specifies the data to be programmed. @@ -609,42 +873,56 @@ FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) * @verbatim =============================================================================== - Option Bytes Programming functions + ##### Option Bytes Programming functions ##### =============================================================================== - - This group includes the following functions: - - void FLASH_OB_Unlock(void) - - void FLASH_OB_Lock(void) - - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) - - void FLASH_OB_RDPConfig(uint8_t OB_RDP) - - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) - - void FLASH_OB_BORConfig(uint8_t OB_BOR) - - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) - - FLASH_Status FLASH_OB_Launch(void) - - uint32_t FLASH_OB_GetUser(void) - - uint8_t FLASH_OB_GetWRP(void) - - uint8_t FLASH_OB_GetRDP(void) - - uint8_t FLASH_OB_GetBOR(void) - - Any operation of erase or program should follow these steps: - 1. Call the FLASH_OB_Unlock() function to enable the FLASH option control register access - - 2. Call one or several functions to program the desired Option Bytes: - - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable - the desired sector write protection - - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level - - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure - the user Option Bytes. - - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level - - 3. Once all needed Option Bytes to be programmed are correctly written, call the - FLASH_OB_Launch() function to launch the Option Bytes programming process. + [..] + This group includes the following functions: + (+) void FLASH_OB_Unlock(void) + (+) void FLASH_OB_Lock(void) + (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) + (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState) + (+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect) + (+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState) + (+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) + (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP) + (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) + (+) void FLASH_OB_BORConfig(uint8_t OB_BOR) + (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) + (+) FLASH_Status FLASH_OB_Launch(void) + (+) uint32_t FLASH_OB_GetUser(void) + (+) uint8_t FLASH_OB_GetWRP(void) + (+) uint8_t FLASH_OB_GetWRP1(void) + (+) uint8_t FLASH_OB_GetPCROP(void) + (+) uint8_t FLASH_OB_GetPCROP1(void) + (+) uint8_t FLASH_OB_GetRDP(void) + (+) uint8_t FLASH_OB_GetBOR(void) + [..] + The following function can be used only for STM32F42xxx/43xxx devices. + (+) void FLASH_OB_BootConfig(uint8_t OB_BOOT) + [..] + Any operation of erase or program should follow these steps: + (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control + register access + + (#) Call one or several functions to program the desired Option Bytes: + (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) + => to Enable/Disable the desired sector write protection + (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read + Protection Level + (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) + => to configure the user Option Bytes. + (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level + + (#) Once all needed Option Bytes to be programmed are correctly written, + call the FLASH_OB_Launch() function to launch the Option Bytes + programming process. - @note When changing the IWDG mode from HW to SW or from SW to HW, a system - reset is needed to make the change effective. + -@- When changing the IWDG mode from HW to SW or from SW to HW, a system + reset is needed to make the change effective. - 4. Call the FLASH_OB_Lock() function to disable the FLASH option control register - access (recommended to protect the Option Bytes against possible unwanted operations) + (#) Call the FLASH_OB_Lock() function to disable the FLASH option control + register access (recommended to protect the Option Bytes against + possible unwanted operations) @endverbatim * @{ @@ -677,7 +955,14 @@ void FLASH_OB_Lock(void) } /** - * @brief Enables or disables the write protection of the desired sectors + * @brief Enables or disables the write protection of the desired sectors, for the first + * 1 Mb of the Flash + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. * This parameter can be one of the following values: * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11 @@ -709,6 +994,166 @@ void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) } } +/** + * @brief Enables or disables the write protection of the desired sectors, for the second + * 1 Mb of the Flash + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note When the memory read out protection is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23 + * @arg OB_WRP_Sector_All + * @param Newstate: new state of the Write Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_WRP(OB_WRP)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + if(NewState != DISABLE) + { + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP); + } + else + { + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP; + } + } +} + +/** + * @brief Select the Protection Mode (SPRMOD). + * + * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices. + * + * @note After PCROP activation, Option Byte modification is not possible. + * Exception made for the global Read Out Protection modification level (level1 to level0) + * @note Once SPRMOD bit is active unprotection of a protected sector is not possible + * + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * + * @note Some Precautions should be taken when activating the PCROP feature : + * The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1 + * and WRPi = 1 (default value), then the user sector i is read/write protected. + * In order to avoid activation of PCROP Mode for undesired sectors, please follow the + * below safety sequence : + * - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function + * for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2 + * - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function + * - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function. + * + * @param OB_PCROP: Select the Protection Mode of nWPRi bits + * This parameter can be one of the following values: + * @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors. + * @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors. + * @retval None + */ +void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP) +{ + uint8_t optiontmp = 0xFF; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_SELECT(OB_PcROP)); + + /* Mask SPRMOD bit */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); + /* Update Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp); + +} + +/** + * @brief Enables or disables the read/write protection (PCROP) of the desired + * sectors, for the first 1 MB of the Flash. + * + * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices. + * + * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for + * STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and + * OB_PCROP_Sector5 for STM32F401xx devices. + * @arg OB_PCROP_Sector_All + * @param Newstate: new state of the Write Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_PCROP(OB_PCROP)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + if(NewState != DISABLE) + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP; + } + else + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP); + } + } +} + +/** + * @brief Enables or disables the read/write protection (PCROP) of the desired + * sectors + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23 + * @arg OB_PCROP_Sector_All + * @param Newstate: new state of the Write Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_PCROP(OB_PCROP)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + if(NewState != DISABLE) + { + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP; + } + else + { + *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP); + } + } +} + + /** * @brief Sets the read protection level. * @param OB_RDP: specifies the read protection level. @@ -717,7 +1162,7 @@ void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) * @arg OB_RDP_Level_1: Read protection of the memory * @arg OB_RDP_Level_2: Full chip protection * - * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 * * @retval None */ @@ -768,14 +1213,43 @@ void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) if(status == FLASH_COMPLETE) { +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) + /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#if defined (STM32F40_41xxx) || defined (STM32F401xx) /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */ optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); +#endif /* STM32F40_41xxx || STM32F401xx */ /* Update User Option Byte */ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); } } +/** + * @brief Configure the Dual Bank Boot. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @param OB_BOOT: specifies the Dual Bank Boot Option byte. + * This parameter can be one of the following values: + * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable + * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled + * @retval None + */ +void FLASH_OB_BootConfig(uint8_t OB_BOOT) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOT(OB_BOOT)); + + /* Set Dual Bank Boot */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2); + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT; + +} + /** * @brief Sets the BOR Level. * @param OB_BOR: specifies the Option Bytes BOR Reset Level. @@ -839,6 +1313,48 @@ uint16_t FLASH_OB_GetWRP(void) return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); } +/** + * @brief Returns the FLASH Write Protection Option Bytes value. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @param None + * @retval The FLASH Write Protection Option Bytes value + */ +uint16_t FLASH_OB_GetWRP1(void) +{ + /* Return the FLASH write protection Register value */ + return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); +} + +/** + * @brief Returns the FLASH PC Read/Write Protection Option Bytes value. + * + * @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx devices. + * + * @param None + * @retval The FLASH PC Read/Write Protection Option Bytes value + */ +uint16_t FLASH_OB_GetPCROP(void) +{ + /* Return the FLASH PC Read/write protection Register value */ + return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); +} + +/** + * @brief Returns the FLASH PC Read/Write Protection Option Bytes value. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @param None + * @retval The FLASH PC Read/Write Protection Option Bytes value + */ +uint16_t FLASH_OB_GetPCROP1(void) +{ + /* Return the FLASH write protection Register value */ + return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); +} + /** * @brief Returns the FLASH Read Protection level. * @param None @@ -885,9 +1401,8 @@ uint8_t FLASH_OB_GetBOR(void) * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== - @endverbatim * @{ */ @@ -928,6 +1443,7 @@ void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42/43xxx and STM32F401xx devices) * @arg FLASH_FLAG_BSY: FLASH Busy flag * @retval The new state of FLASH_FLAG (SET or RESET). */ @@ -959,6 +1475,7 @@ FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42/43xxx and STM32F401xx devices) * @retval None */ void FLASH_ClearFlag(uint32_t FLASH_FLAG) @@ -974,7 +1491,7 @@ void FLASH_ClearFlag(uint32_t FLASH_FLAG) * @brief Returns the FLASH Status. * @param None * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + * FLASH_ERROR_WRP, FLASH_ERROR_RD, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_GetStatus(void) { @@ -990,21 +1507,28 @@ FLASH_Status FLASH_GetStatus(void) { flashstatus = FLASH_ERROR_WRP; } - else + else { - if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_PROGRAM; - } - else + if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00) + { + flashstatus = FLASH_ERROR_RD; + } + else { - if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00) + if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00) { - flashstatus = FLASH_ERROR_OPERATION; + flashstatus = FLASH_ERROR_PROGRAM; } else { - flashstatus = FLASH_COMPLETE; + if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00) + { + flashstatus = FLASH_ERROR_OPERATION; + } + else + { + flashstatus = FLASH_COMPLETE; + } } } } @@ -1053,4 +1577,4 @@ FLASH_Status FLASH_WaitForLastOperation(void) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c new file mode 100644 index 0000000000..63d4baf9dc --- /dev/null +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c @@ -0,0 +1,1373 @@ +/** + ****************************************************************************** + * @file stm32f4xx_fmc.c + * @author MCD Application Team + * @version V1.3.0 + * @date 08-November-2013 + * @brief This file provides firmware functions to manage the following + * functionalities of the FMC peripheral: + * + Interface with SRAM, PSRAM, NOR and OneNAND memories + * + Interface with NAND memories + * + Interface with 16-bit PC Card compatible memories + * + Interface with SDRAM memories + * + Interrupts and flags management + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_fmc.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup FMC + * @brief FMC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* --------------------- FMC registers bit mask ---------------------------- */ +/* FMC BCRx Mask */ +#define BCR_MBKEN_SET ((uint32_t)0x00000001) +#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_SET ((uint32_t)0x00000040) + +/* FMC PCRx Mask */ +#define PCR_PBKEN_SET ((uint32_t)0x00000004) +#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_SET ((uint32_t)0x00000040) +#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) +#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) + +/* FMC SDCRx write protection Mask*/ +#define SDCR_WriteProtection_RESET ((uint32_t)0x00007DFF) + +/* FMC SDCMR Mask*/ +#define SDCMR_CTB1_RESET ((uint32_t)0x003FFFEF) +#define SDCMR_CTB2_RESET ((uint32_t)0x003FFFF7) +#define SDCMR_CTB1_2_RESET ((uint32_t)0x003FFFE7) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FMC_Private_Functions + * @{ + */ + +/** @defgroup FMC_Group1 NOR/SRAM Controller functions + * @brief NOR/SRAM Controller functions + * +@verbatim + =============================================================================== + ##### NOR and SRAM Controller functions ##### + =============================================================================== + + [..] The following sequence should be followed to configure the FMC to interface + with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: + + (#) Enable the clock for the FMC and associated GPIOs using the following functions: + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) FMC pins configuration + (++) Connect the involved FMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); + (++) Configure these FMC pins in alternate function mode by calling the function + GPIO_Init(); + + (#) Declare a FMC_NORSRAMInitTypeDef structure, for example: + FMC_NORSRAMInitTypeDef FMC_NORSRAMInitStructure; + and fill the FMC_NORSRAMInitStructure variable with the allowed values of + the structure member. + + (#) Initialize the NOR/SRAM Controller by calling the function + FMC_NORSRAMInit(&FMC_NORSRAMInitStructure); + + (#) Then enable the NOR/SRAM Bank, for example: + FMC_NORSRAMCmd(FMC_Bank1_NORSRAM2, ENABLE); + + (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the FMC NOR/SRAM Banks registers to their default + * reset values. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1 + * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2 + * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3 + * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4 + * @retval None + */ +void FMC_NORSRAMDeInit(uint32_t FMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank)); + + /* FMC_Bank1_NORSRAM1 */ + if(FMC_Bank == FMC_Bank1_NORSRAM1) + { + FMC_Bank1->BTCR[FMC_Bank] = 0x000030DB; + } + /* FMC_Bank1_NORSRAM2, FMC_Bank1_NORSRAM3 or FMC_Bank1_NORSRAM4 */ + else + { + FMC_Bank1->BTCR[FMC_Bank] = 0x000030D2; + } + FMC_Bank1->BTCR[FMC_Bank + 1] = 0x0FFFFFFF; + FMC_Bank1E->BWTR[FMC_Bank] = 0x0FFFFFFF; +} + +/** + * @brief Initializes the FMC NOR/SRAM Banks according to the specified + * parameters in the FMC_NORSRAMInitStruct. + * @param FMC_NORSRAMInitStruct : pointer to a FMC_NORSRAMInitTypeDef structure + * that contains the configuration information for the FMC NOR/SRAM + * specified Banks. + * @retval None + */ +void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank)); + assert_param(IS_FMC_MUX(FMC_NORSRAMInitStruct->FMC_DataAddressMux)); + assert_param(IS_FMC_MEMORY(FMC_NORSRAMInitStruct->FMC_MemoryType)); + assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(FMC_NORSRAMInitStruct->FMC_MemoryDataWidth)); + assert_param(IS_FMC_BURSTMODE(FMC_NORSRAMInitStruct->FMC_BurstAccessMode)); + assert_param(IS_FMC_WAIT_POLARITY(FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity)); + assert_param(IS_FMC_WRAP_MODE(FMC_NORSRAMInitStruct->FMC_WrapMode)); + assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(FMC_NORSRAMInitStruct->FMC_WaitSignalActive)); + assert_param(IS_FMC_WRITE_OPERATION(FMC_NORSRAMInitStruct->FMC_WriteOperation)); + assert_param(IS_FMC_WAITE_SIGNAL(FMC_NORSRAMInitStruct->FMC_WaitSignal)); + assert_param(IS_FMC_EXTENDED_MODE(FMC_NORSRAMInitStruct->FMC_ExtendedMode)); + assert_param(IS_FMC_ASYNWAIT(FMC_NORSRAMInitStruct->FMC_AsynchronousWait)); + assert_param(IS_FMC_WRITE_BURST(FMC_NORSRAMInitStruct->FMC_WriteBurst)); + assert_param(IS_FMC_CONTINOUS_CLOCK(FMC_NORSRAMInitStruct->FMC_ContinousClock)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration)); + assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode)); + + /* NOR/SRAM Bank control register configuration */ + FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] = + (uint32_t)FMC_NORSRAMInitStruct->FMC_DataAddressMux | + FMC_NORSRAMInitStruct->FMC_MemoryType | + FMC_NORSRAMInitStruct->FMC_MemoryDataWidth | + FMC_NORSRAMInitStruct->FMC_BurstAccessMode | + FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity | + FMC_NORSRAMInitStruct->FMC_WrapMode | + FMC_NORSRAMInitStruct->FMC_WaitSignalActive | + FMC_NORSRAMInitStruct->FMC_WriteOperation | + FMC_NORSRAMInitStruct->FMC_WaitSignal | + FMC_NORSRAMInitStruct->FMC_ExtendedMode | + FMC_NORSRAMInitStruct->FMC_AsynchronousWait | + FMC_NORSRAMInitStruct->FMC_WriteBurst | + FMC_NORSRAMInitStruct->FMC_ContinousClock; + + + if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR) + { + FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (uint32_t)BCR_FACCEN_SET; + } + + /* Configure Continuous clock feature when bank2..4 is used */ + if((FMC_NORSRAMInitStruct->FMC_ContinousClock == FMC_CClock_SyncAsync) && (FMC_NORSRAMInitStruct->FMC_Bank != FMC_Bank1_NORSRAM1)) + { + tmpr = (uint32_t)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((uint32_t)0x0F) << 20)); + + FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_NORSRAMInitStruct->FMC_ContinousClock; + FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_BurstAccessMode_Enable; + FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (uint32_t)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20)); + } + + /* NOR/SRAM Bank timing register configuration */ + FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] = + (uint32_t)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime | + (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) | + (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) | + (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) | + ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision) << 20) | + ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency) << 24) | + FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode; + + /* NOR/SRAM Bank timing register for write configuration, if extended mode is used */ + if(FMC_NORSRAMInitStruct->FMC_ExtendedMode == FMC_ExtendedMode_Enable) + { + assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime)); + assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode)); + + FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = + (uint32_t)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime | + (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4 )| + (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) | + ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision) << 20) | + ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency) << 24) | + FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode; + } + else + { + FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = 0x0FFFFFFF; + } + +} + +/** + * @brief Fills each FMC_NORSRAMInitStruct member with its default value. + * @param FMC_NORSRAMInitStruct: pointer to a FMC_NORSRAMInitTypeDef structure + * which will be initialized. + * @retval None + */ +void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FMC_NORSRAMInitStruct->FMC_Bank = FMC_Bank1_NORSRAM1; + FMC_NORSRAMInitStruct->FMC_DataAddressMux = FMC_DataAddressMux_Enable; + FMC_NORSRAMInitStruct->FMC_MemoryType = FMC_MemoryType_SRAM; + FMC_NORSRAMInitStruct->FMC_MemoryDataWidth = FMC_NORSRAM_MemoryDataWidth_16b; + FMC_NORSRAMInitStruct->FMC_BurstAccessMode = FMC_BurstAccessMode_Disable; + FMC_NORSRAMInitStruct->FMC_AsynchronousWait = FMC_AsynchronousWait_Disable; + FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low; + FMC_NORSRAMInitStruct->FMC_WrapMode = FMC_WrapMode_Disable; + FMC_NORSRAMInitStruct->FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState; + FMC_NORSRAMInitStruct->FMC_WriteOperation = FMC_WriteOperation_Enable; + FMC_NORSRAMInitStruct->FMC_WaitSignal = FMC_WaitSignal_Enable; + FMC_NORSRAMInitStruct->FMC_ExtendedMode = FMC_ExtendedMode_Disable; + FMC_NORSRAMInitStruct->FMC_WriteBurst = FMC_WriteBurst_Disable; + FMC_NORSRAMInitStruct->FMC_ContinousClock = FMC_CClock_SyncOnly; + + FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime = 15; + FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime = 15; + FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime = 255; + FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration = 15; + FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision = 15; + FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency = 15; + FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A; + FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime = 15; + FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime = 15; + FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime = 255; + FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_BusTurnAroundDuration = 15; + FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision = 15; + FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency = 15; + FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1 + * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2 + * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3 + * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4 + * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FMC_Bank1->BTCR[FMC_Bank] |= BCR_MBKEN_SET; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FMC_Bank1->BTCR[FMC_Bank] &= BCR_MBKEN_RESET; + } +} +/** + * @} + */ + +/** @defgroup FMC_Group2 NAND Controller functions + * @brief NAND Controller functions + * +@verbatim + =============================================================================== + ##### NAND Controller functions ##### + =============================================================================== + + [..] The following sequence should be followed to configure the FMC to interface + with 8-bit or 16-bit NAND memory connected to the NAND Bank: + + (#) Enable the clock for the FMC and associated GPIOs using the following functions: + (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); + (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) FMC pins configuration + (++) Connect the involved FMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); + (++) Configure these FMC pins in alternate function mode by calling the function + GPIO_Init(); + + (#) Declare a FMC_NANDInitTypeDef structure, for example: + FMC_NANDInitTypeDef FMC_NANDInitStructure; + and fill the FMC_NANDInitStructure variable with the allowed values of + the structure member. + + (#) Initialize the NAND Controller by calling the function + FMC_NANDInit(&FMC_NANDInitStructure); + + (#) Then enable the NAND Bank, for example: + FMC_NANDCmd(FMC_Bank3_NAND, ENABLE); + + (#) At this stage you can read/write from/to the memory connected to the NAND Bank. + + [..] + (@) To enable the Error Correction Code (ECC), you have to use the function + FMC_NANDECCCmd(FMC_Bank3_NAND, ENABLE); + [..] + (@) and to get the current ECC value you have to use the function + ECCval = FMC_GetECC(FMC_Bank3_NAND); + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the FMC NAND Banks registers to their default reset values. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @retval None + */ +void FMC_NANDDeInit(uint32_t FMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FMC_NAND_BANK(FMC_Bank)); + + if(FMC_Bank == FMC_Bank2_NAND) + { + /* Set the FMC_Bank2 registers to their reset values */ + FMC_Bank2->PCR2 = 0x00000018; + FMC_Bank2->SR2 = 0x00000040; + FMC_Bank2->PMEM2 = 0xFCFCFCFC; + FMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FMC_Bank3_NAND */ + else + { + /* Set the FMC_Bank3 registers to their reset values */ + FMC_Bank3->PCR3 = 0x00000018; + FMC_Bank3->SR3 = 0x00000040; + FMC_Bank3->PMEM3 = 0xFCFCFCFC; + FMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/** + * @brief Initializes the FMC NAND Banks according to the specified parameters + * in the FMC_NANDInitStruct. + * @param FMC_NANDInitStruct : pointer to a FMC_NANDInitTypeDef structure that + * contains the configuration information for the FMC NAND specified Banks. + * @retval None + */ +void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_BANK(FMC_NANDInitStruct->FMC_Bank)); + assert_param(IS_FMC_WAIT_FEATURE(FMC_NANDInitStruct->FMC_Waitfeature)); + assert_param(IS_FMC_NAND_MEMORY_WIDTH(FMC_NANDInitStruct->FMC_MemoryDataWidth)); + assert_param(IS_FMC_ECC_STATE(FMC_NANDInitStruct->FMC_ECC)); + assert_param(IS_FMC_ECCPAGE_SIZE(FMC_NANDInitStruct->FMC_ECCPageSize)); + assert_param(IS_FMC_TCLR_TIME(FMC_NANDInitStruct->FMC_TCLRSetupTime)); + assert_param(IS_FMC_TAR_TIME(FMC_NANDInitStruct->FMC_TARSetupTime)); + assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime)); + assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime)); + assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime)); + assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime)); + + /* Set the tmppcr value according to FMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)FMC_NANDInitStruct->FMC_Waitfeature | + PCR_MEMORYTYPE_NAND | + FMC_NANDInitStruct->FMC_MemoryDataWidth | + FMC_NANDInitStruct->FMC_ECC | + FMC_NANDInitStruct->FMC_ECCPageSize | + (FMC_NANDInitStruct->FMC_TCLRSetupTime << 9 )| + (FMC_NANDInitStruct->FMC_TARSetupTime << 13); + + /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime | + (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) | + (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)| + (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime | + (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) | + (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)| + (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24); + + if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND) + { + /* FMC_Bank2_NAND registers configuration */ + FMC_Bank2->PCR2 = tmppcr; + FMC_Bank2->PMEM2 = tmppmem; + FMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FMC_Bank3_NAND registers configuration */ + FMC_Bank3->PCR3 = tmppcr; + FMC_Bank3->PMEM3 = tmppmem; + FMC_Bank3->PATT3 = tmppatt; + } +} + + +/** + * @brief Fills each FMC_NANDInitStruct member with its default value. + * @param FMC_NANDInitStruct: pointer to a FMC_NANDInitTypeDef structure which + * will be initialized. + * @retval None + */ +void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FMC_NANDInitStruct->FMC_Bank = FMC_Bank2_NAND; + FMC_NANDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable; + FMC_NANDInitStruct->FMC_MemoryDataWidth = FMC_NAND_MemoryDataWidth_16b; + FMC_NANDInitStruct->FMC_ECC = FMC_ECC_Disable; + FMC_NANDInitStruct->FMC_ECCPageSize = FMC_ECCPageSize_256Bytes; + FMC_NANDInitStruct->FMC_TCLRSetupTime = 0x0; + FMC_NANDInitStruct->FMC_TARSetupTime = 0x0; + FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252; + FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252; + FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252; + FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252; + FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252; + FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252; + FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252; + FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252; +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FMC_NAND_BANK(FMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->PCR2 |= PCR_PBKEN_SET; + } + else + { + FMC_Bank3->PCR3 |= PCR_PBKEN_SET; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->PCR2 &= PCR_PBKEN_RESET; + } + else + { + FMC_Bank3->PCR3 &= PCR_PBKEN_RESET; + } + } +} +/** + * @brief Enables or disables the FMC NAND ECC feature. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @param NewState: new state of the FMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FMC_NAND_BANK(FMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->PCR2 |= PCR_ECCEN_SET; + } + else + { + FMC_Bank3->PCR3 |= PCR_ECCEN_SET; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->PCR2 &= PCR_ECCEN_RESET; + } + else + { + FMC_Bank3->PCR3 &= PCR_ECCEN_RESET; + } + } +} + +/** + * @brief Returns the error correction code register value. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @retval The Error Correction Code (ECC) value. + */ +uint32_t FMC_GetECC(uint32_t FMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FMC_Bank == FMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} +/** + * @} + */ + +/** @defgroup FMC_Group3 PCCARD Controller functions + * @brief PCCARD Controller functions + * +@verbatim + =============================================================================== + ##### PCCARD Controller functions ##### + =============================================================================== + + [..] he following sequence should be followed to configure the FMC to interface + with 16-bit PC Card compatible memory connected to the PCCARD Bank: + + (#) Enable the clock for the FMC and associated GPIOs using the following functions: + (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); + (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) FMC pins configuration + (++) Connect the involved FMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); + (++) Configure these FMC pins in alternate function mode by calling the function + GPIO_Init(); + + (#) Declare a FMC_PCCARDInitTypeDef structure, for example: + FMC_PCCARDInitTypeDef FMC_PCCARDInitStructure; + and fill the FMC_PCCARDInitStructure variable with the allowed values of + the structure member. + + (#) Initialize the PCCARD Controller by calling the function + FMC_PCCARDInit(&FMC_PCCARDInitStructure); + + (#) Then enable the PCCARD Bank: + FMC_PCCARDCmd(ENABLE); + + (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank. + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the FMC PCCARD Bank registers to their default reset values. + * @param None + * @retval None + */ +void FMC_PCCARDDeInit(void) +{ + /* Set the FMC_Bank4 registers to their reset values */ + FMC_Bank4->PCR4 = 0x00000018; + FMC_Bank4->SR4 = 0x00000000; + FMC_Bank4->PMEM4 = 0xFCFCFCFC; + FMC_Bank4->PATT4 = 0xFCFCFCFC; + FMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/** + * @brief Initializes the FMC PCCARD Bank according to the specified parameters + * in the FMC_PCCARDInitStruct. + * @param FMC_PCCARDInitStruct : pointer to a FMC_PCCARDInitTypeDef structure + * that contains the configuration information for the FMC PCCARD Bank. + * @retval None + */ +void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FMC_WAIT_FEATURE(FMC_PCCARDInitStruct->FMC_Waitfeature)); + assert_param(IS_FMC_TCLR_TIME(FMC_PCCARDInitStruct->FMC_TCLRSetupTime)); + assert_param(IS_FMC_TAR_TIME(FMC_PCCARDInitStruct->FMC_TARSetupTime)); + + assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime)); + assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime)); + + assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime)); + assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime)); + assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime)); + assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */ + FMC_Bank4->PCR4 = (uint32_t)FMC_PCCARDInitStruct->FMC_Waitfeature | + FMC_NAND_MemoryDataWidth_16b | + (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) | + (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */ + FMC_Bank4->PMEM4 = (uint32_t)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime | + (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) | + (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)| + (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */ + FMC_Bank4->PATT4 = (uint32_t)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime | + (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) | + (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)| + (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */ + FMC_Bank4->PIO4 = (uint32_t)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime | + (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) | + (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)| + (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24); +} + +/** + * @brief Fills each FMC_PCCARDInitStruct member with its default value. + * @param FMC_PCCARDInitStruct: pointer to a FMC_PCCARDInitTypeDef structure + * which will be initialized. + * @retval None + */ +void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FMC_PCCARDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable; + FMC_PCCARDInitStruct->FMC_TCLRSetupTime = 0; + FMC_PCCARDInitStruct->FMC_TARSetupTime = 0; + FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252; + FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252; + FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252; + FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252; + FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252; + FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252; + FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252; + FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252; + FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime = 252; + FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime = 252; + FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime = 252; + FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime = 252; +} + +/** + * @brief Enables or disables the PCCARD Memory Bank. + * @param NewState: new state of the PCCARD Memory Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FMC_Bank4->PCR4 |= PCR_PBKEN_SET; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FMC_Bank4->PCR4 &= PCR_PBKEN_RESET; + } +} + +/** + * @} + */ + +/** @defgroup FMC_Group4 SDRAM Controller functions + * @brief SDRAM Controller functions + * +@verbatim + =============================================================================== + ##### SDRAM Controller functions ##### + =============================================================================== + + [..] The following sequence should be followed to configure the FMC to interface + with SDRAM memory connected to the SDRAM Bank 1 or SDRAM bank 2: + + (#) Enable the clock for the FMC and associated GPIOs using the following functions: + (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); + (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) FMC pins configuration + (++) Connect the involved FMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); + (++) Configure these FMC pins in alternate function mode by calling the function + GPIO_Init(); + + (#) Declare a FMC_SDRAMInitTypeDef structure, for example: + FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; + and fill the FMC_SDRAMInitStructure variable with the allowed values of + the structure member. + + (#) Initialize the SDRAM Controller by calling the function + FMC_SDRAMInit(&FMC_SDRAMInitStructure); + + (#) Declare a FMC_SDRAMCommandTypeDef structure, for example: + FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; + and fill the FMC_SDRAMCommandStructure variable with the allowed values of + the structure member. + + (#) Configure the SDCMR register with the desired command parameters by calling + the function FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + + (#) At this stage, the SDRAM memory is ready for any valid command. + +@endverbatim + * @{ + */ + +/** + * @brief De-initializes the FMC SDRAM Banks registers to their default + * reset values. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM + * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM + * @retval None + */ +void FMC_SDRAMDeInit(uint32_t FMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FMC_SDRAM_BANK(FMC_Bank)); + + FMC_Bank5_6->SDCR[FMC_Bank] = 0x000002D0; + FMC_Bank5_6->SDTR[FMC_Bank] = 0x0FFFFFFF; + FMC_Bank5_6->SDCMR = 0x00000000; + FMC_Bank5_6->SDRTR = 0x00000000; + FMC_Bank5_6->SDSR = 0x00000000; +} + +/** + * @brief Initializes the FMC SDRAM Banks according to the specified + * parameters in the FMC_SDRAMInitStruct. + * @param FMC_SDRAMInitStruct : pointer to a FMC_SDRAMInitTypeDef structure + * that contains the configuration information for the FMC SDRAM + * specified Banks. + * @retval None + */ +void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct) +{ + /* temporary registers */ + uint32_t tmpr1 = 0; + uint32_t tmpr2 = 0; + uint32_t tmpr3 = 0; + uint32_t tmpr4 = 0; + + /* Check the parameters */ + + /* Control parameters */ + assert_param(IS_FMC_SDRAM_BANK(FMC_SDRAMInitStruct->FMC_Bank)); + assert_param(IS_FMC_COLUMNBITS_NUMBER(FMC_SDRAMInitStruct->FMC_ColumnBitsNumber)); + assert_param(IS_FMC_ROWBITS_NUMBER(FMC_SDRAMInitStruct->FMC_RowBitsNumber)); + assert_param(IS_FMC_SDMEMORY_WIDTH(FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth)); + assert_param(IS_FMC_INTERNALBANK_NUMBER(FMC_SDRAMInitStruct->FMC_InternalBankNumber)); + assert_param(IS_FMC_CAS_LATENCY(FMC_SDRAMInitStruct->FMC_CASLatency)); + assert_param(IS_FMC_WRITE_PROTECTION(FMC_SDRAMInitStruct->FMC_WriteProtection)); + assert_param(IS_FMC_SDCLOCK_PERIOD(FMC_SDRAMInitStruct->FMC_SDClockPeriod)); + assert_param(IS_FMC_READ_BURST(FMC_SDRAMInitStruct->FMC_ReadBurst)); + assert_param(IS_FMC_READPIPE_DELAY(FMC_SDRAMInitStruct->FMC_ReadPipeDelay)); + + /* Timing parameters */ + assert_param(IS_FMC_LOADTOACTIVE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)); + assert_param(IS_FMC_EXITSELFREFRESH_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)); + assert_param(IS_FMC_SELFREFRESH_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)); + assert_param(IS_FMC_ROWCYCLE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)); + assert_param(IS_FMC_WRITE_RECOVERY_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)); + assert_param(IS_FMC_RP_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)); + assert_param(IS_FMC_RCD_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)); + + /* SDRAM bank control register configuration */ + tmpr1 = (uint32_t)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber | + FMC_SDRAMInitStruct->FMC_RowBitsNumber | + FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth | + FMC_SDRAMInitStruct->FMC_InternalBankNumber | + FMC_SDRAMInitStruct->FMC_CASLatency | + FMC_SDRAMInitStruct->FMC_WriteProtection | + FMC_SDRAMInitStruct->FMC_SDClockPeriod | + FMC_SDRAMInitStruct->FMC_ReadBurst | + FMC_SDRAMInitStruct->FMC_ReadPipeDelay; + + if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM ) + { + FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1; + } + else /* SDCR2 "don't care" bits configuration */ + { + tmpr3 = (uint32_t)FMC_SDRAMInitStruct->FMC_SDClockPeriod | + FMC_SDRAMInitStruct->FMC_ReadBurst | + FMC_SDRAMInitStruct->FMC_ReadPipeDelay; + + FMC_Bank5_6->SDCR[FMC_Bank1_SDRAM] = tmpr3; + FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1; + } + /* SDRAM bank timing register configuration */ + if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM ) + { + tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24); + + FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2; + } + else /* SDTR "don't care bits configuration */ + { + tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16); + + tmpr4 = (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) | + (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20); + + FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4; + FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2; + } + +} + +/** + * @brief Fills each FMC_SDRAMInitStruct member with its default value. + * @param FMC_SDRAMInitStruct: pointer to a FMC_SDRAMInitTypeDef structure + * which will be initialized. + * @retval None + */ +void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct) +{ + /* Reset SDRAM Init structure parameters values */ + FMC_SDRAMInitStruct->FMC_Bank = FMC_Bank1_SDRAM; + FMC_SDRAMInitStruct->FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; + FMC_SDRAMInitStruct->FMC_RowBitsNumber = FMC_RowBits_Number_11b; + FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b; + FMC_SDRAMInitStruct->FMC_InternalBankNumber = FMC_InternalBank_Number_4; + FMC_SDRAMInitStruct->FMC_CASLatency = FMC_CAS_Latency_1; + FMC_SDRAMInitStruct->FMC_WriteProtection = FMC_Write_Protection_Enable; + FMC_SDRAMInitStruct->FMC_SDClockPeriod = FMC_SDClock_Disable; + FMC_SDRAMInitStruct->FMC_ReadBurst = FMC_Read_Burst_Disable; + FMC_SDRAMInitStruct->FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0; + + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay = 16; + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay = 16; + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime = 16; + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay = 16; + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime = 16; + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay = 16; + FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay = 16; + +} + +/** + * @brief Configures the SDRAM memory command issued when the device is accessed. + * @param FMC_SDRAMCommandStruct: pointer to a FMC_SDRAMCommandTypeDef structure + * which will be configured. + * @retval None + */ +void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct) +{ + uint32_t tmpr = 0x0; + + /* check parameters */ + assert_param(IS_FMC_COMMAND_MODE(FMC_SDRAMCommandStruct->FMC_CommandMode)); + assert_param(IS_FMC_COMMAND_TARGET(FMC_SDRAMCommandStruct->FMC_CommandTarget)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)); + assert_param(IS_FMC_MODE_REGISTER(FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)); + + tmpr = (uint32_t)(FMC_SDRAMCommandStruct->FMC_CommandMode | + FMC_SDRAMCommandStruct->FMC_CommandTarget | + (((FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)-1)<<5) | + ((FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)<<9)); + + FMC_Bank5_6->SDCMR = tmpr; + +} + + +/** + * @brief Returns the indicated FMC SDRAM bank mode status. + * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be + * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. + * @retval The FMC SDRAM bank mode status + */ +uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank) +{ + uint32_t tmpreg = 0; + + /* Check the parameter */ + assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank)); + + /* Get the busy flag status */ + if(SDRAM_Bank == FMC_Bank1_SDRAM) + { + tmpreg = (uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1); + } + else + { + tmpreg = ((uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2); + } + + /* Return the mode status */ + return tmpreg; +} + +/** + * @brief defines the SDRAM Memory Refresh rate. + * @param FMC_Count: specifies the Refresh timer count. + * @retval None + */ +void FMC_SetRefreshCount(uint32_t FMC_Count) +{ + /* check the parameters */ + assert_param(IS_FMC_REFRESH_COUNT(FMC_Count)); + + FMC_Bank5_6->SDRTR |= (FMC_Count<<1); + +} + +/** + * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. + * @param FMC_Number: specifies the auto Refresh number. + * @retval None + */ +void FMC_SetAutoRefresh_Number(uint32_t FMC_Number) +{ + /* check the parameters */ + assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_Number)); + + FMC_Bank5_6->SDCMR |= (FMC_Number << 5); +} + +/** + * @brief Enables or disables write protection to the specified FMC SDRAM Bank. + * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be + * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. + * @param NewState: new state of the write protection flag. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState) +{ + /* Check the parameter */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank)); + + if (NewState != DISABLE) + { + FMC_Bank5_6->SDCR[SDRAM_Bank] |= FMC_Write_Protection_Enable; + } + else + { + FMC_Bank5_6->SDCR[SDRAM_Bank] &= SDCR_WriteProtection_RESET; + } + +} + +/** + * @} + */ + +/** @defgroup FMC_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified FMC interrupts. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD + * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM + * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM + * @param FMC_IT: specifies the FMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FMC_IT_Level: Level edge detection interrupt. + * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. + * @arg FMC_IT_Refresh: Refresh error detection interrupt. + * @param NewState: new state of the specified FMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState) +{ + assert_param(IS_FMC_IT_BANK(FMC_Bank)); + assert_param(IS_FMC_IT(FMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FMC_Bank2 interrupts */ + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->SR2 |= FMC_IT; + } + /* Enable the selected FMC_Bank3 interrupts */ + else if (FMC_Bank == FMC_Bank3_NAND) + { + FMC_Bank3->SR3 |= FMC_IT; + } + /* Enable the selected FMC_Bank4 interrupts */ + else if (FMC_Bank == FMC_Bank4_PCCARD) + { + FMC_Bank4->SR4 |= FMC_IT; + } + /* Enable the selected FMC_Bank5_6 interrupt */ + else + { + /* Enables the interrupt if the refresh error flag is set */ + FMC_Bank5_6->SDRTR |= FMC_IT; + } + } + else + { + /* Disable the selected FMC_Bank2 interrupts */ + if(FMC_Bank == FMC_Bank2_NAND) + { + + FMC_Bank2->SR2 &= (uint32_t)~FMC_IT; + } + /* Disable the selected FMC_Bank3 interrupts */ + else if (FMC_Bank == FMC_Bank3_NAND) + { + FMC_Bank3->SR3 &= (uint32_t)~FMC_IT; + } + /* Disable the selected FMC_Bank4 interrupts */ + else if(FMC_Bank == FMC_Bank4_PCCARD) + { + FMC_Bank4->SR4 &= (uint32_t)~FMC_IT; + } + /* Disable the selected FMC_Bank5_6 interrupt */ + else + { + /* Disables the interrupt if the refresh error flag is not set */ + FMC_Bank5_6->SDRTR &= (uint32_t)~FMC_IT; + } + } +} + +/** + * @brief Checks whether the specified FMC flag is set or not. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD + * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM + * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM + * @arg FMC_Bank1_SDRAM | FMC_Bank2_SDRAM: FMC Bank1 or Bank2 SDRAM + * @param FMC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag. + * @arg FMC_FLAG_Level: Level detection Flag. + * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag. + * @arg FMC_FLAG_FEMPT: Fifo empty Flag. + * @arg FMC_FLAG_Refresh: Refresh error Flag. + * @arg FMC_FLAG_Busy: Busy status Flag. + * @retval The new state of FMC_FLAG (SET or RESET). + */ +FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank)); + assert_param(IS_FMC_GET_FLAG(FMC_FLAG)); + + if(FMC_Bank == FMC_Bank2_NAND) + { + tmpsr = FMC_Bank2->SR2; + } + else if(FMC_Bank == FMC_Bank3_NAND) + { + tmpsr = FMC_Bank3->SR3; + } + else if(FMC_Bank == FMC_Bank4_PCCARD) + { + tmpsr = FMC_Bank4->SR4; + } + else + { + tmpsr = FMC_Bank5_6->SDSR; + } + + /* Get the flag status */ + if ((tmpsr & FMC_FLAG) != FMC_FLAG ) + { + bitstatus = RESET; + } + else + { + bitstatus = SET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the FMC's pending flags. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD + * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM + * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM + * @param FMC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag. + * @arg FMC_FLAG_Level: Level detection Flag. + * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag. + * @arg FMC_FLAG_Refresh: Refresh error Flag. + * @retval None + */ +void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank)); + assert_param(IS_FMC_CLEAR_FLAG(FMC_FLAG)) ; + + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->SR2 &= (~FMC_FLAG); + } + else if(FMC_Bank == FMC_Bank3_NAND) + { + FMC_Bank3->SR3 &= (~FMC_FLAG); + } + else if(FMC_Bank == FMC_Bank4_PCCARD) + { + FMC_Bank4->SR4 &= (~FMC_FLAG); + } + /* FMC_Bank5_6 SDRAM*/ + else + { + FMC_Bank5_6->SDRTR &= (~FMC_FLAG); + } + +} + +/** + * @brief Checks whether the specified FMC interrupt has occurred or not. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD + * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM + * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM + * @param FMC_IT: specifies the FMC interrupt source to check. + * This parameter can be one of the following values: + * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FMC_IT_Level: Level edge detection interrupt. + * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. + * @arg FMC_IT_Refresh: Refresh error detection interrupt. + * @retval The new state of FMC_IT (SET or RESET). + */ +ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0; + uint32_t tmpsr2 = 0x0; + uint32_t itstatus = 0x0; + uint32_t itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FMC_IT_BANK(FMC_Bank)); + assert_param(IS_FMC_GET_IT(FMC_IT)); + + if(FMC_Bank == FMC_Bank2_NAND) + { + tmpsr = FMC_Bank2->SR2; + } + else if(FMC_Bank == FMC_Bank3_NAND) + { + tmpsr = FMC_Bank3->SR3; + } + else if(FMC_Bank == FMC_Bank4_PCCARD) + { + tmpsr = FMC_Bank4->SR4; + } + /* FMC_Bank5_6 SDRAM*/ + else + { + tmpsr = FMC_Bank5_6->SDRTR; + tmpsr2 = FMC_Bank5_6->SDSR; + } + + /* get the IT enable bit status*/ + itenable = tmpsr & FMC_IT; + + /* get the corresponding IT Flag status*/ + if((FMC_Bank == FMC_Bank1_SDRAM) || (FMC_Bank == FMC_Bank2_SDRAM)) + { + itstatus = tmpsr2 & FMC_SDSR_RE; + } + else + { + itstatus = tmpsr & (FMC_IT >> 3); + } + + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the FMC's interrupt pending bits. + * @param FMC_Bank: specifies the FMC Bank to be used + * This parameter can be one of the following values: + * @arg FMC_Bank2_NAND: FMC Bank2 NAND + * @arg FMC_Bank3_NAND: FMC Bank3 NAND + * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD + * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM + * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM + * @param FMC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FMC_IT_Level: Level edge detection interrupt. + * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. + * @arg FMC_IT_Refresh: Refresh error detection interrupt. + * @retval None + */ +void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FMC_IT_BANK(FMC_Bank)); + assert_param(IS_FMC_IT(FMC_IT)); + + if(FMC_Bank == FMC_Bank2_NAND) + { + FMC_Bank2->SR2 &= ~(FMC_IT >> 3); + } + else if(FMC_Bank == FMC_Bank3_NAND) + { + FMC_Bank3->SR3 &= ~(FMC_IT >> 3); + } + else if(FMC_Bank == FMC_Bank4_PCCARD) + { + FMC_Bank4->SR4 &= ~(FMC_IT >> 3); + } + /* FMC_Bank5_6 SDRAM*/ + else + { + FMC_Bank5_6->SDRTR |= FMC_SDRTR_CRE; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c deleted file mode 100644 index c9780a5762..0000000000 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c +++ /dev/null @@ -1,982 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_fsmc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the FSMC peripheral: - * - Interface with SRAM, PSRAM, NOR and OneNAND memories - * - Interface with NAND memories - * - Interface with 16-bit PC Card compatible memories - * - Interrupts and flags management - * - ****************************************************************************** - - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

    © COPYRIGHT 2011 STMicroelectronics

    - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_fsmc.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FSMC - * @brief FSMC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* --------------------- FSMC registers bit mask ---------------------------- */ -/* FSMC BCRx Mask */ -#define BCR_MBKEN_SET ((uint32_t)0x00000001) -#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_SET ((uint32_t)0x00000040) - -/* FSMC PCRx Mask */ -#define PCR_PBKEN_SET ((uint32_t)0x00000004) -#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_SET ((uint32_t)0x00000040) -#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) -#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FSMC_Private_Functions - * @{ - */ - -/** @defgroup FSMC_Group1 NOR/SRAM Controller functions - * @brief NOR/SRAM Controller functions - * -@verbatim - =============================================================================== - NOR/SRAM Controller functions - =============================================================================== - - The following sequence should be followed to configure the FSMC to interface with - SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: - - 1. Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - 2. FSMC pins configuration - - Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - - Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - 3. Declare a FSMC_NORSRAMInitTypeDef structure, for example: - FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; - and fill the FSMC_NORSRAMInitStructure variable with the allowed values of - the structure member. - - 4. Initialize the NOR/SRAM Controller by calling the function - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - 5. Then enable the NOR/SRAM Bank, for example: - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); - - 6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default - * reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @retval None - */ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - - /* FSMC_Bank1_NORSRAM1 */ - if(FSMC_Bank == FSMC_Bank1_NORSRAM1) - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; - } - /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ - else - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; - } - FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; - FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. - * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure - * that contains the configuration information for the FSMC NOR/SRAM - * specified Banks. - * @retval None - */ -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); - assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); - assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); - assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); - assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); - assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); - assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); - assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); - - /* Bank1 NOR/SRAM control register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | - FSMC_NORSRAMInitStruct->FSMC_MemoryType | - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | - FSMC_NORSRAMInitStruct->FSMC_WrapMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | - FSMC_NORSRAMInitStruct->FSMC_WriteOperation | - FSMC_NORSRAMInitStruct->FSMC_WaitSignal | - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | - FSMC_NORSRAMInitStruct->FSMC_WriteBurst; - if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) - { - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET; - } - /* Bank1 NOR/SRAM timing register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; - - - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ - if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) - { - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; - } - else - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; - } -} - -/** - * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. - * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; - FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FSMC_Group2 NAND Controller functions - * @brief NAND Controller functions - * -@verbatim - =============================================================================== - NAND Controller functions - =============================================================================== - - The following sequence should be followed to configure the FSMC to interface with - 8-bit or 16-bit NAND memory connected to the NAND Bank: - - 1. Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - 2. FSMC pins configuration - - Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - - Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - 3. Declare a FSMC_NANDInitTypeDef structure, for example: - FSMC_NANDInitTypeDef FSMC_NANDInitStructure; - and fill the FSMC_NANDInitStructure variable with the allowed values of - the structure member. - - 4. Initialize the NAND Controller by calling the function - FSMC_NANDInit(&FSMC_NANDInitStructure); - - 5. Then enable the NAND Bank, for example: - FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE); - - 6. At this stage you can read/write from/to the memory connected to the NAND Bank. - -@note To enable the Error Correction Code (ECC), you have to use the function - FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE); - and to get the current ECC value you have to use the function - ECCval = FSMC_GetECC(FSMC_Bank3_NAND); - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval None - */ -void FSMC_NANDDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Set the FSMC_Bank2 registers to their reset values */ - FSMC_Bank2->PCR2 = 0x00000018; - FSMC_Bank2->SR2 = 0x00000040; - FSMC_Bank2->PMEM2 = 0xFCFCFCFC; - FSMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FSMC_Bank3_NAND */ - else - { - /* Set the FSMC_Bank3 registers to their reset values */ - FSMC_Bank3->PCR3 = 0x00000018; - FSMC_Bank3->SR3 = 0x00000040; - FSMC_Bank3->PMEM3 = 0xFCFCFCFC; - FSMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Initializes the FSMC NAND Banks according to the specified parameters - * in the FSMC_NANDInitStruct. - * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that - * contains the configuration information for the FSMC NAND specified Banks. - * @retval None - */ -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); - assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); - assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); - assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); - assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); - assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); - assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ - tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | - PCR_MEMORYTYPE_NAND | - FSMC_NANDInitStruct->FSMC_MemoryDataWidth | - FSMC_NANDInitStruct->FSMC_ECC | - FSMC_NANDInitStruct->FSMC_ECCPageSize | - (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| - (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); - - /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ - tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ - tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* FSMC_Bank2_NAND registers configuration */ - FSMC_Bank2->PCR2 = tmppcr; - FSMC_Bank2->PMEM2 = tmppmem; - FSMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FSMC_Bank3_NAND registers configuration */ - FSMC_Bank3->PCR3 = tmppcr; - FSMC_Bank3->PMEM3 = tmppmem; - FSMC_Bank3->PATT3 = tmppatt; - } -} - - -/** - * @brief Fills each FSMC_NANDInitStruct member with its default value. - * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which - * will be initialized. - * @retval None - */ -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; - FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; - FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_PBKEN_SET; - } - else - { - FSMC_Bank3->PCR3 |= PCR_PBKEN_SET; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET; - } - else - { - FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET; - } - } -} -/** - * @brief Enables or disables the FSMC NAND ECC feature. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_ECCEN_SET; - } - else - { - FSMC_Bank3->PCR3 |= PCR_ECCEN_SET; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET; - } - else - { - FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FSMC_GetECC(uint32_t FSMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FSMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FSMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} -/** - * @} - */ - -/** @defgroup FSMC_Group3 PCCARD Controller functions - * @brief PCCARD Controller functions - * -@verbatim - =============================================================================== - PCCARD Controller functions - =============================================================================== - - The following sequence should be followed to configure the FSMC to interface with - 16-bit PC Card compatible memory connected to the PCCARD Bank: - - 1. Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - 2. FSMC pins configuration - - Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - - Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - 3. Declare a FSMC_PCCARDInitTypeDef structure, for example: - FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure; - and fill the FSMC_PCCARDInitStructure variable with the allowed values of - the structure member. - - 4. Initialize the PCCARD Controller by calling the function - FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); - - 5. Then enable the PCCARD Bank: - FSMC_PCCARDCmd(ENABLE); - - 6. At this stage you can read/write from/to the memory connected to the PCCARD Bank. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FSMC_PCCARDDeInit(void) -{ - /* Set the FSMC_Bank4 registers to their reset values */ - FSMC_Bank4->PCR4 = 0x00000018; - FSMC_Bank4->SR4 = 0x00000000; - FSMC_Bank4->PMEM4 = 0xFCFCFCFC; - FSMC_Bank4->PATT4 = 0xFCFCFCFC; - FSMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FSMC PCCARD Bank according to the specified parameters - * in the FSMC_PCCARDInitStruct. - * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure - * that contains the configuration information for the FSMC PCCARD Bank. - * @retval None - */ -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); - assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ - FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | - FSMC_MemoryDataWidth_16b | - (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | - (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); - - /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ - FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ - FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ - FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); -} - -/** - * @brief Fills each FSMC_PCCARDInitStruct member with its default value. - * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 |= PCR_PBKEN_SET; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FSMC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FSMC interrupts. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @param NewState: new state of the specified FSMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) -{ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 |= FSMC_IT; - } - } - else - { - /* Disable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - - FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FSMC flag is set or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. - * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. - * @retval The new state of FSMC_FLAG (SET or RESET). - */ -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - /* Get the flag status */ - if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FSMC's pending flags. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. - * @retval None - */ -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~FSMC_FLAG; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~FSMC_FLAG; - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~FSMC_FLAG; - } -} - -/** - * @brief Checks whether the specified FSMC interrupt has occurred or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval The new state of FSMC_IT (SET or RESET). - */ -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - itstatus = tmpsr & FSMC_IT; - - itenable = tmpsr & (FSMC_IT >> 3); - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FSMC's interrupt pending bits. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval None - */ -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c index 8e16716195..1706fd3092 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c @@ -2,76 +2,81 @@ ****************************************************************************** * @file stm32f4xx_gpio.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the GPIO peripheral: - * - Initialization and Configuration - * - GPIO Read and Write - * - GPIO Alternate functions configuration + * + Initialization and Configuration + * + GPIO Read and Write + * + GPIO Alternate functions configuration * - * @verbatim +@verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + (#) Configure the GPIO pin(s) using GPIO_Init() + Four possible configuration are available for each pin: + (++) Input: Floating, Pull-up, Pull-down. + (++) Output: Push-Pull (Pull-up, Pull-down or no Pull) + Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed + is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz. + (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open + Drain (Pull-up, Pull-down or no Pull). + (++) Analog: required mode when a pin is to be used as ADC channel or DAC + output. + + (#) Peripherals alternate function: + (++) For ADC and DAC, configure the desired pin in analog mode using + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; + (+++) For other peripherals (TIM, USART...): + (+++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function + (+++) Configure the desired pin in alternate function mode using + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (+++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (+++) Call GPIO_Init() function + + (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() + + (#) To set/reset the level of a pin configured in output mode use + GPIO_SetBits()/GPIO_ResetBits() + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + +@endverbatim * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable the GPIO AHB clock using the following function - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - * 2. Configure the GPIO pin(s) using GPIO_Init() - * Four possible configuration are available for each pin: - * - Input: Floating, Pull-up, Pull-down. - * - Output: Push-Pull (Pull-up, Pull-down or no Pull) - * Open Drain (Pull-up, Pull-down or no Pull). - * In output mode, the speed is configurable: 2 MHz, 25 MHz, - * 50 MHz or 100 MHz. - * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) - * Open Drain (Pull-up, Pull-down or no Pull). - * - Analog: required mode when a pin is to be used as ADC channel - * or DAC output. - * - * 3- Peripherals alternate function: - * - For ADC and DAC, configure the desired pin in analog mode using - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; - * - For other peripherals (TIM, USART...): - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function mode using - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() - * - * 5. To set/reset the level of a pin configured in output mode use - * GPIO_SetBits()/GPIO_ResetBits() - * - * 6. During and just after reset, the alternate functions are not - * active and the GPIO pins are configured in input floating mode - * (except JTAG pins). + ****************************************************************************** + * @attention * - * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as - * general-purpose (PC14 and PC15, respectively) when the LSE - * oscillator is off. The LSE has priority over the GPIO function. + *

    © COPYRIGHT 2013 STMicroelectronics

    * - * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as - * general-purpose PH0 and PH1, respectively, when the HSE - * oscillator is off. The HSE has priority over the GPIO function. - * - * @endverbatim + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -104,7 +109,7 @@ * @verbatim =============================================================================== - Initialization and Configuration + ##### Initialization and Configuration ##### =============================================================================== @endverbatim @@ -112,9 +117,11 @@ */ /** - * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @brief De-initializes the GPIOx peripheral registers to their default reset values. * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @retval None */ void GPIO_DeInit(GPIO_TypeDef* GPIOx) @@ -162,19 +169,32 @@ void GPIO_DeInit(GPIO_TypeDef* GPIOx) RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); } + + else if (GPIOx == GPIOI) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); + } + else if (GPIOx == GPIOJ) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE); + } else { - if (GPIOx == GPIOI) + if (GPIOx == GPIOK) { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE); } } } /** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None @@ -189,7 +209,7 @@ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); - /* -------------------------Configure the port pins---------------- */ + /* ------------------------- Configure the port pins ---------------- */ /*-- GPIO Mode Configuration --*/ for (pinpos = 0x00; pinpos < 0x10; pinpos++) { @@ -247,7 +267,9 @@ void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: specifies the port bit to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None @@ -282,7 +304,7 @@ void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * @verbatim =============================================================================== - GPIO Read and Write + ##### GPIO Read and Write ##### =============================================================================== @endverbatim @@ -291,7 +313,9 @@ void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_Pin_x where x can be (0..15). * @retval The input port pin value. @@ -317,7 +341,9 @@ uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @retval GPIO input data port value. */ uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) @@ -330,7 +356,9 @@ uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) /** * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_Pin_x where x can be (0..15). * @retval The output port pin value. @@ -343,7 +371,7 @@ uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET) { bitstatus = (uint8_t)Bit_SET; } @@ -356,7 +384,9 @@ uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @retval GPIO output data port value. */ uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) @@ -372,7 +402,9 @@ uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) * @note This functions uses GPIOx_BSRR register to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: specifies the port bits to be written. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None @@ -391,7 +423,9 @@ void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * @note This functions uses GPIOx_BSRR register to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: specifies the port bits to be written. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None @@ -407,7 +441,9 @@ void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_Pin_x where x can be (0..15). * @param BitVal: specifies the value to be written to the selected bit. @@ -435,7 +471,9 @@ void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) /** * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param PortVal: specifies the value to be written to the port output data register. * @retval None */ @@ -449,7 +487,9 @@ void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) /** * @brief Toggles the specified GPIO pins.. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ @@ -470,7 +510,7 @@ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * @verbatim =============================================================================== - GPIO Alternate functions configuration function + ##### GPIO Alternate functions configuration function ##### =============================================================================== @endverbatim @@ -479,7 +519,9 @@ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief Changes the mapping of the specified pin. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices + * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. + * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_PinSource: specifies the pin for the Alternate function. * This parameter can be GPIO_PinSourcex where x can be (0..15). * @param GPIO_AFSelection: selects the pin to used as Alternate function. @@ -503,6 +545,10 @@ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 + * @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5 + * @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5 + * @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5 + * @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices. * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7 * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 @@ -511,6 +557,8 @@ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 + * @arg GPIO_AF_UART7: Connect UART7 pins to AF8 + * @arg GPIO_AF_UART8: Connect UART8 pins to AF8 * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 @@ -519,10 +567,12 @@ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 - * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 + * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 + * @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices. * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 + * @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices. * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 * @retval None */ @@ -558,4 +608,4 @@ void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c index d4fe401d71..8006174d8a 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hash.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the HASH / HMAC Processor (HASH) peripheral: * - Initialization and Configuration functions @@ -12,110 +12,110 @@ * - DMA interface function * - Interrupts and flags management * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * HASH operation : - * ---------------- - * 1. Enable the HASH controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function. - * - * 2. Initialise the HASH using HASH_Init() function. - * - * 3 . Reset the HASH processor core, so that the HASH will be ready - * to compute he message digest of a new message by using - * HASH_Reset() function. - * - * 4. Enable the HASH controller using the HASH_Cmd() function. - * - * 5. if using DMA for Data input transfer, Activate the DMA Request - * using HASH_DMACmd() function - * - * 6. if DMA is not used for data transfer, use HASH_DataIn() function - * to enter data to IN FIFO. - * - * - * 7. Configure the Number of valid bits in last word of the message - * using HASH_SetLastWordValidBitsNbr() function. - * - * 8. if the message length is not an exact multiple of 512 bits, - * then the function HASH_StartDigest() must be called to - * launch the computation of the final digest. - * - * 9. Once computed, the digest can be read using HASH_GetDigest() - * function. - * - * 10. To control HASH events you can use one of the following - * two methods: - * a- Check on HASH flags using the HASH_GetFlagStatus() function. - * b- Use HASH interrupts through the function HASH_ITConfig() at - * initialization phase and HASH_GetITStatus() function into - * interrupt routines in hashing phase. - * After checking on a flag you should clear it using HASH_ClearFlag() - * function. And after checking on an interrupt event you should - * clear it using HASH_ClearITPendingBit() function. - * - * 11. Save and restore hash processor context using - * HASH_SaveContext() and HASH_RestoreContext() functions. - * - * - * - * HMAC operation : - * ---------------- - * The HMAC algorithm is used for message authentication, by - * irreversibly binding the message being processed to a key chosen - * by the user. - * For HMAC specifications, refer to "HMAC: keyed-hashing for message - * authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997" - * - * Basically, the HMAC algorithm consists of two nested hash operations: - * HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)] - * where: - * - "pad" is a sequence of zeroes needed to extend the key to the - * length of the underlying hash function data block (that is - * 512 bits for both the SHA-1 and MD5 hash algorithms) - * - "|" represents the concatenation operator - * - * - * To compute the HMAC, four different phases are required: - * - * 1. Initialise the HASH using HASH_Init() function to do HMAC - * operation. - * - * 2. The key (to be used for the inner hash function) is then given - * to the core. This operation follows the same mechanism as the - * one used to send the message in the hash operation (that is, - * by HASH_DataIn() function and, finally, - * HASH_StartDigest() function. - * - * 3. Once the last word has been entered and computation has started, - * the hash processor elaborates the key. It is then ready to - * accept the message text using the same mechanism as the one - * used to send the message in the hash operation. - * - * 4. After the first hash round, the hash processor returns "ready" - * to indicate that it is ready to receive the key to be used for - * the outer hash function (normally, this key is the same as the - * one used for the inner hash function). When the last word of - * the key is entered and computation starts, the HMAC result is - * made available using HASH_GetDigest() function. - * - * - * @endverbatim +@verbatim + =================================================================== + ##### How to use this driver ##### + =================================================================== + + *** HASH operation : *** + ======================== + [..] + (#) Enable the HASH controller clock using + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function. + + (#) Initialise the HASH using HASH_Init() function. + + (#) Reset the HASH processor core, so that the HASH will be ready + to compute he message digest of a new message by using HASH_Reset() function. + + (#) Enable the HASH controller using the HASH_Cmd() function. + + (#) if using DMA for Data input transfer, Activate the DMA Request + using HASH_DMACmd() function + + (#) if DMA is not used for data transfer, use HASH_DataIn() function + to enter data to IN FIFO. + + + (#) Configure the Number of valid bits in last word of the message + using HASH_SetLastWordValidBitsNbr() function. + + (#) if the message length is not an exact multiple of 512 bits, + then the function HASH_StartDigest() must be called to launch the computation + of the final digest. + + (#) Once computed, the digest can be read using HASH_GetDigest() function. + + (#) To control HASH events you can use one of the following wo methods: + (++) Check on HASH flags using the HASH_GetFlagStatus() function. + (++) Use HASH interrupts through the function HASH_ITConfig() at + initialization phase and HASH_GetITStatus() function into + interrupt routines in hashing phase. + After checking on a flag you should clear it using HASH_ClearFlag() + function. And after checking on an interrupt event you should + clear it using HASH_ClearITPendingBit() function. + + (#) Save and restore hash processor context using + HASH_SaveContext() and HASH_RestoreContext() functions. + + + + *** HMAC operation : *** + ======================== + [..] The HMAC algorithm is used for message authentication, by + irreversibly binding the message being processed to a key chosen + by the user. + For HMAC specifications, refer to "HMAC: keyed-hashing for message + authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997" + + [..] Basically, the HMAC algorithm consists of two nested hash operations: + HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)] + where: + (+) "pad" is a sequence of zeroes needed to extend the key to the + length of the underlying hash function data block (that is + 512 bits for both the SHA-1 and MD5 hash algorithms) + (+) "|" represents the concatenation operator + + + [..]To compute the HMAC, four different phases are required: + (#) Initialise the HASH using HASH_Init() function to do HMAC + operation. + + (#) The key (to be used for the inner hash function) is then given to the core. + This operation follows the same mechanism as the one used to send the + message in the hash operation (that is, by HASH_DataIn() function and, + finally, HASH_StartDigest() function. + + (#) Once the last word has been entered and computation has started, + the hash processor elaborates the key. It is then ready to accept the message + text using the same mechanism as the one used to send the message in the + hash operation. + + (#) After the first hash round, the hash processor returns "ready" to indicate + that it is ready to receive the key to be used for the outer hash function + (normally, this key is the same as the one used for the inner hash function). + When the last word of the key is entered and computation starts, the HMAC + result is made available using HASH_GetDigest() function. + +@endverbatim * ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -148,23 +148,23 @@ * @verbatim =============================================================================== - Initialization and Configuration functions + ##### Initialization and Configuration functions ##### =============================================================================== - This section provides functions allowing to - - Initialize the HASH peripheral - - Configure the HASH Processor - - MD5/SHA1, - - HASH/HMAC, - - datatype - - HMAC Key (if mode = HMAC) - - Reset the HASH Processor + [..] This section provides functions allowing to + (+) Initialize the HASH peripheral + (+) Configure the HASH Processor + (+) MD5/SHA1, + (+) HASH/HMAC, + (+) datatype + (+) HMAC Key (if mode = HMAC) + (+) Reset the HASH Processor @endverbatim * @{ */ /** - * @brief Deinitializes the HASH peripheral registers to their default reset values + * @brief De-initializes the HASH peripheral registers to their default reset values * @param None * @retval None */ @@ -260,14 +260,14 @@ void HASH_Reset(void) * @verbatim =============================================================================== - Message Digest generation functions + ##### Message Digest generation functions ##### =============================================================================== - This section provides functions allowing the generation of message digest: - - Push data in the IN FIFO : using HASH_DataIn() - - Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() - - set the last word valid bits number using HASH_SetLastWordValidBitsNbr() - - start digest calculation : using HASH_StartDigest() - - Get the Digest message : using HASH_GetDigest() + [..] This section provides functions allowing the generation of message digest: + (+) Push data in the IN FIFO : using HASH_DataIn() + (+) Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() + (+) set the last word valid bits number using HASH_SetLastWordValidBitsNbr() + (+) start digest calculation : using HASH_StartDigest() + (+) Get the Digest message : using HASH_GetDigest() @endverbatim * @{ @@ -322,7 +322,11 @@ uint8_t HASH_GetInFIFOWordsNbr(void) /** * @brief Provides the message digest result. - * @note In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used + * @note In MD5 mode, Data[7] to Data[4] filed of HASH_MsgDigest structure is not used + * and is read as zero. + * In SHA-1 mode, Data[7] to Data[5] filed of HASH_MsgDigest structure is not used + * and is read as zero. + * In SHA-224 mode, Data[7] filed of HASH_MsgDigest structure is not used * and is read as zero. * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will * hold the message digest result @@ -336,6 +340,9 @@ void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest) HASH_MessageDigest->Data[2] = HASH->HR[2]; HASH_MessageDigest->Data[3] = HASH->HR[3]; HASH_MessageDigest->Data[4] = HASH->HR[4]; + HASH_MessageDigest->Data[5] = HASH_DIGEST->HR[5]; + HASH_MessageDigest->Data[6] = HASH_DIGEST->HR[6]; + HASH_MessageDigest->Data[7] = HASH_DIGEST->HR[7]; } /** @@ -357,19 +364,19 @@ void HASH_StartDigest(void) * @verbatim =============================================================================== - Context swapping functions + ##### Context swapping functions ##### =============================================================================== - - This section provides functions allowing to save and store HASH Context + + [..] This section provides functions allowing to save and store HASH Context - It is possible to interrupt a HASH/HMAC process to perform another processing - with a higher priority, and to complete the interrupted process later on, when - the higher priority task is complete. To do so, the context of the interrupted - task must be saved from the HASH registers to memory, and then be restored - from memory to the HASH registers. + [..] It is possible to interrupt a HASH/HMAC process to perform another processing + with a higher priority, and to complete the interrupted process later on, when + the higher priority task is complete. To do so, the context of the interrupted + task must be saved from the HASH registers to memory, and then be restored + from memory to the HASH registers. - 1. To save the current context, use HASH_SaveContext() function - 2. To restore the saved context, use HASH_RestoreContext() function + (#) To save the current context, use HASH_SaveContext() function + (#) To restore the saved context, use HASH_RestoreContext() function @endverbatim @@ -394,7 +401,7 @@ void HASH_SaveContext(HASH_Context* HASH_ContextSave) HASH_ContextSave->HASH_IMR = HASH->IMR; HASH_ContextSave->HASH_STR = HASH->STR; HASH_ContextSave->HASH_CR = HASH->CR; - for(i=0; i<=50;i++) + for(i=0; i<=53;i++) { HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i]; } @@ -421,7 +428,7 @@ void HASH_RestoreContext(HASH_Context* HASH_ContextRestore) HASH->CR |= HASH_CR_INIT; /* continue restoring context registers */ - for(i=0; i<=50;i++) + for(i=0; i<=53;i++) { HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i]; } @@ -435,20 +442,42 @@ void HASH_RestoreContext(HASH_Context* HASH_ContextRestore) * @verbatim =============================================================================== - HASH's DMA interface Configuration function + ##### HASH's DMA interface Configuration function ##### =============================================================================== - This section provides functions allowing to configure the DMA interface for - HASH/ HMAC data input transfer. + [..] This section provides functions allowing to configure the DMA interface for + HASH/ HMAC data input transfer. - When the DMA mode is enabled (using the HASH_DMACmd() function), data can be - sent to the IN FIFO using the DMA peripheral. - - + [..] When the DMA mode is enabled (using the HASH_DMACmd() function), data can be + sent to the IN FIFO using the DMA peripheral. @endverbatim * @{ */ + +/** + * @brief Enables or disables auto-start message padding and + * calculation of the final message digest at the end of DMA transfer. + * @param NewState: new state of the selected HASH DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void HASH_AutoStartDigest(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the auto start of the final message digest at the end of DMA transfer */ + HASH->CR &= ~HASH_CR_MDMAT; + } + else + { + /* Disable the auto start of the final message digest at the end of DMA transfer */ + HASH->CR |= HASH_CR_MDMAT; + } +} /** * @brief Enables or disables the HASH DMA interface. @@ -482,61 +511,58 @@ void HASH_DMACmd(FunctionalState NewState) * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== - This section provides functions allowing to configure the HASH Interrupts and - to get the status and clear flags and Interrupts pending bits. + [..] This section provides functions allowing to configure the HASH Interrupts and + to get the status and clear flags and Interrupts pending bits. - The HASH provides 2 Interrupts sources and 5 Flags: + [..] The HASH provides 2 Interrupts sources and 5 Flags: - Flags : - ---------- - 1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO - which means that a new block (512 bit) can be entered - into the input buffer. + *** Flags : *** + =============== + [..] + (#) HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO + which means that a new block (512 bit) can be entered into the input buffer. - 2. HASH_FLAG_DCIS : set when Digest calculation is complete + (#) HASH_FLAG_DCIS : set when Digest calculation is complete - 3. HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or - a transfer is ongoing. - This Flag is cleared only by hardware. + (#) HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or + a transfer is ongoing. This Flag is cleared only by hardware. - 4. HASH_FLAG_BUSY : set when The hash core is processing a block of data - This Flag is cleared only by hardware. + (#) HASH_FLAG_BUSY : set when The hash core is processing a block of data + This Flag is cleared only by hardware. - 5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that - the Data IN FIFO contains at least one word of data. - This Flag is cleared only by hardware. + (#) HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that + the Data IN FIFO contains at least one word of data. This Flag is cleared + only by hardware. - Interrupts : - ------------ - - 1. HASH_IT_DINI : if enabled, this interrupt source is pending when 16 - locations are free in the Data IN FIFO which means that - a new block (512 bit) can be entered into the input buffer. - This interrupt source is cleared using - HASH_ClearITPendingBit(HASH_IT_DINI) function. + *** Interrupts : *** + ==================== + [..] + (#) HASH_IT_DINI : if enabled, this interrupt source is pending when 16 + locations are free in the Data IN FIFO which means that a new block (512 bit) + can be entered into the input buffer. This interrupt source is cleared using + HASH_ClearITPendingBit(HASH_IT_DINI) function. - 2. HASH_IT_DCI : if enabled, this interrupt source is pending when Digest - calculation is complete. - This interrupt source is cleared using - HASH_ClearITPendingBit(HASH_IT_DCI) function. - - Managing the HASH controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the HASH controller events: Polling mode or Interrupt mode. + (#) HASH_IT_DCI : if enabled, this interrupt source is pending when Digest + calculation is complete. This interrupt source is cleared using + HASH_ClearITPendingBit(HASH_IT_DCI) function. + + *** Managing the HASH controller events : *** + ============================================= + [..] The user should identify which mode will be used in his application to manage + the HASH controller events: Polling mode or Interrupt mode. - 1. In the Polling Mode it is advised to use the following functions: - - HASH_GetFlagStatus() : to check if flags events occur. - - HASH_ClearFlag() : to clear the flags events. + (#) In the Polling Mode it is advised to use the following functions: + (++) HASH_GetFlagStatus() : to check if flags events occur. + (++) HASH_ClearFlag() : to clear the flags events. - 2. In the Interrupt Mode it is advised to use the following functions: - - HASH_ITConfig() : to enable or disable the interrupt source. - - HASH_GetITStatus() : to check if Interrupt occurs. - - HASH_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). + (#) In the Interrupt Mode it is advised to use the following functions: + (++) HASH_ITConfig() : to enable or disable the interrupt source. + (++) HASH_GetITStatus() : to check if Interrupt occurs. + (++) HASH_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). @endverbatim * @{ @@ -552,7 +578,7 @@ void HASH_DMACmd(FunctionalState NewState) * This parameter can be: ENABLE or DISABLE. * @retval None */ -void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState) +void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_HASH_IT(HASH_IT)); @@ -566,7 +592,7 @@ void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState) else { /* Disable the selected HASH interrupt */ - HASH->IMR &= (uint8_t) ~HASH_IT; + HASH->IMR &= (uint32_t)(~HASH_IT); } } @@ -581,7 +607,7 @@ void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState) * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag * @retval The new state of HASH_FLAG (SET or RESET) */ -FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG) +FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG) { FlagStatus bitstatus = RESET; uint32_t tempreg = 0; @@ -590,7 +616,7 @@ FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG) assert_param(IS_HASH_GET_FLAG(HASH_FLAG)); /* check if the FLAG is in CR register */ - if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET ) + if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint32_t)RESET ) { tempreg = HASH->CR; } @@ -600,7 +626,7 @@ FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG) } /* Check the status of the specified HASH flag */ - if ((tempreg & HASH_FLAG) != (uint16_t)RESET) + if ((tempreg & HASH_FLAG) != (uint32_t)RESET) { /* HASH is set */ bitstatus = SET; @@ -622,7 +648,7 @@ FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG) * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag * @retval None */ -void HASH_ClearFlag(uint16_t HASH_FLAG) +void HASH_ClearFlag(uint32_t HASH_FLAG) { /* Check the parameters */ assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG)); @@ -638,7 +664,7 @@ void HASH_ClearFlag(uint16_t HASH_FLAG) * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt * @retval The new state of HASH_IT (SET or RESET). */ -ITStatus HASH_GetITStatus(uint8_t HASH_IT) +ITStatus HASH_GetITStatus(uint32_t HASH_IT) { ITStatus bitstatus = RESET; uint32_t tmpreg = 0; @@ -672,13 +698,13 @@ ITStatus HASH_GetITStatus(uint8_t HASH_IT) * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt * @retval None */ -void HASH_ClearITPendingBit(uint8_t HASH_IT) +void HASH_ClearITPendingBit(uint32_t HASH_IT) { /* Check the parameters */ assert_param(IS_HASH_IT(HASH_IT)); /* Clear the selected HASH interrupt pending bit */ - HASH->SR = (uint8_t)~HASH_IT; + HASH->SR = (uint32_t)(~HASH_IT); } /** @@ -697,4 +723,4 @@ void HASH_ClearITPendingBit(uint8_t HASH_IT) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c index 56d495fd61..b2a91d2246 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c @@ -2,38 +2,44 @@ ****************************************************************************** * @file stm32f4xx_hash_md5.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides high level functions to compute the HASH MD5 and * HMAC MD5 Digest of an input message. * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH * peripheral. * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The HASH controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. +@verbatim + =================================================================== + ##### How to use this driver ##### + =================================================================== + [..] + (#) Enable The HASH controller clock using + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. + + (#) Calculate the HASH MD5 Digest using HASH_MD5() function. + + (#) Calculate the HMAC MD5 Digest using HMAC_MD5() function. + +@endverbatim * - * 2. Calculate the HASH MD5 Digest using HASH_MD5() function. + ****************************************************************************** + * @attention * - * 3. Calculate the HMAC MD5 Digest using HMAC_MD5() function. + *

    © COPYRIGHT 2013 STMicroelectronics

    * - * @endverbatim + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -67,7 +73,7 @@ * @verbatim =============================================================================== - High Level MD5 Hash and HMAC functions + ##### High Level MD5 Hash and HMAC functions ##### =============================================================================== @@ -310,5 +316,5 @@ ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, uint8_t *Input, * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c index 37fbfeb6da..f9b4e07cc8 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c @@ -2,38 +2,44 @@ ****************************************************************************** * @file stm32f4xx_hash_sha1.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides high level functions to compute the HASH SHA1 and * HMAC SHA1 Digest of an input message. * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH * peripheral. * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The HASH controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. +@verbatim + =================================================================== + ##### How to use this driver ##### + =================================================================== + [..] + (#) Enable The HASH controller clock using + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. + + (#) Calculate the HASH SHA1 Digest using HASH_SHA1() function. + + (#) Calculate the HMAC SHA1 Digest using HMAC_SHA1() function. + +@endverbatim * - * 2. Calculate the HASH SHA1 Digest using HASH_SHA1() function. + ****************************************************************************** + * @attention * - * 3. Calculate the HMAC SHA1 Digest using HMAC_SHA1() function. + *

    © COPYRIGHT 2013 STMicroelectronics

    * - * @endverbatim + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -67,7 +73,7 @@ * @verbatim =============================================================================== - High Level SHA1 Hash and HMAC functions + ##### High Level SHA1 Hash and HMAC functions ##### =============================================================================== @@ -314,4 +320,4 @@ ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, uint8_t *Input, * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c index 3dcd2ab3f4..f73188ccaa 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c @@ -2,84 +2,89 @@ ****************************************************************************** * @file stm32f4xx_i2c.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Inter-integrated circuit (I2C) - * - Initialization and Configuration - * - Data transfers - * - PEC management - * - DMA transfers management - * - Interrupts, events and flags management + * + Initialization and Configuration + * + Data transfers + * + PEC management + * + DMA transfers management + * + Interrupts, events and flags management * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE) - * function for I2C1, I2C2 or I2C3. - * - * 2. Enable SDA, SCL and SMBA (when used) GPIO clocks using - * RCC_AHBPeriphClockCmd() function. - * - * 3. Peripherals alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * Recommended configuration is Push-Pull, Pull-up, Open-Drain. - * Add an external pull up if necessary (typically 4.7 KOhm). - * - * 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged - * Address using the I2C_Init() function. - * - * 5. Optionally you can enable/configure the following parameters without - * re-initialization (i.e there is no need to call again I2C_Init() function): - * - Enable the acknowledge feature using I2C_AcknowledgeConfig() function - * - Enable the dual addressing mode using I2C_DualAddressCmd() function - * - Enable the general call using the I2C_GeneralCallCmd() function - * - Enable the clock stretching using I2C_StretchClockCmd() function - * - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() - * function. - * - Configure the NACK position for Master Receiver mode in case of - * 2 bytes reception using the function I2C_NACKPositionConfig(). - * - Enable the PEC Calculation using I2C_CalculatePEC() function - * - For SMBus Mode: - * - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function - * - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE) + function for I2C1, I2C2 or I2C3. + + (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using + RCC_AHBPeriphClockCmd() function. + + (#) Peripherals alternate function: + (++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (++) Call GPIO_Init() function + Recommended configuration is Push-Pull, Pull-up, Open-Drain. + Add an external pull up if necessary (typically 4.7 KOhm). + + (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged + Address using the I2C_Init() function. + + (#) Optionally you can enable/configure the following parameters without + re-initialization (i.e there is no need to call again I2C_Init() function): + (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function + (++) Enable the dual addressing mode using I2C_DualAddressCmd() function + (++) Enable the general call using the I2C_GeneralCallCmd() function + (++) Enable the clock stretching using I2C_StretchClockCmd() function + (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() + function. + (++) Configure the NACK position for Master Receiver mode in case of + 2 bytes reception using the function I2C_NACKPositionConfig(). + (++) Enable the PEC Calculation using I2C_CalculatePEC() function + (++) For SMBus Mode: + (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function + (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function + + (#) Enable the NVIC and the corresponding interrupt using the function + I2C_ITConfig() if you need to use interrupt mode. + + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function + (++) Active the needed channel Request using I2C_DMACmd() or + I2C_DMALastTransferCmd() function. + -@@- When using DMA mode, I2C interrupts may be used at the same time to + control the communication flow (Start/Stop/Ack... events and errors). + + (#) Enable the I2C using the I2C_Cmd() function. + + (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the + transfers. + + @endverbatim + ****************************************************************************** + * @attention * - * 6. Enable the NVIC and the corresponding interrupt using the function - * I2C_ITConfig() if you need to use interrupt mode. + *

    © COPYRIGHT 2013 STMicroelectronics

    * - * 7. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using I2C_DMACmd() or - * I2C_DMALastTransferCmd() function. - * @note When using DMA mode, I2C interrupts may be used at the same time to - * control the communication flow (Start/Stop/Ack... events and errors). - * - * 8. Enable the I2C using the I2C_Cmd() function. - * - * 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the - * transfers. + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - * @endverbatim - * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -117,7 +122,7 @@ * @verbatim =============================================================================== - Initialization and Configuration functions + ##### Initialization and Configuration functions ##### =============================================================================== @endverbatim @@ -322,6 +327,68 @@ void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) } } +/** + * @brief Enables or disables the Analog filter of I2C peripheral. + * + * @note This function can be used only for STM32F42xxx/STM3243xxx and STM32F401xx devices. + * + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the Analog filter. + * This parameter can be: ENABLE or DISABLE. + * @note This function should be called before initializing and enabling + the I2C Peripheral. + * @retval None + */ +void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the analog filter */ + I2Cx->FLTR &= (uint16_t)~((uint16_t)I2C_FLTR_ANOFF); + } + else + { + /* Disable the analog filter */ + I2Cx->FLTR |= I2C_FLTR_ANOFF; + } +} + +/** + * @brief Configures the Digital noise filter of I2C peripheral. + * + * @note This function can be used only for STM32F42xxx/STM3243xxx and STM32F401xx devices. + * + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_DigitalFilter: Coefficient of digital noise filter. + * This parameter can be a number between 0x00 and 0x0F. + * @note This function should be called before initializing and enabling + the I2C Peripheral. + * @retval None + */ +void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIGITAL_FILTER(I2C_DigitalFilter)); + + /* Get the old register value */ + tmpreg = I2Cx->FLTR; + + /* Reset I2Cx DNF bit [3:0] */ + tmpreg &= (uint16_t)~((uint16_t)I2C_FLTR_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= (uint16_t)((uint16_t)I2C_DigitalFilter & I2C_FLTR_DNF); + + /* Store the new register value */ + I2Cx->FLTR = tmpreg; +} + /** * @brief Generates I2Cx communication START condition. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. @@ -673,7 +740,7 @@ void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) * @verbatim =============================================================================== - Data transfers functions + ##### Data transfers functions ##### =============================================================================== @endverbatim @@ -716,7 +783,7 @@ uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) * @verbatim =============================================================================== - PEC management functions + ##### PEC management functions ##### =============================================================================== @endverbatim @@ -824,7 +891,7 @@ uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) * @verbatim =============================================================================== - DMA transfers management functions + ##### DMA transfers management functions ##### =============================================================================== This section provides functions allowing to configure the I2C DMA channels requests. @@ -890,94 +957,94 @@ void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) * @verbatim =============================================================================== - Interrupts, events and flags management functions - =============================================================================== - This section provides functions allowing to configure the I2C Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - + ##### Interrupts, events and flags management functions ##### =============================================================================== - I2C State Monitoring Functions - =============================================================================== - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: + [..] + This section provides functions allowing to configure the I2C Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + + ##### I2C State Monitoring Functions ##### + =============================================================================== + [..] + This I2C driver provides three different ways for I2C state monitoring + depending on the application requirements and constraints: - 1. Basic state monitoring (Using I2C_CheckEvent() function) - ----------------------------------------------------------- + (#) Basic state monitoring (Using I2C_CheckEvent() function) + It compares the status registers (SR1 and SR2) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status. - - When to use - - This function is suitable for most applications as well as for startup + (++) When to use + (+++) This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0090). - - It is also suitable for users who need to define their own events. + (+++) It is also suitable for users who need to define their own events. - - Limitations - - If an error occurs (ie. error flags are set besides to the monitored + (++) Limitations + If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler. - @note - For error management, it is advised to use the following functions: - - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. + -@@- For error management, it is advised to use the following functions: + (+@@) I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + Where x is the peripheral instance (I2C1, I2C2 ...) + (+@@) I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the + I2Cx_ER_IRQHandler() function in order to determine which error occurred. + (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + and/or I2C_GenerateStop() in order to clear the error flag and source + and return to correct communication status. - 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) - -------------------------------------------------------------------- + (#) Advanced state monitoring (Using the function I2C_GetLastEvent()) + Using the function I2C_GetLastEvent() which returns the image of both status registers in a single word (uint32_t) (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). - - When to use - - This function is suitable for the same applications above but it + (++) When to use + (+++) This function is suitable for the same applications above but it allows to overcome the mentioned limitation of I2C_GetFlagStatus() function. - - The returned value could be compared to events already defined in + (+++) The returned value could be compared to events already defined in the library (stm32f4xx_i2c.h) or to custom values defined by user. This function is suitable when multiple flags are monitored at the same time. - - At the opposite of I2C_CheckEvent() function, this function allows + (+++) At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function. - - Limitations - - User may need to define his own events. - - Same remark concerning the error management is applicable for this + (++) Limitations + (+++) User may need to define his own events. + (+++) Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags). - 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - ----------------------------------------------------------------------- + (#) Flag-based state monitoring (Using the function I2C_GetFlagStatus()) Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...). - - When to use - - This function could be used for specific applications or in debug + (++) When to use + (+++) This function could be used for specific applications or in debug phase. - - It is suitable when only one flag checking is needed (most I2C + (+++) It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags). - - Limitations: - - When calling this function, the Status register is accessed. + (++) Limitations: + (+++) When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones. - - Function may need to be called twice or more in order to monitor + (+++) Function may need to be called twice or more in order to monitor one single event. For detailed description of Events, please refer to section I2C_Events in @@ -1392,4 +1459,4 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c index a4fddec2aa..c4ce7159e2 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c @@ -2,79 +2,82 @@ ****************************************************************************** * @file stm32f4xx_iwdg.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Independent watchdog (IWDG) peripheral: - * - Prescaler and Counter configuration - * - IWDG activation - * - Flag management + * + Prescaler and Counter configuration + * + IWDG activation + * + Flag management * - * @verbatim - * - * =================================================================== - * IWDG features - * =================================================================== - * - * The IWDG can be started by either software or hardware (configurable - * through option byte). - * - * The IWDG is clocked by its own dedicated low-speed clock (LSI) and - * thus stays active even if the main clock fails. - * Once the IWDG is started, the LSI is forced ON and cannot be disabled - * (LSI cannot be disabled too), and the counter starts counting down from - * the reset value of 0xFFF. When it reaches the end of count value (0x000) - * a system reset is generated. - * The IWDG counter should be reloaded at regular intervals to prevent - * an MCU reset. - * - * The IWDG is implemented in the VDD voltage domain that is still functional - * in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - * - * IWDGRST flag in RCC_CSR register can be used to inform when a IWDG - * reset occurs. - * - * Min-max timeout value @32KHz (LSI): ~125us / ~32.7s - * The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx - * devices provide the capability to measure the LSI frequency (LSI clock - * connected internally to TIM5 CH4 input capture). The measured value - * can be used to have an IWDG timeout with an acceptable accuracy. - * For more information, please refer to the STM32F4xx Reference manual - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable write access to IWDG_PR and IWDG_RLR registers using - * IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function - * - * 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function - * - * 3. Configure the IWDG counter value using IWDG_SetReload() function. - * This value will be loaded in the IWDG counter each time the counter - * is reloaded, then the IWDG will start counting down from this value. - * - * 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used - * in software mode (no need to enable the LSI, it will be enabled - * by hardware) - * - * 5. Then the application program must reload the IWDG counter at regular - * intervals during normal operation to prevent an MCU reset, using - * IWDG_ReloadCounter() function. - * - * @endverbatim - * + @verbatim + =============================================================================== + ##### IWDG features ##### + =============================================================================== + [..] + The IWDG can be started by either software or hardware (configurable + through option byte). + + The IWDG is clocked by its own dedicated low-speed clock (LSI) and + thus stays active even if the main clock fails. + Once the IWDG is started, the LSI is forced ON and cannot be disabled + (LSI cannot be disabled too), and the counter starts counting down from + the reset value of 0xFFF. When it reaches the end of count value (0x000) + a system reset is generated. + The IWDG counter should be reloaded at regular intervals to prevent + an MCU reset. + + The IWDG is implemented in the VDD voltage domain that is still functional + in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + + IWDGRST flag in RCC_CSR register can be used to inform when a IWDG + reset occurs. + + Min-max timeout value @32KHz (LSI): ~125us / ~32.7s + The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx + devices provide the capability to measure the LSI frequency (LSI clock + connected internally to TIM5 CH4 input capture). The measured value + can be used to have an IWDG timeout with an acceptable accuracy. + For more information, please refer to the STM32F4xx Reference manual + + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable write access to IWDG_PR and IWDG_RLR registers using + IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function + + (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function + + (#) Configure the IWDG counter value using IWDG_SetReload() function. + This value will be loaded in the IWDG counter each time the counter + is reloaded, then the IWDG will start counting down from this value. + + (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used + in software mode (no need to enable the LSI, it will be enabled + by hardware) + + (#) Then the application program must reload the IWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + IWDG_ReloadCounter() function. + + @endverbatim ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -111,7 +114,7 @@ * @verbatim =============================================================================== - Prescaler and Counter configuration functions + ##### Prescaler and Counter configuration functions ##### =============================================================================== @endverbatim @@ -186,7 +189,7 @@ void IWDG_ReloadCounter(void) * @verbatim =============================================================================== - IWDG activation function + ##### IWDG activation function ##### =============================================================================== @endverbatim @@ -212,7 +215,7 @@ void IWDG_Enable(void) * @verbatim =============================================================================== - Flag management function + ##### Flag management function ##### =============================================================================== @endverbatim @@ -260,4 +263,4 @@ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c new file mode 100644 index 0000000000..56ab2dca05 --- /dev/null +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c @@ -0,0 +1,1104 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ltdc.c + * @author MCD Application Team + * @version V1.3.0 + * @date 08-November-2013 + * @brief This file provides firmware functions to manage the following + * functionalities of the LTDC controller (LTDC) peripheral: + * + Initialization and configuration + * + Interrupts and flags management + * + * @verbatim + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable LTDC clock using + RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, ENABLE) function. + (#) Configures LTDC + (++) Configure the required Pixel clock following the panel datasheet + (++) Configure the Synchronous timings: VSYNC, HSYNC, Vertical and + Horizontal back proch, active data area and the front proch + timings + (++) Configure the synchronous signals and clock polarity in the + LTDC_GCR register + (#) Configures Layer1/2 parameters + (++) The Layer window horizontal and vertical position in the LTDC_LxWHPCR and + LTDC_WVPCR registers. The layer window must be in the active data area. + (++) The pixel input format in the LTDC_LxPFCR register + (++) The color frame buffer start address in the LTDC_LxCFBAR register + (++) The line length and pitch of the color frame buffer in the + LTDC_LxCFBLR register + (++) The number of lines of the color frame buffer in + the LTDC_LxCFBLNR register + (++) if needed, load the CLUT with the RGB values and the address + in the LTDC_LxCLUTWR register + (++) If needed, configure the default color and the blending factors + respectively in the LTDC_LxDCCR and LTDC_LxBFCR registers + + (++) If needed, Dithering and color keying can be be enabled respectively + in the LTDC_GCR and LTDC_LxCKCR registers. It can be also enabled + on the fly. + (#) Enable Layer1/2 and if needed the CLUT in the LTDC_LxCR register + + (#) Reload the shadow registers to active register through + the LTDC_SRCR register. + -@- All layer parameters can be be modified on the fly except the CLUT. + The new configuration has to be either reloaded immediately + or during vertical blanking period by configuring the LTDC_SRCR register. + (#) Call the LTDC_Cmd() to enable the LTDC controller. + + @endverbatim + + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

    © COPYRIGHT 2013 STMicroelectronics

    + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_ltdc.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup LTDC + * @brief LTDC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +#define GCR_MASK ((uint32_t)0x0FFE888F) /* LTDC GCR Mask */ + + +/** @defgroup LTDC_Private_Functions + * @{ + */ + +/** @defgroup LTDC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + (+) Enable or Disable Dither + (+) Define the position of the line interrupt + (+) reload layers registers with new parameters + (+) Initialize and configure layer1 and layer2 + (+) Set and configure the color keying functionality + (+) Configure and Enables or disables CLUT + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the LTDC peripheral registers to their default reset + * values. + * @param None + * @retval None + */ + +void LTDC_DeInit(void) +{ + /* Enable LTDC reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, ENABLE); + /* Release LTDC from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, DISABLE); +} + +/** + * @brief Initializes the LTDC peripheral according to the specified parameters + * in the LTDC_InitStruct. + * @note This function can be used only when the LTDC is disabled. + * @param LTDC_InitStruct: pointer to a LTDC_InitTypeDef structure that contains + * the configuration information for the specified LTDC peripheral. + * @retval None + */ + +void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct) +{ + uint32_t horizontalsync = 0; + uint32_t accumulatedHBP = 0; + uint32_t accumulatedactiveW = 0; + uint32_t totalwidth = 0; + uint32_t backgreen = 0; + uint32_t backred = 0; + + /* Check function parameters */ + assert_param(IS_LTDC_HSYNC(LTDC_InitStruct->LTDC_HorizontalSync)); + assert_param(IS_LTDC_VSYNC(LTDC_InitStruct->LTDC_VerticalSync)); + assert_param(IS_LTDC_AHBP(LTDC_InitStruct->LTDC_AccumulatedHBP)); + assert_param(IS_LTDC_AVBP(LTDC_InitStruct->LTDC_AccumulatedVBP)); + assert_param(IS_LTDC_AAH(LTDC_InitStruct->LTDC_AccumulatedActiveH)); + assert_param(IS_LTDC_AAW(LTDC_InitStruct->LTDC_AccumulatedActiveW)); + assert_param(IS_LTDC_TOTALH(LTDC_InitStruct->LTDC_TotalHeigh)); + assert_param(IS_LTDC_TOTALW(LTDC_InitStruct->LTDC_TotalWidth)); + assert_param(IS_LTDC_HSPOL(LTDC_InitStruct->LTDC_HSPolarity)); + assert_param(IS_LTDC_VSPOL(LTDC_InitStruct->LTDC_VSPolarity)); + assert_param(IS_LTDC_DEPOL(LTDC_InitStruct->LTDC_DEPolarity)); + assert_param(IS_LTDC_PCPOL(LTDC_InitStruct->LTDC_PCPolarity)); + assert_param(IS_LTDC_BackBlueValue(LTDC_InitStruct->LTDC_BackgroundBlueValue)); + assert_param(IS_LTDC_BackGreenValue(LTDC_InitStruct->LTDC_BackgroundGreenValue)); + assert_param(IS_LTDC_BackRedValue(LTDC_InitStruct->LTDC_BackgroundRedValue)); + + /* Sets Synchronization size */ + LTDC->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); + horizontalsync = (LTDC_InitStruct->LTDC_HorizontalSync << 16); + LTDC->SSCR |= (horizontalsync | LTDC_InitStruct->LTDC_VerticalSync); + + /* Sets Accumulated Back porch */ + LTDC->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); + accumulatedHBP = (LTDC_InitStruct->LTDC_AccumulatedHBP << 16); + LTDC->BPCR |= (accumulatedHBP | LTDC_InitStruct->LTDC_AccumulatedVBP); + + /* Sets Accumulated Active Width */ + LTDC->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); + accumulatedactiveW = (LTDC_InitStruct->LTDC_AccumulatedActiveW << 16); + LTDC->AWCR |= (accumulatedactiveW | LTDC_InitStruct->LTDC_AccumulatedActiveH); + + /* Sets Total Width */ + LTDC->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); + totalwidth = (LTDC_InitStruct->LTDC_TotalWidth << 16); + LTDC->TWCR |= (totalwidth | LTDC_InitStruct->LTDC_TotalHeigh); + + LTDC->GCR &= (uint32_t)GCR_MASK; + LTDC->GCR |= (uint32_t)(LTDC_InitStruct->LTDC_HSPolarity | LTDC_InitStruct->LTDC_VSPolarity | \ + LTDC_InitStruct->LTDC_DEPolarity | LTDC_InitStruct->LTDC_PCPolarity); + + /* sets the background color value */ + backgreen = (LTDC_InitStruct->LTDC_BackgroundGreenValue << 8); + backred = (LTDC_InitStruct->LTDC_BackgroundRedValue << 16); + + LTDC->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); + LTDC->BCCR |= (backred | backgreen | LTDC_InitStruct->LTDC_BackgroundBlueValue); +} + +/** + * @brief Fills each LTDC_InitStruct member with its default value. + * @param LTDC_InitStruct: pointer to a LTDC_InitTypeDef structure which will + * be initialized. + * @retval None + */ + +void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct) +{ + /*--------------- Reset LTDC init structure parameters values ----------------*/ + LTDC_InitStruct->LTDC_HSPolarity = LTDC_HSPolarity_AL; /*!< Initialize the LTDC_HSPolarity member */ + LTDC_InitStruct->LTDC_VSPolarity = LTDC_VSPolarity_AL; /*!< Initialize the LTDC_VSPolarity member */ + LTDC_InitStruct->LTDC_DEPolarity = LTDC_DEPolarity_AL; /*!< Initialize the LTDC_DEPolarity member */ + LTDC_InitStruct->LTDC_PCPolarity = LTDC_PCPolarity_IPC; /*!< Initialize the LTDC_PCPolarity member */ + LTDC_InitStruct->LTDC_HorizontalSync = 0x00; /*!< Initialize the LTDC_HorizontalSync member */ + LTDC_InitStruct->LTDC_VerticalSync = 0x00; /*!< Initialize the LTDC_VerticalSync member */ + LTDC_InitStruct->LTDC_AccumulatedHBP = 0x00; /*!< Initialize the LTDC_AccumulatedHBP member */ + LTDC_InitStruct->LTDC_AccumulatedVBP = 0x00; /*!< Initialize the LTDC_AccumulatedVBP member */ + LTDC_InitStruct->LTDC_AccumulatedActiveW = 0x00; /*!< Initialize the LTDC_AccumulatedActiveW member */ + LTDC_InitStruct->LTDC_AccumulatedActiveH = 0x00; /*!< Initialize the LTDC_AccumulatedActiveH member */ + LTDC_InitStruct->LTDC_TotalWidth = 0x00; /*!< Initialize the LTDC_TotalWidth member */ + LTDC_InitStruct->LTDC_TotalHeigh = 0x00; /*!< Initialize the LTDC_TotalHeigh member */ + LTDC_InitStruct->LTDC_BackgroundRedValue = 0x00; /*!< Initialize the LTDC_BackgroundRedValue member */ + LTDC_InitStruct->LTDC_BackgroundGreenValue = 0x00; /*!< Initialize the LTDC_BackgroundGreenValue member */ + LTDC_InitStruct->LTDC_BackgroundBlueValue = 0x00; /*!< Initialize the LTDC_BackgroundBlueValue member */ +} + +/** + * @brief Enables or disables the LTDC Controller. + * @param NewState: new state of the LTDC peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void LTDC_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable LTDC by setting LTDCEN bit */ + LTDC->GCR |= (uint32_t)LTDC_GCR_LTDCEN; + } + else + { + /* Disable LTDC by clearing LTDCEN bit */ + LTDC->GCR &= ~(uint32_t)LTDC_GCR_LTDCEN; + } +} + +/** + * @brief Enables or disables Dither. + * @param NewState: new state of the Dither. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void LTDC_DitherCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Dither by setting DTEN bit */ + LTDC->GCR |= (uint32_t)LTDC_GCR_DTEN; + } + else + { + /* Disable Dither by clearing DTEN bit */ + LTDC->GCR &= ~(uint32_t)LTDC_GCR_DTEN; + } +} + +/** + * @brief Get the dither RGB width. + * @param LTDC_RGB_InitStruct: pointer to a LTDC_RGBTypeDef structure that contains + * the Dither RGB width. + * @retval None + */ + +LTDC_RGBTypeDef LTDC_GetRGBWidth(void) +{ + LTDC_RGBTypeDef LTDC_RGB_InitStruct; + + LTDC->GCR &= (uint32_t)GCR_MASK; + + LTDC_RGB_InitStruct.LTDC_BlueWidth = (uint32_t)((LTDC->GCR >> 4) & 0x7); + LTDC_RGB_InitStruct.LTDC_GreenWidth = (uint32_t)((LTDC->GCR >> 8) & 0x7); + LTDC_RGB_InitStruct.LTDC_RedWidth = (uint32_t)((LTDC->GCR >> 12) & 0x7); + + return LTDC_RGB_InitStruct; +} + +/** + * @brief Fills each LTDC_RGBStruct member with its default value. + * @param LTDC_RGB_InitStruct: pointer to a LTDC_RGBTypeDef structure which will + * be initialized. + * @retval None + */ + +void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct) +{ + LTDC_RGB_InitStruct->LTDC_BlueWidth = 0x02; + LTDC_RGB_InitStruct->LTDC_GreenWidth = 0x02; + LTDC_RGB_InitStruct->LTDC_RedWidth = 0x02; +} + + +/** + * @brief Define the position of the line interrupt . + * @param LTDC_LIPositionConfig: Line Interrupt Position. + * @retval None + */ + +void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LIPOS(LTDC_LIPositionConfig)); + + /* Sets the Line Interrupt position */ + LTDC->LIPCR = (uint32_t)LTDC_LIPositionConfig; +} + +/** + * @brief reload layers registers with new parameters + * @param LTDC_Reload: specifies the type of reload. + * This parameter can be one of the following values: + * @arg LTDC_IMReload: Vertical blanking reload. + * @arg LTDC_VBReload: Immediate reload. + * @retval None + */ + +void LTDC_ReloadConfig(uint32_t LTDC_Reload) +{ + /* Check the parameters */ + assert_param(IS_LTDC_RELOAD(LTDC_Reload)); + + /* Sets the Reload type */ + LTDC->SRCR = (uint32_t)LTDC_Reload; +} + + +/** + * @brief Initializes the LTDC Layer according to the specified parameters + * in the LTDC_LayerStruct. + * @note This function can be used only when the LTDC is disabled. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @param LTDC_LayerStruct: pointer to a LTDC_LayerTypeDef structure that contains + * the configuration information for the specified LTDC peripheral. + * @retval None + */ + +void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct) +{ + + uint32_t whsppos = 0; + uint32_t wvsppos = 0; + uint32_t dcgreen = 0; + uint32_t dcred = 0; + uint32_t dcalpha = 0; + uint32_t cfbp = 0; + +/* Check the parameters */ + assert_param(IS_LTDC_Pixelformat(LTDC_Layer_InitStruct->LTDC_PixelFormat)); + assert_param(IS_LTDC_BlendingFactor1(LTDC_Layer_InitStruct->LTDC_BlendingFactor_1)); + assert_param(IS_LTDC_BlendingFactor2(LTDC_Layer_InitStruct->LTDC_BlendingFactor_2)); + assert_param(IS_LTDC_HCONFIGST(LTDC_Layer_InitStruct->LTDC_HorizontalStart)); + assert_param(IS_LTDC_HCONFIGSP(LTDC_Layer_InitStruct->LTDC_HorizontalStop)); + assert_param(IS_LTDC_VCONFIGST(LTDC_Layer_InitStruct->LTDC_VerticalStart)); + assert_param(IS_LTDC_VCONFIGSP(LTDC_Layer_InitStruct->LTDC_VerticalStop)); + assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorBlue)); + assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorGreen)); + assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorRed)); + assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha)); + assert_param(IS_LTDC_CFBP(LTDC_Layer_InitStruct->LTDC_CFBPitch)); + assert_param(IS_LTDC_CFBLL(LTDC_Layer_InitStruct->LTDC_CFBLineLength)); + assert_param(IS_LTDC_CFBLNBR(LTDC_Layer_InitStruct->LTDC_CFBLineNumber)); + + /* Configures the horizontal start and stop position */ + whsppos = LTDC_Layer_InitStruct->LTDC_HorizontalStop << 16; + LTDC_Layerx->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); + LTDC_Layerx->WHPCR = (LTDC_Layer_InitStruct->LTDC_HorizontalStart | whsppos); + + /* Configures the vertical start and stop position */ + wvsppos = LTDC_Layer_InitStruct->LTDC_VerticalStop << 16; + LTDC_Layerx->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); + LTDC_Layerx->WVPCR = (LTDC_Layer_InitStruct->LTDC_VerticalStart | wvsppos); + + /* Specifies the pixel format */ + LTDC_Layerx->PFCR &= ~(LTDC_LxPFCR_PF); + LTDC_Layerx->PFCR = (LTDC_Layer_InitStruct->LTDC_PixelFormat); + + /* Configures the default color values */ + dcgreen = (LTDC_Layer_InitStruct->LTDC_DefaultColorGreen << 8); + dcred = (LTDC_Layer_InitStruct->LTDC_DefaultColorRed << 16); + dcalpha = (LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha << 24); + LTDC_Layerx->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); + LTDC_Layerx->DCCR = (LTDC_Layer_InitStruct->LTDC_DefaultColorBlue | dcgreen | \ + dcred | dcalpha); + + /* Specifies the constant alpha value */ + LTDC_Layerx->CACR &= ~(LTDC_LxCACR_CONSTA); + LTDC_Layerx->CACR = (LTDC_Layer_InitStruct->LTDC_ConstantAlpha); + + /* Specifies the blending factors */ + LTDC_Layerx->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); + LTDC_Layerx->BFCR = (LTDC_Layer_InitStruct->LTDC_BlendingFactor_1 | LTDC_Layer_InitStruct->LTDC_BlendingFactor_2); + + /* Configures the color frame buffer start address */ + LTDC_Layerx->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); + LTDC_Layerx->CFBAR = (LTDC_Layer_InitStruct->LTDC_CFBStartAdress); + + /* Configures the color frame buffer pitch in byte */ + cfbp = (LTDC_Layer_InitStruct->LTDC_CFBPitch << 16); + LTDC_Layerx->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); + LTDC_Layerx->CFBLR = (LTDC_Layer_InitStruct->LTDC_CFBLineLength | cfbp); + + /* Configures the frame buffer line number */ + LTDC_Layerx->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); + LTDC_Layerx->CFBLNR = (LTDC_Layer_InitStruct->LTDC_CFBLineNumber); + +} + +/** + * @brief Fills each LTDC_Layer_InitStruct member with its default value. + * @param LTDC_Layer_InitStruct: pointer to a LTDC_LayerTypeDef structure which will + * be initialized. + * @retval None + */ + +void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct) +{ + /*--------------- Reset Layer structure parameters values -------------------*/ + + /*!< Initialize the horizontal limit member */ + LTDC_Layer_InitStruct->LTDC_HorizontalStart = 0x00; + LTDC_Layer_InitStruct->LTDC_HorizontalStop = 0x00; + + /*!< Initialize the vertical limit member */ + LTDC_Layer_InitStruct->LTDC_VerticalStart = 0x00; + LTDC_Layer_InitStruct->LTDC_VerticalStop = 0x00; + + /*!< Initialize the pixel format member */ + LTDC_Layer_InitStruct->LTDC_PixelFormat = LTDC_Pixelformat_ARGB8888; + + /*!< Initialize the constant alpha value */ + LTDC_Layer_InitStruct->LTDC_ConstantAlpha = 0xFF; + + /*!< Initialize the default color values */ + LTDC_Layer_InitStruct->LTDC_DefaultColorBlue = 0x00; + LTDC_Layer_InitStruct->LTDC_DefaultColorGreen = 0x00; + LTDC_Layer_InitStruct->LTDC_DefaultColorRed = 0x00; + LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha = 0x00; + + /*!< Initialize the blending factors */ + LTDC_Layer_InitStruct->LTDC_BlendingFactor_1 = LTDC_BlendingFactor1_PAxCA; + LTDC_Layer_InitStruct->LTDC_BlendingFactor_2 = LTDC_BlendingFactor2_PAxCA; + + /*!< Initialize the frame buffer start address */ + LTDC_Layer_InitStruct->LTDC_CFBStartAdress = 0x00; + + /*!< Initialize the frame buffer pitch and line length */ + LTDC_Layer_InitStruct->LTDC_CFBLineLength = 0x00; + LTDC_Layer_InitStruct->LTDC_CFBPitch = 0x00; + + /*!< Initialize the frame buffer line number */ + LTDC_Layer_InitStruct->LTDC_CFBLineNumber = 0x00; +} + + +/** + * @brief Enables or disables the LTDC_Layer Controller. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @param NewState: new state of the LTDC_Layer peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable LTDC_Layer by setting LEN bit */ + LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_LEN; + } + else + { + /* Disable LTDC_Layer by clearing LEN bit */ + LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_LEN; + } +} + + +/** + * @brief Get the current position. + * @param LTDC_Pos_InitStruct: pointer to a LTDC_PosTypeDef structure that contains + * the current position. + * @retval None + */ + +LTDC_PosTypeDef LTDC_GetPosStatus(void) +{ + LTDC_PosTypeDef LTDC_Pos_InitStruct; + + LTDC->CPSR &= ~(LTDC_CPSR_CYPOS | LTDC_CPSR_CXPOS); + + LTDC_Pos_InitStruct.LTDC_POSX = (uint32_t)(LTDC->CPSR >> 16); + LTDC_Pos_InitStruct.LTDC_POSY = (uint32_t)(LTDC->CPSR & 0xFFFF); + + return LTDC_Pos_InitStruct; +} + +/** + * @brief Fills each LTDC_Pos_InitStruct member with its default value. + * @param LTDC_Pos_InitStruct: pointer to a LTDC_PosTypeDef structure which will + * be initialized. + * @retval None + */ + +void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct) +{ + LTDC_Pos_InitStruct->LTDC_POSX = 0x00; + LTDC_Pos_InitStruct->LTDC_POSY = 0x00; +} + +/** + * @brief Checks whether the specified LTDC's flag is set or not. + * @param LTDC_CD: specifies the flag to check. + * This parameter can be one of the following values: + * @arg LTDC_CD_VDES: vertical data enable current status. + * @arg LTDC_CD_HDES: horizontal data enable current status. + * @arg LTDC_CD_VSYNC: Vertical Synchronization current status. + * @arg LTDC_CD_HSYNC: Horizontal Synchronization current status. + * @retval The new state of LTDC_CD (SET or RESET). + */ + +FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD) +{ + FlagStatus bitstatus; + + /* Check the parameters */ + assert_param(IS_LTDC_GET_CD(LTDC_CD)); + + if ((LTDC->CDSR & LTDC_CD) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Set and configure the color keying. + * @param LTDC_colorkeying_InitStruct: pointer to a LTDC_ColorKeying_InitTypeDef + * structure that contains the color keying configuration. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval None + */ + +void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState) +{ + uint32_t ckgreen = 0; + uint32_t ckred = 0; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue)); + assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen)); + assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed)); + + if (NewState != DISABLE) + { + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Sets the color keying values */ + ckgreen = (LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen << 8); + ckred = (LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed << 16); + LTDC_Layerx->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_Layerx->CKCR |= (LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue | ckgreen | ckred); + } + else + { + /* Disable LTDC color keying by clearing COLKEN bit */ + LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + } + + /* Reload shadow register */ + LTDC->SRCR = LTDC_IMReload; +} + +/** + * @brief Fills each LTDC_colorkeying_InitStruct member with its default value. + * @param LTDC_colorkeying_InitStruct: pointer to a LTDC_ColorKeying_InitTypeDef structure which will + * be initialized. + * @retval None + */ + +void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct) +{ + /*!< Initialize the color keying values */ + LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue = 0x00; + LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen = 0x00; + LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed = 0x00; +} + + +/** + * @brief Enables or disables CLUT. + * @param NewState: new state of CLUT. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable CLUT by setting CLUTEN bit */ + LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + } + else + { + /* Disable CLUT by clearing CLUTEN bit */ + LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + } + + /* Reload shadow register */ + LTDC->SRCR = LTDC_IMReload; +} + +/** + * @brief configure the CLUT. + * @param LTDC_CLUT_InitStruct: pointer to a LTDC_CLUT_InitTypeDef structure that contains + * the CLUT configuration. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval None + */ + +void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct) +{ + uint32_t green = 0; + uint32_t red = 0; + uint32_t clutadd = 0; + + /* Check the parameters */ + assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_CLUTAdress)); + assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_RedValue)); + assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_GreenValue)); + assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_BlueValue)); + + /* Specifies the CLUT address and RGB value */ + green = (LTDC_CLUT_InitStruct->LTDC_GreenValue << 8); + red = (LTDC_CLUT_InitStruct->LTDC_RedValue << 16); + clutadd = (LTDC_CLUT_InitStruct->LTDC_CLUTAdress << 24); + LTDC_Layerx->CLUTWR = (clutadd | LTDC_CLUT_InitStruct->LTDC_BlueValue | \ + green | red); +} + +/** + * @brief Fills each LTDC_CLUT_InitStruct member with its default value. + * @param LTDC_CLUT_InitStruct: pointer to a LTDC_CLUT_InitTypeDef structure which will + * be initialized. + * @retval None + */ + +void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct) +{ + /*!< Initialize the CLUT adress and RGB values */ + LTDC_CLUT_InitStruct->LTDC_CLUTAdress = 0x00; + LTDC_CLUT_InitStruct->LTDC_BlueValue = 0x00; + LTDC_CLUT_InitStruct->LTDC_GreenValue = 0x00; + LTDC_CLUT_InitStruct->LTDC_RedValue = 0x00; +} + + +/** + * @brief reconfigure the layer position. + * @param OffsetX: horizontal offset from start active width . + * @param OffsetY: vertical offset from start active height. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval Reload of the shadow registers values must be applied after layer + * position reconfiguration. + */ + +void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY) +{ + + uint32_t tempreg, temp; + uint32_t horizontal_start; + uint32_t horizontal_stop; + uint32_t vertical_start; + uint32_t vertical_stop; + + LTDC_Layerx->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); + LTDC_Layerx->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); + + /* Reconfigures the horizontal and vertical start position */ + tempreg = LTDC->BPCR; + horizontal_start = (tempreg >> 16) + 1 + OffsetX; + vertical_start = (tempreg & 0xFFFF) + 1 + OffsetY; + + /* Reconfigures the horizontal and vertical stop position */ + /* Get the number of byte per pixel */ + + tempreg = LTDC_Layerx->PFCR; + + if (tempreg == LTDC_Pixelformat_ARGB8888) + { + temp = 4; + } + else if (tempreg == LTDC_Pixelformat_RGB888) + { + temp = 3; + } + else if ((tempreg == LTDC_Pixelformat_ARGB4444) || + (tempreg == LTDC_Pixelformat_RGB565) || + (tempreg == LTDC_Pixelformat_ARGB1555) || + (tempreg == LTDC_Pixelformat_AL88)) + { + temp = 2; + } + else + { + temp = 1; + } + + tempreg = LTDC_Layerx->CFBLR; + horizontal_stop = (((tempreg & 0x1FFF) - 3)/temp) + horizontal_start - 1; + + tempreg = LTDC_Layerx->CFBLNR; + vertical_stop = (tempreg & 0x7FF) + vertical_start - 1; + + LTDC_Layerx->WHPCR = horizontal_start | (horizontal_stop << 16); + LTDC_Layerx->WVPCR = vertical_start | (vertical_stop << 16); +} + +/** + * @brief reconfigure constant alpha. + * @param ConstantAlpha: constant alpha value. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval Reload of the shadow registers values must be applied after constant + * alpha reconfiguration. + */ + +void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha) +{ + /* reconfigure the constant alpha value */ + LTDC_Layerx->CACR = ConstantAlpha; +} + +/** + * @brief reconfigure layer address. + * @param Address: The color frame buffer start address. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval Reload of the shadow registers values must be applied after layer + * address reconfiguration. + */ + +void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address) +{ + /* Reconfigures the color frame buffer start address */ + LTDC_Layerx->CFBAR = Address; +} + +/** + * @brief reconfigure layer size. + * @param Width: layer window width. + * @param Height: layer window height. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval Reload of the shadow registers values must be applied after layer + * size reconfiguration. + */ + +void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height) +{ + + uint8_t temp; + uint32_t tempreg; + uint32_t horizontal_start; + uint32_t horizontal_stop; + uint32_t vertical_start; + uint32_t vertical_stop; + + tempreg = LTDC_Layerx->PFCR; + + if (tempreg == LTDC_Pixelformat_ARGB8888) + { + temp = 4; + } + else if (tempreg == LTDC_Pixelformat_RGB888) + { + temp = 3; + } + else if ((tempreg == LTDC_Pixelformat_ARGB4444) || \ + (tempreg == LTDC_Pixelformat_RGB565) || \ + (tempreg == LTDC_Pixelformat_ARGB1555) || \ + (tempreg == LTDC_Pixelformat_AL88)) + { + temp = 2; + } + else + { + temp = 1; + } + + /* update horizontal and vertical stop */ + tempreg = LTDC_Layerx->WHPCR; + horizontal_start = (tempreg & 0x1FFF); + horizontal_stop = Width + horizontal_start - 1; + + tempreg = LTDC_Layerx->WVPCR; + vertical_start = (tempreg & 0x1FFF); + vertical_stop = Height + vertical_start - 1; + + LTDC_Layerx->WHPCR = horizontal_start | (horizontal_stop << 16); + LTDC_Layerx->WVPCR = vertical_start | (vertical_stop << 16); + + /* Reconfigures the color frame buffer pitch in byte */ + LTDC_Layerx->CFBLR = ((Width * temp) << 16) | ((Width * temp) + 3); + + /* Reconfigures the frame buffer line number */ + LTDC_Layerx->CFBLNR = Height; + +} + +/** + * @brief reconfigure layer pixel format. + * @param PixelFormat: reconfigure the pixel format, this parameter can be + * one of the following values:@ref LTDC_Pixelformat. + * @param LTDC_layerx: Select the layer to be configured, this parameter can be + * one of the following values: LTDC_Layer1, LTDC_Layer2 + * @retval Reload of the shadow registers values must be applied after layer + * pixel format reconfiguration. + */ + +void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat) +{ + + uint8_t temp; + uint32_t tempreg; + + tempreg = LTDC_Layerx->PFCR; + + if (tempreg == LTDC_Pixelformat_ARGB8888) + { + temp = 4; + } + else if (tempreg == LTDC_Pixelformat_RGB888) + { + temp = 3; + } + else if ((tempreg == LTDC_Pixelformat_ARGB4444) || \ + (tempreg == LTDC_Pixelformat_RGB565) || \ + (tempreg == LTDC_Pixelformat_ARGB1555) || \ + (tempreg == LTDC_Pixelformat_AL88)) + { + temp = 2; + } + else + { + temp = 1; + } + + tempreg = (LTDC_Layerx->CFBLR >> 16); + tempreg = (tempreg / temp); + + if (PixelFormat == LTDC_Pixelformat_ARGB8888) + { + temp = 4; + } + else if (PixelFormat == LTDC_Pixelformat_RGB888) + { + temp = 3; + } + else if ((PixelFormat == LTDC_Pixelformat_ARGB4444) || \ + (PixelFormat == LTDC_Pixelformat_RGB565) || \ + (PixelFormat == LTDC_Pixelformat_ARGB1555) || \ + (PixelFormat == LTDC_Pixelformat_AL88)) + { + temp = 2; + } + else + { + temp = 1; + } + + /* Reconfigures the color frame buffer pitch in byte */ + LTDC_Layerx->CFBLR = ((tempreg * temp) << 16) | ((tempreg * temp) + 3); + + /* Reconfigures the color frame buffer start address */ + LTDC_Layerx->PFCR = PixelFormat; + +} + +/** + * @} + */ + +/** @defgroup LTDC_Group2 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure the LTDC Interrupts + and to get the status and clear flags and Interrupts pending bits. + + [..] The LTDC provides 4 Interrupts sources and 4 Flags + + *** Flags *** + ============= + [..] + (+) LTDC_FLAG_LI: Line Interrupt flag. + (+) LTDC_FLAG_FU: FIFO Underrun Interrupt flag. + (+) LTDC_FLAG_TERR: Transfer Error Interrupt flag. + (+) LTDC_FLAG_RR: Register Reload interrupt flag. + + *** Interrupts *** + ================== + [..] + (+) LTDC_IT_LI: Line Interrupt is generated when a programmed line + is reached. The line interrupt position is programmed in + the LTDC_LIPR register. + (+) LTDC_IT_FU: FIFO Underrun interrupt is generated when a pixel is requested + from an empty layer FIFO + (+) LTDC_IT_TERR: Transfer Error interrupt is generated when an AHB bus + error occurs during data transfer. + (+) LTDC_IT_RR: Register Reload interrupt is generated when the shadow + registers reload was performed during the vertical blanking + period. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified LTDC's interrupts. + * @param LTDC_IT: specifies the LTDC interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt Enable. + * @arg LTDC_IT_FU: FIFO Underrun Interrupt Enable. + * @arg LTDC_IT_TERR: Transfer Error Interrupt Enable. + * @arg LTDC_IT_RR: Register Reload interrupt enable. + * @param NewState: new state of the specified LTDC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_LTDC_IT(LTDC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + LTDC->IER |= LTDC_IT; + } + else + { + LTDC->IER &= (uint32_t)~LTDC_IT; + } +} + +/** + * @brief Checks whether the specified LTDC's flag is set or not. + * @param LTDC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag. + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag. + * @arg LTDC_FLAG_TERR: Transfer Error Interrupt flag. + * @arg LTDC_FLAG_RR: Register Reload interrupt flag. + * @retval The new state of LTDC_FLAG (SET or RESET). + */ +FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_LTDC_FLAG(LTDC_FLAG)); + + if ((LTDC->ISR & LTDC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the LTDC's pending flags. + * @param LTDC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag. + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag. + * @arg LTDC_FLAG_TERR: Transfer Error Interrupt flag. + * @arg LTDC_FLAG_RR: Register Reload interrupt flag. + * @retval None + */ +void LTDC_ClearFlag(uint32_t LTDC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_LTDC_FLAG(LTDC_FLAG)); + + /* Clear the corresponding LTDC flag */ + LTDC->ICR = (uint32_t)LTDC_FLAG; +} + +/** + * @brief Checks whether the specified LTDC's interrupt has occurred or not. + * @param LTDC_IT: specifies the LTDC interrupts sources to check. + * This parameter can be one of the following values: + * @arg LTDC_IT_LI: Line Interrupt Enable. + * @arg LTDC_IT_FU: FIFO Underrun Interrupt Enable. + * @arg LTDC_IT_TERR: Transfer Error Interrupt Enable. + * @arg LTDC_IT_RR: Register Reload interrupt Enable. + * @retval The new state of the LTDC_IT (SET or RESET). + */ +ITStatus LTDC_GetITStatus(uint32_t LTDC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_LTDC_IT(LTDC_IT)); + + if ((LTDC->ISR & LTDC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + if (((LTDC->IER & LTDC_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + + +/** + * @brief Clears the LTDC's interrupt pending bits. + * @param LTDC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LIE: Line Interrupt. + * @arg LTDC_IT_FUIE: FIFO Underrun Interrupt. + * @arg LTDC_IT_TERRIE: Transfer Error Interrupt. + * @arg LTDC_IT_RRIE: Register Reload interrupt. + * @retval None + */ +void LTDC_ClearITPendingBit(uint32_t LTDC_IT) +{ + /* Check the parameters */ + assert_param(IS_LTDC_IT(LTDC_IT)); + + /* Clear the corresponding LTDC Interrupt */ + LTDC->ICR = (uint32_t)LTDC_IT; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c index 9a14f55836..43b4f6b363 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c @@ -2,29 +2,35 @@ ****************************************************************************** * @file stm32f4xx_pwr.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: - * - Backup Domain Access - * - PVD configuration - * - WakeUp pin configuration - * - Main and Backup Regulators configuration - * - FLASH Power Down configuration - * - Low Power modes configuration - * - Flags management + * + Backup Domain Access + * + PVD configuration + * + WakeUp pin configuration + * + Main and Backup Regulators configuration + * + FLASH Power Down configuration + * + Low Power modes configuration + * + Flags management * ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -65,6 +71,13 @@ #define PMODE_BitNumber 0x0E #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4)) +/* Alias word address of ODEN bit */ +#define ODEN_BitNumber 0x10 +#define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4)) + +/* Alias word address of ODSWEN bit */ +#define ODSWEN_BitNumber 0x11 +#define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4)) /* --- CSR Register ---*/ @@ -80,8 +93,9 @@ /* ------------------ PWR registers bit mask ------------------------ */ /* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CR_DS_MASK ((uint32_t)0xFFFFF3FC) #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) +#define CR_VOS_MASK ((uint32_t)0xFFFF3FFF) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -97,16 +111,16 @@ * @verbatim =============================================================================== - Backup Domain Access function + ##### Backup Domain Access function ##### =============================================================================== - - After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - - Enable the Power Controller (PWR) APB1 interface clock using the - RCC_APB1PeriphClockCmd() function. - - Enable access to RTC domain using the PWR_BackupAccessCmd() function. + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + RCC_APB1PeriphClockCmd() function. + (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function. @endverbatim * @{ @@ -149,15 +163,15 @@ void PWR_BackupAccessCmd(FunctionalState NewState) * @verbatim =============================================================================== - PVD configuration functions + ##### PVD configuration functions ##### =============================================================================== - - - The PVD is used to monitor the VDD power supply by comparing it to a threshold - selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the - PVD threshold. This event is internally connected to the EXTI line16 - and can generate an interrupt if enabled through the EXTI registers. - - The PVD is stopped in Standby mode. + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled through the EXTI registers. + (+) The PVD is stopped in Standby mode. @endverbatim * @{ @@ -167,15 +181,17 @@ void PWR_BackupAccessCmd(FunctionalState NewState) * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). * @param PWR_PVDLevel: specifies the PVD detection level * This parameter can be one of the following values: - * @arg PWR_PVDLevel_0: PVD detection level set to 2.0V - * @arg PWR_PVDLevel_1: PVD detection level set to 2.2V - * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V - * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V - * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V - * @arg PWR_PVDLevel_5: PVD detection level set to 2.8V - * @arg PWR_PVDLevel_6: PVD detection level set to 2.9V - * @arg PWR_PVDLevel_7: PVD detection level set to 3.0V - * @note Refer to the electrical characteristics of you device datasheet for more details. + * @arg PWR_PVDLevel_0 + * @arg PWR_PVDLevel_1 + * @arg PWR_PVDLevel_2 + * @arg PWR_PVDLevel_3 + * @arg PWR_PVDLevel_4 + * @arg PWR_PVDLevel_5 + * @arg PWR_PVDLevel_6 + * @arg PWR_PVDLevel_7 + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. * @retval None */ void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) @@ -220,12 +236,12 @@ void PWR_PVDCmd(FunctionalState NewState) * @verbatim =============================================================================== - WakeUp pin configuration functions + ##### WakeUp pin configuration functions ##### =============================================================================== - - - WakeUp pin is used to wakeup the system from Standby mode. This pin is - forced in input pull down configuration and is active on rising edges. - - There is only one WakeUp pin: WakeUp Pin 1 on PA.00. + [..] + (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is + forced in input pull down configuration and is active on rising edges. + (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00. @endverbatim * @{ @@ -254,37 +270,76 @@ void PWR_WakeUpPinCmd(FunctionalState NewState) * @verbatim =============================================================================== - Main and Backup Regulators configuration functions + ##### Main and Backup Regulators configuration functions ##### =============================================================================== - - - The backup domain includes 4 Kbytes of backup SRAM accessible only from the - CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained - even in Standby or VBAT mode when the low power backup regulator is enabled. - It can be considered as an internal EEPROM when VBAT is always present. - You can use the PWR_BackupRegulatorCmd() function to enable the low power - backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is - ready or not. - - - When the backup domain is supplied by VDD (analog switch connected to VDD) - the backup SRAM is powered from VDD which replaces the VBAT power supply to - save battery life. - - - The backup SRAM is not mass erased by an tamper event. It is read protected - to prevent confidential data, such as cryptographic private key, from being - accessed. The backup SRAM can be erased only through the Flash interface when - a protection level change from level 1 to level 0 is requested. - Refer to the description of Read protection (RDP) in the Flash programming manual. - - - The main internal regulator can be configured to have a tradeoff between performance - and power consumption when the device does not operate at the maximum frequency. - This is done through PWR_MainRegulatorModeConfig() function which configure VOS bit - in PWR_CR register: - - When this bit is set (Regulator voltage output Scale 1 mode selected) the System - frequency can go up to 168 MHz. - - When this bit is reset (Regulator voltage output Scale 2 mode selected) the System - frequency can go up to 144 MHz. - Refer to the datasheets for more details. - + [..] + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from + the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is + retained even in Standby or VBAT mode when the low power backup regulator + is enabled. It can be considered as an internal EEPROM when VBAT is + always present. You can use the PWR_BackupRegulatorCmd() function to + enable the low power backup regulator and use the PWR_GetFlagStatus + (PWR_FLAG_BRR) to check if it is ready or not. + + (+) When the backup domain is supplied by VDD (analog switch connected to VDD) + the backup SRAM is powered from VDD which replaces the VBAT power supply to + save battery life. + + (+) The backup SRAM is not mass erased by an tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the reference manual. + + (+) The main internal regulator can be configured to have a tradeoff between + performance and power consumption when the device does not operate at + the maximum frequency. + (+) For STM32F405xx/407xx and STM32F415xx/417xx Devices, the regulator can be + configured on the fly through PWR_MainRegulatorModeConfig() function which + configure VOS bit in PWR_CR register: + (++) When this bit is set (Regulator voltage output Scale 1 mode selected) + the System frequency can go up to 168 MHz. + (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) + the System frequency can go up to 144 MHz. + + (+) For STM32F42xxx/43xxx Devices, the regulator can be configured through + PWR_MainRegulatorModeConfig() function which configure VOS[1:0] bits in + PWR_CR register: + which configure VOS[1:0] bits in PWR_CR register: + (++) When VOS[1:0] = 11 (Regulator voltage output Scale 1 mode selected) + the System frequency can go up to 168 MHz. + (++) When VOS[1:0] = 10 (Regulator voltage output Scale 2 mode selected) + the System frequency can go up to 144 MHz. + (++) When VOS[1:0] = 01 (Regulator voltage output Scale 3 mode selected) + the System frequency can go up to 120 MHz. + + (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL + is OFF and the HSI or HSE clock source is selected as system clock. + The new value programmed is active only when the PLL is ON. + When the PLL is OFF, the voltage scale 3 is automatically selected. + Refer to the datasheets for more details. + + (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has + 2 operating modes available: + (++) Normal mode: The CPU and core logic operate at maximum frequency at a given + voltage scaling (scale 1, scale 2 or scale 3) + (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a + higher frequency than the normal mode for a given voltage scaling (scale 1, + scale 2 or scale 3). This mode is enabled through PWR_OverDriveCmd() function and + PWR_OverDriveSWCmd() function, to enter or exit from Over-drive mode please follow + the sequence described in Reference manual. + + (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator + supplies a low power voltage to the 1.2V domain, thus preserving the content of registers + and internal SRAM. 2 operating modes are available: + (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only + available when the main regulator or the low power regulator is used in Scale 3 or + low voltage mode. + (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only + available when the main regulator or the low power regulator is in low voltage mode. + This mode is enabled through PWR_UnderDriveCmd() function. + @endverbatim * @{ */ @@ -313,20 +368,104 @@ void PWR_BackupRegulatorCmd(FunctionalState NewState) * System frequency up to 168 MHz. * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, * System frequency up to 144 MHz. + * @arg PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode, + * System frequency up to 120 MHz (only for STM32F42xxx/43xxx devices) * @retval None */ void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage) { + uint32_t tmpreg = 0; + /* Check the parameters */ assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage)); - if (PWR_Regulator_Voltage == PWR_Regulator_Voltage_Scale2) + tmpreg = PWR->CR; + + /* Clear VOS[15:14] bits */ + tmpreg &= CR_VOS_MASK; + + /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */ + tmpreg |= PWR_Regulator_Voltage; + + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the Over-Drive. + * + * @note This function can be used only for STM32F42xxx/STM3243xxx devices. + * This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * + * @param NewState: new state of the Over Drive mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_OverDriveCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Set/Reset the ODEN bit to enable/disable the Over Drive mode */ + *(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Over-Drive switching. + * + * @note This function can be used only for STM32F42xxx/STM3243xxx devices. + * + * @param NewState: new state of the Over Drive switching mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_OverDriveSWCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Set/Reset the ODSWEN bit to enable/disable the Over Drive switching mode */ + *(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Under-Drive mode. + * + * @note This function can be used only for STM32F42xxx/STM3243xxx devices. + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode + * + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + * + * @param NewState: new state of the Under Drive mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_UnderDriveCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { - PWR->CR &= ~PWR_Regulator_Voltage_Scale1; + /* Set the UDEN[1:0] bits to enable the Under Drive mode */ + PWR->CR |= (uint32_t)PWR_CR_UDEN; } else - { - PWR->CR |= PWR_Regulator_Voltage_Scale1; + { + /* Reset the UDEN[1:0] bits to disable the Under Drive mode */ + PWR->CR &= (uint32_t)(~PWR_CR_UDEN); } } @@ -339,14 +478,14 @@ void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage) * @verbatim =============================================================================== - FLASH Power Down configuration functions + ##### FLASH Power Down configuration functions ##### =============================================================================== - - - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd() - function, the Flash memory also enters power down mode when the device enters - Stop mode. When the Flash memory is in power down mode, an additional startup - delay is incurred when waking up from Stop mode. - + [..] + (+) By setting the FPDS bit in the PWR_CR register by using the + PWR_FlashPowerDownCmd() function, the Flash memory also enters power + down mode when the device enters Stop mode. When the Flash memory + is in power down mode, an additional startup delay is incurred when + waking up from Stop mode. @endverbatim * @{ */ @@ -374,103 +513,109 @@ void PWR_FlashPowerDownCmd(FunctionalState NewState) * @verbatim =============================================================================== - Low Power modes configuration functions + ##### Low Power modes configuration functions ##### =============================================================================== - - The devices feature 3 low-power modes: - - Sleep mode: Cortex-M4 core stopped, peripherals kept running. - - Stop mode: all clocks are stopped, regulator running, regulator in low power mode - - Standby mode: 1.2V domain powered off. + [..] + The devices feature 3 low-power modes: + (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator + in low power mode + (+) Standby mode: 1.2V domain powered off. - Sleep mode - =========== - - Entry: - - The Sleep mode is entered by using the __WFI() or __WFE() functions. - - Exit: - - Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - Stop mode - ========== - In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents - are preserved. - The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption In Stop mode, FLASH can be powered off before - entering the Stop mode. It can be switched on again by software after exiting - the Stop mode using the PWR_FlashPowerDownCmd() function. + *** Sleep mode *** + ================== + [..] + (+) Entry: + (++) The Sleep mode is entered by using the __WFI() or __WFE() functions. + (+) Exit: + (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] + In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption In Stop mode, FLASH can be powered off before + entering the Stop mode. It can be switched on again by software after exiting + the Stop mode using the PWR_FlashPowerDownCmd() function. - - Entry: - - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) - function with regulator in LowPower or with Regulator ON. - - Exit: - - Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + (+) Entry: + (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_MainRegulator_ON) + function with: + (+++) Main regulator ON. + (+++) Low Power regulator ON. + (+) Exit: + (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. - Standby mode - ============ - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. - The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers, backup SRAM and Standby - circuitry. + *** Standby mode *** + ==================== + [..] + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. + The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers, backup SRAM and Standby + circuitry. - The voltage regulator is OFF. + The voltage regulator is OFF. - - Entry: - - The Standby mode is entered using the PWR_EnterSTANDBYMode() function. - - Exit: - - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - Auto-wakeup (AWU) from low-power mode - ===================================== - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event, a time-stamp event, or a comparator event, - without depending on an external interrupt (Auto-wakeup mode). - - - RTC auto-wakeup (AWU) from the Stop mode - ---------------------------------------- - - - To wake up from the Stop mode with an RTC alarm event, it is necessary to: - - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - - To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to: - - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - - Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: - - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - - RTC auto-wakeup (AWU) from the Standby mode - ------------------------------------------- - - To wake up from the Standby mode with an RTC alarm event, it is necessary to: - - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - - To wake up from the Standby mode with an RTC Tamper or time stamp event, it - is necessary to: - - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - - Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: - - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. + (+) Entry: + (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event, a time-stamp event, or a comparator event, + without depending on an external interrupt (Auto-wakeup mode). + + (#) RTC auto-wakeup (AWU) from the Stop mode + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: + (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function + (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + and RTC_AlarmCmd() functions. + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to: + (+++) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + function + (+++) Configure the RTC to detect the tamper or time stamp event using the + RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + functions. + (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: + (+++) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function + (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), + RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. + + (#) RTC auto-wakeup (AWU) from the Standby mode + + (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: + (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function + (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + and RTC_AlarmCmd() functions. + (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it + is necessary to: + (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + function + (+++) Configure the RTC to detect the tamper or time stamp event using the + RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + functions. + (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: + (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function + (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), + RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. @endverbatim * @{ @@ -485,12 +630,12 @@ void PWR_FlashPowerDownCmd(FunctionalState NewState) * @note When the voltage regulator operates in low power mode, an additional * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. + * is higher although the startup time is reduced. * * @param PWR_Regulator: specifies the regulator state in STOP mode. * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: STOP mode with regulator ON - * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @arg PWR_MainRegulator_ON: STOP mode with regulator ON + * @arg PWR_LowPowerRegulator_ON: STOP mode with low power regulator ON * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction @@ -507,10 +652,74 @@ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) /* Select the regulator state in STOP mode ---------------------------------*/ tmpreg = PWR->CR; - /* Clear PDDS and LPDSR bits */ + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_MASK; + + /* Set LPDS, MRLVDS and LPLVDS bits according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters in Under-Drive STOP mode. + * + * @note This mode is only available for STM32F42xxx/STM3243xxx devices. + * + * @note This mode can be selected only when the Under-Drive is already active + * + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MainRegulator_UnderDrive_ON: Main Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @arg PWR_LowPowerRegulator_UnderDrive_ON: Low Power Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR_UNDERDRIVE(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ tmpreg &= CR_DS_MASK; - /* Set LPDSR bit according to PWR_Regulator value */ + /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ tmpreg |= PWR_Regulator; /* Store the new value */ @@ -573,7 +782,7 @@ void PWR_EnterSTANDBYMode(void) * @verbatim =============================================================================== - Flags management functions + ##### Flags management functions ##### =============================================================================== @endverbatim @@ -599,7 +808,13 @@ void PWR_EnterSTANDBYMode(void) * when the device wakes up from Standby mode or by a system reset * or power reset. * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage - * scaling output selection is ready. + * scaling output selection is ready. + * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode + * is ready (STM32F42xxx/43xxx devices) + * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode + * switcching is ready (STM32F42xxx/43xxx devices) + * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode + * is enabled in Stop mode (STM32F42xxx/43xxx devices) * @retval The new state of PWR_FLAG (SET or RESET). */ FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) @@ -627,14 +842,28 @@ FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag + * @arg PWR_FLAG_UDRDY: Under-drive ready flag (STM32F42xxx/43xxx devices) * @retval None */ void PWR_ClearFlag(uint32_t PWR_FLAG) { /* Check the parameters */ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) + if (PWR_FLAG != PWR_FLAG_UDRDY) + { + PWR->CR |= PWR_FLAG << 2; + } + else + { + PWR->CSR |= PWR_FLAG_UDRDY; + } +#endif /* STM32F427_437xx || STM32F429_439xx */ + +#if defined (STM32F40_41xxx) || defined (STM32F401xx) PWR->CR |= PWR_FLAG << 2; +#endif /* STM32F40_41xxx */ } /** @@ -653,4 +882,4 @@ void PWR_ClearFlag(uint32_t PWR_FLAG) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c index 87763748a6..741f609b52 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c @@ -2,53 +2,56 @@ ****************************************************************************** * @file stm32f4xx_rcc.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Reset and clock control (RCC) peripheral: - * - Internal/external clocks, PLL, CSS and MCO configuration - * - System, AHB and APB busses clocks configuration - * - Peripheral clocks configuration - * - Interrupts and flags management + * + Internal/external clocks, PLL, CSS and MCO configuration + * + System, AHB and APB busses clocks configuration + * + Peripheral clocks configuration + * + Interrupts and flags management * - * @verbatim - * - * =================================================================== - * RCC specific features - * =================================================================== - * - * After reset the device is running from Internal High Speed oscillator - * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache - * and I-Cache are disabled, and all peripherals are off except internal - * SRAM, Flash and JTAG. - * - There is no prescaler on High speed (AHB) and Low speed (APB) busses; - * all peripherals mapped on these busses are running at HSI speed. - * - The clock for all peripherals is switched off, except the SRAM and FLASH. - * - All GPIOs are in input floating state, except the JTAG pins which - * are assigned to be used for debug purpose. - * - * Once the device started from reset, the user application has to: - * - Configure the clock source to be used to drive the System clock - * (if the application needs higher frequency/performance) - * - Configure the System clock frequency and Flash settings - * - Configure the AHB and APB busses prescalers - * - Enable the clock for the peripheral(s) to be used - * - Configure the clock source(s) for peripherals which clocks are not - * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - * - * @endverbatim - * + @verbatim + =============================================================================== + ##### RCC specific features ##### + =============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; + all peripherals mapped on these busses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + @endverbatim ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -83,6 +86,10 @@ #define PLLI2SON_BitNumber 0x1A #define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) +/* Alias word address of PLLSAION bit */ +#define PLLSAION_BitNumber 0x1C +#define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4)) + /* --- CFGR Register ---*/ /* Alias word address of I2SSRC bit */ #define CFGR_OFFSET (RCC_OFFSET + 0x08) @@ -97,11 +104,18 @@ /* Alias word address of BDRST bit */ #define BDRST_BitNumber 0x10 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + /* --- CSR Register ---*/ /* Alias word address of LSION bit */ #define CSR_OFFSET (RCC_OFFSET + 0x74) #define LSION_BitNumber 0x00 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +/* --- DCKCFGR Register ---*/ +/* Alias word address of TIMPRE bit */ +#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C) +#define TIMPRE_BitNumber 0x18 +#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4)) /* ---------------------- RCC registers bit mask ------------------------ */ /* CFGR register bit mask */ #define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) @@ -137,45 +151,48 @@ static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6 * @brief Internal and external clocks, PLL, CSS and MCO configuration functions * @verbatim - =============================================================================== - Internal/external clocks, PLL, CSS and MCO configuration functions - =============================================================================== - - This section provide functions allowing to configure the internal/external clocks, - PLLs, CSS and MCO pins. + =================================================================================== + ##### Internal and external clocks, PLL, CSS and MCO configuration functions ##### + =================================================================================== + [..] + This section provide functions allowing to configure the internal/external clocks, + PLLs, CSS and MCO pins. - 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. + (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. - 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC - clock source. + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. - 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. + (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. - 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - 5. PLL (clocked by HSI or HSE), featuring two different output clocks: - - The first output is used to generate the high speed system clock (up to 168 MHz) - - The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). + (#) PLL (clocked by HSI or HSE), featuring two different output clocks: + (++) The first output is used to generate the high speed system clock (up to 168 MHz) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). - 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve - high-quality audio performance on the I2S interface. + (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve + high-quality audio performance on the I2S interface or SAI interface in case + of STM32F429x/439x devices. + + (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI + interface and LCD TFT controller available only for STM32F42xxx/43xxx devices. - 7. CSS (Clock security system), once enable and if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) - exception vector. - - 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL - clock (through a configurable prescaler) on PA8 pin. - - 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S - clock (through a configurable prescaler) on PC9 pin. - -@endverbatim + (#) CSS (Clock security system), once enable and if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) + exception vector. + + (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL + clock (through a configurable prescaler) on PA8 pin. + + (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S + clock (through a configurable prescaler) on PC9 pin. + @endverbatim * @{ */ @@ -188,7 +205,7 @@ static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6 * - CSS, MCO1 and MCO2 OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the - * - Peripheral clocks + * - Peripheral clocks * - LSI, LSE and RTC clocks * @param None * @retval None @@ -201,17 +218,27 @@ void RCC_DeInit(void) /* Reset CFGR register */ RCC->CFGR = 0x00000000; - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; + /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42/43xxx devices) bits */ + RCC->CR &= (uint32_t)0xEAF6FFFF; /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x24003010; + /* Reset PLLI2SCFGR register */ + RCC->PLLI2SCFGR = 0x20003000; + + /* Reset PLLSAICFGR register, only available for STM32F42/43xxx devices */ + RCC->PLLSAICFGR = 0x24003000; + /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /* Disable all interrupts */ RCC->CIR = 0x00000000; + + /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx devices */ + RCC->DCKCFGR = 0x00000000; + } /** @@ -463,9 +490,13 @@ void RCC_PLLCmd(FunctionalState NewState) *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; } +#if defined (STM32F40_41xxx) || defined (STM32F401xx) /** * @brief Configures the PLLI2S clock multiplication and division factors. * + * @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx + * or STM32F401xx devices. + * * @note This function must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * RCC_PLLConfig function ) @@ -490,6 +521,44 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); } +#endif /* STM32F40_41xxx || STM32F401xx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +/** + * @brief Configures the PLLI2S clock multiplication and division factors. + * + * @note This function can be used only for STM32F42xxx/43xxx devices + * + * @note This function must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between 192 and 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between 192 and 432 MHz. + * + * @param PLLI2SQ: specifies the division factor for SAI1 clock + * This parameter must be a number between 2 and 15. + * + * @param PLLI2SR: specifies the division factor for I2S clock + * This parameter must be a number between 2 and 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices. + * + * @retval None + */ +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); + + RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28); +} +#endif /* STM32F427_437xx || STM32F429_439xx */ /** * @brief Enables or disables the PLLI2S. @@ -504,6 +573,53 @@ void RCC_PLLI2SCmd(FunctionalState NewState) *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; } +/** + * @brief Configures the PLLSAI clock multiplication and division factors. + * + * @note This function can be used only for STM32F42xxx/43xxx devices + * + * @note This function must be used only when the PLLSAI is disabled. + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock + * This parameter must be a number between 192 and 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between 192 and 432 MHz. + * + * @param PLLSAIQ: specifies the division factor for SAI1 clock + * This parameter must be a number between 2 and 15. + * + * @param PLLSAIR: specifies the division factor for LTDC clock + * This parameter must be a number between 2 and 7. + * + * @retval None + */ +void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN)); + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR)); + + RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28); +} + +/** + * @brief Enables or disables the PLLSAI. + * + * @note This function can be used only for STM32F42xxx/43xxx devices + * + * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLSAICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState; +} + /** * @brief Enables or disables the Clock Security System. * @note If a failure is detected on the HSE oscillator clock, this oscillator @@ -607,59 +723,119 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) * @verbatim =============================================================================== - System, AHB and APB busses clocks configuration functions + ##### System, AHB and APB busses clocks configuration functions ##### =============================================================================== - - This section provide functions allowing to configure the System, AHB, APB1 and - APB2 busses clocks. + [..] + This section provide functions allowing to configure the System, AHB, APB1 and + APB2 busses clocks. - 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable prescaler - and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). - APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through - configurable prescalers and used to clock the peripherals mapped on these busses. - You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. - -@note All the peripheral clocks are derived from the System clock (SYSCLK) except: - - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or - from an external clock mapped on the I2S_CKIN pin. - You have to use RCC_I2SCLKConfig() function to configure this clock. - - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() - functions to configure this clock. - - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz - to work correctly, while the SDIO require a frequency equal or lower than - to 48. This clock is derived of the main PLL through PLLQ divider. - - IWDG clock which is always the LSI clock. + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or + from an external clock mapped on the I2S_CKIN pin. + You have to use RCC_I2SCLKConfig() function to configure this clock. + (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() + functions to configure this clock. + (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz + to work correctly, while the SDIO require a frequency equal or lower than + to 48. This clock is derived of the main PLL through PLLQ divider. + (+@) IWDG clock which is always the LSI clock. - 2. The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 82 MHz and PCLK1 42 MHz. - Depending on the device voltage range, the maximum frequency should be - adapted accordingly: + (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency + of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending + on the device voltage range, the maximum frequency should be adapted accordingly: + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| + +---------------|----------------|----------------|-----------------|-----------------+ + (#) For STM32F42xxx/43xxx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz, + PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum + frequency should be adapted accordingly: +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |---------------------------------------------------------------------| | | voltage range | voltage range | voltage range | voltage range | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | + |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | + |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 | + |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| + |---------------|----------------|----------------|-----------------|-----------------| + |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| + +-------------------------------------------------------------------------------------+ + + (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz, + PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum + frequency should be adapted accordingly: + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 | + |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120| - +-------------------------------------------------------------------------------------+ - @note When VOS bit (in PWR_CR register) is reset to '0’, the maximum value of HCLK is 144 MHz. - You can use PWR_MainRegulatorModeConfig() function to set or reset this bit. + |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | + +-------------------------------------------------------------------------------------+ + + -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: + (++) when VOS = '0', the maximum value of fHCLK = 144MHz. + (++) when VOS = '1', the maximum value of fHCLK = 168MHz. + [..] + On STM32F42xxx/43xxx devices: + (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz. + (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz. + (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz + [..] + On STM32F401x devices: + (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz. + (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz. + You can use PWR_MainRegulatorModeConfig() function to control VOS bits. @endverbatim * @{ @@ -926,26 +1102,26 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) * @verbatim =============================================================================== - Peripheral clocks configuration functions + ##### Peripheral clocks configuration functions ##### =============================================================================== - - This section provide functions allowing to configure the Peripheral clocks. + [..] This section provide functions allowing to configure the Peripheral clocks. - 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31. + (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided + by 2 to 31. - 2. After restart from Reset or wakeup from STANDBY, all peripherals are off - except internal SRAM, Flash and JTAG. Before to start using a peripheral you - have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd() - , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. - - 3. To reset the peripherals configuration (to the default state after device reset) - you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and - RCC_APB1PeriphResetCmd() functions. + (#) After restart from Reset or wakeup from STANDBY, all peripherals are off + except internal SRAM, Flash and JTAG. Before to start using a peripheral + you have to enable its interface clock. You can do this using + RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. + + (#) To reset the peripherals configuration (to the default state after device reset) + you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and + RCC_APB1PeriphResetCmd() functions. - 4. To further reduce power consumption in SLEEP mode the peripheral clocks can - be disabled prior to executing the WFI or WFE instructions. You can do this - using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and - RCC_APB1PeriphClockLPModeCmd() functions. + (#) To further reduce power consumption in SLEEP mode the peripheral clocks + can be disabled prior to executing the WFI or WFE instructions. + You can do this using RCC_AHBPeriphClockLPModeCmd(), + RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions. @endverbatim * @{ @@ -1051,6 +1227,202 @@ void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; } +/** + * @brief Configures the SAI clock Divider coming from PLLI2S. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note This function must be called before enabling the PLLI2S. + * + * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock . + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ + * + * @retval None + */ +void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ)); + + tmpreg = RCC->DCKCFGR; + + /* Clear PLLI2SDIVQ[4:0] bits */ + tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ); + + /* Set PLLI2SDIVQ values */ + tmpreg |= (RCC_PLLI2SDivQ - 1); + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + +/** + * @brief Configures the SAI clock Divider coming from PLLSAI. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note This function must be called before enabling the PLLSAI. + * + * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock . + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ + * + * @retval None + */ +void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ)); + + tmpreg = RCC->DCKCFGR; + + /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */ + tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ); + + /* Set PLLSAIDIVQ values */ + tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8); + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + +/** + * @brief Configures SAI1BlockA clock source selection. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block A clock + * @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block A clock + * @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin + * used as SAI1 Block A clock + * @retval None + */ +void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource)); + + tmpreg = RCC->DCKCFGR; + + /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */ + tmpreg &= ~RCC_DCKCFGR_SAI1ASRC; + + /* Set SAI Block A source selection value */ + tmpreg |= RCC_SAIBlockACLKSource; + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + +/** + * @brief Configures SAI1BlockB clock source selection. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block B clock + * @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block B clock + * @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin + * used as SAI1 Block B clock + * @retval None + */ +void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource)); + + tmpreg = RCC->DCKCFGR; + + /* Clear RCC_DCKCFGR_SAI1BSRC[1:0] bits */ + tmpreg &= ~RCC_DCKCFGR_SAI1BSRC; + + /* Set SAI Block B source selection value */ + tmpreg |= RCC_SAIBlockBCLKSource; + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + + +/** + * @brief Configures the LTDC clock Divider coming from PLLSAI. + * + * @note The LTDC peripheral is only available with STM32F429xx/439xx Devices. + * + * @note This function must be called before enabling the PLLSAI. + * + * @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock . + * This parameter must be a number between 2 and 16. + * LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR + * + * @retval None + */ +void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(RCC_PLLSAIDivR)); + + tmpreg = RCC->DCKCFGR; + + /* Clear PLLSAIDIVR[2:0] bits */ + tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR; + + /* Set PLLSAIDIVR values */ + tmpreg |= RCC_PLLSAIDivR; + + /* Store the new value */ + RCC->DCKCFGR = tmpreg; +} + +/** + * @brief Configures the Timers clocks prescalers selection. + * + * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices. + * + * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1 or 2, + * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to + * division by 4 or more. + * + * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding + * to division by 8 or more. + * @retval None + */ +void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler) +{ + /* Check the parameters */ + assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler)); + + *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler; + +} + /** * @brief Enables or disables the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1067,11 +1439,14 @@ void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock @@ -1137,6 +1512,7 @@ void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) * using it. * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. * This parameter must be: RCC_AHB3Periph_FSMC + * or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1187,6 +1563,8 @@ void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) * @arg RCC_APB1Periph_CAN2: CAN2 clock * @arg RCC_APB1Periph_PWR: PWR clock * @arg RCC_APB1Periph_DAC: DAC clock + * @arg RCC_APB1Periph_UART7: UART7 clock + * @arg RCC_APB1Periph_UART8: UART8 clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1223,10 +1601,15 @@ void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) * @arg RCC_APB2Periph_ADC3: ADC3 clock * @arg RCC_APB2Periph_SDIO: SDIO clock * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SPI4: SPI4 clock * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock * @arg RCC_APB2Periph_TIM9: TIM9 clock * @arg RCC_APB2Periph_TIM10: TIM10 clock * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @arg RCC_APB2Periph_SPI5: SPI5 clock + * @arg RCC_APB2Periph_SPI6: SPI6 clock + * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) + * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1260,9 +1643,12 @@ void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices) * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock * @@ -1319,6 +1705,7 @@ void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) * @brief Forces or releases AHB3 peripheral reset. * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. * This parameter must be: RCC_AHB3Periph_FSMC + * or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1366,6 +1753,8 @@ void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) * @arg RCC_APB1Periph_CAN2: CAN2 clock * @arg RCC_APB1Periph_PWR: PWR clock * @arg RCC_APB1Periph_DAC: DAC clock + * @arg RCC_APB1Periph_UART7: UART7 clock + * @arg RCC_APB1Periph_UART8: UART8 clock * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1398,10 +1787,15 @@ void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) * @arg RCC_APB2Periph_ADC3: ADC3 clock * @arg RCC_APB2Periph_SDIO: SDIO clock * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SPI4: SPI4 clock * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock * @arg RCC_APB2Periph_TIM9: TIM9 clock * @arg RCC_APB2Periph_TIM10: TIM10 clock * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @arg RCC_APB2Periph_SPI5: SPI5 clock + * @arg RCC_APB2Periph_SPI6: SPI6 clock + * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) + * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1438,10 +1832,13 @@ void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) + * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock @@ -1507,6 +1904,7 @@ void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewSt * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. * This parameter must be: RCC_AHB3Periph_FSMC + * or RCC_AHB3Periph_FMC (STM32F429x/439x devices) * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1557,6 +1955,8 @@ void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewSt * @arg RCC_APB1Periph_CAN2: CAN2 clock * @arg RCC_APB1Periph_PWR: PWR clock * @arg RCC_APB1Periph_DAC: DAC clock + * @arg RCC_APB1Periph_UART7: UART7 clock + * @arg RCC_APB1Periph_UART8: UART8 clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1593,10 +1993,15 @@ void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewSt * @arg RCC_APB2Periph_ADC3: ADC3 clock * @arg RCC_APB2Periph_SDIO: SDIO clock * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SPI4: SPI4 clock * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock * @arg RCC_APB2Periph_TIM9: TIM9 clock * @arg RCC_APB2Periph_TIM10: TIM10 clock * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @arg RCC_APB2Periph_SPI5: SPI5 clock + * @arg RCC_APB2Periph_SPI6: SPI6 clock + * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) + * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1625,7 +2030,7 @@ void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewSt * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim @@ -1641,7 +2046,8 @@ void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewSt * @arg RCC_IT_HSIRDY: HSI ready interrupt * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices) * @param NewState: new state of the specified RCC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1671,6 +2077,7 @@ void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready * @arg RCC_FLAG_PLLRDY: main PLL clock ready * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready + * @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx devices) * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset @@ -1742,7 +2149,8 @@ void RCC_ClearFlag(void) * @arg RCC_IT_HSIRDY: HSI ready interrupt * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx devices) * @arg RCC_IT_CSS: Clock Security System interrupt * @retval The new state of RCC_IT (SET or RESET). */ @@ -1776,6 +2184,7 @@ ITStatus RCC_GetITStatus(uint8_t RCC_IT) * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: main PLL ready interrupt * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices) * @arg RCC_IT_CSS: Clock Security System interrupt * @retval None */ @@ -1805,4 +2214,4 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c index 9f0ba059f8..ee13e9fd07 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c @@ -2,48 +2,53 @@ ****************************************************************************** * @file stm32f4xx_rng.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 - * @brief This file provides firmware functions to manage the following + * @version V1.3.0 + * @date 08-November-2013 + * @brief This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: - * - Initialization and Configuration - * - Get 32 bit Random number - * - Interrupts and flags management + * + Initialization and Configuration + * + Get 32 bit Random number + * + Interrupts and flags management * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The RNG controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. - * - * 2. Activate the RNG peripheral using RNG_Cmd() function. - * - * 3. Wait until the 32 bit Random number Generator contains a valid - * random data (using polling/interrupt mode). For more details, - * refer to "Interrupts and flags management functions" module - * description. - * - * 4. Get the 32 bit Random number using RNG_GetRandomNumber() function - * - * 5. To get another 32 bit Random number, go to step 3. - * - * - * - * @endverbatim +@verbatim + + =================================================================== + ##### How to use this driver ##### + =================================================================== + [..] + (#) Enable The RNG controller clock using + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. + + (#) Activate the RNG peripheral using RNG_Cmd() function. + + (#) Wait until the 32 bit Random number Generator contains a valid random data + (using polling/interrupt mode). For more details, refer to "Interrupts and + flags management functions" module description. + + (#) Get the 32 bit Random number using RNG_GetRandomNumber() function + + (#) To get another 32 bit Random number, go to step 3. + + +@endverbatim * ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -76,18 +81,18 @@ * @verbatim =============================================================================== - Initialization and Configuration functions + ##### Initialization and Configuration functions ##### =============================================================================== - This section provides functions allowing to - - Initialize the RNG peripheral - - Enable or disable the RNG peripheral + [..] This section provides functions allowing to + (+) Initialize the RNG peripheral + (+) Enable or disable the RNG peripheral @endverbatim * @{ */ /** - * @brief Deinitializes the RNG peripheral registers to their default reset values. + * @brief De-initializes the RNG peripheral registers to their default reset values. * @param None * @retval None */ @@ -132,12 +137,12 @@ void RNG_Cmd(FunctionalState NewState) @verbatim =============================================================================== - Get 32 bit Random number function + ##### Get 32 bit Random number function ##### =============================================================================== - This section provides a function allowing to get the 32 bit Random number + [..] This section provides a function allowing to get the 32 bit Random number - @note Before to call this function you have to wait till DRDY flag is set, - using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. + (@) Before to call this function you have to wait till DRDY flag is set, + using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. @endverbatim * @{ @@ -184,69 +189,63 @@ uint32_t RNG_GetRandomNumber(void) * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== - This section provides functions allowing to configure the RNG Interrupts and - to get the status and clear flags and Interrupts pending bits. + [..] This section provides functions allowing to configure the RNG Interrupts and + to get the status and clear flags and Interrupts pending bits. - The RNG provides 3 Interrupts sources and 3 Flags: + [..] The RNG provides 3 Interrupts sources and 3 Flags: - Flags : - ---------- - 1. RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid - random data. it is cleared by reading the valid data - (using RNG_GetRandomNumber() function). - - 2. RNG_FLAG_CECS : In the case of a seed error detection. + *** Flags : *** + =============== + [..] + (#) RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid + random data. it is cleared by reading the valid data(using + RNG_GetRandomNumber() function). + + (#) RNG_FLAG_CECS : In the case of a seed error detection. - 3. RNG_FLAG_SECS : In the case of a clock error detection. + (#) RNG_FLAG_SECS : In the case of a clock error detection. - - Interrupts : - ------------ - if enabled, an RNG interrupt is pending : + *** Interrupts *** + ================== + [..] If enabled, an RNG interrupt is pending : - 1. In the case of the RNG_DR register contains valid random data. + (#) In the case of the RNG_DR register contains valid random data. This interrupt source is cleared once the RNG_DR register has been read (using RNG_GetRandomNumber() function) until a new valid value is - computed. - - or - 2. In the case of a seed error : One of the following faulty sequences has - been detected: - - More than 64 consecutive bits at the same value (0 or 1) - - More than 32 consecutive alternance of 0 and 1 (0101010101...01) - This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) - function. - - or - 3. In the case of a clock error : the PLL48CLK (RNG peripheral clock source) - was not correctly detected (fPLL48CLK< fHCLK/16). - This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI) - function. - @note In this case, User have to check that the clock controller is - correctly configured to provide the RNG clock. - - Managing the RNG controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the RNG controller events: Polling mode or Interrupt mode. + computed; or + (#) In the case of a seed error : One of the following faulty sequences has + been detected: + (++) More than 64 consecutive bits at the same value (0 or 1) + (++) More than 32 consecutive alternance of 0 and 1 (0101010101...01) + This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) + function; or + (#) In the case of a clock error : the PLL48CLK (RNG peripheral clock source) + was not correctly detected (fPLL48CLK< fHCLK/16). This interrupt source is + cleared using RNG_ClearITPendingBit(RNG_IT_CEI) function. + -@- note In this case, User have to check that the clock controller is + correctly configured to provide the RNG clock. + + *** Managing the RNG controller events : *** + ============================================ + [..] The user should identify which mode will be used in his application to manage + the RNG controller events: Polling mode or Interrupt mode. - 1. In the Polling Mode it is advised to use the following functions: - - RNG_GetFlagStatus() : to check if flags events occur. - - RNG_ClearFlag() : to clear the flags events. + (#) In the Polling Mode it is advised to use the following functions: + (++) RNG_GetFlagStatus() : to check if flags events occur. + (++) RNG_ClearFlag() : to clear the flags events. - @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only - by reading the Random number data. + -@@- RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only + by reading the Random number data. - 2. In the Interrupt Mode it is advised to use the following functions: - - RNG_ITConfig() : to enable or disable the interrupt source. - - RNG_GetITStatus() : to check if Interrupt occurs. - - RNG_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). + (#) In the Interrupt Mode it is advised to use the following functions: + (++) RNG_ITConfig() : to enable or disable the interrupt source. + (++) RNG_GetITStatus() : to check if Interrupt occurs. + (++) RNG_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). - @endverbatim * @{ */ @@ -390,10 +389,9 @@ void RNG_ClearITPendingBit(uint8_t RNG_IT) * @} */ - /** * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c index 159f0f37bb..05d2a1d1c7 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c @@ -2,280 +2,287 @@ ****************************************************************************** * @file stm32f4xx_rtc.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Real-Time Clock (RTC) peripheral: - * - Initialization - * - Calendar (Time and Date) configuration - * - Alarms (Alarm A and Alarm B) configuration - * - WakeUp Timer configuration - * - Daylight Saving configuration - * - Output pin Configuration - * - Coarse digital Calibration configuration - * - Smooth digital Calibration configuration - * - TimeStamp configuration - * - Tampers configuration - * - Backup Data Registers configuration - * - Shift control synchronisation - * - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - * - Interrupts and flags management + * + Initialization + * + Calendar (Time and Date) configuration + * + Alarms (Alarm A and Alarm B) configuration + * + WakeUp Timer configuration + * + Daylight Saving configuration + * + Output pin Configuration + * + Coarse digital Calibration configuration + * + Smooth digital Calibration configuration + * + TimeStamp configuration + * + Tampers configuration + * + Backup Data Registers configuration + * + Shift control synchronisation + * + RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration + * + Interrupts and flags management * - * @verbatim - * - * =================================================================== - * Backup Domain Operating Condition - * =================================================================== - * The real-time clock (RTC), the RTC backup registers, and the backup - * SRAM (BKP SRAM) can be powered from the VBAT voltage when the main - * VDD supply is powered off. - * To retain the content of the RTC backup registers, backup SRAM, - * and supply the RTC when VDD is turned off, VBAT pin can be connected - * to an optional standby voltage supplied by a battery or by another - * source. - * - * To allow the RTC to operate even when the main digital supply (VDD) - * is turned off, the VBAT pin powers the following blocks: - * 1 - The RTC - * 2 - The LSE oscillator - * 3 - The backup SRAM when the low power backup regulator is enabled - * 4 - PC13 to PC15 I/Os, plus PI8 I/O (when available) - * - * When the backup domain is supplied by VDD (analog switch connected - * to VDD), the following functions are available: - * 1 - PC14 and PC15 can be used as either GPIO or LSE pins - * 2 - PC13 can be used as a GPIO or as the RTC_AF1 pin - * 3 - PI8 can be used as a GPIO or as the RTC_AF2 pin - * - * When the backup domain is supplied by VBAT (analog switch connected - * to VBAT because VDD is not present), the following functions are available: - * 1 - PC14 and PC15 can be used as LSE pins only - * 2 - PC13 can be used as the RTC_AF1 pin - * 3 - PI8 can be used as the RTC_AF2 pin - * - * =================================================================== - * Backup Domain Reset - * =================================================================== - * The backup domain reset sets all RTC registers and the RCC_BDCR - * register to their reset values. The BKPSRAM is not affected by this - * reset. The only way of resetting the BKPSRAM is through the Flash - * interface by requesting a protection level change from 1 to 0. - * A backup domain reset is generated when one of the following events - * occurs: - * 1 - Software reset, triggered by setting the BDRST bit in the - * RCC Backup domain control register (RCC_BDCR). You can use the - * RCC_BackupResetCmd(). - * 2 - VDD or VBAT power on, if both supplies have previously been - * powered off. - * - * =================================================================== - * Backup Domain Access - * =================================================================== - * After reset, the backup domain (RTC registers, RTC backup data - * registers and backup SRAM) is protected against possible unwanted - * write accesses. - * To enable access to the RTC Domain and RTC registers, proceed as follows: - * - Enable the Power Controller (PWR) APB1 interface clock using the - * RCC_APB1PeriphClockCmd() function. - * - Enable access to RTC domain using the PWR_BackupAccessCmd() function. - * - Select the RTC clock source using the RCC_RTCCLKConfig() function. - * - Enable RTC Clock using the RCC_RTCCLKCmd() function. - * - * =================================================================== - * RTC Driver: how to use it - * =================================================================== - * - Enable the RTC domain access (see description in the section above) - * - Configure the RTC Prescaler (Asynchronous and Synchronous) and - * RTC hour format using the RTC_Init() function. - * - * Time and Date configuration - * =========================== - * - To configure the RTC Calendar (Time and Date) use the RTC_SetTime() - * and RTC_SetDate() functions. - * - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() - * functions. - * - Use the RTC_DayLightSavingConfig() function to add or sub one - * hour to the RTC Calendar. - * - * Alarm configuration - * =================== - * - To configure the RTC Alarm use the RTC_SetAlarm() function. - * - Enable the selected RTC Alarm using the RTC_AlarmCmd() function - * - To read the RTC Alarm, use the RTC_GetAlarm() function. - * - To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function. - * - * RTC Wakeup configuration - * ======================== - * - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() - * function. - * - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() - * function - * - Enable the RTC WakeUp using the RTC_WakeUpCmd() function - * - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() - * function. - * - * Outputs configuration - * ===================== - * The RTC has 2 different outputs: - * - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B - * and WaKeUp signals. - * To output the selected RTC signal on RTC_AF1 pin, use the - * RTC_OutputConfig() function. - * - AFO_CALIB: this output is 512Hz signal or 1Hz . - * To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd() - * function. - * - * Smooth digital Calibration configuration - * ================================= - * - Configure the RTC Original Digital Calibration Value and the corresponding - * calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() - * function. - * - * Coarse digital Calibration configuration - * ================================= - * - Configure the RTC Coarse Calibration Value and the corresponding - * sign using the RTC_CoarseCalibConfig() function. - * - Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() - * function - * - * TimeStamp configuration - * ======================= - * - Configure the RTC_AF1 trigger and enables the RTC TimeStamp - * using the RTC_TimeStampCmd() function. - * - To read the RTC TimeStamp Time and Date register, use the - * RTC_GetTimeStamp() function. - * - To read the RTC TimeStamp SubSecond register, use the - * RTC_GetTimeStampSubSecond() function. - * - The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) - * or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in - * RTC_TAFCR register. You can use the RTC_TamperPinSelection() - * function to select the corresponding pin. - * - * Tamper configuration - * ==================== - * - Enable the RTC Tamper using the RTC_TamperCmd() function. - * - Configure the Tamper filter count using RTC_TamperFilterConfig() - * function. - * - Configure the RTC Tamper trigger Edge or Level according to the Tamper - * filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function. - * - Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig() - * function. - * - Configure the Tamper precharge or discharge duration using - * RTC_TamperPinsPrechargeDuration() function. - * - Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function. - * - Enable the Time stamp on Tamper detection event using - * RTC_TSOnTamperDetecCmd() function. - * - The TIMESTAMP alternate function can be mapped to either RTC_AF1 - * or RTC_AF2 depending on the value of the TSINSEL bit in the - * RTC_TAFCR register. You can use the RTC_TimeStampPinSelection() - * function to select the corresponding pin. - * - * Backup Data Registers configuration - * =================================== - * - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() - * function. - * - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() - * function. - * - * =================================================================== - * RTC and low power modes - * =================================================================== - * The MCU can be woken up from a low power mode by an RTC alternate - * function. - * The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - * RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - * These RTC alternate functions can wake up the system from the Stop - * and Standby lowpower modes. - * The system can also wake up from low power modes without depending - * on an external interrupt (Auto-wakeup mode), by using the RTC alarm - * or the RTC wakeup events. - * The RTC provides a programmable time base for waking up from the - * Stop or Standby mode at regular intervals. - * Wakeup from STOP and Standby modes is possible only when the RTC - * clock source is LSE or LSI. - * - * =================================================================== - * Selection of RTC_AF1 alternate functions - * =================================================================== - * The RTC_AF1 pin (PC13) can be used for the following purposes: - * - AFO_ALARM output - * - AFO_CALIB output - * - AFI_TAMPER - * - AFI_TIMESTAMP - * - * +-------------------------------------------------------------------------------------------------------------+ - * | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - * | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - * | and function | | | | | selection | selection |Configuration | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Alarm out | | | | | Don't | Don't | | - * | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Alarm out | | | | | Don't | Don't | | - * | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Calibration out | | | | | Don't | Don't | | - * | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | TAMPER input | | | | | | Don't | | - * | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP and | | | | | | | | - * | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care | - * | floating | | | | | | | | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP input | | | | | Don't | | | - * | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care | - * +-------------------------------------------------------------------------------------------------------------+ - * - * - * =================================================================== - * Selection of RTC_AF2 alternate functions - * =================================================================== - * The RTC_AF2 pin (PI8) can be used for the following purposes: - * - AFI_TAMPER - * - AFI_TIMESTAMP +@verbatim + + =================================================================== + ##### Backup Domain Operating Condition ##### + =================================================================== + [..] The real-time clock (RTC), the RTC backup registers, and the backup + SRAM (BKP SRAM) can be powered from the VBAT voltage when the main + VDD supply is powered off. + To retain the content of the RTC backup registers, backup SRAM, and supply + the RTC when VDD is turned off, VBAT pin can be connected to an optional + standby voltage supplied by a battery or by another source. + + [..] To allow the RTC to operate even when the main digital supply (VDD) is turned + off, the VBAT pin powers the following blocks: + (#) The RTC + (#) The LSE oscillator + (#) The backup SRAM when the low power backup regulator is enabled + (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) + + [..] When the backup domain is supplied by VDD (analog switch connected to VDD), + the following functions are available: + (#) PC14 and PC15 can be used as either GPIO or LSE pins + (#) PC13 can be used as a GPIO or as the RTC_AF1 pin + (#) PI8 can be used as a GPIO or as the RTC_AF2 pin + + [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT + because VDD is not present), the following functions are available: + (#) PC14 and PC15 can be used as LSE pins only + (#) PC13 can be used as the RTC_AF1 pin + (#) PI8 can be used as the RTC_AF2 pin + + + ##### Backup Domain Reset ##### + =================================================================== + [..] The backup domain reset sets all RTC registers and the RCC_BDCR register + to their reset values. The BKPSRAM is not affected by this reset. The only + way of resetting the BKPSRAM is through the Flash interface by requesting + a protection level change from 1 to 0. + [..] A backup domain reset is generated when one of the following events occurs: + (#) Software reset, triggered by setting the BDRST bit in the + RCC Backup domain control register (RCC_BDCR). You can use the + RCC_BackupResetCmd(). + (#) VDD or VBAT power on, if both supplies have previously been powered off. + + + ##### Backup Domain Access ##### + =================================================================== + [..] After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted write + accesses. + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + RCC_APB1PeriphClockCmd() function. + (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function. + (+) Select the RTC clock source using the RCC_RTCCLKConfig() function. + (+) Enable RTC Clock using the RCC_RTCCLKCmd() function. + + + ##### How to use RTC Driver ##### + =================================================================== + [..] + (+) Enable the RTC domain access (see description in the section above) + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the RTC_Init() function. + + *** Time and Date configuration *** + =================================== + [..] + (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime() + and RTC_SetDate() functions. + (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() functions. + (+) Use the RTC_DayLightSavingConfig() function to add or sub one + hour to the RTC Calendar. + + *** Alarm configuration *** + =========================== + [..] + (+) To configure the RTC Alarm use the RTC_SetAlarm() function. + (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function + (+) To read the RTC Alarm, use the RTC_GetAlarm() function. + (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function. + + *** RTC Wakeup configuration *** + ================================ + [..] + (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() + function. + (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() function + (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function + (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() + function. + + *** Outputs configuration *** + ============================= + [..] The RTC has 2 different outputs: + (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B + and WaKeUp signals. To output the selected RTC signal on RTC_AF1 pin, use the + RTC_OutputConfig() function. + (+) AFO_CALIB: this output is 512Hz signal or 1Hz. To output the RTC Clock on + RTC_AF1 pin, use the RTC_CalibOutputCmd() function. + + *** Smooth digital Calibration configuration *** + ================================================ + [..] + (+) Configure the RTC Original Digital Calibration Value and the corresponding + calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() + function. + + *** Coarse digital Calibration configuration *** + ================================================ + [..] + (+) Configure the RTC Coarse Calibration Value and the corresponding + sign using the RTC_CoarseCalibConfig() function. + (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() function + + *** TimeStamp configuration *** + =============================== + [..] + (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp using the RTC + _TimeStampCmd() function. + (+) To read the RTC TimeStamp Time and Date register, use the RTC_GetTimeStamp() + function. + (+) To read the RTC TimeStamp SubSecond register, use the + RTC_GetTimeStampSubSecond() function. + (+) The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) + or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in + RTC_TAFCR register. You can use the RTC_TamperPinSelection() function to + select the corresponding pin. + + *** Tamper configuration *** + ============================ + [..] + (+) Enable the RTC Tamper using the RTC_TamperCmd() function. + (+) Configure the Tamper filter count using RTC_TamperFilterConfig() + function. + (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper + filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() + function. + (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig() + function. + (+) Configure the Tamper precharge or discharge duration using + RTC_TamperPinsPrechargeDuration() function. + (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function. + (+) Enable the Time stamp on Tamper detection event using + TC_TSOnTamperDetecCmd() function. + (+) The TIMESTAMP alternate function can be mapped to either RTC_AF1 + or RTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR + register. You can use the RTC_TimeStampPinSelection() function to select + the corresponding pin. + + *** Backup Data Registers configuration *** + =========================================== + [..] + (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() + function. + (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() + function. + + + ##### RTC and low power modes ##### + =================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate + function. + [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + RTC wakeup, RTC tamper event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby lowpower modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wakeup mode), by using the RTC alarm + or the RTC wakeup events. + [..] The RTC provides a programmable time base for waking up from the + Stop or Standby mode at regular intervals. + Wakeup from STOP and Standby modes is possible only when the RTC clock source + is LSE or LSI. + + + ##### Selection of RTC_AF1 alternate functions ##### + =================================================================== + [..] The RTC_AF1 pin (PC13) can be used for the following purposes: + (+) AFO_ALARM output + (+) AFO_CALIB output + (+) AFI_TAMPER + (+) AFI_TIMESTAMP + + [..] + +-------------------------------------------------------------------------------------------------------------+ + | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | + | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | + | and function | | | | | selection | selection |Configuration | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | Alarm out | | | | | Don't | Don't | | + | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | Alarm out | | | | | Don't | Don't | | + | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | Calibration out | | | | | Don't | Don't | | + | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | TAMPER input | | | | | | Don't | | + | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | TIMESTAMP and | | | | | | | | + | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care | + | floating | | | | | | | | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | TIMESTAMP input | | | | | Don't | | | + | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care | + |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care | + +-------------------------------------------------------------------------------------------------------------+ + + + ##### Selection of RTC_AF2 alternate functions ##### + =================================================================== + [..] The RTC_AF2 pin (PI8) can be used for the following purposes: + (+) AFI_TAMPER + (+) AFI_TIMESTAMP + [..] + +---------------------------------------------------------------------------------------+ + | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | + | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | + | and function | | | selection | selection |Configuration | + |-----------------|-----------|--------------|------------|--------------|--------------| + | TAMPER input | | | | Don't | | + | floating | 1 | 0 | 1 | care | Don't care | + |-----------------|-----------|--------------|------------|--------------|--------------| + | TIMESTAMP and | | | | | | + | TAMPER input | 1 | 1 | 1 | 1 | Don't care | + | floating | | | | | | + |-----------------|-----------|--------------|------------|--------------|--------------| + | TIMESTAMP input | | | Don't | | | + | floating | 0 | 1 | care | 1 | Don't care | + |-----------------|-----------|--------------|------------|--------------|--------------| + | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care | + +---------------------------------------------------------------------------------------+ + + +@endverbatim + + ****************************************************************************** + * @attention * - * +---------------------------------------------------------------------------------------+ - * | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - * | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - * | and function | | | selection | selection |Configuration | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | TAMPER input | | | | Don't | | - * | floating | 1 | 0 | 1 | care | Don't care | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP and | | | | | | - * | TAMPER input | 1 | 1 | 1 | 1 | Don't care | - * | floating | | | | | | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP input | | | Don't | | | - * | floating | 0 | 1 | care | 1 | Don't care | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care | - * +---------------------------------------------------------------------------------------+ - * + *

    © COPYRIGHT 2013 STMicroelectronics

    * - * @endverbatim + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_rtc.h" -#include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ @@ -297,7 +304,8 @@ #define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ - RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F )) + RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \ + RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) #define INITMODE_TIMEOUT ((uint32_t) 0x00010000) #define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000) @@ -321,35 +329,35 @@ static uint8_t RTC_Bcd2ToByte(uint8_t Value); * @verbatim =============================================================================== - Initialization and Configuration functions + ##### Initialization and Configuration functions ##### =============================================================================== - - This section provide functions allowing to initialize and configure the RTC - Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers - Write protection, enter and exit the RTC initialization mode, RTC registers - synchronization check and reference clock detection enable. - - 1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is - split into 2 programmable prescalers to minimize power consumption. - - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. - - When both prescalers are used, it is recommended to configure the asynchronous - prescaler to a high value to minimize consumption. - - 2. All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - - 3. To Configure the RTC Calendar, user application should enter initialization - mode. In this mode, the calendar counter is stopped and its value can be - updated. When the initialization sequence is complete, the calendar restarts - counting after 4 RTCCLK cycles. - - 4. To read the calendar through the shadow registers after Calendar initialization, - calendar update or after wakeup from low power modes the software must first - clear the RSF flag. The software must then wait until it is set again before - reading the calendar, which means that the calendar registers have been - correctly copied into the RTC_TR and RTC_DR shadow registers. - The RTC_WaitForSynchro() function implements the above software sequence - (RSF clear and RSF check). + + [..] This section provide functions allowing to initialize and configure the RTC + Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers + Write protection, enter and exit the RTC initialization mode, RTC registers + synchronization check and reference clock detection enable. + + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is + split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize consumption. + + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WPR. + + (#) To Configure the RTC Calendar, user application should enter initialization + mode. In this mode, the calendar counter is stopped and its value can be + updated. When the initialization sequence is complete, the calendar restarts + counting after 4 RTCCLK cycles. + + (#) To read the calendar through the shadow registers after Calendar initialization, + calendar update or after wakeup from low power modes the software must first + clear the RSF flag. The software must then wait until it is set again before + reading the calendar, which means that the calendar registers have been + correctly copied into the RTC_TR and RTC_DR shadow registers. + The RTC_WaitForSynchro() function implements the above software sequence + (RSF clear and RSF check). @endverbatim * @{ @@ -407,6 +415,10 @@ ErrorStatus RTC_DeInit(void) RTC->CALIBR = (uint32_t)0x00000000; RTC->ALRMAR = (uint32_t)0x00000000; RTC->ALRMBR = (uint32_t)0x00000000; + RTC->SHIFTR = (uint32_t)0x00000000; + RTC->CALR = (uint32_t)0x00000000; + RTC->ALRMASSR = (uint32_t)0x00000000; + RTC->ALRMBSSR = (uint32_t)0x00000000; /* Reset ISR register and exit initialization mode */ RTC->ISR = (uint32_t)0x00000000; @@ -728,11 +740,11 @@ void RTC_BypassShadowCmd(FunctionalState NewState) * @verbatim =============================================================================== - Time and Date configuration functions + ##### Time and Date configuration functions ##### =============================================================================== - - This section provide functions allowing to program and read the RTC Calendar - (Time and Date). + + [..] This section provide functions allowing to program and read the RTC Calendar + (Time and Date). @endverbatim * @{ @@ -823,6 +835,9 @@ ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) /* Exit Initialization mode */ RTC_ExitInitMode(); + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) + { if(RTC_WaitForSynchro() == ERROR) { status = ERROR; @@ -831,7 +846,11 @@ ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) { status = SUCCESS; } - + } + else + { + status = SUCCESS; + } } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; @@ -892,17 +911,17 @@ void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) } /** - * @brief Gets the RTC current Calendar Subseconds value. + * @brief Gets the RTC current Calendar Sub seconds value. * @note This function freeze the Time and Date registers after reading the * SSR register. * @param None - * @retval RTC current Calendar Subseconds value. + * @retval RTC current Calendar Sub seconds value. */ uint32_t RTC_GetSubSecond(void) { uint32_t tmpreg = 0; - /* Get subseconds values from the correspondent registers*/ + /* Get sub seconds values from the correspondent registers*/ tmpreg = (uint32_t)(RTC->SSR); /* Read DR register to unfroze calendar registers */ @@ -984,6 +1003,9 @@ ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) /* Exit Initialization mode */ RTC_ExitInitMode(); + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) + { if(RTC_WaitForSynchro() == ERROR) { status = ERROR; @@ -992,6 +1014,11 @@ ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) { status = SUCCESS; } + } + else + { + status = SUCCESS; + } } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; @@ -1060,10 +1087,10 @@ void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) * @verbatim =============================================================================== - Alarms (Alarm A and Alarm B) configuration functions + ##### Alarms A and B configuration functions ##### =============================================================================== - - This section provide functions allowing to program and read the RTC Alarms. + + [..] This section provide functions allowing to program and read the RTC Alarms. @endverbatim * @{ @@ -1330,15 +1357,15 @@ ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) } /** - * @brief Configure the RTC AlarmA/B Subseconds value and mask.* + * @brief Configure the RTC AlarmA/B Sub seconds value and mask.* * @note This function is performed only when the Alarm is disabled. * @param RTC_Alarm: specifies the alarm to be configured. * This parameter can be one of the following values: * @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmSubSecondValue: specifies the Subseconds value. + * @param RTC_AlarmSubSecondValue: specifies the Sub seconds value. * This parameter can be a value from 0 to 0x00007FFF. - * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask. + * @param RTC_AlarmSubSecondMask: specifies the Sub seconds Mask. * This parameter can be any combination of the following values: * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked. * There is no comparison on sub seconds for Alarm. @@ -1387,17 +1414,17 @@ void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondVal RTC->WPR = 0xCA; RTC->WPR = 0x53; - /* Configure the Alarm A or Alarm B SubSecond registers */ + /* Configure the Alarm A or Alarm B Sub Second registers */ tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); if (RTC_Alarm == RTC_Alarm_A) { - /* Configure the AlarmA SubSecond register */ + /* Configure the Alarm A Sub Second register */ RTC->ALRMASSR = tmpreg; } else { - /* Configure the Alarm B SubSecond register */ + /* Configure the Alarm B Sub Second register */ RTC->ALRMBSSR = tmpreg; } @@ -1407,13 +1434,13 @@ void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondVal } /** - * @brief Gets the RTC Alarm Subseconds value. + * @brief Gets the RTC Alarm Sub seconds value. * @param RTC_Alarm: specifies the alarm to be read. * This parameter can be one of the following values: * @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_B: to select Alarm B * @param None - * @retval RTC Alarm Subseconds value. + * @retval RTC Alarm Sub seconds value. */ uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) { @@ -1441,10 +1468,10 @@ uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) * @verbatim =============================================================================== - WakeUp Timer configuration functions + ##### WakeUp Timer configuration functions ##### =============================================================================== - This section provide functions allowing to program and read the RTC WakeUp. + [..] This section provide functions allowing to program and read the RTC WakeUp. @endverbatim * @{ @@ -1579,10 +1606,10 @@ ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) * @verbatim =============================================================================== - Daylight Saving configuration functions + ##### Daylight Saving configuration functions ##### =============================================================================== - This section provide functions allowing to configure the RTC DayLight Saving. + [..] This section provide functions allowing to configure the RTC DayLight Saving. @endverbatim * @{ @@ -1642,10 +1669,10 @@ uint32_t RTC_GetStoreOperation(void) * @verbatim =============================================================================== - Output pin Configuration function + ##### Output pin Configuration function ##### =============================================================================== - This section provide functions allowing to configure the RTC Output source. + [..] This section provide functions allowing to configure the RTC Output source. @endverbatim * @{ @@ -1696,7 +1723,7 @@ void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) * @verbatim =============================================================================== - Digital Calibration configuration functions + ##### Digital Calibration configuration functions ##### =============================================================================== @endverbatim @@ -1849,7 +1876,7 @@ void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) RTC->WPR = 0xCA; RTC->WPR = 0x53; - /*clear flags before config*/ + /*clear flags before configuration */ RTC->CR &= (uint32_t)~(RTC_CR_COSEL); /* Configure the RTC_CR register */ @@ -1863,9 +1890,9 @@ void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) * @brief Configures the Smooth Calibration Settings. * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period. * This parameter can be can be one of the following values: - * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration periode is 32s. - * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration periode is 16s. - * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion periode is 8s. + * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration period is 32s. + * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration period is 16s. + * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion period is 8s. * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit. * This parameter can be one of the following values: * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses. @@ -1931,7 +1958,7 @@ ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, * @verbatim =============================================================================== - TimeStamp configuration functions + ##### TimeStamp configuration functions ##### =============================================================================== @endverbatim @@ -2036,13 +2063,13 @@ void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, } /** - * @brief Get the RTC timestamp Subseconds value. + * @brief Get the RTC timestamp Sub seconds value. * @param None - * @retval RTC current timestamp Subseconds value. + * @retval RTC current timestamp Sub seconds value. */ uint32_t RTC_GetTimeStampSubSecond(void) { - /* Get timestamp subseconds values from the correspondent registers */ + /* Get timestamp sub seconds values from the correspondent registers */ return (uint32_t)(RTC->TSSSR); } @@ -2055,7 +2082,7 @@ uint32_t RTC_GetTimeStampSubSecond(void) * @verbatim =============================================================================== - Tampers configuration functions + ##### Tampers configuration functions ##### =============================================================================== @endverbatim @@ -2183,10 +2210,10 @@ void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input * Precharge Duration. * This parameter can be one of the following values: - * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle + * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are precharged before sampling during 1 RTCCLK cycle + * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are precharged before sampling during 2 RTCCLK cycle + * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are precharged before sampling during 4 RTCCLK cycle + * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are precharged before sampling during 8 RTCCLK cycle * @retval None */ void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) @@ -2258,7 +2285,7 @@ void RTC_TamperPullUpCmd(FunctionalState NewState) * @verbatim =============================================================================== - Backup Data Registers configuration functions + ##### Backup Data Registers configuration functions ##### =============================================================================== @endverbatim @@ -2317,10 +2344,9 @@ uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) * configuration functions * @verbatim - =============================================================================== - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - functions - =============================================================================== + ================================================================================================== + ##### RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions ##### + ================================================================================================== @endverbatim * @{ @@ -2388,7 +2414,7 @@ void RTC_OutputTypeConfig(uint32_t RTC_OutputType) * @verbatim =============================================================================== - Shift control synchronisation functions + ##### Shift control synchronisation functions ##### =============================================================================== @endverbatim @@ -2474,41 +2500,42 @@ ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSu * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== - All RTC interrupts are connected to the EXTI controller. + [..] All RTC interrupts are connected to the EXTI controller. - - To enable the RTC Alarm interrupt, the following sequence is required: - - Configure and enable the EXTI Line 17 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using - the RTC_SetAlarm() and RTC_AlarmCmd() functions. - - - To enable the RTC Wakeup interrupt, the following sequence is required: - - Configure and enable the EXTI Line 22 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to generate the RTC wakeup timer event using the - RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - - To enable the RTC Tamper interrupt, the following sequence is required: - - Configure and enable the EXTI Line 21 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to detect the RTC tamper event using the - RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. - - - To enable the RTC TimeStamp interrupt, the following sequence is required: - - Configure and enable the EXTI Line 21 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to detect the RTC time-stamp event using the - RTC_TimeStampCmd() functions. + (+) To enable the RTC Alarm interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 17 in interrupt mode and select + the rising edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the + NVIC_Init() function. + (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using + the RTC_SetAlarm() and RTC_AlarmCmd() functions. + + (+) To enable the RTC Wakeup interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 22 in interrupt mode and select the + rising edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the + NVIC_Init() function. + (++) Configure the RTC to generate the RTC wakeup timer event using the + RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() + functions. + + (+) To enable the RTC Tamper interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 21 in interrupt mode and select + the rising edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the + NVIC_Init() function. + (++) Configure the RTC to detect the RTC tamper event using the + RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. + + (+) To enable the RTC TimeStamp interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 21 in interrupt mode and select the + rising edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the + NVIC_Init() function. + (++) Configure the RTC to detect the RTC time stamp event using the + RTC_TimeStampCmd() functions. @endverbatim * @{ @@ -2559,6 +2586,7 @@ void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) * @brief Checks whether the specified RTC flag is set or not. * @param RTC_FLAG: specifies the flag to check. * This parameter can be one of the following values: + * @arg RTC_FLAG_RECALPF: RECALPF event flag. * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag * @arg RTC_FLAG_TSF: Time Stamp event flag @@ -2568,6 +2596,7 @@ void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) * @arg RTC_FLAG_INITF: Initialization mode flag * @arg RTC_FLAG_RSF: Registers Synchronized flag * @arg RTC_FLAG_INITS: Registers Configured flag + * @arg RTC_FLAG_SHPF: Shift operation pending flag. * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag * @arg RTC_FLAG_ALRBWF: Alarm B Write flag * @arg RTC_FLAG_ALRAWF: Alarm A write flag @@ -2729,4 +2758,4 @@ static uint8_t RTC_Bcd2ToByte(uint8_t Value) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c new file mode 100644 index 0000000000..cb363a7e9f --- /dev/null +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c @@ -0,0 +1,1079 @@ +/** + ****************************************************************************** + * @file stm32f4xx_sai.c + * @author MCD Application Team + * @version V1.3.0 + * @date 08-November-2013 + * @brief This file provides firmware functions to manage the following + * functionalities of the Serial Audio Interface (SAI): + * + Initialization and Configuration + * + Data transfers functions + * + DMA transfers management + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + + (#) Enable peripheral clock using the following functions + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SAI1, ENABLE) for SAI1 + + (#) For each SAI Block A/B enable SCK, SD, FS and MCLK GPIO clocks + using RCC_AHB1PeriphClockCmd() function. + + (#) Peripherals alternate function: + (++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function. + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (++) Call GPIO_Init() function + -@@- If an external clock source is used then the I2S CKIN pin should be + also configured in Alternate function Push-pull pull-up mode. + + (#) The SAI clock can be generated from different clock source : + PLL I2S, PLL SAI or external clock source. + (++) The PLL I2S is configured using the following functions RCC_PLLI2SConfig(), + RCC_PLLI2SCmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY) and + RCC_SAIPLLI2SClkDivConfig() or; + + (++) The PLL SAI is configured using the following functions RCC_PLLSAIConfig(), + RCC_PLLSAICmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLSAIRDY) and + RCC_SAIPLLSAIClkDivConfig()or; + + (++) External clock source is configured using the function + RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the + define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. + + (#) Each SAI Block A or B has its own clock generator to make these two blocks + completely independent. The Clock generator is configured using RCC_SAIBlockACLKConfig() and + RCC_SAIBlockBCLKConfig() functions. + + (#) Each SAI Block A or B can be configured separetely : + (++) Program the Master clock divider, Audio mode, Protocol, Data Length, Clock Strobing Edge, + Synchronous mode, Output drive and FIFO Thresold using SAI_Init() function. + In case of master mode, program the Master clock divider (MCKDIV) using + the following formula : + (+++) MCLK_x = SAI_CK_x / (MCKDIV * 2) with MCLK_x = 256 * FS + (+++) FS = SAI_CK_x / (MCKDIV * 2) * 256 + (+++) MCKDIV = SAI_CK_x / FS * 512 + (++) Program the Frame Length, Frame active Length, FS Definition, FS Polarity, + FS Offset using SAI_FrameInit() function. + (++) Program the Slot First Bit Offset, Slot Size, Slot Number, Slot Active + using SAI_SlotInit() function. + + (#) Enable the NVIC and the corresponding interrupt using the function + SAI_ITConfig() if you need to use interrupt mode. + + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function + (++) Active the needed channel Request using SAI_DMACmd() function + + (#) Enable the SAI using the SAI_Cmd() function. + + (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. + + (#) The SAI has some specific functions which can be useful depending + on the audio protocol selected. + (++) Enable Mute mode when the audio block is a transmitter using SAI_MuteModeCmd() + function and configure the value transmitted during mute using SAI_MuteValueConfig(). + (++) Detect the Mute mode when audio block is a receiver using SAI_MuteFrameCounterConfig(). + (++) Enable the MONO mode without any data preprocessing in memory when the number + of slot is equal to 2 using SAI_MonoModeConfig() function. + (++) Enable data companding algorithm (U law and A law) using SAI_CompandingModeConfig(). + (++) Choose the behavior of the SD line in output when an inactive slot is sent + on the data line using SAI_TRIStateConfig() function. + [..] + (@) In master TX mode: enabling the audio block immediately generates the bit clock + for the external slaves even if there is no data in the FIFO, However FS signal + generation is conditioned by the presence of data in the FIFO. + + (@) In master RX mode: enabling the audio block immediately generates the bit clock + and FS signal for the external slaves. + + (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: + (+@) First bit Offset <= (SLOT size - Data size) + (+@) Data size <= SLOT size + (+@) Number of SLOT x SLOT size = Frame length + (+@) The number of slots should be even when bit FSDEF in the SAI_xFRCR is set. + + @endverbatim + + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_sai.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SAI + * @brief SAI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* *SAI registers Masks */ +#define CR1_CLEAR_MASK ((uint32_t)0xFF07C010) +#define FRCR_CLEAR_MASK ((uint32_t)0xFFF88000) +#define SLOTR_CLEAR_MASK ((uint32_t)0x0000F020) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SAI_Private_Functions + * @{ + */ + +/** @defgroup SAI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This section provides a set of functions allowing to initialize the SAI Audio + Block Mode, Audio Protocol, Data size, Synchronization between audio block, + Master clock Divider, Fifo threshold, Frame configuration, slot configuration, + Tristate mode, Companding mode and Mute mode. + [..] + The SAI_Init(), SAI_FrameInit() and SAI_SlotInit() functions follows the SAI Block + configuration procedures for Master mode and Slave mode (details for these procedures + are available in reference manual(RM0090). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the SAIx peripheral registers to their default reset values. + * @param SAIx: To select the SAIx peripheral, where x can be the different instances + * + * @retval None + */ +void SAI_DeInit(SAI_TypeDef* SAIx) +{ + /* Check the parameters */ + assert_param(IS_SAI_PERIPH(SAIx)); + + /* Enable SAI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, ENABLE); + /* Release SAI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, DISABLE); +} + +/** + * @brief Initializes the SAI Block x peripheral according to the specified + * parameters in the SAI_InitStruct. + * + * @note SAI clock is generated from a specific output of the PLLSAI or a specific + * output of the PLLI2S or from an alternate function bypassing the PLL I2S. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure that + * contains the configuration information for the specified SAI Block peripheral. + * @retval None + */ +void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* Check the SAI Block parameters */ + assert_param(IS_SAI_BLOCK_MODE(SAI_InitStruct->SAI_AudioMode)); + assert_param(IS_SAI_BLOCK_PROTOCOL(SAI_InitStruct->SAI_Protocol)); + assert_param(IS_SAI_BLOCK_DATASIZE(SAI_InitStruct->SAI_DataSize)); + assert_param(IS_SAI_BLOCK_FIRST_BIT(SAI_InitStruct->SAI_FirstBit)); + assert_param(IS_SAI_BLOCK_CLOCK_STROBING(SAI_InitStruct->SAI_ClockStrobing)); + assert_param(IS_SAI_BLOCK_SYNCHRO(SAI_InitStruct->SAI_Synchro)); + assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(SAI_InitStruct->SAI_OUTDRIV)); + assert_param(IS_SAI_BLOCK_NODIVIDER(SAI_InitStruct->SAI_NoDivider)); + assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(SAI_InitStruct->SAI_MasterDivider)); + assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(SAI_InitStruct->SAI_FIFOThreshold)); + + /* SAI Block_x CR1 Configuration */ + /* Get the SAI Block_x CR1 value */ + tmpreg = SAI_Block_x->CR1; + /* Clear MODE, PRTCFG, DS, LSBFIRST, CKSTR, SYNCEN, OUTDRIV, NODIV, and MCKDIV bits */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure SAI_Block_x: Audio mode, Protocol, Data Size, first transmitted bit, Clock strobing + edge, Synchronization mode, Output drive, Master Divider and FIFO level */ + /* Set MODE bits according to SAI_AudioMode value */ + /* Set PRTCFG bits according to SAI_Protocol value */ + /* Set DS bits according to SAI_DataSize value */ + /* Set LSBFIRST bit according to SAI_FirstBit value */ + /* Set CKSTR bit according to SAI_ClockStrobing value */ + /* Set SYNCEN bit according to SAI_Synchro value */ + /* Set OUTDRIV bit according to SAI_OUTDRIV value */ + /* Set NODIV bit according to SAI_NoDivider value */ + /* Set MCKDIV bits according to SAI_MasterDivider value */ + tmpreg |= (uint32_t)(SAI_InitStruct->SAI_AudioMode | SAI_InitStruct->SAI_Protocol | + SAI_InitStruct->SAI_DataSize | SAI_InitStruct->SAI_FirstBit | + SAI_InitStruct->SAI_ClockStrobing | SAI_InitStruct->SAI_Synchro | + SAI_InitStruct->SAI_OUTDRIV | SAI_InitStruct->SAI_NoDivider | + (uint32_t)((SAI_InitStruct->SAI_MasterDivider) << 20)); + /* Write to SAI_Block_x CR1 */ + SAI_Block_x->CR1 = tmpreg; + + /* SAI Block_x CR2 Configuration */ + /* Get the SAIBlock_x CR2 value */ + tmpreg = SAI_Block_x->CR2; + /* Clear FTH bits */ + tmpreg &= ~(SAI_xCR2_FTH); + /* Configure the FIFO Level */ + /* Set FTH bits according to SAI_FIFOThreshold value */ + tmpreg |= (uint32_t)(SAI_InitStruct->SAI_FIFOThreshold); + /* Write to SAI_Block_x CR2 */ + SAI_Block_x->CR2 = tmpreg; +} + +/** + * @brief Initializes the SAI Block Audio frame according to the specified + * parameters in the SAI_FrameInitStruct. + * + * @note this function has no meaning if the AC'97 or SPDIF audio protocol + * are selected. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_FrameInitStruct: pointer to an SAI_FrameInitTypeDef structure that + * contains the configuration of audio frame for a specified SAI Block + * @retval None + */ +void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* Check the SAI Block frame parameters */ + assert_param(IS_SAI_BLOCK_FRAME_LENGTH(SAI_FrameInitStruct->SAI_FrameLength)); + assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(SAI_FrameInitStruct->SAI_ActiveFrameLength)); + assert_param(IS_SAI_BLOCK_FS_DEFINITION(SAI_FrameInitStruct->SAI_FSDefinition)); + assert_param(IS_SAI_BLOCK_FS_POLARITY(SAI_FrameInitStruct->SAI_FSPolarity)); + assert_param(IS_SAI_BLOCK_FS_OFFSET(SAI_FrameInitStruct->SAI_FSOffset)); + + /* SAI Block_x FRCR Configuration */ + /* Get the SAI Block_x FRCR value */ + tmpreg = SAI_Block_x->FRCR; + /* Clear FRL, FSALL, FSDEF, FSPOL, FSOFF bits */ + tmpreg &= FRCR_CLEAR_MASK; + /* Configure SAI_Block_x Frame: Frame Length, Active Frame Length, Frame Synchronization + Definition, Frame Synchronization Polarity and Frame Synchronization Polarity */ + /* Set FRL bits according to SAI_FrameLength value */ + /* Set FSALL bits according to SAI_ActiveFrameLength value */ + /* Set FSDEF bit according to SAI_FSDefinition value */ + /* Set FSPOL bit according to SAI_FSPolarity value */ + /* Set FSOFF bit according to SAI_FSOffset value */ + tmpreg |= (uint32_t)((uint32_t)(SAI_FrameInitStruct->SAI_FrameLength - 1) | + SAI_FrameInitStruct->SAI_FSOffset | + SAI_FrameInitStruct->SAI_FSDefinition | + SAI_FrameInitStruct->SAI_FSPolarity | + (uint32_t)((SAI_FrameInitStruct->SAI_ActiveFrameLength - 1) << 8)); + + /* Write to SAI_Block_x FRCR */ + SAI_Block_x->FRCR = tmpreg; +} + +/** + * @brief Initializes the SAI Block audio Slot according to the specified + * parameters in the SAI_SlotInitStruct. + * + * @note this function has no meaning if the AC'97 or SPDIF audio protocol + * are selected. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_SlotInitStruct: pointer to an SAI_SlotInitTypeDef structure that + * contains the configuration of audio slot for a specified SAI Block + * @retval None + */ +void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* Check the SAI Block Slot parameters */ + assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(SAI_SlotInitStruct->SAI_FirstBitOffset)); + assert_param(IS_SAI_BLOCK_SLOT_SIZE(SAI_SlotInitStruct->SAI_SlotSize)); + assert_param(IS_SAI_BLOCK_SLOT_NUMBER(SAI_SlotInitStruct->SAI_SlotNumber)); + assert_param(IS_SAI_SLOT_ACTIVE(SAI_SlotInitStruct->SAI_SlotActive)); + + /* SAI Block_x SLOTR Configuration */ + /* Get the SAI Block_x SLOTR value */ + tmpreg = SAI_Block_x->SLOTR; + /* Clear FBOFF, SLOTSZ, NBSLOT, SLOTEN bits */ + tmpreg &= SLOTR_CLEAR_MASK; + /* Configure SAI_Block_x Slot: First bit offset, Slot size, Number of Slot in + audio frame and slots activated in audio frame */ + /* Set FBOFF bits according to SAI_FirstBitOffset value */ + /* Set SLOTSZ bits according to SAI_SlotSize value */ + /* Set NBSLOT bits according to SAI_SlotNumber value */ + /* Set SLOTEN bits according to SAI_SlotActive value */ + tmpreg |= (uint32_t)(SAI_SlotInitStruct->SAI_FirstBitOffset | + SAI_SlotInitStruct->SAI_SlotSize | + SAI_SlotInitStruct->SAI_SlotActive | + (uint32_t)((SAI_SlotInitStruct->SAI_SlotNumber - 1) << 8)); + + /* Write to SAI_Block_x SLOTR */ + SAI_Block_x->SLOTR = tmpreg; +} + +/** + * @brief Fills each SAI_InitStruct member with its default value. + * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct) +{ + /* Reset SAI init structure parameters values */ + /* Initialize the SAI_AudioMode member */ + SAI_InitStruct->SAI_AudioMode = SAI_Mode_MasterTx; + /* Initialize the SAI_Protocol member */ + SAI_InitStruct->SAI_Protocol = SAI_Free_Protocol; + /* Initialize the SAI_DataSize member */ + SAI_InitStruct->SAI_DataSize = SAI_DataSize_8b; + /* Initialize the SAI_FirstBit member */ + SAI_InitStruct->SAI_FirstBit = SAI_FirstBit_MSB; + /* Initialize the SAI_ClockStrobing member */ + SAI_InitStruct->SAI_ClockStrobing = SAI_ClockStrobing_FallingEdge; + /* Initialize the SAI_Synchro member */ + SAI_InitStruct->SAI_Synchro = SAI_Asynchronous; + /* Initialize the SAI_OUTDRIV member */ + SAI_InitStruct->SAI_OUTDRIV = SAI_OutputDrive_Disabled; + /* Initialize the SAI_NoDivider member */ + SAI_InitStruct->SAI_NoDivider = SAI_MasterDivider_Enabled; + /* Initialize the SAI_MasterDivider member */ + SAI_InitStruct->SAI_MasterDivider = 0; + /* Initialize the SAI_FIFOThreshold member */ + SAI_InitStruct->SAI_FIFOThreshold = SAI_Threshold_FIFOEmpty; +} + +/** + * @brief Fills each SAI_FrameInitStruct member with its default value. + * @param SAI_FrameInitStruct: pointer to a SAI_FrameInitTypeDef structure + * which will be initialized. + * @retval None + */ +void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct) +{ + /* Reset SAI Frame init structure parameters values */ + /* Initialize the SAI_FrameLength member */ + SAI_FrameInitStruct->SAI_FrameLength = 8; + /* Initialize the SAI_ActiveFrameLength member */ + SAI_FrameInitStruct->SAI_ActiveFrameLength = 1; + /* Initialize the SAI_FSDefinition member */ + SAI_FrameInitStruct->SAI_FSDefinition = SAI_FS_StartFrame; + /* Initialize the SAI_FSPolarity member */ + SAI_FrameInitStruct->SAI_FSPolarity = SAI_FS_ActiveLow; + /* Initialize the SAI_FSOffset member */ + SAI_FrameInitStruct->SAI_FSOffset = SAI_FS_FirstBit; +} + +/** + * @brief Fills each SAI_SlotInitStruct member with its default value. + * @param SAI_SlotInitStruct: pointer to a SAI_SlotInitTypeDef structure + * which will be initialized. + * @retval None + */ +void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct) +{ + /* Reset SAI Slot init structure parameters values */ + /* Initialize the SAI_FirstBitOffset member */ + SAI_SlotInitStruct->SAI_FirstBitOffset = 0; + /* Initialize the SAI_SlotSize member */ + SAI_SlotInitStruct->SAI_SlotSize = SAI_SlotSize_DataSize; + /* Initialize the SAI_SlotNumber member */ + SAI_SlotInitStruct->SAI_SlotNumber = 1; + /* Initialize the SAI_SlotActive member */ + SAI_SlotInitStruct->SAI_SlotActive = SAI_Slot_NotActive; + +} + +/** + * @brief Enables or disables the specified SAI Block peripheral. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param NewState: new state of the SAI_Block_x peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SAI peripheral */ + SAI_Block_x->CR1 |= SAI_xCR1_SAIEN; + } + else + { + /* Disable the selected SAI peripheral */ + SAI_Block_x->CR1 &= ~(SAI_xCR1_SAIEN); + } +} + +/** + * @brief Configures the mono mode for the selected SAI block. + * + * @note This function has a meaning only when the number of slot is equal to 2. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_MonoMode: specifies the SAI block mono mode. + * This parameter can be one of the following values: + * @arg SAI_MonoMode : Set mono audio mode + * @arg SAI_StreoMode : Set streo audio mode + * @retval None + */ +void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_MONO_STREO_MODE(SAI_MonoMode)); + /* Clear MONO bit */ + SAI_Block_x->CR1 &= ~(SAI_xCR1_MONO); + /* Set new Mono Mode value */ + SAI_Block_x->CR1 |= SAI_MonoMode; +} + +/** + * @brief Configures the TRIState managment on data line for the selected SAI block. + * + * @note This function has a meaning only when the SAI block is configured in transmitter + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_TRIState: specifies the SAI block TRIState management. + * This parameter can be one of the following values: + * @arg SAI_Output_NotReleased : SD output line is still drived by the SAI. + * @arg SAI_Output_Released : SD output line is released (HI-Z) + * @retval None + */ +void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(SAI_TRIState)); + /* Clear MONO bit */ + SAI_Block_x->CR1 &= ~(SAI_xCR1_MONO); + /* Set new Mono Mode value */ + SAI_Block_x->CR1 |= SAI_MonoMode; + +} + +/** + * @brief Configures the companding mode for the selected SAI block. + * + * @note The data expansion or data compression are determined by the state of + * SAI block selected (transmitter or receiver). + + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_CompandingMode: specifies the SAI block companding mode. + * This parameter can be one of the following values: + * @arg SAI_NoCompanding : no companding algorithm set + * @arg SAI_ULaw_1CPL_Companding : Set U law (algorithm 1's complement representation) + * @arg SAI_ALaw_1CPL_Companding : Set A law (algorithm 1's complement repesentation) + * @arg SAI_ULaw_2CPL_Companding : Set U law (algorithm 2's complement representation) + * @arg SAI_ALaw_2CPL_Companding : Set A law (algorithm 2's complement repesentation) + * @retval None + */ +void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_COMPANDING_MODE(SAI_CompandingMode)); + /* Clear Companding Mode bits */ + SAI_Block_x->CR2 &= ~(SAI_xCR2_COMP); + /* Set new Companding Mode value */ + SAI_Block_x->CR2 |= SAI_CompandingMode; +} + +/** + * @brief Enables or disables the Mute mode for the selected SAI block. + * + * @note This function has a meaning only when the audio block is transmitter + * @note Mute mode is applied for an entire frame for all the valid slot + * It becomes active at the end of an audio frame when set somewhere in a frame. + * Mute mode exit occurs at the end of the frame in which the bit MUTE has been set. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param NewState: new state of the SAIx block. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SAI block mute mode */ + SAI_Block_x->CR2 |= SAI_xCR2_MUTE; + } + else + { + /* Disable the selected SAI SS output */ + SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTE); + } +} + +/** + * @brief Configure the mute value for the selected SAI block. + * + * @note This function has a meaning only when the audio block is transmitter + * @note the configuration last value sent during mute mode has only a meaning + * when the number of slot is lower or equal to 2 and if the MUTE bit is set. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_MuteValue: specifies the SAI block mute value. + * This parameter can be one of the following values: + * @arg SAI_ZeroValue : bit value 0 is sent during Mute Mode + * @arg SAI_LastSentValue : Last value is sent during Mute Mode + * @retval None + */ +void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_MUTE_VALUE(SAI_MuteValue)); + + /* Clear Mute value bits */ + SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTEVAL); + /* Set new Mute value */ + SAI_Block_x->CR2 |= SAI_MuteValue; +} + +/** + * @brief Enables or disables the Mute mode for the selected SAI block. + * + * @note This function has a meaning only when the audio block is Receiver + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_MuteCounter: specifies the SAI block mute value. + * This parameter can be a number between 0 and 63. + + * @retval None + */ +void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_MUTE_COUNTER(SAI_MuteCounter)); + + /* Clear Mute value bits */ + SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTECNT); + /* Set new Mute value */ + SAI_Block_x->CR2 |= (SAI_MuteCounter << 7); +} + +/** + * @brief Reinitialize the FIFO pointer + * + * @note The FIFO pointers can be reinitialized at anytime The data present + * into the FIFO, if it is not empty, will be lost. + * + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param NewState: new state of the selected SAI TI communication mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* FIFO flush */ + SAI_Block_x->CR2 |= SAI_xCR2_FFLUSH; +} + +/** + * @} + */ + +/** @defgroup SAI_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Data transfers functions ##### + =============================================================================== + [..] + This section provides a set of functions allowing to manage the SAI data transfers. + [..] + In reception, data are received and then stored into an internal FIFO while + In transmission, data are first stored into an internal FIFO before being + transmitted. + [..] + The read access of the SAI_xDR register can be done using the SAI_ReceiveData() + function and returns the Rx buffered value. Whereas a write access to the SAI_DR + can be done using SAI_SendData() function and stores the written data into + Tx buffer. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the most recent received data by the SAI block x peripheral. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * + * @retval The value of the received data. + */ +uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* Return the data in the DR register */ + return SAI_Block_x->DR; +} + +/** + * @brief Transmits a Data through the SAI block x peripheral. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * + * @param Data: Data to be transmitted. + * @retval None + */ +void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* Write in the DR register the data to be sent */ + SAI_Block_x->DR = Data; +} + +/** + * @} + */ + +/** @defgroup SAI_Group3 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + ##### DMA transfers management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SAI Block x DMA interface. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param NewState: new state of the selected SAI block DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SAI block mute mode */ + SAI_Block_x->CR1 |= SAI_xCR1_DMAEN; + } + else + { + /* Disable the selected SAI SS output */ + SAI_Block_x->CR1 &= ~(SAI_xCR1_DMAEN); + } +} + +/** + * @} + */ + +/** @defgroup SAI_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] + This section provides a set of functions allowing to configure the SAI Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + *** Polling Mode *** + ==================== + [..] + In Polling Mode, the SAI communication can be managed by 7 flags: + (#) SAI_FLAG_FREQ : to indicate if there is a FIFO Request to write or to read. + (#) SAI_FLAG_MUTEDET : to indicate if a MUTE frame detected + (#) SAI_FLAG_OVRUDR : to indicate if an Overrun or Underrun error occur + (#) SAI_FLAG_AFSDET : to indicate if there is the detection of a audio frame + synchronisation (FS) earlier than expected + (#) SAI_FLAG_LFSDET : to indicate if there is the detection of a audio frame + synchronisation (FS) later than expected + (#) SAI_FLAG_CNRDY : to indicate if the codec is not ready to communicate during + the reception of the TAG 0 (slot0) of the AC97 audio frame + (#) SAI_FLAG_WCKCFG: to indicate if wrong clock configuration in master mode + error occurs. + [..] + In this Mode it is advised to use the following functions: + (+) FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); + (+) void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); + + *** Interrupt Mode *** + ====================== + [..] + In Interrupt Mode, the SAI communication can be managed by 7 interrupt sources + and 7 pending bits: + (+) Pending Bits: + (##) SAI_IT_FREQ : to indicate if there is a FIFO Request to write or to read. + (##) SAI_IT_MUTEDET : to indicate if a MUTE frame detected. + (##) SAI_IT_OVRUDR : to indicate if an Overrun or Underrun error occur. + (##) SAI_IT_AFSDET : to indicate if there is the detection of a audio frame + synchronisation (FS) earlier than expected. + (##) SAI_IT_LFSDET : to indicate if there is the detection of a audio frame + synchronisation (FS) later than expected. + (##) SAI_IT_CNRDY : to indicate if the codec is not ready to communicate during + the reception of the TAG 0 (slot0) of the AC97 audio frame. + (##) SAI_IT_WCKCFG: to indicate if wrong clock configuration in master mode + error occurs. + + (+) Interrupt Source: + (##) SAI_IT_FREQ : specifies the interrupt source for FIFO Request. + (##) SAI_IT_MUTEDET : specifies the interrupt source for MUTE frame detected. + (##) SAI_IT_OVRUDR : specifies the interrupt source for overrun or underrun error. + (##) SAI_IT_AFSDET : specifies the interrupt source for anticipated frame synchronization + detection interrupt. + (##) SAI_IT_LFSDET : specifies the interrupt source for late frame synchronization + detection interrupt. + (##) SAI_IT_CNRDY : specifies the interrupt source for codec not ready interrupt + (##) SAI_IT_WCKCFG: specifies the interrupt source for wrong clock configuration + interrupt. + [..] + In this Mode it is advised to use the following functions: + (+) void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState); + (+) ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); + (+) void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); + + *** DMA Mode *** + ================ + [..] + In DMA Mode, each SAI audio block has an independent DMA interface in order to + read or to write into the SAI_xDR register (to hit the internal FIFO). + There is one DMA channel by audio block following basic DMA request/acknowledge + protocol. + [..] + In this Mode it is advised to use the following function: + (+) void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); + [..] + This section provides also functions allowing to + (+) Check the SAI Block enable status + (+)Check the FIFO status + + *** SAI Block Enable status *** + =============================== + [..] + After disabling a SAI Block, it is recommended to check (or wait until) the SAI Block + is effectively disabled. If a Block is disabled while an audio frame transfer is ongoing + the current frame will be transferred and the block will be effectively disabled only at + the end of audio frame. + To monitor this state it is possible to use the following function: + (+) FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x); + + *** SAI Block FIFO status *** + ============================= + [..] + It is possible to monitor the FIFO status when a transfer is ongoing using the following + function: + (+) uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified SAI Block interrupts. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_IT: specifies the SAI interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SAI_IT_FREQ: FIFO Request interrupt mask + * @arg SAI_IT_MUTEDET: MUTE detection interrupt mask + * @arg SAI_IT_OVRUDR: overrun/underrun interrupt mask + * @arg SAI_IT_AFSDET: anticipated frame synchronization detection + * interrupt mask + * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt + * mask + * @arg SAI_IT_CNRDY: codec not ready interrupt mask + * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt mask + * @param NewState: new state of the specified SAI interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected SAI Block interrupt */ + SAI_Block_x->IMR |= SAI_IT; + } + else + { + /* Disable the selected SAI Block interrupt */ + SAI_Block_x->IMR &= ~(SAI_IT); + } +} + +/** + * @brief Checks whether the specified SAI block x flag is set or not. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_FLAG: specifies the SAI block flag to check. + * This parameter can be one of the following values: + * @arg SAI_FLAG_FREQ: FIFO Request flag. + * @arg SAI_FLAG_MUTEDET: MUTE detection flag. + * @arg SAI_FLAG_OVRUDR: overrun/underrun flag. + * @arg SAI_FLAG_WCKCFG: wrong clock configuration flag. + * @arg SAI_FLAG_CNRDY: codec not ready flag. + * @arg SAI_FLAG_AFSDET: anticipated frame synchronization detection flag. + * @arg SAI_FLAG_LFSDET: late frame synchronization detection flag. + * @retval The new state of SAI_FLAG (SET or RESET). + */ +FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_GET_FLAG(SAI_FLAG)); + + /* Check the status of the specified SAI flag */ + if ((SAI_Block_x->SR & SAI_FLAG) != (uint32_t)RESET) + { + /* SAI_FLAG is set */ + bitstatus = SET; + } + else + { + /* SAI_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SAI_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the specified SAI Block x flag. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_FLAG: specifies the SAI block flag to check. + * This parameter can be one of the following values: + * @arg SAI_FLAG_MUTEDET: MUTE detection flag. + * @arg SAI_FLAG_OVRUDR: overrun/underrun flag. + * @arg SAI_FLAG_WCKCFG: wrong clock configuration flag. + * @arg SAI_FLAG_CNRDY: codec not ready flag. + * @arg SAI_FLAG_AFSDET: anticipated frame synchronization detection flag. + * @arg SAI_FLAG_LFSDET: late frame synchronization detection flag. + * + * @note FREQ (FIFO Request) flag is cleared : + * - When the audio block is transmitter and the FIFO is full or the FIFO + * has one data (one buffer mode) depending the bit FTH in the + * SAI_xCR2 register. + * - When the audio block is receiver and the FIFO is not empty + * + * @retval None + */ +void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_CLEAR_FLAG(SAI_FLAG)); + + /* Clear the selected SAI Block flag */ + SAI_Block_x->CLRFR |= SAI_FLAG; +} + +/** + * @brief Checks whether the specified SAI Block x interrupt has occurred or not. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_IT: specifies the SAI interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SAI_IT_FREQ: FIFO Request interrupt + * @arg SAI_IT_MUTEDET: MUTE detection interrupt + * @arg SAI_IT_OVRUDR: overrun/underrun interrupt + * @arg SAI_IT_AFSDET: anticipated frame synchronization detection interrupt + * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt + * @arg SAI_IT_CNRDY: codec not ready interrupt + * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt + * + * @retval The new state of SAI_IT (SET or RESET). + */ +ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); + + /* Get the SAI_IT enable bit status */ + enablestatus = (SAI_Block_x->IMR & SAI_IT) ; + + /* Check the status of the specified SAI interrupt */ + if (((SAI_Block_x->SR & SAI_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + /* SAI_IT is set */ + bitstatus = SET; + } + else + { + /* SAI_IT is reset */ + bitstatus = RESET; + } + /* Return the SAI_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SAI Block x interrupt pending bit. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * @param SAI_IT: specifies the SAI Block interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg SAI_IT_MUTEDET: MUTE detection interrupt. + * @arg SAI_IT_OVRUDR: overrun/underrun interrupt. + * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt. + * @arg SAI_IT_CNRDY: codec not ready interrupt. + * @arg SAI_IT_AFSDET: anticipated frame synchronization detection interrupt. + * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt. + * + * @note FREQ (FIFO Request) flag is cleared : + * - When the audio block is transmitter and the FIFO is full or the FIFO + * has one data (one buffer mode) depending the bit FTH in the + * SAI_xCR2 register. + * - When the audio block is receiver and the FIFO is not empty + * + * @retval None + */ +void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT) +{ + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); + + /* Clear the selected SAI Block x interrupt pending bit */ + SAI_Block_x->CLRFR |= SAI_IT; +} + +/** + * @brief Returns the status of EN bit for the specified SAI Block x. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * + * @note After disabling a SAI Block, it is recommended to check (or wait until) + * the SAI Block is effectively disabled. If a Block is disabled while + * an audio frame transfer is ongoing, the current frame will be + * transferred and the block will be effectively disabled only at + * the end of audio frame. + * + * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). + */ +FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x) +{ + FunctionalState state = DISABLE; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + if ((SAI_Block_x->CR1 & (uint32_t)SAI_xCR1_SAIEN) != 0) + { + /* The selected SAI Block x EN bit is set (audio frame transfer is ongoing) */ + state = ENABLE; + } + else + { + /* The selected SAI Block x EN bit is cleared (SAI Block is disabled and + all transfers are complete) */ + state = DISABLE; + } + return state; +} + +/** + * @brief Returns the current SAI Block x FIFO filled level. + * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. + * + * @retval The FIFO filling state. + * - SAI_FIFOStatus_Empty: when FIFO is empty + * - SAI_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - SAI_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - SAI_FIFOStatus_HalfFull: if more than 1 half-full. + * - SAI_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - SAI_FIFOStatus_Full: when FIFO is full + */ +uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); + + /* Get the FIFO level bits */ + tmpreg = (uint32_t)((SAI_Block_x->SR & SAI_xSR_FLVL)); + + return tmpreg; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c index 24a6c5ef23..94fed74571 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c @@ -2,146 +2,153 @@ ****************************************************************************** * @file stm32f4xx_sdio.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Secure digital input/output interface (SDIO) * peripheral: - * - Initialization and Configuration - * - Command path state machine (CPSM) management - * - Data path state machine (DPSM) management - * - SDIO IO Cards mode management - * - CE-ATA mode management - * - DMA transfers management - * - Interrupts and flags management + * + Initialization and Configuration + * + Command path state machine (CPSM) management + * + Data path state machine (DPSM) management + * + SDIO IO Cards mode management + * + CE-ATA mode management + * + DMA transfers management + * + Interrupts and flags management * - * @verbatim - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output - * of PLL (PLL48CLK). Before to start working with SDIO peripheral - * make sure that the PLL is well configured. - * The SDIO peripheral uses two clock signals: - * - SDIO adapter clock (SDIOCLK = 48 MHz) - * - APB2 bus clock (PCLK2) - * PCLK2 and SDIO_CK clock frequencies must respect the following condition: - * Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) - * - * 2. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). - * - * 3. According to the SDIO mode, enable the GPIO clocks using - * RCC_AHB1PeriphClockCmd() function. - * The I/O can be one of the following configurations: - * - 1-bit data length: SDIO_CMD, SDIO_CK and D0. - * - 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. - * - 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. - * - * 4. Peripheral's alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 5. Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, - * hardware, flow control and the Clock Divider using the SDIO_Init() - * function. - * - * 6. Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) - * function. - * - * 7. Enable the clock using the SDIO_ClockCmd() function. - * - * 8. Enable the NVIC and the corresponding interrupt using the function - * SDIO_ITConfig() if you need to use interrupt mode. - * - * 9. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using SDIO_DMACmd() function - * - * 10. Enable the DMA using the DMA_Cmd() function, when using DMA mode. - * - * 11. To control the CPSM (Command Path State Machine) and send - * commands to the card use the SDIO_SendCommand(), - * SDIO_GetCommandResponse() and SDIO_GetResponse() functions. - * First, user has to fill the command structure (pointer to - * SDIO_CmdInitTypeDef) according to the selected command to be sent. - * The parameters that should be filled are: - * - Command Argument - * - Command Index - * - Command Response type - * - Command Wait - * - CPSM Status (Enable or Disable) - * - * To check if the command is well received, read the SDIO_CMDRESP - * register using the SDIO_GetCommandResponse(). - * The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the - * SDIO_GetResponse() function. - * - * 12. To control the DPSM (Data Path State Machine) and send/receive - * data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), - * SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. - * - * Read Operations - * --------------- - * a) First, user has to fill the data structure (pointer to - * SDIO_DataInitTypeDef) according to the selected data type to - * be received. - * The parameters that should be filled are: - * - Data TimeOut - * - Data Length - * - Data Block size - * - Data Transfer direction: should be from card (To SDIO) - * - Data Transfer mode - * - DPSM Status (Enable or Disable) - * - * b) Configure the SDIO resources to receive the data from the card - * according to selected transfer mode (Refer to Step 8, 9 and 10). - * - * c) Send the selected Read command (refer to step 11). - * - * d) Use the SDIO flags/interrupts to check the transfer status. - * - * Write Operations - * --------------- - * a) First, user has to fill the data structure (pointer to - * SDIO_DataInitTypeDef) according to the selected data type to - * be received. - * The parameters that should be filled are: - * - Data TimeOut - * - Data Length - * - Data Block size - * - Data Transfer direction: should be to card (To CARD) - * - Data Transfer mode - * - DPSM Status (Enable or Disable) +@verbatim + + =================================================================== + ##### How to use this driver ##### + =================================================================== + [..] + (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL + (PLL48CLK). Before to start working with SDIO peripheral make sure that the + PLL is well configured. + The SDIO peripheral uses two clock signals: + (++) SDIO adapter clock (SDIOCLK = 48 MHz) + (++) APB2 bus clock (PCLK2) + + -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition: + Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) + + (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). + + (#) According to the SDIO mode, enable the GPIO clocks using + RCC_AHB1PeriphClockCmd() function. + The I/O can be one of the following configurations: + (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0. + (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. + (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. + + (#) Peripheral alternate function: + (++) Connect the pin to the desired peripherals' Alternate Function (AF) + using GPIO_PinAFConfig() function + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, + GPIO_OType and GPIO_Speed members + (++) Call GPIO_Init() function + + (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, + hardware, flow control and the Clock Divider using the SDIO_Init() + function. + + (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) + function. + + (#) Enable the clock using the SDIO_ClockCmd() function. + + (#) Enable the NVIC and the corresponding interrupt using the function + SDIO_ITConfig() if you need to use interrupt mode. + + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function + (++) Active the needed channel Request using SDIO_DMACmd() function + + (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. + + (#) To control the CPSM (Command Path State Machine) and send + commands to the card use the SDIO_SendCommand(), + SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has + to fill the command structure (pointer to SDIO_CmdInitTypeDef) according + to the selected command to be sent. + The parameters that should be filled are: + (++) Command Argument + (++) Command Index + (++) Command Response type + (++) Command Wait + (++) CPSM Status (Enable or Disable). + + -@@- To check if the command is well received, read the SDIO_CMDRESP + register using the SDIO_GetCommandResponse(). + The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the + SDIO_GetResponse() function. + + (#) To control the DPSM (Data Path State Machine) and send/receive + data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), + SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. + + *** Read Operations *** + ======================= + [..] + (#) First, user has to fill the data structure (pointer to + SDIO_DataInitTypeDef) according to the selected data type to be received. + The parameters that should be filled are: + (++) Data TimeOut + (++) Data Length + (++) Data Block size + (++) Data Transfer direction: should be from card (To SDIO) + (++) Data Transfer mode + (++) DPSM Status (Enable or Disable) + + (#) Configure the SDIO resources to receive the data from the card + according to selected transfer mode (Refer to Step 8, 9 and 10). + + (#) Send the selected Read command (refer to step 11). + + (#) Use the SDIO flags/interrupts to check the transfer status. + + *** Write Operations *** + ======================== + [..] + (#) First, user has to fill the data structure (pointer to + SDIO_DataInitTypeDef) according to the selected data type to be received. + The parameters that should be filled are: + (++) Data TimeOut + (++) Data Length + (++) Data Block size + (++) Data Transfer direction: should be to card (To CARD) + (++) Data Transfer mode + (++) DPSM Status (Enable or Disable) + + (#) Configure the SDIO resources to send the data to the card according to + selected transfer mode (Refer to Step 8, 9 and 10). + + (#) Send the selected Write command (refer to step 11). + + (#) Use the SDIO flags/interrupts to check the transfer status. + + +@endverbatim * - * b) Configure the SDIO resources to send the data to the card - * according to selected transfer mode (Refer to Step 8, 9 and 10). - * - * c) Send the selected Write command (refer to step 11). - * - * d) Use the SDIO flags/interrupts to check the transfer status. * + ****************************************************************************** + * @attention * - * @endverbatim + *

    © COPYRIGHT 2013 STMicroelectronics

    * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -244,7 +251,7 @@ * @verbatim =============================================================================== - Initialization and Configuration functions + ##### Initialization and Configuration functions ##### =============================================================================== @endverbatim @@ -371,7 +378,7 @@ uint32_t SDIO_GetPowerState(void) * @verbatim =============================================================================== - Command path state machine (CPSM) management functions + ##### Command path state machine (CPSM) management functions ##### =============================================================================== This section provide functions allowing to program and read the Command path @@ -476,7 +483,7 @@ uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) * @verbatim =============================================================================== - Data path state machine (DPSM) management functions + ##### Data path state machine (DPSM) management functions ##### =============================================================================== This section provide functions allowing to program and read the Data path @@ -594,7 +601,7 @@ uint32_t SDIO_GetFIFOCount(void) * @verbatim =============================================================================== - SDIO IO Cards mode management functions + ##### SDIO IO Cards mode management functions ##### =============================================================================== This section provide functions allowing to program and read the SDIO IO Cards. @@ -684,7 +691,7 @@ void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) * @verbatim =============================================================================== - CE-ATA mode management functions + ##### CE-ATA mode management functions ##### =============================================================================== This section provide functions allowing to program and read the CE-ATA card. @@ -744,7 +751,7 @@ void SDIO_SendCEATACmd(FunctionalState NewState) * @verbatim =============================================================================== - DMA transfers management functions + ##### DMA transfers management functions ##### =============================================================================== This section provide functions allowing to program SDIO DMA transfer. @@ -776,7 +783,7 @@ void SDIO_DMACmd(FunctionalState NewState) * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== @@ -1001,4 +1008,4 @@ void SDIO_ClearITPendingBit(uint32_t SDIO_IT) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c index d02193ea52..616f2a86e4 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c @@ -2,149 +2,156 @@ ****************************************************************************** * @file stm32f4xx_spi.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Serial peripheral interface (SPI): - * - Initialization and Configuration - * - Data transfers functions - * - Hardware CRC Calculation - * - DMA transfers management - * - Interrupts and flags management + * + Initialization and Configuration + * + Data transfers functions + * + Hardware CRC Calculation + * + DMA transfers management + * + Interrupts and flags management * - * @verbatim - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * 1. Enable peripheral clock using the following functions - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 - * RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3. - * - * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() - * function. - * In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO - * clock should also be enabled. - * - * 3. Peripherals alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * In I2S mode, if an external clock source is used then the I2S CKIN pin - * should be also configured in Alternate function Push-pull pull-up mode. - * - * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave - * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - * function. - * In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio - * frequency and Polarity using I2S_Init() function. - * For I2S mode, make sure that either: - * - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), - * RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY). - * or - * - External clock source is configured using the function - * RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant - * I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. - * - * 5. Enable the NVIC and the corresponding interrupt using the function - * SPI_ITConfig() if you need to use interrupt mode. - * - * 6. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using SPI_I2S_DMACmd() function - * - * 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using - * I2S_Cmd(). - * - * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. - * - * 9. Optionally, you can enable/configure the following parameters without - * re-initialization (i.e there is no need to call again SPI_Init() function): - * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) - * is programmed as Data direction parameter using the SPI_Init() function - * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx - * using the SPI_BiDirectionalLineConfig() function. - * - When SPI_NSS_Soft is selected as Slave Select Management parameter - * using the SPI_Init() function it can be possible to manage the - * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. - * - Reconfigure the data size using the SPI_DataSizeConfig() function - * - Enable or disable the SS output using the SPI_SSOutputCmd() function - * - * 10. To use the CRC Hardware calculation feature refer to the Peripheral - * CRC hardware Calculation subsection. - * - * - * It is possible to use SPI in I2S full duplex mode, in this case, each SPI - * peripheral is able to manage sending and receiving data simultaneously - * using two data lines. Each SPI peripheral has an extended block called I2Sxext - * (ie. I2S2ext for SPI2 and I2S3ext for SPI3). - * The extension block is not a full SPI IP, it is used only as I2S slave to - * implement full duplex mode. The extension block uses the same clock sources - * as its master. - * To configure I2S full duplex you have to: - * - * 1. Configure SPIx in I2S mode (I2S_Init() function) as described above. - * - * 2. Call the I2S_FullDuplexConfig() function using the same strucutre passed to - * I2S_Init() function. - * - * 3. Call I2S_Cmd() for SPIx then for its extended block. - * - * 4. To configure interrupts or DMA requests and to get/clear flag status, - * use I2Sxext instance for the extension block. - * - * Functions that can be called with I2Sxext instances are: - * I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), - * SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(), - * SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit(). - * - * Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx): - * - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); - * I2S_StructInit(&I2SInitStruct); - * I2SInitStruct.Mode = I2S_Mode_MasterTx; - * I2S_Init(SPI3, &I2SInitStruct); - * I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct) - * I2S_Cmd(SPI3, ENABLE); - * I2S_Cmd(SPI3ext, ENABLE); - * ... - * while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) - * {} - * SPI_I2S_SendData(SPI3, txdata[i]); - * ... - * while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET) - * {} - * rxdata[i] = SPI_I2S_ReceiveData(I2S3ext); - * ... - * - * - * @note In I2S mode: if an external clock is used as source clock for the I2S, - * then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should - * be enabled and set to the value of the source clock frequency (in Hz). - * - * @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() - * just after calling the function SPI_Init(). - * - * @endverbatim +@verbatim + + =================================================================== + ##### How to use this driver ##### + =================================================================== + [..] + (#) Enable peripheral clock using the following functions + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 + RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3 + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI4 + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI5 + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI6. + + (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() + function. In I2S mode, if an external clock source is used then the I2S + CKIN pin GPIO clock should also be enabled. + + (#) Peripherals alternate function: + (++) Connect the pin to the desired peripherals' Alternate Function (AF) + using GPIO_PinAFConfig() function + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, + GPIO_OType and GPIO_Speed members + (++) Call GPIO_Init() function In I2S mode, if an external clock source is + used then the I2S CKIN pin should be also configured in Alternate + function Push-pull pull-up mode. + + (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave + Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + function. + In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio + frequency and Polarity using I2S_Init() function. For I2S mode, make sure + that either: + (++) I2S PLL is configured using the functions + RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), RCC_PLLI2SCmd(ENABLE) and + RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY); or + (++) External clock source is configured using the function + RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly + the define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. + + (#) Enable the NVIC and the corresponding interrupt using the function + SPI_ITConfig() if you need to use interrupt mode. + + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function + (++) Active the needed channel Request using SPI_I2S_DMACmd() function + + (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using + I2S_Cmd(). + + (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. + + (#) Optionally, you can enable/configure the following parameters without + re-initialization (i.e there is no need to call again SPI_Init() function): + (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) + is programmed as Data direction parameter using the SPI_Init() function + it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx + using the SPI_BiDirectionalLineConfig() function. + (++) When SPI_NSS_Soft is selected as Slave Select Management parameter + using the SPI_Init() function it can be possible to manage the + NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. + (++) Reconfigure the data size using the SPI_DataSizeConfig() function + (++) Enable or disable the SS output using the SPI_SSOutputCmd() function + + (#) To use the CRC Hardware calculation feature refer to the Peripheral + CRC hardware Calculation subsection. + + + [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI + peripheral is able to manage sending and receiving data simultaneously + using two data lines. Each SPI peripheral has an extended block called I2Sxext + (ie. I2S2ext for SPI2 and I2S3ext for SPI3). + The extension block is not a full SPI IP, it is used only as I2S slave to + implement full duplex mode. The extension block uses the same clock sources + as its master. + To configure I2S full duplex you have to: + + (#) Configure SPIx in I2S mode (I2S_Init() function) as described above. + + (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to + I2S_Init() function. + + (#) Call I2S_Cmd() for SPIx then for its extended block. + + (#) To configure interrupts or DMA requests and to get/clear flag status, + use I2Sxext instance for the extension block. + + [..] Functions that can be called with I2Sxext instances are: I2S_Cmd(), + I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), + SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), + SPI_I2S_ClearFlag(), SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit(). + + Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx): + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); + I2S_StructInit(&I2SInitStruct); + I2SInitStruct.Mode = I2S_Mode_MasterTx; + I2S_Init(SPI3, &I2SInitStruct); + I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct) + I2S_Cmd(SPI3, ENABLE); + I2S_Cmd(SPI3ext, ENABLE); + ... + while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) + {} + SPI_I2S_SendData(SPI3, txdata[i]); + ... + while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET) + {} + rxdata[i] = SPI_I2S_ReceiveData(I2S3ext); + ... + + [..] + (@) In I2S mode: if an external clock is used as source clock for the I2S, + then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should + be enabled and set to the value of the source clock frequency (in Hz). + + (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() + just after calling the function SPI_Init(). + +@endverbatim * ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -189,28 +196,27 @@ * @verbatim =============================================================================== - Initialization and Configuration functions + ##### Initialization and Configuration functions ##### =============================================================================== - - This section provides a set of functions allowing to initialize the SPI Direction, - SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud - Rate Prescaler, SPI First Bit and SPI CRC Polynomial. + [..] This section provides a set of functions allowing to initialize the SPI + Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS + Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial. - The SPI_Init() function follows the SPI configuration procedures for Master mode - and Slave mode (details for these procedures are available in reference manual - (RM0090)). + [..] The SPI_Init() function follows the SPI configuration procedures for Master + mode and Slave mode (details for these procedures are available in reference + manual (RM0090)). @endverbatim * @{ */ /** - * @brief Deinitialize the SPIx peripheral registers to their default reset values. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * @brief De-initialize the SPIx peripheral registers to their default reset values. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode. * - * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are deinitialized - * when the relative I2S peripheral is deinitialized (the extended block's clock + * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are de-initialized + * when the relative I2S peripheral is de-initialized (the extended block's clock * is managed by the I2S peripheral clock). * * @retval None @@ -233,15 +239,36 @@ void SPI_I2S_DeInit(SPI_TypeDef* SPIx) RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); /* Release SPI2 from reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else + } + else if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + else if (SPIx == SPI4) + { + /* Enable SPI4 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE); + /* Release SPI4 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, DISABLE); + } + else if (SPIx == SPI5) + { + /* Enable SPI5 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, ENABLE); + /* Release SPI5 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, DISABLE); + } + else { - if (SPIx == SPI3) + if (SPIx == SPI6) { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + /* Enable SPI6 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, ENABLE); + /* Release SPI6 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, DISABLE); } } } @@ -249,7 +276,7 @@ void SPI_I2S_DeInit(SPI_TypeDef* SPIx) /** * @brief Initializes the SPIx peripheral according to the specified * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that * contains the configuration information for the specified SPI peripheral. * @retval None @@ -395,7 +422,7 @@ void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) /* Get the PLLM value */ pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - + /* Get the I2S source clock value */ i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); #endif /* I2S_EXTERNAL_CLOCK_VAL */ @@ -502,7 +529,7 @@ void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) /** * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param NewState: new state of the SPIx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -552,7 +579,7 @@ void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) /** * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param SPI_DataSize: specifies the SPI data size. * This parameter can be one of the following values: * @arg SPI_DataSize_16b: Set data frame format to 16bit @@ -572,7 +599,7 @@ void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) /** * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. * This parameter can be one of the following values: * @arg SPI_Direction_Tx: Selects Tx transmission direction @@ -598,7 +625,7 @@ void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) /** * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. * This parameter can be one of the following values: * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally @@ -624,7 +651,7 @@ void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSo /** * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param NewState: new state of the SPIx SS output. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -655,7 +682,7 @@ void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) * are not taken into consideration and are configured by hardware * respectively to the TI mode requirements. * - * @param SPIx: where x can be 1, 2 or 3 + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 * @param NewState: new state of the selected SPI TI communication mode. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -748,19 +775,18 @@ void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct) * @verbatim =============================================================================== - Data transfers functions + ##### Data transfers functions ##### =============================================================================== - This section provides a set of functions allowing to manage the SPI data transfers - - In reception, data are received and then stored into an internal Rx buffer while - In transmission, data are first stored into an internal Tx buffer before being - transmitted. + [..] This section provides a set of functions allowing to manage the SPI data + transfers. In reception, data are received and then stored into an internal + Rx buffer while. In transmission, data are first stored into an internal Tx + buffer before being transmitted. - The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() - function and returns the Rx buffered value. Whereas a write access to the SPI_DR - can be done using SPI_I2S_SendData() function and stores the written data into - Tx buffer. + [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() + function and returns the Rx buffered value. Whereas a write access to the SPI_DR + can be done using SPI_I2S_SendData() function and stores the written data into + Tx buffer. @endverbatim * @{ @@ -768,7 +794,7 @@ void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct) /** * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @retval The value of the received data. */ @@ -783,7 +809,7 @@ uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) /** * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param Data: Data to be transmitted. * @retval None @@ -806,65 +832,66 @@ void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) * @verbatim =============================================================================== - Hardware CRC Calculation functions + ##### Hardware CRC Calculation functions ##### =============================================================================== - This section provides a set of functions allowing to manage the SPI CRC hardware - calculation - - SPI communication using CRC is possible through the following procedure: - 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, - Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - 2. Enable the CRC calculation using the SPI_CalculateCRC() function. - 3. Enable the SPI using the SPI_Cmd() function - 4. Before writing the last data to the TX buffer, set the CRCNext bit using the - SPI_TransmitCRC() function to indicate that after transmission of the last - data, the CRC should be transmitted. - 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT + [..] This section provides a set of functions allowing to manage the SPI CRC hardware + calculation + + [..] SPI communication using CRC is possible through the following procedure: + (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, + Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + function. + (#) Enable the CRC calculation using the SPI_CalculateCRC() function. + (#) Enable the SPI using the SPI_Cmd() function + (#) Before writing the last data to the TX buffer, set the CRCNext bit using the + SPI_TransmitCRC() function to indicate that after transmission of the last + data, the CRC should be transmitted. + (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT bit is reset. The CRC is also received and compared against the SPI_RXCRCR value. If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt can be generated when the SPI_I2S_IT_ERR interrupt is enabled. -@note It is advised not to read the calculated CRC values during the communication. - -@note When the SPI is in slave mode, be careful to enable CRC calculation only - when the clock is stable, that is, when the clock is in the steady state. - If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive - to the SCK slave input clock as soon as CRCEN is set, and this, whatever - the value of the SPE bit. - -@note With high bitrate frequencies, be careful when transmitting the CRC. - As the number of used CPU cycles has to be as low as possible in the CRC - transfer phase, it is forbidden to call software functions in the CRC - transmission sequence to avoid errors in the last data and CRC reception. - In fact, CRCNEXT bit has to be written before the end of the transmission/reception - of the last data. - -@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the - degradation of the SPI speed performance due to CPU accesses impacting the - SPI bandwidth. - -@note When the STM32F4xx is configured as slave and the NSS hardware mode is - used, the NSS pin needs to be kept low between the data phase and the CRC - phase. - -@note When the SPI is configured in slave mode with the CRC feature enabled, CRC - calculation takes place even if a high level is applied on the NSS pin. - This may happen for example in case of a multi-slave environment where the - communication master addresses slaves alternately. - -@note Between a slave de-selection (high level on NSS) and a new slave selection - (low level on NSS), the CRC value should be cleared on both master and slave - sides in order to resynchronize the master and slave for their respective - CRC calculation. - -@note To clear the CRC, follow the procedure below: - 1. Disable SPI using the SPI_Cmd() function - 2. Disable the CRC calculation using the SPI_CalculateCRC() function. - 3. Enable the CRC calculation using the SPI_CalculateCRC() function. - 4. Enable SPI using the SPI_Cmd() function. + [..] + (@) It is advised not to read the calculated CRC values during the communication. + + (@) When the SPI is in slave mode, be careful to enable CRC calculation only + when the clock is stable, that is, when the clock is in the steady state. + If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive + to the SCK slave input clock as soon as CRCEN is set, and this, whatever + the value of the SPE bit. + + (@) With high bitrate frequencies, be careful when transmitting the CRC. + As the number of used CPU cycles has to be as low as possible in the CRC + transfer phase, it is forbidden to call software functions in the CRC + transmission sequence to avoid errors in the last data and CRC reception. + In fact, CRCNEXT bit has to be written before the end of the transmission/reception + of the last data. + + (@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the + degradation of the SPI speed performance due to CPU accesses impacting the + SPI bandwidth. + + (@) When the STM32F4xx is configured as slave and the NSS hardware mode is + used, the NSS pin needs to be kept low between the data phase and the CRC + phase. + + (@) When the SPI is configured in slave mode with the CRC feature enabled, CRC + calculation takes place even if a high level is applied on the NSS pin. + This may happen for example in case of a multi-slave environment where the + communication master addresses slaves alternately. + + (@) Between a slave de-selection (high level on NSS) and a new slave selection + (low level on NSS), the CRC value should be cleared on both master and slave + sides in order to resynchronize the master and slave for their respective + CRC calculation. + + (@) To clear the CRC, follow the procedure below: + (#@) Disable SPI using the SPI_Cmd() function + (#@) Disable the CRC calculation using the SPI_CalculateCRC() function. + (#@) Enable the CRC calculation using the SPI_CalculateCRC() function. + (#@) Enable SPI using the SPI_Cmd() function. @endverbatim * @{ @@ -872,7 +899,7 @@ void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) /** * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param NewState: new state of the SPIx CRC value calculation. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -896,7 +923,7 @@ void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) /** * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @retval None */ void SPI_TransmitCRC(SPI_TypeDef* SPIx) @@ -910,7 +937,7 @@ void SPI_TransmitCRC(SPI_TypeDef* SPIx) /** * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param SPI_CRC: specifies the CRC register to be read. * This parameter can be one of the following values: * @arg SPI_CRC_Tx: Selects Tx CRC register @@ -939,7 +966,7 @@ uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) /** * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @retval The CRC Polynomial register value. */ uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) @@ -960,7 +987,7 @@ uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) * @verbatim =============================================================================== - DMA transfers management functions + ##### DMA transfers management functions ##### =============================================================================== @endverbatim @@ -969,7 +996,7 @@ uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) /** * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. * This parameter can be any combination of the following values: @@ -1007,69 +1034,68 @@ void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== - - This section provides a set of functions allowing to configure the SPI Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. + + [..] This section provides a set of functions allowing to configure the SPI Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. - Polling Mode - ============= - In Polling Mode, the SPI/I2S communication can be managed by 9 flags: - 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register - 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register - 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. - 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur - 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur - 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur - 7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. - 8. I2S_FLAG_UDR: to indicate an Underrun error occurs. - 9. I2S_FLAG_CHSIDE: to indicate Channel Side. - -@note Do not use the BSY flag to handle each data transmission or reception. It is + *** Polling Mode *** + ==================== +[..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags: + (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register + (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register + (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. + (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur + (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur + (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur + (#) I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. + (#) I2S_FLAG_UDR: to indicate an Underrun error occurs. + (#) I2S_FLAG_CHSIDE: to indicate Channel Side. + + (@) Do not use the BSY flag to handle each data transmission or reception. It is better to use the TXE and RXNE flags instead. - In this Mode it is advised to use the following functions: - - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - Interrupt Mode - =============== - In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources - and 7 pending bits: - Pending Bits: - ------------- - 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register - 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register - 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) - 4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) - 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur - 6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). - 7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). - - Interrupt Source: - ----------------- - 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty - interrupt. - 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. - - In this Mode it is advised to use the following functions: - - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); - - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - DMA Mode - ======== - In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: - 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request - 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - In this Mode it is advised to use the following function: - - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); + [..] In this Mode it is advised to use the following functions: + (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + + *** Interrupt Mode *** + ====================== + [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources + and 7 pending bits: + (+) Pending Bits: + (##) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register + (##) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register + (##) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) + (##) SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) + (##) SPI_I2S_IT_OVR : to indicate if an Overrun error occur + (##) I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). + (##) I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). + + (+) Interrupt Source: + (##) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty + interrupt. + (##) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not + empty interrupt. + (##) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. + + [..] In this Mode it is advised to use the following functions: + (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); + (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + + *** DMA Mode *** + ================ + [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: + (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request + (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request + + [..] In this Mode it is advised to use the following function: + (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState + NewState); @endverbatim * @{ @@ -1077,7 +1103,7 @@ void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState /** * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. * This parameter can be one of the following values: @@ -1117,7 +1143,7 @@ void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState New /** * @brief Checks whether the specified SPIx/I2Sx flag is set or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_FLAG: specifies the SPI flag to check. * This parameter can be one of the following values: @@ -1156,7 +1182,7 @@ FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) /** * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_FLAG: specifies the SPI flag to clear. * This function clears only CRCERR flag. @@ -1185,7 +1211,7 @@ void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) /** * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_IT: specifies the SPI interrupt source to check. * This parameter can be one of the following values: @@ -1236,7 +1262,7 @@ ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) /** * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. * This function clears only CRCERR interrupt pending bit. @@ -1283,4 +1309,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c index 2625cfee4c..357051167c 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c @@ -2,40 +2,47 @@ ****************************************************************************** * @file stm32f4xx_syscfg.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the SYSCFG peripheral. * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * This driver provides functions for: - * - * 1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() - * - * 2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() - * - * 3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() - * - * @note SYSCFG APB clock must be enabled to get write access to SYSCFG registers, - * using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - * - * @endverbatim - * + @verbatim + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] This driver provides functions for: + + (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() + + (#) Swapping the internal flash Bank1 and Bank2 this features is only visible for + STM32F42xxx/43xxx devices Devices. + + (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() + + (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() + + -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers, + using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + @endverbatim ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -56,6 +63,13 @@ /* Private define ------------------------------------------------------------*/ /* ------------ RCC registers bit address in the alias region ----------- */ #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) +/* --- MEMRMP Register ---*/ +/* Alias word address of UFB_MODE bit */ +#define MEMRMP_OFFSET SYSCFG_OFFSET +#define UFB_MODE_BitNumber ((uint8_t)0x8) +#define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4)) + + /* --- PMC Register ---*/ /* Alias word address of MII_RMII_SEL bit */ #define PMC_OFFSET (SYSCFG_OFFSET + 0x04) @@ -95,8 +109,10 @@ void SYSCFG_DeInit(void) * This parameter can be one of the following values: * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx and STM32F415xx/417xx devices. + * @arg SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices. * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices. * @retval None */ void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) @@ -107,13 +123,40 @@ void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) SYSCFG->MEMRMP = SYSCFG_MemoryRemap; } +/** + * @brief Enables or disables the Interal FLASH Bank Swapping. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @param NewState: new state of Interal FLASH Bank swapping. + * This parameter can be one of the following values: + * @arg ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) + * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) + * @arg DISABLE:(the default state) Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) + and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) + * @retval None + */ +void SYSCFG_MemorySwappingBank(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) UFB_MODE_BB = (uint32_t)NewState; +} + /** * @brief Selects the GPIO pin used as EXTI Line. * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for - * EXTI lines where x can be (A..I). + * EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I) + * for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H) + * for STM32401xx devices. + * * @param EXTI_PinSourcex: specifies the EXTI line to be configured. * This parameter can be EXTI_PinSourcex where x can be (0..15, except - * for EXTI_PortSourceGPIOI x can be (0..11). + * for EXTI_PortSourceGPIOI x can be (0..11) for STM32F405xx/407xx + * and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK x can + * be (0..7) for STM32F42xxx/43xxx devices. + * * @retval None */ void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) @@ -194,4 +237,4 @@ FlagStatus SYSCFG_GetCompensationCellStatus(void) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c index 02982f880f..ad57d8301e 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c @@ -2,111 +2,116 @@ ****************************************************************************** * @file stm32f4xx_tim.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the TIM peripheral: - * - TimeBase management - * - Output Compare management - * - Input Capture management - * - Advanced-control timers (TIM1 and TIM8) specific features - * - Interrupts, DMA and flags management - * - Clocks management - * - Synchronization management - * - Specific interface management - * - Specific remapping management + * + TimeBase management + * + Output Compare management + * + Input Capture management + * + Advanced-control timers (TIM1 and TIM8) specific features + * + Interrupts, DMA and flags management + * + Clocks management + * + Synchronization management + * + Specific interface management + * + Specific remapping management * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * This driver provides functions to configure and program the TIM - * of all STM32F4xx devices. - * These functions are split in 9 groups: - * - * 1. TIM TimeBase management: this group includes all needed functions - * to configure the TM Timebase unit: - * - Set/Get Prescaler - * - Set/Get Autoreload - * - Counter modes configuration - * - Set Clock division - * - Select the One Pulse mode - * - Update Request Configuration - * - Update Disable Configuration - * - Auto-Preload Configuration - * - Enable/Disable the counter - * - * 2. TIM Output Compare management: this group includes all needed - * functions to configure the Capture/Compare unit used in Output - * compare mode: - * - Configure each channel, independently, in Output Compare mode - * - Select the output compare modes - * - Select the Polarities of each channel - * - Set/Get the Capture/Compare register values - * - Select the Output Compare Fast mode - * - Select the Output Compare Forced mode - * - Output Compare-Preload Configuration - * - Clear Output Compare Reference - * - Select the OCREF Clear signal - * - Enable/Disable the Capture/Compare Channels - * - * 3. TIM Input Capture management: this group includes all needed - * functions to configure the Capture/Compare unit used in - * Input Capture mode: - * - Configure each channel in input capture mode - * - Configure Channel1/2 in PWM Input mode - * - Set the Input Capture Prescaler - * - Get the Capture/Compare values - * - * 4. Advanced-control timers (TIM1 and TIM8) specific features - * - Configures the Break input, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable) - * - Enable/Disable the TIM peripheral Main Outputs - * - Select the Commutation event - * - Set/Reset the Capture Compare Preload Control bit - * - * 5. TIM interrupts, DMA and flags management - * - Enable/Disable interrupt sources - * - Get flags status - * - Clear flags/ Pending bits - * - Enable/Disable DMA requests - * - Configure DMA burst mode - * - Select CaptureCompare DMA request - * - * 6. TIM clocks management: this group includes all needed functions - * to configure the clock controller unit: - * - Select internal/External clock - * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx - * - * 7. TIM synchronization management: this group includes all needed - * functions to configure the Synchronization unit: - * - Select Input Trigger - * - Select Output Trigger - * - Select Master Slave Mode - * - ETR Configuration when used as external trigger - * - * 8. TIM specific interface management, this group includes all - * needed functions to use the specific TIM interface: - * - Encoder Interface Configuration - * - Select Hall Sensor - * - * 9. TIM specific remapping management includes the Remapping - * configuration of specific timers - * - * @endverbatim - * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + This driver provides functions to configure and program the TIM + of all STM32F4xx devices. + These functions are split in 9 groups: + + (#) TIM TimeBase management: this group includes all needed functions + to configure the TM Timebase unit: + (++) Set/Get Prescaler + (++) Set/Get Autoreload + (++) Counter modes configuration + (++) Set Clock division + (++) Select the One Pulse mode + (++) Update Request Configuration + (++) Update Disable Configuration + (++) Auto-Preload Configuration + (++) Enable/Disable the counter + + (#) TIM Output Compare management: this group includes all needed + functions to configure the Capture/Compare unit used in Output + compare mode: + (++) Configure each channel, independently, in Output Compare mode + (++) Select the output compare modes + (++) Select the Polarities of each channel + (++) Set/Get the Capture/Compare register values + (++) Select the Output Compare Fast mode + (++) Select the Output Compare Forced mode + (++) Output Compare-Preload Configuration + (++) Clear Output Compare Reference + (++) Select the OCREF Clear signal + (++) Enable/Disable the Capture/Compare Channels + + (#) TIM Input Capture management: this group includes all needed + functions to configure the Capture/Compare unit used in + Input Capture mode: + (++) Configure each channel in input capture mode + (++) Configure Channel1/2 in PWM Input mode + (++) Set the Input Capture Prescaler + (++) Get the Capture/Compare values + + (#) Advanced-control timers (TIM1 and TIM8) specific features + (++) Configures the Break input, dead time, Lock level, the OSSI, + the OSSR State and the AOE(automatic output enable) + (++) Enable/Disable the TIM peripheral Main Outputs + (++) Select the Commutation event + (++) Set/Reset the Capture Compare Preload Control bit + + (#) TIM interrupts, DMA and flags management + (++) Enable/Disable interrupt sources + (++) Get flags status + (++) Clear flags/ Pending bits + (++) Enable/Disable DMA requests + (++) Configure DMA burst mode + (++) Select CaptureCompare DMA request + + (#) TIM clocks management: this group includes all needed functions + to configure the clock controller unit: + (++) Select internal/External clock + (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx + + (#) TIM synchronization management: this group includes all needed + functions to configure the Synchronization unit: + (++) Select Input Trigger + (++) Select Output Trigger + (++) Select Master Slave Mode + (++) ETR Configuration when used as external trigger + + (#) TIM specific interface management, this group includes all + needed functions to use the specific TIM interface: + (++) Encoder Interface Configuration + (++) Select Hall Sensor + + (#) TIM specific remapping management includes the Remapping + configuration of specific timers + + @endverbatim ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -157,29 +162,30 @@ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ * @verbatim =============================================================================== - TimeBase management functions + ##### TimeBase management functions ##### =============================================================================== - =================================================================== - TIM Driver: how to use it in Timing(Time base) Mode - =================================================================== - To use the Timer in Timing(Time base) mode, the following steps are mandatory: + + ##### TIM Driver: how to use it in Timing(Time base) Mode ##### + =============================================================================== + [..] + To use the Timer in Timing(Time base) mode, the following steps are mandatory: - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function + (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - 2. Fill the TIM_TimeBaseInitStruct with the desired parameters. + (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. - 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit + (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit with the corresponding configuration - 4. Enable the NVIC if you need to generate the update interrupt. + (#) Enable the NVIC if you need to generate the update interrupt. - 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) + (#) Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) - 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - Note1: All other functions can be used separately to modify, if needed, - a specific feature of the Timer. + -@- All other functions can be used separately to modify, if needed, + a specific feature of the Timer. @endverbatim * @{ @@ -609,46 +615,48 @@ void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) * @verbatim =============================================================================== - Output Compare management functions + ##### Output Compare management functions ##### =============================================================================== - =================================================================== - TIM Driver: how to use it in Output Compare Mode - =================================================================== - To use the Timer in Output Compare mode, the following steps are mandatory: + + ##### TIM Driver: how to use it in Output Compare Mode ##### + =============================================================================== + [..] + To use the Timer in Output Compare mode, the following steps are mandatory: - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function + (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) + function - 2. Configure the TIM pins by configuring the corresponding GPIO pins + (#) Configure the TIM pins by configuring the corresponding GPIO pins - 2. Configure the Time base unit as described in the first part of this driver, - if needed, else the Timer will run with the default configuration: - - Autoreload value = 0xFFFF - - Prescaler value = 0x0000 - - Counter mode = Up counting - - Clock Division = TIM_CKD_DIV1 + (#) Configure the Time base unit as described in the first part of this driver, + (++) if needed, else the Timer will run with the default configuration: + Autoreload value = 0xFFFF + (++) Prescaler value = 0x0000 + (++) Counter mode = Up counting + (++) Clock Division = TIM_CKD_DIV1 - 3. Fill the TIM_OCInitStruct with the desired parameters including: - - The TIM Output Compare mode: TIM_OCMode - - TIM Output State: TIM_OutputState - - TIM Pulse value: TIM_Pulse - - TIM Output Compare Polarity : TIM_OCPolarity + (#) Fill the TIM_OCInitStruct with the desired parameters including: + (++) The TIM Output Compare mode: TIM_OCMode + (++) TIM Output State: TIM_OutputState + (++) TIM Pulse value: TIM_Pulse + (++) TIM Output Compare Polarity : TIM_OCPolarity - 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the - corresponding configuration + (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired + channel with the corresponding configuration - 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - Note1: All other functions can be used separately to modify, if needed, - a specific feature of the Timer. + -@- All other functions can be used separately to modify, if needed, + a specific feature of the Timer. - Note2: In case of PWM mode, this function is mandatory: - TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); + -@- In case of PWM mode, this function is mandatory: + TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); - Note3: If the corresponding interrupt or DMA request are needed, the user should: - 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). - 2. Enable the corresponding interrupt (or DMA request) using the function - TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) + -@- If the corresponding interrupt or DMA request are needed, the user should: + (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). + (+@) Enable the corresponding interrupt (or DMA request) using the function + TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) @endverbatim * @{ @@ -1831,49 +1839,51 @@ void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) * @verbatim =============================================================================== - Input Capture management functions + ##### Input Capture management functions ##### =============================================================================== - - =================================================================== - TIM Driver: how to use it in Input Capture Mode - =================================================================== - To use the Timer in Input Capture mode, the following steps are mandatory: + + ##### TIM Driver: how to use it in Input Capture Mode ##### + =============================================================================== + [..] + To use the Timer in Input Capture mode, the following steps are mandatory: - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function + (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) + function - 2. Configure the TIM pins by configuring the corresponding GPIO pins + (#) Configure the TIM pins by configuring the corresponding GPIO pins - 2. Configure the Time base unit as described in the first part of this driver, + (#) Configure the Time base unit as described in the first part of this driver, if needed, else the Timer will run with the default configuration: - - Autoreload value = 0xFFFF - - Prescaler value = 0x0000 - - Counter mode = Up counting - - Clock Division = TIM_CKD_DIV1 + (++) Autoreload value = 0xFFFF + (++) Prescaler value = 0x0000 + (++) Counter mode = Up counting + (++) Clock Division = TIM_CKD_DIV1 - 3. Fill the TIM_ICInitStruct with the desired parameters including: - - TIM Channel: TIM_Channel - - TIM Input Capture polarity: TIM_ICPolarity - - TIM Input Capture selection: TIM_ICSelection - - TIM Input Capture Prescaler: TIM_ICPrescaler - - TIM Input CApture filter value: TIM_ICFilter + (#) Fill the TIM_ICInitStruct with the desired parameters including: + (++) TIM Channel: TIM_Channel + (++) TIM Input Capture polarity: TIM_ICPolarity + (++) TIM Input Capture selection: TIM_ICSelection + (++) TIM Input Capture Prescaler: TIM_ICPrescaler + (++) TIM Input CApture filter value: TIM_ICFilter - 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the - corresponding configuration and to measure only frequency or duty cycle of the input signal, - or, - Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the - corresponding configuration and to measure the frequency and the duty cycle of the input signal + (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel + with the corresponding configuration and to measure only frequency + or duty cycle of the input signal, or, Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) + to configure the desired channels with the corresponding configuration + and to measure the frequency and the duty cycle of the input signal - 5. Enable the NVIC or the DMA to read the measured frequency. + (#) Enable the NVIC or the DMA to read the measured frequency. - 6. Enable the corresponding interrupt (or DMA request) to read the Captured value, - using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) + (#) Enable the corresponding interrupt (or DMA request) to read the Captured + value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) + (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - 8. Use TIM_GetCapturex(TIMx); to read the captured value. + (#) Use TIM_GetCapturex(TIMx); to read the captured value. - Note1: All other functions can be used separately to modify, if needed, - a specific feature of the Timer. + -@- All other functions can be used separately to modify, if needed, + a specific feature of the Timer. @endverbatim * @{ @@ -2176,23 +2186,23 @@ void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) * @verbatim =============================================================================== - Advanced-control timers (TIM1 and TIM8) specific features + ##### Advanced-control timers (TIM1 and TIM8) specific features ##### =============================================================================== - - =================================================================== - TIM Driver: how to use the Break feature - =================================================================== - After configuring the Timer channel(s) in the appropriate Output Compare mode: + + ##### TIM Driver: how to use the Break feature ##### + =============================================================================== + [..] + After configuring the Timer channel(s) in the appropriate Output Compare mode: - 1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer + (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer Break Polarity, dead time, Lock level, the OSSI/OSSR State and the AOE(automatic output enable). - 2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer + (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer - 3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) + (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) - 4. Once the break even occurs, the Timer's output signals are put in reset + (#) Once the break even occurs, the Timer's output signals are put in reset state or in a known state (according to the configuration made in TIM_BDTRConfig() function). @@ -2327,7 +2337,7 @@ void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) * @verbatim =============================================================================== - Interrupts, DMA and flags management functions + ##### Interrupts, DMA and flags management functions ##### =============================================================================== @endverbatim @@ -2657,7 +2667,7 @@ void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) * @verbatim =============================================================================== - Clocks management functions + ##### Clocks management functions ##### =============================================================================== @endverbatim @@ -2832,29 +2842,32 @@ void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, * @verbatim =============================================================================== - Synchronization management functions + ##### Synchronization management functions ##### =============================================================================== - - =================================================================== - TIM Driver: how to use it in synchronization Mode - =================================================================== - Case of two/several Timers - ************************** - 1. Configure the Master Timers using the following functions: - - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); - - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); - 2. Configure the Slave Timers using the following functions: - - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + + ##### TIM Driver: how to use it in synchronization Mode ##### + =============================================================================== + [..] + + *** Case of two/several Timers *** + ================================== + [..] + (#) Configure the Master Timers using the following functions: + (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); + (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); + (#) Configure the Slave Timers using the following functions: + (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); + (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - Case of Timers and external trigger(ETR pin) - ******************************************** - 1. Configure the External trigger using this function: - - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + *** Case of Timers and external trigger(ETR pin) *** + ==================================================== + [..] + (#) Configure the External trigger using this function: + (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); - 2. Configure the Slave Timers using the following functions: - - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + (#) Configure the Slave Timers using the following functions: + (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); + (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); @endverbatim * @{ @@ -3027,7 +3040,7 @@ void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, * @verbatim =============================================================================== - Specific interface management functions + ##### Specific interface management functions ##### =============================================================================== @endverbatim @@ -3132,7 +3145,7 @@ void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) * @verbatim =============================================================================== - Specific remapping management function + ##### Specific remapping management function ##### =============================================================================== @endverbatim @@ -3349,4 +3362,4 @@ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c index 1bb99ad22e..3376c90c12 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c @@ -2,82 +2,89 @@ ****************************************************************************** * @file stm32f4xx_usart.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Universal synchronous asynchronous receiver * transmitter (USART): - * - Initialization and Configuration - * - Data transfers - * - Multi-Processor Communication - * - LIN mode - * - Half-duplex mode - * - Smartcard mode - * - IrDA mode - * - DMA transfers management - * - Interrupts and flags management + * + Initialization and Configuration + * + Data transfers + * + Multi-Processor Communication + * + LIN mode + * + Half-duplex mode + * + Smartcard mode + * + IrDA mode + * + DMA transfers management + * + Interrupts and flags management * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable peripheral clock using the follwoing functions - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5. - * - * 2. According to the USART mode, enable the GPIO clocks using - * RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, - * or/and SCLK). - * - * 3. Peripheral's alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - * flow control and Mode(Receiver/Transmitter) using the USART_Init() - * function. - * - * 5. For synchronous mode, enable the clock and program the polarity, - * phase and last bit using the USART_ClockInit() function. + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable peripheral clock using the following functions + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, + UART4 or UART5. + + (#) According to the USART mode, enable the GPIO clocks using + RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, + or/and SCLK). + + (#) Peripheral's alternate function: + (++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (++) Call GPIO_Init() function + + (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) using the USART_Init() + function. + + (#) For synchronous mode, enable the clock and program the polarity, + phase and last bit using the USART_ClockInit() function. + + (#) Enable the NVIC and the corresponding interrupt using the function + USART_ITConfig() if you need to use interrupt mode. + + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function + (++) Active the needed channel Request using USART_DMACmd() function + + (#) Enable the USART using the USART_Cmd() function. + + (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. + + -@- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections + for more details + + [..] + In order to reach higher communication baudrates, it is possible to + enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). + This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) + and before calling the function USART_Init(). + + @endverbatim + ****************************************************************************** + * @attention * - * 5. Enable the NVIC and the corresponding interrupt using the function - * USART_ITConfig() if you need to use interrupt mode. + *

    © COPYRIGHT 2013 STMicroelectronics

    * - * 6. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using USART_DMACmd() function - * - * 7. Enable the USART using the USART_Cmd() function. - * - * 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: * - * Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections - * for more details - * - * In order to reach higher communication baudrates, it is possible to - * enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). - * This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) - * and before calling the function USART_Init(). - * - * @endverbatim - * - ****************************************************************************** - * @attention + * http://www.st.com/software_license_agreement_liberty_v2 * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -126,19 +133,19 @@ * @verbatim =============================================================================== - Initialization and Configuration functions + ##### Initialization and Configuration functions ##### =============================================================================== - - This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - - For the asynchronous mode only these parameters can be configured: - - Baud Rate - - Word Length - - Stop Bit - - Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: + [..] + This subsection provides a set of functions allowing to initialize the USART + in asynchronous and in synchronous modes. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible USART frame formats are as listed in the following table: +-------------------------------------------------------------+ | M bit | PCE bit | USART frame | |---------------------|---------------------------------------| @@ -150,20 +157,22 @@ |---------|-----------|---------------------------------------| | 1 | 1 | | SB | 8 bit data | PB | STB | | +-------------------------------------------------------------+ - - Hardware flow control - - Receiver/transmitter modes - - The USART_Init() function follows the USART asynchronous configuration procedure - (details for the procedure are available in reference manual (RM0090)). - - - For the synchronous mode in addition to the asynchronous mode parameters these - parameters should be also configured: - - USART Clock Enabled - - USART polarity - - USART phase - - USART LastBit + (++) Hardware flow control + (++) Receiver/transmitter modes + + [..] + The USART_Init() function follows the USART asynchronous configuration + procedure (details for the procedure are available in reference manual (RM0090)). + + (+) For the synchronous mode in addition to the asynchronous mode parameters these + parameters should be also configured: + (++) USART Clock Enabled + (++) USART polarity + (++) USART phase + (++) USART LastBit - These parameters can be configured using the USART_ClockInit() function. + [..] + These parameters can be configured using the USART_ClockInit() function. @endverbatim * @{ @@ -171,7 +180,7 @@ /** * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None */ @@ -204,13 +213,23 @@ void USART_DeInit(USART_TypeDef* USARTx) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + else if (USARTx == USART6) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); + } + else if (USARTx == UART7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); } else { - if (USARTx == USART6) + if (USARTx == UART8) { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE); } } } @@ -218,7 +237,7 @@ void USART_DeInit(USART_TypeDef* USARTx) /** * @brief Initializes the USARTx peripheral according to the specified * parameters in the USART_InitStruct . - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains * the configuration information for the specified USART peripheral. @@ -399,7 +418,7 @@ void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) /** * @brief Enables or disables the specified USART peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the USARTx peripheral. * This parameter can be: ENABLE or DISABLE. @@ -425,7 +444,7 @@ void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) /** * @brief Sets the system clock prescaler. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_Prescaler: specifies the prescaler clock. * @note The function is used for IrDA mode with UART4 and UART5. @@ -446,7 +465,7 @@ void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) * @brief Enables or disables the USART's 8x oversampling mode. * @note This function has to be called before calling USART_Init() function * in order to have correct baudrate Divider value. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the USART 8x oversampling mode. * This parameter can be: ENABLE or DISABLE. @@ -472,7 +491,7 @@ void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) /** * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the USART one bit sampling method. * This parameter can be: ENABLE or DISABLE. @@ -505,24 +524,24 @@ void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) * @verbatim =============================================================================== - Data transfers functions + ##### Data transfers functions ##### =============================================================================== - - This subsection provides a set of functions allowing to manage the USART data - transfers. - - During an USART reception, data shifts in least significant bit first through - the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) - between the internal bus and the received shift register. - - When a transmission is taking place, a write instruction to the USART_DR register - stores the data in the TDR register and which is copied in the shift register - at the end of the current transmission. - - The read access of the USART_DR register can be done using the USART_ReceiveData() - function and returns the RDR buffered value. Whereas a write access to the USART_DR - can be done using USART_SendData() function and stores the written data into - TDR buffer. + [..] + This subsection provides a set of functions allowing to manage the USART data + transfers. + [..] + During an USART reception, data shifts in least significant bit first through + the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) + between the internal bus and the received shift register. + [..] + When a transmission is taking place, a write instruction to the USART_DR register + stores the data in the TDR register and which is copied in the shift register + at the end of the current transmission. + [..] + The read access of the USART_DR register can be done using the USART_ReceiveData() + function and returns the RDR buffered value. Whereas a write access to the USART_DR + can be done using USART_SendData() function and stores the written data into + TDR buffer. @endverbatim * @{ @@ -530,7 +549,7 @@ void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) /** * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param Data: the data to transmit. * @retval None @@ -547,7 +566,7 @@ void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) /** * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval The received data. */ @@ -569,27 +588,28 @@ uint16_t USART_ReceiveData(USART_TypeDef* USARTx) * @verbatim =============================================================================== - Multi-Processor Communication functions + ##### Multi-Processor Communication functions ##### =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - multiprocessor communication. - - For instance one of the USARTs can be the master, its TX output is connected to - the RX input of the other USART. The others are slaves, their respective TX outputs - are logically ANDed together and connected to the RX input of the master. - - USART multiprocessor communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - 2. Configures the USART address using the USART_SetAddress() function. - 3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) - using USART_WakeUpConfig() function only for the slaves. - 4. Enable the USART using the USART_Cmd() function. - 5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. - - The USART Slave exit from mute mode when receive the wake up condition. + [..] + This subsection provides a set of functions allowing to manage the USART + multiprocessor communication. + [..] + For instance one of the USARTs can be the master, its TX output is connected + to the RX input of the other USART. The others are slaves, their respective + TX outputs are logically ANDed together and connected to the RX input of the + master. + [..] + USART multiprocessor communication is possible through the following procedure: + (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode + transmitter or Mode receiver and hardware flow control values using + the USART_Init() function. + (#) Configures the USART address using the USART_SetAddress() function. + (#) Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) + using USART_WakeUpConfig() function only for the slaves. + (#) Enable the USART using the USART_Cmd() function. + (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. + [..] + The USART Slave exit from mute mode when receive the wake up condition. @endverbatim * @{ @@ -597,7 +617,7 @@ uint16_t USART_ReceiveData(USART_TypeDef* USARTx) /** * @brief Sets the address of the USART node. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_Address: Indicates the address of the USART node. * @retval None @@ -616,7 +636,7 @@ void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) /** * @brief Determines if the USART is in mute mode or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the USART mute mode. * This parameter can be: ENABLE or DISABLE. @@ -641,7 +661,7 @@ void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) } /** * @brief Selects the USART WakeUp method. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_WakeUp: specifies the USART wakeup method. * This parameter can be one of the following values: @@ -668,41 +688,41 @@ void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) * @verbatim =============================================================================== - LIN mode functions + ##### LIN mode functions ##### =============================================================================== - - This subsection provides a set of functions allowing to manage the USART LIN - Mode communication. - - In LIN mode, 8-bit data format with 1 stop bit is required in accordance with - the LIN standard. - - Only this LIN Feature is supported by the USART IP: - - LIN Master Synchronous Break send capability and LIN slave break detection - capability : 13-bit break generation and 10/11 bit break detection - - - USART LIN Master transmitter communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Enable the LIN mode using the USART_LINCmd() function. - 4. Send the break character using USART_SendBreak() function. - - USART LIN Master receiver communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + [..] + This subsection provides a set of functions allowing to manage the USART LIN + Mode communication. + [..] + In LIN mode, 8-bit data format with 1 stop bit is required in accordance with + the LIN standard. + [..] + Only this LIN Feature is supported by the USART IP: + (+) LIN Master Synchronous Break send capability and LIN slave break detection + capability : 13-bit break generation and 10/11 bit break detection + + [..] + USART LIN Master transmitter communication is possible through the following + procedure: + (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, Mode transmitter or Mode receiver and hardware flow control values using the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Configures the break detection length using the USART_LINBreakDetectLengthConfig() - function. - 4. Enable the LIN mode using the USART_LINCmd() function. - - -@note In LIN mode, the following bits must be kept cleared: - - CLKEN in the USART_CR2 register, - - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. + (#) Enable the USART using the USART_Cmd() function. + (#) Enable the LIN mode using the USART_LINCmd() function. + (#) Send the break character using USART_SendBreak() function. + [..] + USART LIN Master receiver communication is possible through the following procedure: + (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + Mode transmitter or Mode receiver and hardware flow control values using + the USART_Init() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Configures the break detection length using the USART_LINBreakDetectLengthConfig() + function. + (#) Enable the LIN mode using the USART_LINCmd() function. + + -@- In LIN mode, the following bits must be kept cleared: + (+@) CLKEN in the USART_CR2 register, + (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. @endverbatim * @{ @@ -710,7 +730,7 @@ void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) /** * @brief Sets the USART LIN Break detection length. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_LINBreakDetectLength: specifies the LIN break detection length. * This parameter can be one of the following values: @@ -730,7 +750,7 @@ void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINB /** * @brief Enables or disables the USART's LIN mode. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the USART LIN mode. * This parameter can be: ENABLE or DISABLE. @@ -756,7 +776,7 @@ void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) /** * @brief Transmits break characters. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None */ @@ -778,28 +798,28 @@ void USART_SendBreak(USART_TypeDef* USARTx) * @verbatim =============================================================================== - Half-duplex mode function + ##### Half-duplex mode function ##### =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - Half-duplex communication. - - The USART can be configured to follow a single-wire half-duplex protocol where - the TX and RX lines are internally connected. - - USART Half duplex communication is possible through the following procedure: - 1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - 2. Configures the USART address using the USART_SetAddress() function. - 3. Enable the USART using the USART_Cmd() function. - 4. Enable the half duplex mode using USART_HalfDuplexCmd() function. - - -@note The RX pin is no longer used -@note In Half-duplex mode the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register. - - SCEN and IREN bits in the USART_CR3 register. + [..] + This subsection provides a set of functions allowing to manage the USART + Half-duplex communication. + [..] + The USART can be configured to follow a single-wire half-duplex protocol where + the TX and RX lines are internally connected. + [..] + USART Half duplex communication is possible through the following procedure: + (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter + or Mode receiver and hardware flow control values using the USART_Init() + function. + (#) Configures the USART address using the USART_SetAddress() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Enable the half duplex mode using USART_HalfDuplexCmd() function. + + + -@- The RX pin is no longer used + -@- In Half-duplex mode the following bits must be kept cleared: + (+@) LINEN and CLKEN bits in the USART_CR2 register. + (+@) SCEN and IREN bits in the USART_CR3 register. @endverbatim * @{ @@ -807,7 +827,7 @@ void USART_SendBreak(USART_TypeDef* USARTx) /** * @brief Enables or disables the USART's Half Duplex communication. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the USART Communication. * This parameter can be: ENABLE or DISABLE. @@ -841,51 +861,50 @@ void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) * @verbatim =============================================================================== - Smartcard mode functions + ##### Smartcard mode functions ##### =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - Smartcard communication. - - The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. - - The USART can provide a clock to the smartcard through the SCLK output. - In smartcard mode, SCLK is not associated to the communication but is simply derived - from the internal peripheral input clock through a 5-bit prescaler. - - Smartcard communication is possible through the following procedure: - 1. Configures the Smartcard Prescaler using the USART_SetPrescaler() function. - 2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function. - 3. Program the USART clock using the USART_ClockInit() function as following: - - USART Clock enabled - - USART CPOL Low - - USART CPHA on first edge - - USART Last Bit Clock Enabled - 4. Program the Smartcard interface using the USART_Init() function as following: - - Word Length = 9 Bits - - 1.5 Stop Bit - - Even parity - - BaudRate = 12096 baud - - Hardware flow control disabled (RTS and CTS signals) - - Tx and Rx enabled - 5. Optionally you can enable the parity error interrupt using the USART_ITConfig() - function - 6. Enable the USART using the USART_Cmd() function. - 7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function. - 8. Enable the Smartcard interface using the USART_SmartCardCmd() function. - - Please refer to the ISO 7816-3 specification for more details. - - -@note It is also possible to choose 0.5 stop bit for receiving but it is recommended - to use 1.5 stop bits for both transmitting and receiving to avoid switching - between the two configurations. -@note In smartcard mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register. - - HDSEL and IREN bits in the USART_CR3 register. -@note Smartcard mode is available on USART peripherals only (not available on UART4 - and UART5 peripherals). + [..] + This subsection provides a set of functions allowing to manage the USART + Smartcard communication. + [..] + The Smartcard interface is designed to support asynchronous protocol Smartcards as + defined in the ISO 7816-3 standard. + [..] + The USART can provide a clock to the smartcard through the SCLK output. + In smartcard mode, SCLK is not associated to the communication but is simply derived + from the internal peripheral input clock through a 5-bit prescaler. + [..] + Smartcard communication is possible through the following procedure: + (#) Configures the Smartcard Prescaler using the USART_SetPrescaler() function. + (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() function. + (#) Program the USART clock using the USART_ClockInit() function as following: + (++) USART Clock enabled + (++) USART CPOL Low + (++) USART CPHA on first edge + (++) USART Last Bit Clock Enabled + (#) Program the Smartcard interface using the USART_Init() function as following: + (++) Word Length = 9 Bits + (++) 1.5 Stop Bit + (++) Even parity + (++) BaudRate = 12096 baud + (++) Hardware flow control disabled (RTS and CTS signals) + (++) Tx and Rx enabled + (#) POptionally you can enable the parity error interrupt using the USART_ITConfig() + function + (#) PEnable the USART using the USART_Cmd() function. + (#) PEnable the Smartcard NACK using the USART_SmartCardNACKCmd() function. + (#) PEnable the Smartcard interface using the USART_SmartCardCmd() function. + + Please refer to the ISO 7816-3 specification for more details. + + -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended + to use 1.5 stop bits for both transmitting and receiving to avoid switching + between the two configurations. + -@- In smartcard mode, the following bits must be kept cleared: + (+@) LINEN bit in the USART_CR2 register. + (+@) HDSEL and IREN bits in the USART_CR3 register. + -@- Smartcard mode is available on USART peripherals only (not available on UART4 + and UART5 peripherals). @endverbatim * @{ @@ -968,36 +987,36 @@ void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) * @verbatim =============================================================================== - IrDA mode functions + ##### IrDA mode functions ##### =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - IrDA communication. - - IrDA is a half duplex communication protocol. If the Transmitter is busy, any data - on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver - is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. - While receiving data, transmission should be avoided as the data to be transmitted - could be corrupted. - - IrDA communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver - modes and hardware flow control values using the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Configures the IrDA pulse width by configuring the prescaler using - the USART_SetPrescaler() function. - 4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode - using the USART_IrDAConfig() function. - 5. Enable the IrDA using the USART_IrDACmd() function. - -@note A pulse of width less than two and greater than one PSC period(s) may or may - not be rejected. -@note The receiver set up time should be managed by software. The IrDA physical layer - specification specifies a minimum of 10 ms delay between transmission and - reception (IrDA is a half duplex protocol). -@note In IrDA mode, the following bits must be kept cleared: - - LINEN, STOP and CLKEN bits in the USART_CR2 register. - - SCEN and HDSEL bits in the USART_CR3 register. + [..] + This subsection provides a set of functions allowing to manage the USART + IrDA communication. + [..] + IrDA is a half duplex communication protocol. If the Transmitter is busy, any data + on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver + is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. + While receiving data, transmission should be avoided as the data to be transmitted + could be corrupted. + [..] + IrDA communication is possible through the following procedure: + (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver + modes and hardware flow control values using the USART_Init() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Configures the IrDA pulse width by configuring the prescaler using + the USART_SetPrescaler() function. + (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode + using the USART_IrDAConfig() function. + (#) Enable the IrDA using the USART_IrDACmd() function. + + -@- A pulse of width less than two and greater than one PSC period(s) may or may + not be rejected. + -@- The receiver set up time should be managed by software. The IrDA physical layer + specification specifies a minimum of 10 ms delay between transmission and + reception (IrDA is a half duplex protocol). + -@- In IrDA mode, the following bits must be kept cleared: + (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register. + (+@) SCEN and HDSEL bits in the USART_CR3 register. @endverbatim * @{ @@ -1005,7 +1024,7 @@ void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) /** * @brief Configures the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_IrDAMode: specifies the IrDA mode. * This parameter can be one of the following values: @@ -1025,7 +1044,7 @@ void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) /** * @brief Enables or disables the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the IrDA mode. * This parameter can be: ENABLE or DISABLE. @@ -1058,7 +1077,7 @@ void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) * @verbatim =============================================================================== - DMA transfers management functions + ##### DMA transfers management functions ##### =============================================================================== @endverbatim @@ -1067,7 +1086,7 @@ void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) /** * @brief Enables or disables the USART's DMA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_DMAReq: specifies the DMA request. * This parameter can be any combination of the following values: @@ -1107,81 +1126,85 @@ void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== - - This subsection provides a set of functions allowing to configure the USART - Interrupts sources, DMA channels requests and check or clear the flags or - pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. + [..] + This subsection provides a set of functions allowing to configure the USART + Interrupts sources, DMA channels requests and check or clear the flags or + pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. - Polling Mode - ============= - In Polling Mode, the SPI communication can be managed by 10 flags: - 1. USART_FLAG_TXE : to indicate the status of the transmit buffer register - 2. USART_FLAG_RXNE : to indicate the status of the receive buffer register - 3. USART_FLAG_TC : to indicate the status of the transmit operation - 4. USART_FLAG_IDLE : to indicate the status of the Idle Line - 5. USART_FLAG_CTS : to indicate the status of the nCTS input - 6. USART_FLAG_LBD : to indicate the status of the LIN break detection - 7. USART_FLAG_NE : to indicate if a noise error occur - 8. USART_FLAG_FE : to indicate if a frame error occur - 9. USART_FLAG_PE : to indicate if a parity error occur - 10. USART_FLAG_ORE : to indicate if an Overrun error occur - - In this Mode it is advised to use the following functions: - - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); - - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); - - Interrupt Mode - =============== - In Interrupt Mode, the USART communication can be managed by 8 interrupt sources - and 10 pending bits: - - Pending Bits: - ------------- - 1. USART_IT_TXE : to indicate the status of the transmit buffer register - 2. USART_IT_RXNE : to indicate the status of the receive buffer register - 3. USART_IT_TC : to indicate the status of the transmit operation - 4. USART_IT_IDLE : to indicate the status of the Idle Line - 5. USART_IT_CTS : to indicate the status of the nCTS input - 6. USART_IT_LBD : to indicate the status of the LIN break detection - 7. USART_IT_NE : to indicate if a noise error occur - 8. USART_IT_FE : to indicate if a frame error occur - 9. USART_IT_PE : to indicate if a parity error occur - 10. USART_IT_ORE : to indicate if an Overrun error occur - - Interrupt Source: - ----------------- - 1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty - interrupt. - 2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - 3. USART_IT_TC : specifies the interrupt source for the Transmit complete - interrupt. - 4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. - 5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. - 6. USART_IT_LBD : specifies the interrupt source for the LIN break detection - interrupt. - 7. USART_IT_PE : specifies the interrupt source for the parity error interrupt. - 8. USART_IT_ERR : specifies the interrupt source for the errors interrupt. - -@note Some parameters are coded in order to use them as interrupt source or as pending bits. - - In this Mode it is advised to use the following functions: - - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); - - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); - - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - - DMA Mode - ======== - In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: - 1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request - 2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - In this Mode it is advised to use the following function: - - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); + *** Polling Mode *** + ==================== + [..] + In Polling Mode, the SPI communication can be managed by 10 flags: + (#) USART_FLAG_TXE : to indicate the status of the transmit buffer register + (#) USART_FLAG_RXNE : to indicate the status of the receive buffer register + (#) USART_FLAG_TC : to indicate the status of the transmit operation + (#) USART_FLAG_IDLE : to indicate the status of the Idle Line + (#) USART_FLAG_CTS : to indicate the status of the nCTS input + (#) USART_FLAG_LBD : to indicate the status of the LIN break detection + (#) USART_FLAG_NE : to indicate if a noise error occur + (#) USART_FLAG_FE : to indicate if a frame error occur + (#) USART_FLAG_PE : to indicate if a parity error occur + (#) USART_FLAG_ORE : to indicate if an Overrun error occur + [..] + In this Mode it is advised to use the following functions: + (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); + (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); + + *** Interrupt Mode *** + ====================== + [..] + In Interrupt Mode, the USART communication can be managed by 8 interrupt sources + and 10 pending bits: + + (#) Pending Bits: + + (##) USART_IT_TXE : to indicate the status of the transmit buffer register + (##) USART_IT_RXNE : to indicate the status of the receive buffer register + (##) USART_IT_TC : to indicate the status of the transmit operation + (##) USART_IT_IDLE : to indicate the status of the Idle Line + (##) USART_IT_CTS : to indicate the status of the nCTS input + (##) USART_IT_LBD : to indicate the status of the LIN break detection + (##) USART_IT_NE : to indicate if a noise error occur + (##) USART_IT_FE : to indicate if a frame error occur + (##) USART_IT_PE : to indicate if a parity error occur + (##) USART_IT_ORE : to indicate if an Overrun error occur + + (#) Interrupt Source: + + (##) USART_IT_TXE : specifies the interrupt source for the Tx buffer empty + interrupt. + (##) USART_IT_RXNE : specifies the interrupt source for the Rx buffer not + empty interrupt. + (##) USART_IT_TC : specifies the interrupt source for the Transmit complete + interrupt. + (##) USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. + (##) USART_IT_CTS : specifies the interrupt source for the CTS interrupt. + (##) USART_IT_LBD : specifies the interrupt source for the LIN break detection + interrupt. + (##) USART_IT_PE : specifies the interrupt source for the parity error interrupt. + (##) USART_IT_ERR : specifies the interrupt source for the errors interrupt. + + -@@- Some parameters are coded in order to use them as interrupt source + or as pending bits. + [..] + In this Mode it is advised to use the following functions: + (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); + (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); + (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + + *** DMA Mode *** + ================ + [..] + In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: + (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request + (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request + [..] + In this Mode it is advised to use the following function: + (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); @endverbatim * @{ @@ -1189,7 +1212,7 @@ void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState /** * @brief Enables or disables the specified USART interrupts. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. * This parameter can be one of the following values: @@ -1253,7 +1276,7 @@ void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState Ne /** * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_FLAG: specifies the flag to check. * This parameter can be one of the following values: @@ -1295,7 +1318,7 @@ FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) /** * @brief Clears the USARTx's pending flags. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: @@ -1335,7 +1358,7 @@ void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) /** * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_IT: specifies the USART interrupt source to check. * This parameter can be one of the following values: @@ -1402,7 +1425,7 @@ ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) /** * @brief Clears the USARTx's interrupt pending bits. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_IT: specifies the interrupt pending bit to clear. * This parameter can be one of the following values: @@ -1460,4 +1483,4 @@ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c index 816a92d814..d2ac0f56f1 100644 --- a/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c +++ b/bsp/stm32f429-disco/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c @@ -2,77 +2,81 @@ ****************************************************************************** * @file stm32f4xx_wwdg.c * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.3.0 + * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Window watchdog (WWDG) peripheral: - * - Prescaler, Refresh window and Counter configuration - * - WWDG activation - * - Interrupts and flags management + * + Prescaler, Refresh window and Counter configuration + * + WWDG activation + * + Interrupts and flags management * - * @verbatim - * - * =================================================================== - * WWDG features - * =================================================================== - * - * Once enabled the WWDG generates a system reset on expiry of a programmed - * time period, unless the program refreshes the counter (downcounter) - * before to reach 0x3F value (i.e. a reset is generated when the counter - * value rolls over from 0x40 to 0x3F). - * An MCU reset is also generated if the counter value is refreshed - * before the counter has reached the refresh window value. This - * implies that the counter must be refreshed in a limited window. - * - * Once enabled the WWDG cannot be disabled except by a system reset. - * - * WWDGRST flag in RCC_CSR register can be used to inform when a WWDG - * reset occurs. - * - * The WWDG counter input clock is derived from the APB clock divided - * by a programmable prescaler. - * - * WWDG counter clock = PCLK1 / Prescaler - * WWDG timeout = (WWDG counter clock) * (counter value) - * - * Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function - * - * 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function - * - * 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function - * - * 4. Set the WWDG counter value and start it using WWDG_Enable() function. - * When the WWDG is enabled the counter value should be configured to - * a value greater than 0x40 to prevent generating an immediate reset. - * - * 5. Optionally you can enable the Early wakeup interrupt which is - * generated when the counter reach 0x40. - * Once enabled this interrupt cannot be disabled except by a system reset. - * - * 6. Then the application program must refresh the WWDG counter at regular - * intervals during normal operation to prevent an MCU reset, using - * WWDG_SetCounter() function. This operation must occur only when - * the counter value is lower than the refresh window value, - * programmed using WWDG_SetWindowValue(). - * - * @endverbatim - * + @verbatim + =============================================================================== + ##### WWDG features ##### + =============================================================================== + [..] + Once enabled the WWDG generates a system reset on expiry of a programmed + time period, unless the program refreshes the counter (downcounter) + before to reach 0x3F value (i.e. a reset is generated when the counter + value rolls over from 0x40 to 0x3F). + An MCU reset is also generated if the counter value is refreshed + before the counter has reached the refresh window value. This + implies that the counter must be refreshed in a limited window. + + Once enabled the WWDG cannot be disabled except by a system reset. + + WWDGRST flag in RCC_CSR register can be used to inform when a WWDG + reset occurs. + + The WWDG counter input clock is derived from the APB clock divided + by a programmable prescaler. + + WWDG counter clock = PCLK1 / Prescaler + WWDG timeout = (WWDG counter clock) * (counter value) + + Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms + + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function + + (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function + + (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function + + (#) Set the WWDG counter value and start it using WWDG_Enable() function. + When the WWDG is enabled the counter value should be configured to + a value greater than 0x40 to prevent generating an immediate reset. + + (#) Optionally you can enable the Early wakeup interrupt which is + generated when the counter reach 0x40. + Once enabled this interrupt cannot be disabled except by a system reset. + + (#) Then the application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + WWDG_SetCounter() function. This operation must occur only when + the counter value is lower than the refresh window value, + programmed using WWDG_SetWindowValue(). + + @endverbatim ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

    © COPYRIGHT 2013 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

    © COPYRIGHT 2011 STMicroelectronics

    ****************************************************************************** */ @@ -119,7 +123,7 @@ * @verbatim =============================================================================== - Prescaler, Refresh window and Counter configuration functions + ##### Prescaler, Refresh window and Counter configuration functions ##### =============================================================================== @endverbatim @@ -218,7 +222,7 @@ void WWDG_SetCounter(uint8_t Counter) * @verbatim =============================================================================== - WWDG activation function + ##### WWDG activation function ##### =============================================================================== @endverbatim @@ -247,7 +251,7 @@ void WWDG_Enable(uint8_t Counter) * @verbatim =============================================================================== - Interrupts and flags management functions + ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim @@ -300,4 +304,4 @@ void WWDG_ClearFlag(void) * @} */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f429-disco/applications/sram.c b/bsp/stm32f429-disco/applications/sram.c new file mode 100644 index 0000000000..a00295aa35 --- /dev/null +++ b/bsp/stm32f429-disco/applications/sram.c @@ -0,0 +1,60 @@ +/* +* File : sram.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2015, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: +* Date Author Notes +* 2015-08-03 xiaonong The first version for STM32F7 +*/ + +#include "sram.h" +#include "board.h" + +#include + +#ifdef RT_USING_EXT_SDRAM +struct rt_memheap system_heap; + +void sram_init(void) +{ + /* initialize the built-in SRAM as a memory heap */ + rt_memheap_init(&system_heap, + "system", + (void *)HEAP_BEGIN, + (rt_uint32_t)HEAP_END - (rt_uint32_t)HEAP_BEGIN); +} + +void *sram_malloc(unsigned long size) +{ + return rt_memheap_alloc(&system_heap, size); +} +RTM_EXPORT(sram_malloc); + +void sram_free(void *ptr) +{ + rt_memheap_free(ptr); +} +RTM_EXPORT(sram_free); + +void *sram_realloc(void *ptr, unsigned long size) +{ + return rt_memheap_realloc(&system_heap, ptr, size); +} +RTM_EXPORT(sram_realloc); + +#endif diff --git a/bsp/stm32f429-disco/applications/sram.h b/bsp/stm32f429-disco/applications/sram.h new file mode 100644 index 0000000000..6a6f4f0cff --- /dev/null +++ b/bsp/stm32f429-disco/applications/sram.h @@ -0,0 +1,23 @@ +/* + * File : sram.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2015 RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2015-08-03 xiaonong The first version for STM32F7 + */ + +#ifndef __SRAM_H__ +#define __SRAM_H__ + +void sram_init(void); +void *sram_malloc(unsigned long nbytes); +void sram_free(void *ptr); +void *sram_realloc(void *ptr, unsigned long nbytes); + +#endif diff --git a/bsp/stm32f429-disco/drivers/SConscript b/bsp/stm32f429-disco/drivers/SConscript index 8037c3ea5b..5d963ae4e3 100644 --- a/bsp/stm32f429-disco/drivers/SConscript +++ b/bsp/stm32f429-disco/drivers/SConscript @@ -9,6 +9,7 @@ src = Split(""" board.c stm32f4xx_it.c usart.c +drv_sdram.c """) # add Ethernet drivers. @@ -24,4 +25,3 @@ CPPPATH = [cwd] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') - diff --git a/bsp/stm32f429-disco/drivers/board.c b/bsp/stm32f429-disco/drivers/board.c index ba46e903ea..30e71eb3da 100644 --- a/bsp/stm32f429-disco/drivers/board.c +++ b/bsp/stm32f429-disco/drivers/board.c @@ -19,6 +19,7 @@ #include "board.h" #include "usart.h" #include "gpio.h" +#include "sram.h" /** * @addtogroup STM32 @@ -93,9 +94,20 @@ void rt_hw_board_init() /* Configure the SysTick */ SysTick_Configuration(); +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#else stm32_hw_usart_init(); stm32_hw_pin_init(); - +#endif + +#ifdef RT_USING_EXT_SDRAM + rt_system_heap_init((void*)EXT_SDRAM_BEGIN, (void*)EXT_SDRAM_END); + sram_init(); +#else + rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); +#endif + #ifdef RT_USING_CONSOLE rt_console_set_device(CONSOLE_DEVICE); #endif diff --git a/bsp/stm32f429-disco/drivers/board.h b/bsp/stm32f429-disco/drivers/board.h index 7f362503b0..e613db07cc 100644 --- a/bsp/stm32f429-disco/drivers/board.h +++ b/bsp/stm32f429-disco/drivers/board.h @@ -17,22 +17,21 @@ #define __BOARD_H__ #include +#include /* board configuration */ // SDCard Driver <1=>SDIO sdcard <0=>SPI MMC card // Default: 1 #define STM32_USE_SDIO 0 -/* whether use board external SRAM memory */ -// Use external SRAM memory on the board -// Enable External SRAM memory -#define STM32_EXT_SRAM 0 -// Begin Address of External SRAM -// Default: 0x68000000 -#define STM32_EXT_SRAM_BEGIN 0x68000000 /* the begining address of external SRAM */ +#define IS42S16400J_SIZE 0x400000 + +// Begin Address of External SDRAM +// Default: 0xD0000000 +#define EXT_SDRAM_BEGIN SDRAM_BANK_ADDR /* the begining address of external SRAM */ // End Address of External SRAM -// Default: 0x68080000 -#define STM32_EXT_SRAM_END 0x68080000 /* the end address of external SRAM */ +// Default: 0xD0800000 +#define EXT_SDRAM_END SDRAM_BANK_ADDR + IS42S16400J_SIZE /* the end address of external SRAM */ // // Internal SRAM memory size[Kbytes] <8-64> @@ -42,10 +41,23 @@ extern char __ICFEDIT_region_RAM_end__; #define STM32_SRAM_END &__ICFEDIT_region_RAM_end__ #else -#define STM32_SRAM_SIZE 128 +#define STM32_SRAM_SIZE 256 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) #endif +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END STM32_SRAM_END + // Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3 // Default: 1 #define STM32_CONSOLE_USART 2 diff --git a/bsp/stm32f429-disco/drivers/drv_sdram.c b/bsp/stm32f429-disco/drivers/drv_sdram.c new file mode 100644 index 0000000000..54093c9935 --- /dev/null +++ b/bsp/stm32f429-disco/drivers/drv_sdram.c @@ -0,0 +1,400 @@ +/* + * File : drv_sdram.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2016, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2016-08-20 xuzhuoyi The first version for STM32F42x + */ + +/* Includes ------------------------------------------------------------------*/ +#include "drv_sdram.h" +#include "stm32f4xx_fmc.h" +#include + + +#ifndef USE_Delay +static void delay(__IO uint32_t nCount); +#endif /* USE_Delay*/ + +/** + * @brief Configures the FMC and GPIOs to interface with the SDRAM memory. + * This function must be called before any read/write operation + * on the SDRAM. + * @param None + * @retval None + */ +void SDRAM_Init(void) +{ + FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; + FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure; + + /* GPIO configuration for FMC SDRAM bank */ + SDRAM_GPIOConfig(); + + /* Enable FMC clock */ + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); + +/* FMC Configuration ---------------------------------------------------------*/ +/* FMC SDRAM Bank configuration */ + /* Timing configuration for 90 Mhz of SD clock frequency (180Mhz/2) */ + /* TMRD: 2 Clock cycles */ + FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; + /* TXSR: min=70ns (7x11.11ns) */ + FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7; + /* TRAS: min=42ns (4x11.11ns) max=120k (ns) */ + FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; + /* TRC: min=70 (7x11.11ns) */ + FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7; + /* TWR: min=1+ 7ns (1+1x11.11ns) */ + FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; + /* TRP: 20ns => 2x11.11ns */ + FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; + /* TRCD: 20ns => 2x11.11ns */ + FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; + +/* FMC SDRAM control configuration */ + FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM; + /* Row addressing: [7:0] */ + FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; + /* Column addressing: [11:0] */ + FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b; + FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH; + FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; + FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY; + FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; + FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD; + FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST; + FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1; + FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; + + /* FMC SDRAM bank initialization */ + FMC_SDRAMInit(&FMC_SDRAMInitStructure); + + /* FMC SDRAM device initialization sequence */ + SDRAM_InitSequence(); + +} + +/** + * @brief Configures all SDRAM memory I/Os pins. + * @param None. + * @retval None. + */ +void SDRAM_GPIOConfig(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIOs clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | + RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOG, ENABLE); + +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+--------------------+--------------------+ + + SDRAM pins assignment + + +-------------------+--------------------+--------------------+--------------------+ + | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | + | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | + | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK | + | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS | + | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+ + | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | + | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | + +-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 | + | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 | + | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 | + | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 | + +-------------------+--------------------+--------------------+ + | PB5 <-> FMC_SDCKE1| + | PB6 <-> FMC_SDNE1 | + | PC0 <-> FMC_SDNWE | + +-------------------+ + +*/ + + /* Common GPIO configuration */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + + /* GPIOB configuration */ + GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource6 , GPIO_AF_FMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6; + + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* GPIOC configuration */ + GPIO_PinAFConfig(GPIOC, GPIO_PinSource0 , GPIO_AF_FMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* GPIOD configuration */ + GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | + GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | + GPIO_Pin_15; + + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* GPIOE configuration */ + GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 | + GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | + GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | + GPIO_Pin_14 | GPIO_Pin_15; + + GPIO_Init(GPIOE, &GPIO_InitStructure); + + /* GPIOF configuration */ + GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | + GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | + GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | + GPIO_Pin_14 | GPIO_Pin_15; + + GPIO_Init(GPIOF, &GPIO_InitStructure); + + /* GPIOG configuration */ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC); + + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | + GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15; + + GPIO_Init(GPIOG, &GPIO_InitStructure); +} + +/** + * @brief Executes the SDRAM memory initialization sequence. + * @param None. + * @retval None. + */ +void SDRAM_InitSequence(void) +{ + FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; + uint32_t tmpr = 0; + +/* Step 3 --------------------------------------------------------------------*/ + /* Configure a clock configuration enable command */ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + +/* Step 4 --------------------------------------------------------------------*/ + /* Insert 100 ms delay */ + __Delay(10); + +/* Step 5 --------------------------------------------------------------------*/ + /* Configure a PALL (precharge all) command */ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + +/* Step 6 --------------------------------------------------------------------*/ + /* Configure a Auto-Refresh command */ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the first command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the second command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + +/* Step 7 --------------------------------------------------------------------*/ + /* Program the external memory mode register */ + tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | + SDRAM_MODEREG_CAS_LATENCY_3 | + SDRAM_MODEREG_OPERATING_MODE_STANDARD | + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; + + /* Configure a load Mode register command*/ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + +/* Step 8 --------------------------------------------------------------------*/ + + /* Set the refresh rate counter */ + /* (15.62 us x Freq) - 20 */ + /* Set the device refresh counter */ + FMC_SetRefreshCount(1386); + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } +} + + +/** + * @brief Writes a Entire-word buffer to the SDRAM memory. + * @param pBuffer: pointer to buffer. + * @param uwWriteAddress: SDRAM memory internal address from which the data will be + * written. + * @param uwBufferSize: number of words to write. + * @retval None. + */ +void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize) +{ + __IO uint32_t write_pointer = (uint32_t)uwWriteAddress; + + /* Disable write protection */ + FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE); + + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + + /* While there is data to write */ + for (; uwBufferSize != 0; uwBufferSize--) + { + /* Transfer data to the memory */ + *(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++; + + /* Increment the address*/ + write_pointer += 4; + } + +} + +/** + * @brief Reads data buffer from the SDRAM memory. + * @param pBuffer: pointer to buffer. + * @param ReadAddress: SDRAM memory internal address from which the data will be + * read. + * @param uwBufferSize: number of words to write. + * @retval None. + */ +void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize) +{ + __IO uint32_t write_pointer = (uint32_t)uwReadAddress; + + + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + + /* Read data */ + for(; uwBufferSize != 0x00; uwBufferSize--) + { + *pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer ); + + /* Increment the address*/ + write_pointer += 4; + } +} + +#ifndef USE_Delay +/** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + */ +static void delay(__IO uint32_t nCount) +{ + __IO uint32_t index = 0; + for(index = (100000 * nCount); index != 0; index--) + { + } +} +#endif /* USE_Delay */ + +rt_err_t sdram_hw_init(void) +{ + SDRAM_Init(); + return RT_EOK; +} + +static int rt_sdram_hw_init(void) +{ + return (int)sdram_hw_init(); +} +INIT_BOARD_EXPORT(rt_sdram_hw_init); diff --git a/bsp/stm32f429-disco/drivers/drv_sdram.h b/bsp/stm32f429-disco/drivers/drv_sdram.h new file mode 100644 index 0000000000..87fcd097e8 --- /dev/null +++ b/bsp/stm32f429-disco/drivers/drv_sdram.h @@ -0,0 +1,108 @@ +/* + * File : drv_sdram.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2016 RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2016-08-20 xuzhuoyi The first version for STM32F42x + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DRV_SDRAM_H +#define __DRV_SDRAM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include + + +#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000) + +/** + * @brief FMC SDRAM Memory Width + */ +/* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */ +#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b + +/** + * @brief FMC SDRAM CAS Latency + */ +/* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */ +#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3 + +/** + * @brief FMC SDRAM Memory clock period + */ +#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */ +/* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */ + +/** + * @brief FMC SDRAM Memory Read Burst feature + */ +#define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */ +/* #define SDRAM_READBURST FMC_Read_Burst_Enable */ + +/** + * @brief FMC SDRAM Bank Remap + */ +/* #define SDRAM_BANK_REMAP */ + + + +/** + * @brief Uncomment the line below if you want to use user defined Delay function + * (for precise timing), otherwise default _delay_ function defined within + * this driver is used (less precise timing). + */ + +/* #define USE_Delay */ + +#ifdef USE_Delay + #define __Delay Delay /* User can provide more timing precise __Delay function + (with 10ms time base), using SysTick for example */ +#else + #define __Delay delay /* Default __Delay function with less precise timing */ +#endif + +/** + * @brief FMC SDRAM Mode definition register defines + */ +#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +/** + * @} + */ + +/** @defgroup STM32429I_DISCO_SDRAM_Exported_Functions + * @{ + */ +void SDRAM_Init(void); +void SDRAM_GPIOConfig(void); +void SDRAM_InitSequence(void); +void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize); +void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32f429-disco/drivers/gpio.h b/bsp/stm32f429-disco/drivers/gpio.h index a4947b100d..864cad73f8 100644 --- a/bsp/stm32f429-disco/drivers/gpio.h +++ b/bsp/stm32f429-disco/drivers/gpio.h @@ -14,6 +14,12 @@ #ifndef GPIO_H__ #define GPIO_H__ +struct stm32_gpio_dsc { + GPIO_TypeDef * port; + uint32_t pin; + uint8_t pin_source; +}; + int stm32_hw_pin_init(void); #endif diff --git a/bsp/stm32f429-disco/drivers/stm32f4xx_conf.h b/bsp/stm32f429-disco/drivers/stm32f4xx_conf.h index 065e72e94f..46983936d2 100644 --- a/bsp/stm32f429-disco/drivers/stm32f4xx_conf.h +++ b/bsp/stm32f429-disco/drivers/stm32f4xx_conf.h @@ -41,7 +41,7 @@ #include "stm32f4xx_dma.h" #include "stm32f4xx_exti.h" #include "stm32f4xx_flash.h" -#include "stm32f4xx_fsmc.h" +#include "stm32f4xx_fmc.h" #include "stm32f4xx_hash.h" #include "stm32f4xx_gpio.h" #include "stm32f4xx_i2c.h" -- GitLab